bsp/stm32：Separate STM32WL HAL drivers (#10218)

bsp/stm32/libraries/Kconfig

@@ -98,6 +98,7 @@ config SOC_SERIES_STM32WL
     bool
     select ARCH_ARM_CORTEX_M4
     select SOC_FAMILY_STM32
+    select PKG_USING_STM32WL_HAL_DRIVER
 
 config SOC_SERIES_STM32WB
     bool

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Include/stm32wl54xx.h

@@ -1,11461 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wl54xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex Device Peripheral Access Layer Header File.
-  *          This file contains all the peripheral register's definitions, bits
-  *          definitions and memory mapping for stm32wl54xx devices.
-  *
-  *          This file contains:selected
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2020(-2021) STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32wl54xx
-  * @{
-  */
-
-#ifndef __STM32WL54xx_H
-#define __STM32WL54xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-#define DUAL_CORE
-
-
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief stm32wl54xx Interrupt Number Definition, according to the selected device
- *        in @ref Library_configuration_section
- */
-#if defined(CORE_CM0PLUS)
-  /*!< Interrupt Number Definition for M0 */
-  typedef enum
-  {
-  /******  Cortex-M0 Processor Exceptions Numbers ****************************************************************/
-    NonMaskableInt_IRQn          = -14,    /*!< Non Maskable Interrupt                                            */
-    HardFault_IRQn               = -13,    /*!< Cortex-M0+ Hard Fault Interrupt                                   */
-    SVC_IRQn                     = -5,     /*!< Cortex-M0+ SV Call Interrupt                                      */
-    PendSV_IRQn                  = -2,     /*!< Cortex-M0+ Pend SV Interrupt                                      */
-    SysTick_IRQn                 = -1,     /*!< Cortex-M0+ System Tick Interrupt                                  */
-
-  /*************  STM32WLxx specific Interrupt Numbers on M0 core ************************************************/
-    TZIC_ILA_IRQn                = 0,      /*!< Security Interrupt controller illegal access interrupt            */
-    PVD_PVM_IRQn                 = 1,      /*!< PVD and PVM detector                                              */
-    RTC_LSECSS_IRQn              = 2,      /*!< RTC Wakeup + RTC Tamper and RTC TimeStamp + RTC Alarms (A & B) and*/
-                                           /*!< RTC SSRU Interrupts and LSECSS Interrupts                         */
-    RCC_FLASH_C1SEV_IRQn         = 3,      /*!< RCC Interrupt, FLASH interrupt and CPU1 SEV                       */
-    EXTI1_0_IRQn                 = 4,      /*!< EXTI Line 1:0 Interrupt                                           */
-    EXTI3_2_IRQn                 = 5,      /*!< EXTI Line 3:2 Interrupt                                           */
-    EXTI15_4_IRQn                = 6,      /*!< EXTI Line 15:4 interrupt                                          */
-    ADC_COMP_DAC_IRQn            = 7,      /*!< ADC, COMP1, COMP2, DAC interrupts                                 */
-    DMA1_Channel1_2_3_IRQn       = 8,      /*!< DMA1 Channels 1,2,3 Interrupt                                     */
-    DMA1_Channel4_5_6_7_IRQn     = 9,      /*!< DMA1 Channels 4,5,6,7 Interrupt                                   */
-    DMA2_DMAMUX1_OVR_IRQn        = 10,     /*!< DMA2 Channels[1..7] and DMAMUX1 Overrun Interrupt                 */
-    LPTIM1_IRQn                  = 11,     /*!< LPTIM1 Global Interrupt                                           */
-    LPTIM2_IRQn                  = 12,     /*!< LPTIM2 Global Interrupt                                           */
-    LPTIM3_IRQn                  = 13,     /*!< LPTIM3 Global Interrupt                                           */
-    TIM1_IRQn                    = 14,     /*!< TIM1 Global Interrupt                                             */
-    TIM2_IRQn                    = 15,     /*!< TIM2 Global Interrupt                                             */
-    TIM16_IRQn                   = 16,     /*!< TIM16 Global Interrupt                                            */
-    TIM17_IRQn                   = 17,     /*!< TIM17 Global Interrupt                                            */
-    IPCC_C2_RX_C2_TX_IRQn        = 18,     /*!< IPCC RX Occupied and TX Free Interrupt                            */
-    HSEM_IRQn                    = 19,     /*!< HSEM Interrupt                                                    */
-    RNG_IRQn                     = 20,     /*!< RNG Interrupt                                                     */
-    AES_PKA_IRQn                 = 21,     /*!< AES and PKA Interrupt                                             */
-    I2C1_IRQn                    = 22,     /*!< I2C1 Event and Error Interrupt                                    */
-    I2C2_IRQn                    = 23,     /*!< I2C2 Event and Error Interrupt                                    */
-    I2C3_IRQn                    = 24,     /*!< I2C3 Event and Error Interrupt                                    */
-    SPI1_IRQn                    = 25,     /*!< SPI1 Interrupt                                                    */
-    SPI2_IRQn                    = 26,     /*!< SPI2 Interrupt                                                    */
-    USART1_IRQn                  = 27,     /*!< USART1 Interrupt                                                  */
-    USART2_IRQn                  = 28,     /*!< USART2 Interrupt                                                  */
-    LPUART1_IRQn                 = 29,     /*!< LPUART1 Interrupt                                                 */
-    SUBGHZSPI_IRQn               = 30,     /*!< SUBGHZSPI Interrupt                                               */
-    SUBGHZ_Radio_IRQn            = 31,     /*!< SUBGHZ Radio Interrupt                                            */
-  } IRQn_Type;
-#else /* CORE_CM4 */
-/*!< Interrupt Number Definition for M4 */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn                 = -14,    /*!< Non Maskable Interrupt                                            */
-  HardFault_IRQn                      = -13,    /*!< Cortex-M4 Hard Fault Interrupt                                    */
-  MemoryManagement_IRQn               = -12,    /*!< Cortex-M4 Memory Management Interrupt                             */
-  BusFault_IRQn                       = -11,    /*!< Cortex-M4 Bus Fault Interrupt                                     */
-  UsageFault_IRQn                     = -10,    /*!< Cortex-M4 Usage Fault Interrupt                                   */
-  SVCall_IRQn                         = -5,     /*!< Cortex-M4 SV Call Interrupt                                       */
-  DebugMonitor_IRQn                   = -4,     /*!< Cortex-M4 Debug Monitor Interrupt                                 */
-  PendSV_IRQn                         = -2,     /*!< Cortex-M4 Pend SV Interrupt                                       */
-  SysTick_IRQn                        = -1,     /*!< Cortex-M4 System Tick Interrupt                                   */
-
-/*************  STM32WLxx specific Interrupt Numbers on M4 core ************************************************/
-  WWDG_IRQn                           = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_PVM_IRQn                        = 1,      /*!< PVD and PVM detector                                              */
-  TAMP_STAMP_LSECSS_SSRU_IRQn         = 2,      /*!< RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts         */
-  RTC_WKUP_IRQn                       = 3,      /*!< RTC Wakeup Interrupt                                              */
-  FLASH_IRQn                          = 4,      /*!< FLASH (CFI)  global Interrupt                                     */
-  RCC_IRQn                            = 5,      /*!< RCC Interrupt                                                     */
-  EXTI0_IRQn                          = 6,      /*!< EXTI Line 0 Interrupt                                             */
-  EXTI1_IRQn                          = 7,      /*!< EXTI Line 1 Interrupt                                             */
-  EXTI2_IRQn                          = 8,      /*!< EXTI Line 2 Interrupt                                             */
-  EXTI3_IRQn                          = 9,      /*!< EXTI Line 3 Interrupt                                             */
-  EXTI4_IRQn                          = 10,     /*!< EXTI Line 4 Interrupt                                             */
-  DMA1_Channel1_IRQn                  = 11,     /*!< DMA1 Channel 1 Interrupt                                          */
-  DMA1_Channel2_IRQn                  = 12,     /*!< DMA1 Channel 2 Interrupt                                          */
-  DMA1_Channel3_IRQn                  = 13,     /*!< DMA1 Channel 3 Interrupt                                          */
-  DMA1_Channel4_IRQn                  = 14,     /*!< DMA1 Channel 4 Interrupt                                          */
-  DMA1_Channel5_IRQn                  = 15,     /*!< DMA1 Channel 5 Interrupt                                          */
-  DMA1_Channel6_IRQn                  = 16,     /*!< DMA1 Channel 6 Interrupt                                          */
-  DMA1_Channel7_IRQn                  = 17,     /*!< DMA1 Channel 7 Interrupt                                          */
-  ADC_IRQn                            = 18,     /*!< ADC Interrupt                                                     */
-  DAC_IRQn                            = 19,     /*!< DAC Interrupt                                                     */
-  C2SEV_PWR_C2H_IRQn                  = 20,     /*!< CPU2 SEV Interrupt                                                */
-  COMP_IRQn                           = 21,     /*!< COMP1 and COMP2 Interrupts                                        */
-  EXTI9_5_IRQn                        = 22,     /*!< EXTI Lines [9:5] Interrupt                                        */
-  TIM1_BRK_IRQn                       = 23,     /*!< TIM1 Break Interrupt                                              */
-  TIM1_UP_IRQn                        = 24,     /*!< TIM1 Update Interrupt                                             */
-  TIM1_TRG_COM_IRQn                   = 25,     /*!< TIM1 Trigger and Communication Interrupts                         */
-  TIM1_CC_IRQn                        = 26,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                           = 27,     /*!< TIM2 Global Interrupt                                             */
-  TIM16_IRQn                          = 28,     /*!< TIM16 Global Interrupt                                            */
-  TIM17_IRQn                          = 29,     /*!< TIM17 Global Interrupt                                            */
-  I2C1_EV_IRQn                        = 30,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                        = 31,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                        = 32,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                        = 33,     /*!< I2C2 Error Interrupt                                              */
-  SPI1_IRQn                           = 34,     /*!< SPI1 Interrupt                                                    */
-  SPI2_IRQn                           = 35,     /*!< SPI2 Interrupt                                                    */
-  USART1_IRQn                         = 36,     /*!< USART1 Interrupt                                                  */
-  USART2_IRQn                         = 37,     /*!< USART2 Interrupt                                                  */
-  LPUART1_IRQn                        = 38,     /*!< LPUART1 Interrupt                                                 */
-  LPTIM1_IRQn                         = 39,     /*!< LPTIM1 Global Interrupt                                           */
-  LPTIM2_IRQn                         = 40,     /*!< LPTIM2 Global Interrupt                                           */
-  EXTI15_10_IRQn                      = 41,     /*!< EXTI Lines [15:10] Interrupt                                      */
-  RTC_Alarm_IRQn                      = 42,     /*!< RTC Alarms (A and B) Interrupt                                    */
-  LPTIM3_IRQn                         = 43,     /*!< LPTIM3 Global Interrupt                                           */
-  SUBGHZSPI_IRQn                      = 44,     /*!< SUBGHZSPI Interrupt                                               */
-  IPCC_C1_RX_IRQn                     = 45,     /*!< IPCC RX Occupied Interrupt                                        */
-  IPCC_C1_TX_IRQn                     = 46,     /*!< IPCC TX Free Interrupt                                            */
-  HSEM_IRQn                           = 47,     /*!< HSEM Interrupt                                                    */
-  I2C3_EV_IRQn                        = 48,     /*!< I2C3 Event Interrupt                                              */
-  I2C3_ER_IRQn                        = 49,     /*!< I2C3 Error Interrupt                                              */
-  SUBGHZ_Radio_IRQn                   = 50,     /*!< SUBGHZ Radio Interrupt                                            */
-  AES_IRQn                            = 51,     /*!< AES Interrupt                                                     */
-  RNG_IRQn                            = 52,     /*!< RNG Interrupt                                                     */
-  PKA_IRQn                            = 53,     /*!< PKA Interrupt                                                     */
-  DMA2_Channel1_IRQn                  = 54,     /*!< DMA2 Channel 1 Interrupt                                          */
-  DMA2_Channel2_IRQn                  = 55,     /*!< DMA2 Channel 2 Interrupt                                          */
-  DMA2_Channel3_IRQn                  = 56,     /*!< DMA2 Channel 3 Interrupt                                          */
-  DMA2_Channel4_IRQn                  = 57,     /*!< DMA2 Channel 4 Interrupt                                          */
-  DMA2_Channel5_IRQn                  = 58,     /*!< DMA2 Channel 5 Interrupt                                          */
-  DMA2_Channel6_IRQn                  = 59,     /*!< DMA2 Channel 6 Interrupt                                          */
-  DMA2_Channel7_IRQn                  = 60,     /*!< DMA2 Channel 7 Interrupt                                          */
-  DMAMUX1_OVR_IRQn                    = 61      /*!< DMAMUX1 overrun Interrupt                                         */
-} IRQn_Type;
-/**
-  * @}
-  */
-#endif
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
-  */
-#define __CM0PLUS_REV             1U /*!< Core Revision r0p1                            */
-#define __MPU_PRESENT             1U /*!< M0 provides an MPU                            */
-#define __VTOR_PRESENT            1U /*!< Vector Table Register supported               */
-#define __NVIC_PRIO_BITS          2U /*!< M0 core uses 2 Bits for the Priority Levels   */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             0U /*!< FPU not present                               */
-
-#include "core_cm0plus.h"            /* Cortex-M0+ processor and core peripherals */
-
-#else /* CORE_CM4*/
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
-  */
-#define __CM4_REV                 1U /*!< Core Revision r0p1                            */
-#define __MPU_PRESENT             1U /*!< M4 provides an MPU                            */
-#define __VTOR_PRESENT            1U /*!< Vector Table Register supported               */
-#define __NVIC_PRIO_BITS          4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             0U /*!< FPU not present                                   */
-
-#include "core_cm4.h"                /* Cortex-M4 processor and core peripherals */
-
-#endif
-
-#include "system_stm32wlxx.h"
-#include <stdint.h>
-
-/**
-  * @}
-  */
-
-
-
-
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */
-
-/**
-  * @brief Analog to Digital Converter
-  */
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
-  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
-  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC configuration register 1,                  Address offset: 0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR;         /*!< ADC sampling time register,                    Address offset: 0x14 */
-       uint32_t RESERVED1;    /*!< Reserved,                                                      0x18 */
-       uint32_t RESERVED2;    /*!< Reserved,                                                      0x1C */
-  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
-  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC group regular sequencer register,          Address offset: 0x28 */
-  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x2C */
-       uint32_t RESERVED3[4]; /*!< Reserved,                                               0x30 - 0x3C */
-  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
-       uint32_t RESERVED4[23];/*!< Reserved,                                               0x44 - 0x9C */
-  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
-  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 configuration register,  Address offset: 0xA4 */
-       uint32_t RESERVED5[3]; /*!< Reserved,                                               0xA8 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC Calibration factor register,               Address offset: 0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/**
-  * @brief AES hardware accelerator
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;          /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;        /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;       /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;       /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;       /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;       /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;       /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;        /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;        /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;        /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;        /*!< AES initialization vector register 3,        Address offset: 0x2C */
-  __IO uint32_t KEYR4;       /*!< AES key register 4,                          Address offset: 0x30 */
-  __IO uint32_t KEYR5;       /*!< AES key register 5,                          Address offset: 0x34 */
-  __IO uint32_t KEYR6;       /*!< AES key register 6,                          Address offset: 0x38 */
-  __IO uint32_t KEYR7;       /*!< AES key register 7,                          Address offset: 0x3C */
-  __IO uint32_t SUSP0R;      /*!< AES Suspend register 0,                      Address offset: 0x40 */
-  __IO uint32_t SUSP1R;      /*!< AES Suspend register 1,                      Address offset: 0x44 */
-  __IO uint32_t SUSP2R;      /*!< AES Suspend register 2,                      Address offset: 0x48 */
-  __IO uint32_t SUSP3R;      /*!< AES Suspend register 3,                      Address offset: 0x4C */
-  __IO uint32_t SUSP4R;      /*!< AES Suspend register 4,                      Address offset: 0x50 */
-  __IO uint32_t SUSP5R;      /*!< AES Suspend register 5,                      Address offset: 0x54 */
-  __IO uint32_t SUSP6R;      /*!< AES Suspend register 6,                      Address offset: 0x58 */
-  __IO uint32_t SUSP7R;      /*!< AES Suspend register 7,                      Address offset: 0x6C */
-} AES_TypeDef;
-
-/**
-  * @brief Comparator
-  */
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register,               Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/**
-  * @brief CRC calculation unit
-  */
-typedef struct
-{
-  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
-  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
-       uint32_t RESERVED2;   /*!< Reserved,                                                    0x0C */
-  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
-  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Digital to Analog Converter
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-       uint32_t RESERVED1;   /*!< Reserved                                                 Address offset: 0x14 */
-       uint32_t RESERVED2;   /*!< Reserved                                                 Address offset: 0x18 */
-       uint32_t RESERVED3;   /*!< Reserved                                                 Address offset: 0x1C */
-  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-       uint32_t RESERVED4;   /*!< Reserved                                                 Address offset: 0x30 */
-  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
-  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
-  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
-  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
-       uint32_t RESERVED5;   /*!< Reserved                                                 Address offset: 0x44 */
-  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
-  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
-} DAC_TypeDef;
-
-#if defined(CORE_CM0PLUS)
-#else
-/**
-  * @brief Debug MCU
-  */
-typedef struct
-{
-  __IO uint32_t IDCODE;      /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;          /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  uint32_t RESERVED1[13];    /*!< Reserved,                                               0x08-0x38 */
-  __IO uint32_t APB1FZR1;    /*!< Debug MCU CPU1 APB1 freeze register,         Address offset: 0x3C */
-  __IO uint32_t C2APB1FZR1;  /*!< Debug MCU CPU2 APB1 freeze register,         Address offset: 0x40 */
-  __IO uint32_t APB1FZR2;    /*!< Debug MCU CPU1 APB1 freeze register,         Address offset: 0x44 */
-  __IO uint32_t C2APB1FZR2;  /*!< Debug MCU CPU2 APB1 freeze register,         Address offset: 0x48 */
-  __IO uint32_t APB2FZR;     /*!< Debug MCU CPU1 APB2 freeze register,         Address offset: 0x4C */
-  __IO uint32_t C2APB2FZR;   /*!< Debug MCU CPU2 APB2 freeze register,         Address offset: 0x50 */
-} DBGMCU_TypeDef;
-#endif
-
-/**
-  * @brief DMA Controller
-  */
-typedef struct
-{
-  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
-  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
-} DMA_TypeDef;
-
-/**
-  * @brief DMA Multiplexer
-  */
-typedef struct
-{
-  __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
-}DMAMUX_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t   CSR;       /*!< DMA Channel Status Register                    Address offset: 0x0080   */
-  __IO uint32_t   CFR;       /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
-}DMAMUX_ChannelStatus_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
-}DMAMUX_RequestGen_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
-  __IO uint32_t   RGCFR;       /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
-}DMAMUX_RequestGenStatus_TypeDef;
-
-/**
-  * @brief Async Interrupts and Events Controller
-  */
-typedef struct
-{
-  __IO uint32_t RTSR1;          /*!< EXTI rising trigger selection register [31:0],            Address offset: 0x00 */
-  __IO uint32_t FTSR1;          /*!< EXTI falling trigger selection register [31:0],           Address offset: 0x04 */
-  __IO uint32_t SWIER1;         /*!< EXTI software interrupt event register [31:0],            Address offset: 0x08 */
-  __IO uint32_t PR1;            /*!< EXTI pending register [31:0],                             Address offset: 0x0C */
-  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                                 Address offset: 0x10 - 0x1C */
-  __IO uint32_t RTSR2;          /*!< EXTI rising trigger selection register [31:0],            Address offset: 0x20 */
-  __IO uint32_t FTSR2;          /*!< EXTI falling trigger selection register [31:0],           Address offset: 0x24 */
-  __IO uint32_t SWIER2;         /*!< EXTI software interrupt event register [31:0],            Address offset: 0x28 */
-  __IO uint32_t PR2;            /*!< EXTI pending register [31:0],                             Address offset: 0x2C */
-  __IO uint32_t RESERVED2[4];   /*!< Reserved,                                                 Address offset: 0x30 - 0x3C */
-  __IO uint32_t RESERVED3[8];   /*!< Reserved,                                                 Address offset: 0x40 - 0x5C */
-  __IO uint32_t RESERVED4[8];   /*!< Reserved,                                                 Address offset: 0x60 - 0x7C */
-  __IO uint32_t IMR1;           /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
-  __IO uint32_t EMR1;           /*!< EXTI wakeup with event mask register for cpu1 [31:0],     Address offset: 0x84 */
-  __IO uint32_t RESERVED5[2];   /*!< Reserved,                                                 Address offset: 0x88 - 0x8C */
-  __IO uint32_t IMR2;           /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
-  __IO uint32_t EMR2;           /*!< EXTI wakeup with event mask register for cpu1 [31:0],     Address offset: 0x94 */
-  __IO uint32_t RESERVED8[10];  /*!< Reserved,                                                 Address offset: 0x98 - 0xBC */
-  __IO uint32_t C2IMR1;         /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */
-  __IO uint32_t C2EMR1;         /*!< EXTI wakeup with event mask register for cpu2 [31:0],     Address offset: 0xC4 */
-  __IO uint32_t RESERVED9[2];   /*!< Reserved,                                                 Address offset: 0xC8 - 0xCC */
-  __IO uint32_t C2IMR2;         /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */
-  __IO uint32_t C2EMR2;         /*!< EXTI wakeup with event mask register for cpu2 [31:0],     Address offset: 0xD4 */
-}EXTI_TypeDef;
-
-/**
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< FLASH Access control register,                      Address offset: 0x00      */
-  __IO uint32_t ACR2;          /*!< FLASH Access control register 2,                    Address offset: 0x04      */
-  __IO uint32_t KEYR;          /*!< FLASH Key register,                                 Address offset: 0x08      */
-  __IO uint32_t OPTKEYR;       /*!< FLASH Option Key register,                          Address offset: 0x0C      */
-  __IO uint32_t SR;            /*!< FLASH Status register,                              Address offset: 0x10      */
-  __IO uint32_t CR;            /*!< FLASH Control register,                             Address offset: 0x14      */
-  __IO uint32_t ECCR;          /*!< FLASH ECC register,                                 Address offset: 0x18      */
-  uint32_t RESERVED1;          /*!< Reserved,                                           Address offset: 0x1C      */
-  __IO uint32_t OPTR;          /*!< FLASH Option register,                              Address offset: 0x20      */
-  __IO uint32_t PCROP1ASR;     /*!< FLASH Bank 1 PCROP area A Start address register,   Address offset: 0x24      */
-  __IO uint32_t PCROP1AER;     /*!< FLASH Bank 1 PCROP area A End address register,     Address offset: 0x28      */
-  __IO uint32_t WRP1AR;        /*!< FLASH Bank 1 WRP area A address register,           Address offset: 0x2C      */
-  __IO uint32_t WRP1BR;        /*!< FLASH Bank 1 WRP area B address register,           Address offset: 0x30      */
-  __IO uint32_t PCROP1BSR;     /*!< FLASH Bank 1 PCROP area B Start address register,   Address offset: 0x34      */
-  __IO uint32_t PCROP1BER;     /*!< FLASH Bank 1 PCROP area B End address register,     Address offset: 0x38      */
-  __IO uint32_t IPCCBR;        /*!< FLASH IPCC data buffer address,                     Address offset: 0x3C      */
-  uint32_t RESERVED2[7];       /*!< Reserved,                                           Address offset: 0x40-0x58 */
-  __IO uint32_t C2ACR;         /*!< FLASH Core MO+ Access Control Register ,            Address offset: 0x5C      */
-  __IO uint32_t C2SR;          /*!< FLASH Core MO+ Status Register,                     Address offset: 0x60      */
-  __IO uint32_t C2CR;          /*!< FLASH Core MO+ Control register,                    Address offset: 0x64      */
-  uint32_t RESERVED3[6];       /*!< Reserved,                                           Address offset: 0x68-0x7C */
-  __IO uint32_t SFR;           /*!< FLASH secure start address,                         Address offset: 0x80      */
-  __IO uint32_t SRRVR;         /*!< FlASH secure SRAM2 start addr and CPU2 reset vector Address offset: 0x84      */
-} FLASH_TypeDef;
-
-/**
-  * @brief General Purpose I/O
-  */
-typedef struct
-{
-  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
-  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/**
-  * @brief Global Security Controller
-  */
-typedef struct{
-  __IO uint32_t CR;             /*!< TZSC control register,                             Address offset: 0x00       */
-       uint32_t RESERVED1[3];   /*!< Reserved1,                                         Address offset: 0x04-0x0C  */
-  __IO uint32_t SECCFGR1;       /*!< TZSC secure configuration register 1,              Address offset: 0x10       */
-       uint32_t RESERVED2[3];   /*!< Reserved2,                                         Address offset: 0x14-0x1C  */
-  __IO uint32_t PRIVCFGR1;      /*!< TZSC privilege configuration register 1,           Address offset: 0x20       */
-       uint32_t RESERVED3[67];  /*!< Reserved3,                                         Address offset: 0x24-0x12C */
-  __IO uint32_t MPCWM1_UPWMR;   /*!< TZSC Unprivileged Water Mark 1 register,           Address offset: 0x130      */
-  __IO uint32_t MPCWM1_UPWWMR;  /*!< TZSC Unprivileged Writable Water Mark 1 register,  Address offset: 0x134      */
-  __IO uint32_t MPCWM2_UPWMR;   /*!< TZSC Unprivileged Water Mark 2 register,           Address offset: 0x138      */
-       uint32_t RESERVED4;      /*!< Reserved4,                                         Address offset: 0x13C      */
-  __IO uint32_t MPCWM3_UPWMR;   /*!< TZSC Unprivileged Water Mark 2 register,           Address offset: 0x140      */
-} GTZC_TZSC_TypeDef;
-
-typedef struct{
-  __IO uint32_t IER1;           /*!< TZIC interrupt enable register 1,    Address offset: 0x00 */
-  uint32_t RESERVED1[3];        /*!< Reserved1,                           Address offset: 0x0C */
-  __IO uint32_t MISR1;          /*!< TZIC interrupt status register 1,    Address offset: 0x10 */
-  uint32_t RESERVED2[3];        /*!< Reserved2,                           Address offset: 0x1C */
-  __IO uint32_t ICR1;           /*!< TZIC interrupt clear register 1,     Address offset: 0x20 */
-} GTZC_TZIC_TypeDef;
-
-/**
-  * @brief HW Semaphore HSEM
-  */
-typedef struct
-{
-  __IO uint32_t R[16];      /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-3Ch  */
-   uint32_t  Reserved1[16]; /*!< Reserved                                        Address offset: 40h-7Ch  */
-  __IO uint32_t RLR[16];    /*!< HSEM 1-step read lock registers,                Address offset: 80h-BCh  */
-   uint32_t  Reserved2[16]; /*!< Reserved                                        Address offset: C0h-FCh  */
-  __IO uint32_t C1IER;      /*!< HSEM CPU1 interrupt enable register ,           Address offset: 100h     */
-  __IO uint32_t C1ICR;      /*!< HSEM CPU1 interrupt clear register ,            Address offset: 104h     */
-  __IO uint32_t C1ISR;      /*!< HSEM CPU1 interrupt status register ,           Address offset: 108h     */
-  __IO uint32_t C1MISR;     /*!< HSEM CPU1 masked interrupt status register ,    Address offset: 10Ch     */
-  __IO uint32_t C2IER;      /*!< HSEM CPU2 interrupt enable register ,           Address offset: 110h     */
-  __IO uint32_t C2ICR;      /*!< HSEM CPU2 interrupt clear register ,            Address offset: 114h     */
-  __IO uint32_t C2ISR;      /*!< HSEM CPU2 interrupt status register ,           Address offset: 118h     */
-  __IO uint32_t C2MISR;     /*!< HSEM CPU2 masked interrupt status register ,    Address offset: 11Ch     */
-   uint32_t  Reserved[8];   /*!< Reserved                                        Address offset: 120h-13Ch*/
-  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                 Address offset: 140h     */
-  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,             Address offset: 144h     */
-} HSEM_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */
-  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */
-  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */
-  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */
-} HSEM_Common_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
-} I2C_TypeDef;
-
-/**
-  * @brief Inter-Processor Communication
-  */
-typedef struct
-{
-  __IO uint32_t C1CR;             /*!< Inter-Processor Communication: C1 control register,                  Address offset: 0x000 */
-  __IO uint32_t C1MR ;            /*!< Inter-Processor Communication: C1 mask register,                     Address offset: 0x004 */
-  __IO uint32_t C1SCR;            /*!< Inter-Processor Communication: C1 status set clear register,         Address offset: 0x008 */
-  __IO uint32_t C1TOC2SR;         /*!< Inter-Processor Communication: C1 to processor M4  status register,  Address offset: 0x00C */
-  __IO uint32_t C2CR;             /*!< Inter-Processor Communication: C2 control register,                  Address offset: 0x010 */
-  __IO uint32_t C2MR ;            /*!< Inter-Processor Communication: C2 mask register,                     Address offset: 0x014 */
-  __IO uint32_t C2SCR;            /*!< Inter-Processor Communication: C2 status set clear register,         Address offset: 0x018 */
-  __IO uint32_t C2TOC1SR;         /*!< Inter-Processor Communication: C2 to processor M4 status register,   Address offset: 0x01C */
-} IPCC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR;               /*!< Control register,                                                    Address offset: 0x000 */
-  __IO uint32_t MR;               /*!< Mask register,                                                       Address offset: 0x004 */
-  __IO uint32_t SCR;              /*!< Status set clear register,                                           Address offset: 0x008 */
-  __IO uint32_t SR;               /*!< Status register,                                                     Address offset: 0x00C */
-} IPCC_CommonTypeDef;
-
-/**
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/**
-  * @brief LPTIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
-  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
-  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
-  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
-  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
-  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
-  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
-  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
-  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
-  __IO uint32_t RESERVED;    /*!< Reserved,                                           Address offset: 0x24 */
-  __IO uint32_t RCR;         /*!< LPTIM repetition register,                          Address offset: 0x28 */
-} LPTIM_TypeDef;
-
-/**
-  * @brief Public Key Accelerator (PKA)
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< PKA control register,                 Address offset: 0x00 */
-  __IO uint32_t SR;          /*!< PKA status register,                  Address offset: 0x04 */
-  __IO uint32_t CLRFR;       /*!< PKA clear flag register,              Address offset: 0x08 */
-  uint32_t  Reserved1[253];  /*!< Reserved                              Address offset: 0x000C-0x03FC*/
-  __IO uint32_t RAM[894];    /*!< PKA RAM,                              Address offset: 0x0400-0x11F4 */
-} PKA_TypeDef;
-
-/**
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< PWR Power Control Register 1,                     Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< PWR Power Control Register 2,                     Address offset: 0x04 */
-  __IO uint32_t CR3;          /*!< PWR Power Control Register 3,                     Address offset: 0x08 */
-  __IO uint32_t CR4;          /*!< PWR Power Control Register 4,                     Address offset: 0x0C */
-  __IO uint32_t SR1;          /*!< PWR Power Status Register 1,                      Address offset: 0x10 */
-  __IO uint32_t SR2;          /*!< PWR Power Status Register 2,                      Address offset: 0x14 */
-  __IO uint32_t SCR;          /*!< PWR Power Status Reset Register,                  Address offset: 0x18 */
-  __IO uint32_t CR5;          /*!< PWR Power Control Register 5,                     Address offset: 0x1C */
-  __IO uint32_t PUCRA;        /*!< PWR Pull-Up Control Register of port A,           Address offset: 0x20 */
-  __IO uint32_t PDCRA;        /*!< PWR Pull-Down Control Register of port A,         Address offset: 0x24 */
-  __IO uint32_t PUCRB;        /*!< PWR Pull-Up Control Register of port B,           Address offset: 0x28 */
-  __IO uint32_t PDCRB;        /*!< PWR Pull-Down Control Register of port B,         Address offset: 0x2C */
-  __IO uint32_t PUCRC;        /*!< PWR Pull-Up Control Register of port C,           Address offset: 0x30 */
-  __IO uint32_t PDCRC;        /*!< PWR Pull-Down Control Register of port C,         Address offset: 0x34 */
-       uint32_t RESERVED0[8]; /*!< Reserved,                                         Address offset: 0x38-0x54 */
-  __IO uint32_t PUCRH;        /*!< PWR Pull-Up Control Register of port H,           Address offset: 0x58 */
-  __IO uint32_t PDCRH;        /*!< PWR Pull-Down Control Register of port H,         Address offset: 0x5C */
-       uint32_t RESERVED1[8]; /*!< Reserved,                                         Address offset: 0x60-0x7C */
-  __IO uint32_t C2CR1;        /*!< PWR Power Control Register 1 for CPU2,            Address offset: 0x80 */
-  __IO uint32_t C2CR3;        /*!< PWR Power Control Register 3 for CPU2,            Address offset: 0x84 */
-  __IO uint32_t EXTSCR;       /*!< PWR Power Status Reset Register for CPU2,         Address offset: 0x88 */
-  __IO uint32_t SECCFGR;      /*!< PWR Security Configuration Register,              Address offset: 0x8C */
-  __IO uint32_t SUBGHZSPICR;  /*!< PWR SUBGHZSPI Control Register,                   Address offset: 0x90 */
-       uint32_t RESERVED2;    /*!< Reserved,                                         Address offset: 0x94 */
-  __IO uint32_t RSSCMDR;      /*!< PWR RSS Command Register,                         Address offset: 0x98 */
-} PWR_TypeDef;
-
-/**
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;           /*!< RCC clock  Control Register,                                                    Address offset: 0x00 */
-  __IO uint32_t ICSCR;        /*!< RCC Internal Clock Sources Calibration Register,                                Address offset: 0x04 */
-  __IO uint32_t CFGR;         /*!< RCC Clocks Configuration Register,                                              Address offset: 0x08 */
-  __IO uint32_t PLLCFGR;      /*!< RCC System PLL configuration Register,                                          Address offset: 0x0C */
-uint32_t RESERVED0;           /*!< Reserved,                                                                       Address offset: 0x10 */
-uint32_t RESERVED1;           /*!< Reserved,                                                                       Address offset: 0x14 */
-  __IO uint32_t CIER;         /*!< RCC Clock Interrupt Enable Register,                                            Address offset: 0x18 */
-  __IO uint32_t CIFR;         /*!< RCC Clock Interrupt Flag Register,                                              Address offset: 0x1C */
-  __IO uint32_t CICR;         /*!< RCC Clock Interrupt Clear Register,                                             Address offset: 0x20 */
-uint32_t RESERVED2;           /*!< Reserved,                                                                       Address offset: 0x24 */
-  __IO uint32_t AHB1RSTR;     /*!< RCC AHB1 peripheral reset register,                                             Address offset: 0x28 */
-  __IO uint32_t AHB2RSTR;     /*!< RCC AHB2 peripheral reset register,                                             Address offset: 0x2C */
-  __IO uint32_t AHB3RSTR;     /*!< RCC AHB3 peripheral reset register,                                             Address offset: 0x30 */
-uint32_t RESERVED3;           /*!< Reserved,                                                                       Address offset: 0x34 */
-  __IO uint32_t APB1RSTR1;    /*!< RCC APB1 peripheral reset register 1,                                           Address offset: 0x38 */
-  __IO uint32_t APB1RSTR2;    /*!< RCC APB1 peripheral reset register 2,                                           Address offset: 0x3C */
-  __IO uint32_t APB2RSTR;     /*!< RCC APB2 peripheral reset register,                                             Address offset: 0x40 */
-  __IO uint32_t APB3RSTR;     /*!< RCC APB3 peripheral reset register,                                             Address offset: 0x44 */
-  __IO uint32_t AHB1ENR;      /*!< RCC AHB1 peripheral clocks enable register,                                     Address offset: 0x48 */
-  __IO uint32_t AHB2ENR;      /*!< RCC AHB2 peripheral clocks enable register,                                     Address offset: 0x4C */
-  __IO uint32_t AHB3ENR;      /*!< RCC AHB3 peripheral clocks enable register,                                     Address offset: 0x50 */
-uint32_t RESERVED4;           /*!< Reserved,                                                                       Address offset: 0x54 */
-  __IO uint32_t APB1ENR1;     /*!< RCC APB1 peripheral clocks enable register 1,                                   Address offset: 0x58 */
-  __IO uint32_t APB1ENR2;     /*!< RCC APB1 peripheral clocks enable register 2,                                   Address offset: 0x5C */
-  __IO uint32_t APB2ENR;      /*!< RCC APB2 peripheral clocks enable register,                                     Address offset: 0x60 */
-  __IO uint32_t APB3ENR;      /*!< RCC APB3 peripheral clocks enable register,                                     Address offset: 0x64 */
-  __IO uint32_t AHB1SMENR;    /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,             Address offset: 0x68 */
-  __IO uint32_t AHB2SMENR;    /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,             Address offset: 0x6C */
-  __IO uint32_t AHB3SMENR;    /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
-uint32_t RESERVED5;           /*!< Reserved,                                                                       Address offset: 0x74 */
-  __IO uint32_t APB1SMENR1;   /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1,      Address offset: 0x78 */
-  __IO uint32_t APB1SMENR2;   /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2,      Address offset: 0x7C */
-  __IO uint32_t APB2SMENR;    /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register,        Address offset: 0x80 */
-  __IO uint32_t APB3SMENR;    /*!< RCC APB3 peripheral clocks enable in sleep mode and stop modes register,        Address offset: 0x84 */
-  __IO uint32_t CCIPR;        /*!< RCC Peripherals Clock Configuration Independent Register,                       Address offset: 0x88 */
-uint32_t RESERVED6;           /*!< Reserved,                                                                       Address offset: 0x8C */
-  __IO uint32_t BDCR;         /*!< RCC Backup Domain Control Register,                                             Address offset: 0x90 */
-  __IO uint32_t CSR;          /*!< RCC Control and Status Register,                                                Address offset: 0x94 */
-uint32_t RESERVED7[28];       /*!< Reserved,                                                                       Address offset: 0x98-0x104 */
-  __IO uint32_t EXTCFGR;      /*!< RCC Extended Clock Recovery Register,                                           Address offset: 0x108 */
-  __IO uint32_t RESERVED8[15]; /*!< Reserved,                                                                      Address offset: 0x10C-0x144 */
-  __IO uint32_t C2AHB1ENR;   /*!< RRCC AHB1 peripheral CPU2 clocks enable register,                                Address offset: 0x148 */
-  __IO uint32_t C2AHB2ENR;   /*!< RCC AHB2 peripheral CPU2 clocks enable register,                                 Address offset: 0x14C */
-  __IO uint32_t C2AHB3ENR;   /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,,                         Address offset: 0x150 */
-uint32_t RESERVED9;           /*!< Reserved,                                                                       Address offset: 0x154 */
-  __IO uint32_t C2APB1ENR1;  /*!< RCC APB1 peripheral CPU2 clocks enable register 1,                               Address offset: 0x158 */
-  __IO uint32_t C2APB1ENR2;  /*!< RCC APB1 peripheral CPU2 clocks enable register 2,                               Address offset: 0x15C */
-  __IO uint32_t C2APB2ENR;   /*!< RCC APB2 peripheral CPU2 clocks enable register 1,                               Address offset: 0x160 */
-  __IO uint32_t C2APB3ENR;   /*!< RCC APB3 peripheral CPU2 clocks enable register 1,                               Address offset: 0x164 */
-  __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register,         Address offset: 0x168 */
-  __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register,         Address offset: 0x16C */
-  __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register,  Address offset: 0x170 */
-uint32_t RESERVED10;          /*!< Reserved,                                                                                             */
-  __IO uint32_t C2APB1SMENR1;/*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1,  Address offset: 0x178 */
-  __IO uint32_t C2APB1SMENR2;/*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2,  Address offset: 0x17C */
-  __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register,    Address offset: 0x180 */
-  __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register,    Address offset: 0x184 */
-} RCC_TypeDef;
-
-/**
-  * @brief RNG
-  */
-typedef struct
-{
-  __IO uint32_t CR;        /*!< RNG control register,             Address offset: 0x00 */
-  __IO uint32_t SR;        /*!< RNG status register,              Address offset: 0x04 */
-  __IO uint32_t DR;        /*!< RNG data register,                Address offset: 0x08 */
-  uint32_t      RESERVED0; /*!< Reserved,                         Address offset: 0x0C */
-  __IO uint32_t HTCR;      /*!< RNG health test control register, Address offset: 0x10 */
-} RNG_TypeDef;
-
-/**
-  * @brief RTC Specific device feature definitions
-  */
-#define RTC_BACKUP_NB       20u
-#define RTC_TAMP_NB         3u
-
-/**
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
-  __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
-  __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
-  __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
-  __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
-  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
-  __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
-       uint32_t RESERVED0;   /*!< Reserved,                                       Address offset: 0x1C */
-       uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x20 */
-  __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
-  __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
-  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
-  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
-  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
-  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
-       uint32_t RESERVED2;   /*!< Reserved,                                       Address offset: 0x3C */
-  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
-  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
-  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
-  __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
-  __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
-       uint32_t RESERVED3;   /*!< Reserved,                                       Address offset: 0x58 */
-  __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
-       uint32_t RESERVED4[4];/*!< Reserved,                                       Address offset: 0x58 */
-  __IO uint32_t ALRABINR;/*!< RTC alarm A binary mode register,                   Address offset: 0x70 */
-  __IO uint32_t ALRBBINR;/*!< RTC alarm B binary mode register,                   Address offset: 0x74 */
-} RTC_TypeDef;
-
-/**
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/**
-  * @brief System configuration controller
-  */
-typedef struct
-{
-  __IO uint32_t MEMRMP;            /*!< SYSCFG memory remap register                                            Address offset: 0x00       */
-  __IO uint32_t CFGR1;             /*!< SYSCFG configuration register 1,                                        Address offset: 0x04       */
-  __IO uint32_t EXTICR[4];         /*!< SYSCFG external interrupt configuration registers,                      Address offset: 0x08-0x14  */
-  __IO uint32_t SCSR;              /*!< SYSCFG SRAM2 control and status register,                               Address offset: 0x18       */
-  __IO uint32_t CFGR2;             /*!< SYSCFG configuration register 2,                                        Address offset: 0x1C       */
-  __IO uint32_t SWPR;              /*!< SYSCFG SRAM2 write protection register part,                            Address offset: 0x20       */
-  __IO uint32_t SKR;               /*!< SYSCFG SRAM2 key register,                                              Address offset: 0x24       */
-       uint32_t RESERVED1[54];     /*!< Reserved,                                                               Address offset: 0x28-0xFC  */
-  __IO uint32_t IMR1;              /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 1, Address offset: 0x100      */
-  __IO uint32_t IMR2;              /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 2, Address offset: 0x104      */
-  __IO uint32_t C2IMR1;            /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 1, Address offset: 0x108      */
-  __IO uint32_t C2IMR2;            /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 2, Address offset: 0x10C      */
-       uint32_t RESERVED2[62];     /*!< Reserved,                                                               Address offset: 0x110-0x204*/
-  __IO uint32_t RFDCR;             /*!< SYSCFG CPU2 radio debug control register,                               Address offset: 0x208      */
-} SYSCFG_TypeDef;
-
-/**
-  * @brief Tamper and backup registers
-  */
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TAMP configuration register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TAMP configuration register 2,            Address offset: 0x04 */
-  __IO uint32_t CR3;         /*!< TAMP configuration register 3,            Address offset: 0x08 */
-  __IO uint32_t FLTCR;       /*!< TAMP filter control register,             Address offset: 0x0C */
-       uint32_t RESERVED0[7];/*!< Reserved,                                 Address offset: 0x10 */
-  __IO uint32_t IER;         /*!< TAMP interrupt enable register,           Address offset: 0x2C */
-  __IO uint32_t SR;          /*!< TAMP status register,                     Address offset: 0x30 */
-  __IO uint32_t MISR;        /*!< TAMP masked interrupt status register,    Address offset: 0x34 */
-       uint32_t RESERVED1;   /*!< Reserved,                                 Address offset: 0x38 */
-  __IO uint32_t SCR;         /*!< TAMP status clear register,               Address offset: 0x3C */
-  __IO uint32_t COUNTR;      /*!< TAMP monotonic counter register,          Address offset: 0x40 */
-       uint32_t RESERVED2[47];/*!< Reserved,                                Address offset: 0x54 -- 0xFC */
-  __IO uint32_t BKP0R;       /*!< TAMP backup register 0,                   Address offset: 0x100 */
-  __IO uint32_t BKP1R;       /*!< TAMP backup register 1,                   Address offset: 0x104 */
-  __IO uint32_t BKP2R;       /*!< TAMP backup register 2,                   Address offset: 0x108 */
-  __IO uint32_t BKP3R;       /*!< TAMP backup register 3,                   Address offset: 0x10C */
-  __IO uint32_t BKP4R;       /*!< TAMP backup register 4,                   Address offset: 0x110 */
-  __IO uint32_t BKP5R;       /*!< TAMP backup register 5,                   Address offset: 0x114 */
-  __IO uint32_t BKP6R;       /*!< TAMP backup register 6,                   Address offset: 0x118 */
-  __IO uint32_t BKP7R;       /*!< TAMP backup register 7,                   Address offset: 0x11C */
-  __IO uint32_t BKP8R;       /*!< TAMP backup register 8,                   Address offset: 0x120 */
-  __IO uint32_t BKP9R;       /*!< TAMP backup register 9,                   Address offset: 0x124 */
-  __IO uint32_t BKP10R;      /*!< TAMP backup register 10,                  Address offset: 0x128 */
-  __IO uint32_t BKP11R;      /*!< TAMP backup register 11,                  Address offset: 0x12C */
-  __IO uint32_t BKP12R;      /*!< TAMP backup register 12,                  Address offset: 0x130 */
-  __IO uint32_t BKP13R;      /*!< TAMP backup register 13,                  Address offset: 0x134 */
-  __IO uint32_t BKP14R;      /*!< TAMP backup register 14,                  Address offset: 0x138 */
-  __IO uint32_t BKP15R;      /*!< TAMP backup register 15,                  Address offset: 0x13C */
-  __IO uint32_t BKP16R;      /*!< TAMP backup register 16,                  Address offset: 0x140 */
-  __IO uint32_t BKP17R;      /*!< TAMP backup register 17,                  Address offset: 0x144 */
-  __IO uint32_t BKP18R;      /*!< TAMP backup register 18,                  Address offset: 0x148 */
-  __IO uint32_t BKP19R;      /*!< TAMP backup register 19,                  Address offset: 0x14C */
-} TAMP_TypeDef;
-
-/**
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler register,                   Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
-  __IO uint32_t OR1;         /*!< TIM option register                       Address offset: 0x50 */
-  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
-  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
-  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
-  __IO uint32_t AF1;         /*!< TIM Alternate function option register 1, Address offset: 0x60 */
-  __IO uint32_t AF2;         /*!< TIM Alternate function option register 2, Address offset: 0x64 */
-} TIM_TypeDef;
-
-/**
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;               /*!< USART Control register 1,                 Address offset: 0x00  */
-  __IO uint32_t CR2;               /*!< USART Control register 2,                 Address offset: 0x04  */
-  __IO uint32_t CR3;               /*!< USART Control register 3,                 Address offset: 0x08  */
-  __IO uint32_t BRR;               /*!< USART Baud rate register,                 Address offset: 0x0C  */
-  __IO uint32_t GTPR;              /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
-  __IO uint32_t RTOR;              /*!< USART Receiver Time Out register,         Address offset: 0x14  */
-  __IO uint32_t RQR;               /*!< USART Request register,                   Address offset: 0x18  */
-  __IO uint32_t ISR;               /*!< USART Interrupt and status register,      Address offset: 0x1C  */
-  __IO uint32_t ICR;               /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
-  __IO uint32_t RDR;               /*!< USART Receive Data register,              Address offset: 0x24  */
-  __IO uint32_t TDR;               /*!< USART Transmit Data register,             Address offset: 0x28  */
-  __IO uint32_t PRESC;             /*!< USART Prescaler register,                 Address offset: 0x2C  */
-} USART_TypeDef;
-
-/**
-  * @brief VREFBUF
-  */
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
-  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
-} VREFBUF_TypeDef;
-
-/**
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-/*!< Boundary memory map */
-#define FLASH_BASE              0x08000000UL   /*!< FLASH(up to 256 KB) base address */
-#define SYSTEM_FLASH_BASE       0x1FFF0000UL   /*!< System FLASH(28Kb) base address */
-#define SRAM1_BASE              0x20000000UL   /*!< SRAM1(up to 32 KB) base address */
-#define SRAM2_BASE              0x20008000UL   /*!< SRAM2(up to 32 KB) base address */
-#define PERIPH_BASE             0x40000000UL   /*!< Peripheral base address */
-
-#define FLASH_SIZE              (((*((uint32_t *)FLASHSIZE_BASE)) & 0xFFFFU) << 10U)
-#define SRAM1_SIZE              0x00008000UL   /*!< SRAM1 default size : 32 kB */
-#define SRAM2_SIZE              0x00008000UL   /*!< SRAM2 default size : 32 kB  */
-
-/*!< Memory, OTP and Option bytes */
-#define RSSLIB_PFUNC_BASE       (SYSTEM_FLASH_BASE + 0x00003A00UL) /*!< RSS area                                      */
-#define OTP_AREA_BASE           (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 – 0x1FFF73FF)      */
-#define ENGI_BYTES_BASE         (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 – 0x1FFF77FF)    */
-#define OPTION_BYTES_BASE       (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 – 0x1FFF7FFF)  */
-
-/*!< Device Electronic Signature */
-#define PACKAGE_BASE            (ENGI_BYTES_BASE + 0x00000100UL) /*!< Package data register base address     */
-#define UID64_BASE              (ENGI_BYTES_BASE + 0x00000180UL) /*!< 64-bit Unique device Identification    */
-#define UID_BASE                (ENGI_BYTES_BASE + 0x00000190UL) /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE          (ENGI_BYTES_BASE + 0x000001E0UL) /*!< Flash size data register base address  */
-
-#define SYSTEM_MEMORY_END_ADDR  (0x1FFF6FFFUL)   /*!< System Memory : 28KB (0x1FFF0000 – 0x1FFF6FFF)  */
-#define OTP_AREA_END_ADDR       (0x1FFF73FFUL)   /*!< OTP area : 1KB (0x1FFF7000 – 0x1FFF73FF)        */
-#define ENGI_BYTE_END_ADDR      (0x1FFF77FFUL)   /*!< Engi Bytes : 1kB (0x1FFF7400 – 0x1FFF77FF)      */
-#define OPTION_BYTE_END_ADDR    (0x1FFF7FFFUL)   /*!< Option Bytes : 2KB (0x1FFF7800 – 0x1FFF7FFF)    */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE         PERIPH_BASE
-#define APB2PERIPH_BASE         (PERIPH_BASE + 0x00010000UL)
-#define AHB1PERIPH_BASE         (PERIPH_BASE + 0x00020000UL)
-#define AHB2PERIPH_BASE         (PERIPH_BASE + 0x08000000UL)
-#define AHB3PERIPH_BASE         (PERIPH_BASE + 0x18000000UL)
-#define APB3PERIPH_BASE         (PERIPH_BASE + 0x18010000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE               (APB1PERIPH_BASE + 0x00000000UL)
-#define RTC_BASE                (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE               (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE               (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE               (APB1PERIPH_BASE + 0x00003800UL)
-#define USART2_BASE             (APB1PERIPH_BASE + 0x00004400UL)
-#define I2C1_BASE               (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE               (APB1PERIPH_BASE + 0x00005800UL)
-#define I2C3_BASE               (APB1PERIPH_BASE + 0x00005C00UL)
-#define DAC_BASE                (APB1PERIPH_BASE + 0x00007400UL)
-#define LPTIM1_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define LPUART1_BASE            (APB1PERIPH_BASE + 0x00008000UL)
-#define LPTIM2_BASE             (APB1PERIPH_BASE + 0x00009400UL)
-#define LPTIM3_BASE             (APB1PERIPH_BASE + 0x00009800UL)
-#define TAMP_BASE               (APB1PERIPH_BASE + 0x0000B000UL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE             (APB2PERIPH_BASE + 0x00000000UL)
-#define VREFBUF_BASE            (APB2PERIPH_BASE + 0x00000030UL)
-#define COMP1_BASE              (APB2PERIPH_BASE + 0x00000200UL)
-#define COMP2_BASE              (APB2PERIPH_BASE + 0x00000204UL)
-#define ADC_BASE                (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_COMMON_BASE         (APB2PERIPH_BASE + 0x00002708UL)
-#define TIM1_BASE               (APB2PERIPH_BASE + 0x00002C00UL)
-#define SPI1_BASE               (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE             (APB2PERIPH_BASE + 0x00003800UL)
-#define TIM16_BASE              (APB2PERIPH_BASE + 0x00004400UL)
-#define TIM17_BASE              (APB2PERIPH_BASE + 0x00004800UL)
-
-/*!< AHB1 peripherals */
-#define DMA1_BASE               (AHB1PERIPH_BASE + 0x00000000UL)
-#define DMA2_BASE               (AHB1PERIPH_BASE + 0x00000400UL)
-#define DMAMUX1_BASE            (AHB1PERIPH_BASE + 0x00000800UL)
-#define CRC_BASE                (AHB1PERIPH_BASE + 0x00003000UL)
-
-#define DMA1_Channel1_BASE       (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE       (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE       (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE       (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE       (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE       (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE       (DMA1_BASE + 0x00000080UL)
-
-#define DMA2_Channel1_BASE       (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE       (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE       (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE       (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE       (DMA2_BASE + 0x00000058UL)
-#define DMA2_Channel6_BASE       (DMA2_BASE + 0x0000006CUL)
-#define DMA2_Channel7_BASE       (DMA2_BASE + 0x00000080UL)
-
-#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
-#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x00000004UL)
-#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x00000008UL)
-#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x0000000CUL)
-#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x00000010UL)
-#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x00000014UL)
-#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x00000018UL)
-#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x0000001CUL)
-#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x00000020UL)
-#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x00000024UL)
-#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x00000028UL)
-#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x0000002CUL)
-#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x00000030UL)
-#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x00000034UL)
-
-#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x00000100UL)
-#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x00000104UL)
-#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x00000108UL)
-#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x0000010CUL)
-
-#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x00000080UL)
-#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x00000140UL)
-
-/*!< AHB2 peripherals */
-#define IOPORT_BASE             (AHB2PERIPH_BASE + 0x00000000UL)
-#define GPIOA_BASE              (IOPORT_BASE + 0x00000000UL)
-#define GPIOB_BASE              (IOPORT_BASE + 0x00000400UL)
-#define GPIOC_BASE              (IOPORT_BASE + 0x00000800UL)
-#define GPIOH_BASE              (IOPORT_BASE + 0x00001C00UL)
-
-/*!< AHB3 peripherals */
-#define PWR_BASE                (AHB3PERIPH_BASE + 0x00000400UL)
-#define EXTI_BASE               (AHB3PERIPH_BASE + 0x00000800UL)
-#define IPCC_BASE               (AHB3PERIPH_BASE + 0x00000C00UL)
-#define RCC_BASE                (AHB3PERIPH_BASE + 0x00000000UL)
-#define RNG_BASE                (AHB3PERIPH_BASE + 0x00001000UL)
-#define HSEM_BASE               (AHB3PERIPH_BASE + 0x00001400UL)
-#define AES_BASE                (AHB3PERIPH_BASE + 0x00001800UL)
-#define PKA_BASE                (AHB3PERIPH_BASE + 0x00002000UL)
-#define FLASH_REG_BASE          (AHB3PERIPH_BASE + 0x00004000UL)
-#define GTZC_TZSC_BASE          (AHB3PERIPH_BASE + 0x00004400UL)
-#define GTZC_TZIC_BASE          (AHB3PERIPH_BASE + 0x00004800UL)
-
-/*!< APB3 peripherals */
-#define SUBGHZSPI_BASE          (APB3PERIPH_BASE + 0x00000000UL)
-
-#if defined(CORE_CM0PLUS)
-#else
-/*!< Peripherals available on CPU1 external PPB bus */
-#define DBGMCU_BASE             (0xE0042000UL)
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_declaration
-  * @{
-  */
-
-/* Peripherals available on APB1 bus */
-#define TIM2                    ((TIM_TypeDef *) TIM2_BASE)
-#define IWDG                    ((IWDG_TypeDef *) IWDG_BASE)
-#define WWDG                    ((WWDG_TypeDef *) WWDG_BASE)
-#define DAC                     ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1                  ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define LPTIM2                  ((LPTIM_TypeDef *) LPTIM2_BASE)
-#define LPTIM3                  ((LPTIM_TypeDef *) LPTIM3_BASE)
-#define RTC                     ((RTC_TypeDef *) RTC_BASE)
-#define SPI2                    ((SPI_TypeDef *) SPI2_BASE)
-#define I2C1                    ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                    ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                    ((I2C_TypeDef *) I2C3_BASE)
-#define TAMP                    ((TAMP_TypeDef *) TAMP_BASE)
-#define USART2                  ((USART_TypeDef *) USART2_BASE)
-#define LPUART1                 ((USART_TypeDef *) LPUART1_BASE)
-
-/* Peripherals available on APB2 bus */
-#define SYSCFG                  ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define VREFBUF                 ((VREFBUF_TypeDef *) VREFBUF_BASE)
-#define COMP1                   ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2                   ((COMP_TypeDef *) COMP2_BASE)
-#define COMP12_COMMON           ((COMP_Common_TypeDef *) COMP2_BASE)
-#define TIM1                    ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1                    ((SPI_TypeDef *) SPI1_BASE)
-#define ADC                     ((ADC_TypeDef *) ADC_BASE)
-#define ADC_COMMON              ((ADC_Common_TypeDef *) ADC_COMMON_BASE)
-#define TIM16                   ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17                   ((TIM_TypeDef *) TIM17_BASE)
-#define USART1                  ((USART_TypeDef *) USART1_BASE)
-
-/* Peripherals available on AHB1 bus */
-#define DMA1                    ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1           ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2           ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3           ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4           ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5           ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6           ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7           ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-
-#define DMA2                    ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1           ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2           ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3           ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4           ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5           ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DMA2_Channel6           ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
-#define DMA2_Channel7           ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
-
-#define DMAMUX1                 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
-#define DMAMUX1_Channel0        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
-#define DMAMUX1_Channel1        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
-#define DMAMUX1_Channel2        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
-#define DMAMUX1_Channel3        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
-#define DMAMUX1_Channel4        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
-#define DMAMUX1_Channel5        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
-#define DMAMUX1_Channel6        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
-#define DMAMUX1_Channel7        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
-#define DMAMUX1_Channel8        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
-#define DMAMUX1_Channel9        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
-#define DMAMUX1_Channel10       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
-#define DMAMUX1_Channel11       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
-#define DMAMUX1_Channel12       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
-#define DMAMUX1_Channel13       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
-
-#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
-#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
-#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
-#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
-
-#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
-#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
-
-#define CRC                     ((CRC_TypeDef *) CRC_BASE)
-
-/* Peripherals available on AHB2 bus */
-#define GPIOA                   ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB                   ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC                   ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOH                   ((GPIO_TypeDef *) GPIOH_BASE)
-
-/* Peripherals available on AH3 bus */
-#define AES                     ((AES_TypeDef *) AES_BASE)
-
-#define EXTI                    ((EXTI_TypeDef *) EXTI_BASE)
-#define IPCC                    ((IPCC_TypeDef *) IPCC_BASE)
-#define IPCC_C1                 ((IPCC_CommonTypeDef *) IPCC_BASE)
-#define IPCC_C2                 ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U))
-#define RCC                     ((RCC_TypeDef *) RCC_BASE)
-#define PWR                     ((PWR_TypeDef *) PWR_BASE)
-#define RNG                     ((RNG_TypeDef *) RNG_BASE)
-#define HSEM                    ((HSEM_TypeDef *) HSEM_BASE)
-#if defined(CORE_CM0PLUS)
-#define HSEM_COMMON             ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110U))
-#else
-#define HSEM_COMMON             ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U))
-#endif
-#define PKA                     ((PKA_TypeDef *) PKA_BASE)
-#define FLASH                   ((FLASH_TypeDef *) FLASH_REG_BASE)
-#define GTZC_TZSC               ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE)
-#define GTZC_TZIC               ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE)
-
-/* Peripherals available on APB3 bus */
-#define SUBGHZSPI               ((SPI_TypeDef *) SUBGHZSPI_BASE)
-
-#if defined(CORE_CM0PLUS)
-#else
-/* Peripherals available on CPU1 external PPB bus */
-#define DBGMCU                  ((DBGMCU_TypeDef *) DBGMCU_BASE)
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-/** @addtogroup Hardware_Constant_Definition
-  * @{
-  */
-#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_ISR register  *******************/
-#define ADC_ISR_ADRDY_Pos              (0U)
-#define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
-#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
-#define ADC_ISR_EOSMP_Pos              (1U)
-#define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
-#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
-#define ADC_ISR_EOC_Pos                (2U)
-#define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
-#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
-#define ADC_ISR_EOS_Pos                (3U)
-#define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
-#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
-#define ADC_ISR_OVR_Pos                (4U)
-#define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
-#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
-#define ADC_ISR_AWD1_Pos               (7U)
-#define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
-#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
-#define ADC_ISR_AWD2_Pos               (8U)
-#define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
-#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
-#define ADC_ISR_AWD3_Pos               (9U)
-#define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
-#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
-#define ADC_ISR_EOCAL_Pos              (11U)
-#define ADC_ISR_EOCAL_Msk              (0x1UL << ADC_ISR_EOCAL_Pos)            /*!< 0x00000800 */
-#define ADC_ISR_EOCAL                  ADC_ISR_EOCAL_Msk                       /*!< ADC end of calibration flag */
-#define ADC_ISR_CCRDY_Pos              (13U)
-#define ADC_ISR_CCRDY_Msk              (0x1UL << ADC_ISR_CCRDY_Pos)            /*!< 0x00002000 */
-#define ADC_ISR_CCRDY                  ADC_ISR_CCRDY_Msk                       /*!< ADC channel configuration ready flag */
-
-/********************  Bit definition for ADC_IER register  *******************/
-#define ADC_IER_ADRDYIE_Pos            (0U)
-#define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
-#define ADC_IER_EOSMPIE_Pos            (1U)
-#define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
-#define ADC_IER_EOCIE_Pos              (2U)
-#define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
-#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
-#define ADC_IER_EOSIE_Pos              (3U)
-#define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
-#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
-#define ADC_IER_OVRIE_Pos              (4U)
-#define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
-#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
-#define ADC_IER_AWD1IE_Pos             (7U)
-#define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
-#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
-#define ADC_IER_AWD2IE_Pos             (8U)
-#define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
-#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
-#define ADC_IER_AWD3IE_Pos             (9U)
-#define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
-#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
-#define ADC_IER_EOCALIE_Pos            (11U)
-#define ADC_IER_EOCALIE_Msk            (0x1UL << ADC_IER_EOCALIE_Pos)          /*!< 0x00000800 */
-#define ADC_IER_EOCALIE                ADC_IER_EOCALIE_Msk                     /*!< ADC end of calibration interrupt */
-#define ADC_IER_CCRDYIE_Pos            (13U)
-#define ADC_IER_CCRDYIE_Msk            (0x1UL << ADC_IER_CCRDYIE_Pos)          /*!< 0x00002000 */
-#define ADC_IER_CCRDYIE                ADC_IER_CCRDYIE_Msk                     /*!< ADC channel configuration ready interrupt */
-
-/********************  Bit definition for ADC_CR register  ********************/
-#define ADC_CR_ADEN_Pos                (0U)
-#define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
-#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
-#define ADC_CR_ADDIS_Pos               (1U)
-#define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
-#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
-#define ADC_CR_ADSTART_Pos             (2U)
-#define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
-#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
-#define ADC_CR_ADSTP_Pos               (4U)
-#define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
-#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
-#define ADC_CR_ADVREGEN_Pos            (28U)
-#define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
-#define ADC_CR_ADCAL_Pos               (31U)
-#define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
-#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
-
-/********************  Bit definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_DMAEN_Pos            (0U)
-#define ADC_CFGR1_DMAEN_Msk            (0x1UL << ADC_CFGR1_DMAEN_Pos)          /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN                ADC_CFGR1_DMAEN_Msk                     /*!< ADC DMA transfer enable */
-#define ADC_CFGR1_DMACFG_Pos           (1U)
-#define ADC_CFGR1_DMACFG_Msk           (0x1UL << ADC_CFGR1_DMACFG_Pos)         /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG               ADC_CFGR1_DMACFG_Msk                    /*!< ADC DMA transfer configuration */
-
-#define ADC_CFGR1_SCANDIR_Pos          (2U)
-#define ADC_CFGR1_SCANDIR_Msk          (0x1UL << ADC_CFGR1_SCANDIR_Pos)        /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR              ADC_CFGR1_SCANDIR_Msk                   /*!< ADC group regular sequencer scan direction */
-
-#define ADC_CFGR1_RES_Pos              (3U)
-#define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000018 */
-#define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
-#define ADC_CFGR1_RES_0                (0x1UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1                (0x2UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000010 */
-
-#define ADC_CFGR1_ALIGN_Pos            (5U)
-#define ADC_CFGR1_ALIGN_Msk            (0x1UL << ADC_CFGR1_ALIGN_Pos)          /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN                ADC_CFGR1_ALIGN_Msk                     /*!< ADC data alignement */
-
-#define ADC_CFGR1_EXTSEL_Pos           (6U)
-#define ADC_CFGR1_EXTSEL_Msk           (0x7UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
-#define ADC_CFGR1_EXTSEL_0             (0x1UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1             (0x2UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2             (0x4UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000100 */
-
-#define ADC_CFGR1_EXTEN_Pos            (10U)
-#define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
-#define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */
-
-#define ADC_CFGR1_OVRMOD_Pos           (12U)
-#define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
-#define ADC_CFGR1_CONT_Pos             (13U)
-#define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
-#define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
-#define ADC_CFGR1_WAIT_Pos             (14U)
-#define ADC_CFGR1_WAIT_Msk             (0x1UL << ADC_CFGR1_WAIT_Pos)           /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT                 ADC_CFGR1_WAIT_Msk                      /*!< ADC low power auto wait */
-#define ADC_CFGR1_AUTOFF_Pos           (15U)
-#define ADC_CFGR1_AUTOFF_Msk           (0x1UL << ADC_CFGR1_AUTOFF_Pos)         /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF               ADC_CFGR1_AUTOFF_Msk                    /*!< ADC low power auto power off */
-#define ADC_CFGR1_DISCEN_Pos           (16U)
-#define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CFGR1_CHSELRMOD_Pos        (21U)
-#define ADC_CFGR1_CHSELRMOD_Msk        (0x1UL << ADC_CFGR1_CHSELRMOD_Pos)      /*!< 0x00200000 */
-#define ADC_CFGR1_CHSELRMOD            ADC_CFGR1_CHSELRMOD_Msk                 /*!< ADC group regular sequencer mode */
-
-#define ADC_CFGR1_AWD1SGL_Pos          (22U)
-#define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
-#define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CFGR1_AWD1EN_Pos           (23U)
-#define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
-#define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CFGR1_AWD1CH_Pos           (26U)
-#define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
-#define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
-#define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
-#define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
-#define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
-#define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */
-
-/********************  Bit definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_OVSE_Pos             (0U)
-#define ADC_CFGR2_OVSE_Msk             (0x1UL << ADC_CFGR2_OVSE_Pos)           /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE                 ADC_CFGR2_OVSE_Msk                      /*!< ADC oversampler enable on scope ADC group regular */
-
-#define ADC_CFGR2_OVSR_Pos             (2U)
-#define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
-#define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
-
-#define ADC_CFGR2_OVSS_Pos             (5U)
-#define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
-#define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
-
-#define ADC_CFGR2_TOVS_Pos             (9U)
-#define ADC_CFGR2_TOVS_Msk             (0x1UL << ADC_CFGR2_TOVS_Pos)           /*!< 0x00000200 */
-#define ADC_CFGR2_TOVS                 ADC_CFGR2_TOVS_Msk                      /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
-
-#define ADC_CFGR2_LFTRIG_Pos           (29U)
-#define ADC_CFGR2_LFTRIG_Msk           (0x1UL << ADC_CFGR2_LFTRIG_Pos)         /*!< 0x20000000 */
-#define ADC_CFGR2_LFTRIG               ADC_CFGR2_LFTRIG_Msk                    /*!< ADC low frequency trigger mode */
-
-#define ADC_CFGR2_CKMODE_Pos           (30U)
-#define ADC_CFGR2_CKMODE_Msk           (0x3UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE               ADC_CFGR2_CKMODE_Msk                    /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
-#define ADC_CFGR2_CKMODE_1             (0x2UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x80000000 */
-#define ADC_CFGR2_CKMODE_0             (0x1UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x40000000 */
-
-/********************  Bit definition for ADC_SMPR register  ******************/
-#define ADC_SMPR_SMP1_Pos              (0U)
-#define ADC_SMPR_SMP1_Msk              (0x7UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000007 */
-#define ADC_SMPR_SMP1                  ADC_SMPR_SMP1_Msk                       /*!< ADC group of channels sampling time 1 */
-#define ADC_SMPR_SMP1_0                (0x1UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000001 */
-#define ADC_SMPR_SMP1_1                (0x2UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000002 */
-#define ADC_SMPR_SMP1_2                (0x4UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000004 */
-
-#define ADC_SMPR_SMP2_Pos              (4U)
-#define ADC_SMPR_SMP2_Msk              (0x7UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000070 */
-#define ADC_SMPR_SMP2                  ADC_SMPR_SMP2_Msk                       /*!< ADC group of channels sampling time 2 */
-#define ADC_SMPR_SMP2_0                (0x1UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000010 */
-#define ADC_SMPR_SMP2_1                (0x2UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000020 */
-#define ADC_SMPR_SMP2_2                (0x4UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000040 */
-
-#define ADC_SMPR_SMPSEL_Pos            (8U)
-#define ADC_SMPR_SMPSEL_Msk            (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos)      /*!< 0x03FFFF00 */
-#define ADC_SMPR_SMPSEL                ADC_SMPR_SMPSEL_Msk                     /*!< ADC all channels sampling time selection */
-#define ADC_SMPR_SMPSEL0_Pos           (8U)
-#define ADC_SMPR_SMPSEL0_Msk           (0x1UL << ADC_SMPR_SMPSEL0_Pos)         /*!< 0x00000100 */
-#define ADC_SMPR_SMPSEL0               ADC_SMPR_SMPSEL0_Msk                    /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR_SMPSEL1_Pos           (9U)
-#define ADC_SMPR_SMPSEL1_Msk           (0x1UL << ADC_SMPR_SMPSEL1_Pos)         /*!< 0x00000200 */
-#define ADC_SMPR_SMPSEL1               ADC_SMPR_SMPSEL1_Msk                    /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR_SMPSEL2_Pos           (10U)
-#define ADC_SMPR_SMPSEL2_Msk           (0x1UL << ADC_SMPR_SMPSEL2_Pos)         /*!< 0x00000400 */
-#define ADC_SMPR_SMPSEL2               ADC_SMPR_SMPSEL2_Msk                    /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR_SMPSEL3_Pos           (11U)
-#define ADC_SMPR_SMPSEL3_Msk           (0x1UL << ADC_SMPR_SMPSEL3_Pos)         /*!< 0x00000800 */
-#define ADC_SMPR_SMPSEL3               ADC_SMPR_SMPSEL3_Msk                    /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR_SMPSEL4_Pos           (12U)
-#define ADC_SMPR_SMPSEL4_Msk           (0x1UL << ADC_SMPR_SMPSEL4_Pos)         /*!< 0x00001000 */
-#define ADC_SMPR_SMPSEL4               ADC_SMPR_SMPSEL4_Msk                    /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR_SMPSEL5_Pos           (13U)
-#define ADC_SMPR_SMPSEL5_Msk           (0x1UL << ADC_SMPR_SMPSEL5_Pos)         /*!< 0x00002000 */
-#define ADC_SMPR_SMPSEL5               ADC_SMPR_SMPSEL5_Msk                    /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR_SMPSEL6_Pos           (14U)
-#define ADC_SMPR_SMPSEL6_Msk           (0x1UL << ADC_SMPR_SMPSEL6_Pos)         /*!< 0x00004000 */
-#define ADC_SMPR_SMPSEL6               ADC_SMPR_SMPSEL6_Msk                    /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR_SMPSEL7_Pos           (15U)
-#define ADC_SMPR_SMPSEL7_Msk           (0x1UL << ADC_SMPR_SMPSEL7_Pos)         /*!< 0x00008000 */
-#define ADC_SMPR_SMPSEL7               ADC_SMPR_SMPSEL7_Msk                    /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR_SMPSEL8_Pos           (16U)
-#define ADC_SMPR_SMPSEL8_Msk           (0x1UL << ADC_SMPR_SMPSEL8_Pos)         /*!< 0x00010000 */
-#define ADC_SMPR_SMPSEL8               ADC_SMPR_SMPSEL8_Msk                    /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR_SMPSEL9_Pos           (17U)
-#define ADC_SMPR_SMPSEL9_Msk           (0x1UL << ADC_SMPR_SMPSEL9_Pos)         /*!< 0x00020000 */
-#define ADC_SMPR_SMPSEL9               ADC_SMPR_SMPSEL9_Msk                    /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR_SMPSEL10_Pos          (18U)
-#define ADC_SMPR_SMPSEL10_Msk          (0x1UL << ADC_SMPR_SMPSEL10_Pos)        /*!< 0x00040000 */
-#define ADC_SMPR_SMPSEL10              ADC_SMPR_SMPSEL10_Msk                   /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR_SMPSEL11_Pos          (19U)
-#define ADC_SMPR_SMPSEL11_Msk          (0x1UL << ADC_SMPR_SMPSEL11_Pos)        /*!< 0x00080000 */
-#define ADC_SMPR_SMPSEL11              ADC_SMPR_SMPSEL11_Msk                   /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR_SMPSEL12_Pos          (20U)
-#define ADC_SMPR_SMPSEL12_Msk          (0x1UL << ADC_SMPR_SMPSEL12_Pos)        /*!< 0x00100000 */
-#define ADC_SMPR_SMPSEL12              ADC_SMPR_SMPSEL12_Msk                   /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR_SMPSEL13_Pos          (21U)
-#define ADC_SMPR_SMPSEL13_Msk          (0x1UL << ADC_SMPR_SMPSEL13_Pos)        /*!< 0x00200000 */
-#define ADC_SMPR_SMPSEL13              ADC_SMPR_SMPSEL13_Msk                   /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR_SMPSEL14_Pos          (22U)
-#define ADC_SMPR_SMPSEL14_Msk          (0x1UL << ADC_SMPR_SMPSEL14_Pos)        /*!< 0x00400000 */
-#define ADC_SMPR_SMPSEL14              ADC_SMPR_SMPSEL14_Msk                   /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR_SMPSEL15_Pos          (23U)
-#define ADC_SMPR_SMPSEL15_Msk          (0x1UL << ADC_SMPR_SMPSEL15_Pos)        /*!< 0x00800000 */
-#define ADC_SMPR_SMPSEL15              ADC_SMPR_SMPSEL15_Msk                   /*!< ADC channel 15 sampling time selection */
-#define ADC_SMPR_SMPSEL16_Pos          (24U)
-#define ADC_SMPR_SMPSEL16_Msk          (0x1UL << ADC_SMPR_SMPSEL16_Pos)        /*!< 0x01000000 */
-#define ADC_SMPR_SMPSEL16              ADC_SMPR_SMPSEL16_Msk                   /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR_SMPSEL17_Pos          (25U)
-#define ADC_SMPR_SMPSEL17_Msk          (0x1UL << ADC_SMPR_SMPSEL17_Pos)        /*!< 0x02000000 */
-#define ADC_SMPR_SMPSEL17              ADC_SMPR_SMPSEL17_Msk                   /*!< ADC channel 17 sampling time selection */
-
-/********************  Bit definition for ADC_TR1 register  *******************/
-#define ADC_TR1_LT1_Pos                (0U)
-#define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
-#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
-#define ADC_TR1_LT1_0                  (0x001UL << ADC_TR1_LT1_Pos)            /*!< 0x00000001 */
-#define ADC_TR1_LT1_1                  (0x002UL << ADC_TR1_LT1_Pos)            /*!< 0x00000002 */
-#define ADC_TR1_LT1_2                  (0x004UL << ADC_TR1_LT1_Pos)            /*!< 0x00000004 */
-#define ADC_TR1_LT1_3                  (0x008UL << ADC_TR1_LT1_Pos)            /*!< 0x00000008 */
-#define ADC_TR1_LT1_4                  (0x010UL << ADC_TR1_LT1_Pos)            /*!< 0x00000010 */
-#define ADC_TR1_LT1_5                  (0x020UL << ADC_TR1_LT1_Pos)            /*!< 0x00000020 */
-#define ADC_TR1_LT1_6                  (0x040UL << ADC_TR1_LT1_Pos)            /*!< 0x00000040 */
-#define ADC_TR1_LT1_7                  (0x080UL << ADC_TR1_LT1_Pos)            /*!< 0x00000080 */
-#define ADC_TR1_LT1_8                  (0x100UL << ADC_TR1_LT1_Pos)            /*!< 0x00000100 */
-#define ADC_TR1_LT1_9                  (0x200UL << ADC_TR1_LT1_Pos)            /*!< 0x00000200 */
-#define ADC_TR1_LT1_10                 (0x400UL << ADC_TR1_LT1_Pos)            /*!< 0x00000400 */
-#define ADC_TR1_LT1_11                 (0x800UL << ADC_TR1_LT1_Pos)            /*!< 0x00000800 */
-
-#define ADC_TR1_HT1_Pos                (16U)
-#define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
-#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
-#define ADC_TR1_HT1_0                  (0x001UL << ADC_TR1_HT1_Pos)            /*!< 0x00010000 */
-#define ADC_TR1_HT1_1                  (0x002UL << ADC_TR1_HT1_Pos)            /*!< 0x00020000 */
-#define ADC_TR1_HT1_2                  (0x004UL << ADC_TR1_HT1_Pos)            /*!< 0x00040000 */
-#define ADC_TR1_HT1_3                  (0x008UL << ADC_TR1_HT1_Pos)            /*!< 0x00080000 */
-#define ADC_TR1_HT1_4                  (0x010UL << ADC_TR1_HT1_Pos)            /*!< 0x00100000 */
-#define ADC_TR1_HT1_5                  (0x020UL << ADC_TR1_HT1_Pos)            /*!< 0x00200000 */
-#define ADC_TR1_HT1_6                  (0x040UL << ADC_TR1_HT1_Pos)            /*!< 0x00400000 */
-#define ADC_TR1_HT1_7                  (0x080UL << ADC_TR1_HT1_Pos)            /*!< 0x00800000 */
-#define ADC_TR1_HT1_8                  (0x100UL << ADC_TR1_HT1_Pos)            /*!< 0x01000000 */
-#define ADC_TR1_HT1_9                  (0x200UL << ADC_TR1_HT1_Pos)            /*!< 0x02000000 */
-#define ADC_TR1_HT1_10                 (0x400UL << ADC_TR1_HT1_Pos)            /*!< 0x04000000 */
-#define ADC_TR1_HT1_11                 (0x800UL << ADC_TR1_HT1_Pos)            /*!< 0x08000000 */
-
-/********************  Bit definition for ADC_TR2 register  *******************/
-#define ADC_TR2_LT2_Pos                (0U)
-#define ADC_TR2_LT2_Msk                (0xFFFUL << ADC_TR2_LT2_Pos)            /*!< 0x00000FFF */
-#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
-#define ADC_TR2_LT2_0                  (0x001UL << ADC_TR2_LT2_Pos)            /*!< 0x00000001 */
-#define ADC_TR2_LT2_1                  (0x002UL << ADC_TR2_LT2_Pos)            /*!< 0x00000002 */
-#define ADC_TR2_LT2_2                  (0x004UL << ADC_TR2_LT2_Pos)            /*!< 0x00000004 */
-#define ADC_TR2_LT2_3                  (0x008UL << ADC_TR2_LT2_Pos)            /*!< 0x00000008 */
-#define ADC_TR2_LT2_4                  (0x010UL << ADC_TR2_LT2_Pos)            /*!< 0x00000010 */
-#define ADC_TR2_LT2_5                  (0x020UL << ADC_TR2_LT2_Pos)            /*!< 0x00000020 */
-#define ADC_TR2_LT2_6                  (0x040UL << ADC_TR2_LT2_Pos)            /*!< 0x00000040 */
-#define ADC_TR2_LT2_7                  (0x080UL << ADC_TR2_LT2_Pos)            /*!< 0x00000080 */
-#define ADC_TR2_LT2_8                  (0x100UL << ADC_TR2_LT2_Pos)            /*!< 0x00000100 */
-#define ADC_TR2_LT2_9                  (0x200UL << ADC_TR2_LT2_Pos)            /*!< 0x00000200 */
-#define ADC_TR2_LT2_10                 (0x400UL << ADC_TR2_LT2_Pos)            /*!< 0x00000400 */
-#define ADC_TR2_LT2_11                 (0x800UL << ADC_TR2_LT2_Pos)            /*!< 0x00000800 */
-
-#define ADC_TR2_HT2_Pos                (16U)
-#define ADC_TR2_HT2_Msk                (0xFFFUL << ADC_TR2_HT2_Pos)            /*!< 0x0FFF0000 */
-#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
-#define ADC_TR2_HT2_0                  (0x001UL << ADC_TR2_HT2_Pos)            /*!< 0x00010000 */
-#define ADC_TR2_HT2_1                  (0x002UL << ADC_TR2_HT2_Pos)            /*!< 0x00020000 */
-#define ADC_TR2_HT2_2                  (0x004UL << ADC_TR2_HT2_Pos)            /*!< 0x00040000 */
-#define ADC_TR2_HT2_3                  (0x008UL << ADC_TR2_HT2_Pos)            /*!< 0x00080000 */
-#define ADC_TR2_HT2_4                  (0x010UL << ADC_TR2_HT2_Pos)            /*!< 0x00100000 */
-#define ADC_TR2_HT2_5                  (0x020UL << ADC_TR2_HT2_Pos)            /*!< 0x00200000 */
-#define ADC_TR2_HT2_6                  (0x040UL << ADC_TR2_HT2_Pos)            /*!< 0x00400000 */
-#define ADC_TR2_HT2_7                  (0x080UL << ADC_TR2_HT2_Pos)            /*!< 0x00800000 */
-#define ADC_TR2_HT2_8                  (0x100UL << ADC_TR2_HT2_Pos)            /*!< 0x01000000 */
-#define ADC_TR2_HT2_9                  (0x200UL << ADC_TR2_HT2_Pos)            /*!< 0x02000000 */
-#define ADC_TR2_HT2_10                 (0x400UL << ADC_TR2_HT2_Pos)            /*!< 0x04000000 */
-#define ADC_TR2_HT2_11                 (0x800UL << ADC_TR2_HT2_Pos)            /*!< 0x08000000 */
-
-/********************  Bit definition for ADC_CHSELR register  ****************/
-#define ADC_CHSELR_CHSEL_Pos           (0U)
-#define ADC_CHSELR_CHSEL_Msk           (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos)     /*!< 0x0003FFFF */
-#define ADC_CHSELR_CHSEL               ADC_CHSELR_CHSEL_Msk                    /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL17_Pos         (17U)
-#define ADC_CHSELR_CHSEL17_Msk         (0x1UL << ADC_CHSELR_CHSEL17_Pos)       /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17             ADC_CHSELR_CHSEL17_Msk                  /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL16_Pos         (16U)
-#define ADC_CHSELR_CHSEL16_Msk         (0x1UL << ADC_CHSELR_CHSEL16_Pos)       /*!< 0x00010000 */
-#define ADC_CHSELR_CHSEL16             ADC_CHSELR_CHSEL16_Msk                  /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL15_Pos         (15U)
-#define ADC_CHSELR_CHSEL15_Msk         (0x1UL << ADC_CHSELR_CHSEL15_Pos)       /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15             ADC_CHSELR_CHSEL15_Msk                  /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL14_Pos         (14U)
-#define ADC_CHSELR_CHSEL14_Msk         (0x1UL << ADC_CHSELR_CHSEL14_Pos)       /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14             ADC_CHSELR_CHSEL14_Msk                  /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL13_Pos         (13U)
-#define ADC_CHSELR_CHSEL13_Msk         (0x1UL << ADC_CHSELR_CHSEL13_Pos)       /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13             ADC_CHSELR_CHSEL13_Msk                  /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL12_Pos         (12U)
-#define ADC_CHSELR_CHSEL12_Msk         (0x1UL << ADC_CHSELR_CHSEL12_Pos)       /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12             ADC_CHSELR_CHSEL12_Msk                  /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL11_Pos         (11U)
-#define ADC_CHSELR_CHSEL11_Msk         (0x1UL << ADC_CHSELR_CHSEL11_Pos)       /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11             ADC_CHSELR_CHSEL11_Msk                  /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL10_Pos         (10U)
-#define ADC_CHSELR_CHSEL10_Msk         (0x1UL << ADC_CHSELR_CHSEL10_Pos)       /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10             ADC_CHSELR_CHSEL10_Msk                  /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL9_Pos          (9U)
-#define ADC_CHSELR_CHSEL9_Msk          (0x1UL << ADC_CHSELR_CHSEL9_Pos)        /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9              ADC_CHSELR_CHSEL9_Msk                   /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL8_Pos          (8U)
-#define ADC_CHSELR_CHSEL8_Msk          (0x1UL << ADC_CHSELR_CHSEL8_Pos)        /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8              ADC_CHSELR_CHSEL8_Msk                   /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL7_Pos          (7U)
-#define ADC_CHSELR_CHSEL7_Msk          (0x1UL << ADC_CHSELR_CHSEL7_Pos)        /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7              ADC_CHSELR_CHSEL7_Msk                   /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL6_Pos          (6U)
-#define ADC_CHSELR_CHSEL6_Msk          (0x1UL << ADC_CHSELR_CHSEL6_Pos)        /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6              ADC_CHSELR_CHSEL6_Msk                   /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL5_Pos          (5U)
-#define ADC_CHSELR_CHSEL5_Msk          (0x1UL << ADC_CHSELR_CHSEL5_Pos)        /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5              ADC_CHSELR_CHSEL5_Msk                   /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL4_Pos          (4U)
-#define ADC_CHSELR_CHSEL4_Msk          (0x1UL << ADC_CHSELR_CHSEL4_Pos)        /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4              ADC_CHSELR_CHSEL4_Msk                   /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL3_Pos          (3U)
-#define ADC_CHSELR_CHSEL3_Msk          (0x1UL << ADC_CHSELR_CHSEL3_Pos)        /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3              ADC_CHSELR_CHSEL3_Msk                   /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL2_Pos          (2U)
-#define ADC_CHSELR_CHSEL2_Msk          (0x1UL << ADC_CHSELR_CHSEL2_Pos)        /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2              ADC_CHSELR_CHSEL2_Msk                   /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL1_Pos          (1U)
-#define ADC_CHSELR_CHSEL1_Msk          (0x1UL << ADC_CHSELR_CHSEL1_Pos)        /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1              ADC_CHSELR_CHSEL1_Msk                   /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL0_Pos          (0U)
-#define ADC_CHSELR_CHSEL0_Msk          (0x1UL << ADC_CHSELR_CHSEL0_Pos)        /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0              ADC_CHSELR_CHSEL0_Msk                   /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
-
-#define ADC_CHSELR_SQ_ALL_Pos          (0U)
-#define ADC_CHSELR_SQ_ALL_Msk          (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
-#define ADC_CHSELR_SQ_ALL              ADC_CHSELR_SQ_ALL_Msk                   /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
-
-#define ADC_CHSELR_SQ8_Pos             (28U)
-#define ADC_CHSELR_SQ8_Msk             (0xFUL << ADC_CHSELR_SQ8_Pos)           /*!< 0xF0000000 */
-#define ADC_CHSELR_SQ8                 ADC_CHSELR_SQ8_Msk                      /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ8_0               (0x1UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x10000000 */
-#define ADC_CHSELR_SQ8_1               (0x2UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x20000000 */
-#define ADC_CHSELR_SQ8_2               (0x4UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x40000000 */
-#define ADC_CHSELR_SQ8_3               (0x8UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x80000000 */
-
-#define ADC_CHSELR_SQ7_Pos             (24U)
-#define ADC_CHSELR_SQ7_Msk             (0xFUL << ADC_CHSELR_SQ7_Pos)           /*!< 0x0F000000 */
-#define ADC_CHSELR_SQ7                 ADC_CHSELR_SQ7_Msk                      /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ7_0               (0x1UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x01000000 */
-#define ADC_CHSELR_SQ7_1               (0x2UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x02000000 */
-#define ADC_CHSELR_SQ7_2               (0x4UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x04000000 */
-#define ADC_CHSELR_SQ7_3               (0x8UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x08000000 */
-
-#define ADC_CHSELR_SQ6_Pos             (20U)
-#define ADC_CHSELR_SQ6_Msk             (0xFUL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00F00000 */
-#define ADC_CHSELR_SQ6                 ADC_CHSELR_SQ6_Msk                      /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ6_0               (0x1UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00100000 */
-#define ADC_CHSELR_SQ6_1               (0x2UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00200000 */
-#define ADC_CHSELR_SQ6_2               (0x4UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00400000 */
-#define ADC_CHSELR_SQ6_3               (0x8UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00800000 */
-
-#define ADC_CHSELR_SQ5_Pos             (16U)
-#define ADC_CHSELR_SQ5_Msk             (0xFUL << ADC_CHSELR_SQ5_Pos)           /*!< 0x000F0000 */
-#define ADC_CHSELR_SQ5                 ADC_CHSELR_SQ5_Msk                      /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ5_0               (0x1UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00010000 */
-#define ADC_CHSELR_SQ5_1               (0x2UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00020000 */
-#define ADC_CHSELR_SQ5_2               (0x4UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00040000 */
-#define ADC_CHSELR_SQ5_3               (0x8UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00080000 */
-
-#define ADC_CHSELR_SQ4_Pos             (12U)
-#define ADC_CHSELR_SQ4_Msk             (0xFUL << ADC_CHSELR_SQ4_Pos)           /*!< 0x0000F000 */
-#define ADC_CHSELR_SQ4                 ADC_CHSELR_SQ4_Msk                      /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ4_0               (0x1UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00001000 */
-#define ADC_CHSELR_SQ4_1               (0x2UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00002000 */
-#define ADC_CHSELR_SQ4_2               (0x4UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00004000 */
-#define ADC_CHSELR_SQ4_3               (0x8UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00008000 */
-
-#define ADC_CHSELR_SQ3_Pos             (8U)
-#define ADC_CHSELR_SQ3_Msk             (0xFUL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000F00 */
-#define ADC_CHSELR_SQ3                 ADC_CHSELR_SQ3_Msk                      /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ3_0               (0x1UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000100 */
-#define ADC_CHSELR_SQ3_1               (0x2UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000200 */
-#define ADC_CHSELR_SQ3_2               (0x4UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000400 */
-#define ADC_CHSELR_SQ3_3               (0x8UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000800 */
-
-#define ADC_CHSELR_SQ2_Pos             (4U)
-#define ADC_CHSELR_SQ2_Msk             (0xFUL << ADC_CHSELR_SQ2_Pos)           /*!< 0x000000F0 */
-#define ADC_CHSELR_SQ2                 ADC_CHSELR_SQ2_Msk                      /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ2_0               (0x1UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000010 */
-#define ADC_CHSELR_SQ2_1               (0x2UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000020 */
-#define ADC_CHSELR_SQ2_2               (0x4UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000040 */
-#define ADC_CHSELR_SQ2_3               (0x8UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000080 */
-
-#define ADC_CHSELR_SQ1_Pos             (0U)
-#define ADC_CHSELR_SQ1_Msk             (0xFUL << ADC_CHSELR_SQ1_Pos)           /*!< 0x0000000F */
-#define ADC_CHSELR_SQ1                 ADC_CHSELR_SQ1_Msk                      /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ1_0               (0x1UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000001 */
-#define ADC_CHSELR_SQ1_1               (0x2UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000002 */
-#define ADC_CHSELR_SQ1_2               (0x4UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000004 */
-#define ADC_CHSELR_SQ1_3               (0x8UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000008 */
-
-/********************  Bit definition for ADC_TR3 register  *******************/
-#define ADC_TR3_LT3_Pos                (0U)
-#define ADC_TR3_LT3_Msk                (0xFFFUL << ADC_TR3_LT3_Pos)            /*!< 0x00000FFF */
-#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
-#define ADC_TR3_LT3_0                  (0x001UL << ADC_TR3_LT3_Pos)            /*!< 0x00000001 */
-#define ADC_TR3_LT3_1                  (0x002UL << ADC_TR3_LT3_Pos)            /*!< 0x00000002 */
-#define ADC_TR3_LT3_2                  (0x004UL << ADC_TR3_LT3_Pos)            /*!< 0x00000004 */
-#define ADC_TR3_LT3_3                  (0x008UL << ADC_TR3_LT3_Pos)            /*!< 0x00000008 */
-#define ADC_TR3_LT3_4                  (0x010UL << ADC_TR3_LT3_Pos)            /*!< 0x00000010 */
-#define ADC_TR3_LT3_5                  (0x020UL << ADC_TR3_LT3_Pos)            /*!< 0x00000020 */
-#define ADC_TR3_LT3_6                  (0x040UL << ADC_TR3_LT3_Pos)            /*!< 0x00000040 */
-#define ADC_TR3_LT3_7                  (0x080UL << ADC_TR3_LT3_Pos)            /*!< 0x00000080 */
-#define ADC_TR3_LT3_8                  (0x100UL << ADC_TR3_LT3_Pos)            /*!< 0x00000100 */
-#define ADC_TR3_LT3_9                  (0x200UL << ADC_TR3_LT3_Pos)            /*!< 0x00000200 */
-#define ADC_TR3_LT3_10                 (0x400UL << ADC_TR3_LT3_Pos)            /*!< 0x00000400 */
-#define ADC_TR3_LT3_11                 (0x800UL << ADC_TR3_LT3_Pos)            /*!< 0x00000800 */
-
-#define ADC_TR3_HT3_Pos                (16U)
-#define ADC_TR3_HT3_Msk                (0xFFFUL << ADC_TR3_HT3_Pos)            /*!< 0x0FFF0000 */
-#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
-#define ADC_TR3_HT3_0                  (0x001UL << ADC_TR3_HT3_Pos)            /*!< 0x00010000 */
-#define ADC_TR3_HT3_1                  (0x002UL << ADC_TR3_HT3_Pos)            /*!< 0x00020000 */
-#define ADC_TR3_HT3_2                  (0x004UL << ADC_TR3_HT3_Pos)            /*!< 0x00040000 */
-#define ADC_TR3_HT3_3                  (0x008UL << ADC_TR3_HT3_Pos)            /*!< 0x00080000 */
-#define ADC_TR3_HT3_4                  (0x010UL << ADC_TR3_HT3_Pos)            /*!< 0x00100000 */
-#define ADC_TR3_HT3_5                  (0x020UL << ADC_TR3_HT3_Pos)            /*!< 0x00200000 */
-#define ADC_TR3_HT3_6                  (0x040UL << ADC_TR3_HT3_Pos)            /*!< 0x00400000 */
-#define ADC_TR3_HT3_7                  (0x080UL << ADC_TR3_HT3_Pos)            /*!< 0x00800000 */
-#define ADC_TR3_HT3_8                  (0x100UL << ADC_TR3_HT3_Pos)            /*!< 0x01000000 */
-#define ADC_TR3_HT3_9                  (0x200UL << ADC_TR3_HT3_Pos)            /*!< 0x02000000 */
-#define ADC_TR3_HT3_10                 (0x400UL << ADC_TR3_HT3_Pos)            /*!< 0x04000000 */
-#define ADC_TR3_HT3_11                 (0x800UL << ADC_TR3_HT3_Pos)            /*!< 0x08000000 */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                (0U)
-#define ADC_DR_DATA_Msk                (0xFFFFUL << ADC_DR_DATA_Pos)           /*!< 0x0000FFFF */
-#define ADC_DR_DATA                    ADC_DR_DATA_Msk                         /*!< ADC group regular conversion data */
-#define ADC_DR_DATA_0                  (0x0001UL << ADC_DR_DATA_Pos)           /*!< 0x00000001 */
-#define ADC_DR_DATA_1                  (0x0002UL << ADC_DR_DATA_Pos)           /*!< 0x00000002 */
-#define ADC_DR_DATA_2                  (0x0004UL << ADC_DR_DATA_Pos)           /*!< 0x00000004 */
-#define ADC_DR_DATA_3                  (0x0008UL << ADC_DR_DATA_Pos)           /*!< 0x00000008 */
-#define ADC_DR_DATA_4                  (0x0010UL << ADC_DR_DATA_Pos)           /*!< 0x00000010 */
-#define ADC_DR_DATA_5                  (0x0020UL << ADC_DR_DATA_Pos)           /*!< 0x00000020 */
-#define ADC_DR_DATA_6                  (0x0040UL << ADC_DR_DATA_Pos)           /*!< 0x00000040 */
-#define ADC_DR_DATA_7                  (0x0080UL << ADC_DR_DATA_Pos)           /*!< 0x00000080 */
-#define ADC_DR_DATA_8                  (0x0100UL << ADC_DR_DATA_Pos)           /*!< 0x00000100 */
-#define ADC_DR_DATA_9                  (0x0200UL << ADC_DR_DATA_Pos)           /*!< 0x00000200 */
-#define ADC_DR_DATA_10                 (0x0400UL << ADC_DR_DATA_Pos)           /*!< 0x00000400 */
-#define ADC_DR_DATA_11                 (0x0800UL << ADC_DR_DATA_Pos)           /*!< 0x00000800 */
-#define ADC_DR_DATA_12                 (0x1000UL << ADC_DR_DATA_Pos)           /*!< 0x00001000 */
-#define ADC_DR_DATA_13                 (0x2000UL << ADC_DR_DATA_Pos)           /*!< 0x00002000 */
-#define ADC_DR_DATA_14                 (0x4000UL << ADC_DR_DATA_Pos)           /*!< 0x00004000 */
-#define ADC_DR_DATA_15                 (0x8000UL << ADC_DR_DATA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for ADC_AWD2CR register  ****************/
-#define ADC_AWD2CR_AWD2CH_Pos          (0U)
-#define ADC_AWD2CR_AWD2CH_Msk          (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0003FFFF */
-#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
-#define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
-#define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
-#define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
-#define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
-#define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
-#define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
-#define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
-#define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
-#define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
-#define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
-#define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
-#define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
-#define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
-#define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
-#define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
-#define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
-#define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
-#define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
-
-/********************  Bit definition for ADC_AWD3CR register  ****************/
-#define ADC_AWD3CR_AWD3CH_Pos          (0U)
-#define ADC_AWD3CR_AWD3CH_Msk          (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0003FFFF */
-#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
-#define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
-#define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
-#define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
-#define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
-#define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
-#define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
-#define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
-#define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
-#define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
-#define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
-#define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
-#define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
-#define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
-#define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
-#define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
-#define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
-#define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
-#define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
-
-/********************  Bit definition for ADC_CALFACT register  ***************/
-#define ADC_CALFACT_CALFACT_Pos        (0U)
-#define ADC_CALFACT_CALFACT_Msk        (0x7FUL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT            ADC_CALFACT_CALFACT_Msk                 /*!< ADC calibration factor in single-ended mode */
-#define ADC_CALFACT_CALFACT_0          (0x01UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000001 */
-#define ADC_CALFACT_CALFACT_1          (0x02UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000002 */
-#define ADC_CALFACT_CALFACT_2          (0x04UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000004 */
-#define ADC_CALFACT_CALFACT_3          (0x08UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000008 */
-#define ADC_CALFACT_CALFACT_4          (0x10UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000010 */
-#define ADC_CALFACT_CALFACT_5          (0x20UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000020 */
-#define ADC_CALFACT_CALFACT_6          (0x40UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000040 */
-
-/*************************  ADC Common registers  *****************************/
-/********************  Bit definition for ADC_CCR register  *******************/
-#define ADC_CCR_PRESC_Pos              (18U)
-#define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
-#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
-#define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
-
-#define ADC_CCR_VREFEN_Pos             (22U)
-#define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
-#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
-#define ADC_CCR_TSEN_Pos               (23U)
-#define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
-#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
-#define ADC_CCR_VBATEN_Pos             (24U)
-#define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
-#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/**********************  Bit definition for COMP_CSR register  ****************/
-#define COMP_CSR_EN_Pos            (0U)
-#define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
-#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
-
-#define COMP_CSR_PWRMODE_Pos       (2U)
-#define COMP_CSR_PWRMODE_Msk       (0x3UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x0000000C */
-#define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
-#define COMP_CSR_PWRMODE_0         (0x1UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000004 */
-#define COMP_CSR_PWRMODE_1         (0x2UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000008 */
-
-#define COMP_CSR_INMSEL_Pos        (4U)
-#define COMP_CSR_INMSEL_Msk        (0x7UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */
-#define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
-#define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
-#define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
-#define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
-
-#define COMP_CSR_INPSEL_Pos        (7U)
-#define COMP_CSR_INPSEL_Msk        (0x3UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000180 */
-#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
-#define COMP_CSR_INPSEL_0          (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000080 */
-#define COMP_CSR_INPSEL_1          (0x2UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
-
-#define COMP_CSR_WINMODE_Pos       (9U)
-#define COMP_CSR_WINMODE_Msk       (0x1UL << COMP_CSR_WINMODE_Pos)             /*!< 0x00000200 */
-#define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_POLARITY_Pos      (15U)
-#define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
-#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
-
-#define COMP_CSR_HYST_Pos          (16U)
-#define COMP_CSR_HYST_Msk          (0x3UL << COMP_CSR_HYST_Pos)                /*!< 0x00030000 */
-#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
-#define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
-#define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
-
-#define COMP_CSR_BLANKING_Pos      (18U)
-#define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x001C0000 */
-#define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
-#define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00040000 */
-#define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */
-#define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */
-
-#define COMP_CSR_BRGEN_Pos         (22U)
-#define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */
-#define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
-#define COMP_CSR_SCALEN_Pos        (23U)
-#define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */
-#define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
-
-#define COMP_CSR_INMESEL_Pos       (25U)
-#define COMP_CSR_INMESEL_Msk       (0x3UL << COMP_CSR_INMESEL_Pos)             /*!< 0x06000000 */
-#define COMP_CSR_INMESEL           COMP_CSR_INMESEL_Msk                        /*!< Comparator input minus extended selection */
-#define COMP_CSR_INMESEL_0         (0x1UL << COMP_CSR_INMESEL_Pos)             /*!< 0x02000000 */
-#define COMP_CSR_INMESEL_1         (0x2UL << COMP_CSR_INMESEL_Pos)             /*!< 0x04000000 */
-
-#define COMP_CSR_VALUE_Pos         (30U)
-#define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
-#define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
-
-#define COMP_CSR_LOCK_Pos          (31U)
-#define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
-#define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)
-#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
-#define DAC_CR_TEN1_Pos             (1U)
-#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (2U)
-#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000004 */
-#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */
-#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */
-#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)
-#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)
-#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)
-#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)
-#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
-#define DAC_CR_CEN1_Pos             (14U)
-#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
-#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos    (0U)
-#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos    (4U)
-#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos     (0U)
-#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos       (0U)
-#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)
-#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_CAL_FLAG1_Pos        (14U)
-#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
-#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
-#define DAC_SR_BWST1_Pos            (15U)
-#define DAC_SR_BWST1_Msk            (0x1UL << DAC_SR_BWST1_Pos)                /*!< 0x00008000 */
-#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
-
-/*******************  Bit definition for DAC_CCR register  ********************/
-#define DAC_CCR_OTRIM1_Pos          (0U)
-#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
-#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
-
-/*******************  Bit definition for DAC_MCR register  *******************/
-#define DAC_MCR_MODE1_Pos           (0U)
-#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
-#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
-#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */
-#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */
-#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */
-
-/******************  Bit definition for DAC_SHSR1 register  ******************/
-#define DAC_SHSR1_TSAMPLE1_Pos      (0U)
-#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
-#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
-
-/******************  Bit definition for DAC_SHHR register  ******************/
-#define DAC_SHHR_THOLD1_Pos         (0U)
-#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
-#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
-
-/******************  Bit definition for DAC_SHRR register  ******************/
-#define DAC_SHRR_TREFRESH1_Pos      (0U)
-#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
-#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-#define LPTIM_ISR_UE_Pos            (7U)
-#define LPTIM_ISR_UE_Msk            (0x1UL << LPTIM_ISR_UE_Pos)                /*!< 0x00000080 */
-#define LPTIM_ISR_UE                LPTIM_ISR_UE_Msk                           /*!< Update event occurrence */
-#define LPTIM_ISR_REPOK_Pos         (8U)
-#define LPTIM_ISR_REPOK_Msk         (0x1UL << LPTIM_ISR_REPOK_Pos)              /*!< 0x00000100 */
-#define LPTIM_ISR_REPOK             LPTIM_ISR_REPOK_Msk                         /*!< Repetition register update OK */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-#define LPTIM_ICR_UECF_Pos          (7U)
-#define LPTIM_ICR_UECF_Msk          (0x1UL << LPTIM_ICR_UECF_Pos)              /*!< 0x00000080 */
-#define LPTIM_ICR_UECF              LPTIM_ICR_UECF_Msk                         /*!< Update event Clear Flag */
-#define LPTIM_ICR_REPOKCF_Pos       (8U)
-#define LPTIM_ICR_REPOKCF_Msk       (0x1UL << LPTIM_ICR_REPOKCF_Pos)           /*!< 0x00000100 */
-#define LPTIM_ICR_REPOKCF           LPTIM_ICR_REPOKCF_Msk                      /*!< Repetition register update OK Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-#define LPTIM_IER_UEIE_Pos          (7U)
-#define LPTIM_IER_UEIE_Msk          (0x1UL << LPTIM_IER_UEIE_Pos)              /*!< 0x00000080 */
-#define LPTIM_IER_UEIE              LPTIM_IER_UEIE_Msk                         /*!< Update event Interrupt Enable */
-#define LPTIM_IER_REPOKIE_Pos       (8U)
-#define LPTIM_IER_REPOKIE_Msk       (0x1UL << LPTIM_IER_REPOKIE_Pos)           /*!< 0x00000100 */
-#define LPTIM_IER_REPOKIE           LPTIM_IER_REPOKIE_Msk                      /*!< Repetition register update OK Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-#define LPTIM_CR_COUNTRST_Pos       (3U)
-#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
-#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
-#define LPTIM_CR_RSTARE_Pos         (4U)
-#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
-#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************  Bit definition for LPTIM_OR register  ********************/
-#define LPTIM_OR_OR_Pos             (0U)
-#define LPTIM_OR_OR_Msk             (0x3UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000003 */
-#define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
-#define LPTIM_OR_OR_0               (0x1UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000001 */
-#define LPTIM_OR_OR_1               (0x2UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000002 */
-
-/******************  Bit definition for LPTIM_RCR register  *******************/
-#define LPTIM_RCR_REP_Pos           (0U)
-#define LPTIM_RCR_REP_Msk           (0xFFUL << LPTIM_RCR_REP_Pos)              /*!< 0x000000FF */
-#define LPTIM_RCR_REP               LPTIM_RCR_REP_Msk                          /*!<Repetition Counter Value */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos             (0U)
-#define USART_CR1_UE_Msk             (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                 USART_CR1_UE_Msk                          /*!< USART Enable */
-#define USART_CR1_UESM_Pos           (1U)
-#define USART_CR1_UESM_Msk           (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM               USART_CR1_UESM_Msk                        /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos             (2U)
-#define USART_CR1_RE_Msk             (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                 USART_CR1_RE_Msk                          /*!< Receiver Enable */
-#define USART_CR1_TE_Pos             (3U)
-#define USART_CR1_TE_Msk             (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                 USART_CR1_TE_Msk                          /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos         (4U)
-#define USART_CR1_IDLEIE_Msk         (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE             USART_CR1_IDLEIE_Msk                      /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_RXFNEIE_Pos   (5U)
-#define USART_CR1_RXNEIE_RXFNEIE_Msk   (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
-#define USART_CR1_RXNEIE_RXFNEIE       USART_CR1_RXNEIE_RXFNEIE_Msk            /*!< RXNE/RXFIFO not empty Interrupt Enable */
-#define USART_CR1_TCIE_Pos           (6U)
-#define USART_CR1_TCIE_Msk           (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE               USART_CR1_TCIE_Msk                        /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_TXFNFIE_Pos  (7U)
-#define USART_CR1_TXEIE_TXFNFIE_Msk   (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)   /*!< 0x00000080 */
-#define USART_CR1_TXEIE_TXFNFIE       USART_CR1_TXEIE_TXFNFIE_Msk              /*!< TXE/TXFIFO not full Interrupt Enable */
-#define USART_CR1_PEIE_Pos           (8U)
-#define USART_CR1_PEIE_Msk           (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE               USART_CR1_PEIE_Msk                        /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos             (9U)
-#define USART_CR1_PS_Msk             (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                 USART_CR1_PS_Msk                          /*!< Parity Selection */
-#define USART_CR1_PCE_Pos            (10U)
-#define USART_CR1_PCE_Msk            (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                USART_CR1_PCE_Msk                         /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos           (11U)
-#define USART_CR1_WAKE_Msk           (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE               USART_CR1_WAKE_Msk                        /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos              (12U)
-#define USART_CR1_M_Msk              (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                  USART_CR1_M_Msk                           /*!< Word length */
-#define USART_CR1_M0_Pos             (12U)
-#define USART_CR1_M0_Msk             (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                 USART_CR1_M0_Msk                          /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos            (13U)
-#define USART_CR1_MME_Msk            (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                USART_CR1_MME_Msk                         /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos           (14U)
-#define USART_CR1_CMIE_Msk           (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE               USART_CR1_CMIE_Msk                        /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos          (15U)
-#define USART_CR1_OVER8_Msk          (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8              USART_CR1_OVER8_Msk                       /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos           (16U)
-#define USART_CR1_DEDT_Msk           (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT               USART_CR1_DEDT_Msk                        /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0             (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1             (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2             (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3             (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4             (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos           (21U)
-#define USART_CR1_DEAT_Msk           (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT               USART_CR1_DEAT_Msk                        /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0             (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1             (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2             (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3             (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4             (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos          (26U)
-#define USART_CR1_RTOIE_Msk          (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE              USART_CR1_RTOIE_Msk                       /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos          (27U)
-#define USART_CR1_EOBIE_Msk          (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE              USART_CR1_EOBIE_Msk                       /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos             (28U)
-#define USART_CR1_M1_Msk             (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                 USART_CR1_M1_Msk                          /*!< Word length - Bit 1 */
-#define USART_CR1_FIFOEN_Pos         (29U)
-#define USART_CR1_FIFOEN_Msk         (0x1UL << USART_CR1_FIFOEN_Pos)           /*!< 0x20000000 */
-#define USART_CR1_FIFOEN             USART_CR1_FIFOEN_Msk                      /*!< FIFO mode enable */
-#define USART_CR1_TXFEIE_Pos         (30U)
-#define USART_CR1_TXFEIE_Msk         (0x1UL << USART_CR1_TXFEIE_Pos)           /*!< 0x40000000 */
-#define USART_CR1_TXFEIE             USART_CR1_TXFEIE_Msk                      /*!< TXFIFO empty interrupt enable */
-#define USART_CR1_RXFFIE_Pos         (31U)
-#define USART_CR1_RXFFIE_Msk         (0x1UL << USART_CR1_RXFFIE_Pos)           /*!< 0x80000000 */
-#define USART_CR1_RXFFIE             USART_CR1_RXFFIE_Msk                      /*!< RXFIFO Full interrupt enable */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_SLVEN_Pos          (0U)
-#define USART_CR2_SLVEN_Msk          (0x1UL << USART_CR2_SLVEN_Pos)            /*!< 0x00000001 */
-#define USART_CR2_SLVEN              USART_CR2_SLVEN_Msk                       /*!< Synchronous Slave mode enable */
-#define USART_CR2_DIS_NSS_Pos        (3U)
-#define USART_CR2_DIS_NSS_Msk        (0x1UL << USART_CR2_DIS_NSS_Pos)          /*!< 0x00000008 */
-#define USART_CR2_DIS_NSS            USART_CR2_DIS_NSS_Msk                     /*!< NSS input pin disable for SPI slave selection */
-#define USART_CR2_ADDM7_Pos          (4U)
-#define USART_CR2_ADDM7_Msk          (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7              USART_CR2_ADDM7_Msk                       /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos           (5U)
-#define USART_CR2_LBDL_Msk           (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL               USART_CR2_LBDL_Msk                        /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos          (6U)
-#define USART_CR2_LBDIE_Msk          (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE              USART_CR2_LBDIE_Msk                       /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos           (8U)
-#define USART_CR2_LBCL_Msk           (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL               USART_CR2_LBCL_Msk                        /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos           (9U)
-#define USART_CR2_CPHA_Msk           (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA               USART_CR2_CPHA_Msk                        /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos           (10U)
-#define USART_CR2_CPOL_Msk           (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL               USART_CR2_CPOL_Msk                        /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos          (11U)
-#define USART_CR2_CLKEN_Msk          (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN              USART_CR2_CLKEN_Msk                       /*!< Clock Enable */
-#define USART_CR2_STOP_Pos           (12U)
-#define USART_CR2_STOP_Msk           (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP               USART_CR2_STOP_Msk                        /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0             (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1             (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos          (14U)
-#define USART_CR2_LINEN_Msk          (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN              USART_CR2_LINEN_Msk                       /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos           (15U)
-#define USART_CR2_SWAP_Msk           (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP               USART_CR2_SWAP_Msk                        /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos          (16U)
-#define USART_CR2_RXINV_Msk          (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV              USART_CR2_RXINV_Msk                       /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos          (17U)
-#define USART_CR2_TXINV_Msk          (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV              USART_CR2_TXINV_Msk                       /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos        (18U)
-#define USART_CR2_DATAINV_Msk        (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV            USART_CR2_DATAINV_Msk                     /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos       (19U)
-#define USART_CR2_MSBFIRST_Msk       (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST           USART_CR2_MSBFIRST_Msk                    /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos          (20U)
-#define USART_CR2_ABREN_Msk          (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN              USART_CR2_ABREN_Msk                       /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos        (21U)
-#define USART_CR2_ABRMODE_Msk        (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE            USART_CR2_ABRMODE_Msk                     /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0          (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1          (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos          (23U)
-#define USART_CR2_RTOEN_Msk          (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN              USART_CR2_RTOEN_Msk                       /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos            (24U)
-#define USART_CR2_ADD_Msk            (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                USART_CR2_ADD_Msk                         /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos            (0U)
-#define USART_CR3_EIE_Msk            (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                USART_CR3_EIE_Msk                         /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos           (1U)
-#define USART_CR3_IREN_Msk           (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN               USART_CR3_IREN_Msk                        /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos           (2U)
-#define USART_CR3_IRLP_Msk           (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP               USART_CR3_IRLP_Msk                        /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos          (3U)
-#define USART_CR3_HDSEL_Msk          (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL              USART_CR3_HDSEL_Msk                       /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos           (4U)
-#define USART_CR3_NACK_Msk           (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK               USART_CR3_NACK_Msk                        /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos           (5U)
-#define USART_CR3_SCEN_Msk           (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN               USART_CR3_SCEN_Msk                        /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos           (6U)
-#define USART_CR3_DMAR_Msk           (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR               USART_CR3_DMAR_Msk                        /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos           (7U)
-#define USART_CR3_DMAT_Msk           (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT               USART_CR3_DMAT_Msk                        /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos           (8U)
-#define USART_CR3_RTSE_Msk           (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE               USART_CR3_RTSE_Msk                        /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos           (9U)
-#define USART_CR3_CTSE_Msk           (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE               USART_CR3_CTSE_Msk                        /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos          (10U)
-#define USART_CR3_CTSIE_Msk          (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE              USART_CR3_CTSIE_Msk                       /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos         (11U)
-#define USART_CR3_ONEBIT_Msk         (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT             USART_CR3_ONEBIT_Msk                      /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos         (12U)
-#define USART_CR3_OVRDIS_Msk         (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS             USART_CR3_OVRDIS_Msk                      /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos           (13U)
-#define USART_CR3_DDRE_Msk           (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE               USART_CR3_DDRE_Msk                        /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos            (14U)
-#define USART_CR3_DEM_Msk            (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                USART_CR3_DEM_Msk                         /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos            (15U)
-#define USART_CR3_DEP_Msk            (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                USART_CR3_DEP_Msk                         /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos        (17U)
-#define USART_CR3_SCARCNT_Msk        (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT            USART_CR3_SCARCNT_Msk                     /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0          (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1          (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2          (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos            (20U)
-#define USART_CR3_WUS_Msk            (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                USART_CR3_WUS_Msk                         /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0              (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1              (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos          (22U)
-#define USART_CR3_WUFIE_Msk          (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE              USART_CR3_WUFIE_Msk                       /*!< Wake Up Interrupt Enable */
-#define USART_CR3_TXFTIE_Pos         (23U)
-#define USART_CR3_TXFTIE_Msk         (0x1UL << USART_CR3_TXFTIE_Pos)           /*!< 0x00800000 */
-#define USART_CR3_TXFTIE             USART_CR3_TXFTIE_Msk                      /*!< TXFIFO threshold interrupt enable */
-#define USART_CR3_TCBGTIE_Pos        (24U)
-#define USART_CR3_TCBGTIE_Msk        (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
-#define USART_CR3_TCBGTIE            USART_CR3_TCBGTIE_Msk                     /*!< Transmission Complete Before Guard Time Interrupt Enable */
-#define USART_CR3_RXFTCFG_Pos        (25U)
-#define USART_CR3_RXFTCFG_Msk        (0x7UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x0E000000 */
-#define USART_CR3_RXFTCFG            USART_CR3_RXFTCFG_Msk                     /*!< RXFIFO FIFO threshold configuration */
-#define USART_CR3_RXFTCFG_0          (0x1UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x02000000 */
-#define USART_CR3_RXFTCFG_1          (0x2UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x04000000 */
-#define USART_CR3_RXFTCFG_2          (0x4UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x08000000 */
-#define USART_CR3_RXFTIE_Pos         (28U)
-#define USART_CR3_RXFTIE_Msk         (0x1UL << USART_CR3_RXFTIE_Pos)           /*!< 0x10000000 */
-#define USART_CR3_RXFTIE             USART_CR3_RXFTIE_Msk                      /*!< RXFIFO threshold interrupt enable */
-#define USART_CR3_TXFTCFG_Pos        (29U)
-#define USART_CR3_TXFTCFG_Msk        (0x7UL << USART_CR3_TXFTCFG_Pos)          /*!< 0xE0000000 */
-#define USART_CR3_TXFTCFG            USART_CR3_TXFTCFG_Msk                     /*!< TXFIFO threshold configuration */
-#define USART_CR3_TXFTCFG_0          (0x1UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x20000000 */
-#define USART_CR3_TXFTCFG_1          (0x2UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x40000000 */
-#define USART_CR3_TXFTCFG_2          (0x4UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x80000000 */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_BRR                ((uint16_t)0xFFFF)                        /*!< USART  Baud rate register [15:0] */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos           (0U)
-#define USART_GTPR_PSC_Msk           (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC               USART_GTPR_PSC_Msk                        /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos            (8U)
-#define USART_GTPR_GT_Msk            (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                USART_GTPR_GT_Msk                         /*!< GT[7:0] bits (Guard time value) */
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos           (0U)
-#define USART_RTOR_RTO_Msk           (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO               USART_RTOR_RTO_Msk                        /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos          (24U)
-#define USART_RTOR_BLEN_Msk          (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN              USART_RTOR_BLEN_Msk                       /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ        ((uint16_t)0x0001)                              /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ        ((uint16_t)0x0002)                              /*!< Send Break Request */
-#define USART_RQR_MMRQ         ((uint16_t)0x0004)                              /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ        ((uint16_t)0x0008)                              /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ        ((uint16_t)0x0010)                              /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos             (0U)
-#define USART_ISR_PE_Msk             (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                 USART_ISR_PE_Msk                          /*!< Parity Error */
-#define USART_ISR_FE_Pos             (1U)
-#define USART_ISR_FE_Msk             (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                 USART_ISR_FE_Msk                          /*!< Framing Error */
-#define USART_ISR_NE_Pos             (2U)
-#define USART_ISR_NE_Msk             (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                 USART_ISR_NE_Msk                          /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos            (3U)
-#define USART_ISR_ORE_Msk            (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                USART_ISR_ORE_Msk                         /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos           (4U)
-#define USART_ISR_IDLE_Msk           (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE               USART_ISR_IDLE_Msk                        /*!< IDLE line detected */
-#define USART_ISR_RXNE_RXFNE_Pos     (5U)
-#define USART_ISR_RXNE_RXFNE_Msk     (0x1UL << USART_ISR_RXNE_RXFNE_Pos)      /*!< 0x00000020 */
-#define USART_ISR_RXNE_RXFNE         USART_ISR_RXNE_RXFNE_Msk                /*!< Read Data Register Not Empty/RXFIFO Not Empty */
-#define USART_ISR_TC_Pos             (6U)
-#define USART_ISR_TC_Msk             (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                 USART_ISR_TC_Msk                          /*!< Transmission Complete */
-#define USART_ISR_TXE_TXFNF_Pos      (7U)
-#define USART_ISR_TXE_TXFNF_Msk      (0x1UL << USART_ISR_TXE_TXFNF_Pos)       /*!< 0x00000080 */
-#define USART_ISR_TXE_TXFNF          USART_ISR_TXE_TXFNF_Msk                  /*!< Transmit Data Register Empty/TXFIFO Not Full */
-#define USART_ISR_LBDF_Pos           (8U)
-#define USART_ISR_LBDF_Msk           (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF               USART_ISR_LBDF_Msk                        /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos          (9U)
-#define USART_ISR_CTSIF_Msk          (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF              USART_ISR_CTSIF_Msk                       /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos            (10U)
-#define USART_ISR_CTS_Msk            (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                USART_ISR_CTS_Msk                         /*!< CTS flag */
-#define USART_ISR_RTOF_Pos           (11U)
-#define USART_ISR_RTOF_Msk           (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF               USART_ISR_RTOF_Msk                        /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos           (12U)
-#define USART_ISR_EOBF_Msk           (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF               USART_ISR_EOBF_Msk                        /*!< End Of Block Flag */
-#define USART_ISR_UDR_Pos            (13U)
-#define USART_ISR_UDR_Msk            (0x1UL << USART_ISR_UDR_Pos)              /*!< 0x00002000 */
-#define USART_ISR_UDR                 USART_ISR_UDR_Msk                        /*!< SPI Slave Underrun Error Flag */
-#define USART_ISR_ABRE_Pos           (14U)
-#define USART_ISR_ABRE_Msk           (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE               USART_ISR_ABRE_Msk                        /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos           (15U)
-#define USART_ISR_ABRF_Msk           (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF               USART_ISR_ABRF_Msk                        /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos           (16U)
-#define USART_ISR_BUSY_Msk           (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY               USART_ISR_BUSY_Msk                        /*!< Busy Flag */
-#define USART_ISR_CMF_Pos            (17U)
-#define USART_ISR_CMF_Msk            (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                USART_ISR_CMF_Msk                         /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos           (18U)
-#define USART_ISR_SBKF_Msk           (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF               USART_ISR_SBKF_Msk                        /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos            (19U)
-#define USART_ISR_RWU_Msk            (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                USART_ISR_RWU_Msk                         /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos            (20U)
-#define USART_ISR_WUF_Msk            (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                USART_ISR_WUF_Msk                         /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos          (21U)
-#define USART_ISR_TEACK_Msk          (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK              USART_ISR_TEACK_Msk                       /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos          (22U)
-#define USART_ISR_REACK_Msk          (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK              USART_ISR_REACK_Msk                       /*!< Receive Enable Acknowledge Flag */
-#define USART_ISR_TXFE_Pos           (23U)
-#define USART_ISR_TXFE_Msk           (0x1UL << USART_ISR_TXFE_Pos)             /*!< 0x00800000 */
-#define USART_ISR_TXFE               USART_ISR_TXFE_Msk                        /*!< TXFIFO Empty Flag */
-#define USART_ISR_RXFF_Pos           (24U)
-#define USART_ISR_RXFF_Msk           (0x1UL << USART_ISR_RXFF_Pos)             /*!< 0x01000000 */
-#define USART_ISR_RXFF               USART_ISR_RXFF_Msk                        /*!< RXFIFO Full Flag */
-#define USART_ISR_TCBGT_Pos          (25U)
-#define USART_ISR_TCBGT_Msk          (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
-#define USART_ISR_TCBGT              USART_ISR_TCBGT_Msk                       /*!< Transmission Complete Before Guard Time Completion Flag */
-#define USART_ISR_RXFT_Pos           (26U)
-#define USART_ISR_RXFT_Msk           (0x1UL << USART_ISR_RXFT_Pos)             /*!< 0x04000000 */
-#define USART_ISR_RXFT               USART_ISR_RXFT_Msk                        /*!< RXFIFO Threshold Flag */
-#define USART_ISR_TXFT_Pos           (27U)
-#define USART_ISR_TXFT_Msk           (0x1UL << USART_ISR_TXFT_Pos)             /*!< 0x08000000 */
-#define USART_ISR_TXFT               USART_ISR_TXFT_Msk                        /*!< TXFIFO Threshold Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos           (0U)
-#define USART_ICR_PECF_Msk           (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF               USART_ICR_PECF_Msk                        /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos           (1U)
-#define USART_ICR_FECF_Msk           (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF               USART_ICR_FECF_Msk                        /*!< Framing Error Clear Flag */
-#define USART_ICR_NECF_Pos           (2U)
-#define USART_ICR_NECF_Msk           (0x1UL << USART_ICR_NECF_Pos)             /*!< 0x00000004 */
-#define USART_ICR_NECF               USART_ICR_NECF_Msk                        /*!< Noise Error detected Clear Flag */
-#define USART_ICR_ORECF_Pos          (3U)
-#define USART_ICR_ORECF_Msk          (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF              USART_ICR_ORECF_Msk                       /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos         (4U)
-#define USART_ICR_IDLECF_Msk         (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF             USART_ICR_IDLECF_Msk                      /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TXFECF_Pos         (5U)
-#define USART_ICR_TXFECF_Msk         (0x1UL << USART_ICR_TXFECF_Pos)           /*!< 0x00000020 */
-#define USART_ICR_TXFECF             USART_ICR_TXFECF_Msk                      /*!< TXFIFO Empty Clear Flag */
-#define USART_ICR_TCCF_Pos           (6U)
-#define USART_ICR_TCCF_Msk           (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF               USART_ICR_TCCF_Msk                        /*!< Transmission Complete Clear Flag */
-#define USART_ICR_TCBGTCF_Pos        (7U)
-#define USART_ICR_TCBGTCF_Msk        (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
-#define USART_ICR_TCBGTCF            USART_ICR_TCBGTCF_Msk                     /*!< Transmission Complete Before Guard Time Clear Flag */
-#define USART_ICR_LBDCF_Pos          (8U)
-#define USART_ICR_LBDCF_Msk          (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF              USART_ICR_LBDCF_Msk                       /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos          (9U)
-#define USART_ICR_CTSCF_Msk          (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF              USART_ICR_CTSCF_Msk                       /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos          (11U)
-#define USART_ICR_RTOCF_Msk          (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF              USART_ICR_RTOCF_Msk                       /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos          (12U)
-#define USART_ICR_EOBCF_Msk          (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF              USART_ICR_EOBCF_Msk                       /*!< End Of Block Clear Flag */
-#define USART_ICR_UDRCF_Pos          (13U)
-#define USART_ICR_UDRCF_Msk          (0x1UL << USART_ICR_UDRCF_Pos)            /*!< 0x00002000 */
-#define USART_ICR_UDRCF              USART_ICR_UDRCF_Msk                       /*!< SPI Slave Underrun Clear Flag */
-#define USART_ICR_CMCF_Pos           (17U)
-#define USART_ICR_CMCF_Msk           (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF               USART_ICR_CMCF_Msk                        /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos           (20U)
-#define USART_ICR_WUCF_Msk           (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF               USART_ICR_WUCF_Msk                        /*!< Wake Up from stop mode Clear Flag */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)           /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)           /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/*******************  Bit definition for USART_PRESC register  ****************/
-#define USART_PRESC_PRESCALER_Pos    (0U)
-#define USART_PRESC_PRESCALER_Msk    (0xFUL << USART_PRESC_PRESCALER_Pos)      /*!< 0x0000000F */
-#define USART_PRESC_PRESCALER        USART_PRESC_PRESCALER_Msk                 /*!< PRESCALER[3:0] bits (Clock prescaler) */
-#define USART_PRESC_PRESCALER_0      (0x1UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000001 */
-#define USART_PRESC_PRESCALER_1      (0x2UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000002 */
-#define USART_PRESC_PRESCALER_2      (0x4UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000004 */
-#define USART_PRESC_PRESCALER_3      (0x8UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000008 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos          (0U)
-#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)                   /*!< 0x000000FF */
-#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bits data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos            (0U)
-#define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                      /*!< 0x00000001 */
-#define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos      (1U)
-#define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000006 */
-#define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
-#define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos          (3U)
-#define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                    /*!< 0x00000018 */
-#define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                    /*!< 0x00000008 */
-#define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                    /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos         (5U)
-#define AES_CR_CHMOD_Msk         (0x803UL << AES_CR_CHMOD_Pos)                 /*!< 0x00010060 */
-#define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0           (0x001UL << AES_CR_CHMOD_Pos)                 /*!< 0x00000020 */
-#define AES_CR_CHMOD_1           (0x002UL << AES_CR_CHMOD_Pos)                 /*!< 0x00000040 */
-#define AES_CR_CHMOD_2           (0x800UL << AES_CR_CHMOD_Pos)                 /*!< 0x00010000 */
-
-#define AES_CR_CCFC_Pos          (7U)
-#define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                    /*!< 0x00000080 */
-#define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos          (8U)
-#define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                    /*!< 0x00000100 */
-#define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
-#define AES_CR_CCFIE_Pos         (9U)
-#define AES_CR_CCFIE_Msk         (0x1UL << AES_CR_CCFIE_Pos)                   /*!< 0x00000200 */
-#define AES_CR_CCFIE             AES_CR_CCFIE_Msk                              /*!< Computation Complete Flag Interrupt Enable */
-#define AES_CR_ERRIE_Pos         (10U)
-#define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                   /*!< 0x00000400 */
-#define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos       (11U)
-#define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                 /*!< 0x00000800 */
-#define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< Enable data input phase DMA management  */
-#define AES_CR_DMAOUTEN_Pos      (12U)
-#define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< Enable data output phase DMA management */
-
-#define AES_CR_GCMPH_Pos         (13U)
-#define AES_CR_GCMPH_Msk         (0x3UL << AES_CR_GCMPH_Pos)                   /*!< 0x00006000 */
-#define AES_CR_GCMPH             AES_CR_GCMPH_Msk                              /*!< GCM Phase */
-#define AES_CR_GCMPH_0           (0x1UL << AES_CR_GCMPH_Pos)                   /*!< 0x00002000 */
-#define AES_CR_GCMPH_1           (0x2UL << AES_CR_GCMPH_Pos)                   /*!< 0x00004000 */
-
-#define AES_CR_KEYSIZE_Pos       (18U)
-#define AES_CR_KEYSIZE_Msk       (0x1UL << AES_CR_KEYSIZE_Pos)                 /*!< 0x00040000 */
-#define AES_CR_KEYSIZE           AES_CR_KEYSIZE_Msk                            /*!< Key size selection */
-
-#define AES_CR_NPBLB_Pos         (20U)
-#define AES_CR_NPBLB_Msk         (0xFUL << AES_CR_NPBLB_Pos)                   /*!< 0x00F00000 */
-#define AES_CR_NPBLB             AES_CR_NPBLB_Msk                              /*!< Number of padding bytes in last payload block */
-#define AES_CR_NPBLB_0           (0x1UL << AES_CR_NPBLB_Pos)                   /*!< 0x00100000 */
-#define AES_CR_NPBLB_1           (0x2UL << AES_CR_NPBLB_Pos)                   /*!< 0x00200000 */
-#define AES_CR_NPBLB_2           (0x4UL << AES_CR_NPBLB_Pos)                   /*!< 0x00400000 */
-#define AES_CR_NPBLB_3           (0x8UL << AES_CR_NPBLB_Pos)                   /*!< 0x00800000 */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos           (0U)
-#define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                     /*!< 0x00000001 */
-#define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos         (1U)
-#define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                   /*!< 0x00000002 */
-#define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos         (2U)
-#define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                   /*!< 0x00000004 */
-#define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
-#define AES_SR_BUSY_Pos          (3U)
-#define AES_SR_BUSY_Msk          (0x1UL << AES_SR_BUSY_Pos)                    /*!< 0x00000008 */
-#define AES_SR_BUSY              AES_SR_BUSY_Msk                               /*!< Busy Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos             (0U)
-#define AES_DINR_Msk             (0xFFFFFFFFUL << AES_DINR_Pos)                /*!< 0xFFFFFFFF */
-#define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos            (0U)
-#define AES_DOUTR_Msk            (0xFFFFFFFFUL << AES_DOUTR_Pos)               /*!< 0xFFFFFFFF */
-#define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos            (0U)
-#define AES_KEYR0_Msk            (0xFFFFFFFFUL << AES_KEYR0_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos            (0U)
-#define AES_KEYR1_Msk            (0xFFFFFFFFUL << AES_KEYR1_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos            (0U)
-#define AES_KEYR2_Msk            (0xFFFFFFFFUL << AES_KEYR2_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos            (0U)
-#define AES_KEYR3_Msk            (0xFFFFFFFFUL << AES_KEYR3_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_KEYR4 register  ******************/
-#define AES_KEYR4_Pos            (0U)
-#define AES_KEYR4_Msk            (0xFFFFFFFFUL << AES_KEYR4_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR4                AES_KEYR4_Msk                                 /*!< AES Key Register 4 */
-
-/*******************  Bit definition for AES_KEYR5 register  ******************/
-#define AES_KEYR5_Pos            (0U)
-#define AES_KEYR5_Msk            (0xFFFFFFFFUL << AES_KEYR5_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR5                AES_KEYR5_Msk                                 /*!< AES Key Register 5 */
-
-/*******************  Bit definition for AES_KEYR6 register  ******************/
-#define AES_KEYR6_Pos            (0U)
-#define AES_KEYR6_Msk            (0xFFFFFFFFUL << AES_KEYR6_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR6                AES_KEYR6_Msk                                 /*!< AES Key Register 6 */
-
-/*******************  Bit definition for AES_KEYR7 register  ******************/
-#define AES_KEYR7_Pos            (0U)
-#define AES_KEYR7_Msk            (0xFFFFFFFFUL << AES_KEYR7_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR7                AES_KEYR7_Msk                                 /*!< AES Key Register 7 */
-
-/*******************  Bit definition for AES_IVR0 register   ******************/
-#define AES_IVR0_Pos             (0U)
-#define AES_IVR0_Msk             (0xFFFFFFFFUL << AES_IVR0_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register   ******************/
-#define AES_IVR1_Pos             (0U)
-#define AES_IVR1_Msk             (0xFFFFFFFFUL << AES_IVR1_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register   ******************/
-#define AES_IVR2_Pos             (0U)
-#define AES_IVR2_Msk             (0xFFFFFFFFUL << AES_IVR2_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register   ******************/
-#define AES_IVR3_Pos             (0U)
-#define AES_IVR3_Msk             (0xFFFFFFFFUL << AES_IVR3_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
-
-/*******************  Bit definition for AES_SUSP0R register  ******************/
-#define AES_SUSP0R_Pos           (0U)
-#define AES_SUSP0R_Msk           (0xFFFFFFFFUL << AES_SUSP0R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP0R               AES_SUSP0R_Msk                                /*!< AES Suspend registers 0 */
-
-/*******************  Bit definition for AES_SUSP1R register  ******************/
-#define AES_SUSP1R_Pos           (0U)
-#define AES_SUSP1R_Msk           (0xFFFFFFFFUL << AES_SUSP1R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP1R               AES_SUSP1R_Msk                                /*!< AES Suspend registers 1 */
-
-/*******************  Bit definition for AES_SUSP2R register  ******************/
-#define AES_SUSP2R_Pos           (0U)
-#define AES_SUSP2R_Msk           (0xFFFFFFFFUL << AES_SUSP2R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP2R               AES_SUSP2R_Msk                                /*!< AES Suspend registers 2 */
-
-/*******************  Bit definition for AES_SUSP3R register  ******************/
-#define AES_SUSP3R_Pos           (0U)
-#define AES_SUSP3R_Msk           (0xFFFFFFFFUL << AES_SUSP3R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP3R               AES_SUSP3R_Msk                                /*!< AES Suspend registers 3 */
-
-/*******************  Bit definition for AES_SUSP4R register  ******************/
-#define AES_SUSP4R_Pos           (0U)
-#define AES_SUSP4R_Msk           (0xFFFFFFFFUL << AES_SUSP4R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP4R               AES_SUSP4R_Msk                                /*!< AES Suspend registers 4 */
-
-/*******************  Bit definition for AES_SUSP5R register  ******************/
-#define AES_SUSP5R_Pos           (0U)
-#define AES_SUSP5R_Msk           (0xFFFFFFFFUL << AES_SUSP5R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP5R               AES_SUSP5R_Msk                                /*!< AES Suspend registers 5 */
-
-/*******************  Bit definition for AES_SUSP6R register  ******************/
-#define AES_SUSP6R_Pos           (0U)
-#define AES_SUSP6R_Msk           (0xFFFFFFFFUL << AES_SUSP6R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP6R               AES_SUSP6R_Msk                                /*!< AES Suspend registers 6 */
-
-/*******************  Bit definition for AES_SUSP7R register  ******************/
-#define AES_SUSP7R_Pos           (0U)
-#define AES_SUSP7R_Msk           (0xFFFFFFFFUL << AES_SUSP7R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP7R               AES_SUSP7R_Msk                                /*!< AES Suspend registers 7 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos      (1U)
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos      (2U)
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos      (3U)
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos       (4U)
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos      (5U)
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos      (6U)
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos      (7U)
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos       (8U)
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos      (9U)
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos      (10U)
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos      (11U)
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos       (12U)
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos      (13U)
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos      (14U)
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos      (15U)
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos       (16U)
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos      (17U)
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos      (18U)
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos      (19U)
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos       (20U)
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos    (1U)
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos    (2U)
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos    (3U)
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos     (4U)
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos    (5U)
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos    (6U)
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos    (7U)
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos     (8U)
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos    (9U)
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos    (10U)
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos    (11U)
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos     (12U)
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos    (13U)
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos    (14U)
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos    (15U)
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos     (16U)
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos    (17U)
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos    (18U)
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos    (19U)
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos     (20U)
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-#define DMA_CCR_SECM_Pos       (17U)
-#define DMA_CCR_SECM_Msk       (0x1UL << DMA_CCR_SECM_Pos)                    /*!< 0x00020000 */
-#define DMA_CCR_SECM           DMA_CCR_SECM_Msk                               /*!< Secure mode                          */
-#define DMA_CCR_SSEC_Pos       (18U)
-#define DMA_CCR_SSEC_Msk       (0x1UL << DMA_CCR_SSEC_Pos)                    /*!< 0x00040000 */
-#define DMA_CCR_SSEC           DMA_CCR_SSEC_Msk                               /*!< Security of the DMA transfer from the source, only accessible write, read by CM0PLUS    */
-#define DMA_CCR_DSEC_Pos       (19U)
-#define DMA_CCR_DSEC_Msk       (0x1UL << DMA_CCR_DSEC_Pos)                    /*!< 0x00080000 */
-#define DMA_CCR_DSEC           DMA_CCR_DSEC_Msk                               /*!< Security of the DMA transfer to the destination, only accessible write, read by CM0PLUS */
-#define DMA_CCR_PRIV_Pos       (20U)
-#define DMA_CCR_PRIV_Msk       (0x1UL << DMA_CCR_PRIV_Pos)                    /*!< 0x00100000 */
-#define DMA_CCR_PRIV           DMA_CCR_PRIV_Msk                               /*!< Privileged mode                      */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)
-#define DMA_CNDTR_NDT_Msk      (0x3FFFFUL << DMA_CNDTR_NDT_Pos)                /*!< 0x0003FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMAMUX Controller                              */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMAMUX_CxCR register  **************/
-#define DMAMUX_CxCR_DMAREQ_ID_Pos              (0U)
-#define DMAMUX_CxCR_DMAREQ_ID_Msk              (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x0000007F */
-#define DMAMUX_CxCR_DMAREQ_ID                  DMAMUX_CxCR_DMAREQ_ID_Msk       /*!< DMA Request ID                       */
-#define DMAMUX_CxCR_DMAREQ_ID_0                (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
-#define DMAMUX_CxCR_DMAREQ_ID_1                (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
-#define DMAMUX_CxCR_DMAREQ_ID_2                (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
-#define DMAMUX_CxCR_DMAREQ_ID_3                (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
-#define DMAMUX_CxCR_DMAREQ_ID_4                (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
-#define DMAMUX_CxCR_DMAREQ_ID_5                (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
-#define DMAMUX_CxCR_DMAREQ_ID_6                (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
-#define DMAMUX_CxCR_SOIE_Pos                   (8U)
-#define DMAMUX_CxCR_SOIE_Msk                   (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
-#define DMAMUX_CxCR_SOIE                       DMAMUX_CxCR_SOIE_Msk            /*!< Synchro overrun interrupt enable     */
-#define DMAMUX_CxCR_EGE_Pos                    (9U)
-#define DMAMUX_CxCR_EGE_Msk                    (0x1UL << DMAMUX_CxCR_EGE_Pos)  /*!< 0x00000200 */
-#define DMAMUX_CxCR_EGE                        DMAMUX_CxCR_EGE_Msk             /*!< Event generation interrupt enable    */
-#define DMAMUX_CxCR_SE_Pos                     (16U)
-#define DMAMUX_CxCR_SE_Msk                     (0x1UL << DMAMUX_CxCR_SE_Pos)   /*!< 0x00010000 */
-#define DMAMUX_CxCR_SE                         DMAMUX_CxCR_SE_Msk              /*!< Synchronization enable               */
-#define DMAMUX_CxCR_SPOL_Pos                   (17U)
-#define DMAMUX_CxCR_SPOL_Msk                   (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
-#define DMAMUX_CxCR_SPOL                       DMAMUX_CxCR_SPOL_Msk            /*!< Synchronization polarity             */
-#define DMAMUX_CxCR_SPOL_0                     (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
-#define DMAMUX_CxCR_SPOL_1                     (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
-#define DMAMUX_CxCR_NBREQ_Pos                  (19U)
-#define DMAMUX_CxCR_NBREQ_Msk                  (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
-#define DMAMUX_CxCR_NBREQ                      DMAMUX_CxCR_NBREQ_Msk           /*!< Number of request                    */
-#define DMAMUX_CxCR_NBREQ_0                    (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
-#define DMAMUX_CxCR_NBREQ_1                    (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
-#define DMAMUX_CxCR_NBREQ_2                    (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
-#define DMAMUX_CxCR_NBREQ_3                    (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
-#define DMAMUX_CxCR_NBREQ_4                    (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
-#define DMAMUX_CxCR_SYNC_ID_Pos                (24U)
-#define DMAMUX_CxCR_SYNC_ID_Msk                (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
-#define DMAMUX_CxCR_SYNC_ID                    DMAMUX_CxCR_SYNC_ID_Msk         /*!< Synchronization ID                   */
-#define DMAMUX_CxCR_SYNC_ID_0                  (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
-#define DMAMUX_CxCR_SYNC_ID_1                  (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
-#define DMAMUX_CxCR_SYNC_ID_2                  (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
-#define DMAMUX_CxCR_SYNC_ID_3                  (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
-#define DMAMUX_CxCR_SYNC_ID_4                  (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
-
-/*******************  Bits definition for DMAMUX_CSR register  **************/
-#define DMAMUX_CSR_SOF0_Pos                    (0U)
-#define DMAMUX_CSR_SOF0_Msk                    (0x1UL << DMAMUX_CSR_SOF0_Pos)  /*!< 0x00000001 */
-#define DMAMUX_CSR_SOF0                        DMAMUX_CSR_SOF0_Msk             /*!< Synchronization Overrun Flag 0       */
-#define DMAMUX_CSR_SOF1_Pos                    (1U)
-#define DMAMUX_CSR_SOF1_Msk                    (0x1UL << DMAMUX_CSR_SOF1_Pos)  /*!< 0x00000002 */
-#define DMAMUX_CSR_SOF1                        DMAMUX_CSR_SOF1_Msk             /*!< Synchronization Overrun Flag 1       */
-#define DMAMUX_CSR_SOF2_Pos                    (2U)
-#define DMAMUX_CSR_SOF2_Msk                    (0x1UL << DMAMUX_CSR_SOF2_Pos)  /*!< 0x00000004 */
-#define DMAMUX_CSR_SOF2                        DMAMUX_CSR_SOF2_Msk             /*!< Synchronization Overrun Flag 2       */
-#define DMAMUX_CSR_SOF3_Pos                    (3U)
-#define DMAMUX_CSR_SOF3_Msk                    (0x1UL << DMAMUX_CSR_SOF3_Pos)  /*!< 0x00000008 */
-#define DMAMUX_CSR_SOF3                        DMAMUX_CSR_SOF3_Msk             /*!< Synchronization Overrun Flag 3       */
-#define DMAMUX_CSR_SOF4_Pos                    (4U)
-#define DMAMUX_CSR_SOF4_Msk                    (0x1UL << DMAMUX_CSR_SOF4_Pos)  /*!< 0x00000010 */
-#define DMAMUX_CSR_SOF4                        DMAMUX_CSR_SOF4_Msk             /*!< Synchronization Overrun Flag 4       */
-#define DMAMUX_CSR_SOF5_Pos                    (5U)
-#define DMAMUX_CSR_SOF5_Msk                    (0x1UL << DMAMUX_CSR_SOF5_Pos)  /*!< 0x00000020 */
-#define DMAMUX_CSR_SOF5                        DMAMUX_CSR_SOF5_Msk             /*!< Synchronization Overrun Flag 5       */
-#define DMAMUX_CSR_SOF6_Pos                    (6U)
-#define DMAMUX_CSR_SOF6_Msk                    (0x1UL << DMAMUX_CSR_SOF6_Pos)  /*!< 0x00000040 */
-#define DMAMUX_CSR_SOF6                        DMAMUX_CSR_SOF6_Msk             /*!< Synchronization Overrun Flag 6       */
-#define DMAMUX_CSR_SOF7_Pos                    (7U)
-#define DMAMUX_CSR_SOF7_Msk                    (0x1UL << DMAMUX_CSR_SOF7_Pos)  /*!< 0x00000080 */
-#define DMAMUX_CSR_SOF7                        DMAMUX_CSR_SOF7_Msk             /*!< Synchronization Overrun Flag 7       */
-#define DMAMUX_CSR_SOF8_Pos                    (8U)
-#define DMAMUX_CSR_SOF8_Msk                    (0x1UL << DMAMUX_CSR_SOF8_Pos)  /*!< 0x00000100 */
-#define DMAMUX_CSR_SOF8                        DMAMUX_CSR_SOF8_Msk             /*!< Synchronization Overrun Flag 8       */
-#define DMAMUX_CSR_SOF9_Pos                    (9U)
-#define DMAMUX_CSR_SOF9_Msk                    (0x1UL << DMAMUX_CSR_SOF9_Pos)  /*!< 0x00000200 */
-#define DMAMUX_CSR_SOF9                        DMAMUX_CSR_SOF9_Msk             /*!< Synchronization Overrun Flag 9       */
-#define DMAMUX_CSR_SOF10_Pos                   (10U)
-#define DMAMUX_CSR_SOF10_Msk                   (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
-#define DMAMUX_CSR_SOF10                       DMAMUX_CSR_SOF10_Msk            /*!< Synchronization Overrun Flag 10      */
-#define DMAMUX_CSR_SOF11_Pos                   (11U)
-#define DMAMUX_CSR_SOF11_Msk                   (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
-#define DMAMUX_CSR_SOF11                       DMAMUX_CSR_SOF11_Msk            /*!< Synchronization Overrun Flag 11      */
-#define DMAMUX_CSR_SOF12_Pos                   (12U)
-#define DMAMUX_CSR_SOF12_Msk                   (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
-#define DMAMUX_CSR_SOF12                       DMAMUX_CSR_SOF12_Msk            /*!< Synchronization Overrun Flag 12      */
-#define DMAMUX_CSR_SOF13_Pos                   (13U)
-#define DMAMUX_CSR_SOF13_Msk                   (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
-#define DMAMUX_CSR_SOF13                       DMAMUX_CSR_SOF13_Msk            /*!< Synchronization Overrun Flag 13      */
-
-/********************  Bits definition for DMAMUX_CFR register  **************/
-#define DMAMUX_CFR_CSOF0_Pos                   (0U)
-#define DMAMUX_CFR_CSOF0_Msk                   (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
-#define DMAMUX_CFR_CSOF0                       DMAMUX_CFR_CSOF0_Msk            /*!< Clear Overrun Flag 0                 */
-#define DMAMUX_CFR_CSOF1_Pos                   (1U)
-#define DMAMUX_CFR_CSOF1_Msk                   (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
-#define DMAMUX_CFR_CSOF1                       DMAMUX_CFR_CSOF1_Msk            /*!< Clear Overrun Flag 1                 */
-#define DMAMUX_CFR_CSOF2_Pos                   (2U)
-#define DMAMUX_CFR_CSOF2_Msk                   (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
-#define DMAMUX_CFR_CSOF2                       DMAMUX_CFR_CSOF2_Msk            /*!< Clear Overrun Flag 2                 */
-#define DMAMUX_CFR_CSOF3_Pos                   (3U)
-#define DMAMUX_CFR_CSOF3_Msk                   (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
-#define DMAMUX_CFR_CSOF3                       DMAMUX_CFR_CSOF3_Msk            /*!< Clear Overrun Flag 3                 */
-#define DMAMUX_CFR_CSOF4_Pos                   (4U)
-#define DMAMUX_CFR_CSOF4_Msk                   (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
-#define DMAMUX_CFR_CSOF4                       DMAMUX_CFR_CSOF4_Msk            /*!< Clear Overrun Flag 4                 */
-#define DMAMUX_CFR_CSOF5_Pos                   (5U)
-#define DMAMUX_CFR_CSOF5_Msk                   (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
-#define DMAMUX_CFR_CSOF5                       DMAMUX_CFR_CSOF5_Msk            /*!< Clear Overrun Flag 5                 */
-#define DMAMUX_CFR_CSOF6_Pos                   (6U)
-#define DMAMUX_CFR_CSOF6_Msk                   (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
-#define DMAMUX_CFR_CSOF6                       DMAMUX_CFR_CSOF6_Msk            /*!< Clear Overrun Flag 6                 */
-#define DMAMUX_CFR_CSOF7_Pos                   (7U)
-#define DMAMUX_CFR_CSOF7_Msk                   (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
-#define DMAMUX_CFR_CSOF7                       DMAMUX_CFR_CSOF7_Msk            /*!< Clear Overrun Flag 7                 */
-#define DMAMUX_CFR_CSOF8_Pos                   (8U)
-#define DMAMUX_CFR_CSOF8_Msk                   (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
-#define DMAMUX_CFR_CSOF8                       DMAMUX_CFR_CSOF8_Msk            /*!< Clear Overrun Flag 8                 */
-#define DMAMUX_CFR_CSOF9_Pos                   (9U)
-#define DMAMUX_CFR_CSOF9_Msk                   (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
-#define DMAMUX_CFR_CSOF9                       DMAMUX_CFR_CSOF9_Msk            /*!< Clear Overrun Flag 9                 */
-#define DMAMUX_CFR_CSOF10_Pos                  (10U)
-#define DMAMUX_CFR_CSOF10_Msk                  (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
-#define DMAMUX_CFR_CSOF10                      DMAMUX_CFR_CSOF10_Msk           /*!< Clear Overrun Flag 10                */
-#define DMAMUX_CFR_CSOF11_Pos                  (11U)
-#define DMAMUX_CFR_CSOF11_Msk                  (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
-#define DMAMUX_CFR_CSOF11                      DMAMUX_CFR_CSOF11_Msk           /*!< Clear Overrun Flag 11                */
-#define DMAMUX_CFR_CSOF12_Pos                  (12U)
-#define DMAMUX_CFR_CSOF12_Msk                  (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
-#define DMAMUX_CFR_CSOF12                      DMAMUX_CFR_CSOF12_Msk           /*!< Clear Overrun Flag 12                */
-#define DMAMUX_CFR_CSOF13_Pos                  (13U)
-#define DMAMUX_CFR_CSOF13_Msk                  (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
-#define DMAMUX_CFR_CSOF13                      DMAMUX_CFR_CSOF13_Msk           /*!< Clear Overrun Flag 13                */
-
-/********************  Bits definition for DMAMUX_RGxCR register  ************/
-#define DMAMUX_RGxCR_SIG_ID_Pos                (0U)
-#define DMAMUX_RGxCR_SIG_ID_Msk                (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
-#define DMAMUX_RGxCR_SIG_ID                    DMAMUX_RGxCR_SIG_ID_Msk         /*!< Signal ID                            */
-#define DMAMUX_RGxCR_SIG_ID_0                  (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
-#define DMAMUX_RGxCR_SIG_ID_1                  (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
-#define DMAMUX_RGxCR_SIG_ID_2                  (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
-#define DMAMUX_RGxCR_SIG_ID_3                  (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
-#define DMAMUX_RGxCR_SIG_ID_4                  (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
-#define DMAMUX_RGxCR_OIE_Pos                   (8U)
-#define DMAMUX_RGxCR_OIE_Msk                   (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
-#define DMAMUX_RGxCR_OIE                       DMAMUX_RGxCR_OIE_Msk            /*!< Overrun interrupt enable             */
-#define DMAMUX_RGxCR_GE_Pos                    (16U)
-#define DMAMUX_RGxCR_GE_Msk                    (0x1UL << DMAMUX_RGxCR_GE_Pos)  /*!< 0x00010000 */
-#define DMAMUX_RGxCR_GE                        DMAMUX_RGxCR_GE_Msk             /*!< Generation enable                    */
-#define DMAMUX_RGxCR_GPOL_Pos                  (17U)
-#define DMAMUX_RGxCR_GPOL_Msk                  (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
-#define DMAMUX_RGxCR_GPOL                      DMAMUX_RGxCR_GPOL_Msk           /*!< Generation polarity                  */
-#define DMAMUX_RGxCR_GPOL_0                    (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
-#define DMAMUX_RGxCR_GPOL_1                    (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
-#define DMAMUX_RGxCR_GNBREQ_Pos                (19U)
-#define DMAMUX_RGxCR_GNBREQ_Msk                (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
-#define DMAMUX_RGxCR_GNBREQ                    DMAMUX_RGxCR_GNBREQ_Msk          /*!< Number of request                    */
-#define DMAMUX_RGxCR_GNBREQ_0                  (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
-#define DMAMUX_RGxCR_GNBREQ_1                  (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
-#define DMAMUX_RGxCR_GNBREQ_2                  (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
-#define DMAMUX_RGxCR_GNBREQ_3                  (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
-#define DMAMUX_RGxCR_GNBREQ_4                  (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
-
-/********************  Bits definition for DMAMUX_RGSR register  **************/
-#define DMAMUX_RGSR_OF0_Pos                    (0U)
-#define DMAMUX_RGSR_OF0_Msk                    (0x1UL << DMAMUX_RGSR_OF0_Pos)  /*!< 0x00000001 */
-#define DMAMUX_RGSR_OF0                        DMAMUX_RGSR_OF0_Msk             /*!< Overrun flag 0                       */
-#define DMAMUX_RGSR_OF1_Pos                    (1U)
-#define DMAMUX_RGSR_OF1_Msk                    (0x1UL << DMAMUX_RGSR_OF1_Pos)  /*!< 0x00000002 */
-#define DMAMUX_RGSR_OF1                        DMAMUX_RGSR_OF1_Msk             /*!< Overrun flag 1                       */
-#define DMAMUX_RGSR_OF2_Pos                    (2U)
-#define DMAMUX_RGSR_OF2_Msk                    (0x1UL << DMAMUX_RGSR_OF2_Pos)  /*!< 0x00000004 */
-#define DMAMUX_RGSR_OF2                        DMAMUX_RGSR_OF2_Msk             /*!< Overrun flag 2                       */
-#define DMAMUX_RGSR_OF3_Pos                    (3U)
-#define DMAMUX_RGSR_OF3_Msk                    (0x1UL << DMAMUX_RGSR_OF3_Pos)  /*!< 0x00000008 */
-#define DMAMUX_RGSR_OF3                        DMAMUX_RGSR_OF3_Msk             /*!< Overrun flag 3                       */
-
-/********************  Bits definition for DMAMUX_RGCFR register  **************/
-#define DMAMUX_RGCFR_COF0_Pos                  (0U)
-#define DMAMUX_RGCFR_COF0_Msk                  (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
-#define DMAMUX_RGCFR_COF0                      DMAMUX_RGCFR_COF0_Msk           /*!< Clear Overrun flag 0                 */
-#define DMAMUX_RGCFR_COF1_Pos                  (1U)
-#define DMAMUX_RGCFR_COF1_Msk                  (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
-#define DMAMUX_RGCFR_COF1                      DMAMUX_RGCFR_COF1_Msk           /*!< Clear Overrun flag 1                 */
-#define DMAMUX_RGCFR_COF2_Pos                  (2U)
-#define DMAMUX_RGCFR_COF2_Msk                  (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
-#define DMAMUX_RGCFR_COF2                      DMAMUX_RGCFR_COF2_Msk           /*!< Clear Overrun flag 2                 */
-#define DMAMUX_RGCFR_COF3_Pos                  (3U)
-#define DMAMUX_RGCFR_COF3_Msk                  (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
-#define DMAMUX_RGCFR_COF3                      DMAMUX_RGCFR_COF3_Msk           /*!< Clear Overrun flag 3                 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Asynchronous Interrupt/Event Controller                 */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for EXTI_RTSR1 register  ******************/
-#define EXTI_RTSR1_RT0_Pos       (0U)
-#define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */
-#define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR1_RT1_Pos       (1U)
-#define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */
-#define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR1_RT2_Pos       (2U)
-#define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */
-#define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR1_RT3_Pos       (3U)
-#define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */
-#define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR1_RT4_Pos       (4U)
-#define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */
-#define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR1_RT5_Pos       (5U)
-#define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */
-#define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR1_RT6_Pos       (6U)
-#define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */
-#define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR1_RT7_Pos       (7U)
-#define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */
-#define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR1_RT8_Pos       (8U)
-#define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */
-#define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR1_RT9_Pos       (9U)
-#define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */
-#define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR1_RT10_Pos      (10U)
-#define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */
-#define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR1_RT11_Pos      (11U)
-#define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */
-#define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR1_RT12_Pos      (12U)
-#define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */
-#define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR1_RT13_Pos      (13U)
-#define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */
-#define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR1_RT14_Pos      (14U)
-#define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */
-#define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR1_RT15_Pos      (15U)
-#define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */
-#define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR1_RT16_Pos      (16U)
-#define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */
-#define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR1_RT21_Pos      (21U)
-#define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */
-#define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR1_RT22_Pos      (22U)
-#define EXTI_RTSR1_RT22_Msk      (0x1UL << EXTI_RTSR1_RT22_Pos)                /*!< 0x00400000 */
-#define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR1 register  ******************/
-#define EXTI_FTSR1_FT0_Pos       (0U)
-#define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */
-#define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR1_FT1_Pos       (1U)
-#define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */
-#define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR1_FT2_Pos       (2U)
-#define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */
-#define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR1_FT3_Pos       (3U)
-#define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */
-#define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR1_FT4_Pos       (4U)
-#define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */
-#define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR1_FT5_Pos       (5U)
-#define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */
-#define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR1_FT6_Pos       (6U)
-#define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */
-#define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR1_FT7_Pos       (7U)
-#define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */
-#define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR1_FT8_Pos       (8U)
-#define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */
-#define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR1_FT9_Pos       (9U)
-#define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */
-#define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR1_FT10_Pos      (10U)
-#define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */
-#define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR1_FT11_Pos      (11U)
-#define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */
-#define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR1_FT12_Pos      (12U)
-#define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */
-#define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR1_FT13_Pos      (13U)
-#define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */
-#define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR1_FT14_Pos      (14U)
-#define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */
-#define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR1_FT15_Pos      (15U)
-#define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */
-#define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR1_FT16_Pos      (16U)
-#define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */
-#define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR1_FT21_Pos      (21U)
-#define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */
-#define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR1_FT22_Pos      (22U)
-#define EXTI_FTSR1_FT22_Msk      (0x1UL << EXTI_FTSR1_FT22_Pos)                /*!< 0x00400000 */
-#define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER1 register  *****************/
-#define EXTI_SWIER1_SWI0_Pos     (0U)
-#define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */
-#define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER1_SWI1_Pos     (1U)
-#define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */
-#define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER1_SWI2_Pos     (2U)
-#define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */
-#define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER1_SWI3_Pos     (3U)
-#define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */
-#define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER1_SWI4_Pos     (4U)
-#define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */
-#define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER1_SWI5_Pos     (5U)
-#define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */
-#define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER1_SWI6_Pos     (6U)
-#define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */
-#define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER1_SWI7_Pos     (7U)
-#define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */
-#define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER1_SWI8_Pos     (8U)
-#define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */
-#define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER1_SWI9_Pos     (9U)
-#define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */
-#define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER1_SWI10_Pos    (10U)
-#define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */
-#define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER1_SWI11_Pos    (11U)
-#define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */
-#define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER1_SWI12_Pos    (12U)
-#define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */
-#define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER1_SWI13_Pos    (13U)
-#define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */
-#define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER1_SWI14_Pos    (14U)
-#define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */
-#define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER1_SWI15_Pos    (15U)
-#define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */
-#define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER1_SWI16_Pos    (16U)
-#define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */
-#define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER1_SWI21_Pos    (21U)
-#define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */
-#define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER1_SWI22_Pos    (22U)
-#define EXTI_SWIER1_SWI22_Msk    (0x1UL << EXTI_SWIER1_SWI22_Pos)              /*!< 0x00400000 */
-#define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR1 register  *******************/
-#define EXTI_PR1_PIF0_Pos        (0U)
-#define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */
-#define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
-#define EXTI_PR1_PIF1_Pos        (1U)
-#define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */
-#define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
-#define EXTI_PR1_PIF2_Pos        (2U)
-#define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */
-#define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
-#define EXTI_PR1_PIF3_Pos        (3U)
-#define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */
-#define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
-#define EXTI_PR1_PIF4_Pos        (4U)
-#define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */
-#define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
-#define EXTI_PR1_PIF5_Pos        (5U)
-#define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */
-#define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
-#define EXTI_PR1_PIF6_Pos        (6U)
-#define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */
-#define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
-#define EXTI_PR1_PIF7_Pos        (7U)
-#define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */
-#define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
-#define EXTI_PR1_PIF8_Pos        (8U)
-#define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */
-#define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
-#define EXTI_PR1_PIF9_Pos        (9U)
-#define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */
-#define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
-#define EXTI_PR1_PIF10_Pos       (10U)
-#define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */
-#define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
-#define EXTI_PR1_PIF11_Pos       (11U)
-#define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */
-#define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
-#define EXTI_PR1_PIF12_Pos       (12U)
-#define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */
-#define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
-#define EXTI_PR1_PIF13_Pos       (13U)
-#define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */
-#define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
-#define EXTI_PR1_PIF14_Pos       (14U)
-#define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */
-#define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
-#define EXTI_PR1_PIF15_Pos       (15U)
-#define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */
-#define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
-#define EXTI_PR1_PIF16_Pos       (16U)
-#define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */
-#define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
-#define EXTI_PR1_PIF21_Pos       (21U)
-#define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */
-#define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
-#define EXTI_PR1_PIF22_Pos       (22U)
-#define EXTI_PR1_PIF22_Msk       (0x1UL << EXTI_PR1_PIF22_Pos)                 /*!< 0x00400000 */
-#define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
-
-/******************  Bit definition for EXTI_RTSR2 register  ******************/
-#define EXTI_RTSR2_RT34_Pos      (2U)
-#define EXTI_RTSR2_RT34_Msk      (0x1UL << EXTI_RTSR2_RT34_Pos)                /*!< 0x00000004 */
-#define EXTI_RTSR2_RT34          EXTI_RTSR2_RT34_Msk                           /*!< Rising trigger event configuration bit of line 34 */
-#define EXTI_RTSR2_RT40_Pos      (8U)
-#define EXTI_RTSR2_RT40_Msk      (0x1UL << EXTI_RTSR2_RT40_Pos)                /*!< 0x00000100 */
-#define EXTI_RTSR2_RT40          EXTI_RTSR2_RT40_Msk                           /*!< Rising trigger event configuration bit of line 40 */
-#define EXTI_RTSR2_RT41_Pos      (9U)
-#define EXTI_RTSR2_RT41_Msk      (0x1UL << EXTI_RTSR2_RT41_Pos)                /*!< 0x00000200 */
-#define EXTI_RTSR2_RT41          EXTI_RTSR2_RT41_Msk                           /*!< Rising trigger event configuration bit of line 41 */
-#define EXTI_RTSR2_RT45_Pos      (13U)
-#define EXTI_RTSR2_RT45_Msk      (0x1UL << EXTI_RTSR2_RT45_Pos)                /*!< 0x00002000 */
-#define EXTI_RTSR2_RT45          EXTI_RTSR2_RT45_Msk                           /*!< Rising trigger event configuration bit of line 45 */
-
-/******************  Bit definition for EXTI_FTSR2 register  ******************/
-#define EXTI_FTSR2_FT34_Pos      (2U)
-#define EXTI_FTSR2_FT34_Msk      (0x1UL << EXTI_FTSR2_FT34_Pos)                /*!< 0x00000004 */
-#define EXTI_FTSR2_FT34          EXTI_FTSR2_FT34_Msk                           /*!< Falling trigger event configuration bit of line 34 */
-#define EXTI_FTSR2_FT40_Pos      (8U)
-#define EXTI_FTSR2_FT40_Msk      (0x1UL << EXTI_FTSR2_FT40_Pos)                /*!< 0x00000100 */
-#define EXTI_FTSR2_FT40          EXTI_FTSR2_FT40_Msk                           /*!< Falling trigger event configuration bit of line 40 */
-#define EXTI_FTSR2_FT41_Pos      (9U)
-#define EXTI_FTSR2_FT41_Msk      (0x1UL << EXTI_FTSR2_FT41_Pos)                /*!< 0x00000200 */
-#define EXTI_FTSR2_FT41          EXTI_FTSR2_FT41_Msk                           /*!< Falling trigger event configuration bit of line 41 */
-#define EXTI_FTSR2_FT45_Pos      (13U)
-#define EXTI_FTSR2_FT45_Msk      (0x1UL << EXTI_FTSR2_FT45_Pos)                /*!< 0x00002000 */
-#define EXTI_FTSR2_FT45          EXTI_FTSR2_FT45_Msk                           /*!< Falling trigger event configuration bit of line 45 */
-
-/******************  Bit definition for EXTI_SWIER2 register  *****************/
-#define EXTI_SWIER2_SWI34_Pos    (2U)
-#define EXTI_SWIER2_SWI34_Msk    (0x1UL << EXTI_SWIER2_SWI34_Pos)              /*!< 0x00000004 */
-#define EXTI_SWIER2_SWI34        EXTI_SWIER2_SWI34_Msk                         /*!< Software Interrupt on line 34 */
-#define EXTI_SWIER2_SWI40_Pos    (8U)
-#define EXTI_SWIER2_SWI40_Msk    (0x1UL << EXTI_SWIER2_SWI40_Pos)              /*!< 0x00000100 */
-#define EXTI_SWIER2_SWI40        EXTI_SWIER2_SWI40_Msk                         /*!< Software Interrupt on line 40 */
-#define EXTI_SWIER2_SWI41_Pos    (9U)
-#define EXTI_SWIER2_SWI41_Msk    (0x1UL << EXTI_SWIER2_SWI41_Pos)              /*!< 0x00000200 */
-#define EXTI_SWIER2_SWI41        EXTI_SWIER2_SWI41_Msk                         /*!< Software Interrupt on line 41 */
-#define EXTI_SWIER2_SWI45_Pos    (13U)
-#define EXTI_SWIER2_SWI45_Msk    (0x1UL << EXTI_SWIER2_SWI45_Pos)              /*!< 0x00002000 */
-#define EXTI_SWIER2_SWI45        EXTI_SWIER2_SWI45_Msk                         /*!< Software Interrupt on line 45 */
-
-/*******************  Bit definition for EXTI_PR2 register  *******************/
-#define EXTI_PR2_PIF34_Pos       (2U)
-#define EXTI_PR2_PIF34_Msk       (0x1UL << EXTI_PR2_PIF34_Pos)                 /*!< 0x00000004 */
-#define EXTI_PR2_PIF34           EXTI_PR2_PIF34_Msk                            /*!< Pending bit for line 34 */
-#define EXTI_PR2_PIF40_Pos       (8U)
-#define EXTI_PR2_PIF40_Msk       (0x1UL << EXTI_PR2_PIF40_Pos)                 /*!< 0x00000100 */
-#define EXTI_PR2_PIF40           EXTI_PR2_PIF40_Msk                            /*!< Pending bit for line 40 */
-#define EXTI_PR2_PIF41_Pos       (9U)
-#define EXTI_PR2_PIF41_Msk       (0x1UL << EXTI_PR2_PIF41_Pos)                 /*!< 0x00000200 */
-#define EXTI_PR2_PIF41           EXTI_PR2_PIF41_Msk                            /*!< Pending bit for line 41 */
-#define EXTI_PR2_PIF45_Pos       (13U)
-#define EXTI_PR2_PIF45_Msk       (0x1UL << EXTI_PR2_PIF45_Pos)                 /*!< 0x00002000 */
-#define EXTI_PR2_PIF45           EXTI_PR2_PIF45_Msk                            /*!< Pending bit for line 45 */
-
-/********************  Bits definition for EXTI_IMR1 register  **************/
-#define EXTI_IMR1_IM0_Pos        (0U)
-#define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */
-#define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< CPU1 Interrupt Mask on line 0 */
-#define EXTI_IMR1_IM1_Pos        (1U)
-#define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */
-#define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< CPU1 Interrupt Mask on line 1 */
-#define EXTI_IMR1_IM2_Pos        (2U)
-#define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */
-#define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< CPU1 Interrupt Mask on line 2 */
-#define EXTI_IMR1_IM3_Pos        (3U)
-#define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */
-#define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< CPU1 Interrupt Mask on line 3 */
-#define EXTI_IMR1_IM4_Pos        (4U)
-#define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */
-#define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< CPU1 Interrupt Mask on line 4 */
-#define EXTI_IMR1_IM5_Pos        (5U)
-#define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */
-#define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< CPU1 Interrupt Mask on line 5 */
-#define EXTI_IMR1_IM6_Pos        (6U)
-#define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */
-#define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< CPU1 Interrupt Mask on line 6 */
-#define EXTI_IMR1_IM7_Pos        (7U)
-#define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */
-#define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< CPU1 Interrupt Mask on line 7 */
-#define EXTI_IMR1_IM8_Pos        (8U)
-#define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */
-#define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< CPU1 Interrupt Mask on line 8 */
-#define EXTI_IMR1_IM9_Pos        (9U)
-#define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */
-#define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< CPU1 Interrupt Mask on line 9 */
-#define EXTI_IMR1_IM10_Pos       (10U)
-#define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */
-#define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< CPU1 Interrupt Mask on line 10 */
-#define EXTI_IMR1_IM11_Pos       (11U)
-#define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */
-#define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< CPU1 Interrupt Mask on line 11 */
-#define EXTI_IMR1_IM12_Pos       (12U)
-#define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */
-#define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< CPU1 Interrupt Mask on line 12 */
-#define EXTI_IMR1_IM13_Pos       (13U)
-#define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */
-#define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< CPU1 Interrupt Mask on line 13 */
-#define EXTI_IMR1_IM14_Pos       (14U)
-#define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */
-#define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< CPU1 Interrupt Mask on line 14 */
-#define EXTI_IMR1_IM15_Pos       (15U)
-#define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */
-#define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< CPU1 Interrupt Mask on line 15 */
-#define EXTI_IMR1_IM16_Pos       (16U)
-#define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */
-#define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< CPU1 Interrupt Mask on line 16 */
-#define EXTI_IMR1_IM17_Pos       (17U)
-#define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */
-#define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< CPU1 Interrupt Mask on line 17 */
-#define EXTI_IMR1_IM18_Pos       (18U)
-#define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */
-#define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< CPU1 Interrupt Mask on line 18 */
-#define EXTI_IMR1_IM19_Pos       (19U)
-#define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */
-#define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< CPU1 Interrupt Mask on line 19 */
-#define EXTI_IMR1_IM20_Pos       (20U)
-#define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */
-#define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< CPU1 Interrupt Mask on line 20 */
-#define EXTI_IMR1_IM21_Pos       (21U)
-#define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */
-#define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< CPU1 Interrupt Mask on line 21 */
-#define EXTI_IMR1_IM22_Pos       (22U)
-#define EXTI_IMR1_IM22_Msk       (0x1UL << EXTI_IMR1_IM22_Pos)                 /*!< 0x00400000 */
-#define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< CPU1 Interrupt Mask on line 22 */
-#define EXTI_IMR1_IM23_Pos       (23U)
-#define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */
-#define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< CPU1 Interrupt Mask on line 23 */
-#define EXTI_IMR1_IM24_Pos       (24U)
-#define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */
-#define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< CPU1 Interrupt Mask on line 24 */
-#define EXTI_IMR1_IM25_Pos       (25U)
-#define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */
-#define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< CPU1 Interrupt Mask on line 25 */
-#define EXTI_IMR1_IM26_Pos       (26U)
-#define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */
-#define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< CPU1 Interrupt Mask on line 26 */
-#define EXTI_IMR1_IM27_Pos       (27U)
-#define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */
-#define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< CPU1 Interrupt Mask on line 27 */
-#define EXTI_IMR1_IM28_Pos       (28U)
-#define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */
-#define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< CPU1 Interrupt Mask on line 28 */
-#define EXTI_IMR1_IM29_Pos       (29U)
-#define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */
-#define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< CPU1 Interrupt Mask on line 29 */
-#define EXTI_IMR1_IM30_Pos       (30U)
-#define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */
-#define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< CPU1 Interrupt Mask on line 30 */
-#define EXTI_IMR1_IM31_Pos       (31U)
-#define EXTI_IMR1_IM31_Msk       (0x1UL << EXTI_IMR1_IM31_Pos)                 /*!< 0x80000000 */
-#define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< CPU1 Interrupt Mask on line 31 */
-
-/********************  Bits definition for EXTI_EMR1 register  **************/
-#define EXTI_EMR1_EM0_Pos        (0U)
-#define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */
-#define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< CPU1 Event Mask on line 0 */
-#define EXTI_EMR1_EM1_Pos        (1U)
-#define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */
-#define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< CPU1 Event Mask on line 1 */
-#define EXTI_EMR1_EM2_Pos        (2U)
-#define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */
-#define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< CPU1 Event Mask on line 2 */
-#define EXTI_EMR1_EM3_Pos        (3U)
-#define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */
-#define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< CPU1 Event Mask on line 3 */
-#define EXTI_EMR1_EM4_Pos        (4U)
-#define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */
-#define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< CPU1 Event Mask on line 4 */
-#define EXTI_EMR1_EM5_Pos        (5U)
-#define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */
-#define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< CPU1 Event Mask on line 5 */
-#define EXTI_EMR1_EM6_Pos        (6U)
-#define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */
-#define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< CPU1 Event Mask on line 6 */
-#define EXTI_EMR1_EM7_Pos        (7U)
-#define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */
-#define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< CPU1 Event Mask on line 7 */
-#define EXTI_EMR1_EM8_Pos        (8U)
-#define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */
-#define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< CPU1 Event Mask on line 8 */
-#define EXTI_EMR1_EM9_Pos        (9U)
-#define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */
-#define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< CPU1 Event Mask on line 9 */
-#define EXTI_EMR1_EM10_Pos       (10U)
-#define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */
-#define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< CPU1 Event Mask on line 10 */
-#define EXTI_EMR1_EM11_Pos       (11U)
-#define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */
-#define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< CPU1 Event Mask on line 11 */
-#define EXTI_EMR1_EM12_Pos       (12U)
-#define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */
-#define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< CPU1 Event Mask on line 12 */
-#define EXTI_EMR1_EM13_Pos       (13U)
-#define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */
-#define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< CPU1 Event Mask on line 13 */
-#define EXTI_EMR1_EM14_Pos       (14U)
-#define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */
-#define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< CPU1 Event Mask on line 14 */
-#define EXTI_EMR1_EM15_Pos       (15U)
-#define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */
-#define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< CPU1 Event Mask on line 15 */
-#define EXTI_EMR1_EM17_Pos       (17U)
-#define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */
-#define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< CPU1 Event Mask on line 17 */
-#define EXTI_EMR1_EM19_Pos       (19U)
-#define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */
-#define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< CPU1 Event Mask on line 19 */
-#define EXTI_EMR1_EM20_Pos       (20U)
-#define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */
-#define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< CPU1 Event Mask on line 20 */
-#define EXTI_EMR1_EM21_Pos       (21U)
-#define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */
-#define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< CPU1 Event Mask on line 21 */
-#define EXTI_EMR1_EM22_Pos       (22U)
-#define EXTI_EMR1_EM22_Msk       (0x1UL << EXTI_EMR1_EM22_Pos)                 /*!< 0x00400000 */
-#define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< CPU1 Event Mask on line 22 */
-
-/********************  Bits definition for EXTI_IMR2 register  **************/
-#define EXTI_IMR2_IM34_Pos       (2U)
-#define EXTI_IMR2_IM34_Msk       (0x1UL << EXTI_IMR2_IM34_Pos)                 /*!< 0x00000004 */
-#define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< CPU1 Interrupt Mask on line 34 */
-#define EXTI_IMR2_IM36_Pos       (4U)
-#define EXTI_IMR2_IM36_Msk       (0x1UL << EXTI_IMR2_IM36_Pos)                 /*!< 0x00000010 */
-#define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< CPU1 Interrupt Mask on line 36 */
-#define EXTI_IMR2_IM37_Pos       (5U)
-#define EXTI_IMR2_IM37_Msk       (0x1UL << EXTI_IMR2_IM37_Pos)                 /*!< 0x00000020 */
-#define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< CPU1 Interrupt Mask on line 37 */
-#define EXTI_IMR2_IM38_Pos       (6U)
-#define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */
-#define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< CPU1 Interrupt Mask on line 38 */
-#define EXTI_IMR2_IM39_Pos       (7U)
-#define EXTI_IMR2_IM39_Msk       (0x1UL << EXTI_IMR2_IM39_Pos)                 /*!< 0x00000080 */
-#define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< CPU1 Interrupt Mask on line 39 */
-#define EXTI_IMR2_IM40_Pos       (8U)
-#define EXTI_IMR2_IM40_Msk       (0x1UL << EXTI_IMR2_IM40_Pos)                 /*!< 0x00000100 */
-#define EXTI_IMR2_IM40           EXTI_IMR2_IM40_Msk                            /*!< CPU1 Interrupt Mask on line 40 */
-#define EXTI_IMR2_IM41_Pos       (9U)
-#define EXTI_IMR2_IM41_Msk       (0x1UL << EXTI_IMR2_IM41_Pos)                 /*!< 0x00000200 */
-#define EXTI_IMR2_IM41           EXTI_IMR2_IM41_Msk                            /*!< CPU1 Interrupt Mask on line 41 */
-#define EXTI_IMR2_IM42_Pos       (10U)
-#define EXTI_IMR2_IM42_Msk       (0x1UL << EXTI_IMR2_IM42_Pos)                 /*!< 0x00000400 */
-#define EXTI_IMR2_IM42           EXTI_IMR2_IM42_Msk                            /*!< CPU1 Interrupt Mask on line 42 */
-#define EXTI_IMR2_IM43_Pos       (11U)
-#define EXTI_IMR2_IM43_Msk       (0x1UL << EXTI_IMR2_IM43_Pos)                 /*!< 0x00000800 */
-#define EXTI_IMR2_IM43           EXTI_IMR2_IM43_Msk                            /*!< CPU1 Interrupt Mask on line 43 */
-#define EXTI_IMR2_IM44_Pos       (12U)
-#define EXTI_IMR2_IM44_Msk       (0x1UL << EXTI_IMR2_IM44_Pos)                 /*!< 0x00001000 */
-#define EXTI_IMR2_IM44           EXTI_IMR2_IM44_Msk                            /*!< CPU1 Interrupt Mask on line 44 */
-#define EXTI_IMR2_IM45_Pos       (13U)
-#define EXTI_IMR2_IM45_Msk       (0x1UL << EXTI_IMR2_IM45_Pos)                 /*!< 0x00002000 */
-#define EXTI_IMR2_IM45           EXTI_IMR2_IM45_Msk                            /*!< CPU1 Interrupt Mask on line 45 */
-#define EXTI_IMR2_IM46_Pos       (14U)
-#define EXTI_IMR2_IM46_Msk       (0x1UL << EXTI_IMR2_IM46_Pos)                 /*!< 0x00004000 */
-#define EXTI_IMR2_IM46           EXTI_IMR2_IM46_Msk                            /*!< CPU1 Interrupt Mask on line 46 */
-
-/********************  Bits definition for EXTI_EMR2 register  **************/
-#define EXTI_EMR2_EM40_Pos       (8U)
-#define EXTI_EMR2_EM40_Msk       (0x1UL << EXTI_EMR2_EM40_Pos)                 /*!< 0x00000100 */
-#define EXTI_EMR2_EM40           EXTI_EMR2_EM40_Msk                            /*!< CPU1 Event Mask on line 40 */
-#define EXTI_EMR2_EM41_Pos       (9U)
-#define EXTI_EMR2_EM41_Msk       (0x1UL << EXTI_EMR2_EM41_Pos)                 /*!< 0x00000200 */
-#define EXTI_EMR2_EM41           EXTI_EMR2_EM41_Msk                            /*!< CPU1 Event Mask on line 41 */
-
-/********************  Bits definition for EXTI_C2IMR1 register  **************/
-#define EXTI_C2IMR1_IM0_Pos      (0U)
-#define EXTI_C2IMR1_IM0_Msk      (0x1UL << EXTI_C2IMR1_IM0_Pos)                /*!< 0x00000001 */
-#define EXTI_C2IMR1_IM0          EXTI_C2IMR1_IM0_Msk                           /*!< CPU2 Interrupt Mask on line 0 */
-#define EXTI_C2IMR1_IM1_Pos      (1U)
-#define EXTI_C2IMR1_IM1_Msk      (0x1UL << EXTI_C2IMR1_IM1_Pos)                /*!< 0x00000002 */
-#define EXTI_C2IMR1_IM1          EXTI_C2IMR1_IM1_Msk                           /*!< CPU2 Interrupt Mask on line 1 */
-#define EXTI_C2IMR1_IM2_Pos      (2U)
-#define EXTI_C2IMR1_IM2_Msk      (0x1UL << EXTI_C2IMR1_IM2_Pos)                /*!< 0x00000004 */
-#define EXTI_C2IMR1_IM2          EXTI_C2IMR1_IM2_Msk                           /*!< CPU2 Interrupt Mask on line 2 */
-#define EXTI_C2IMR1_IM3_Pos      (3U)
-#define EXTI_C2IMR1_IM3_Msk      (0x1UL << EXTI_C2IMR1_IM3_Pos)                /*!< 0x00000008 */
-#define EXTI_C2IMR1_IM3          EXTI_C2IMR1_IM3_Msk                           /*!< CPU2 Interrupt Mask on line 3 */
-#define EXTI_C2IMR1_IM4_Pos      (4U)
-#define EXTI_C2IMR1_IM4_Msk      (0x1UL << EXTI_C2IMR1_IM4_Pos)                /*!< 0x00000010 */
-#define EXTI_C2IMR1_IM4          EXTI_C2IMR1_IM4_Msk                           /*!< CPU2 Interrupt Mask on line 4 */
-#define EXTI_C2IMR1_IM5_Pos      (5U)
-#define EXTI_C2IMR1_IM5_Msk      (0x1UL << EXTI_C2IMR1_IM5_Pos)                /*!< 0x00000020 */
-#define EXTI_C2IMR1_IM5          EXTI_C2IMR1_IM5_Msk                           /*!< CPU2 Interrupt Mask on line 5 */
-#define EXTI_C2IMR1_IM6_Pos      (6U)
-#define EXTI_C2IMR1_IM6_Msk      (0x1UL << EXTI_C2IMR1_IM6_Pos)                /*!< 0x00000040 */
-#define EXTI_C2IMR1_IM6          EXTI_C2IMR1_IM6_Msk                           /*!< CPU2 Interrupt Mask on line 6 */
-#define EXTI_C2IMR1_IM7_Pos      (7U)
-#define EXTI_C2IMR1_IM7_Msk      (0x1UL << EXTI_C2IMR1_IM7_Pos)                /*!< 0x00000080 */
-#define EXTI_C2IMR1_IM7          EXTI_C2IMR1_IM7_Msk                           /*!< CPU2 Interrupt Mask on line 7 */
-#define EXTI_C2IMR1_IM8_Pos      (8U)
-#define EXTI_C2IMR1_IM8_Msk      (0x1UL << EXTI_C2IMR1_IM8_Pos)                /*!< 0x00000100 */
-#define EXTI_C2IMR1_IM8          EXTI_C2IMR1_IM8_Msk                           /*!< CPU2 Interrupt Mask on line 8 */
-#define EXTI_C2IMR1_IM9_Pos      (9U)
-#define EXTI_C2IMR1_IM9_Msk      (0x1UL << EXTI_C2IMR1_IM9_Pos)                /*!< 0x00000200 */
-#define EXTI_C2IMR1_IM9          EXTI_C2IMR1_IM9_Msk                           /*!< CPU2 Interrupt Mask on line 9 */
-#define EXTI_C2IMR1_IM10_Pos     (10U)
-#define EXTI_C2IMR1_IM10_Msk     (0x1UL << EXTI_C2IMR1_IM10_Pos)               /*!< 0x00000400 */
-#define EXTI_C2IMR1_IM10         EXTI_C2IMR1_IM10_Msk                          /*!< CPU2 Interrupt Mask on line 10 */
-#define EXTI_C2IMR1_IM11_Pos     (11U)
-#define EXTI_C2IMR1_IM11_Msk     (0x1UL << EXTI_C2IMR1_IM11_Pos)               /*!< 0x00000800 */
-#define EXTI_C2IMR1_IM11         EXTI_C2IMR1_IM11_Msk                          /*!< CPU2 Interrupt Mask on line 11 */
-#define EXTI_C2IMR1_IM12_Pos     (12U)
-#define EXTI_C2IMR1_IM12_Msk     (0x1UL << EXTI_C2IMR1_IM12_Pos)               /*!< 0x00001000 */
-#define EXTI_C2IMR1_IM12         EXTI_C2IMR1_IM12_Msk                          /*!< CPU2 Interrupt Mask on line 12 */
-#define EXTI_C2IMR1_IM13_Pos     (13U)
-#define EXTI_C2IMR1_IM13_Msk     (0x1UL << EXTI_C2IMR1_IM13_Pos)               /*!< 0x00002000 */
-#define EXTI_C2IMR1_IM13         EXTI_C2IMR1_IM13_Msk                          /*!< CPU2 Interrupt Mask on line 13 */
-#define EXTI_C2IMR1_IM14_Pos     (14U)
-#define EXTI_C2IMR1_IM14_Msk     (0x1UL << EXTI_C2IMR1_IM14_Pos)               /*!< 0x00004000 */
-#define EXTI_C2IMR1_IM14         EXTI_C2IMR1_IM14_Msk                          /*!< CPU2 Interrupt Mask on line 14 */
-#define EXTI_C2IMR1_IM15_Pos     (15U)
-#define EXTI_C2IMR1_IM15_Msk     (0x1UL << EXTI_C2IMR1_IM15_Pos)               /*!< 0x00008000 */
-#define EXTI_C2IMR1_IM15         EXTI_C2IMR1_IM15_Msk                          /*!< CPU2 Interrupt Mask on line 15 */
-#define EXTI_C2IMR1_IM16_Pos     (16U)
-#define EXTI_C2IMR1_IM16_Msk     (0x1UL << EXTI_C2IMR1_IM16_Pos)               /*!< 0x00010000 */
-#define EXTI_C2IMR1_IM16         EXTI_C2IMR1_IM16_Msk                          /*!< CPU2 Interrupt Mask on line 16 */
-#define EXTI_C2IMR1_IM17_Pos     (17U)
-#define EXTI_C2IMR1_IM17_Msk     (0x1UL << EXTI_C2IMR1_IM17_Pos)               /*!< 0x00020000 */
-#define EXTI_C2IMR1_IM17         EXTI_C2IMR1_IM17_Msk                          /*!< CPU2 Interrupt Mask on line 17 */
-#define EXTI_C2IMR1_IM18_Pos     (18U)
-#define EXTI_C2IMR1_IM18_Msk     (0x1UL << EXTI_C2IMR1_IM18_Pos)               /*!< 0x00040000 */
-#define EXTI_C2IMR1_IM18         EXTI_C2IMR1_IM18_Msk                          /*!< CPU2 Interrupt Mask on line 18 */
-#define EXTI_C2IMR1_IM19_Pos     (19U)
-#define EXTI_C2IMR1_IM19_Msk     (0x1UL << EXTI_C2IMR1_IM19_Pos)               /*!< 0x00080000 */
-#define EXTI_C2IMR1_IM19         EXTI_C2IMR1_IM19_Msk                          /*!< CPU2 Interrupt Mask on line 19 */
-#define EXTI_C2IMR1_IM20_Pos     (20U)
-#define EXTI_C2IMR1_IM20_Msk     (0x1UL << EXTI_C2IMR1_IM20_Pos)               /*!< 0x00100000 */
-#define EXTI_C2IMR1_IM20         EXTI_C2IMR1_IM20_Msk                          /*!< CPU2 Interrupt Mask on line 20 */
-#define EXTI_C2IMR1_IM21_Pos     (21U)
-#define EXTI_C2IMR1_IM21_Msk     (0x1UL << EXTI_C2IMR1_IM21_Pos)               /*!< 0x00200000 */
-#define EXTI_C2IMR1_IM21         EXTI_C2IMR1_IM21_Msk                          /*!< CPU2 Interrupt Mask on line 21 */
-#define EXTI_C2IMR1_IM22_Pos     (22U)
-#define EXTI_C2IMR1_IM22_Msk     (0x1UL << EXTI_C2IMR1_IM22_Pos)               /*!< 0x00400000 */
-#define EXTI_C2IMR1_IM22         EXTI_C2IMR1_IM22_Msk                          /*!< CPU2 Interrupt Mask on line 22 */
-#define EXTI_C2IMR1_IM23_Pos     (23U)
-#define EXTI_C2IMR1_IM23_Msk     (0x1UL << EXTI_C2IMR1_IM23_Pos)               /*!< 0x00800000 */
-#define EXTI_C2IMR1_IM23         EXTI_C2IMR1_IM23_Msk                          /*!< CPU2 Interrupt Mask on line 23 */
-#define EXTI_C2IMR1_IM24_Pos     (24U)
-#define EXTI_C2IMR1_IM24_Msk     (0x1UL << EXTI_C2IMR1_IM24_Pos)               /*!< 0x01000000 */
-#define EXTI_C2IMR1_IM24         EXTI_C2IMR1_IM24_Msk                          /*!< CPU2 Interrupt Mask on line 24 */
-#define EXTI_C2IMR1_IM25_Pos     (25U)
-#define EXTI_C2IMR1_IM25_Msk     (0x1UL << EXTI_C2IMR1_IM25_Pos)               /*!< 0x02000000 */
-#define EXTI_C2IMR1_IM25         EXTI_C2IMR1_IM25_Msk                          /*!< CPU2 Interrupt Mask on line 25 */
-#define EXTI_C2IMR1_IM26_Pos     (26U)
-#define EXTI_C2IMR1_IM26_Msk     (0x1UL << EXTI_C2IMR1_IM26_Pos)               /*!< 0x04000000 */
-#define EXTI_C2IMR1_IM26         EXTI_C2IMR1_IM26_Msk                          /*!< CPU2 Interrupt Mask on line 26 */
-#define EXTI_C2IMR1_IM27_Pos     (27U)
-#define EXTI_C2IMR1_IM27_Msk     (0x1UL << EXTI_C2IMR1_IM27_Pos)               /*!< 0x08000000 */
-#define EXTI_C2IMR1_IM27         EXTI_C2IMR1_IM27_Msk                          /*!< CPU2 Interrupt Mask on line 27 */
-#define EXTI_C2IMR1_IM28_Pos     (28U)
-#define EXTI_C2IMR1_IM28_Msk     (0x1UL << EXTI_C2IMR1_IM28_Pos)               /*!< 0x10000000 */
-#define EXTI_C2IMR1_IM28         EXTI_C2IMR1_IM28_Msk                          /*!< CPU2 Interrupt Mask on line 28 */
-#define EXTI_C2IMR1_IM29_Pos     (29U)
-#define EXTI_C2IMR1_IM29_Msk     (0x1UL << EXTI_C2IMR1_IM29_Pos)               /*!< 0x20000000 */
-#define EXTI_C2IMR1_IM29         EXTI_C2IMR1_IM29_Msk                          /*!< CPU2 Interrupt Mask on line 29 */
-#define EXTI_C2IMR1_IM30_Pos     (30U)
-#define EXTI_C2IMR1_IM30_Msk     (0x1UL << EXTI_C2IMR1_IM30_Pos)               /*!< 0x40000000 */
-#define EXTI_C2IMR1_IM30         EXTI_C2IMR1_IM30_Msk                          /*!< CPU2 Interrupt Mask on line 30 */
-#define EXTI_C2IMR1_IM31_Pos     (31U)
-#define EXTI_C2IMR1_IM31_Msk     (0x1UL << EXTI_C2IMR1_IM31_Pos)               /*!< 0x80000000 */
-#define EXTI_C2IMR1_IM31         EXTI_C2IMR1_IM31_Msk                          /*!< CPU2 Interrupt Mask on line 31 */
-
-/********************  Bits definition for EXTI_C2EMR1 register  **************/
-#define EXTI_C2EMR1_EM0_Pos      (0U)
-#define EXTI_C2EMR1_EM0_Msk      (0x1UL << EXTI_C2EMR1_EM0_Pos)                /*!< 0x00000001 */
-#define EXTI_C2EMR1_EM0          EXTI_C2EMR1_EM0_Msk                           /*!< CPU2 Event Mask on line 0 */
-#define EXTI_C2EMR1_EM1_Pos      (1U)
-#define EXTI_C2EMR1_EM1_Msk      (0x1UL << EXTI_C2EMR1_EM1_Pos)                /*!< 0x00000002 */
-#define EXTI_C2EMR1_EM1          EXTI_C2EMR1_EM1_Msk                           /*!< CPU2 Event Mask on line 1 */
-#define EXTI_C2EMR1_EM2_Pos      (2U)
-#define EXTI_C2EMR1_EM2_Msk      (0x1UL << EXTI_C2EMR1_EM2_Pos)                /*!< 0x00000004 */
-#define EXTI_C2EMR1_EM2          EXTI_C2EMR1_EM2_Msk                           /*!< CPU2 Event Mask on line 2 */
-#define EXTI_C2EMR1_EM3_Pos      (3U)
-#define EXTI_C2EMR1_EM3_Msk      (0x1UL << EXTI_C2EMR1_EM3_Pos)                /*!< 0x00000008 */
-#define EXTI_C2EMR1_EM3          EXTI_C2EMR1_EM3_Msk                           /*!< CPU2 Event Mask on line 3 */
-#define EXTI_C2EMR1_EM4_Pos      (4U)
-#define EXTI_C2EMR1_EM4_Msk      (0x1UL << EXTI_C2EMR1_EM4_Pos)                /*!< 0x00000010 */
-#define EXTI_C2EMR1_EM4          EXTI_C2EMR1_EM4_Msk                           /*!< CPU2 Event Mask on line 4 */
-#define EXTI_C2EMR1_EM5_Pos      (5U)
-#define EXTI_C2EMR1_EM5_Msk      (0x1UL << EXTI_C2EMR1_EM5_Pos)                /*!< 0x00000020 */
-#define EXTI_C2EMR1_EM5          EXTI_C2EMR1_EM5_Msk                           /*!< CPU2 Event Mask on line 5 */
-#define EXTI_C2EMR1_EM6_Pos      (6U)
-#define EXTI_C2EMR1_EM6_Msk      (0x1UL << EXTI_C2EMR1_EM6_Pos)                /*!< 0x00000040 */
-#define EXTI_C2EMR1_EM6          EXTI_C2EMR1_EM6_Msk                           /*!< CPU2 Event Mask on line 6 */
-#define EXTI_C2EMR1_EM7_Pos      (7U)
-#define EXTI_C2EMR1_EM7_Msk      (0x1UL << EXTI_C2EMR1_EM7_Pos)                /*!< 0x00000080 */
-#define EXTI_C2EMR1_EM7          EXTI_C2EMR1_EM7_Msk                           /*!< CPU2 Event Mask on line 7 */
-#define EXTI_C2EMR1_EM8_Pos      (8U)
-#define EXTI_C2EMR1_EM8_Msk      (0x1UL << EXTI_C2EMR1_EM8_Pos)                /*!< 0x00000100 */
-#define EXTI_C2EMR1_EM8          EXTI_C2EMR1_EM8_Msk                           /*!< CPU2 Event Mask on line 8 */
-#define EXTI_C2EMR1_EM9_Pos      (9U)
-#define EXTI_C2EMR1_EM9_Msk      (0x1UL << EXTI_C2EMR1_EM9_Pos)                /*!< 0x00000200 */
-#define EXTI_C2EMR1_EM9          EXTI_C2EMR1_EM9_Msk                           /*!< CPU2 Event Mask on line 9 */
-#define EXTI_C2EMR1_EM10_Pos     (10U)
-#define EXTI_C2EMR1_EM10_Msk     (0x1UL << EXTI_C2EMR1_EM10_Pos)               /*!< 0x00000400 */
-#define EXTI_C2EMR1_EM10         EXTI_C2EMR1_EM10_Msk                          /*!< CPU2 Event Mask on line 10 */
-#define EXTI_C2EMR1_EM11_Pos     (11U)
-#define EXTI_C2EMR1_EM11_Msk     (0x1UL << EXTI_C2EMR1_EM11_Pos)               /*!< 0x00000800 */
-#define EXTI_C2EMR1_EM11         EXTI_C2EMR1_EM11_Msk                          /*!< CPU2 Event Mask on line 11 */
-#define EXTI_C2EMR1_EM12_Pos     (12U)
-#define EXTI_C2EMR1_EM12_Msk     (0x1UL << EXTI_C2EMR1_EM12_Pos)               /*!< 0x00001000 */
-#define EXTI_C2EMR1_EM12         EXTI_C2EMR1_EM12_Msk                          /*!< CPU2 Event Mask on line 12 */
-#define EXTI_C2EMR1_EM13_Pos     (13U)
-#define EXTI_C2EMR1_EM13_Msk     (0x1UL << EXTI_C2EMR1_EM13_Pos)               /*!< 0x00002000 */
-#define EXTI_C2EMR1_EM13         EXTI_C2EMR1_EM13_Msk                          /*!< CPU2 Event Mask on line 13 */
-#define EXTI_C2EMR1_EM14_Pos     (14U)
-#define EXTI_C2EMR1_EM14_Msk     (0x1UL << EXTI_C2EMR1_EM14_Pos)               /*!< 0x00004000 */
-#define EXTI_C2EMR1_EM14         EXTI_C2EMR1_EM14_Msk                          /*!< CPU2 Event Mask on line 14 */
-#define EXTI_C2EMR1_EM15_Pos     (15U)
-#define EXTI_C2EMR1_EM15_Msk     (0x1UL << EXTI_C2EMR1_EM15_Pos)               /*!< 0x00008000 */
-#define EXTI_C2EMR1_EM15         EXTI_C2EMR1_EM15_Msk                          /*!< CPU2 Event Mask on line 15 */
-#define EXTI_C2EMR1_EM17_Pos     (17U)
-#define EXTI_C2EMR1_EM17_Msk     (0x1UL << EXTI_C2EMR1_EM17_Pos)               /*!< 0x00020000 */
-#define EXTI_C2EMR1_EM17         EXTI_C2EMR1_EM17_Msk                          /*!< CPU2 Event Mask on line 17 */
-#define EXTI_C2EMR1_EM19_Pos     (19U)
-#define EXTI_C2EMR1_EM19_Msk     (0x1UL << EXTI_C2EMR1_EM19_Pos)               /*!< 0x00080000 */
-#define EXTI_C2EMR1_EM19         EXTI_C2EMR1_EM19_Msk                          /*!< CPU2 Event Mask on line 19 */
-#define EXTI_C2EMR1_EM20_Pos     (20U)
-#define EXTI_C2EMR1_EM20_Msk     (0x1UL << EXTI_C2EMR1_EM20_Pos)               /*!< 0x00100000 */
-#define EXTI_C2EMR1_EM20         EXTI_C2EMR1_EM20_Msk                          /*!< CPU2 Event Mask on line 20 */
-#define EXTI_C2EMR1_EM21_Pos     (21U)
-#define EXTI_C2EMR1_EM21_Msk     (0x1UL << EXTI_C2EMR1_EM21_Pos)               /*!< 0x00200000 */
-#define EXTI_C2EMR1_EM21         EXTI_C2EMR1_EM21_Msk                          /*!< CPU2 Event Mask on line 21 */
-#define EXTI_C2EMR1_EM22_Pos     (22U)
-#define EXTI_C2EMR1_EM22_Msk     (0x1UL << EXTI_C2EMR1_EM22_Pos)               /*!< 0x00400000 */
-#define EXTI_C2EMR1_EM22         EXTI_C2EMR1_EM22_Msk                          /*!< CPU2 Event Mask on line 22 */
-
-/********************  Bits definition for EXTI_C2IMR2 register  **************/
-#define EXTI_C2IMR2_IM34_Pos     (2U)
-#define EXTI_C2IMR2_IM34_Msk     (0x1UL << EXTI_C2IMR2_IM34_Pos)               /*!< 0x00000004 */
-#define EXTI_C2IMR2_IM34         EXTI_C2IMR2_IM34_Msk                          /*!< CPU2 Interrupt Mask on line 34 */
-#define EXTI_C2IMR2_IM36_Pos     (4U)
-#define EXTI_C2IMR2_IM36_Msk     (0x1UL << EXTI_C2IMR2_IM36_Pos)               /*!< 0x00000010 */
-#define EXTI_C2IMR2_IM36         EXTI_C2IMR2_IM36_Msk                          /*!< CPU2 Interrupt Mask on line 36 */
-#define EXTI_C2IMR2_IM37_Pos     (5U)
-#define EXTI_C2IMR2_IM37_Msk     (0x1UL << EXTI_C2IMR2_IM37_Pos)               /*!< 0x00000020 */
-#define EXTI_C2IMR2_IM37         EXTI_C2IMR2_IM37_Msk                          /*!< CPU2 Interrupt Mask on line 37 */
-#define EXTI_C2IMR2_IM38_Pos     (6U)
-#define EXTI_C2IMR2_IM38_Msk     (0x1UL << EXTI_C2IMR2_IM38_Pos)               /*!< 0x00000040 */
-#define EXTI_C2IMR2_IM38         EXTI_C2IMR2_IM38_Msk                          /*!< CPU2 Interrupt Mask on line 38 */
-#define EXTI_C2IMR2_IM39_Pos     (7U)
-#define EXTI_C2IMR2_IM39_Msk     (0x1UL << EXTI_C2IMR2_IM39_Pos)               /*!< 0x00000080 */
-#define EXTI_C2IMR2_IM39         EXTI_C2IMR2_IM39_Msk                          /*!< CPU2 Interrupt Mask on line 39 */
-#define EXTI_C2IMR2_IM40_Pos     (8U)
-#define EXTI_C2IMR2_IM40_Msk     (0x1UL << EXTI_C2IMR2_IM40_Pos)               /*!< 0x00000100 */
-#define EXTI_C2IMR2_IM40         EXTI_C2IMR2_IM40_Msk                          /*!< CPU2 Interrupt Mask on line 40 */
-#define EXTI_C2IMR2_IM41_Pos     (9U)
-#define EXTI_C2IMR2_IM41_Msk     (0x1UL << EXTI_C2IMR2_IM41_Pos)               /*!< 0x00000200 */
-#define EXTI_C2IMR2_IM41         EXTI_C2IMR2_IM41_Msk                          /*!< CPU2 Interrupt Mask on line 41 */
-#define EXTI_C2IMR2_IM42_Pos     (10U)
-#define EXTI_C2IMR2_IM42_Msk     (0x1UL << EXTI_C2IMR2_IM42_Pos)               /*!< 0x00000400 */
-#define EXTI_C2IMR2_IM42         EXTI_C2IMR2_IM42_Msk                          /*!< CPU2 Interrupt Mask on line 42 */
-#define EXTI_C2IMR2_IM43_Pos     (11U)
-#define EXTI_C2IMR2_IM43_Msk     (0x1UL << EXTI_C2IMR2_IM43_Pos)               /*!< 0x00000800 */
-#define EXTI_C2IMR2_IM43         EXTI_C2IMR2_IM43_Msk                          /*!< CPU2 Interrupt Mask on line 43 */
-#define EXTI_C2IMR2_IM44_Pos     (12U)
-#define EXTI_C2IMR2_IM44_Msk     (0x1UL << EXTI_C2IMR2_IM44_Pos)               /*!< 0x00001000 */
-#define EXTI_C2IMR2_IM44         EXTI_C2IMR2_IM44_Msk                          /*!< CPU2 Interrupt Mask on line 44 */
-#define EXTI_C2IMR2_IM45_Pos     (13U)
-#define EXTI_C2IMR2_IM45_Msk     (0x1UL << EXTI_C2IMR2_IM45_Pos)               /*!< 0x00002000 */
-#define EXTI_C2IMR2_IM45         EXTI_C2IMR2_IM45_Msk                          /*!< CPU2 Interrupt Mask on line 45 */
-#define EXTI_C2IMR2_IM46_Pos     (14U)
-#define EXTI_C2IMR2_IM46_Msk     (0x1UL << EXTI_C2IMR2_IM46_Pos)               /*!< 0x00004000 */
-#define EXTI_C2IMR2_IM46         EXTI_C2IMR2_IM46_Msk                          /*!< CPU2 Interrupt Mask on line 46 */
-
-/********************  Bits definition for EXTI_C2EMR2 register  **************/
-#define EXTI_C2EMR2_EM40_Pos     (8U)
-#define EXTI_C2EMR2_EM40_Msk     (0x1UL << EXTI_C2EMR2_EM40_Pos)               /*!< 0x00000100 */
-#define EXTI_C2EMR2_EM40         EXTI_C2EMR2_EM40_Msk                          /*!< CPU2 Event Mask on line 40 */
-#define EXTI_C2EMR2_EM41_Pos     (9U)
-#define EXTI_C2EMR2_EM41_Msk     (0x1UL << EXTI_C2EMR2_EM41_Pos)               /*!< 0x00000200 */
-#define EXTI_C2EMR2_EM41         EXTI_C2EMR2_EM41_Msk                          /*!< CPU2 Event Mask on line 41 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Global Security Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for registers x = 0  ********************/
-#define GTZC_CFGR1_TZIC_Pos                 (0U)
-#define GTZC_CFGR1_TZIC_Msk                 (0x01UL << GTZC_CFGR1_TZIC_Pos)     /*!< 0x00000001 */
-#define GTZC_CFGR1_TZSC_Pos                 (1U)
-#define GTZC_CFGR1_TZSC_Msk                 (0x01UL << GTZC_CFGR1_TZSC_Pos)     /*!< 0x00000002 */
-#define GTZC_CFGR1_AES_Pos                  (2U)
-#define GTZC_CFGR1_AES_Msk                  (0x01UL << GTZC_CFGR1_AES_Pos)      /*!< 0x00000004 */
-#define GTZC_CFGR1_RNG_Pos                  (3U)
-#define GTZC_CFGR1_RNG_Msk                  (0x01UL << GTZC_CFGR1_RNG_Pos)      /*!< 0x00000008 */
-#define GTZC_CFGR1_SUBGHZSPI_Pos            (4U)
-#define GTZC_CFGR1_SUBGHZSPI_Msk            (0x01UL << GTZC_CFGR1_SUBGHZSPI_Pos)/*!< 0x00000010 */
-#define GTZC_CFGR1_PWR_Pos                  (5U)
-#define GTZC_CFGR1_PWR_Msk                  (0x01UL << GTZC_CFGR1_PWR_Pos)      /*!< 0x00000020 */
-#define GTZC_CFGR1_FLASHIF_Pos              (6U)
-#define GTZC_CFGR1_FLASHIF_Msk              (0x01UL << GTZC_CFGR1_FLASHIF_Pos)  /*!< 0x00000040 */
-#define GTZC_CFGR1_DMA1_Pos                 (7U)
-#define GTZC_CFGR1_DMA1_Msk                 (0x01UL << GTZC_CFGR1_DMA1_Pos)     /*!< 0x00000080 */
-#define GTZC_CFGR1_DMA2_Pos                 (8U)
-#define GTZC_CFGR1_DMA2_Msk                 (0x01UL << GTZC_CFGR1_DMA2_Pos)     /*!< 0x00000100 */
-#define GTZC_CFGR1_DMAMUX_Pos               (9U)
-#define GTZC_CFGR1_DMAMUX_Msk               (0x01UL << GTZC_CFGR1_DMAMUX_Pos)   /*!< 0x00000200 */
-#define GTZC_CFGR1_FLASH_Pos                (10U)
-#define GTZC_CFGR1_FLASH_Msk                (0x01UL << GTZC_CFGR1_FLASH_Pos)    /*!< 0x00000400 */
-#define GTZC_CFGR1_SRAM1_Pos                (11U)
-#define GTZC_CFGR1_SRAM1_Msk                (0x01UL << GTZC_CFGR1_SRAM1_Pos)    /*!< 0x00000800 */
-#define GTZC_CFGR1_SRAM2_Pos                (12U)
-#define GTZC_CFGR1_SRAM2_Msk                (0x01UL << GTZC_CFGR1_SRAM2_Pos)    /*!< 0x00001000 */
-#define GTZC_CFGR1_PKA_Pos                  (13U)
-#define GTZC_CFGR1_PKA_Msk                  (0x01UL << GTZC_CFGR1_PKA_Pos)      /*!< 0x00002000 */
-
-/*******************  Bits definition for TZSC_CR register  *******************/
-#define TZSC_CR_LCK_Pos                     (0U)
-#define TZSC_CR_LCK_Msk                     (0x01UL << TZSC_CR_LCK_Pos)         /*!< 0x00000001 */
-
-/*******************  Bits definition for TZSC_SECCFGR1 register  *************/
-#define TZSC_SECCFGR1_ALL_Pos               (0U)
-#define TZSC_SECCFGR1_ALL_Msk               (0x0000200CU)                       /*!< 0x0000200C */
-#define TZSC_SECCFGR1_AESSEC_Pos            GTZC_CFGR1_AES_Pos                  /*!< AES Secure enable */
-#define TZSC_SECCFGR1_AESSEC_Msk            GTZC_CFGR1_AES_Msk                  /*!< 0x00000001 */
-#define TZSC_SECCFGR1_RNGSEC_Pos            GTZC_CFGR1_RNG_Pos                  /*!< RNG Secure enable */
-#define TZSC_SECCFGR1_RNGSEC_Msk            GTZC_CFGR1_RNG_Msk                  /*!< 0x00000002 */
-#define TZSC_SECCFGR1_PKASEC_Pos            GTZC_CFGR1_PKA_Pos                  /*!< PKA Secure enable */
-#define TZSC_SECCFGR1_PKASEC_Msk            GTZC_CFGR1_PKA_Msk                  /*!< 0x00000008 */
-
-/*******************  Bits definition for TZSC_PRIVCFGR1 register  ************/
-#define TZSC_PRIVCFGR1_ALL_Pos              (0U)
-#define TZSC_PRIVCFGR1_ALL_Msk              (0x0000201CU)                       /*!< 0x0000201C */
-#define TZSC_PRIVCFGR1_AESPRIV_Pos          GTZC_CFGR1_AES_Pos                  /*!< AES Privileged enable */
-#define TZSC_PRIVCFGR1_AESPRIV_Msk          GTZC_CFGR1_AES_Msk                  /*!< 0x00000001 */
-#define TZSC_PRIVCFGR1_RNGPRIV_Pos          GTZC_CFGR1_RNG_Pos                  /*!< RNG Privileged enable */
-#define TZSC_PRIVCFGR1_RNGPRIV_Msk          GTZC_CFGR1_RNG_Msk                  /*!< 0x00000002 */
-#define TZSC_PRIVCFGR1_SUBGHZSPIPRIV_Pos    GTZC_CFGR1_SUBGHZSPI_Pos            /*!< SUBGHZSPI Privileged enable */
-#define TZSC_PRIVCFGR1_SUBGHZSPIPRIV_Msk    GTZC_CFGR1_SUBGHZSPI_Msk            /*!< 0x00000004 */
-#define TZSC_PRIVCFGR1_PKAPRIV_Pos          GTZC_CFGR1_PKA_Pos                  /*!< PKA Privileged enable */
-#define TZSC_PRIVCFGR1_PKAPRIV_Msk          GTZC_CFGR1_PKA_Msk                  /*!< 0x00000008 */
-
-/*******************  Bits definition for TZSC_MPCWM1_UPWMR register  *********/
-#define TZSC_MPCWM1_UPWMR_LGTH_Pos          (16U)                                     /*!< User Flash Unprivileged area */
-#define TZSC_MPCWM1_UPWMR_LGTH_Msk          (0x0FFFUL << TZSC_MPCWM1_UPWMR_LGTH_Pos)  /*!< 0x0FFF0000 */
-
-/*******************  Bits definition for TZSC_MPCWM1_UPWWMR register  ********/
-#define TZSC_MPCWM1_UPWWMR_LGTH_Pos         (16U)                                     /*!< User Flash Flash Unprivileged Writable area */
-#define TZSC_MPCWM1_UPWWMR_LGTH_Msk         (0x0FFFUL << TZSC_MPCWM1_UPWWMR_LGTH_Pos) /*!< 0x0FFF0000 */
-
-/*******************  Bits definition for TZSC_MPCWM2_UPWMR register  *********/
-#define TZSC_MPCWM2_UPWMR_LGTH_Pos          (16U)                                     /*!< User SRAM1 Unprivileged area */
-#define TZSC_MPCWM2_UPWMR_LGTH_Msk          (0x0FFFUL << TZSC_MPCWM2_UPWMR_LGTH_Pos)  /*!< 0x0FFF0000 */
-
-/*******************  Bits definition for TZSC_MPCWM3_UPWMR register  *********/
-#define TZSC_MPCWM3_UPWMR_LGTH_Pos          (16U)                                     /*!< User Flash Unprivileged area */
-#define TZSC_MPCWM3_UPWMR_LGTH_Msk          (0x0FFFUL << TZSC_MPCWM3_UPWMR_LGTH_Pos)  /*!< 0x0FFF0000 */
-
-
-/*******************  Bits definition for TZIC_IMR0 register  *****************/
-#define TZIC_IER1_ALL_Msk                   0x00003FFFu
-#define TZIC_IER1_TZICIE_Pos                GTZC_CFGR1_TZIC_Pos
-#define TZIC_IER1_TZICIE_Msk                GTZC_CFGR1_TZIC_Msk                  /*!< 0x00000001 */
-#define TZIC_IER1_TZSCIE_Pos                GTZC_CFGR1_TZSC_Pos
-#define TZIC_IER1_TZSCIE_Msk                GTZC_CFGR1_TZSC_Msk                  /*!< 0x00000002 */
-#define TZIC_IER1_AESIE_Pos                 GTZC_CFGR1_AES_Pos
-#define TZIC_IER1_AESIE_Msk                 GTZC_CFGR1_AES_Msk                   /*!< 0x00000004 */
-#define TZIC_IER1_RNGIE_Pos                 GTZC_CFGR1_RNG_Pos
-#define TZIC_IER1_RNGIE_Msk                 GTZC_CFGR1_RNG_Msk                   /*!< 0x00000008 */
-#define TZIC_IER1_SUBGHZSPIIE_Pos           GTZC_CFGR1_SUBGHZSPI_Pos
-#define TZIC_IER1_SUBGHZSPIIE_Msk           GTZC_CFGR1_SUBGHZSPI_Msk             /*!< 0x00000010 */
-#define TZIC_IER1_PWRIE_Pos                 GTZC_CFGR1_PWR_Pos
-#define TZIC_IER1_PWRIE_Msk                 GTZC_CFGR1_PWR_Msk                   /*!< 0x00000020 */
-#define TZIC_IER1_FLASHIFIE_Pos             GTZC_CFGR1_FLASHIF_Pos
-#define TZIC_IER1_FLASHIFIE_Msk             GTZC_CFGR1_FLASHIF_Msk               /*!< 0x00000040 */
-#define TZIC_IER1_DMA1IE_Pos                GTZC_CFGR1_DMA1_Pos
-#define TZIC_IER1_DMA1IE_Msk                GTZC_CFGR1_DMA1_Msk                  /*!< 0x00000080 */
-#define TZIC_IER1_DMA2IE_Pos                GTZC_CFGR1_DMA2_Pos
-#define TZIC_IER1_DMA2IE_Msk                GTZC_CFGR1_DMA2_Msk                  /*!< 0x00000100 */
-#define TZIC_IER1_DMAMUXIE_Pos              GTZC_CFGR1_DMAMUX_Pos
-#define TZIC_IER1_DMAMUXIE_Msk              GTZC_CFGR1_DMAMUX_Msk                /*!< 0x00000200 */
-#define TZIC_IER1_FLASHIE_Pos               GTZC_CFGR1_FLASH_Pos
-#define TZIC_IER1_FLASHIE_Msk               GTZC_CFGR1_FLASH_Msk                 /*!< 0x00000400 */
-#define TZIC_IER1_SRAM1IE_Pos               GTZC_CFGR1_SRAM1_Pos
-#define TZIC_IER1_SRAM1IE_Msk               GTZC_CFGR1_SRAM1_Msk                 /*!< 0x00000800 */
-#define TZIC_IER1_SRAM2IE_Pos               GTZC_CFGR1_SRAM2_Pos
-#define TZIC_IER1_SRAM2IE_Msk               GTZC_CFGR1_SRAM2_Msk                 /*!< 0x00001000 */
-#define TZIC_IER1_PKAIE_Pos                 GTZC_CFGR1_PKA_Pos
-#define TZIC_IER1_PKAIE_Msk                 GTZC_CFGR1_PKA_Msk                   /*!< 0x00002000 */
-
-/*******************  Bits definition for TZIC_MISR1 register  ****************/
-#define TZIC_MISR1_TZICMF_Pos               GTZC_CFGR1_TZIC_Pos
-#define TZIC_MISR1_TZICMF_Msk               GTZC_CFGR1_TZIC_Msk                  /*!< 0x00000001 */
-#define TZIC_MISR1_TZSCMF_Pos               GTZC_CFGR1_TZSC_Pos
-#define TZIC_MISR1_TZSCMF_Msk               GTZC_CFGR1_TZSC_Msk                  /*!< 0x00000002 */
-#define TZIC_MISR1_AESMF_Pos                GTZC_CFGR1_AES_Pos
-#define TZIC_MISR1_AESMF_Msk                GTZC_CFGR1_AES_Msk                   /*!< 0x00000004 */
-#define TZIC_MISR1_RNGMF_Pos                GTZC_CFGR1_RNG_Pos
-#define TZIC_MISR1_RNGMF_Msk                GTZC_CFGR1_RNG_Msk                   /*!< 0x00000008 */
-#define TZIC_MISR1_SUBGHZSPIMF_Pos          GTZC_CFGR1_SUBGHZSPI_Pos
-#define TZIC_MISR1_SUBGHZSPIMF_Msk          GTZC_CFGR1_SUBGHZSPI_Msk             /*!< 0x00000010 */
-#define TZIC_MISR1_PWRMF_Pos                GTZC_CFGR1_PWR_Pos
-#define TZIC_MISR1_PWRMF_Msk                GTZC_CFGR1_PWR_Msk                   /*!< 0x00000020 */
-#define TZIC_MISR1_FLASHIFMF_Pos            GTZC_CFGR1_FLASHIF_Pos
-#define TZIC_MISR1_FLASHIFMF_Msk            GTZC_CFGR1_FLASHIF_Msk               /*!< 0x00000040 */
-#define TZIC_MISR1_DMA1MF_Pos               GTZC_CFGR1_DMA1_Pos
-#define TZIC_MISR1_DMA1MF_Msk               GTZC_CFGR1_DMA1_Msk                  /*!< 0x00000080 */
-#define TZIC_MISR1_DMA2MF_Pos               GTZC_CFGR1_DMA2_Pos
-#define TZIC_MISR1_DMA2MF_Msk               GTZC_CFGR1_DMA2_Msk                  /*!< 0x00000100 */
-#define TZIC_MISR1_DMAMUXMF_Pos             GTZC_CFGR1_DMAMUX_Pos
-#define TZIC_MISR1_DMAMUXMF_Msk             GTZC_CFGR1_DMAMUX_Msk                /*!< 0x00000200 */
-#define TZIC_MISR1_FLASHMF_Pos              GTZC_CFGR1_FLASH_Pos
-#define TZIC_MISR1_FLASHMF_Msk              GTZC_CFGR1_FLASH_Msk                 /*!< 0x00000400 */
-#define TZIC_MISR1_SRAM1MF_Pos              GTZC_CFGR1_SRAM1_Pos
-#define TZIC_MISR1_SRAM1MF_Msk              GTZC_CFGR1_SRAM1_Msk                 /*!< 0x00000800 */
-#define TZIC_MISR1_SRAM2MF_Pos              GTZC_CFGR1_SRAM2_Pos
-#define TZIC_MISR1_SRAM2MF_Msk              GTZC_CFGR1_SRAM2_Msk                 /*!< 0x00001000 */
-#define TZIC_MISR1_PKAMF_Pos                GTZC_CFGR1_PKA_Pos
-#define TZIC_MISR1_PKAMF_Msk                GTZC_CFGR1_PKA_Msk                   /*!< 0x00002000 */
-
-/*******************  Bits definition for TZIC_IFCR0 register  ****************/
-#define TZIC_ICR1_TZICCF_Pos                GTZC_CFGR1_TZIC_Pos
-#define TZIC_ICR1_TZICCF_Msk                GTZC_CFGR1_TZIC_Msk                  /*!< 0x00000001 */
-#define TZIC_ICR1_TZSCCF_Pos                GTZC_CFGR1_TZSC_Pos
-#define TZIC_ICR1_TZSCCF_Msk                GTZC_CFGR1_TZSC_Msk                  /*!< 0x00000002 */
-#define TZIC_ICR1_AESCF_Pos                 GTZC_CFGR1_AES_Pos
-#define TZIC_ICR1_AESCF_Msk                 GTZC_CFGR1_AES_Msk                   /*!< 0x00000004 */
-#define TZIC_ICR1_RNGCF_Pos                 GTZC_CFGR1_RNG_Pos
-#define TZIC_ICR1_RNGCF_Msk                 GTZC_CFGR1_RNG_Msk                   /*!< 0x00000008 */
-#define TZIC_ICR1_SUBGHZSPICF_Pos           GTZC_CFGR1_SUBGHZSPI_Pos
-#define TZIC_ICR1_SUBGHZSPICF_Msk           GTZC_CFGR1_SUBGHZSPI_Msk             /*!< 0x00000010 */
-#define TZIC_ICR1_PWRCF_Pos                 GTZC_CFGR1_PWR_Pos
-#define TZIC_ICR1_PWRCF_Msk                 GTZC_CFGR1_PWR_Msk                   /*!< 0x00000020 */
-#define TZIC_ICR1_FLASHIFCF_Pos             GTZC_CFGR1_FLASHIF_Pos
-#define TZIC_ICR1_FLASHIFCF_Msk             GTZC_CFGR1_FLASHIF_Msk               /*!< 0x00000040 */
-#define TZIC_ICR1_DMA1CF_Pos                GTZC_CFGR1_DMA1_Pos
-#define TZIC_ICR1_DMA1CF_Msk                GTZC_CFGR1_DMA1_Msk                  /*!< 0x00000080 */
-#define TZIC_ICR1_DMA2CF_Pos                GTZC_CFGR1_DMA2_Pos
-#define TZIC_ICR1_DMA2CF_Msk                GTZC_CFGR1_DMA2_Msk                  /*!< 0x00000100 */
-#define TZIC_ICR1_DMAMUXCF_Pos              GTZC_CFGR1_DMAMUX_Pos
-#define TZIC_ICR1_DMAMUXCF_Msk              GTZC_CFGR1_DMAMUX_Msk                /*!< 0x00000200 */
-#define TZIC_ICR1_FLASHCF_Pos               GTZC_CFGR1_FLASH_Pos
-#define TZIC_ICR1_FLASHCF_Msk               GTZC_CFGR1_FLASH_Msk                 /*!< 0x00000400 */
-#define TZIC_ICR1_SRAM1CF_Pos               GTZC_CFGR1_SRAM1_Pos
-#define TZIC_ICR1_SRAM1CF_Msk               GTZC_CFGR1_SRAM1_Msk                 /*!< 0x00000800 */
-#define TZIC_ICR1_SRAM2CF_Pos               GTZC_CFGR1_SRAM2_Pos
-#define TZIC_ICR1_SRAM2CF_Msk               GTZC_CFGR1_SRAM2_Msk                 /*!< 0x00001000 */
-#define TZIC_ICR1_PKACF_Pos                 GTZC_CFGR1_PKA_Pos
-#define TZIC_ICR1_PKACF_Msk                 GTZC_CFGR1_PKA_Msk                   /*!< 0x00002000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY_Pos               (0U)
-#define FLASH_ACR_LATENCY_Msk               (0x7UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000007 */
-#define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk              /*!< Latency                                             */
-#define FLASH_ACR_LATENCY_0                 (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY_1                 (0x2UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN_Pos                (8U)
-#define FLASH_ACR_PRFTEN_Msk                (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000100 */
-#define FLASH_ACR_PRFTEN                    FLASH_ACR_PRFTEN_Msk               /*!< Prefetch enable                                     */
-#define FLASH_ACR_ICEN_Pos                  (9U)
-#define FLASH_ACR_ICEN_Msk                  (0x1UL << FLASH_ACR_ICEN_Pos)      /*!< 0x00000200 */
-#define FLASH_ACR_ICEN                      FLASH_ACR_ICEN_Msk                 /*!< Instruction cache enable                            */
-#define FLASH_ACR_DCEN_Pos                  (10U)
-#define FLASH_ACR_DCEN_Msk                  (0x1UL << FLASH_ACR_DCEN_Pos)      /*!< 0x00000400 */
-#define FLASH_ACR_DCEN                      FLASH_ACR_DCEN_Msk                 /*!< Data cache enable                                   */
-#define FLASH_ACR_ICRST_Pos                 (11U)
-#define FLASH_ACR_ICRST_Msk                 (0x1UL << FLASH_ACR_ICRST_Pos)     /*!< 0x00000800 */
-#define FLASH_ACR_ICRST                     FLASH_ACR_ICRST_Msk                /*!< Instruction cache reset                             */
-#define FLASH_ACR_DCRST_Pos                 (12U)
-#define FLASH_ACR_DCRST_Msk                 (0x1UL << FLASH_ACR_DCRST_Pos)     /*!< 0x00001000 */
-#define FLASH_ACR_DCRST                     FLASH_ACR_DCRST_Msk                /*!< Data cache reset                                    */
-#define FLASH_ACR_PES_Pos                   (15U)
-#define FLASH_ACR_PES_Msk                   (0x1UL << FLASH_ACR_PES_Pos)       /*!< 0x00008000 */
-#define FLASH_ACR_PES                       FLASH_ACR_PES_Msk                  /*!< Program/erase suspend request                       */
-#define FLASH_ACR_EMPTY_Pos                 (16U)
-#define FLASH_ACR_EMPTY_Msk                 (0x1UL << FLASH_ACR_EMPTY_Pos)     /*!< 0x00010000 */
-#define FLASH_ACR_EMPTY                     FLASH_ACR_EMPTY_Msk                /*!< Flash use area empty                                */
-
-/*******************  Bits definition for FLASH_ACR2 register  ****************/
-#define FLASH_ACR2_PRIVMODE_Pos             (0U)
-#define FLASH_ACR2_PRIVMODE_Msk             (0x1UL << FLASH_ACR2_PRIVMODE_Pos) /*!< 0x00000001 */
-#define FLASH_ACR2_PRIVMODE                 FLASH_ACR2_PRIVMODE_Msk            /*!< CFI privileged mode                                 */
-#define FLASH_ACR2_HDPADIS_Pos              (1U)
-#define FLASH_ACR2_HDPADIS_Msk              (0x1UL << FLASH_ACR2_HDPADIS_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR2_HDPADIS                  FLASH_ACR2_HDPADIS_Msk               /*!< Flash User Hide Protection area access disable    */
-#define FLASH_ACR2_C2SWDBGEN_Pos            (2U)
-#define FLASH_ACR2_C2SWDBGEN_Msk            (0x1UL << FLASH_ACR2_C2SWDBGEN_Pos)/*!< 0x00000004 */
-#define FLASH_ACR2_C2SWDBGEN                FLASH_ACR2_C2SWDBGEN_Msk           /*!< CPU2 Software debug enable                          */
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP_Pos                    (0U)
-#define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                   /*!< End of Operation                                    */
-#define FLASH_SR_OPERR_Pos                  (1U)
-#define FLASH_SR_OPERR_Msk                  (0x1UL << FLASH_SR_OPERR_Pos)      /*!< 0x00000002 */
-#define FLASH_SR_OPERR                      FLASH_SR_OPERR_Msk                 /*!< Operation error                                     */
-#define FLASH_SR_PROGERR_Pos                (3U)
-#define FLASH_SR_PROGERR_Msk                (0x1UL << FLASH_SR_PROGERR_Pos)    /*!< 0x00000008 */
-#define FLASH_SR_PROGERR                    FLASH_SR_PROGERR_Msk               /*!< Programming error                                   */
-#define FLASH_SR_WRPERR_Pos                 (4U)
-#define FLASH_SR_WRPERR_Msk                 (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000010 */
-#define FLASH_SR_WRPERR                     FLASH_SR_WRPERR_Msk                /*!< Write protection error                              */
-#define FLASH_SR_PGAERR_Pos                 (5U)
-#define FLASH_SR_PGAERR_Msk                 (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000020 */
-#define FLASH_SR_PGAERR                     FLASH_SR_PGAERR_Msk                /*!< Programming alignment error                         */
-#define FLASH_SR_SIZERR_Pos                 (6U)
-#define FLASH_SR_SIZERR_Msk                 (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000040 */
-#define FLASH_SR_SIZERR                     FLASH_SR_SIZERR_Msk                /*!< Size error                                          */
-#define FLASH_SR_PGSERR_Pos                 (7U)
-#define FLASH_SR_PGSERR_Msk                 (0x1UL << FLASH_SR_PGSERR_Pos)     /*!< 0x00000080 */
-#define FLASH_SR_PGSERR                     FLASH_SR_PGSERR_Msk                /*!< Programming sequence error                          */
-#define FLASH_SR_MISERR_Pos                 (8U)
-#define FLASH_SR_MISERR_Msk                 (0x1UL << FLASH_SR_MISERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_MISERR                     FLASH_SR_MISERR_Msk                /*!< Fast programming data miss error                    */
-#define FLASH_SR_FASTERR_Pos                (9U)
-#define FLASH_SR_FASTERR_Msk                (0x1UL << FLASH_SR_FASTERR_Pos)    /*!< 0x00000200 */
-#define FLASH_SR_FASTERR                    FLASH_SR_FASTERR_Msk               /*!< Fast programming error                              */
-#define FLASH_SR_OPTNV_Pos                  (13U)
-#define FLASH_SR_OPTNV_Msk                  (0x1UL << FLASH_SR_OPTNV_Pos)     /*!< 0x00002000 */
-#define FLASH_SR_OPTNV                      FLASH_SR_OPTNV_Msk                /*!< User option OPTVAL indication                       */
-#define FLASH_SR_RDERR_Pos                  (14U)
-#define FLASH_SR_RDERR_Msk                  (0x1UL << FLASH_SR_RDERR_Pos)      /*!< 0x00004000 */
-#define FLASH_SR_RDERR                      FLASH_SR_RDERR_Msk                 /*!< PCROP read error                                    */
-#define FLASH_SR_OPTVERR_Pos                (15U)
-#define FLASH_SR_OPTVERR_Msk                (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00008000 */
-#define FLASH_SR_OPTVERR                    FLASH_SR_OPTVERR_Msk               /*!< Option validity error                               */
-#define FLASH_SR_BSY_Pos                    (16U)
-#define FLASH_SR_BSY_Msk                    (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00010000 */
-#define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                   /*!< Flash Busy                                          */
-#define FLASH_SR_CFGBSY_Pos                 (18U)
-#define FLASH_SR_CFGBSY_Msk                 (0x1UL << FLASH_SR_CFGBSY_Pos)     /*!< 0x00040000 */
-#define FLASH_SR_CFGBSY                     FLASH_SR_CFGBSY_Msk                /*!< Programming or erase configuration busy             */
-#define FLASH_SR_PESD_Pos                   (19U)
-#define FLASH_SR_PESD_Msk                   (0x1UL << FLASH_SR_PESD_Pos)       /*!< 0x00080000 */
-#define FLASH_SR_PESD                       FLASH_SR_PESD_Msk                  /*!< Programming/erase operation suspended               */
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG_Pos                     (0U)
-#define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)         /*!< 0x00000001 */
-#define FLASH_CR_PG                         FLASH_CR_PG_Msk                    /*!< Flash programming                                   */
-#define FLASH_CR_PER_Pos                    (1U)
-#define FLASH_CR_PER_Msk                    (0x1UL << FLASH_CR_PER_Pos)        /*!< 0x00000002 */
-#define FLASH_CR_PER                        FLASH_CR_PER_Msk                   /*!< Page erase                                          */
-#define FLASH_CR_MER_Pos                    (2U)
-#define FLASH_CR_MER_Msk                    (0x1UL << FLASH_CR_MER_Pos)        /*!< 0x00000004 */
-#define FLASH_CR_MER                        FLASH_CR_MER_Msk                   /*!< Mass erase                                          */
-#define FLASH_CR_PNB_Pos                    (3U)
-#define FLASH_CR_PNB_Msk                    (0x7FUL << FLASH_CR_PNB_Pos)       /*!< 0x000003F8 */
-#define FLASH_CR_PNB                        FLASH_CR_PNB_Msk                   /*!< Page number selection mask                          */
-#define FLASH_CR_STRT_Pos                   (16U)
-#define FLASH_CR_STRT_Msk                   (0x1UL << FLASH_CR_STRT_Pos)       /*!< 0x00010000 */
-#define FLASH_CR_STRT                       FLASH_CR_STRT_Msk                  /*!< Start an erase operation                            */
-#define FLASH_CR_OPTSTRT_Pos                (17U)
-#define FLASH_CR_OPTSTRT_Msk                (0x1UL << FLASH_CR_OPTSTRT_Pos)    /*!< 0x00020000 */
-#define FLASH_CR_OPTSTRT                    FLASH_CR_OPTSTRT_Msk               /*!< Options modification start                          */
-#define FLASH_CR_FSTPG_Pos                  (18U)
-#define FLASH_CR_FSTPG_Msk                  (0x1UL << FLASH_CR_FSTPG_Pos)      /*!< 0x00040000 */
-#define FLASH_CR_FSTPG                      FLASH_CR_FSTPG_Msk                 /*!< Fast programming                                    */
-#define FLASH_CR_EOPIE_Pos                  (24U)
-#define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)      /*!< 0x01000000 */
-#define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                 /*!< End of operation interrupt enable                   */
-#define FLASH_CR_ERRIE_Pos                  (25U)
-#define FLASH_CR_ERRIE_Msk                  (0x1UL << FLASH_CR_ERRIE_Pos)      /*!< 0x02000000 */
-#define FLASH_CR_ERRIE                      FLASH_CR_ERRIE_Msk                 /*!< Error interrupt enable                              */
-#define FLASH_CR_RDERRIE_Pos                (26U)
-#define FLASH_CR_RDERRIE_Msk                (0x1UL << FLASH_CR_RDERRIE_Pos)    /*!< 0x04000000 */
-#define FLASH_CR_RDERRIE                    FLASH_CR_RDERRIE_Msk               /*!< PCROP read error interrupt enable                   */
-#define FLASH_CR_OBL_LAUNCH_Pos             (27U)
-#define FLASH_CR_OBL_LAUNCH_Msk             (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
-#define FLASH_CR_OBL_LAUNCH                 FLASH_CR_OBL_LAUNCH_Msk            /*!< Force the option bute loading                       */
-#define FLASH_CR_OPTLOCK_Pos                (30U)
-#define FLASH_CR_OPTLOCK_Msk                (0x1UL << FLASH_CR_OPTLOCK_Pos)    /*!< 0x40000000 */
-#define FLASH_CR_OPTLOCK                    FLASH_CR_OPTLOCK_Msk               /*!< Options lock                                        */
-#define FLASH_CR_LOCK_Pos                   (31U)
-#define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)       /*!< 0x80000000 */
-#define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                  /*!< Flash control register lock                         */
-
-/*******************  Bits definition for FLASH_ECCR register  ****************/
-#define FLASH_ECCR_ADDR_ECC_Pos             (0U)
-#define FLASH_ECCR_ADDR_ECC_Msk             (0x1FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0001FFFF */
-#define FLASH_ECCR_ADDR_ECC                 FLASH_ECCR_ADDR_ECC_Msk            /*!< double-word address ECC fail                        */
-#define FLASH_ECCR_SYSF_ECC_Pos             (20U)
-#define FLASH_ECCR_SYSF_ECC_Msk             (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
-#define FLASH_ECCR_SYSF_ECC                 FLASH_ECCR_SYSF_ECC_Msk            /*!< System flash ECC fail                               */
-#define FLASH_ECCR_ECCCIE_Pos               (24U)
-#define FLASH_ECCR_ECCCIE_Msk               (0x1UL << FLASH_ECCR_ECCCIE_Pos)   /*!< 0x01000000 */
-#define FLASH_ECCR_ECCCIE                   FLASH_ECCR_ECCCIE_Msk              /*!< ECC correction interrupt enable                     */
-#define FLASH_ECCR_CPUID_Pos                (26U)
-#define FLASH_ECCR_CPUID_Msk                (0x7UL << FLASH_ECCR_CPUID_Pos)    /*!< 0x1C000000 */
-#define FLASH_ECCR_CPUID                    FLASH_ECCR_CPUID_Msk               /*!< CPU identification                                  */
-#define FLASH_ECCR_ECCC_Pos                 (30U)
-#define FLASH_ECCR_ECCC_Msk                 (0x1UL << FLASH_ECCR_ECCC_Pos)     /*!< 0x40000000 */
-#define FLASH_ECCR_ECCC                     FLASH_ECCR_ECCC_Msk                /*!< ECC correction                                      */
-#define FLASH_ECCR_ECCD_Pos                 (31U)
-#define FLASH_ECCR_ECCD_Msk                 (0x1UL << FLASH_ECCR_ECCD_Pos)     /*!< 0x80000000 */
-#define FLASH_ECCR_ECCD                     FLASH_ECCR_ECCD_Msk                /*!< ECC detection                                       */
-
-/*******************  Bits definition for FLASH_OPTR register  ****************/
-#define FLASH_OPTR_RDP_Pos                  (0U)
-#define FLASH_OPTR_RDP_Msk                  (0xFFUL << FLASH_OPTR_RDP_Pos)     /*!< 0x000000FF */
-#define FLASH_OPTR_RDP                      FLASH_OPTR_RDP_Msk                 /*!< Read protection level                               */
-#define FLASH_OPTR_ESE_Pos                  (8U)
-#define FLASH_OPTR_ESE_Msk                  (0x1UL << FLASH_OPTR_ESE_Pos)      /*!< 0x00000100 */
-#define FLASH_OPTR_ESE                      FLASH_OPTR_ESE_Msk                 /*!< Security enable                                     */
-#define FLASH_OPTR_BOR_LEV_Pos              (9U)
-#define FLASH_OPTR_BOR_LEV_Msk              (0x7UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000E00 */
-#define FLASH_OPTR_BOR_LEV                  FLASH_OPTR_BOR_LEV_Msk             /*!< BOR reset level mask                                */
-#define FLASH_OPTR_BOR_LEV_0                (0x1UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000200 */
-#define FLASH_OPTR_BOR_LEV_1                (0x2UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000400 */
-#define FLASH_OPTR_BOR_LEV_2                (0x4UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000800 */
-#define FLASH_OPTR_nRST_STOP_Pos            (12U)
-#define FLASH_OPTR_nRST_STOP_Msk            (0x1UL << FLASH_OPTR_nRST_STOP_Pos)/*!< 0x00001000 */
-#define FLASH_OPTR_nRST_STOP                FLASH_OPTR_nRST_STOP_Msk           /*!< Reset option in Stop mode                           */
-#define FLASH_OPTR_nRST_STDBY_Pos           (13U)
-#define FLASH_OPTR_nRST_STDBY_Msk           (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)/*!< 0x00002000 */
-#define FLASH_OPTR_nRST_STDBY               FLASH_OPTR_nRST_STDBY_Msk          /*!< Reset option in Standby mode                        */
-#define FLASH_OPTR_nRST_SHDW_Pos            (14U)
-#define FLASH_OPTR_nRST_SHDW_Msk            (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)/*!< 0x00004000 */
-#define FLASH_OPTR_nRST_SHDW                FLASH_OPTR_nRST_SHDW_Msk           /*!< Reset option in Shutdown mode                       */
-#define FLASH_OPTR_IWDG_SW_Pos              (16U)
-#define FLASH_OPTR_IWDG_SW_Msk              (0x1UL << FLASH_OPTR_IWDG_SW_Pos)  /*!< 0x00010000 */
-#define FLASH_OPTR_IWDG_SW                  FLASH_OPTR_IWDG_SW_Msk             /*!< Independent watchdog selection                      */
-#define FLASH_OPTR_IWDG_STOP_Pos            (17U)
-#define FLASH_OPTR_IWDG_STOP_Msk            (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)/*!< 0x00020000 */
-#define FLASH_OPTR_IWDG_STOP                FLASH_OPTR_IWDG_STOP_Msk           /*!< Independent watchdog counter option in Stop mode    */
-#define FLASH_OPTR_IWDG_STDBY_Pos           (18U)
-#define FLASH_OPTR_IWDG_STDBY_Msk           (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)/*!< 0x00040000 */
-#define FLASH_OPTR_IWDG_STDBY               FLASH_OPTR_IWDG_STDBY_Msk          /*!< Independent watchdog counter option in Standby mode */
-#define FLASH_OPTR_WWDG_SW_Pos              (19U)
-#define FLASH_OPTR_WWDG_SW_Msk              (0x1UL << FLASH_OPTR_WWDG_SW_Pos)  /*!< 0x00080000 */
-#define FLASH_OPTR_WWDG_SW                  FLASH_OPTR_WWDG_SW_Msk             /*!< Window watchdog selection                           */
-#define FLASH_OPTR_nBOOT1_Pos               (23U)
-#define FLASH_OPTR_nBOOT1_Msk               (0x1UL << FLASH_OPTR_nBOOT1_Pos)   /*!< 0x00800000 */
-#define FLASH_OPTR_nBOOT1                   FLASH_OPTR_nBOOT1_Msk              /*!< Boot Configuration                                  */
-#define FLASH_OPTR_SRAM2_PE_Pos             (24U)
-#define FLASH_OPTR_SRAM2_PE_Msk             (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
-#define FLASH_OPTR_SRAM2_PE                 FLASH_OPTR_SRAM2_PE_Msk            /*!< SRAM2 parity check enable                           */
-#define FLASH_OPTR_SRAM_RST_Pos             (25U)
-#define FLASH_OPTR_SRAM_RST_Msk             (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x02000000 */
-#define FLASH_OPTR_SRAM_RST                 FLASH_OPTR_SRAM_RST_Msk            /*!< SRAM1 and SRAM2 erase option when system reset      */
-#define FLASH_OPTR_nSWBOOT0_Pos             (26U)
-#define FLASH_OPTR_nSWBOOT0_Msk             (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
-#define FLASH_OPTR_nSWBOOT0                 FLASH_OPTR_nSWBOOT0_Msk            /*!< Software BOOT0                                      */
-#define FLASH_OPTR_nBOOT0_Pos               (27U)
-#define FLASH_OPTR_nBOOT0_Msk               (0x1UL << FLASH_OPTR_nBOOT0_Pos)   /*!< 0x08000000 */
-#define FLASH_OPTR_nBOOT0                   FLASH_OPTR_nBOOT0_Msk              /*!< BOOT0 option bit                                    */
-#define FLASH_OPTR_BOOT_LOCK_Pos            (30U)
-#define FLASH_OPTR_BOOT_LOCK_Msk            (0x1UL << FLASH_OPTR_BOOT_LOCK_Pos)/*!< 0x40000000 */
-#define FLASH_OPTR_BOOT_LOCK                FLASH_OPTR_BOOT_LOCK_Msk           /*!< CPU1 Boot Lock enable option bit                    */
-#define FLASH_OPTR_C2BOOT_LOCK_Pos          (31U)
-#define FLASH_OPTR_C2BOOT_LOCK_Msk          (0x1UL << FLASH_OPTR_C2BOOT_LOCK_Pos)/*!< 0x80000000 */
-#define FLASH_OPTR_C2BOOT_LOCK              FLASH_OPTR_C2BOOT_LOCK_Msk           /*!< CPU2 Boot Lock enable option bit                  */
-
-/******************  Bits definition for FLASH_PCROP1ASR register  ************/
-#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos    (0U)
-#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk    (0xFFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1ASR_PCROP1A_STRT        FLASH_PCROP1ASR_PCROP1A_STRT_Msk   /*!< PCROP area A start offset                           */
-
-/******************  Bits definition for FLASH_PCROP1AER register  ************/
-#define FLASH_PCROP1AER_PCROP1A_END_Pos     (0U)
-#define FLASH_PCROP1AER_PCROP1A_END_Msk     (0xFFUL << FLASH_PCROP1AER_PCROP1A_END_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1AER_PCROP1A_END         FLASH_PCROP1AER_PCROP1A_END_Msk    /*!< PCROP area A end offset                             */
-#define FLASH_PCROP1AER_PCROP_RDP_Pos       (31U)
-#define FLASH_PCROP1AER_PCROP_RDP_Msk       (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos)/*!< 0x80000000 */
-#define FLASH_PCROP1AER_PCROP_RDP           FLASH_PCROP1AER_PCROP_RDP_Msk      /*!< PCROP area preserved when RDP level decreased       */
-
-/******************  Bits definition for FLASH_WRP1AR register  ***************/
-#define FLASH_WRP1AR_WRP1A_STRT_Pos         (0U)
-#define FLASH_WRP1AR_WRP1A_STRT_Msk         (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
-#define FLASH_WRP1AR_WRP1A_STRT             FLASH_WRP1AR_WRP1A_STRT_Msk        /*!< WRP area A start offset                             */
-#define FLASH_WRP1AR_WRP1A_END_Pos          (16U)
-#define FLASH_WRP1AR_WRP1A_END_Msk          (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
-#define FLASH_WRP1AR_WRP1A_END              FLASH_WRP1AR_WRP1A_END_Msk         /*!< WRP area A end offset                               */
-
-/******************  Bits definition for FLASH_WRP1BR register  ***************/
-#define FLASH_WRP1BR_WRP1B_STRT_Pos         (0U)
-#define FLASH_WRP1BR_WRP1B_STRT_Msk         (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
-#define FLASH_WRP1BR_WRP1B_STRT             FLASH_WRP1BR_WRP1B_STRT_Msk        /*!< WRP area B start offset                             */
-#define FLASH_WRP1BR_WRP1B_END_Pos          (16U)
-#define FLASH_WRP1BR_WRP1B_END_Msk          (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
-#define FLASH_WRP1BR_WRP1B_END              FLASH_WRP1BR_WRP1B_END_Msk         /*!< WRP area B end offset                               */
-
-/******************  Bits definition for FLASH_PCROP1BSR register  ************/
-#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos    (0U)
-#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk    (0xFFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1BSR_PCROP1B_STRT        FLASH_PCROP1BSR_PCROP1B_STRT_Msk   /*!< PCROP area B start offset                           */
-
-/******************  Bits definition for FLASH_PCROP1BER register  ************/
-#define FLASH_PCROP1BER_PCROP1B_END_Pos     (0U)
-#define FLASH_PCROP1BER_PCROP1B_END_Msk     (0xFFUL << FLASH_PCROP1BER_PCROP1B_END_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1BER_PCROP1B_END         FLASH_PCROP1BER_PCROP1B_END_Msk    /*!< PCROP area B end offset                             */
-
-/******************  Bits definition for FLASH_IPCCBR register  ************/
-#define FLASH_IPCCBR_IPCCDBA_Pos            (0U)
-#define FLASH_IPCCBR_IPCCDBA_Msk            (0x3FFFUL << FLASH_IPCCBR_IPCCDBA_Pos)/*!< 0x00003FFF */
-#define FLASH_IPCCBR_IPCCDBA                FLASH_IPCCBR_IPCCDBA_Msk           /*!< IPCC data buffer base address                       */
-
-/******************  Bits definition for FLASH_C2ACR register  ************/
-#define FLASH_C2ACR_PRFTEN_Pos              (8U)
-#define FLASH_C2ACR_PRFTEN_Msk              (0x1UL << FLASH_C2ACR_PRFTEN_Pos) /*!< 0x00000100 */
-#define FLASH_C2ACR_PRFTEN                  FLASH_C2ACR_PRFTEN_Msk            /*!< CPU2 Prefetch enable                                 */
-#define FLASH_C2ACR_ICEN_Pos                (9U)
-#define FLASH_C2ACR_ICEN_Msk                (0x1UL << FLASH_C2ACR_ICEN_Pos)   /*!< 0x00000200 */
-#define FLASH_C2ACR_ICEN                    FLASH_C2ACR_ICEN_Msk              /*!< CPU2 Instruction cache enable                        */
-#define FLASH_C2ACR_ICRST_Pos               (11U)
-#define FLASH_C2ACR_ICRST_Msk               (0x1UL << FLASH_C2ACR_ICRST_Pos)  /*!< 0x00000800 */
-#define FLASH_C2ACR_ICRST                   FLASH_C2ACR_ICRST_Msk             /*!< CPU2 Instruction cache reset                         */
-#define FLASH_C2ACR_PES_Pos                 (15U)
-#define FLASH_C2ACR_PES_Msk                 (0x1UL << FLASH_C2ACR_PES_Pos)    /*!< 0x00008000 */
-#define FLASH_C2ACR_PES                     FLASH_C2ACR_PES_Msk               /*!< CPU2 Program/erase suspend request                   */
-
-/******************  Bits definition for FLASH_C2SR register  ************/
-#define FLASH_C2SR_EOP_Pos                  (0U)
-#define FLASH_C2SR_EOP_Msk                  (0x1UL << FLASH_C2SR_EOP_Pos)     /*!< 0x00000001 */
-#define FLASH_C2SR_EOP                      FLASH_C2SR_EOP_Msk                /*!< CPU2 End of operation                                */
-#define FLASH_C2SR_OPERR_Pos                (1U)
-#define FLASH_C2SR_OPERR_Msk                (0x1UL << FLASH_C2SR_OPERR_Pos)   /*!< 0x00000002 */
-#define FLASH_C2SR_OPERR                    FLASH_C2SR_OPERR_Msk              /*!< CPU2 Operation error                                 */
-#define FLASH_C2SR_PROGERR_Pos              (3U)
-#define FLASH_C2SR_PROGERR_Msk              (0x1UL << FLASH_C2SR_PROGERR_Pos) /*!< 0x00000008 */
-#define FLASH_C2SR_PROGERR                  FLASH_C2SR_PROGERR_Msk            /*!< CPU2 Programming error                               */
-#define FLASH_C2SR_WRPERR_Pos               (4U)
-#define FLASH_C2SR_WRPERR_Msk               (0x1UL << FLASH_C2SR_WRPERR_Pos)  /*!< 0x00000010 */
-#define FLASH_C2SR_WRPERR                   FLASH_C2SR_WRPERR_Msk             /*!< CPU2 Write protection error                          */
-#define FLASH_C2SR_PGAERR_Pos               (5U)
-#define FLASH_C2SR_PGAERR_Msk               (0x1UL << FLASH_C2SR_PGAERR_Pos)  /*!< 0x00000020 */
-#define FLASH_C2SR_PGAERR                   FLASH_C2SR_PGAERR_Msk             /*!< CPU2 Programming alignment error                     */
-#define FLASH_C2SR_SIZERR_Pos               (6U)
-#define FLASH_C2SR_SIZERR_Msk               (0x1UL << FLASH_C2SR_SIZERR_Pos)  /*!< 0x00000040 */
-#define FLASH_C2SR_SIZERR                   FLASH_C2SR_SIZERR_Msk             /*!< CPU2 Size error                                      */
-#define FLASH_C2SR_PGSERR_Pos               (7U)
-#define FLASH_C2SR_PGSERR_Msk               (0x1UL << FLASH_C2SR_PGSERR_Pos)  /*!< 0x00000080 */
-#define FLASH_C2SR_PGSERR                   FLASH_C2SR_PGSERR_Msk             /*!< CPU2 Programming sequence error                      */
-#define FLASH_C2SR_MISERR_Pos               (8U)
-#define FLASH_C2SR_MISERR_Msk               (0x1UL << FLASH_C2SR_MISERR_Pos)  /*!< 0x00000100 */
-#define FLASH_C2SR_MISERR                   FLASH_C2SR_MISERR_Msk             /*!< CPU2 Fast programming data miss error                */
-#define FLASH_C2SR_FASTERR_Pos              (9U)
-#define FLASH_C2SR_FASTERR_Msk              (0x1UL << FLASH_C2SR_FASTERR_Pos) /*!< 0x00000200 */
-#define FLASH_C2SR_FASTERR                  FLASH_C2SR_FASTERR_Msk            /*!< CPU2 Fast programming error                          */
-#define FLASH_C2SR_RDERR_Pos                (14U)
-#define FLASH_C2SR_RDERR_Msk                (0x1UL << FLASH_C2SR_RDERR_Pos)   /*!< 0x00004000 */
-#define FLASH_C2SR_RDERR                    FLASH_C2SR_RDERR_Msk              /*!< CPU2 PCROP read error                                */
-#define FLASH_C2SR_BSY_Pos                  (16U)
-#define FLASH_C2SR_BSY_Msk                  (0x1UL << FLASH_C2SR_BSY_Pos)     /*!< 0x00010000 */
-#define FLASH_C2SR_BSY                      FLASH_C2SR_BSY_Msk                /*!< CPU2 Flash busy                                      */
-#define FLASH_C2SR_CFGBSY_Pos               (18U)
-#define FLASH_C2SR_CFGBSY_Msk               (0x1UL << FLASH_C2SR_CFGBSY_Pos)  /*!< 0x00040000 */
-#define FLASH_C2SR_CFGBSY                   FLASH_C2SR_CFGBSY_Msk             /*!< CPU2 Programming or erase configuration busy         */
-#define FLASH_C2SR_PESD_Pos                 (19U)
-#define FLASH_C2SR_PESD_Msk                 (0x1UL << FLASH_C2SR_PESD_Pos)    /*!< 0x00080000 */
-#define FLASH_C2SR_PESD                     FLASH_C2SR_PESD_Msk               /*!< CPU2 Programming/erase operation suspended           */
-
-/******************  Bits definition for FLASH_C2CR register  ************/
-#define FLASH_C2CR_PG_Pos                   (0U)
-#define FLASH_C2CR_PG_Msk                   (0x1UL << FLASH_C2CR_PG_Pos)      /*!< 0x00000001 */
-#define FLASH_C2CR_PG                       FLASH_C2CR_PG_Msk                 /*!< CPU2 Flash programming                               */
-#define FLASH_C2CR_PER_Pos                  (1U)
-#define FLASH_C2CR_PER_Msk                  (0x1UL << FLASH_C2CR_PER_Pos)     /*!< 0x00000002 */
-#define FLASH_C2CR_PER                      FLASH_C2CR_PER_Msk                /*!< CPU2 Page erase                                      */
-#define FLASH_C2CR_MER_Pos                  (2U)
-#define FLASH_C2CR_MER_Msk                  (0x1UL << FLASH_C2CR_MER_Pos)     /*!< 0x00000004 */
-#define FLASH_C2CR_MER                      FLASH_C2CR_MER_Msk                /*!< CPU2 Mass erase                                      */
-#define FLASH_C2CR_PNB_Pos                  (3U)
-#define FLASH_C2CR_PNB_Msk                  (0xFFUL << FLASH_C2CR_PNB_Pos)    /*!< 0x000007F8 */
-#define FLASH_C2CR_PNB                      FLASH_C2CR_PNB_Msk                /*!< CPU2 Page number selection mask                      */
-#define FLASH_C2CR_STRT_Pos                 (16U)
-#define FLASH_C2CR_STRT_Msk                 (0x1UL << FLASH_C2CR_STRT_Pos)    /*!< 0x00010000 */
-#define FLASH_C2CR_STRT                     FLASH_C2CR_STRT_Msk               /*!< CPU2 Start an erase operation                        */
-#define FLASH_C2CR_FSTPG_Pos                (18U)
-#define FLASH_C2CR_FSTPG_Msk                (0x1UL << FLASH_C2CR_FSTPG_Pos)   /*!< 0x00040000 */
-#define FLASH_C2CR_FSTPG                    FLASH_C2CR_FSTPG_Msk              /*!< CPU2 Fast programming                                */
-#define FLASH_C2CR_EOPIE_Pos                (24U)
-#define FLASH_C2CR_EOPIE_Msk                (0x1UL << FLASH_C2CR_EOPIE_Pos)   /*!< 0x01000000 */
-#define FLASH_C2CR_EOPIE                    FLASH_C2CR_EOPIE_Msk              /*!< CPU2 End of operation interrupt enable               */
-#define FLASH_C2CR_ERRIE_Pos                (25U)
-#define FLASH_C2CR_ERRIE_Msk                (0x1UL << FLASH_C2CR_ERRIE_Pos)   /*!< 0x02000000 */
-#define FLASH_C2CR_ERRIE                    FLASH_C2CR_ERRIE_Msk              /*!< CPU2 Error interrupt enable                          */
-#define FLASH_C2CR_RDERRIE_Pos              (26U)
-#define FLASH_C2CR_RDERRIE_Msk              (0x1UL << FLASH_C2CR_RDERRIE_Pos) /*!< 0x04000000 */
-#define FLASH_C2CR_RDERRIE                  FLASH_C2CR_RDERRIE_Msk            /*!< CPU2 PCROP read error interrupt enable               */
-
-/******************  Bits definition for FLASH_SFR register  ************/
-#define FLASH_SFR_SFSA_Pos                  (0U)
-#define FLASH_SFR_SFSA_Msk                  (0x7FUL << FLASH_SFR_SFSA_Pos)     /*!< 0x0000007F */
-#define FLASH_SFR_SFSA                      FLASH_SFR_SFSA_Msk                 /* Secure flash start address                            */
-#define FLASH_SFR_FSD_Pos                   (7U)
-#define FLASH_SFR_FSD_Msk                   (0x1UL << FLASH_SFR_FSD_Pos)       /*!< 0x00000080 */
-#define FLASH_SFR_FSD                       FLASH_SFR_FSD_Msk                  /* Flash mode secure                                     */
-#define FLASH_SFR_DDS_Pos                   (12U)
-#define FLASH_SFR_DDS_Msk                   (0x1UL << FLASH_SFR_DDS_Pos)       /*!< 0x00001000 */
-#define FLASH_SFR_DDS                       FLASH_SFR_DDS_Msk                  /* Enabling and disabling CPU2 Debug access              */
-#define FLASH_SFR_HDPSA_Pos                 (16U)
-#define FLASH_SFR_HDPSA_Msk                 (0x7FUL << FLASH_SFR_HDPSA_Pos)    /*!< 0x007F0000 */
-#define FLASH_SFR_HDPSA                     FLASH_SFR_HDPSA_Msk                /*!< User Flash Hide Protection Area start address*/
-#define FLASH_SFR_HDPAD_Pos                 (23U)
-#define FLASH_SFR_HDPAD_Msk                 (0x1UL << FLASH_SFR_HDPAD_Pos)     /*!< 0x00800000 */
-#define FLASH_SFR_HDPAD                     FLASH_SFR_HDPAD_Msk                /* User Flash Hide Protection Area disabled       */
-#define FLASH_SFR_SUBGHZSPISD_Pos           (31U)
-#define FLASH_SFR_SUBGHZSPISD_Msk           (0x1UL << FLASH_SFR_SUBGHZSPISD_Pos)  /*!< 0x80000000 */
-#define FLASH_SFR_SUBGHZSPISD               FLASH_SFR_SUBGHZSPISD_Msk             /* Sub-GHz radio SPI security disable                 */
-
-/******************  Bits definition for FLASH_SRRVR register  ************/
-#define FLASH_SRRVR_SBRV_Pos                (0U)
-#define FLASH_SRRVR_SBRV_Msk                (0xFFFFUL << FLASH_SRRVR_SBRV_Pos)  /*!< 0x0000FFFF */
-#define FLASH_SRRVR_SBRV                    FLASH_SRRVR_SBRV_Msk                /* SCPU2 boot reset vector memory offset                */
-
-#define FLASH_SRRVR_SBRSA_Pos               (18U)
-#define FLASH_SRRVR_SBRSA_Msk               (0x1FUL << FLASH_SRRVR_SBRSA_Pos)   /*!< 0x007C0000 */
-#define FLASH_SRRVR_SBRSA                   FLASH_SRRVR_SBRSA_Msk               /* Secure backup SRAM2 start address                    */
-#define FLASH_SRRVR_BRSD_Pos                (23U)
-#define FLASH_SRRVR_BRSD_Msk                (0x1UL << FLASH_SRRVR_BRSD_Pos)     /*!< 0x00800000 */
-#define FLASH_SRRVR_BRSD                    FLASH_SRRVR_BRSD_Msk                /* Backup SRAM2 secure mode                             */
-
-#define FLASH_SRRVR_SNBRSA_Pos              (25U)
-#define FLASH_SRRVR_SNBRSA_Msk              (0x1FUL << FLASH_SRRVR_SNBRSA_Pos)  /*!< 0x3E000000 */
-#define FLASH_SRRVR_SNBRSA                  FLASH_SRRVR_SNBRSA_Msk              /* Secure non-backup SRAM1 start address                */
-#define FLASH_SRRVR_NBRSD_Pos               (30U)
-#define FLASH_SRRVR_NBRSD_Msk               (0x1UL << FLASH_SRRVR_NBRSD_Pos)    /*!< 0x40000000 */
-#define FLASH_SRRVR_NBRSD                   FLASH_SRRVR_NBRSD_Msk               /* Non-backup SRAM1 secure mode                         */
-#define FLASH_SRRVR_C2OPT_Pos               (31U)
-#define FLASH_SRRVR_C2OPT_Msk               (0x1UL << FLASH_SRRVR_C2OPT_Pos)    /*!< 0x80000000 */
-#define FLASH_SRRVR_C2OPT                   FLASH_SRRVR_C2OPT_Msk               /* SCPU2 boot reset vector memory selection             */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos           (0U)
-#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
-#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos           (2U)
-#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
-#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos           (4U)
-#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
-#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos           (6U)
-#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
-#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos           (8U)
-#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
-#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos           (10U)
-#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
-#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos           (12U)
-#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
-#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos           (14U)
-#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
-#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos           (16U)
-#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
-#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos           (18U)
-#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
-#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos          (20U)
-#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
-#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos          (22U)
-#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
-#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos          (24U)
-#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
-#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos          (26U)
-#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
-#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos          (28U)
-#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
-#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos          (30U)
-#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
-#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT0_Pos            (0U)
-#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
-#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
-#define GPIO_OTYPER_OT1_Pos            (1U)
-#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
-#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
-#define GPIO_OTYPER_OT2_Pos            (2U)
-#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
-#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
-#define GPIO_OTYPER_OT3_Pos            (3U)
-#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
-#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
-#define GPIO_OTYPER_OT4_Pos            (4U)
-#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
-#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
-#define GPIO_OTYPER_OT5_Pos            (5U)
-#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
-#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
-#define GPIO_OTYPER_OT6_Pos            (6U)
-#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
-#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
-#define GPIO_OTYPER_OT7_Pos            (7U)
-#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
-#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
-#define GPIO_OTYPER_OT8_Pos            (8U)
-#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
-#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
-#define GPIO_OTYPER_OT9_Pos            (9U)
-#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
-#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
-#define GPIO_OTYPER_OT10_Pos           (10U)
-#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
-#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
-#define GPIO_OTYPER_OT11_Pos           (11U)
-#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
-#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
-#define GPIO_OTYPER_OT12_Pos           (12U)
-#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
-#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
-#define GPIO_OTYPER_OT13_Pos           (13U)
-#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
-#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
-#define GPIO_OTYPER_OT14_Pos           (14U)
-#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
-#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
-#define GPIO_OTYPER_OT15_Pos           (15U)
-#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
-#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
-#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
-#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
-#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
-#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
-#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
-#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
-#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
-#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
-#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
-#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
-#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
-#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
-#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
-#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
-#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
-#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
-#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
-#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
-#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
-#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
-#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
-#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
-#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
-#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
-#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
-#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
-#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
-#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
-#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
-#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
-#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
-#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
-#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
-#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
-#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
-#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
-#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
-#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
-#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
-#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
-#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
-#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
-#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
-#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
-#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
-#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
-#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
-#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
-#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
-#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
-#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
-#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
-#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
-#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
-#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
-#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
-#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
-#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
-#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
-#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
-#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
-#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
-#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
-#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
-#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
-#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
-#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
-#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
-#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
-#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
-#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
-#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
-#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
-#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
-#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
-#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
-#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
-#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
-#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPD0_Pos           (0U)
-#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
-#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos           (2U)
-#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
-#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos           (4U)
-#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
-#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos           (6U)
-#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
-#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos           (8U)
-#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
-#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos           (10U)
-#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
-#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos           (12U)
-#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
-#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos           (14U)
-#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
-#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos           (16U)
-#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
-#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos           (18U)
-#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
-#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos          (20U)
-#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
-#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos          (22U)
-#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
-#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos          (24U)
-#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
-#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos          (26U)
-#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
-#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos          (28U)
-#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
-#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos          (30U)
-#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
-#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos               (0U)
-#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
-#define GPIO_IDR_ID1_Pos               (1U)
-#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
-#define GPIO_IDR_ID2_Pos               (2U)
-#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
-#define GPIO_IDR_ID3_Pos               (3U)
-#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
-#define GPIO_IDR_ID4_Pos               (4U)
-#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
-#define GPIO_IDR_ID5_Pos               (5U)
-#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
-#define GPIO_IDR_ID6_Pos               (6U)
-#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
-#define GPIO_IDR_ID7_Pos               (7U)
-#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
-#define GPIO_IDR_ID8_Pos               (8U)
-#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
-#define GPIO_IDR_ID9_Pos               (9U)
-#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
-#define GPIO_IDR_ID10_Pos              (10U)
-#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
-#define GPIO_IDR_ID11_Pos              (11U)
-#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
-#define GPIO_IDR_ID12_Pos              (12U)
-#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
-#define GPIO_IDR_ID13_Pos              (13U)
-#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
-#define GPIO_IDR_ID14_Pos              (14U)
-#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
-#define GPIO_IDR_ID15_Pos              (15U)
-#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_OD0_Pos               (0U)
-#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
-#define GPIO_ODR_OD1_Pos               (1U)
-#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
-#define GPIO_ODR_OD2_Pos               (2U)
-#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
-#define GPIO_ODR_OD3_Pos               (3U)
-#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
-#define GPIO_ODR_OD4_Pos               (4U)
-#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
-#define GPIO_ODR_OD5_Pos               (5U)
-#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
-#define GPIO_ODR_OD6_Pos               (6U)
-#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
-#define GPIO_ODR_OD7_Pos               (7U)
-#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
-#define GPIO_ODR_OD8_Pos               (8U)
-#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
-#define GPIO_ODR_OD9_Pos               (9U)
-#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
-#define GPIO_ODR_OD10_Pos              (10U)
-#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
-#define GPIO_ODR_OD11_Pos              (11U)
-#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
-#define GPIO_ODR_OD12_Pos              (12U)
-#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
-#define GPIO_ODR_OD13_Pos              (13U)
-#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
-#define GPIO_ODR_OD14_Pos              (14U)
-#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
-#define GPIO_ODR_OD15_Pos              (15U)
-#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS0_Pos              (0U)
-#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
-#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
-#define GPIO_BSRR_BS1_Pos              (1U)
-#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
-#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
-#define GPIO_BSRR_BS2_Pos              (2U)
-#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
-#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
-#define GPIO_BSRR_BS3_Pos              (3U)
-#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
-#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
-#define GPIO_BSRR_BS4_Pos              (4U)
-#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
-#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
-#define GPIO_BSRR_BS5_Pos              (5U)
-#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
-#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
-#define GPIO_BSRR_BS6_Pos              (6U)
-#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
-#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
-#define GPIO_BSRR_BS7_Pos              (7U)
-#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
-#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
-#define GPIO_BSRR_BS8_Pos              (8U)
-#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
-#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
-#define GPIO_BSRR_BS9_Pos              (9U)
-#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
-#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
-#define GPIO_BSRR_BS10_Pos             (10U)
-#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
-#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
-#define GPIO_BSRR_BS11_Pos             (11U)
-#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
-#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
-#define GPIO_BSRR_BS12_Pos             (12U)
-#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
-#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
-#define GPIO_BSRR_BS13_Pos             (13U)
-#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
-#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
-#define GPIO_BSRR_BS14_Pos             (14U)
-#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
-#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
-#define GPIO_BSRR_BS15_Pos             (15U)
-#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
-#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
-#define GPIO_BSRR_BR0_Pos              (16U)
-#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
-#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
-#define GPIO_BSRR_BR1_Pos              (17U)
-#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
-#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
-#define GPIO_BSRR_BR2_Pos              (18U)
-#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
-#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
-#define GPIO_BSRR_BR3_Pos              (19U)
-#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
-#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
-#define GPIO_BSRR_BR4_Pos              (20U)
-#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
-#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
-#define GPIO_BSRR_BR5_Pos              (21U)
-#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
-#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
-#define GPIO_BSRR_BR6_Pos              (22U)
-#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
-#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
-#define GPIO_BSRR_BR7_Pos              (23U)
-#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
-#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
-#define GPIO_BSRR_BR8_Pos              (24U)
-#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
-#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
-#define GPIO_BSRR_BR9_Pos              (25U)
-#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
-#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
-#define GPIO_BSRR_BR10_Pos             (26U)
-#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
-#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
-#define GPIO_BSRR_BR11_Pos             (27U)
-#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
-#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
-#define GPIO_BSRR_BR12_Pos             (28U)
-#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
-#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
-#define GPIO_BSRR_BR13_Pos             (29U)
-#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
-#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
-#define GPIO_BSRR_BR14_Pos             (30U)
-#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
-#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
-#define GPIO_BSRR_BR15_Pos             (31U)
-#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
-#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0_Pos             (0U)
-#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
-#define GPIO_LCKR_LCK1_Pos             (1U)
-#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
-#define GPIO_LCKR_LCK2_Pos             (2U)
-#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
-#define GPIO_LCKR_LCK3_Pos             (3U)
-#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
-#define GPIO_LCKR_LCK4_Pos             (4U)
-#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
-#define GPIO_LCKR_LCK5_Pos             (5U)
-#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
-#define GPIO_LCKR_LCK6_Pos             (6U)
-#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
-#define GPIO_LCKR_LCK7_Pos             (7U)
-#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
-#define GPIO_LCKR_LCK8_Pos             (8U)
-#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
-#define GPIO_LCKR_LCK9_Pos             (9U)
-#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
-#define GPIO_LCKR_LCK10_Pos            (10U)
-#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
-#define GPIO_LCKR_LCK11_Pos            (11U)
-#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
-#define GPIO_LCKR_LCK12_Pos            (12U)
-#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
-#define GPIO_LCKR_LCK13_Pos            (13U)
-#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
-#define GPIO_LCKR_LCK14_Pos            (14U)
-#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
-#define GPIO_LCKR_LCK15_Pos            (15U)
-#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
-#define GPIO_LCKR_LCKK_Pos             (16U)
-#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
-
-/****************** Bit definition for GPIO_AFRL register *********************/
-#define GPIO_AFRL_AFSEL0_Pos           (0U)
-#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
-#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
-#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
-#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
-#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
-#define GPIO_AFRL_AFSEL1_Pos           (4U)
-#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
-#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
-#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
-#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
-#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
-#define GPIO_AFRL_AFSEL2_Pos           (8U)
-#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
-#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
-#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
-#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
-#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
-#define GPIO_AFRL_AFSEL3_Pos           (12U)
-#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
-#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
-#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
-#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
-#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
-#define GPIO_AFRL_AFSEL4_Pos           (16U)
-#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
-#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
-#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
-#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
-#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
-#define GPIO_AFRL_AFSEL5_Pos           (20U)
-#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
-#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
-#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
-#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
-#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
-#define GPIO_AFRL_AFSEL6_Pos           (24U)
-#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
-#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
-#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
-#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
-#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
-#define GPIO_AFRL_AFSEL7_Pos           (28U)
-#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
-#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
-#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
-#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
-#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
-
-/****************** Bit definition for GPIO_AFRH register *********************/
-#define GPIO_AFRH_AFSEL8_Pos           (0U)
-#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
-#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
-#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
-#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
-#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
-#define GPIO_AFRH_AFSEL9_Pos           (4U)
-#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
-#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
-#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
-#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
-#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
-#define GPIO_AFRH_AFSEL10_Pos          (8U)
-#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
-#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
-#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
-#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
-#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
-#define GPIO_AFRH_AFSEL11_Pos          (12U)
-#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
-#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
-#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
-#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
-#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
-#define GPIO_AFRH_AFSEL12_Pos          (16U)
-#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
-#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
-#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
-#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
-#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
-#define GPIO_AFRH_AFSEL13_Pos          (20U)
-#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
-#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
-#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
-#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
-#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
-#define GPIO_AFRH_AFSEL14_Pos          (24U)
-#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
-#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
-#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
-#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
-#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
-#define GPIO_AFRH_AFSEL15_Pos          (28U)
-#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
-#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
-#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
-#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
-#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_BRR register  ******************/
-#define GPIO_BRR_BR0_Pos               (0U)
-#define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
-#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
-#define GPIO_BRR_BR1_Pos               (1U)
-#define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
-#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
-#define GPIO_BRR_BR2_Pos               (2U)
-#define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
-#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
-#define GPIO_BRR_BR3_Pos               (3U)
-#define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
-#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
-#define GPIO_BRR_BR4_Pos               (4U)
-#define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
-#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
-#define GPIO_BRR_BR5_Pos               (5U)
-#define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
-#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
-#define GPIO_BRR_BR6_Pos               (6U)
-#define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
-#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
-#define GPIO_BRR_BR7_Pos               (7U)
-#define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
-#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
-#define GPIO_BRR_BR8_Pos               (8U)
-#define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
-#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
-#define GPIO_BRR_BR9_Pos               (9U)
-#define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
-#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
-#define GPIO_BRR_BR10_Pos              (10U)
-#define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
-#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
-#define GPIO_BRR_BR11_Pos              (11U)
-#define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
-#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
-#define GPIO_BRR_BR12_Pos              (12U)
-#define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
-#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
-#define GPIO_BRR_BR13_Pos              (13U)
-#define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
-#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
-#define GPIO_BRR_BR14_Pos              (14U)
-#define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
-#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
-#define GPIO_BRR_BR15_Pos              (15U)
-#define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
-#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                        HSEM HW Semaphore                                   */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for HSEM_R register  ********************/
-#define HSEM_R_PROCID_Pos        (0U)
-#define HSEM_R_PROCID_Msk        (0xFFUL << HSEM_R_PROCID_Pos)                 /*!< 0x000000FF */
-#define HSEM_R_PROCID            HSEM_R_PROCID_Msk                             /*!<Semaphore ProcessID */
-#define HSEM_R_COREID_Pos        (8U)
-#define HSEM_R_COREID_Msk        (0xFUL << HSEM_R_COREID_Pos)                  /*!< 0x00000F00 */
-#define HSEM_R_COREID            HSEM_R_COREID_Msk                             /*!<Semaphore CoreID. */
-#define HSEM_R_LOCK_Pos          (31U)
-#define HSEM_R_LOCK_Msk          (0x1UL << HSEM_R_LOCK_Pos)                    /*!< 0x80000000 */
-#define HSEM_R_LOCK              HSEM_R_LOCK_Msk                               /*!<Lock indication. */
-
-/********************  Bit definition for HSEM_RLR register  ******************/
-#define HSEM_RLR_PROCID_Pos      (0U)
-#define HSEM_RLR_PROCID_Msk      (0xFFUL << HSEM_RLR_PROCID_Pos)               /*!< 0x000000FF */
-#define HSEM_RLR_PROCID          HSEM_RLR_PROCID_Msk                           /*!<Semaphore ProcessID */
-#define HSEM_RLR_COREID_Pos      (8U)
-#define HSEM_RLR_COREID_Msk      (0xFUL << HSEM_RLR_COREID_Pos)                /*!< 0x00000F00 */
-#define HSEM_RLR_COREID          HSEM_RLR_COREID_Msk                           /*!<Semaphore CoreID. */
-#define HSEM_RLR_LOCK_Pos        (31U)
-#define HSEM_RLR_LOCK_Msk        (0x1UL << HSEM_RLR_LOCK_Pos)                  /*!< 0x80000000 */
-#define HSEM_RLR_LOCK            HSEM_RLR_LOCK_Msk                             /*!<Lock indication. */
-
-/********************  Bit definition for HSEM_C1IER register  ****************/
-#define HSEM_C1IER_ISE0_Pos      (0U)
-#define HSEM_C1IER_ISE0_Msk      (0x1UL << HSEM_C1IER_ISE0_Pos)                /*!< 0x00000001 */
-#define HSEM_C1IER_ISE0          HSEM_C1IER_ISE0_Msk                           /*!<semaphore 0 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE1_Pos      (1U)
-#define HSEM_C1IER_ISE1_Msk      (0x1UL << HSEM_C1IER_ISE1_Pos)                /*!< 0x00000002 */
-#define HSEM_C1IER_ISE1          HSEM_C1IER_ISE1_Msk                           /*!<semaphore 1 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE2_Pos      (2U)
-#define HSEM_C1IER_ISE2_Msk      (0x1UL << HSEM_C1IER_ISE2_Pos)                /*!< 0x00000004 */
-#define HSEM_C1IER_ISE2          HSEM_C1IER_ISE2_Msk                           /*!<semaphore 2 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE3_Pos      (3U)
-#define HSEM_C1IER_ISE3_Msk      (0x1UL << HSEM_C1IER_ISE3_Pos)                /*!< 0x00000008 */
-#define HSEM_C1IER_ISE3          HSEM_C1IER_ISE3_Msk                           /*!<semaphore 3 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE4_Pos      (4U)
-#define HSEM_C1IER_ISE4_Msk      (0x1UL << HSEM_C1IER_ISE4_Pos)                /*!< 0x00000010 */
-#define HSEM_C1IER_ISE4          HSEM_C1IER_ISE4_Msk                           /*!<semaphore 4 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE5_Pos      (5U)
-#define HSEM_C1IER_ISE5_Msk      (0x1UL << HSEM_C1IER_ISE5_Pos)                /*!< 0x00000020 */
-#define HSEM_C1IER_ISE5          HSEM_C1IER_ISE5_Msk                           /*!<semaphore 5 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE6_Pos      (6U)
-#define HSEM_C1IER_ISE6_Msk      (0x1UL << HSEM_C1IER_ISE6_Pos)                /*!< 0x00000040 */
-#define HSEM_C1IER_ISE6          HSEM_C1IER_ISE6_Msk                           /*!<semaphore 6 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE7_Pos      (7U)
-#define HSEM_C1IER_ISE7_Msk      (0x1UL << HSEM_C1IER_ISE7_Pos)                /*!< 0x00000080 */
-#define HSEM_C1IER_ISE7          HSEM_C1IER_ISE7_Msk                           /*!<semaphore 7 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE8_Pos      (8U)
-#define HSEM_C1IER_ISE8_Msk      (0x1UL << HSEM_C1IER_ISE8_Pos)                /*!< 0x00000100 */
-#define HSEM_C1IER_ISE8          HSEM_C1IER_ISE8_Msk                           /*!<semaphore 8 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE9_Pos      (9U)
-#define HSEM_C1IER_ISE9_Msk      (0x1UL << HSEM_C1IER_ISE9_Pos)                /*!< 0x00000200 */
-#define HSEM_C1IER_ISE9          HSEM_C1IER_ISE9_Msk                           /*!<semaphore 9 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE10_Pos     (10U)
-#define HSEM_C1IER_ISE10_Msk     (0x1UL << HSEM_C1IER_ISE10_Pos)               /*!< 0x00000400 */
-#define HSEM_C1IER_ISE10         HSEM_C1IER_ISE10_Msk                          /*!<semaphore 10 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE11_Pos     (11U)
-#define HSEM_C1IER_ISE11_Msk     (0x1UL << HSEM_C1IER_ISE11_Pos)               /*!< 0x00000800 */
-#define HSEM_C1IER_ISE11         HSEM_C1IER_ISE11_Msk                          /*!<semaphore 11 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE12_Pos     (12U)
-#define HSEM_C1IER_ISE12_Msk     (0x1UL << HSEM_C1IER_ISE12_Pos)               /*!< 0x00001000 */
-#define HSEM_C1IER_ISE12         HSEM_C1IER_ISE12_Msk                          /*!<semaphore 12 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE13_Pos     (13U)
-#define HSEM_C1IER_ISE13_Msk     (0x1UL << HSEM_C1IER_ISE13_Pos)               /*!< 0x00002000 */
-#define HSEM_C1IER_ISE13         HSEM_C1IER_ISE13_Msk                          /*!<semaphore 13 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE14_Pos     (14U)
-#define HSEM_C1IER_ISE14_Msk     (0x1UL << HSEM_C1IER_ISE14_Pos)               /*!< 0x00004000 */
-#define HSEM_C1IER_ISE14         HSEM_C1IER_ISE14_Msk                          /*!<semaphore 14 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE15_Pos     (15U)
-#define HSEM_C1IER_ISE15_Msk     (0x1UL << HSEM_C1IER_ISE15_Pos)               /*!< 0x00008000 */
-#define HSEM_C1IER_ISE15         HSEM_C1IER_ISE15_Msk                          /*!<semaphore 15 CPU1 interrupt enable bit. */
-
-/********************  Bit definition for HSEM_C1ICR register  *****************/
-#define HSEM_C1ICR_ISC0_Pos      (0U)
-#define HSEM_C1ICR_ISC0_Msk      (0x1UL << HSEM_C1ICR_ISC0_Pos)                /*!< 0x00000001 */
-#define HSEM_C1ICR_ISC0          HSEM_C1ICR_ISC0_Msk                           /*!<semaphore 0 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC1_Pos      (1U)
-#define HSEM_C1ICR_ISC1_Msk      (0x1UL << HSEM_C1ICR_ISC1_Pos)                /*!< 0x00000002 */
-#define HSEM_C1ICR_ISC1          HSEM_C1ICR_ISC1_Msk                           /*!<semaphore 1 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC2_Pos      (2U)
-#define HSEM_C1ICR_ISC2_Msk      (0x1UL << HSEM_C1ICR_ISC2_Pos)                /*!< 0x00000004 */
-#define HSEM_C1ICR_ISC2          HSEM_C1ICR_ISC2_Msk                           /*!<semaphore 2 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC3_Pos      (3U)
-#define HSEM_C1ICR_ISC3_Msk      (0x1UL << HSEM_C1ICR_ISC3_Pos)                /*!< 0x00000008 */
-#define HSEM_C1ICR_ISC3          HSEM_C1ICR_ISC3_Msk                           /*!<semaphore 3 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC4_Pos      (4U)
-#define HSEM_C1ICR_ISC4_Msk      (0x1UL << HSEM_C1ICR_ISC4_Pos)                /*!< 0x00000010 */
-#define HSEM_C1ICR_ISC4          HSEM_C1ICR_ISC4_Msk                           /*!<semaphore 4 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC5_Pos      (5U)
-#define HSEM_C1ICR_ISC5_Msk      (0x1UL << HSEM_C1ICR_ISC5_Pos)                /*!< 0x00000020 */
-#define HSEM_C1ICR_ISC5          HSEM_C1ICR_ISC5_Msk                           /*!<semaphore 5 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC6_Pos      (6U)
-#define HSEM_C1ICR_ISC6_Msk      (0x1UL << HSEM_C1ICR_ISC6_Pos)                /*!< 0x00000040 */
-#define HSEM_C1ICR_ISC6          HSEM_C1ICR_ISC6_Msk                           /*!<semaphore 6 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC7_Pos      (7U)
-#define HSEM_C1ICR_ISC7_Msk      (0x1UL << HSEM_C1ICR_ISC7_Pos)                /*!< 0x00000080 */
-#define HSEM_C1ICR_ISC7          HSEM_C1ICR_ISC7_Msk                           /*!<semaphore 7 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC8_Pos      (8U)
-#define HSEM_C1ICR_ISC8_Msk      (0x1UL << HSEM_C1ICR_ISC8_Pos)                /*!< 0x00000100 */
-#define HSEM_C1ICR_ISC8          HSEM_C1ICR_ISC8_Msk                           /*!<semaphore 8 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC9_Pos      (9U)
-#define HSEM_C1ICR_ISC9_Msk      (0x1UL << HSEM_C1ICR_ISC9_Pos)                /*!< 0x00000200 */
-#define HSEM_C1ICR_ISC9          HSEM_C1ICR_ISC9_Msk                           /*!<semaphore 9 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC10_Pos     (10U)
-#define HSEM_C1ICR_ISC10_Msk     (0x1UL << HSEM_C1ICR_ISC10_Pos)               /*!< 0x00000400 */
-#define HSEM_C1ICR_ISC10         HSEM_C1ICR_ISC10_Msk                          /*!<semaphore 10 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC11_Pos     (11U)
-#define HSEM_C1ICR_ISC11_Msk     (0x1UL << HSEM_C1ICR_ISC11_Pos)               /*!< 0x00000800 */
-#define HSEM_C1ICR_ISC11         HSEM_C1ICR_ISC11_Msk                          /*!<semaphore 11 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC12_Pos     (12U)
-#define HSEM_C1ICR_ISC12_Msk     (0x1UL << HSEM_C1ICR_ISC12_Pos)               /*!< 0x00001000 */
-#define HSEM_C1ICR_ISC12         HSEM_C1ICR_ISC12_Msk                          /*!<semaphore 12 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC13_Pos     (13U)
-#define HSEM_C1ICR_ISC13_Msk     (0x1UL << HSEM_C1ICR_ISC13_Pos)               /*!< 0x00002000 */
-#define HSEM_C1ICR_ISC13         HSEM_C1ICR_ISC13_Msk                          /*!<semaphore 13 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC14_Pos     (14U)
-#define HSEM_C1ICR_ISC14_Msk     (0x1UL << HSEM_C1ICR_ISC14_Pos)               /*!< 0x00004000 */
-#define HSEM_C1ICR_ISC14         HSEM_C1ICR_ISC14_Msk                          /*!<semaphore 14 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC15_Pos     (15U)
-#define HSEM_C1ICR_ISC15_Msk     (0x1UL << HSEM_C1ICR_ISC15_Pos)               /*!< 0x00008000 */
-#define HSEM_C1ICR_ISC15         HSEM_C1ICR_ISC15_Msk                          /*!<semaphore 15 CPU1 interrupt clear bit. */
-
-/********************  Bit definition for HSEM_C1ISR register  *****************/
-#define HSEM_C1ISR_ISF0_Pos      (0U)
-#define HSEM_C1ISR_ISF0_Msk      (0x1UL << HSEM_C1ISR_ISF0_Pos)                /*!< 0x00000001 */
-#define HSEM_C1ISR_ISF0          HSEM_C1ISR_ISF0_Msk                           /*!<semaphore 0 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF1_Pos      (1U)
-#define HSEM_C1ISR_ISF1_Msk      (0x1UL << HSEM_C1ISR_ISF1_Pos)                /*!< 0x00000002 */
-#define HSEM_C1ISR_ISF1          HSEM_C1ISR_ISF1_Msk                           /*!<semaphore 1 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF2_Pos      (2U)
-#define HSEM_C1ISR_ISF2_Msk      (0x1UL << HSEM_C1ISR_ISF2_Pos)                /*!< 0x00000004 */
-#define HSEM_C1ISR_ISF2          HSEM_C1ISR_ISF2_Msk                           /*!<semaphore 2 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF3_Pos      (3U)
-#define HSEM_C1ISR_ISF3_Msk      (0x1UL << HSEM_C1ISR_ISF3_Pos)                /*!< 0x00000008 */
-#define HSEM_C1ISR_ISF3          HSEM_C1ISR_ISF3_Msk                           /*!<semaphore 3 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF4_Pos      (4U)
-#define HSEM_C1ISR_ISF4_Msk      (0x1UL << HSEM_C1ISR_ISF4_Pos)                /*!< 0x00000010 */
-#define HSEM_C1ISR_ISF4          HSEM_C1ISR_ISF4_Msk                           /*!<semaphore 4 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF5_Pos      (5U)
-#define HSEM_C1ISR_ISF5_Msk      (0x1UL << HSEM_C1ISR_ISF5_Pos)                /*!< 0x00000020 */
-#define HSEM_C1ISR_ISF5          HSEM_C1ISR_ISF5_Msk                           /*!<semaphore 5 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF6_Pos      (6U)
-#define HSEM_C1ISR_ISF6_Msk      (0x1UL << HSEM_C1ISR_ISF6_Pos)                /*!< 0x00000040 */
-#define HSEM_C1ISR_ISF6          HSEM_C1ISR_ISF6_Msk                           /*!<semaphore 6 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF7_Pos      (7U)
-#define HSEM_C1ISR_ISF7_Msk      (0x1UL << HSEM_C1ISR_ISF7_Pos)                /*!< 0x00000080 */
-#define HSEM_C1ISR_ISF7          HSEM_C1ISR_ISF7_Msk                           /*!<semaphore 7 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF8_Pos      (8U)
-#define HSEM_C1ISR_ISF8_Msk      (0x1UL << HSEM_C1ISR_ISF8_Pos)                /*!< 0x00000100 */
-#define HSEM_C1ISR_ISF8          HSEM_C1ISR_ISF8_Msk                           /*!<semaphore 8 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF9_Pos      (9U)
-#define HSEM_C1ISR_ISF9_Msk      (0x1UL << HSEM_C1ISR_ISF9_Pos)                /*!< 0x00000200 */
-#define HSEM_C1ISR_ISF9          HSEM_C1ISR_ISF9_Msk                           /*!<semaphore 9 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF10_Pos     (10U)
-#define HSEM_C1ISR_ISF10_Msk     (0x1UL << HSEM_C1ISR_ISF10_Pos)               /*!< 0x00000400 */
-#define HSEM_C1ISR_ISF10         HSEM_C1ISR_ISF10_Msk                          /*!<semaphore 10 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF11_Pos     (11U)
-#define HSEM_C1ISR_ISF11_Msk     (0x1UL << HSEM_C1ISR_ISF11_Pos)               /*!< 0x00000800 */
-#define HSEM_C1ISR_ISF11         HSEM_C1ISR_ISF11_Msk                          /*!<semaphore 11 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF12_Pos     (12U)
-#define HSEM_C1ISR_ISF12_Msk     (0x1UL << HSEM_C1ISR_ISF12_Pos)               /*!< 0x00001000 */
-#define HSEM_C1ISR_ISF12         HSEM_C1ISR_ISF12_Msk                          /*!<semaphore 12 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF13_Pos     (13U)
-#define HSEM_C1ISR_ISF13_Msk     (0x1UL << HSEM_C1ISR_ISF13_Pos)               /*!< 0x00002000 */
-#define HSEM_C1ISR_ISF13         HSEM_C1ISR_ISF13_Msk                          /*!<semaphore 13 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF14_Pos     (14U)
-#define HSEM_C1ISR_ISF14_Msk     (0x1UL << HSEM_C1ISR_ISF14_Pos)               /*!< 0x00004000 */
-#define HSEM_C1ISR_ISF14         HSEM_C1ISR_ISF14_Msk                          /*!<semaphore 14 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF15_Pos     (15U)
-#define HSEM_C1ISR_ISF15_Msk     (0x1UL << HSEM_C1ISR_ISF15_Pos)               /*!< 0x00008000 */
-#define HSEM_C1ISR_ISF15         HSEM_C1ISR_ISF15_Msk                          /*!<semaphore 15 CPU1 interrupt status bit. */
-
-/********************  Bit definition for HSEM_C1MISR register  *****************/
-#define HSEM_C1MISR_MISF0_Pos     (0U)
-#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)               /*!< 0x00000001 */
-#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                          /*!<semaphore 0 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF1_Pos     (1U)
-#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)               /*!< 0x00000002 */
-#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                          /*!<semaphore 1 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF2_Pos     (2U)
-#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)               /*!< 0x00000004 */
-#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                          /*!<semaphore 2 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF3_Pos     (3U)
-#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)               /*!< 0x00000008 */
-#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                          /*!<semaphore 3 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF4_Pos     (4U)
-#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)               /*!< 0x00000010 */
-#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                          /*!<semaphore 4 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF5_Pos     (5U)
-#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)               /*!< 0x00000020 */
-#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                          /*!<semaphore 5 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF6_Pos     (6U)
-#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)               /*!< 0x00000040 */
-#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                          /*!<semaphore 6 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF7_Pos     (7U)
-#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)               /*!< 0x00000080 */
-#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                          /*!<semaphore 7 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF8_Pos     (8U)
-#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)               /*!< 0x00000100 */
-#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                          /*!<semaphore 8 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF9_Pos     (9U)
-#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)               /*!< 0x00000200 */
-#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                          /*!<semaphore 9 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF10_Pos    (10U)
-#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)              /*!< 0x00000400 */
-#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                         /*!<semaphore 10 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF11_Pos    (11U)
-#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)              /*!< 0x00000800 */
-#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                         /*!<semaphore 11 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF12_Pos    (12U)
-#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)              /*!< 0x00001000 */
-#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                         /*!<semaphore 12 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF13_Pos    (13U)
-#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)              /*!< 0x00002000 */
-#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                         /*!<semaphore 13 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF14_Pos    (14U)
-#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)              /*!< 0x00004000 */
-#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                         /*!<semaphore 14 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF15_Pos    (15U)
-#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)              /*!< 0x00008000 */
-#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                         /*!<semaphore 15 CPU1 interrupt masked status bit. */
-
-/********************  Bit definition for HSEM_C2IER register  *****************/
-#define HSEM_C2IER_ISE0_Pos      (0U)
-#define HSEM_C2IER_ISE0_Msk      (0x1UL << HSEM_C2IER_ISE0_Pos)                /*!< 0x00000001 */
-#define HSEM_C2IER_ISE0          HSEM_C2IER_ISE0_Msk                           /*!<semaphore 0 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE1_Pos      (1U)
-#define HSEM_C2IER_ISE1_Msk      (0x1UL << HSEM_C2IER_ISE1_Pos)                /*!< 0x00000002 */
-#define HSEM_C2IER_ISE1          HSEM_C2IER_ISE1_Msk                           /*!<semaphore 1 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE2_Pos      (2U)
-#define HSEM_C2IER_ISE2_Msk      (0x1UL << HSEM_C2IER_ISE2_Pos)                /*!< 0x00000004 */
-#define HSEM_C2IER_ISE2          HSEM_C2IER_ISE2_Msk                           /*!<semaphore 2 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE3_Pos      (3U)
-#define HSEM_C2IER_ISE3_Msk      (0x1UL << HSEM_C2IER_ISE3_Pos)                /*!< 0x00000008 */
-#define HSEM_C2IER_ISE3          HSEM_C2IER_ISE3_Msk                           /*!<semaphore 3 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE4_Pos      (4U)
-#define HSEM_C2IER_ISE4_Msk      (0x1UL << HSEM_C2IER_ISE4_Pos)                /*!< 0x00000010 */
-#define HSEM_C2IER_ISE4          HSEM_C2IER_ISE4_Msk                           /*!<semaphore 4 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE5_Pos      (5U)
-#define HSEM_C2IER_ISE5_Msk      (0x1UL << HSEM_C2IER_ISE5_Pos)                /*!< 0x00000020 */
-#define HSEM_C2IER_ISE5          HSEM_C2IER_ISE5_Msk                           /*!<semaphore 5 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE6_Pos      (6U)
-#define HSEM_C2IER_ISE6_Msk      (0x1UL << HSEM_C2IER_ISE6_Pos)                /*!< 0x00000040 */
-#define HSEM_C2IER_ISE6          HSEM_C2IER_ISE6_Msk                           /*!<semaphore 6 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE7_Pos      (7U)
-#define HSEM_C2IER_ISE7_Msk      (0x1UL << HSEM_C2IER_ISE7_Pos)                /*!< 0x00000080 */
-#define HSEM_C2IER_ISE7          HSEM_C2IER_ISE7_Msk                           /*!<semaphore 7 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE8_Pos      (8U)
-#define HSEM_C2IER_ISE8_Msk      (0x1UL << HSEM_C2IER_ISE8_Pos)                /*!< 0x00000100 */
-#define HSEM_C2IER_ISE8          HSEM_C2IER_ISE8_Msk                           /*!<semaphore 8 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE9_Pos      (9U)
-#define HSEM_C2IER_ISE9_Msk      (0x1UL << HSEM_C2IER_ISE9_Pos)                /*!< 0x00000200 */
-#define HSEM_C2IER_ISE9          HSEM_C2IER_ISE9_Msk                           /*!<semaphore 9 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE10_Pos     (10U)
-#define HSEM_C2IER_ISE10_Msk     (0x1UL << HSEM_C2IER_ISE10_Pos)               /*!< 0x00000400 */
-#define HSEM_C2IER_ISE10         HSEM_C2IER_ISE10_Msk                          /*!<semaphore 10 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE11_Pos     (11U)
-#define HSEM_C2IER_ISE11_Msk     (0x1UL << HSEM_C2IER_ISE11_Pos)               /*!< 0x00000800 */
-#define HSEM_C2IER_ISE11         HSEM_C2IER_ISE11_Msk                          /*!<semaphore 11 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE12_Pos     (12U)
-#define HSEM_C2IER_ISE12_Msk     (0x1UL << HSEM_C2IER_ISE12_Pos)               /*!< 0x00001000 */
-#define HSEM_C2IER_ISE12         HSEM_C2IER_ISE12_Msk                          /*!<semaphore 12 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE13_Pos     (13U)
-#define HSEM_C2IER_ISE13_Msk     (0x1UL << HSEM_C2IER_ISE13_Pos)               /*!< 0x00002000 */
-#define HSEM_C2IER_ISE13         HSEM_C2IER_ISE13_Msk                          /*!<semaphore 13 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE14_Pos     (14U)
-#define HSEM_C2IER_ISE14_Msk     (0x1UL << HSEM_C2IER_ISE14_Pos)               /*!< 0x00004000 */
-#define HSEM_C2IER_ISE14         HSEM_C2IER_ISE14_Msk                          /*!<semaphore 14 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE15_Pos     (15U)
-#define HSEM_C2IER_ISE15_Msk     (0x1UL << HSEM_C2IER_ISE15_Pos)               /*!< 0x00008000 */
-#define HSEM_C2IER_ISE15         HSEM_C2IER_ISE15_Msk                          /*!<semaphore 15 CPU2 interrupt enable bit. */
-
-/********************  Bit definition for HSEM_C2ICR register  *****************/
-#define HSEM_C2ICR_ISC0_Pos      (0U)
-#define HSEM_C2ICR_ISC0_Msk      (0x1UL << HSEM_C2ICR_ISC0_Pos)                /*!< 0x00000001 */
-#define HSEM_C2ICR_ISC0          HSEM_C2ICR_ISC0_Msk                           /*!<semaphore 0 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC1_Pos      (1U)
-#define HSEM_C2ICR_ISC1_Msk      (0x1UL << HSEM_C2ICR_ISC1_Pos)                /*!< 0x00000002 */
-#define HSEM_C2ICR_ISC1          HSEM_C2ICR_ISC1_Msk                           /*!<semaphore 1 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC2_Pos      (2U)
-#define HSEM_C2ICR_ISC2_Msk      (0x1UL << HSEM_C2ICR_ISC2_Pos)                /*!< 0x00000004 */
-#define HSEM_C2ICR_ISC2          HSEM_C2ICR_ISC2_Msk                           /*!<semaphore 2 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC3_Pos      (3U)
-#define HSEM_C2ICR_ISC3_Msk      (0x1UL << HSEM_C2ICR_ISC3_Pos)                /*!< 0x00000008 */
-#define HSEM_C2ICR_ISC3          HSEM_C2ICR_ISC3_Msk                           /*!<semaphore 3 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC4_Pos      (4U)
-#define HSEM_C2ICR_ISC4_Msk      (0x1UL << HSEM_C2ICR_ISC4_Pos)                /*!< 0x00000010 */
-#define HSEM_C2ICR_ISC4          HSEM_C2ICR_ISC4_Msk                           /*!<semaphore 4 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC5_Pos      (5U)
-#define HSEM_C2ICR_ISC5_Msk      (0x1UL << HSEM_C2ICR_ISC5_Pos)                /*!< 0x00000020 */
-#define HSEM_C2ICR_ISC5          HSEM_C2ICR_ISC5_Msk                           /*!<semaphore 5 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC6_Pos      (6U)
-#define HSEM_C2ICR_ISC6_Msk      (0x1UL << HSEM_C2ICR_ISC6_Pos)                /*!< 0x00000040 */
-#define HSEM_C2ICR_ISC6          HSEM_C2ICR_ISC6_Msk                           /*!<semaphore 6 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC7_Pos      (7U)
-#define HSEM_C2ICR_ISC7_Msk      (0x1UL << HSEM_C2ICR_ISC7_Pos)                /*!< 0x00000080 */
-#define HSEM_C2ICR_ISC7          HSEM_C2ICR_ISC7_Msk                           /*!<semaphore 7 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC8_Pos      (8U)
-#define HSEM_C2ICR_ISC8_Msk      (0x1UL << HSEM_C2ICR_ISC8_Pos)                /*!< 0x00000100 */
-#define HSEM_C2ICR_ISC8          HSEM_C2ICR_ISC8_Msk                           /*!<semaphore 8 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC9_Pos      (9U)
-#define HSEM_C2ICR_ISC9_Msk      (0x1UL << HSEM_C2ICR_ISC9_Pos)                /*!< 0x00000200 */
-#define HSEM_C2ICR_ISC9          HSEM_C2ICR_ISC9_Msk                           /*!<semaphore 9 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC10_Pos     (10U)
-#define HSEM_C2ICR_ISC10_Msk     (0x1UL << HSEM_C2ICR_ISC10_Pos)               /*!< 0x00000400 */
-#define HSEM_C2ICR_ISC10         HSEM_C2ICR_ISC10_Msk                          /*!<semaphore 10 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC11_Pos     (11U)
-#define HSEM_C2ICR_ISC11_Msk     (0x1UL << HSEM_C2ICR_ISC11_Pos)               /*!< 0x00000800 */
-#define HSEM_C2ICR_ISC11         HSEM_C2ICR_ISC11_Msk                          /*!<semaphore 11 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC12_Pos     (12U)
-#define HSEM_C2ICR_ISC12_Msk     (0x1UL << HSEM_C2ICR_ISC12_Pos)               /*!< 0x00001000 */
-#define HSEM_C2ICR_ISC12         HSEM_C2ICR_ISC12_Msk                          /*!<semaphore 12 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC13_Pos     (13U)
-#define HSEM_C2ICR_ISC13_Msk     (0x1UL << HSEM_C2ICR_ISC13_Pos)               /*!< 0x00002000 */
-#define HSEM_C2ICR_ISC13         HSEM_C2ICR_ISC13_Msk                          /*!<semaphore 13 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC14_Pos     (14U)
-#define HSEM_C2ICR_ISC14_Msk     (0x1UL << HSEM_C2ICR_ISC14_Pos)               /*!< 0x00004000 */
-#define HSEM_C2ICR_ISC14         HSEM_C2ICR_ISC14_Msk                          /*!<semaphore 14 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC15_Pos     (15U)
-#define HSEM_C2ICR_ISC15_Msk     (0x1UL << HSEM_C2ICR_ISC15_Pos)               /*!< 0x00008000 */
-#define HSEM_C2ICR_ISC15         HSEM_C2ICR_ISC15_Msk                          /*!<semaphore 15 CPU2 interrupt clear bit. */
-
-/********************  Bit definition for HSEM_C2ISR register  *****************/
-#define HSEM_C2ISR_ISF0_Pos      (0U)
-#define HSEM_C2ISR_ISF0_Msk      (0x1UL << HSEM_C2ISR_ISF0_Pos)                /*!< 0x00000001 */
-#define HSEM_C2ISR_ISF0          HSEM_C2ISR_ISF0_Msk                           /*!<semaphore 0 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF1_Pos      (1U)
-#define HSEM_C2ISR_ISF1_Msk      (0x1UL << HSEM_C2ISR_ISF1_Pos)                /*!< 0x00000002 */
-#define HSEM_C2ISR_ISF1          HSEM_C2ISR_ISF1_Msk                           /*!<semaphore 1 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF2_Pos      (2U)
-#define HSEM_C2ISR_ISF2_Msk      (0x1UL << HSEM_C2ISR_ISF2_Pos)                /*!< 0x00000004 */
-#define HSEM_C2ISR_ISF2          HSEM_C2ISR_ISF2_Msk                           /*!<semaphore 2 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF3_Pos      (3U)
-#define HSEM_C2ISR_ISF3_Msk      (0x1UL << HSEM_C2ISR_ISF3_Pos)                /*!< 0x00000008 */
-#define HSEM_C2ISR_ISF3          HSEM_C2ISR_ISF3_Msk                           /*!<semaphore 3 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF4_Pos      (4U)
-#define HSEM_C2ISR_ISF4_Msk      (0x1UL << HSEM_C2ISR_ISF4_Pos)                /*!< 0x00000010 */
-#define HSEM_C2ISR_ISF4          HSEM_C2ISR_ISF4_Msk                           /*!<semaphore 4 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF5_Pos      (5U)
-#define HSEM_C2ISR_ISF5_Msk      (0x1UL << HSEM_C2ISR_ISF5_Pos)                /*!< 0x00000020 */
-#define HSEM_C2ISR_ISF5          HSEM_C2ISR_ISF5_Msk                           /*!<semaphore 5 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF6_Pos      (6U)
-#define HSEM_C2ISR_ISF6_Msk      (0x1UL << HSEM_C2ISR_ISF6_Pos)                /*!< 0x00000040 */
-#define HSEM_C2ISR_ISF6          HSEM_C2ISR_ISF6_Msk                           /*!<semaphore 6 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF7_Pos      (7U)
-#define HSEM_C2ISR_ISF7_Msk      (0x1UL << HSEM_C2ISR_ISF7_Pos)                /*!< 0x00000080 */
-#define HSEM_C2ISR_ISF7          HSEM_C2ISR_ISF7_Msk                           /*!<semaphore 7 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF8_Pos      (8U)
-#define HSEM_C2ISR_ISF8_Msk      (0x1UL << HSEM_C2ISR_ISF8_Pos)                /*!< 0x00000100 */
-#define HSEM_C2ISR_ISF8          HSEM_C2ISR_ISF8_Msk                           /*!<semaphore 8 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF9_Pos      (9U)
-#define HSEM_C2ISR_ISF9_Msk      (0x1UL << HSEM_C2ISR_ISF9_Pos)                /*!< 0x00000200 */
-#define HSEM_C2ISR_ISF9          HSEM_C2ISR_ISF9_Msk                           /*!<semaphore 9 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF10_Pos     (10U)
-#define HSEM_C2ISR_ISF10_Msk     (0x1UL << HSEM_C2ISR_ISF10_Pos)               /*!< 0x00000400 */
-#define HSEM_C2ISR_ISF10         HSEM_C2ISR_ISF10_Msk                          /*!<semaphore 10 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF11_Pos     (11U)
-#define HSEM_C2ISR_ISF11_Msk     (0x1UL << HSEM_C2ISR_ISF11_Pos)               /*!< 0x00000800 */
-#define HSEM_C2ISR_ISF11         HSEM_C2ISR_ISF11_Msk                          /*!<semaphore 11 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF12_Pos     (12U)
-#define HSEM_C2ISR_ISF12_Msk     (0x1UL << HSEM_C2ISR_ISF12_Pos)               /*!< 0x00001000 */
-#define HSEM_C2ISR_ISF12         HSEM_C2ISR_ISF12_Msk                          /*!<semaphore 12 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF13_Pos     (13U)
-#define HSEM_C2ISR_ISF13_Msk     (0x1UL << HSEM_C2ISR_ISF13_Pos)               /*!< 0x00002000 */
-#define HSEM_C2ISR_ISF13         HSEM_C2ISR_ISF13_Msk                          /*!<semaphore 13 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF14_Pos     (14U)
-#define HSEM_C2ISR_ISF14_Msk     (0x1UL << HSEM_C2ISR_ISF14_Pos)               /*!< 0x00004000 */
-#define HSEM_C2ISR_ISF14         HSEM_C2ISR_ISF14_Msk                          /*!<semaphore 14 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF15_Pos     (15U)
-#define HSEM_C2ISR_ISF15_Msk     (0x1UL << HSEM_C2ISR_ISF15_Pos)               /*!< 0x00008000 */
-#define HSEM_C2ISR_ISF15         HSEM_C2ISR_ISF15_Msk                          /*!<semaphore 15 CPU2 interrupt status bit. */
-
-/********************  Bit definition for HSEM_C2MISR register  *****************/
-#define HSEM_C2MISR_MISF0_Pos     (0U)
-#define HSEM_C2MISR_MISF0_Msk     (0x1UL << HSEM_C2MISR_MISF0_Pos)               /*!< 0x00000001 */
-#define HSEM_C2MISR_MISF0         HSEM_C2MISR_MISF0_Msk                          /*!<semaphore 0 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF1_Pos     (1U)
-#define HSEM_C2MISR_MISF1_Msk     (0x1UL << HSEM_C2MISR_MISF1_Pos)               /*!< 0x00000002 */
-#define HSEM_C2MISR_MISF1         HSEM_C2MISR_MISF1_Msk                          /*!<semaphore 1 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF2_Pos     (2U)
-#define HSEM_C2MISR_MISF2_Msk     (0x1UL << HSEM_C2MISR_MISF2_Pos)               /*!< 0x00000004 */
-#define HSEM_C2MISR_MISF2         HSEM_C2MISR_MISF2_Msk                          /*!<semaphore 2 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF3_Pos     (3U)
-#define HSEM_C2MISR_MISF3_Msk     (0x1UL << HSEM_C2MISR_MISF3_Pos)               /*!< 0x00000008 */
-#define HSEM_C2MISR_MISF3         HSEM_C2MISR_MISF3_Msk                          /*!<semaphore 3 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF4_Pos     (4U)
-#define HSEM_C2MISR_MISF4_Msk     (0x1UL << HSEM_C2MISR_MISF4_Pos)               /*!< 0x00000010 */
-#define HSEM_C2MISR_MISF4         HSEM_C2MISR_MISF4_Msk                          /*!<semaphore 4 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF5_Pos     (5U)
-#define HSEM_C2MISR_MISF5_Msk     (0x1UL << HSEM_C2MISR_MISF5_Pos)               /*!< 0x00000020 */
-#define HSEM_C2MISR_MISF5         HSEM_C2MISR_MISF5_Msk                          /*!<semaphore 5 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF6_Pos     (6U)
-#define HSEM_C2MISR_MISF6_Msk     (0x1UL << HSEM_C2MISR_MISF6_Pos)               /*!< 0x00000040 */
-#define HSEM_C2MISR_MISF6         HSEM_C2MISR_MISF6_Msk                          /*!<semaphore 6 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF7_Pos     (7U)
-#define HSEM_C2MISR_MISF7_Msk     (0x1UL << HSEM_C2MISR_MISF7_Pos)               /*!< 0x00000080 */
-#define HSEM_C2MISR_MISF7         HSEM_C2MISR_MISF7_Msk                          /*!<semaphore 7 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF8_Pos     (8U)
-#define HSEM_C2MISR_MISF8_Msk     (0x1UL << HSEM_C2MISR_MISF8_Pos)               /*!< 0x00000100 */
-#define HSEM_C2MISR_MISF8         HSEM_C2MISR_MISF8_Msk                          /*!<semaphore 8 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF9_Pos     (9U)
-#define HSEM_C2MISR_MISF9_Msk     (0x1UL << HSEM_C2MISR_MISF9_Pos)               /*!< 0x00000200 */
-#define HSEM_C2MISR_MISF9         HSEM_C2MISR_MISF9_Msk                          /*!<semaphore 9 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF10_Pos    (10U)
-#define HSEM_C2MISR_MISF10_Msk    (0x1UL << HSEM_C2MISR_MISF10_Pos)              /*!< 0x00000400 */
-#define HSEM_C2MISR_MISF10        HSEM_C2MISR_MISF10_Msk                         /*!<semaphore 10 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF11_Pos    (11U)
-#define HSEM_C2MISR_MISF11_Msk    (0x1UL << HSEM_C2MISR_MISF11_Pos)              /*!< 0x00000800 */
-#define HSEM_C2MISR_MISF11        HSEM_C2MISR_MISF11_Msk                         /*!<semaphore 11 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF12_Pos    (12U)
-#define HSEM_C2MISR_MISF12_Msk    (0x1UL << HSEM_C2MISR_MISF12_Pos)              /*!< 0x00001000 */
-#define HSEM_C2MISR_MISF12        HSEM_C2MISR_MISF12_Msk                         /*!<semaphore 12 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF13_Pos    (13U)
-#define HSEM_C2MISR_MISF13_Msk    (0x1UL << HSEM_C2MISR_MISF13_Pos)              /*!< 0x00002000 */
-#define HSEM_C2MISR_MISF13        HSEM_C2MISR_MISF13_Msk                         /*!<semaphore 13 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF14_Pos    (14U)
-#define HSEM_C2MISR_MISF14_Msk    (0x1UL << HSEM_C2MISR_MISF14_Pos)              /*!< 0x00004000 */
-#define HSEM_C2MISR_MISF14        HSEM_C2MISR_MISF14_Msk                         /*!<semaphore 14 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF15_Pos    (15U)
-#define HSEM_C2MISR_MISF15_Msk    (0x1UL << HSEM_C2MISR_MISF15_Pos)              /*!< 0x00008000 */
-#define HSEM_C2MISR_MISF15        HSEM_C2MISR_MISF15_Msk                         /*!<semaphore 15 CPU2 interrupt masked status bit. */
-
-/********************  Bit definition for HSEM_CR register  *****************/
-#define HSEM_CR_COREID_Pos       (8U)
-#define HSEM_CR_COREID_Msk       (0xFUL << HSEM_CR_COREID_Pos)                 /*!< 0x00000F00 */
-#define HSEM_CR_COREID           HSEM_CR_COREID_Msk                            /*!<CoreID of semaphores to be cleared. */
-#define HSEM_CR_COREID_CPU1      (0x4U << HSEM_CR_COREID_Pos)
-#define HSEM_CR_COREID_CPU2      (0x8U << HSEM_CR_COREID_Pos)
-#if defined(CORE_CM0PLUS)
-#define HSEM_CR_COREID_CURRENT   HSEM_CR_COREID_CPU2
-#else
-#define HSEM_CR_COREID_CURRENT   HSEM_CR_COREID_CPU1
-#endif
-#define HSEM_CR_KEY_Pos          (16U)
-#define HSEM_CR_KEY_Msk          (0xFFFFUL << HSEM_CR_KEY_Pos)                 /*!< 0xFFFF0000 */
-#define HSEM_CR_KEY              HSEM_CR_KEY_Msk                               /*!<semaphores clear key. */
-
-/********************  Bit definition for HSEM_KEYR register  *****************/
-#define HSEM_KEYR_KEY_Pos        (16U)
-#define HSEM_KEYR_KEY_Msk        (0xFFFFUL << HSEM_KEYR_KEY_Pos)               /*!< 0xFFFF0000 */
-#define HSEM_KEYR_KEY            HSEM_KEYR_KEY_Msk                             /*!<semaphores clear key. */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Public Key Accelerator (PKA)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bits definition for PKA_CR register  **************/
-#define PKA_CR_EN_Pos              (0U)
-#define PKA_CR_EN_Msk              (0x1UL << PKA_CR_EN_Pos)                /*!< 0x00000001 */
-#define PKA_CR_EN                  PKA_CR_EN_Msk                           /*!< PKA enable */
-#define PKA_CR_START_Pos           (1U)
-#define PKA_CR_START_Msk           (0x1UL << PKA_CR_START_Pos)             /*!< 0x00000002 */
-#define PKA_CR_START               PKA_CR_START_Msk                        /*!< Start operation */
-#define PKA_CR_MODE_Pos            (8U)
-#define PKA_CR_MODE_Msk            (0x3FUL << PKA_CR_MODE_Pos)             /*!< 0x00003F00 */
-#define PKA_CR_MODE                PKA_CR_MODE_Msk                         /*!< MODE[5:0] PKA operation code */
-#define PKA_CR_MODE_0              (0x01UL << PKA_CR_MODE_Pos)             /*!< 0x00000100 */
-#define PKA_CR_MODE_1              (0x02UL << PKA_CR_MODE_Pos)             /*!< 0x00000200 */
-#define PKA_CR_MODE_2              (0x04UL << PKA_CR_MODE_Pos)             /*!< 0x00000400 */
-#define PKA_CR_MODE_3              (0x08UL << PKA_CR_MODE_Pos)             /*!< 0x00000800 */
-#define PKA_CR_MODE_4              (0x10UL << PKA_CR_MODE_Pos)             /*!< 0x00001000 */
-#define PKA_CR_MODE_5              (0x20UL << PKA_CR_MODE_Pos)             /*!< 0x00002000 */
-#define PKA_CR_PROCENDIE_Pos       (17U)
-#define PKA_CR_PROCENDIE_Msk       (0x1UL << PKA_CR_PROCENDIE_Pos)         /*!< 0x00020000 */
-#define PKA_CR_PROCENDIE           PKA_CR_PROCENDIE_Msk                    /*!< End of operation interrupt enable */
-#define PKA_CR_RAMERRIE_Pos        (19U)
-#define PKA_CR_RAMERRIE_Msk        (0x1UL << PKA_CR_RAMERRIE_Pos)          /*!< 0x00080000 */
-#define PKA_CR_RAMERRIE            PKA_CR_RAMERRIE_Msk                     /*!< RAM error interrupt enable */
-#define PKA_CR_ADDRERRIE_Pos       (20U)
-#define PKA_CR_ADDRERRIE_Msk       (0x1UL << PKA_CR_ADDRERRIE_Pos)         /*!< 0x00100000 */
-#define PKA_CR_ADDRERRIE           PKA_CR_ADDRERRIE_Msk                    /*!< RAM error interrupt enable */
-
-/*******************  Bits definition for PKA_SR register  **************/
-#define PKA_SR_BUSY_Pos            (16U)
-#define PKA_SR_BUSY_Msk            (0x1UL << PKA_SR_BUSY_Pos)              /*!< 0x00010000 */
-#define PKA_SR_BUSY                PKA_SR_BUSY_Msk                         /*!< PKA operation is in progress */
-#define PKA_SR_PROCENDF_Pos        (17U)
-#define PKA_SR_PROCENDF_Msk        (0x1UL << PKA_SR_PROCENDF_Pos)          /*!< 0x00020000 */
-#define PKA_SR_PROCENDF            PKA_SR_PROCENDF_Msk                     /*!< PKA end of operation flag */
-#define PKA_SR_RAMERRF_Pos         (19U)
-#define PKA_SR_RAMERRF_Msk         (0x1UL << PKA_SR_RAMERRF_Pos)           /*!< 0x00080000 */
-#define PKA_SR_RAMERRF             PKA_SR_RAMERRF_Msk                      /*!< PKA RAM error flag */
-#define PKA_SR_ADDRERRF_Pos        (20U)
-#define PKA_SR_ADDRERRF_Msk        (0x1UL << PKA_SR_ADDRERRF_Pos)          /*!< 0x00100000 */
-#define PKA_SR_ADDRERRF            PKA_SR_ADDRERRF_Msk                     /*!< Address error flag */
-
-/*******************  Bits definition for PKA_CLRFR register  **************/
-#define PKA_CLRFR_PROCENDFC_Pos    (17U)
-#define PKA_CLRFR_PROCENDFC_Msk    (0x1UL << PKA_CLRFR_PROCENDFC_Pos)      /*!< 0x00020000 */
-#define PKA_CLRFR_PROCENDFC        PKA_CLRFR_PROCENDFC_Msk                 /*!< Clear PKA end of operation flag */
-#define PKA_CLRFR_RAMERRFC_Pos     (19U)
-#define PKA_CLRFR_RAMERRFC_Msk     (0x1UL << PKA_CLRFR_RAMERRFC_Pos)       /*!< 0x00080000 */
-#define PKA_CLRFR_RAMERRFC         PKA_CLRFR_RAMERRFC_Msk                  /*!< Clear PKA RAM error flag */
-#define PKA_CLRFR_ADDRERRFC_Pos    (20U)
-#define PKA_CLRFR_ADDRERRFC_Msk    (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)      /*!< 0x00100000 */
-#define PKA_CLRFR_ADDRERRFC        PKA_CLRFR_ADDRERRFC_Msk                 /*!< Clear address error flag */
-
-/*******************  Bits definition for PKA RAM  *************************/
-#define PKA_RAM_OFFSET                            0x400U                           /*!< PKA RAM address offset */
-
-/* Compute Montgomery parameter input data */
-#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS       ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_MONTGOMERY_PARAM_IN_MODULUS           ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Compute Montgomery parameter output data */
-#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER        ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Output Montgomery parameter */
-
-/* Compute modular exponentiation input data */
-#define PKA_MODULAR_EXP_IN_EXP_NB_BITS            ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent number of bits */
-#define PKA_MODULAR_EXP_IN_OP_NB_BITS             ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM       ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Input storage area for Montgomery parameter */
-#define PKA_MODULAR_EXP_IN_EXPONENT_BASE          ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input base of the exponentiation */
-#define PKA_MODULAR_EXP_IN_EXPONENT               ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent to process */
-#define PKA_MODULAR_EXP_IN_MODULUS                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Compute modular exponentiation output data */
-#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM      ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Output storage area for Montgomery parameter */
-#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1          ((0x724U - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 1 */
-#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2          ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 2 */
-#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE         ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Output base of the exponentiation */
-#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3          ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 3 */
-
-/* Compute ECC scalar multiplication input data */
-#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS         ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent number of bits */
-#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS          ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN        ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_ECC_SCALAR_MUL_IN_A_COEFF             ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_ECC_SCALAR_MUL_IN_MOD_GF              ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM    ((0x4B4U - PKA_RAM_OFFSET)>>2)   /*!< Input storage area for Montgomery parameter */
-#define PKA_ECC_SCALAR_MUL_IN_K                   ((0x508U - PKA_RAM_OFFSET)>>2)   /*!< Input 'k' of KP */
-#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X     ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y     ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-
-/* Compute ECC scalar multiplication output data */
-#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X           ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Output result X coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y           ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Output result Y coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1     ((0xDE8U - PKA_RAM_OFFSET)>>2)   /*!< Output last double X1 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1     ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Output last double Y1 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1     ((0xE90U - PKA_RAM_OFFSET)>>2)   /*!< Output last double Z1 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2     ((0xEE4U - PKA_RAM_OFFSET)>>2)   /*!< Output check point X2 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2     ((0xF38U - PKA_RAM_OFFSET)>>2)   /*!< Output check point Y2 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2     ((0xF8CU - PKA_RAM_OFFSET)>>2)   /*!< Output check point Z2 coordinate */
-
-/* Point check input data */
-#define PKA_POINT_CHECK_IN_MOD_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_POINT_CHECK_IN_A_COEFF_SIGN           ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_POINT_CHECK_IN_A_COEFF                ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_POINT_CHECK_IN_B_COEFF                ((0x7FCU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'b' coefficient */
-#define PKA_POINT_CHECK_IN_MOD_GF                 ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_POINT_CHECK_IN_INITIAL_POINT_X        ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y        ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-
-/* Point check output data */
-#define PKA_POINT_CHECK_OUT_ERROR                 ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Output error */
-
-/* ECDSA signature input data */
-#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS           ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input order number of bits */
-#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS             ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN            ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_ECDSA_SIGN_IN_A_COEFF                 ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_ECDSA_SIGN_IN_MOD_GF                  ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_ECDSA_SIGN_IN_K                       ((0x508U - PKA_RAM_OFFSET)>>2)   /*!< Input k value of the ECDSA */
-#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X         ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y         ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-#define PKA_ECDSA_SIGN_IN_HASH_E                  ((0xDE8U - PKA_RAM_OFFSET)>>2)   /*!< Input e, hash of the message */
-#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D           ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Input d, private key */
-#define PKA_ECDSA_SIGN_IN_ORDER_N                 ((0xE94U - PKA_RAM_OFFSET)>>2)   /*!< Input n, order of the curve */
-
-/* ECDSA signature output data */
-#define PKA_ECDSA_SIGN_OUT_ERROR                  ((0xEE8U - PKA_RAM_OFFSET)>>2)   /*!< Output error */
-#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R            ((0x700U - PKA_RAM_OFFSET)>>2)   /*!< Output signature r */
-#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S            ((0x754U - PKA_RAM_OFFSET)>>2)   /*!< Output signature s */
-#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X          ((0x103CU - PKA_RAM_OFFSET)>>2)   /*!< Output final point kP X coordinate */
-#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y          ((0x1090U - PKA_RAM_OFFSET)>>2)   /*!< Output final point kP Y coordinate */
-
-/* ECDSA verification input data */
-#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS          ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input order number of bits */
-#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS            ((0x4B4U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN           ((0x45CU - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_ECDSA_VERIF_IN_A_COEFF                ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_ECDSA_VERIF_IN_MOD_GF                 ((0x4B8U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X        ((0x5E8U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y        ((0x63CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X     ((0xF40U - PKA_RAM_OFFSET)>>2)   /*!< Input public key point X coordinate */
-#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y     ((0xF94U - PKA_RAM_OFFSET)>>2)   /*!< Input public key point Y coordinate */
-#define PKA_ECDSA_VERIF_IN_SIGNATURE_R            ((0x1098U - PKA_RAM_OFFSET)>>2)   /*!< Input r, part of the signature */
-#define PKA_ECDSA_VERIF_IN_SIGNATURE_S            ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input s, part of the signature */
-#define PKA_ECDSA_VERIF_IN_HASH_E                 ((0xFE8U - PKA_RAM_OFFSET)>>2)   /*!< Input e, hash of the message */
-#define PKA_ECDSA_VERIF_IN_ORDER_N                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input n, order of the curve */
-
-/* ECDSA verification output data */
-#define PKA_ECDSA_VERIF_OUT_RESULT                ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* RSA CRT exponentiation input data */
-#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operands number of bits */
-#define PKA_RSA_CRT_EXP_IN_DP_CRT                 ((0x65CU - PKA_RAM_OFFSET)>>2)   /*!< Input Dp CRT parameter */
-#define PKA_RSA_CRT_EXP_IN_DQ_CRT                 ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Input Dq CRT parameter */
-#define PKA_RSA_CRT_EXP_IN_QINV_CRT               ((0x7ECU - PKA_RAM_OFFSET)>>2)   /*!< Input qInv CRT parameter */
-#define PKA_RSA_CRT_EXP_IN_PRIME_P                ((0x97CU - PKA_RAM_OFFSET)>>2)   /*!< Input Prime p */
-#define PKA_RSA_CRT_EXP_IN_PRIME_Q                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input Prime q */
-#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE          ((0xEECU - PKA_RAM_OFFSET)>>2)   /*!< Input base of the exponentiation */
-
-/* RSA CRT exponentiation output data */
-#define PKA_RSA_CRT_EXP_OUT_RESULT                ((0x724U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular reduction input data */
-#define PKA_MODULAR_REDUC_IN_OP_LENGTH            ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input operand length */
-#define PKA_MODULAR_REDUC_IN_OPERAND              ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand */
-#define PKA_MODULAR_REDUC_IN_MOD_LENGTH           ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus length */
-#define PKA_MODULAR_REDUC_IN_MODULUS              ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Modular reduction output data */
-#define PKA_MODULAR_REDUC_OUT_RESULT              ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Arithmetic addition input data */
-#define PKA_ARITHMETIC_ADD_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_ADD_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_ADD_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Arithmetic addition output data */
-#define PKA_ARITHMETIC_ADD_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Arithmetic substraction input data */
-#define PKA_ARITHMETIC_SUB_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_SUB_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_SUB_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Arithmetic substraction output data */
-#define PKA_ARITHMETIC_SUB_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Arithmetic multiplication input data */
-#define PKA_ARITHMETIC_MUL_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_MUL_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_MUL_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Arithmetic multiplication output data */
-#define PKA_ARITHMETIC_MUL_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Comparison input data */
-#define PKA_COMPARISON_NB_BITS                    ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_COMPARISON_IN_OP1                     ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_COMPARISON_IN_OP2                     ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Comparison output data */
-#define PKA_COMPARISON_OUT_RESULT                 ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular addition input data */
-#define PKA_MODULAR_ADD_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_ADD_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MODULAR_ADD_IN_OP2                    ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_MODULAR_ADD_IN_OP3_MOD                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 (modulus) */
-
-/* Modular addition output data */
-#define PKA_MODULAR_ADD_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular inversion input data */
-#define PKA_MODULAR_INV_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_INV_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MODULAR_INV_IN_OP2_MOD                ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 (modulus) */
-
-/* Modular inversion output data */
-#define PKA_MODULAR_INV_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular substraction input data */
-#define PKA_MODULAR_SUB_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_SUB_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MODULAR_SUB_IN_OP2                    ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_MODULAR_SUB_IN_OP3_MOD                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 */
-
-/* Modular substraction output data */
-#define PKA_MODULAR_SUB_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Montgomery multiplication input data */
-#define PKA_MONTGOMERY_MUL_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MONTGOMERY_MUL_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MONTGOMERY_MUL_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_MONTGOMERY_MUL_IN_OP3_MOD             ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Montgomery multiplication output data */
-#define PKA_MONTGOMERY_MUL_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Generic Arithmetic input data */
-#define PKA_ARITHMETIC_ALL_OPS_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_ALL_OPS_IN_OP1             ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_ALL_OPS_IN_OP2             ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_ARITHMETIC_ALL_OPS_IN_OP3             ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Generic Arithmetic output data */
-#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT         ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Power Control                                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR1 register  ********************/
-#define PWR_CR1_LPMS_Pos               (0U)
-#define PWR_CR1_LPMS_Msk               (0x7UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000007 */
-#define PWR_CR1_LPMS                   PWR_CR1_LPMS_Msk                        /*!< Low Power Mode Selection for CPU1 */
-#define PWR_CR1_LPMS_0                 (0x1UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000001 */
-#define PWR_CR1_LPMS_1                 (0x2UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000002 */
-#define PWR_CR1_LPMS_2                 (0x4UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000004 */
-
-#define PWR_CR1_SUBGHZSPINSSSEL_Pos    (3U)
-#define PWR_CR1_SUBGHZSPINSSSEL_Msk    (0x1UL << PWR_CR1_SUBGHZSPINSSSEL_Pos)  /*!< 0x00000008 */
-#define PWR_CR1_SUBGHZSPINSSSEL        PWR_CR1_SUBGHZSPINSSSEL_Msk             /*!< Sub-GHz radio SPI NSS source select */
-
-#define PWR_CR1_FPDR_Pos               (4U)
-#define PWR_CR1_FPDR_Msk               (0x1UL << PWR_CR1_FPDR_Pos)             /*!< 0x00000010 */
-#define PWR_CR1_FPDR                   PWR_CR1_FPDR_Msk                        /*!< Flash power down mode during LPrun for CPU1 */
-
-#define PWR_CR1_FPDS_Pos               (5U)
-#define PWR_CR1_FPDS_Msk               (0x1UL << PWR_CR1_FPDS_Pos)             /*!< 0x00000020 */
-#define PWR_CR1_FPDS                   PWR_CR1_FPDS_Msk                        /*!< Flash power down mode during LPsleep for CPU1 */
-
-#define PWR_CR1_DBP_Pos                (8U)
-#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
-#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Backup Domain write protection */
-
-#define PWR_CR1_VOS_Pos                (9U)
-#define PWR_CR1_VOS_Msk                (0x3UL << PWR_CR1_VOS_Pos)              /*!< 0x00000600 */
-#define PWR_CR1_VOS                    PWR_CR1_VOS_Msk                         /*!< Voltage scaling range selection */
-#define PWR_CR1_VOS_0                  (0x1UL << PWR_CR1_VOS_Pos)              /*!< 0x00000200 */
-#define PWR_CR1_VOS_1                  (0x2UL << PWR_CR1_VOS_Pos)              /*!< 0x00000400 */
-
-#define PWR_CR1_LPR_Pos                (14U)
-#define PWR_CR1_LPR_Msk                (0x1UL << PWR_CR1_LPR_Pos)              /*!< 0x00004000 */
-#define PWR_CR1_LPR                    PWR_CR1_LPR_Msk                         /*!< Regulator Low-Power Run mode */
-
-/********************  Bit definition for PWR_CR2 register  ********************/
-#define PWR_CR2_PVDE_Pos               (0U)
-#define PWR_CR2_PVDE_Msk               (0x1UL << PWR_CR2_PVDE_Pos)             /*!< 0x00000001 */
-#define PWR_CR2_PVDE                   PWR_CR2_PVDE_Msk                        /*!< Power voltage detector enable */
-
-#define PWR_CR2_PLS_Pos                (1U)
-#define PWR_CR2_PLS_Msk                (0x7UL << PWR_CR2_PLS_Pos)              /*!< 0x0000000E */
-#define PWR_CR2_PLS                    PWR_CR2_PLS_Msk                         /*!< Power voltage detector level selection */
-#define PWR_CR2_PLS_0                  (0x1UL << PWR_CR2_PLS_Pos)              /*!< 0x00000002 */
-#define PWR_CR2_PLS_1                  (0x2UL << PWR_CR2_PLS_Pos)              /*!< 0x00000004 */
-#define PWR_CR2_PLS_2                  (0x4UL << PWR_CR2_PLS_Pos)              /*!< 0x00000008 */
-
-#define PWR_CR2_PVME3_Pos              (6U)
-#define PWR_CR2_PVME3_Msk              (0x1UL << PWR_CR2_PVME3_Pos)            /*!< 0x00000040 */
-#define PWR_CR2_PVME3                  PWR_CR2_PVME3_Msk                       /*!< Peripherical Voltage Monitor Vdda Enable */
-
-/********************  Bit definition for PWR_CR3 register  ********************/
-#define PWR_CR3_EWUP_Pos               (0U)
-#define PWR_CR3_EWUP_Msk               (0x07UL << PWR_CR3_EWUP_Pos)            /*!< 0x00000007 */
-#define PWR_CR3_EWUP                   PWR_CR3_EWUP_Msk                        /*!< Enable all external Wake-Up lines  */
-#define PWR_CR3_EWUP1_Pos              (0U)
-#define PWR_CR3_EWUP1_Msk              (0x1UL << PWR_CR3_EWUP1_Pos)            /*!< 0x00000001 */
-#define PWR_CR3_EWUP1                  PWR_CR3_EWUP1_Msk                       /*!< Enable external WKUP Pin 1 [line 0] */
-#define PWR_CR3_EWUP2_Pos              (1U)
-#define PWR_CR3_EWUP2_Msk              (0x1UL << PWR_CR3_EWUP2_Pos)            /*!< 0x00000002 */
-#define PWR_CR3_EWUP2                  PWR_CR3_EWUP2_Msk                       /*!< Enable external WKUP Pin 2 [line 1] */
-#define PWR_CR3_EWUP3_Pos              (2U)
-#define PWR_CR3_EWUP3_Msk              (0x1UL << PWR_CR3_EWUP3_Pos)            /*!< 0x00000004 */
-#define PWR_CR3_EWUP3                  PWR_CR3_EWUP3_Msk                       /*!< Enable external WKUP Pin 3 [line 2] */
-
-#define PWR_CR3_ULPEN_Pos              (7U)
-#define PWR_CR3_ULPEN_Msk              (0x1UL << PWR_CR3_ULPEN_Pos)            /*!< 0x00000080 */
-#define PWR_CR3_ULPEN                  PWR_CR3_ULPEN_Msk                       /*!< Enable periodical sampling of supply voltage in Stop and Standby modes for detecting condition of PDR and BOR reset */
-
-#define PWR_CR3_EWPVD_Pos              (8U)
-#define PWR_CR3_EWPVD_Msk              (0x1UL << PWR_CR3_EWPVD_Pos)            /*!< 0x00000100 */
-#define PWR_CR3_EWPVD                  PWR_CR3_EWPVD_Msk                       /*!< Enable wakeup PVD for CPU1 */
-
-#define PWR_CR3_RRS_Pos                (9U)
-#define PWR_CR3_RRS_Msk                (0x1UL << PWR_CR3_RRS_Pos)              /*!< 0x00000200 */
-#define PWR_CR3_RRS                    PWR_CR3_RRS_Msk                         /*!< SRAM2 retention in STANDBY mode */
-
-#define PWR_CR3_APC_Pos                (10U)
-#define PWR_CR3_APC_Msk                (0x1UL << PWR_CR3_APC_Pos)              /*!< 0x00000400 */
-#define PWR_CR3_APC                    PWR_CR3_APC_Msk                         /*!< Apply pull-up and pull-down configuration for CPU1 */
-
-#define PWR_CR3_EWRFBUSY_Pos           (11U)
-#define PWR_CR3_EWRFBUSY_Msk           (0x1UL << PWR_CR3_EWRFBUSY_Pos)         /*!< 0x00008000 */
-#define PWR_CR3_EWRFBUSY                PWR_CR3_EWRFBUSY_Msk                   /*!< Enable Radio busy IRQ and wake-up for CPU1 */
-#define PWR_CR3_EWRFIRQ_Pos            (13U)
-#define PWR_CR3_EWRFIRQ_Msk            (0x1UL << PWR_CR3_EWRFIRQ_Pos)          /*!< 0x00020000 */
-#define PWR_CR3_EWRFIRQ                PWR_CR3_EWRFIRQ_Msk                     /*!< Enable Radio IRQ[2:0] and wake-up for CPU1 */
-
-#define PWR_CR3_EC2H_Pos               (14U)
-#define PWR_CR3_EC2H_Msk               (0x1UL << PWR_CR3_EC2H_Pos)             /*!< 0x00040000 */
-#define PWR_CR3_EC2H                    PWR_CR3_EC2H_Msk                       /*!< CPU2 Hold interrupt for CPU1 */
-
-#define PWR_CR3_EIWUL_Pos              (15U)
-#define PWR_CR3_EIWUL_Msk              (0x1UL << PWR_CR3_EIWUL_Pos)            /*!< 0x00080000 */
-#define PWR_CR3_EIWUL                  PWR_CR3_EIWUL_Msk                       /*!< Internal Wake-Up line interrupt for CPU1 */
-
-/********************  Bit definition for PWR_CR4 register  ********************/
-#define PWR_CR4_WP1_Pos                (0U)
-#define PWR_CR4_WP1_Msk                (0x1UL << PWR_CR4_WP1_Pos)              /*!< 0x00000001 */
-#define PWR_CR4_WP1                    PWR_CR4_WP1_Msk                         /*!< Wake-Up Pin 1 [line 0] polarity */
-#define PWR_CR4_WP2_Pos                (1U)
-#define PWR_CR4_WP2_Msk                (0x1UL << PWR_CR4_WP2_Pos)              /*!< 0x00000002 */
-#define PWR_CR4_WP2                    PWR_CR4_WP2_Msk                         /*!< Wake-Up Pin 2 [line 1] polarity */
-#define PWR_CR4_WP3_Pos                (2U)
-#define PWR_CR4_WP3_Msk                (0x1UL << PWR_CR4_WP3_Pos)              /*!< 0x00000004 */
-#define PWR_CR4_WP3                    PWR_CR4_WP3_Msk                         /*!< Wake-Up Pin 3 [line 2] polarity */
-
-#define PWR_CR4_VBE_Pos                (8U)
-#define PWR_CR4_VBE_Msk                (0x1UL << PWR_CR4_VBE_Pos)              /*!< 0x00000100 */
-#define PWR_CR4_VBE                    PWR_CR4_VBE_Msk                         /*!< VBAT battery charging enable  */
-#define PWR_CR4_VBRS_Pos               (9U)
-#define PWR_CR4_VBRS_Msk               (0x1UL << PWR_CR4_VBRS_Pos)             /*!< 0x00000200 */
-#define PWR_CR4_VBRS                   PWR_CR4_VBRS_Msk                        /*!< VBAT battery charging resistor selection */
-
-#define PWR_CR4_WRFBUSYP_Pos           (11U)
-#define PWR_CR4_WRFBUSYP_Msk           (0x1UL << PWR_CR4_WRFBUSYP_Pos)         /*!< 0x00008000 */
-#define PWR_CR4_WRFBUSYP               PWR_CR4_WRFBUSYP_Msk                    /*!< Wake-up radio busy polarity */
-
-#define PWR_CR4_C2BOOT_Pos             (15U)
-#define PWR_CR4_C2BOOT_Msk             (0x1UL << PWR_CR4_C2BOOT_Pos)           /*!< 0x00008000 */
-#define PWR_CR4_C2BOOT                 PWR_CR4_C2BOOT_Msk                      /*!< Boot CPU2 after reset or wakeup from Stop or Standby modes */
-
-/********************  Bit definition for PWR_SR1 register  ********************/
-#define PWR_SR1_WUF_Pos                (0U)
-#define PWR_SR1_WUF_Msk                (0x1FUL << PWR_SR1_WUF_Pos)             /*!< 0x00000007 */
-#define PWR_SR1_WUF                    PWR_SR1_WUF_Msk                         /*!< Wakeup Flags of all pins */
-#define PWR_SR1_WUF1_Pos               (0U)
-#define PWR_SR1_WUF1_Msk               (0x1UL << PWR_SR1_WUF1_Pos)             /*!< 0x00000001 */
-#define PWR_SR1_WUF1                   PWR_SR1_WUF1_Msk                        /*!< Wakeup Pin 1 [Flag 0] */
-#define PWR_SR1_WUF2_Pos               (1U)
-#define PWR_SR1_WUF2_Msk               (0x1UL << PWR_SR1_WUF2_Pos)             /*!< 0x00000002 */
-#define PWR_SR1_WUF2                   PWR_SR1_WUF2_Msk                        /*!< Wakeup Pin 2 [Flag 1] */
-#define PWR_SR1_WUF3_Pos               (2U)
-#define PWR_SR1_WUF3_Msk               (0x1UL << PWR_SR1_WUF3_Pos)             /*!< 0x00000004 */
-#define PWR_SR1_WUF3                   PWR_SR1_WUF3_Msk                        /*!< Wakeup Pin 3 [Flag 2] */
-
-#define PWR_SR1_WPVDF_Pos              (8U)
-#define PWR_SR1_WPVDF_Msk              (0x1UL << PWR_SR1_WPVDF_Pos)            /*!< 0x00000100 */
-#define PWR_SR1_WPVDF                  PWR_SR1_WPVDF_Msk                       /*!< Wakeup PVD flag */
-
-#define PWR_SR1_WRFBUSYF_Pos           (11U)
-#define PWR_SR1_WRFBUSYF_Msk           (0x1UL << PWR_SR1_WRFBUSYF_Pos)          /*!< 0x00000800 */
-#define PWR_SR1_WRFBUSYF               PWR_SR1_WRFBUSYF_Msk                     /*!< Wakeup radio busy flag */
-
-#define PWR_SR1_C2HF_Pos               (14U)
-#define PWR_SR1_C2HF_Msk               (0x1UL << PWR_SR1_C2HF_Pos)             /*!< 0x00004000 */
-#define PWR_SR1_C2HF                   PWR_SR1_C2HF_Msk                        /*!< CPU2 Hold interrupt flag */
-
-#define PWR_SR1_WUFI_Pos               (15U)
-#define PWR_SR1_WUFI_Msk               (0x1UL << PWR_SR1_WUFI_Pos)             /*!< 0x00008000 */
-#define PWR_SR1_WUFI                   PWR_SR1_WUFI_Msk                        /*!< Internal wakeup interrupt flag */
-
-/********************  Bit definition for PWR_SR2 register  ********************/
-#define PWR_SR2_C2BOOTS_Pos            (0U)
-#define PWR_SR2_C2BOOTS_Msk            (0x1UL << PWR_SR2_C2BOOTS_Pos)          /*!< 0x00000001 */
-#define PWR_SR2_C2BOOTS                PWR_SR2_C2BOOTS_Msk                     /*!< CPU2 boot or wakeup request source information */
-
-#define PWR_SR2_RFBUSYS_Pos            (1U)
-#define PWR_SR2_RFBUSYS_Msk            (0x1UL << PWR_SR2_RFBUSYS_Pos)          /*!< 0x00000002 */
-#define PWR_SR2_RFBUSYS                PWR_SR2_RFBUSYS_Msk                     /*!< Radio busy signal status */
-
-#define PWR_SR2_RFBUSYMS_Pos           (2U)
-#define PWR_SR2_RFBUSYMS_Msk           (0x1UL << PWR_SR2_RFBUSYMS_Pos)         /*!< 0x00000004 */
-#define PWR_SR2_RFBUSYMS               PWR_SR2_RFBUSYMS_Msk                    /*!< Radio busy masked signal status */
-
-#define PWR_SR2_SMPSRDY_Pos            (3U)
-#define PWR_SR2_SMPSRDY_Msk            (0x1UL << PWR_SR2_SMPSRDY_Pos)          /*!< 0x00000008 */
-#define PWR_SR2_SMPSRDY                PWR_SR2_SMPSRDY_Msk                     /*!< SMPS ready flag */
-#define PWR_SR2_LDORDY_Pos             (4U)
-#define PWR_SR2_LDORDY_Msk             (0x1UL << PWR_SR2_LDORDY_Pos)           /*!< 0x00000010 */
-#define PWR_SR2_LDORDY                 PWR_SR2_LDORDY_Msk                      /*!< LDO ready flag */
-
-#define PWR_SR2_RFEOLF_Pos             (5U)
-#define PWR_SR2_RFEOLF_Msk             (0x1UL << PWR_SR2_RFEOLF_Pos)           /*!< 0x00000020 */
-#define PWR_SR2_RFEOLF                 PWR_SR2_RFEOLF_Msk                      /*!< Radio end of life flag */
-
-#define PWR_SR2_REGMRS_Pos             (6U)
-#define PWR_SR2_REGMRS_Msk             (0x1UL << PWR_SR2_REGMRS_Pos)           /*!< 0x00000040 */
-#define PWR_SR2_REGMRS                 PWR_SR2_REGMRS_Msk                      /*!< Main regulator status */
-
-#define PWR_SR2_FLASHRDY_Pos           (7U)
-#define PWR_SR2_FLASHRDY_Msk           (0x1UL << PWR_SR2_FLASHRDY_Pos)         /*!< 0x00000080 */
-#define PWR_SR2_FLASHRDY               PWR_SR2_FLASHRDY_Msk                    /*!< Flash ready */
-
-#define PWR_SR2_REGLPS_Pos             (8U)
-#define PWR_SR2_REGLPS_Msk             (0x1UL << PWR_SR2_REGLPS_Pos)           /*!< 0x00000100 */
-#define PWR_SR2_REGLPS                 PWR_SR2_REGLPS_Msk                      /*!< Low-power regulator ready */
-#define PWR_SR2_REGLPF_Pos             (9U)
-#define PWR_SR2_REGLPF_Msk             (0x1UL << PWR_SR2_REGLPF_Pos)           /*!< 0x00000200 */
-#define PWR_SR2_REGLPF                 PWR_SR2_REGLPF_Msk                      /*!< Low-power regulator being used */
-
-#define PWR_SR2_VOSF_Pos               (10U)
-#define PWR_SR2_VOSF_Msk               (0x1UL << PWR_SR2_VOSF_Pos)             /*!< 0x00000400 */
-#define PWR_SR2_VOSF                   PWR_SR2_VOSF_Msk                        /*!< Voltage scaling flag    */
-#define PWR_SR2_PVDO_Pos               (11U)
-#define PWR_SR2_PVDO_Msk               (0x1UL << PWR_SR2_PVDO_Pos)             /*!< 0x00000800 */
-#define PWR_SR2_PVDO                   PWR_SR2_PVDO_Msk                        /*!< Power voltage detector output */
-
-#define PWR_SR2_PVMO3_Pos              (14U)
-#define PWR_SR2_PVMO3_Msk              (0x1UL << PWR_SR2_PVMO3_Pos)            /*!< 0x00004000 */
-#define PWR_SR2_PVMO3                  PWR_SR2_PVMO3_Msk                       /*!< Peripheral voltage monitor output 3: VDDA vs. 1.62V */
-
-/********************  Bit definition for PWR_SCR register  ********************/
-#define PWR_SCR_CWUF_Pos               (0U)
-#define PWR_SCR_CWUF_Msk               (0x7UL << PWR_SCR_CWUF_Pos)             /*!< 0x00000007 */
-#define PWR_SCR_CWUF                   PWR_SCR_CWUF_Msk                        /*!< Clear Wake-up Flags for all pins */
-#define PWR_SCR_CWUF1_Pos              (0U)
-#define PWR_SCR_CWUF1_Msk              (0x1UL << PWR_SCR_CWUF1_Pos)            /*!< 0x00000001 */
-#define PWR_SCR_CWUF1                  PWR_SCR_CWUF1_Msk                       /*!< Clear Wake-up Pin 1 [Flag 0] */
-#define PWR_SCR_CWUF2_Pos              (1U)
-#define PWR_SCR_CWUF2_Msk              (0x1UL << PWR_SCR_CWUF2_Pos)            /*!< 0x00000002 */
-#define PWR_SCR_CWUF2                  PWR_SCR_CWUF2_Msk                       /*!< Clear Wake-up Pin 2 [Flag 1] */
-#define PWR_SCR_CWUF3_Pos              (2U)
-#define PWR_SCR_CWUF3_Msk              (0x1UL << PWR_SCR_CWUF3_Pos)            /*!< 0x00000004 */
-#define PWR_SCR_CWUF3                  PWR_SCR_CWUF3_Msk                       /*!< Clear Wake-up Pin 3 [Flag 2] */
-
-#define PWR_SCR_CWPVDF_Pos             (8U)
-#define PWR_SCR_CWPVDF_Msk             (0x1UL << PWR_SCR_CWPVDF_Pos)           /*!< 0x00000100 */
-#define PWR_SCR_CWPVDF                 PWR_SCR_CWPVDF_Msk                      /*!< Clear wakeup PVD interrupt flag */
-
-#define PWR_SCR_CWRFBUSYF_Pos          (11U)
-#define PWR_SCR_CWRFBUSYF_Msk          (0x1UL << PWR_SCR_CWRFBUSYF_Pos)        /*!< 0x00000800 */
-#define PWR_SCR_CWRFBUSYF              PWR_SCR_CWRFBUSYF_Msk                   /*!< Clear Radio busy interrupt flag */
-
-#define PWR_SCR_CC2HF_Pos              (14U)
-#define PWR_SCR_CC2HF_Msk              (0x1UL << PWR_SCR_CC2HF_Pos)            /*!< 0x00004000 */
-#define PWR_SCR_CC2HF                  PWR_SCR_CC2HF_Msk                       /*!< Clear CPU2 Hold interrupt flag */
-
-/********************  Bit definition for PWR_CR5 register  ********************/
-#define PWR_CR5_RFEOLEN_Pos            (14U)
-#define PWR_CR5_RFEOLEN_Msk            (0x1UL << PWR_CR5_RFEOLEN_Pos)           /*!< 0x00004000 */
-#define PWR_CR5_RFEOLEN                PWR_CR5_RFEOLEN_Msk                      /*!< Enable Radio End Of Life detector enabled */
-
-#define PWR_CR5_SMPSEN_Pos             (15U)
-#define PWR_CR5_SMPSEN_Msk             (0x1UL << PWR_CR5_SMPSEN_Pos)           /*!< 0x00008000 */
-#define PWR_CR5_SMPSEN                 PWR_CR5_SMPSEN_Msk                      /*!< Enable SMPS Step Down converter SMPS mode enable */
-
-/********************  Bit definition for PWR_PUCRA register  *****************/
-#define PWR_PUCRA_PA0_Pos              (0U)
-#define PWR_PUCRA_PA0_Msk              (0x1UL << PWR_PUCRA_PA0_Pos)            /*!< 0x00000001 */
-#define PWR_PUCRA_PA0                  PWR_PUCRA_PA0_Msk                       /*!< Pin PA0 Pull-Up set */
-#define PWR_PUCRA_PA1_Pos              (1U)
-#define PWR_PUCRA_PA1_Msk              (0x1UL << PWR_PUCRA_PA1_Pos)            /*!< 0x00000002 */
-#define PWR_PUCRA_PA1                  PWR_PUCRA_PA1_Msk                       /*!< Pin PA1 Pull-Up set */
-#define PWR_PUCRA_PA2_Pos              (2U)
-#define PWR_PUCRA_PA2_Msk              (0x1UL << PWR_PUCRA_PA2_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRA_PA2                  PWR_PUCRA_PA2_Msk                       /*!< Pin PA2 Pull-Up set */
-#define PWR_PUCRA_PA3_Pos              (3U)
-#define PWR_PUCRA_PA3_Msk              (0x1UL << PWR_PUCRA_PA3_Pos)            /*!< 0x00000008 */
-#define PWR_PUCRA_PA3                  PWR_PUCRA_PA3_Msk                       /*!< Pin PA3 Pull-Up set */
-#define PWR_PUCRA_PA4_Pos              (4U)
-#define PWR_PUCRA_PA4_Msk              (0x1UL << PWR_PUCRA_PA4_Pos)            /*!< 0x00000010 */
-#define PWR_PUCRA_PA4                  PWR_PUCRA_PA4_Msk                       /*!< Pin PA4 Pull-Up set */
-#define PWR_PUCRA_PA5_Pos              (5U)
-#define PWR_PUCRA_PA5_Msk              (0x1UL << PWR_PUCRA_PA5_Pos)            /*!< 0x00000020 */
-#define PWR_PUCRA_PA5                  PWR_PUCRA_PA5_Msk                       /*!< Pin PA5 Pull-Up set */
-#define PWR_PUCRA_PA6_Pos              (6U)
-#define PWR_PUCRA_PA6_Msk              (0x1UL << PWR_PUCRA_PA6_Pos)            /*!< 0x00000040 */
-#define PWR_PUCRA_PA6                  PWR_PUCRA_PA6_Msk                       /*!< Pin PA6 Pull-Up set */
-#define PWR_PUCRA_PA7_Pos              (7U)
-#define PWR_PUCRA_PA7_Msk              (0x1UL << PWR_PUCRA_PA7_Pos)            /*!< 0x00000080 */
-#define PWR_PUCRA_PA7                  PWR_PUCRA_PA7_Msk                       /*!< Pin PA7 Pull-Up set */
-#define PWR_PUCRA_PA8_Pos              (8U)
-#define PWR_PUCRA_PA8_Msk              (0x1UL << PWR_PUCRA_PA8_Pos)            /*!< 0x00000100 */
-#define PWR_PUCRA_PA8                  PWR_PUCRA_PA8_Msk                       /*!< Pin PA8 Pull-Up set */
-#define PWR_PUCRA_PA9_Pos              (9U)
-#define PWR_PUCRA_PA9_Msk              (0x1UL << PWR_PUCRA_PA9_Pos)            /*!< 0x00000200 */
-#define PWR_PUCRA_PA9                  PWR_PUCRA_PA9_Msk                       /*!< Pin PA9 Pull-Up set */
-#define PWR_PUCRA_PA10_Pos             (10U)
-#define PWR_PUCRA_PA10_Msk             (0x1UL << PWR_PUCRA_PA10_Pos)           /*!< 0x00000400 */
-#define PWR_PUCRA_PA10                 PWR_PUCRA_PA10_Msk                      /*!< Pin PA10 Pull-Up set */
-#define PWR_PUCRA_PA11_Pos             (11U)
-#define PWR_PUCRA_PA11_Msk             (0x1UL << PWR_PUCRA_PA11_Pos)           /*!< 0x00000800 */
-#define PWR_PUCRA_PA11                 PWR_PUCRA_PA11_Msk                      /*!< Pin PA11 Pull-Up set */
-#define PWR_PUCRA_PA12_Pos             (12U)
-#define PWR_PUCRA_PA12_Msk             (0x1UL << PWR_PUCRA_PA12_Pos)           /*!< 0x00001000 */
-#define PWR_PUCRA_PA12                 PWR_PUCRA_PA12_Msk                      /*!< Pin PA12 Pull-Up set */
-#define PWR_PUCRA_PA13_Pos             (13U)
-#define PWR_PUCRA_PA13_Msk             (0x1UL << PWR_PUCRA_PA13_Pos)           /*!< 0x00002000 */
-#define PWR_PUCRA_PA13                 PWR_PUCRA_PA13_Msk                      /*!< Pin PA13 Pull-Up set */
-#define PWR_PUCRA_PA14_Pos             (14U)
-#define PWR_PUCRA_PA14_Msk             (0x1UL << PWR_PUCRA_PA14_Pos)           /*!< 0x00004000 */
-#define PWR_PUCRA_PA14                 PWR_PUCRA_PA14_Msk                      /*!< Pin PA14 Pull-Up set */
-#define PWR_PUCRA_PA15_Pos             (15U)
-#define PWR_PUCRA_PA15_Msk             (0x1UL << PWR_PUCRA_PA15_Pos)           /*!< 0x00008000 */
-#define PWR_PUCRA_PA15                 PWR_PUCRA_PA15_Msk                      /*!< Pin PA15 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRA register  *****************/
-#define PWR_PDCRA_PA0_Pos              (0U)
-#define PWR_PDCRA_PA0_Msk              (0x1UL << PWR_PDCRA_PA0_Pos)            /*!< 0x00000001 */
-#define PWR_PDCRA_PA0                  PWR_PDCRA_PA0_Msk                       /*!< Pin PA0 Pull-Down set */
-#define PWR_PDCRA_PA1_Pos              (1U)
-#define PWR_PDCRA_PA1_Msk              (0x1UL << PWR_PDCRA_PA1_Pos)            /*!< 0x00000002 */
-#define PWR_PDCRA_PA1                  PWR_PDCRA_PA1_Msk                       /*!< Pin PA1 Pull-Down set */
-#define PWR_PDCRA_PA2_Pos              (2U)
-#define PWR_PDCRA_PA2_Msk              (0x1UL << PWR_PDCRA_PA2_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRA_PA2                  PWR_PDCRA_PA2_Msk                       /*!< Pin PA2 Pull-Down set */
-#define PWR_PDCRA_PA3_Pos              (3U)
-#define PWR_PDCRA_PA3_Msk              (0x1UL << PWR_PDCRA_PA3_Pos)            /*!< 0x00000008 */
-#define PWR_PDCRA_PA3                  PWR_PDCRA_PA3_Msk                       /*!< Pin PA3 Pull-Down set */
-#define PWR_PDCRA_PA4_Pos              (4U)
-#define PWR_PDCRA_PA4_Msk              (0x1UL << PWR_PDCRA_PA4_Pos)            /*!< 0x00000010 */
-#define PWR_PDCRA_PA4                  PWR_PDCRA_PA4_Msk                       /*!< Pin PA4 Pull-Down set */
-#define PWR_PDCRA_PA5_Pos              (5U)
-#define PWR_PDCRA_PA5_Msk              (0x1UL << PWR_PDCRA_PA5_Pos)            /*!< 0x00000020 */
-#define PWR_PDCRA_PA5                  PWR_PDCRA_PA5_Msk                       /*!< Pin PA5 Pull-Down set */
-#define PWR_PDCRA_PA6_Pos              (6U)
-#define PWR_PDCRA_PA6_Msk              (0x1UL << PWR_PDCRA_PA6_Pos)            /*!< 0x00000040 */
-#define PWR_PDCRA_PA6                  PWR_PDCRA_PA6_Msk                       /*!< Pin PA6 Pull-Down set */
-#define PWR_PDCRA_PA7_Pos              (7U)
-#define PWR_PDCRA_PA7_Msk              (0x1UL << PWR_PDCRA_PA7_Pos)            /*!< 0x00000080 */
-#define PWR_PDCRA_PA7                  PWR_PDCRA_PA7_Msk                       /*!< Pin PA7 Pull-Down set */
-#define PWR_PDCRA_PA8_Pos              (8U)
-#define PWR_PDCRA_PA8_Msk              (0x1UL << PWR_PDCRA_PA8_Pos)            /*!< 0x00000100 */
-#define PWR_PDCRA_PA8                  PWR_PDCRA_PA8_Msk                       /*!< Pin PA8 Pull-Down set */
-#define PWR_PDCRA_PA9_Pos              (9U)
-#define PWR_PDCRA_PA9_Msk              (0x1UL << PWR_PDCRA_PA9_Pos)            /*!< 0x00000200 */
-#define PWR_PDCRA_PA9                  PWR_PDCRA_PA9_Msk                       /*!< Pin PA9 Pull-Down set */
-#define PWR_PDCRA_PA10_Pos             (10U)
-#define PWR_PDCRA_PA10_Msk             (0x1UL << PWR_PDCRA_PA10_Pos)           /*!< 0x00000400 */
-#define PWR_PDCRA_PA10                 PWR_PDCRA_PA10_Msk                      /*!< Pin PA10 Pull-Down set */
-#define PWR_PDCRA_PA11_Pos             (11U)
-#define PWR_PDCRA_PA11_Msk             (0x1UL << PWR_PDCRA_PA11_Pos)           /*!< 0x00000800 */
-#define PWR_PDCRA_PA11                 PWR_PDCRA_PA11_Msk                      /*!< Pin PA11 Pull-Down set */
-#define PWR_PDCRA_PA12_Pos             (12U)
-#define PWR_PDCRA_PA12_Msk             (0x1UL << PWR_PDCRA_PA12_Pos)           /*!< 0x00001000 */
-#define PWR_PDCRA_PA12                 PWR_PDCRA_PA12_Msk                      /*!< Pin PA12 Pull-Down set */
-#define PWR_PDCRA_PA13_Pos             (13U)
-#define PWR_PDCRA_PA13_Msk             (0x1UL << PWR_PDCRA_PA13_Pos)           /*!< 0x00002000 */
-#define PWR_PDCRA_PA13                 PWR_PDCRA_PA13_Msk                      /*!< Pin PA13 Pull-Down set */
-#define PWR_PDCRA_PA14_Pos             (14U)
-#define PWR_PDCRA_PA14_Msk             (0x1UL << PWR_PDCRA_PA14_Pos)           /*!< 0x00004000 */
-#define PWR_PDCRA_PA14                 PWR_PDCRA_PA14_Msk                      /*!< Pin PA14 Pull-Down set */
-#define PWR_PDCRA_PA15_Pos             (15U)
-#define PWR_PDCRA_PA15_Msk             (0x1UL << PWR_PDCRA_PA15_Pos)           /*!< 0x00008000 */
-#define PWR_PDCRA_PA15                 PWR_PDCRA_PA15_Msk                      /*!< Pin PA15 Pull-Down set */
-
-/********************  Bit definition for PWR_PUCRB register  *****************/
-#define PWR_PUCRB_PB0_Pos              (0U)
-#define PWR_PUCRB_PB0_Msk              (0x1UL << PWR_PUCRB_PB0_Pos)            /*!< 0x00000001 */
-#define PWR_PUCRB_PB0                  PWR_PUCRB_PB0_Msk                       /*!< Pin PB0 Pull-Up set */
-#define PWR_PUCRB_PB1_Pos              (1U)
-#define PWR_PUCRB_PB1_Msk              (0x1UL << PWR_PUCRB_PB1_Pos)            /*!< 0x00000002 */
-#define PWR_PUCRB_PB1                  PWR_PUCRB_PB1_Msk                       /*!< Pin PB1 Pull-Up set */
-#define PWR_PUCRB_PB2_Pos              (2U)
-#define PWR_PUCRB_PB2_Msk              (0x1UL << PWR_PUCRB_PB2_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRB_PB2                  PWR_PUCRB_PB2_Msk                       /*!< Pin PB2 Pull-Up set */
-#define PWR_PUCRB_PB3_Pos              (3U)
-#define PWR_PUCRB_PB3_Msk              (0x1UL << PWR_PUCRB_PB3_Pos)            /*!< 0x00000008 */
-#define PWR_PUCRB_PB3                  PWR_PUCRB_PB3_Msk                       /*!< Pin PB3 Pull-Up set */
-#define PWR_PUCRB_PB4_Pos              (4U)
-#define PWR_PUCRB_PB4_Msk              (0x1UL << PWR_PUCRB_PB4_Pos)            /*!< 0x00000010 */
-#define PWR_PUCRB_PB4                  PWR_PUCRB_PB4_Msk                       /*!< Pin PB4 Pull-Up set */
-#define PWR_PUCRB_PB5_Pos              (5U)
-#define PWR_PUCRB_PB5_Msk              (0x1UL << PWR_PUCRB_PB5_Pos)            /*!< 0x00000020 */
-#define PWR_PUCRB_PB5                  PWR_PUCRB_PB5_Msk                       /*!< Pin PB5 Pull-Up set */
-#define PWR_PUCRB_PB6_Pos              (6U)
-#define PWR_PUCRB_PB6_Msk              (0x1UL << PWR_PUCRB_PB6_Pos)            /*!< 0x00000040 */
-#define PWR_PUCRB_PB6                  PWR_PUCRB_PB6_Msk                       /*!< Pin PB6 Pull-Up set */
-#define PWR_PUCRB_PB7_Pos              (7U)
-#define PWR_PUCRB_PB7_Msk              (0x1UL << PWR_PUCRB_PB7_Pos)            /*!< 0x00000080 */
-#define PWR_PUCRB_PB7                  PWR_PUCRB_PB7_Msk                       /*!< Pin PB7 Pull-Up set */
-#define PWR_PUCRB_PB8_Pos              (8U)
-#define PWR_PUCRB_PB8_Msk              (0x1UL << PWR_PUCRB_PB8_Pos)            /*!< 0x00000100 */
-#define PWR_PUCRB_PB8                  PWR_PUCRB_PB8_Msk                       /*!< Pin PB8 Pull-Up set */
-#define PWR_PUCRB_PB9_Pos              (9U)
-#define PWR_PUCRB_PB9_Msk              (0x1UL << PWR_PUCRB_PB9_Pos)            /*!< 0x00000200 */
-#define PWR_PUCRB_PB9                  PWR_PUCRB_PB9_Msk                       /*!< Pin PB9 Pull-Up set */
-#define PWR_PUCRB_PB10_Pos             (10U)
-#define PWR_PUCRB_PB10_Msk             (0x1UL << PWR_PUCRB_PB10_Pos)           /*!< 0x00000400 */
-#define PWR_PUCRB_PB10                 PWR_PUCRB_PB10_Msk                      /*!< Pin PB10 Pull-Up set */
-#define PWR_PUCRB_PB11_Pos             (11U)
-#define PWR_PUCRB_PB11_Msk             (0x1UL << PWR_PUCRB_PB11_Pos)           /*!< 0x00000800 */
-#define PWR_PUCRB_PB11                 PWR_PUCRB_PB11_Msk                      /*!< Pin PB11 Pull-Up set */
-#define PWR_PUCRB_PB12_Pos             (12U)
-#define PWR_PUCRB_PB12_Msk             (0x1UL << PWR_PUCRB_PB12_Pos)           /*!< 0x00001000 */
-#define PWR_PUCRB_PB12                 PWR_PUCRB_PB12_Msk                      /*!< Pin PB12 Pull-Up set */
-#define PWR_PUCRB_PB13_Pos             (13U)
-#define PWR_PUCRB_PB13_Msk             (0x1UL << PWR_PUCRB_PB13_Pos)           /*!< 0x00002000 */
-#define PWR_PUCRB_PB13                 PWR_PUCRB_PB13_Msk                      /*!< Pin PB13 Pull-Up set */
-#define PWR_PUCRB_PB14_Pos             (14U)
-#define PWR_PUCRB_PB14_Msk             (0x1UL << PWR_PUCRB_PB14_Pos)           /*!< 0x00004000 */
-#define PWR_PUCRB_PB14                 PWR_PUCRB_PB14_Msk                      /*!< Pin PB14 Pull-Up set */
-#define PWR_PUCRB_PB15_Pos             (15U)
-#define PWR_PUCRB_PB15_Msk             (0x1UL << PWR_PUCRB_PB15_Pos)           /*!< 0x00008000 */
-#define PWR_PUCRB_PB15                 PWR_PUCRB_PB15_Msk                      /*!< Pin PB15 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRB register  *****************/
-#define PWR_PDCRB_PB0_Pos              (0U)
-#define PWR_PDCRB_PB0_Msk              (0x1UL << PWR_PDCRB_PB0_Pos)            /*!< 0x00000001 */
-#define PWR_PDCRB_PB0                  PWR_PDCRB_PB0_Msk                       /*!< Pin PB0 Pull-Down set */
-#define PWR_PDCRB_PB1_Pos              (1U)
-#define PWR_PDCRB_PB1_Msk              (0x1UL << PWR_PDCRB_PB1_Pos)            /*!< 0x00000002 */
-#define PWR_PDCRB_PB1                  PWR_PDCRB_PB1_Msk                       /*!< Pin PB1 Pull-Down set */
-#define PWR_PDCRB_PB2_Pos              (2U)
-#define PWR_PDCRB_PB2_Msk              (0x1UL << PWR_PDCRB_PB2_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRB_PB2                  PWR_PDCRB_PB2_Msk                       /*!< Pin PB2 Pull-Down set */
-#define PWR_PDCRB_PB3_Pos              (3U)
-#define PWR_PDCRB_PB3_Msk              (0x1UL << PWR_PDCRB_PB3_Pos)            /*!< 0x00000008 */
-#define PWR_PDCRB_PB3                  PWR_PDCRB_PB3_Msk                       /*!< Pin PB3 Pull-Down set */
-#define PWR_PDCRB_PB4_Pos              (4U)
-#define PWR_PDCRB_PB4_Msk              (0x1UL << PWR_PDCRB_PB4_Pos)            /*!< 0x00000010 */
-#define PWR_PDCRB_PB4                  PWR_PDCRB_PB4_Msk                       /*!< Pin PB4 Pull-Down set */
-#define PWR_PDCRB_PB5_Pos              (5U)
-#define PWR_PDCRB_PB5_Msk              (0x1UL << PWR_PDCRB_PB5_Pos)            /*!< 0x00000020 */
-#define PWR_PDCRB_PB5                  PWR_PDCRB_PB5_Msk                       /*!< Pin PB5 Pull-Down set */
-#define PWR_PDCRB_PB6_Pos              (6U)
-#define PWR_PDCRB_PB6_Msk              (0x1UL << PWR_PDCRB_PB6_Pos)            /*!< 0x00000040 */
-#define PWR_PDCRB_PB6                  PWR_PDCRB_PB6_Msk                       /*!< Pin PB6 Pull-Down set */
-#define PWR_PDCRB_PB7_Pos              (7U)
-#define PWR_PDCRB_PB7_Msk              (0x1UL << PWR_PDCRB_PB7_Pos)            /*!< 0x00000080 */
-#define PWR_PDCRB_PB7                  PWR_PDCRB_PB7_Msk                       /*!< Pin PB7 Pull-Down set */
-#define PWR_PDCRB_PB8_Pos              (8U)
-#define PWR_PDCRB_PB8_Msk              (0x1UL << PWR_PDCRB_PB8_Pos)            /*!< 0x00000100 */
-#define PWR_PDCRB_PB8                  PWR_PDCRB_PB8_Msk                       /*!< Pin PB8 Pull-Down set */
-#define PWR_PDCRB_PB9_Pos              (9U)
-#define PWR_PDCRB_PB9_Msk              (0x1UL << PWR_PDCRB_PB9_Pos)            /*!< 0x00000200 */
-#define PWR_PDCRB_PB9                  PWR_PDCRB_PB9_Msk                       /*!< Pin PB9 Pull-Down set */
-#define PWR_PDCRB_PB10_Pos             (10U)
-#define PWR_PDCRB_PB10_Msk             (0x1UL << PWR_PDCRB_PB10_Pos)           /*!< 0x00000400 */
-#define PWR_PDCRB_PB10                 PWR_PDCRB_PB10_Msk                      /*!< Pin PB10 Pull-Down set */
-#define PWR_PDCRB_PB11_Pos             (11U)
-#define PWR_PDCRB_PB11_Msk             (0x1UL << PWR_PDCRB_PB11_Pos)           /*!< 0x00000800 */
-#define PWR_PDCRB_PB11                 PWR_PDCRB_PB11_Msk                      /*!< Pin PB11 Pull-Down set */
-#define PWR_PDCRB_PB12_Pos             (12U)
-#define PWR_PDCRB_PB12_Msk             (0x1UL << PWR_PDCRB_PB12_Pos)           /*!< 0x00001000 */
-#define PWR_PDCRB_PB12                 PWR_PDCRB_PB12_Msk                      /*!< Pin PB12 Pull-Down set */
-#define PWR_PDCRB_PB13_Pos             (13U)
-#define PWR_PDCRB_PB13_Msk             (0x1UL << PWR_PDCRB_PB13_Pos)           /*!< 0x00002000 */
-#define PWR_PDCRB_PB13                 PWR_PDCRB_PB13_Msk                      /*!< Pin PB13 Pull-Down set */
-#define PWR_PDCRB_PB14_Pos             (14U)
-#define PWR_PDCRB_PB14_Msk             (0x1UL << PWR_PDCRB_PB14_Pos)           /*!< 0x00004000 */
-#define PWR_PDCRB_PB14                 PWR_PDCRB_PB14_Msk                      /*!< Pin PB14 Pull-Down set */
-#define PWR_PDCRB_PB15_Pos             (15U)
-#define PWR_PDCRB_PB15_Msk             (0x1UL << PWR_PDCRB_PB15_Pos)           /*!< 0x00008000 */
-#define PWR_PDCRB_PB15                 PWR_PDCRB_PB15_Msk                      /*!< Pin PB15 Pull-Down set */
-
-/********************  Bit definition for PWR_PUCRC register  *****************/
-#define PWR_PUCRC_PC0_Pos              (0U)
-#define PWR_PUCRC_PC0_Msk              (0x1UL << PWR_PUCRC_PC0_Pos)            /*!< 0x00000001 */
-#define PWR_PUCRC_PC0                  PWR_PUCRC_PC0_Msk                       /*!< Pin PC0 Pull-Up set */
-#define PWR_PUCRC_PC1_Pos              (1U)
-#define PWR_PUCRC_PC1_Msk              (0x1UL << PWR_PUCRC_PC1_Pos)            /*!< 0x00000002 */
-#define PWR_PUCRC_PC1                  PWR_PUCRC_PC1_Msk                       /*!< Pin PC1 Pull-Up set */
-#define PWR_PUCRC_PC2_Pos              (2U)
-#define PWR_PUCRC_PC2_Msk              (0x1UL << PWR_PUCRC_PC2_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRC_PC2                  PWR_PUCRC_PC2_Msk                       /*!< Pin PC2 Pull-Up set */
-#define PWR_PUCRC_PC3_Pos              (3U)
-#define PWR_PUCRC_PC3_Msk              (0x1UL << PWR_PUCRC_PC3_Pos)            /*!< 0x00000008 */
-#define PWR_PUCRC_PC3                  PWR_PUCRC_PC3_Msk                       /*!< Pin PC3 Pull-Up set */
-#define PWR_PUCRC_PC4_Pos              (4U)
-#define PWR_PUCRC_PC4_Msk              (0x1UL << PWR_PUCRC_PC4_Pos)            /*!< 0x00000010 */
-#define PWR_PUCRC_PC4                  PWR_PUCRC_PC4_Msk                       /*!< Pin PC4 Pull-Up set */
-#define PWR_PUCRC_PC5_Pos              (5U)
-#define PWR_PUCRC_PC5_Msk              (0x1UL << PWR_PUCRC_PC5_Pos)            /*!< 0x00000020 */
-#define PWR_PUCRC_PC5                  PWR_PUCRC_PC5_Msk                       /*!< Pin PC5 Pull-Up set */
-#define PWR_PUCRC_PC6_Pos              (6U)
-#define PWR_PUCRC_PC6_Msk              (0x1UL << PWR_PUCRC_PC6_Pos)            /*!< 0x00000040 */
-#define PWR_PUCRC_PC6                  PWR_PUCRC_PC6_Msk                       /*!< Pin PC6 Pull-Up set */
-#define PWR_PUCRC_PC13_Pos             (13U)
-#define PWR_PUCRC_PC13_Msk             (0x1UL << PWR_PUCRC_PC13_Pos)           /*!< 0x00002000 */
-#define PWR_PUCRC_PC13                 PWR_PUCRC_PC13_Msk                      /*!< Pin PC13 Pull-Up set */
-#define PWR_PUCRC_PC14_Pos             (14U)
-#define PWR_PUCRC_PC14_Msk             (0x1UL << PWR_PUCRC_PC14_Pos)           /*!< 0x00004000 */
-#define PWR_PUCRC_PC14                 PWR_PUCRC_PC14_Msk                      /*!< Pin PC14 Pull-Up set */
-#define PWR_PUCRC_PC15_Pos             (15U)
-#define PWR_PUCRC_PC15_Msk             (0x1UL << PWR_PUCRC_PC15_Pos)           /*!< 0x00008000 */
-#define PWR_PUCRC_PC15                 PWR_PUCRC_PC15_Msk                      /*!< Pin PC15 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRC register  *****************/
-#define PWR_PDCRC_PC0_Pos              (0U)
-#define PWR_PDCRC_PC0_Msk              (0x1UL << PWR_PDCRC_PC0_Pos)            /*!< 0x00000001 */
-#define PWR_PDCRC_PC0                  PWR_PDCRC_PC0_Msk                       /*!< Pin PC0 Pull-Down set */
-#define PWR_PDCRC_PC1_Pos              (1U)
-#define PWR_PDCRC_PC1_Msk              (0x1UL << PWR_PDCRC_PC1_Pos)            /*!< 0x00000002 */
-#define PWR_PDCRC_PC1                  PWR_PDCRC_PC1_Msk                       /*!< Pin PC1 Pull-Down set */
-#define PWR_PDCRC_PC2_Pos              (2U)
-#define PWR_PDCRC_PC2_Msk              (0x1UL << PWR_PDCRC_PC2_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRC_PC2                  PWR_PDCRC_PC2_Msk                       /*!< Pin PC2 Pull-Down set */
-#define PWR_PDCRC_PC3_Pos              (3U)
-#define PWR_PDCRC_PC3_Msk              (0x1UL << PWR_PDCRC_PC3_Pos)            /*!< 0x00000008 */
-#define PWR_PDCRC_PC3                  PWR_PDCRC_PC3_Msk                       /*!< Pin PC3 Pull-Down set */
-#define PWR_PDCRC_PC4_Pos              (4U)
-#define PWR_PDCRC_PC4_Msk              (0x1UL << PWR_PDCRC_PC4_Pos)            /*!< 0x00000010 */
-#define PWR_PDCRC_PC4                  PWR_PDCRC_PC4_Msk                       /*!< Pin PC4 Pull-Down set */
-#define PWR_PDCRC_PC5_Pos              (5U)
-#define PWR_PDCRC_PC5_Msk              (0x1UL << PWR_PDCRC_PC5_Pos)            /*!< 0x00000020 */
-#define PWR_PDCRC_PC5                  PWR_PDCRC_PC5_Msk                       /*!< Pin PC5 Pull-Down set */
-#define PWR_PDCRC_PC6_Pos              (6U)
-#define PWR_PDCRC_PC6_Msk              (0x1UL << PWR_PDCRC_PC6_Pos)            /*!< 0x00000040 */
-#define PWR_PDCRC_PC6                  PWR_PDCRC_PC6_Msk                       /*!< Pin PC6 Pull-Down set */
-#define PWR_PDCRC_PC13_Pos             (13U)
-#define PWR_PDCRC_PC13_Msk             (0x1UL << PWR_PDCRC_PC13_Pos)           /*!< 0x00002000 */
-#define PWR_PDCRC_PC13                 PWR_PDCRC_PC13_Msk                      /*!< Pin PC13 Pull-Down set */
-#define PWR_PDCRC_PC14_Pos             (14U)
-#define PWR_PDCRC_PC14_Msk             (0x1UL << PWR_PDCRC_PC14_Pos)           /*!< 0x00004000 */
-#define PWR_PDCRC_PC14                 PWR_PDCRC_PC14_Msk                      /*!< Pin PC14 Pull-Down set */
-#define PWR_PDCRC_PC15_Pos             (15U)
-#define PWR_PDCRC_PC15_Msk             (0x1UL << PWR_PDCRC_PC15_Pos)           /*!< 0x00008000 */
-#define PWR_PDCRC_PC15                 PWR_PDCRC_PC15_Msk                      /*!< Pin PC15 Pull-Down set */
-
-/********************  Bit definition for PWR_PUCRH register  *****************/
-#define PWR_PUCRH_PH3_Pos              (3U)
-#define PWR_PUCRH_PH3_Msk              (0x1UL << PWR_PUCRH_PH3_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRH_PH3                  PWR_PUCRH_PH3_Msk                       /*!< Pin PH3 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRH register  *****************/
-#define PWR_PDCRH_PH3_Pos              (3U)
-#define PWR_PDCRH_PH3_Msk              (0x1UL << PWR_PDCRH_PH3_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRH_PH3                  PWR_PDCRH_PH3_Msk                       /*!< Pin PH3 Pull-Down set */
-
-/********************  Bit definition for PWR_C2CR1 register  ********************/
-#define PWR_C2CR1_LPMS_Pos             (0U)
-#define PWR_C2CR1_LPMS_Msk             (0x7UL << PWR_C2CR1_LPMS_Pos)           /*!< 0x00000007 */
-#define PWR_C2CR1_LPMS                 PWR_C2CR1_LPMS_Msk                      /*!< Low Power Mode Selection for CPU2 */
-#define PWR_C2CR1_LPMS_0               (0x1UL << PWR_C2CR1_LPMS_Pos)           /*!< 0x00000001 */
-#define PWR_C2CR1_LPMS_1               (0x2UL << PWR_C2CR1_LPMS_Pos)           /*!< 0x00000002 */
-#define PWR_C2CR1_LPMS_2               (0x4UL << PWR_C2CR1_LPMS_Pos)           /*!< 0x00000004 */
-
-#define PWR_C2CR1_FPDR_Pos             (4U)
-#define PWR_C2CR1_FPDR_Msk             (0x1UL << PWR_C2CR1_FPDR_Pos)           /*!< 0x00000010 */
-#define PWR_C2CR1_FPDR                 PWR_C2CR1_FPDR_Msk                      /*!< Flash power down mode during LPrun for CPU2 */
-
-#define PWR_C2CR1_FPDS_Pos             (5U)
-#define PWR_C2CR1_FPDS_Msk             (0x1UL << PWR_C2CR1_FPDS_Pos)           /*!< 0x00000020 */
-#define PWR_C2CR1_FPDS                 PWR_C2CR1_FPDS_Msk                      /*!< Flash power down mode during LPsleep for CPU2 */
-
-/********************  Bit definition for PWR_C2CR3 register  ********************/
-#define PWR_C2CR3_EWUP_Pos             (0U)
-#define PWR_C2CR3_EWUP_Msk             (0x07UL << PWR_C2CR3_EWUP_Pos)           /*!< 0x00000007 */
-#define PWR_C2CR3_EWUP                 PWR_C2CR3_EWUP_Msk                       /*!< Enable all external Wake-Up lines for CPU2 */
-#define PWR_C2CR3_EWUP1_Pos            (0U)
-#define PWR_C2CR3_EWUP1_Msk            (0x1UL << PWR_C2CR3_EWUP1_Pos)           /*!< 0x00000001 */
-#define PWR_C2CR3_EWUP1                PWR_C2CR3_EWUP1_Msk                      /*!< Enable external WKUP Pin 1 [line 0] for CPU2 */
-#define PWR_C2CR3_EWUP2_Pos            (1U)
-#define PWR_C2CR3_EWUP2_Msk            (0x1UL << PWR_C2CR3_EWUP2_Pos)           /*!< 0x00000002 */
-#define PWR_C2CR3_EWUP2                PWR_C2CR3_EWUP2_Msk                      /*!< Enable external WKUP Pin 2 [line 1] for CPU2 */
-#define PWR_C2CR3_EWUP3_Pos            (2U)
-#define PWR_C2CR3_EWUP3_Msk            (0x1UL << PWR_C2CR3_EWUP3_Pos)           /*!< 0x00000004 */
-#define PWR_C2CR3_EWUP3                PWR_C2CR3_EWUP3_Msk                      /*!< Enable external WKUP Pin 3 [line 2] for CPU2 */
-
-#define PWR_C2CR3_EWPVD_Pos            (8U)
-#define PWR_C2CR3_EWPVD_Msk            (0x1UL << PWR_C2CR3_EWPVD_Pos)         /*!< 0x00000100 */
-#define PWR_C2CR3_EWPVD                PWR_C2CR3_EWPVD_Msk                    /*!< Enable wakeup PVD for CPU2 */
-
-#define PWR_C2CR3_APC_Pos              (10U)
-#define PWR_C2CR3_APC_Msk              (0x1UL << PWR_C2CR3_APC_Pos)            /*!< 0x00000400 */
-#define PWR_C2CR3_APC                  PWR_C2CR3_APC_Msk                       /*!< Apply pull-up and pull-down configuration for CPU2 */
-
-#define PWR_C2CR3_EWRFBUSY_Pos         (11U)
-#define PWR_C2CR3_EWRFBUSY_Msk         (0x1UL << PWR_C2CR3_EWRFBUSY_Pos)       /*!< 0x00000800 */
-#define PWR_C2CR3_EWRFBUSY             PWR_C2CR3_EWRFBUSY_Msk                  /*!< Enable Radio busy IRQ and wake-up for CPU2 */
-#define PWR_C2CR3_EWRFIRQ_Pos          (13U)
-#define PWR_C2CR3_EWRFIRQ_Msk          (0x1UL << PWR_C2CR3_EWRFIRQ_Pos)        /*!< 0x00002000 */
-#define PWR_C2CR3_EWRFIRQ              PWR_C2CR3_EWRFIRQ_Msk                   /*!< Enable Radio IRQ[2:0] and wake-up for CPU2 */
-
-#define PWR_C2CR3_EIWUL_Pos            (15U)
-#define PWR_C2CR3_EIWUL_Msk            (0x1UL << PWR_C2CR3_EIWUL_Pos)          /*!< 0x00008000 */
-#define PWR_C2CR3_EIWUL                PWR_C2CR3_EIWUL_Msk                     /*!< Internal Wake-Up line interrupt for CPU2 */
-
-/********************  Bit definition for PWR_EXTSCR register  ********************/
-#define PWR_EXTSCR_C1CSSF_Pos          (0U)
-#define PWR_EXTSCR_C1CSSF_Msk          (0x1UL << PWR_EXTSCR_C1CSSF_Pos)        /*!< 0x00000001 */
-#define PWR_EXTSCR_C1CSSF              PWR_EXTSCR_C1CSSF_Msk                   /*!< Clear standby and stop flags for CPU1 */
-#define PWR_EXTSCR_C2CSSF_Pos          (1U)
-#define PWR_EXTSCR_C2CSSF_Msk          (0x1UL << PWR_EXTSCR_C2CSSF_Pos)        /*!< 0x00000002 */
-#define PWR_EXTSCR_C2CSSF              PWR_EXTSCR_C2CSSF_Msk                   /*!< Clear standby and stop flags for CPU2 */
-
-#define PWR_EXTSCR_C1SBF_Pos           (8U)
-#define PWR_EXTSCR_C1SBF_Msk           (0x1UL << PWR_EXTSCR_C1SBF_Pos)         /*!< 0x00000100 */
-#define PWR_EXTSCR_C1SBF               PWR_EXTSCR_C1SBF_Msk                    /*!< System standby flag for CPU1 */
-#define PWR_EXTSCR_C1STOP2F_Pos        (9U)
-#define PWR_EXTSCR_C1STOP2F_Msk        (0x1UL << PWR_EXTSCR_C1STOP2F_Pos)      /*!< 0x00000200 */
-#define PWR_EXTSCR_C1STOP2F            PWR_EXTSCR_C1STOP2F_Msk                 /*!< System stop2 flag for CPU1 */
-#define PWR_EXTSCR_C1STOPF_Pos         (10U)
-#define PWR_EXTSCR_C1STOPF_Msk         (0x1UL << PWR_EXTSCR_C1STOPF_Pos)       /*!< 0x00000400 */
-#define PWR_EXTSCR_C1STOPF             PWR_EXTSCR_C1STOPF_Msk                  /*!< System stop0 or stop1 flag for CPU1 */
-
-#define PWR_EXTSCR_C2SBF_Pos           (11U)
-#define PWR_EXTSCR_C2SBF_Msk           (0x1UL << PWR_EXTSCR_C2SBF_Pos)         /*!< 0x00000800 */
-#define PWR_EXTSCR_C2SBF               PWR_EXTSCR_C2SBF_Msk                    /*!< System standby flag for CPU2 */
-#define PWR_EXTSCR_C2STOP2F_Pos        (12U)
-#define PWR_EXTSCR_C2STOP2F_Msk        (0x1UL << PWR_EXTSCR_C2STOP2F_Pos)      /*!< 0x00001000 */
-#define PWR_EXTSCR_C2STOP2F            PWR_EXTSCR_C2STOP2F_Msk                 /*!< System stop2 flag for CPU2 */
-#define PWR_EXTSCR_C2STOPF_Pos         (13U)
-#define PWR_EXTSCR_C2STOPF_Msk         (0x1UL << PWR_EXTSCR_C2STOPF_Pos)       /*!< 0x00002000 */
-#define PWR_EXTSCR_C2STOPF             PWR_EXTSCR_C2STOPF_Msk                  /*!< System stop0 or stop1 flag for CPU2 */
-
-#define PWR_EXTSCR_C1DS_Pos            (14U)
-#define PWR_EXTSCR_C1DS_Msk            (0x1UL << PWR_EXTSCR_C1DS_Pos)          /*!< 0x00004000 */
-#define PWR_EXTSCR_C1DS                PWR_EXTSCR_C1DS_Msk                     /*!< CPU1 deepsleep mode flag */
-#define PWR_EXTSCR_C2DS_Pos            (15U)
-#define PWR_EXTSCR_C2DS_Msk            (0x1UL << PWR_EXTSCR_C2DS_Pos)          /*!< 0x00008000 */
-#define PWR_EXTSCR_C2DS                PWR_EXTSCR_C2DS_Msk                     /*!< CPU2 deepsleep mode flag */
-
-/********************  Bit definition for PWR_SECCFGR register  ********************/
-#define PWR_SECCFGR_C2EWILA_Pos        (15U)
-#define PWR_SECCFGR_C2EWILA_Msk        (0x1UL << PWR_SECCFGR_C2EWILA_Pos)      /*!< 0x00008000 */
-#define PWR_SECCFGR_C2EWILA            PWR_SECCFGR_C2EWILA_Msk                 /*!< CPU2 illegal access interrupt enable */
-
-/********************  Bit definition for PWR_SUBGHZSPICR register  ********************/
-#define PWR_SUBGHZSPICR_NSS_Pos         (15U)
-#define PWR_SUBGHZSPICR_NSS_Msk         (0x1UL << PWR_SUBGHZSPICR_NSS_Pos)       /*!< 0x00008000 */
-#define PWR_SUBGHZSPICR_NSS             PWR_SUBGHZSPICR_NSS_Msk                  /*!< Sub-GHz radio SUBGHZSPI_NSS control */
-
-/********************  Bit definition for PWR_RSSCMDR register  ********************/
-#define PWR_RSSCMDR_RSSCMD_Pos         (0U)
-#define PWR_RSSCMDR_RSSCMD_Msk         (0xFFUL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x000000FF */
-#define PWR_RSSCMDR_RSSCMD             PWR_RSSCMDR_RSSCMD_Msk                  /*!< RSS command */
-#define PWR_RSSCMDR_RSSCMD_0           (0x01UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000001 */
-#define PWR_RSSCMDR_RSSCMD_1           (0x02UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000002 */
-#define PWR_RSSCMDR_RSSCMD_2           (0x04UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000004 */
-#define PWR_RSSCMDR_RSSCMD_3           (0x08UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000008 */
-#define PWR_RSSCMDR_RSSCMD_4           (0x10UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000010 */
-#define PWR_RSSCMDR_RSSCMD_5           (0x20UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000020 */
-#define PWR_RSSCMDR_RSSCMD_6           (0x40UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000040 */
-#define PWR_RSSCMDR_RSSCMD_7           (0x80UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000080 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RCC_CR register  *****************/
-#define RCC_CR_MSION_Pos                     (0U)
-#define RCC_CR_MSION_Msk                     (0x1UL << RCC_CR_MSION_Pos)       /*!< 0x00000001 */
-#define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
-#define RCC_CR_MSIRDY_Pos                    (1U)
-#define RCC_CR_MSIRDY_Msk                    (0x1UL << RCC_CR_MSIRDY_Pos)      /*!< 0x00000002 */
-#define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
-#define RCC_CR_MSIPLLEN_Pos                  (2U)
-#define RCC_CR_MSIPLLEN_Msk                  (0x1UL << RCC_CR_MSIPLLEN_Pos)    /*!< 0x00000004 */
-#define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
-#define RCC_CR_MSIRGSEL_Pos                  (3U)
-#define RCC_CR_MSIRGSEL_Msk                  (0x1UL << RCC_CR_MSIRGSEL_Pos)    /*!< 0x00000008 */
-#define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
-
-/*!< MSIRANGE configuration : 12 frequency ranges available */
-#define RCC_CR_MSIRANGE_Pos                  (4U)
-#define RCC_CR_MSIRANGE_Msk                  (0xFUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000F0 */
-#define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
-#define RCC_CR_MSIRANGE_0                    (0x0UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000000 */
-#define RCC_CR_MSIRANGE_1                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */
-#define RCC_CR_MSIRANGE_2                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */
-#define RCC_CR_MSIRANGE_3                    (0x3UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000030 */
-#define RCC_CR_MSIRANGE_4                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */
-#define RCC_CR_MSIRANGE_5                    (0x5UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000050 */
-#define RCC_CR_MSIRANGE_6                    (0x6UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000060 */
-#define RCC_CR_MSIRANGE_7                    (0x7UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000070 */
-#define RCC_CR_MSIRANGE_8                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */
-#define RCC_CR_MSIRANGE_9                    (0x9UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000090 */
-#define RCC_CR_MSIRANGE_10                   (0xAUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000A0 */
-#define RCC_CR_MSIRANGE_11                   (0xBUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000B0 */
-
-#define RCC_CR_HSION_Pos                     (8U)
-#define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
-#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
-#define RCC_CR_HSIKERON_Pos                  (9U)
-#define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
-#define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                    (10U)
-#define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
-#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
-#define RCC_CR_HSIASFS_Pos                   (11U)
-#define RCC_CR_HSIASFS_Msk                   (0x1UL << RCC_CR_HSIASFS_Pos)     /*!< 0x00000800 */
-#define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
-#define RCC_CR_HSIKERDY_Pos                  (12U)
-#define RCC_CR_HSIKERDY_Msk                  (0x1UL << RCC_CR_HSIKERDY_Pos)     /*!< 0x00001000 */
-#define RCC_CR_HSIKERDY                       RCC_CR_HSIKERDY_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel ready flag*/
-
-#define RCC_CR_HSEON_Pos                     (16U)
-#define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
-#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
-#define RCC_CR_HSERDY_Pos                    (17U)
-#define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
-#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
-#define RCC_CR_CSSON_Pos                     (19U)
-#define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
-#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
-#define RCC_CR_HSEPRE_Pos                    (20U)
-#define RCC_CR_HSEPRE_Msk                    (0x1UL << RCC_CR_HSEPRE_Pos)       /*!< 0x00100000 */
-#define RCC_CR_HSEPRE                        RCC_CR_HSEPRE_Msk                  /*!< HSE sysclk prescaler */
-#define RCC_CR_HSEBYPPWR_Pos                 (21U)
-#define RCC_CR_HSEBYPPWR_Msk                 (0x1UL << RCC_CR_HSEBYPPWR_Pos)    /*!< 0x00200000 */
-#define RCC_CR_HSEBYPPWR                     RCC_CR_HSEBYPPWR_Msk               /*!< Enable HSE32 VDDTCXO */
-
-#define RCC_CR_PLLON_Pos                     (24U)
-#define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
-#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
-#define RCC_CR_PLLRDY_Pos                    (25U)
-#define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
-
-/********************  Bit definition for RCC_ICSCR register  ***************/
-/*!< MSICAL configuration */
-#define RCC_ICSCR_MSICAL_Pos                 (0U)
-#define RCC_ICSCR_MSICAL_Msk                 (0xFFUL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x000000FF */
-#define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
-
-/*!< MSITRIM configuration */
-#define RCC_ICSCR_MSITRIM_Pos                (8U)
-#define RCC_ICSCR_MSITRIM_Msk                (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
-#define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
-
-/*!< HSICAL configuration */
-#define RCC_ICSCR_HSICAL_Pos                 (16U)
-#define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
-#define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
-
-/*!< HSITRIM configuration */
-#define RCC_ICSCR_HSITRIM_Pos                (24U)
-#define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
-#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
-
-/*!< STOPWUCK configuration */
-#define RCC_CFGR_STOPWUCK_Pos                (15U)
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)  /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
-
-/*!< HPREF configuration */
-#define RCC_CFGR_HPREF_Pos                   (16U)
-#define RCC_CFGR_HPREF_Msk                   (0x1UL << RCC_CFGR_HPREF_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_HPREF                       RCC_CFGR_HPREF_Msk                /*!< AHB prescaler flag */
-
-/*!< PPRE1F configuration */
-#define RCC_CFGR_PPRE1F_Pos                  (17U)
-#define RCC_CFGR_PPRE1F_Msk                  (0x1UL << RCC_CFGR_PPRE1F_Pos)    /*!< 0x00020000 */
-#define RCC_CFGR_PPRE1F                      RCC_CFGR_PPRE1F_Msk               /*!< CPU1 APB1 prescaler flag */
-
-/*!< PPRE2F configuration */
-#define RCC_CFGR_PPRE2F_Pos                  (18U)
-#define RCC_CFGR_PPRE2F_Msk                  (0x1UL << RCC_CFGR_PPRE2F_Pos)    /*!< 0x00040000 */
-#define RCC_CFGR_PPRE2F                      RCC_CFGR_PPRE2F_Msk               /*!< APB2 prescaler flag */
-
-/*!< MCOSEL configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x08000000 */
-
-/*!< MCOPRE configuration */
-#define RCC_CFGR_MCOPRE_Pos                  (28U)
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define RCC_PLLCFGR_PLLSRC_Pos               (0U)
-#define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000003 */
-#define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
-#define RCC_PLLCFGR_PLLSRC_0                 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000001 */
-#define RCC_PLLCFGR_PLLSRC_1                 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000002 */
-
-#define RCC_PLLCFGR_PLLM_Pos                 (4U)
-#define RCC_PLLCFGR_PLLM_Msk                 (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
-#define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
-#define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
-#define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
-#define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
-
-#define RCC_PLLCFGR_PLLN_Pos                 (8U)
-#define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00007F00 */
-#define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
-#define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000100 */
-#define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000200 */
-#define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000400 */
-#define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000800 */
-#define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00001000 */
-#define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00002000 */
-#define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00004000 */
-
-#define RCC_PLLCFGR_PLLPEN_Pos               (16U)
-#define RCC_PLLCFGR_PLLPEN_Msk               (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)/*!< 0x00010000 */
-#define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk
-#define RCC_PLLCFGR_PLLP_Pos                 (17U)
-#define RCC_PLLCFGR_PLLP_Msk                 (0x1FUL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x003E0000 */
-#define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk
-#define RCC_PLLCFGR_PLLP_0                   (0x01UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00020000 */
-#define RCC_PLLCFGR_PLLP_1                   (0x02UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00040000 */
-#define RCC_PLLCFGR_PLLP_2                   (0x04UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00080000 */
-#define RCC_PLLCFGR_PLLP_3                   (0x08UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00100000 */
-#define RCC_PLLCFGR_PLLP_4                   (0x10UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00200000 */
-
-#define RCC_PLLCFGR_PLLQEN_Pos               (24U)
-#define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)/*!< 0x01000000 */
-#define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
-#define RCC_PLLCFGR_PLLQ_Pos                 (25U)
-#define RCC_PLLCFGR_PLLQ_Msk                 (0x7UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x0E000000 */
-#define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
-#define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x02000000 */
-#define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x04000000 */
-#define RCC_PLLCFGR_PLLQ_2                   (0x4UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x08000000 */
-
-#define RCC_PLLCFGR_PLLREN_Pos               (28U)
-#define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos)/*!< 0x10000000 */
-#define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
-#define RCC_PLLCFGR_PLLR_Pos                 (29U)
-#define RCC_PLLCFGR_PLLR_Msk                 (0x7UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0xE0000000 */
-#define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
-#define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x20000000 */
-#define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x40000000 */
-#define RCC_PLLCFGR_PLLR_2                   (0x4UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x80000000 */
-
-
-/********************  Bit definition for RCC_CIER register  ******************/
-#define RCC_CIER_LSIRDYIE_Pos                (0U)
-#define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk
-#define RCC_CIER_LSERDYIE_Pos                (1U)
-#define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)   /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
-#define RCC_CIER_MSIRDYIE_Pos                (2U)
-#define RCC_CIER_MSIRDYIE_Msk                (0x1UL << RCC_CIER_MSIRDYIE_Pos)   /*!< 0x00000004 */
-#define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk
-#define RCC_CIER_HSIRDYIE_Pos                (3U)
-#define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)   /*!< 0x00000008 */
-#define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
-#define RCC_CIER_HSERDYIE_Pos                (4U)
-#define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)   /*!< 0x00000010 */
-#define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
-#define RCC_CIER_PLLRDYIE_Pos                (5U)
-#define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)/*!< 0x00000020 */
-#define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
-#define RCC_CIER_LSECSSIE_Pos                (9U)
-#define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)   /*!< 0x00000200 */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
-
-/********************  Bit definition for RCC_CIFR register  ******************/
-#define RCC_CIFR_LSIRDYF_Pos                 (0U)
-#define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)  /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk
-#define RCC_CIFR_LSERDYF_Pos                 (1U)
-#define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
-#define RCC_CIFR_MSIRDYF_Pos                 (2U)
-#define RCC_CIFR_MSIRDYF_Msk                 (0x1UL << RCC_CIFR_MSIRDYF_Pos)   /*!< 0x00000004 */
-#define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk
-#define RCC_CIFR_HSIRDYF_Pos                 (3U)
-#define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */
-#define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
-#define RCC_CIFR_HSERDYF_Pos                 (4U)
-#define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */
-#define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
-#define RCC_CIFR_PLLRDYF_Pos                 (5U)
-#define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)/*!< 0x00000020 */
-#define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
-#define RCC_CIFR_CSSF_Pos                    (8U)
-#define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)   /*!< 0x00000100 */
-#define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
-#define RCC_CIFR_LSECSSF_Pos                 (9U)
-#define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */
-#define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
-
-/********************  Bit definition for RCC_CICR register  ******************/
-#define RCC_CICR_LSIRDYC_Pos                (0U)
-#define RCC_CICR_LSIRDYC_Msk                (0x1UL << RCC_CICR_LSIRDYC_Pos)  /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                    RCC_CICR_LSIRDYC_Msk
-#define RCC_CICR_LSERDYC_Pos                (1U)
-#define RCC_CICR_LSERDYC_Msk                (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                    RCC_CICR_LSERDYC_Msk
-#define RCC_CICR_MSIRDYC_Pos                (2U)
-#define RCC_CICR_MSIRDYC_Msk                (0x1UL << RCC_CICR_MSIRDYC_Pos)   /*!< 0x00000004 */
-#define RCC_CICR_MSIRDYC                    RCC_CICR_MSIRDYC_Msk
-#define RCC_CICR_HSIRDYC_Pos                (3U)
-#define RCC_CICR_HSIRDYC_Msk                (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */
-#define RCC_CICR_HSIRDYC                    RCC_CICR_HSIRDYC_Msk
-#define RCC_CICR_HSERDYC_Pos                (4U)
-#define RCC_CICR_HSERDYC_Msk                (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */
-#define RCC_CICR_HSERDYC                    RCC_CICR_HSERDYC_Msk
-#define RCC_CICR_PLLRDYC_Pos                (5U)
-#define RCC_CICR_PLLRDYC_Msk                (0x1UL << RCC_CICR_PLLRDYC_Pos)/*!< 0x00000020 */
-#define RCC_CICR_PLLRDYC                    RCC_CICR_PLLRDYC_Msk
-#define RCC_CICR_CSSC_Pos                   (8U)
-#define RCC_CICR_CSSC_Msk                   (0x1UL << RCC_CICR_CSSC_Pos)   /*!< 0x00000100 */
-#define RCC_CICR_CSSC                       RCC_CICR_CSSC_Msk
-#define RCC_CICR_LSECSSC_Pos                (9U)
-#define RCC_CICR_LSECSSC_Msk                (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */
-#define RCC_CICR_LSECSSC                    RCC_CICR_LSECSSC_Msk
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
-#define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
-#define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
-#define RCC_AHB1RSTR_DMA2RST_Pos             (1U)
-#define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
-#define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk
-#define RCC_AHB1RSTR_DMAMUX1RST_Pos          (2U)
-#define RCC_AHB1RSTR_DMAMUX1RST_Msk          (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
-#define RCC_AHB1RSTR_DMAMUX1RST              RCC_AHB1RSTR_DMAMUX1RST_Msk
-#define RCC_AHB1RSTR_CRCRST_Pos              (12U)
-#define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
-#define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
-
-/********************  Bit definition for RCC_AHB2RSTR register  ***************/
-#define RCC_AHB2RSTR_GPIOARST_Pos           (0U)
-#define RCC_AHB2RSTR_GPIOARST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
-#define RCC_AHB2RSTR_GPIOARST               RCC_AHB2RSTR_GPIOARST_Msk
-#define RCC_AHB2RSTR_GPIOBRST_Pos           (1U)
-#define RCC_AHB2RSTR_GPIOBRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
-#define RCC_AHB2RSTR_GPIOBRST               RCC_AHB2RSTR_GPIOBRST_Msk
-#define RCC_AHB2RSTR_GPIOCRST_Pos           (2U)
-#define RCC_AHB2RSTR_GPIOCRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
-#define RCC_AHB2RSTR_GPIOCRST               RCC_AHB2RSTR_GPIOCRST_Msk
-#define RCC_AHB2RSTR_GPIOHRST_Pos           (7U)
-#define RCC_AHB2RSTR_GPIOHRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)/*!< 0x00000080 */
-#define RCC_AHB2RSTR_GPIOHRST               RCC_AHB2RSTR_GPIOHRST_Msk
-
-/********************  Bit definition for RCC_AHB3RSTR register  ***************/
-#define RCC_AHB3RSTR_PKARST_Pos             (16U)
-#define RCC_AHB3RSTR_PKARST_Msk             (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00010000 */
-#define RCC_AHB3RSTR_PKARST                 RCC_AHB3RSTR_PKARST_Msk
-#define RCC_AHB3RSTR_AESRST_Pos             (17U)
-#define RCC_AHB3RSTR_AESRST_Msk             (0x1UL << RCC_AHB3RSTR_AESRST_Pos)/*!< 0x00020000 */
-#define RCC_AHB3RSTR_AESRST                 RCC_AHB3RSTR_AESRST_Msk
-#define RCC_AHB3RSTR_RNGRST_Pos             (18U)
-#define RCC_AHB3RSTR_RNGRST_Msk             (0x1UL << RCC_AHB3RSTR_RNGRST_Pos)/*!< 0x00040000 */
-#define RCC_AHB3RSTR_RNGRST                 RCC_AHB3RSTR_RNGRST_Msk
-
-#define RCC_AHB3RSTR_HSEMRST_Pos            (19U)
-#define RCC_AHB3RSTR_HSEMRST_Msk            (0x1UL << RCC_AHB3RSTR_HSEMRST_Pos)/*!< 0x00080000 */
-#define RCC_AHB3RSTR_HSEMRST                RCC_AHB3RSTR_HSEMRST_Msk
-#define RCC_AHB3RSTR_IPCCRST_Pos            (20U)
-#define RCC_AHB3RSTR_IPCCRST_Msk            (0x1UL << RCC_AHB3RSTR_IPCCRST_Pos)/*!< 0x00100000 */
-#define RCC_AHB3RSTR_IPCCRST                RCC_AHB3RSTR_IPCCRST_Msk
-#define RCC_AHB3RSTR_FLASHRST_Pos           (25U)
-#define RCC_AHB3RSTR_FLASHRST_Msk           (0x1UL << RCC_AHB3RSTR_FLASHRST_Pos) /*!< 0x02000000 */
-#define RCC_AHB3RSTR_FLASHRST               RCC_AHB3RSTR_FLASHRST_Msk
-
-/********************  Bit definition for RCC_APB1RSTR1 register  **************/
-#define RCC_APB1RSTR1_TIM2RST_Pos           (0U)
-#define RCC_APB1RSTR1_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
-#define RCC_APB1RSTR1_TIM2RST               RCC_APB1RSTR1_TIM2RST_Msk
-#define RCC_APB1RSTR1_SPI2RST_Pos           (14U)
-#define RCC_APB1RSTR1_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
-#define RCC_APB1RSTR1_SPI2RST               RCC_APB1RSTR1_SPI2RST_Msk
-#define RCC_APB1RSTR1_USART2RST_Pos         (17U)
-#define RCC_APB1RSTR1_USART2RST_Msk         (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
-#define RCC_APB1RSTR1_USART2RST             RCC_APB1RSTR1_USART2RST_Msk
-#define RCC_APB1RSTR1_I2C1RST_Pos           (21U)
-#define RCC_APB1RSTR1_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
-#define RCC_APB1RSTR1_I2C1RST               RCC_APB1RSTR1_I2C1RST_Msk
-#define RCC_APB1RSTR1_I2C2RST_Pos           (22U)
-#define RCC_APB1RSTR1_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
-#define RCC_APB1RSTR1_I2C2RST               RCC_APB1RSTR1_I2C2RST_Msk
-#define RCC_APB1RSTR1_I2C3RST_Pos           (23U)
-#define RCC_APB1RSTR1_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x00800000 */
-#define RCC_APB1RSTR1_I2C3RST               RCC_APB1RSTR1_I2C3RST_Msk
-#define RCC_APB1RSTR1_DACRST_Pos            (29U)
-#define RCC_APB1RSTR1_DACRST_Msk            (0x1UL << RCC_APB1RSTR1_DACRST_Pos)/*!< 0x20000000 */
-#define RCC_APB1RSTR1_DACRST                RCC_APB1RSTR1_DACRST_Msk
-#define RCC_APB1RSTR1_LPTIM1RST_Pos         (31U)
-#define RCC_APB1RSTR1_LPTIM1RST_Msk         (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
-#define RCC_APB1RSTR1_LPTIM1RST             RCC_APB1RSTR1_LPTIM1RST_Msk
-
-/********************  Bit definition for RCC_APB1RSTR2 register  **************/
-#define RCC_APB1RSTR2_LPUART1RST_Pos        (0U)
-#define RCC_APB1RSTR2_LPUART1RST_Msk        (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
-#define RCC_APB1RSTR2_LPUART1RST            RCC_APB1RSTR2_LPUART1RST_Msk
-#define RCC_APB1RSTR2_LPTIM2RST_Pos         (5U)
-#define RCC_APB1RSTR2_LPTIM2RST_Msk         (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)/*!< 0x00000020 */
-#define RCC_APB1RSTR2_LPTIM2RST             RCC_APB1RSTR2_LPTIM2RST_Msk
-#define RCC_APB1RSTR2_LPTIM3RST_Pos         (6U)
-#define RCC_APB1RSTR2_LPTIM3RST_Msk         (0x1UL << RCC_APB1RSTR2_LPTIM3RST_Pos)/*!< 0x00000040 */
-#define RCC_APB1RSTR2_LPTIM3RST             RCC_APB1RSTR2_LPTIM3RST_Msk
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define RCC_APB2RSTR_ADCRST_Pos             (9U)
-#define RCC_APB2RSTR_ADCRST_Msk             (0x1UL << RCC_APB2RSTR_ADCRST_Pos)/*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST                 RCC_APB2RSTR_ADCRST_Msk
-#define RCC_APB2RSTR_TIM1RST_Pos            (11U)
-#define RCC_APB2RSTR_TIM1RST_Msk            (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
-#define RCC_APB2RSTR_TIM1RST                RCC_APB2RSTR_TIM1RST_Msk
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk
-#define RCC_APB2RSTR_TIM16RST_Pos           (17U)
-#define RCC_APB2RSTR_TIM16RST_Msk           (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
-#define RCC_APB2RSTR_TIM16RST               RCC_APB2RSTR_TIM16RST_Msk
-#define RCC_APB2RSTR_TIM17RST_Pos           (18U)
-#define RCC_APB2RSTR_TIM17RST_Msk           (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
-#define RCC_APB2RSTR_TIM17RST               RCC_APB2RSTR_TIM17RST_Msk
-
-/********************  Bit definition for RCC_APB3RSTR register  **************/
-#define RCC_APB3RSTR_SUBGHZSPIRST_Pos            (0U)
-#define RCC_APB3RSTR_SUBGHZSPIRST_Msk            (0x1UL << RCC_APB3RSTR_SUBGHZSPIRST_Pos) /*!< 0x00000001 */
-#define RCC_APB3RSTR_SUBGHZSPIRST                RCC_APB3RSTR_SUBGHZSPIRST_Msk
-
-/********************  Bit definition for RCC_AHB1ENR register  ****************/
-#define RCC_AHB1ENR_DMA1EN_Pos              (0U)
-#define RCC_AHB1ENR_DMA1EN_Msk              (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)  /*!< 0x00000001 */
-#define RCC_AHB1ENR_DMA1EN                  RCC_AHB1ENR_DMA1EN_Msk
-#define RCC_AHB1ENR_DMA2EN_Pos              (1U)
-#define RCC_AHB1ENR_DMA2EN_Msk              (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)  /*!< 0x00000002 */
-#define RCC_AHB1ENR_DMA2EN                  RCC_AHB1ENR_DMA2EN_Msk
-#define RCC_AHB1ENR_DMAMUX1EN_Pos           (2U)
-#define RCC_AHB1ENR_DMAMUX1EN_Msk           (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
-#define RCC_AHB1ENR_DMAMUX1EN               RCC_AHB1ENR_DMAMUX1EN_Msk
-#define RCC_AHB1ENR_CRCEN_Pos               (12U)
-#define RCC_AHB1ENR_CRCEN_Msk               (0x1UL << RCC_AHB1ENR_CRCEN_Pos)   /*!< 0x00001000 */
-#define RCC_AHB1ENR_CRCEN                   RCC_AHB1ENR_CRCEN_Msk
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define RCC_AHB2ENR_GPIOAEN_Pos             (0U)
-#define RCC_AHB2ENR_GPIOAEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
-#define RCC_AHB2ENR_GPIOAEN                 RCC_AHB2ENR_GPIOAEN_Msk
-#define RCC_AHB2ENR_GPIOBEN_Pos             (1U)
-#define RCC_AHB2ENR_GPIOBEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
-#define RCC_AHB2ENR_GPIOBEN                 RCC_AHB2ENR_GPIOBEN_Msk
-#define RCC_AHB2ENR_GPIOCEN_Pos             (2U)
-#define RCC_AHB2ENR_GPIOCEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
-#define RCC_AHB2ENR_GPIOCEN                 RCC_AHB2ENR_GPIOCEN_Msk
-#define RCC_AHB2ENR_GPIOHEN_Pos             (7U)
-#define RCC_AHB2ENR_GPIOHEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
-#define RCC_AHB2ENR_GPIOHEN                 RCC_AHB2ENR_GPIOHEN_Msk
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define RCC_AHB3ENR_PKAEN_Pos               (16U)
-#define RCC_AHB3ENR_PKAEN_Msk               (0x1UL << RCC_AHB3ENR_PKAEN_Pos)   /*!< 0x00010000 */
-#define RCC_AHB3ENR_PKAEN                   RCC_AHB3ENR_PKAEN_Msk
-#define RCC_AHB3ENR_AESEN_Pos               (17U)
-#define RCC_AHB3ENR_AESEN_Msk               (0x1UL << RCC_AHB3ENR_AESEN_Pos)/*!< 0x00020000 */
-#define RCC_AHB3ENR_AESEN                   RCC_AHB3ENR_AESEN_Msk
-#define RCC_AHB3ENR_RNGEN_Pos               (18U)
-#define RCC_AHB3ENR_RNGEN_Msk               (0x1UL << RCC_AHB3ENR_RNGEN_Pos)  /*!< 0x00040000 */
-#define RCC_AHB3ENR_RNGEN                   RCC_AHB3ENR_RNGEN_Msk
-#define RCC_AHB3ENR_HSEMEN_Pos              (19U)
-#define RCC_AHB3ENR_HSEMEN_Msk              (0x1UL << RCC_AHB3ENR_HSEMEN_Pos)  /*!< 0x00080000 */
-#define RCC_AHB3ENR_HSEMEN                  RCC_AHB3ENR_HSEMEN_Msk
-#define RCC_AHB3ENR_IPCCEN_Pos              (20U)
-#define RCC_AHB3ENR_IPCCEN_Msk              (0x1UL << RCC_AHB3ENR_IPCCEN_Pos)  /*!< 0x00100000 */
-#define RCC_AHB3ENR_IPCCEN                  RCC_AHB3ENR_IPCCEN_Msk
-#define RCC_AHB3ENR_FLASHEN_Pos             (25U)
-#define RCC_AHB3ENR_FLASHEN_Msk             (0x1UL << RCC_AHB3ENR_FLASHEN_Pos)   /*!< 0x02000000 */
-#define RCC_AHB3ENR_FLASHEN                 RCC_AHB3ENR_FLASHEN_Msk
-
-/********************  Bit definition for RCC_APB1ENR1 register  **************/
-#define RCC_APB1ENR1_TIM2EN_Pos             (0U)
-#define RCC_APB1ENR1_TIM2EN_Msk             (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
-#define RCC_APB1ENR1_TIM2EN                 RCC_APB1ENR1_TIM2EN_Msk
-#define RCC_APB1ENR1_RTCAPBEN_Pos           (10U)
-#define RCC_APB1ENR1_RTCAPBEN_Msk           (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
-#define RCC_APB1ENR1_RTCAPBEN               RCC_APB1ENR1_RTCAPBEN_Msk
-#define RCC_APB1ENR1_WWDGEN_Pos             (11U)
-#define RCC_APB1ENR1_WWDGEN_Msk             (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1ENR1_WWDGEN                 RCC_APB1ENR1_WWDGEN_Msk
-#define RCC_APB1ENR1_SPI2EN_Pos             (14U)
-#define RCC_APB1ENR1_SPI2EN_Msk             (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
-#define RCC_APB1ENR1_SPI2EN                 RCC_APB1ENR1_SPI2EN_Msk
-#define RCC_APB1ENR1_USART2EN_Pos           (17U)
-#define RCC_APB1ENR1_USART2EN_Msk           (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR1_USART2EN               RCC_APB1ENR1_USART2EN_Msk
-#define RCC_APB1ENR1_I2C1EN_Pos             (21U)
-#define RCC_APB1ENR1_I2C1EN_Msk             (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
-#define RCC_APB1ENR1_I2C1EN                 RCC_APB1ENR1_I2C1EN_Msk
-#define RCC_APB1ENR1_I2C2EN_Pos             (22U)
-#define RCC_APB1ENR1_I2C2EN_Msk             (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
-#define RCC_APB1ENR1_I2C2EN                 RCC_APB1ENR1_I2C2EN_Msk
-#define RCC_APB1ENR1_I2C3EN_Pos             (23U)
-#define RCC_APB1ENR1_I2C3EN_Msk             (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
-#define RCC_APB1ENR1_I2C3EN                 RCC_APB1ENR1_I2C3EN_Msk
-#define RCC_APB1ENR1_DACEN_Pos              (29U)
-#define RCC_APB1ENR1_DACEN_Msk              (0x1UL << RCC_APB1ENR1_DACEN_Pos)/*!< 0x20000000 */
-#define RCC_APB1ENR1_DACEN                  RCC_APB1ENR1_DACEN_Msk
-#define RCC_APB1ENR1_LPTIM1EN_Pos           (31U)
-#define RCC_APB1ENR1_LPTIM1EN_Msk           (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
-#define RCC_APB1ENR1_LPTIM1EN               RCC_APB1ENR1_LPTIM1EN_Msk
-
-/********************  Bit definition for RCC_APB1ENR2 register  **************/
-#define RCC_APB1ENR2_LPUART1EN_Pos          (0U)
-#define RCC_APB1ENR2_LPUART1EN_Msk         (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
-#define RCC_APB1ENR2_LPUART1EN              RCC_APB1ENR2_LPUART1EN_Msk
-#define RCC_APB1ENR2_LPTIM2EN_Pos           (5U)
-#define RCC_APB1ENR2_LPTIM2EN_Msk           (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)/*!< 0x00000020 */
-#define RCC_APB1ENR2_LPTIM2EN               RCC_APB1ENR2_LPTIM2EN_Msk
-#define RCC_APB1ENR2_LPTIM3EN_Pos           (6U)
-#define RCC_APB1ENR2_LPTIM3EN_Msk           (0x1UL << RCC_APB1ENR2_LPTIM3EN_Pos)/*!< 0x00000040 */
-#define RCC_APB1ENR2_LPTIM3EN               RCC_APB1ENR2_LPTIM3EN_Msk
-
-/********************  Bit definition for RCC_APB2ENR register  **************/
-#define RCC_APB2ENR_ADCEN_Pos               (9U)
-#define RCC_APB2ENR_ADCEN_Msk               (0x1UL << RCC_APB2ENR_ADCEN_Pos)  /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                   RCC_APB2ENR_ADCEN_Msk
-#define RCC_APB2ENR_TIM1EN_Pos              (11U)
-#define RCC_APB2ENR_TIM1EN_Msk              (0x1UL << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
-#define RCC_APB2ENR_TIM1EN                  RCC_APB2ENR_TIM1EN_Msk
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk
-#define RCC_APB2ENR_USART1EN_Pos            (14U)
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk
-#define RCC_APB2ENR_TIM16EN_Pos             (17U)
-#define RCC_APB2ENR_TIM16EN_Msk             (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
-#define RCC_APB2ENR_TIM16EN                 RCC_APB2ENR_TIM16EN_Msk
-#define RCC_APB2ENR_TIM17EN_Pos             (18U)
-#define RCC_APB2ENR_TIM17EN_Msk             (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
-#define RCC_APB2ENR_TIM17EN                 RCC_APB2ENR_TIM17EN_Msk
-
-/********************  Bit definition for RCC_APB3ENR register  **************/
-#define RCC_APB3ENR_SUBGHZSPIEN_Pos         (0U)
-#define RCC_APB3ENR_SUBGHZSPIEN_Msk         (0x1UL << RCC_APB3ENR_SUBGHZSPIEN_Pos)/*!< 0x00000001 */
-#define RCC_APB3ENR_SUBGHZSPIEN             RCC_APB3ENR_SUBGHZSPIEN_Msk
-
-/********************  Bit definition for RCC_AHB1SMENR register  ****************/
-#define RCC_AHB1SMENR_DMA1SMEN_Pos          (0U)
-#define RCC_AHB1SMENR_DMA1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
-#define RCC_AHB1SMENR_DMA1SMEN              RCC_AHB1SMENR_DMA1SMEN_Msk
-#define RCC_AHB1SMENR_DMA2SMEN_Pos          (1U)
-#define RCC_AHB1SMENR_DMA2SMEN_Msk          (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
-#define RCC_AHB1SMENR_DMA2SMEN              RCC_AHB1SMENR_DMA2SMEN_Msk
-#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos       (2U)
-#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk       (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
-#define RCC_AHB1SMENR_DMAMUX1SMEN           RCC_AHB1SMENR_DMAMUX1SMEN_Msk
-#define RCC_AHB1SMENR_CRCSMEN_Pos           (12U)
-#define RCC_AHB1SMENR_CRCSMEN_Msk           (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
-#define RCC_AHB1SMENR_CRCSMEN               RCC_AHB1SMENR_CRCSMEN_Msk
-
-/********************  Bit definition for RCC_AHB2SMENR register  ***************/
-#define RCC_AHB2SMENR_GPIOASMEN_Pos         (0U)
-#define RCC_AHB2SMENR_GPIOASMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
-#define RCC_AHB2SMENR_GPIOASMEN             RCC_AHB2SMENR_GPIOASMEN_Msk
-#define RCC_AHB2SMENR_GPIOBSMEN_Pos         (1U)
-#define RCC_AHB2SMENR_GPIOBSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
-#define RCC_AHB2SMENR_GPIOBSMEN             RCC_AHB2SMENR_GPIOBSMEN_Msk
-#define RCC_AHB2SMENR_GPIOCSMEN_Pos         (2U)
-#define RCC_AHB2SMENR_GPIOCSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
-#define RCC_AHB2SMENR_GPIOCSMEN             RCC_AHB2SMENR_GPIOCSMEN_Msk
-#define RCC_AHB2SMENR_GPIOHSMEN_Pos         (7U)
-#define RCC_AHB2SMENR_GPIOHSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos)/*!< 0x00000080 */
-#define RCC_AHB2SMENR_GPIOHSMEN             RCC_AHB2SMENR_GPIOHSMEN_Msk
-
-/********************  Bit definition for RCC_AHB3SMENR register  ***************/
-#define RCC_AHB3SMENR_PKASMEN_Pos           (16U)
-#define RCC_AHB3SMENR_PKASMEN_Msk           (0x1UL << RCC_AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */
-#define RCC_AHB3SMENR_PKASMEN               RCC_AHB3SMENR_PKASMEN_Msk
-#define RCC_AHB3SMENR_AESSMEN_Pos           (17U)
-#define RCC_AHB3SMENR_AESSMEN_Msk           (0x1UL << RCC_AHB3SMENR_AESSMEN_Pos) /*!< 0x00020000 */
-#define RCC_AHB3SMENR_AESSMEN               RCC_AHB3SMENR_AESSMEN_Msk
-#define RCC_AHB3SMENR_RNGSMEN_Pos           (18U)
-#define RCC_AHB3SMENR_RNGSMEN_Msk           (0x1UL << RCC_AHB3SMENR_RNGSMEN_Pos)/*!< 0x00040000 */
-#define RCC_AHB3SMENR_RNGSMEN               RCC_AHB3SMENR_RNGSMEN_Msk
-#define RCC_AHB3SMENR_SRAM1SMEN_Pos         (23U)
-#define RCC_AHB3SMENR_SRAM1SMEN_Msk         (0x1UL << RCC_AHB3SMENR_SRAM1SMEN_Pos)/*!< 0x00800000 */
-#define RCC_AHB3SMENR_SRAM1SMEN             RCC_AHB3SMENR_SRAM1SMEN_Msk
-#define RCC_AHB3SMENR_SRAM2SMEN_Pos         (24U)
-#define RCC_AHB3SMENR_SRAM2SMEN_Msk         (0x1UL << RCC_AHB3SMENR_SRAM2SMEN_Pos)/*!< 0x01000000 */
-#define RCC_AHB3SMENR_SRAM2SMEN             RCC_AHB3SMENR_SRAM2SMEN_Msk
-#define RCC_AHB3SMENR_FLASHSMEN_Pos         (25U)
-#define RCC_AHB3SMENR_FLASHSMEN_Msk         (0x1UL << RCC_AHB3SMENR_FLASHSMEN_Pos)/*!< 0x02000000 */
-#define RCC_AHB3SMENR_FLASHSMEN             RCC_AHB3SMENR_FLASHSMEN_Msk
-
-/********************  Bit definition for RCC_APB1SMENR1 register  **************/
-#define RCC_APB1SMENR1_TIM2SMEN_Pos         (0U)
-#define RCC_APB1SMENR1_TIM2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
-#define RCC_APB1SMENR1_TIM2SMEN             RCC_APB1SMENR1_TIM2SMEN_Msk
-#define RCC_APB1SMENR1_RTCAPBSMEN_Pos       (10U)
-#define RCC_APB1SMENR1_RTCAPBSMEN_Msk       (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
-#define RCC_APB1SMENR1_RTCAPBSMEN           RCC_APB1SMENR1_RTCAPBSMEN_Msk
-#define RCC_APB1SMENR1_WWDGSMEN_Pos         (11U)
-#define RCC_APB1SMENR1_WWDGSMEN_Msk         (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
-#define RCC_APB1SMENR1_WWDGSMEN             RCC_APB1SMENR1_WWDGSMEN_Msk
-#define RCC_APB1SMENR1_SPI2SMEN_Pos         (14U)
-#define RCC_APB1SMENR1_SPI2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
-#define RCC_APB1SMENR1_SPI2SMEN             RCC_APB1SMENR1_SPI2SMEN_Msk
-#define RCC_APB1SMENR1_USART2SMEN_Pos       (17U)
-#define RCC_APB1SMENR1_USART2SMEN_Msk       (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
-#define RCC_APB1SMENR1_USART2SMEN           RCC_APB1SMENR1_USART2SMEN_Msk
-#define RCC_APB1SMENR1_I2C1SMEN_Pos         (21U)
-#define RCC_APB1SMENR1_I2C1SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
-#define RCC_APB1SMENR1_I2C1SMEN             RCC_APB1SMENR1_I2C1SMEN_Msk
-#define RCC_APB1SMENR1_I2C2SMEN_Pos         (22U)
-#define RCC_APB1SMENR1_I2C2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
-#define RCC_APB1SMENR1_I2C2SMEN             RCC_APB1SMENR1_I2C2SMEN_Msk
-#define RCC_APB1SMENR1_I2C3SMEN_Pos         (23U)
-#define RCC_APB1SMENR1_I2C3SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x00800000 */
-#define RCC_APB1SMENR1_I2C3SMEN             RCC_APB1SMENR1_I2C3SMEN_Msk
-#define RCC_APB1SMENR1_DACSMEN_Pos          (29U)
-#define RCC_APB1SMENR1_DACSMEN_Msk          (0x1UL << RCC_APB1SMENR1_DACSMEN_Pos)/*!< 0x20000000 */
-#define RCC_APB1SMENR1_DACSMEN              RCC_APB1SMENR1_DACSMEN_Msk
-#define RCC_APB1SMENR1_LPTIM1SMEN_Pos       (31U)
-#define RCC_APB1SMENR1_LPTIM1SMEN_Msk       (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
-#define RCC_APB1SMENR1_LPTIM1SMEN           RCC_APB1SMENR1_LPTIM1SMEN_Msk
-
-/********************  Bit definition for RCC_APB1SMENR2 register  **************/
-#define RCC_APB1SMENR2_LPUART1SMEN_Pos      (0U)
-#define RCC_APB1SMENR2_LPUART1SMEN_Msk      (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
-#define RCC_APB1SMENR2_LPUART1SMEN          RCC_APB1SMENR2_LPUART1SMEN_Msk
-#define RCC_APB1SMENR2_LPTIM2SMEN_Pos       (5U)
-#define RCC_APB1SMENR2_LPTIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos)/*!< 0x00000020 */
-#define RCC_APB1SMENR2_LPTIM2SMEN           RCC_APB1SMENR2_LPTIM2SMEN_Msk
-#define RCC_APB1SMENR2_LPTIM3SMEN_Pos       (6U)
-#define RCC_APB1SMENR2_LPTIM3SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPTIM3SMEN_Pos)/*!< 0x00000040 */
-#define RCC_APB1SMENR2_LPTIM3SMEN           RCC_APB1SMENR2_LPTIM3SMEN_Msk
-
-/********************  Bit definition for RCC_APB2SMENR register  **************/
-#define RCC_APB2SMENR_ADCSMEN_Pos           (9U)
-#define RCC_APB2SMENR_ADCSMEN_Msk           (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)/*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN               RCC_APB2SMENR_ADCSMEN_Msk
-#define RCC_APB2SMENR_TIM1SMEN_Pos          (11U)
-#define RCC_APB2SMENR_TIM1SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
-#define RCC_APB2SMENR_TIM1SMEN              RCC_APB2SMENR_TIM1SMEN_Msk
-#define RCC_APB2SMENR_SPI1SMEN_Pos          (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk          (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN              RCC_APB2SMENR_SPI1SMEN_Msk
-#define RCC_APB2SMENR_USART1SMEN_Pos        (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk        (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN            RCC_APB2SMENR_USART1SMEN_Msk
-#define RCC_APB2SMENR_TIM16SMEN_Pos         (17U)
-#define RCC_APB2SMENR_TIM16SMEN_Msk         (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
-#define RCC_APB2SMENR_TIM16SMEN             RCC_APB2SMENR_TIM16SMEN_Msk
-#define RCC_APB2SMENR_TIM17SMEN_Pos         (18U)
-#define RCC_APB2SMENR_TIM17SMEN_Msk         (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
-#define RCC_APB2SMENR_TIM17SMEN             RCC_APB2SMENR_TIM17SMEN_Msk
-
-/********************  Bit definition for RCC_APB3SMENR register  **************/
-#define RCC_APB3SMENR_SUBGHZSPISMEN_Pos     (0U)
-#define RCC_APB3SMENR_SUBGHZSPISMEN_Msk     (0x1UL << RCC_APB3SMENR_SUBGHZSPISMEN_Pos)/*!< 0x00000001 */
-#define RCC_APB3SMENR_SUBGHZSPISMEN         RCC_APB3SMENR_SUBGHZSPISMEN_Msk
-
-/********************  Bit definition for RCC_CCIPR register  ******************/
-#define RCC_CCIPR_USART1SEL_Pos             (0U)
-#define RCC_CCIPR_USART1SEL_Msk             (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL                 RCC_CCIPR_USART1SEL_Msk
-#define RCC_CCIPR_USART1SEL_0               (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1               (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
-
-#define RCC_CCIPR_USART2SEL_Pos             (2U)
-#define RCC_CCIPR_USART2SEL_Msk             (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL                 RCC_CCIPR_USART2SEL_Msk
-#define RCC_CCIPR_USART2SEL_0               (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1               (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
-
-#define RCC_CCIPR_I2S2SEL_Pos               (8U)
-#define RCC_CCIPR_I2S2SEL_Msk               (0x3UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000300 */
-#define RCC_CCIPR_I2S2SEL                   RCC_CCIPR_I2S2SEL_Msk
-#define RCC_CCIPR_I2S2SEL_0                 (0x1UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000100 */
-#define RCC_CCIPR_I2S2SEL_1                 (0x2UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000200 */
-
-#define RCC_CCIPR_LPUART1SEL_Pos            (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk            (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL                RCC_CCIPR_LPUART1SEL_Msk
-#define RCC_CCIPR_LPUART1SEL_0              (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
-#define RCC_CCIPR_LPUART1SEL_1              (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
-
-#define RCC_CCIPR_I2C1SEL_Pos               (12U)
-#define RCC_CCIPR_I2C1SEL_Msk               (0x3UL << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                   RCC_CCIPR_I2C1SEL_Msk
-#define RCC_CCIPR_I2C1SEL_0                 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1                 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00002000 */
-
-#define RCC_CCIPR_I2C2SEL_Pos               (14U)
-#define RCC_CCIPR_I2C2SEL_Msk               (0x3UL << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x0000C000 */
-#define RCC_CCIPR_I2C2SEL                   RCC_CCIPR_I2C2SEL_Msk
-#define RCC_CCIPR_I2C2SEL_0                 (0x1UL << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00004000 */
-#define RCC_CCIPR_I2C2SEL_1                 (0x2UL << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00008000 */
-
-#define RCC_CCIPR_I2C3SEL_Pos               (16U)
-#define RCC_CCIPR_I2C3SEL_Msk               (0x3UL << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00030000 */
-#define RCC_CCIPR_I2C3SEL                   RCC_CCIPR_I2C3SEL_Msk
-#define RCC_CCIPR_I2C3SEL_0                 (0x1UL << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00010000 */
-#define RCC_CCIPR_I2C3SEL_1                 (0x2UL << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00020000 */
-
-#define RCC_CCIPR_LPTIM1SEL_Pos             (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk             (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL                 RCC_CCIPR_LPTIM1SEL_Msk
-#define RCC_CCIPR_LPTIM1SEL_0               (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1               (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
-
-#define RCC_CCIPR_LPTIM2SEL_Pos             (20U)
-#define RCC_CCIPR_LPTIM2SEL_Msk             (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
-#define RCC_CCIPR_LPTIM2SEL                 RCC_CCIPR_LPTIM2SEL_Msk
-#define RCC_CCIPR_LPTIM2SEL_0               (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
-#define RCC_CCIPR_LPTIM2SEL_1               (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
-
-#define RCC_CCIPR_LPTIM3SEL_Pos             (22U)
-#define RCC_CCIPR_LPTIM3SEL_Msk             (0x3UL << RCC_CCIPR_LPTIM3SEL_Pos)   /*!< 0x00C00000 */
-#define RCC_CCIPR_LPTIM3SEL                 RCC_CCIPR_LPTIM3SEL_Msk
-#define RCC_CCIPR_LPTIM3SEL_0               (0x1UL << RCC_CCIPR_LPTIM3SEL_Pos)   /*!< 0x00400000 */
-#define RCC_CCIPR_LPTIM3SEL_1               (0x2UL << RCC_CCIPR_LPTIM3SEL_Pos)   /*!< 0x00800000 */
-
-#define RCC_CCIPR_ADCSEL_Pos                (28U)
-#define RCC_CCIPR_ADCSEL_Msk                (0x3UL << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x30000000 */
-#define RCC_CCIPR_ADCSEL                    RCC_CCIPR_ADCSEL_Msk
-#define RCC_CCIPR_ADCSEL_0                  (0x1UL << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x10000000 */
-#define RCC_CCIPR_ADCSEL_1                  (0x2UL << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x20000000 */
-
-#define RCC_CCIPR_RNGSEL_Pos                (30U)
-#define RCC_CCIPR_RNGSEL_Msk                (0x3UL << RCC_CCIPR_RNGSEL_Pos)    /*!< 0xC0000000 */
-#define RCC_CCIPR_RNGSEL                    RCC_CCIPR_RNGSEL_Msk
-#define RCC_CCIPR_RNGSEL_0                  (0x1UL << RCC_CCIPR_RNGSEL_Pos)    /*!< 0x40000000 */
-#define RCC_CCIPR_RNGSEL_1                  (0x2UL << RCC_CCIPR_RNGSEL_Pos)    /*!< 0x80000000 */
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define RCC_BDCR_LSEON_Pos                  (0U)
-#define RCC_BDCR_LSEON_Msk                  (0x1UL << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
-#define RCC_BDCR_LSEON                      RCC_BDCR_LSEON_Msk
-#define RCC_BDCR_LSERDY_Pos                 (1U)
-#define RCC_BDCR_LSERDY_Msk                 (0x1UL << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
-#define RCC_BDCR_LSERDY                     RCC_BDCR_LSERDY_Msk
-#define RCC_BDCR_LSEBYP_Pos                 (2U)
-#define RCC_BDCR_LSEBYP_Msk                 (0x1UL << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
-#define RCC_BDCR_LSEBYP                     RCC_BDCR_LSEBYP_Msk
-
-#define RCC_BDCR_LSEDRV_Pos                 (3U)
-#define RCC_BDCR_LSEDRV_Msk                 (0x3UL << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000018 */
-#define RCC_BDCR_LSEDRV                     RCC_BDCR_LSEDRV_Msk
-#define RCC_BDCR_LSEDRV_0                   (0x1UL << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000008 */
-#define RCC_BDCR_LSEDRV_1                   (0x2UL << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000010 */
-
-#define RCC_BDCR_LSECSSON_Pos               (5U)
-#define RCC_BDCR_LSECSSON_Msk               (0x1UL << RCC_BDCR_LSECSSON_Pos)   /*!< 0x00000020 */
-#define RCC_BDCR_LSECSSON                   RCC_BDCR_LSECSSON_Msk
-#define RCC_BDCR_LSECSSD_Pos                (6U)
-#define RCC_BDCR_LSECSSD_Msk                (0x1UL << RCC_BDCR_LSECSSD_Pos)    /*!< 0x00000040 */
-#define RCC_BDCR_LSECSSD                    RCC_BDCR_LSECSSD_Msk
-#define RCC_BDCR_LSESYSEN_Pos               (7U)
-#define RCC_BDCR_LSESYSEN_Msk               (0x1UL << RCC_BDCR_LSESYSEN_Pos)   /*!< 0x00000080 */
-#define RCC_BDCR_LSESYSEN                   RCC_BDCR_LSESYSEN_Msk
-
-#define RCC_BDCR_RTCSEL_Pos                 (8U)
-#define RCC_BDCR_RTCSEL_Msk                 (0x3UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
-#define RCC_BDCR_RTCSEL                     RCC_BDCR_RTCSEL_Msk
-#define RCC_BDCR_RTCSEL_0                   (0x1UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
-#define RCC_BDCR_RTCSEL_1                   (0x2UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
-
-#define RCC_BDCR_LSESYSRDY_Pos              (11U)
-#define RCC_BDCR_LSESYSRDY_Msk              (0x1UL << RCC_BDCR_LSESYSRDY_Pos) /*!< 0x00000800 */
-#define RCC_BDCR_LSESYSRDY                  RCC_BDCR_LSESYSRDY_Msk
-
-#define RCC_BDCR_RTCEN_Pos                  (15U)
-#define RCC_BDCR_RTCEN_Msk                  (0x1UL << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
-#define RCC_BDCR_RTCEN                      RCC_BDCR_RTCEN_Msk
-
-#define RCC_BDCR_BDRST_Pos                  (16U)
-#define RCC_BDCR_BDRST_Msk                  (0x1UL << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
-#define RCC_BDCR_BDRST                      RCC_BDCR_BDRST_Msk
-
-#define RCC_BDCR_LSCOEN_Pos                 (24U)
-#define RCC_BDCR_LSCOEN_Msk                 (0x1UL << RCC_BDCR_LSCOEN_Pos)     /*!< 0x01000000 */
-#define RCC_BDCR_LSCOEN                     RCC_BDCR_LSCOEN_Msk
-#define RCC_BDCR_LSCOSEL_Pos                (25U)
-#define RCC_BDCR_LSCOSEL_Msk                (0x1UL << RCC_BDCR_LSCOSEL_Pos)    /*!< 0x02000000 */
-#define RCC_BDCR_LSCOSEL                    RCC_BDCR_LSCOSEL_Msk
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                  (0U)
-#define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */
-#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk
-#define RCC_CSR_LSIRDY_Pos                 (1U)
-#define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk
-#define RCC_CSR_LSIPRE_Pos                 (4U)
-#define RCC_CSR_LSIPRE_Msk                 (0x1UL << RCC_CSR_LSIPRE_Pos)     /*!< 0x00000010 */
-#define RCC_CSR_LSIPRE                     RCC_CSR_LSIPRE_Msk
-
-#define RCC_CSR_MSISRANGE_Pos              (8U)
-#define RCC_CSR_MSISRANGE_Msk              (0xFUL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000F00 */
-#define RCC_CSR_MSISRANGE                  RCC_CSR_MSISRANGE_Msk
-#define RCC_CSR_MSISRANGE_1                (0x4UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000400 */
-#define RCC_CSR_MSISRANGE_2                (0x5UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000500 */
-#define RCC_CSR_MSISRANGE_4                (0x6UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000600 */
-#define RCC_CSR_MSISRANGE_8                (0x7UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000700 */
-
-#define RCC_CSR_RFRSTF_Pos                  (14U)
-#define RCC_CSR_RFRSTF_Msk                  (0x1UL << RCC_CSR_RFRSTF_Pos)      /*!< 0x0004000 */
-#define RCC_CSR_RFRSTF                      RCC_CSR_RFRSTF_Msk
-#define RCC_CSR_RFRST_Pos                   (15U)
-#define RCC_CSR_RFRST_Msk                   (0x1UL << RCC_CSR_RFRST_Pos)       /*!< 0x0008000 */
-#define RCC_CSR_RFRST                       RCC_CSR_RFRST_Msk
-
-#define RCC_CSR_RMVF_Pos                    (23U)
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)        /*!< 0x00800000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk
-#define RCC_CSR_RFILARSTF_Pos               (24U)
-#define RCC_CSR_RFILARSTF_Msk               (0x1UL << RCC_CSR_RFILARSTF_Pos)   /*!< 0x01000000 */
-#define RCC_CSR_RFILARSTF                   RCC_CSR_RFILARSTF_Msk
-#define RCC_CSR_OBLRSTF_Pos                 (25U)
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)     /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk
-#define RCC_CSR_PINRSTF_Pos                 (26U)
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk
-#define RCC_CSR_BORRSTF_Pos                 (27U)
-#define RCC_CSR_BORRSTF_Msk                 (0x1UL << RCC_CSR_BORRSTF_Pos)     /*!< 0x08000000 */
-#define RCC_CSR_BORRSTF                     RCC_CSR_BORRSTF_Msk
-#define RCC_CSR_SFTRSTF_Pos                 (28U)
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk
-#define RCC_CSR_IWDGRSTF_Pos                (29U)
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk
-#define RCC_CSR_WWDGRSTF_Pos                (30U)
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk
-#define RCC_CSR_LPWRRSTF_Pos                (31U)
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk
-
-/********************  Bit definition for RCC_EXTCFGR register  *******************/
-#define RCC_EXTCFGR_SHDHPRE_Pos             (0U)
-#define RCC_EXTCFGR_SHDHPRE_Msk             (0xFUL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x0000000F */
-#define RCC_EXTCFGR_SHDHPRE                 RCC_EXTCFGR_SHDHPRE_Msk
-#define RCC_EXTCFGR_SHDHPRE_0               (0x1UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000001 */
-#define RCC_EXTCFGR_SHDHPRE_1               (0x2UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000002 */
-#define RCC_EXTCFGR_SHDHPRE_2               (0x4UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000004 */
-#define RCC_EXTCFGR_SHDHPRE_3               (0x8UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000008 */
-
-#define RCC_EXTCFGR_C2HPRE_Pos              (4U)
-#define RCC_EXTCFGR_C2HPRE_Msk              (0xFUL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x000000F0 */
-#define RCC_EXTCFGR_C2HPRE                  RCC_EXTCFGR_C2HPRE_Msk
-#define RCC_EXTCFGR_C2HPRE_0                (0x1UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000010 */
-#define RCC_EXTCFGR_C2HPRE_1                (0x2UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000020 */
-#define RCC_EXTCFGR_C2HPRE_2                (0x4UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000040 */
-#define RCC_EXTCFGR_C2HPRE_3                (0x8UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000080 */
-
-#define RCC_EXTCFGR_SHDHPREF_Pos            (16U)
-#define RCC_EXTCFGR_SHDHPREF_Msk            (0x1UL << RCC_EXTCFGR_SHDHPREF_Pos)/*!< 0x00010000 */
-#define RCC_EXTCFGR_SHDHPREF                RCC_EXTCFGR_SHDHPREF_Msk
-#define RCC_EXTCFGR_C2HPREF_Pos             (17U)
-#define RCC_EXTCFGR_C2HPREF_Msk             (0x1UL << RCC_EXTCFGR_C2HPREF_Pos)/*!< 0x00020000 */
-#define RCC_EXTCFGR_C2HPREF                 RCC_EXTCFGR_C2HPREF_Msk
-
-/********************  Bit definition for RCC_C2AHB1ENR register  ****************/
-#define RCC_C2AHB1ENR_DMA1EN_Pos            (0U)
-#define RCC_C2AHB1ENR_DMA1EN_Msk            (0x1UL << RCC_C2AHB1ENR_DMA1EN_Pos)/*!< 0x00000001 */
-#define RCC_C2AHB1ENR_DMA1EN                RCC_C2AHB1ENR_DMA1EN_Msk
-#define RCC_C2AHB1ENR_DMA2EN_Pos            (1U)
-#define RCC_C2AHB1ENR_DMA2EN_Msk            (0x1UL << RCC_C2AHB1ENR_DMA2EN_Pos)/*!< 0x00000002 */
-#define RCC_C2AHB1ENR_DMA2EN                RCC_C2AHB1ENR_DMA2EN_Msk
-#define RCC_C2AHB1ENR_DMAMUX1EN_Pos         (2U)
-#define RCC_C2AHB1ENR_DMAMUX1EN_Msk         (0x1UL << RCC_C2AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
-#define RCC_C2AHB1ENR_DMAMUX1EN             RCC_C2AHB1ENR_DMAMUX1EN_Msk
-#define RCC_C2AHB1ENR_CRCEN_Pos             (12U)
-#define RCC_C2AHB1ENR_CRCEN_Msk             (0x1UL << RCC_C2AHB1ENR_CRCEN_Pos)/*!< 0x00001000 */
-#define RCC_C2AHB1ENR_CRCEN                  RCC_C2AHB1ENR_CRCEN_Msk
-
-/********************  Bit definition for RCC_C2AHB2ENR register  ***************/
-#define RCC_C2AHB2ENR_GPIOAEN_Pos          (0U)
-#define RCC_C2AHB2ENR_GPIOAEN_Msk          (0x1UL << RCC_C2AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
-#define RCC_C2AHB2ENR_GPIOAEN              RCC_C2AHB2ENR_GPIOAEN_Msk
-#define RCC_C2AHB2ENR_GPIOBEN_Pos          (1U)
-#define RCC_C2AHB2ENR_GPIOBEN_Msk          (0x1UL << RCC_C2AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
-#define RCC_C2AHB2ENR_GPIOBEN              RCC_C2AHB2ENR_GPIOBEN_Msk
-#define RCC_C2AHB2ENR_GPIOCEN_Pos          (2U)
-#define RCC_C2AHB2ENR_GPIOCEN_Msk          (0x1UL << RCC_C2AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
-#define RCC_C2AHB2ENR_GPIOCEN              RCC_C2AHB2ENR_GPIOCEN_Msk
-#define RCC_C2AHB2ENR_GPIOHEN_Pos          (7U)
-#define RCC_C2AHB2ENR_GPIOHEN_Msk          (0x1UL << RCC_C2AHB2ENR_GPIOHEN_Pos)/*!< 0x00000080 */
-#define RCC_C2AHB2ENR_GPIOHEN              RCC_C2AHB2ENR_GPIOHEN_Msk
-
-/********************  Bit definition for RCC_C2AHB3ENR register  ***************/
-#define RCC_C2AHB3ENR_PKAEN_Pos            (16U)
-#define RCC_C2AHB3ENR_PKAEN_Msk            (0x1UL << RCC_C2AHB3ENR_PKAEN_Pos) /*!< 0x00010000 */
-#define RCC_C2AHB3ENR_PKAEN                RCC_C2AHB3ENR_PKAEN_Msk
-#define RCC_C2AHB3ENR_AESEN_Pos            (17U)
-#define RCC_C2AHB3ENR_AESEN_Msk            (0x1UL << RCC_C2AHB3ENR_AESEN_Pos)/*!< 0x00020000 */
-#define RCC_C2AHB3ENR_AESEN                RCC_C2AHB3ENR_AESEN_Msk
-#define RCC_C2AHB3ENR_RNGEN_Pos            (18U)
-#define RCC_C2AHB3ENR_RNGEN_Msk            (0x1UL << RCC_C2AHB3ENR_RNGEN_Pos)/*!< 0x00040000 */
-#define RCC_C2AHB3ENR_RNGEN                RCC_C2AHB3ENR_RNGEN_Msk
-#define RCC_C2AHB3ENR_HSEMEN_Pos           (19U)
-#define RCC_C2AHB3ENR_HSEMEN_Msk           (0x1UL << RCC_C2AHB3ENR_HSEMEN_Pos)/*!< 0x00080000 */
-#define RCC_C2AHB3ENR_HSEMEN               RCC_C2AHB3ENR_HSEMEN_Msk
-#define RCC_C2AHB3ENR_IPCCEN_Pos           (20U)
-#define RCC_C2AHB3ENR_IPCCEN_Msk           (0x1UL << RCC_C2AHB3ENR_IPCCEN_Pos)/*!< 0x00100000 */
-#define RCC_C2AHB3ENR_IPCCEN               RCC_C2AHB3ENR_IPCCEN_Msk
-#define RCC_C2AHB3ENR_FLASHEN_Pos          (25U)
-#define RCC_C2AHB3ENR_FLASHEN_Msk          (0x1UL << RCC_C2AHB3ENR_FLASHEN_Pos)/*!< 0x02000000 */
-#define RCC_C2AHB3ENR_FLASHEN              RCC_C2AHB3ENR_FLASHEN_Msk
-
-/********************  Bit definition for RCC_C2APB1ENR1 register  **************/
-#define RCC_C2APB1ENR1_TIM2EN_Pos          (0U)
-#define RCC_C2APB1ENR1_TIM2EN_Msk          (0x1UL << RCC_C2APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
-#define RCC_C2APB1ENR1_TIM2EN              RCC_C2APB1ENR1_TIM2EN_Msk
-#define RCC_C2APB1ENR1_RTCAPBEN_Pos        (10U)
-#define RCC_C2APB1ENR1_RTCAPBEN_Msk        (0x1UL << RCC_C2APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
-#define RCC_C2APB1ENR1_RTCAPBEN            RCC_C2APB1ENR1_RTCAPBEN_Msk
-#define RCC_C2APB1ENR1_SPI2EN_Pos          (14U)
-#define RCC_C2APB1ENR1_SPI2EN_Msk          (0x1UL << RCC_C2APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
-#define RCC_C2APB1ENR1_SPI2EN              RCC_C2APB1ENR1_SPI2EN_Msk
-#define RCC_C2APB1ENR1_USART2EN_Pos        (17U)
-#define RCC_C2APB1ENR1_USART2EN_Msk        (0x1UL << RCC_C2APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
-#define RCC_C2APB1ENR1_USART2EN            RCC_C2APB1ENR1_USART2EN_Msk
-#define RCC_C2APB1ENR1_I2C1EN_Pos          (21U)
-#define RCC_C2APB1ENR1_I2C1EN_Msk          (0x1UL << RCC_C2APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
-#define RCC_C2APB1ENR1_I2C1EN              RCC_C2APB1ENR1_I2C1EN_Msk
-#define RCC_C2APB1ENR1_I2C2EN_Pos          (22U)
-#define RCC_C2APB1ENR1_I2C2EN_Msk          (0x1UL << RCC_C2APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
-#define RCC_C2APB1ENR1_I2C2EN              RCC_C2APB1ENR1_I2C2EN_Msk
-#define RCC_C2APB1ENR1_I2C3EN_Pos          (23U)
-#define RCC_C2APB1ENR1_I2C3EN_Msk          (0x1UL << RCC_C2APB1ENR1_I2C3EN_Pos)/*!< 0x00800000 */
-#define RCC_C2APB1ENR1_I2C3EN              RCC_C2APB1ENR1_I2C3EN_Msk
-#define RCC_C2APB1ENR1_DACEN_Pos           (29U)
-#define RCC_C2APB1ENR1_DACEN_Msk           (0x1UL << RCC_C2APB1ENR1_DACEN_Pos)/*!< 0x20000000 */
-#define RCC_C2APB1ENR1_DACEN               RCC_C2APB1ENR1_DACEN_Msk
-#define RCC_C2APB1ENR1_LPTIM1EN_Pos        (31U)
-#define RCC_C2APB1ENR1_LPTIM1EN_Msk        (0x1UL << RCC_C2APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
-#define RCC_C2APB1ENR1_LPTIM1EN            RCC_C2APB1ENR1_LPTIM1EN_Msk
-
-/********************  Bit definition for RCC_C2APB1ENR2 register  **************/
-#define RCC_C2APB1ENR2_LPUART1EN_Pos       (0U)
-#define RCC_C2APB1ENR2_LPUART1EN_Msk       (0x1UL << RCC_C2APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
-#define RCC_C2APB1ENR2_LPUART1EN           RCC_C2APB1ENR2_LPUART1EN_Msk
-#define RCC_C2APB1ENR2_LPTIM2EN_Pos        (5U)
-#define RCC_C2APB1ENR2_LPTIM2EN_Msk        (0x1UL << RCC_C2APB1ENR2_LPTIM2EN_Pos)/*!< 0x00000020 */
-#define RCC_C2APB1ENR2_LPTIM2EN            RCC_C2APB1ENR2_LPTIM2EN_Msk
-#define RCC_C2APB1ENR2_LPTIM3EN_Pos        (6U)
-#define RCC_C2APB1ENR2_LPTIM3EN_Msk        (0x1UL << RCC_C2APB1ENR2_LPTIM3EN_Pos)/*!< 0x00000040 */
-#define RCC_C2APB1ENR2_LPTIM3EN            RCC_C2APB1ENR2_LPTIM3EN_Msk
-
-/********************  Bit definition for RCC_C2APB2ENR register  **************/
-#define RCC_C2APB2ENR_ADCEN_Pos            (9U)
-#define RCC_C2APB2ENR_ADCEN_Msk            (0x1UL << RCC_C2APB2ENR_ADCEN_Pos)/*!< 0x00000200 */
-#define RCC_C2APB2ENR_ADCEN                RCC_C2APB2ENR_ADCEN_Msk
-#define RCC_C2APB2ENR_TIM1EN_Pos           (11U)
-#define RCC_C2APB2ENR_TIM1EN_Msk           (0x1UL << RCC_C2APB2ENR_TIM1EN_Pos)/*!< 0x00000800 */
-#define RCC_C2APB2ENR_TIM1EN               RCC_C2APB2ENR_TIM1EN_Msk
-#define RCC_C2APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_C2APB2ENR_SPI1EN_Msk           (0x1UL << RCC_C2APB2ENR_SPI1EN_Pos)/*!< 0x00001000 */
-#define RCC_C2APB2ENR_SPI1EN               RCC_C2APB2ENR_SPI1EN_Msk
-#define RCC_C2APB2ENR_USART1EN_Pos         (14U)
-#define RCC_C2APB2ENR_USART1EN_Msk         (0x1UL << RCC_C2APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
-#define RCC_C2APB2ENR_USART1EN             RCC_C2APB2ENR_USART1EN_Msk
-#define RCC_C2APB2ENR_TIM16EN_Pos          (17U)
-#define RCC_C2APB2ENR_TIM16EN_Msk          (0x1UL << RCC_C2APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
-#define RCC_C2APB2ENR_TIM16EN              RCC_C2APB2ENR_TIM16EN_Msk
-#define RCC_C2APB2ENR_TIM17EN_Pos          (18U)
-#define RCC_C2APB2ENR_TIM17EN_Msk          (0x1UL << RCC_C2APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
-#define RCC_C2APB2ENR_TIM17EN              RCC_C2APB2ENR_TIM17EN_Msk
-#define RCC_C2APB2ENR_SAI1EN_Pos           (21U)
-#define RCC_C2APB2ENR_SAI1EN_Msk           (0x1UL << RCC_C2APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
-#define RCC_C2APB2ENR_SAI1EN               RCC_C2APB2ENR_SAI1EN_Msk
-
-/********************  Bit definition for RCC_C2APB3ENR register  **************/
-#define RCC_C2APB3ENR_SUBGHZSPIEN_Pos      (0U)
-#define RCC_C2APB3ENR_SUBGHZSPIEN_Msk      (0x1UL << RCC_C2APB3ENR_SUBGHZSPIEN_Pos)/*!< 0x00000001 */
-#define RCC_C2APB3ENR_SUBGHZSPIEN          RCC_C2APB3ENR_SUBGHZSPIEN_Msk
-
-/********************  Bit definition for RCC_C2AHB1SMENR register  ****************/
-#define RCC_C2AHB1SMENR_DMA1SMEN_Pos       (0U)
-#define RCC_C2AHB1SMENR_DMA1SMEN_Msk       (0x1UL << RCC_C2AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
-#define RCC_C2AHB1SMENR_DMA1SMEN           RCC_C2AHB1SMENR_DMA1SMEN_Msk
-#define RCC_C2AHB1SMENR_DMA2SMEN_Pos       (1U)
-#define RCC_C2AHB1SMENR_DMA2SMEN_Msk       (0x1UL << RCC_C2AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
-#define RCC_C2AHB1SMENR_DMA2SMEN           RCC_C2AHB1SMENR_DMA2SMEN_Msk
-#define RCC_C2AHB1SMENR_DMAMUX1SMEN_Pos    (2U)
-#define RCC_C2AHB1SMENR_DMAMUX1SMEN_Msk    (0x1UL << RCC_C2AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
-#define RCC_C2AHB1SMENR_DMAMUX1SMEN        RCC_C2AHB1SMENR_DMAMUX1SMEN_Msk
-#define RCC_C2AHB1SMENR_CRCSMEN_Pos        (12U)
-#define RCC_C2AHB1SMENR_CRCSMEN_Msk        (0x1UL << RCC_C2AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
-#define RCC_C2AHB1SMENR_CRCSMEN            RCC_C2AHB1SMENR_CRCSMEN_Msk
-
-/********************  Bit definition for RCC_C2AHB2SMENR register  ***************/
-#define RCC_C2AHB2SMENR_GPIOASMEN_Pos      (0U)
-#define RCC_C2AHB2SMENR_GPIOASMEN_Msk      (0x1UL << RCC_C2AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
-#define RCC_C2AHB2SMENR_GPIOASMEN          RCC_C2AHB2SMENR_GPIOASMEN_Msk
-#define RCC_C2AHB2SMENR_GPIOBSMEN_Pos      (1U)
-#define RCC_C2AHB2SMENR_GPIOBSMEN_Msk      (0x1UL << RCC_C2AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
-#define RCC_C2AHB2SMENR_GPIOBSMEN          RCC_C2AHB2SMENR_GPIOBSMEN_Msk
-#define RCC_C2AHB2SMENR_GPIOCSMEN_Pos      (2U)
-#define RCC_C2AHB2SMENR_GPIOCSMEN_Msk      (0x1UL << RCC_C2AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
-#define RCC_C2AHB2SMENR_GPIOCSMEN          RCC_C2AHB2SMENR_GPIOCSMEN_Msk
-#define RCC_C2AHB2SMENR_GPIOHSMEN_Pos      (7U)
-#define RCC_C2AHB2SMENR_GPIOHSMEN_Msk      (0x1UL << RCC_C2AHB2SMENR_GPIOHSMEN_Pos)/*!< 0x00000080 */
-#define RCC_C2AHB2SMENR_GPIOHSMEN          RCC_C2AHB2SMENR_GPIOHSMEN_Msk
-
-/********************  Bit definition for RCC_C2AHB3SMENR register  ***************/
-#define RCC_C2AHB3SMENR_PKASMEN_Pos        (16U)
-#define RCC_C2AHB3SMENR_PKASMEN_Msk        (0x1UL << RCC_C2AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */
-#define RCC_C2AHB3SMENR_PKASMEN            RCC_C2AHB3SMENR_PKASMEN_Msk
-#define RCC_C2AHB3SMENR_AESSMEN_Pos        (17U)
-#define RCC_C2AHB3SMENR_AESSMEN_Msk        (0x1UL << RCC_C2AHB3SMENR_AESSMEN_Pos)/*!< 0x00020000 */
-#define RCC_C2AHB3SMENR_AESSMEN            RCC_C2AHB3SMENR_AESSMEN_Msk
-#define RCC_C2AHB3SMENR_RNGSMEN_Pos        (18U)
-#define RCC_C2AHB3SMENR_RNGSMEN_Msk        (0x1UL << RCC_C2AHB3SMENR_RNGSMEN_Pos)/*!< 0x00040000 */
-#define RCC_C2AHB3SMENR_RNGSMEN            RCC_C2AHB3SMENR_RNGSMEN_Msk
-#define RCC_C2AHB3SMENR_SRAM1SMEN_Pos      (23U)
-#define RCC_C2AHB3SMENR_SRAM1SMEN_Msk      (0x1UL << RCC_C2AHB3SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
-#define RCC_C2AHB3SMENR_SRAM1SMEN          RCC_C2AHB3SMENR_SRAM1SMEN_Msk
-#define RCC_C2AHB3SMENR_SRAM2SMEN_Pos      (24U)
-#define RCC_C2AHB3SMENR_SRAM2SMEN_Msk      (0x1UL << RCC_C2AHB3SMENR_SRAM2SMEN_Pos)/*!< 0x01000000 */
-#define RCC_C2AHB3SMENR_SRAM2SMEN           RCC_C2AHB3SMENR_SRAM2SMEN_Msk
-#define RCC_C2AHB3SMENR_FLASHSMEN_Pos      (25U)
-#define RCC_C2AHB3SMENR_FLASHSMEN_Msk      (0x1UL << RCC_C2AHB3SMENR_FLASHSMEN_Pos)/*!< 0x02000000 */
-#define RCC_C2AHB3SMENR_FLASHSMEN           RCC_C2AHB3SMENR_FLASHSMEN_Msk
-
-/********************  Bit definition for RCC_C2APB1SMENR1 register  **************/
-#define RCC_C2APB1SMENR1_TIM2SMEN_Pos      (0U)
-#define RCC_C2APB1SMENR1_TIM2SMEN_Msk      (0x1UL << RCC_C2APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
-#define RCC_C2APB1SMENR1_TIM2SMEN          RCC_C2APB1SMENR1_TIM2SMEN_Msk
-#define RCC_C2APB1SMENR1_RTCAPBSMEN_Pos    (10U)
-#define RCC_C2APB1SMENR1_RTCAPBSMEN_Msk    (0x1UL << RCC_C2APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
-#define RCC_C2APB1SMENR1_RTCAPBSMEN        RCC_C2APB1SMENR1_RTCAPBSMEN_Msk
-#define RCC_C2APB1SMENR1_SPI2SMEN_Pos      (14U)
-#define RCC_C2APB1SMENR1_SPI2SMEN_Msk      (0x1UL << RCC_C2APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
-#define RCC_C2APB1SMENR1_SPI2SMEN          RCC_C2APB1SMENR1_SPI2SMEN_Msk
-#define RCC_C2APB1SMENR1_USART2SMEN_Pos    (17U)
-#define RCC_C2APB1SMENR1_USART2SMEN_Msk    (0x1UL << RCC_C2APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
-#define RCC_C2APB1SMENR1_USART2SMEN        RCC_C2APB1SMENR1_USART2SMEN_Msk
-#define RCC_C2APB1SMENR1_I2C1SMEN_Pos      (21U)
-#define RCC_C2APB1SMENR1_I2C1SMEN_Msk      (0x1UL << RCC_C2APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
-#define RCC_C2APB1SMENR1_I2C1SMEN          RCC_C2APB1SMENR1_I2C1SMEN_Msk
-#define RCC_C2APB1SMENR1_I2C2SMEN_Pos      (22U)
-#define RCC_C2APB1SMENR1_I2C2SMEN_Msk      (0x1UL << RCC_C2APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
-#define RCC_C2APB1SMENR1_I2C2SMEN          RCC_C2APB1SMENR1_I2C2SMEN_Msk
-#define RCC_C2APB1SMENR1_I2C3SMEN_Pos      (23U)
-#define RCC_C2APB1SMENR1_I2C3SMEN_Msk      (0x1UL << RCC_C2APB1SMENR1_I2C3SMEN_Pos)/*!< 0x00800000 */
-#define RCC_C2APB1SMENR1_I2C3SMEN          RCC_C2APB1SMENR1_I2C3SMEN_Msk
-#define RCC_C2APB1SMENR1_DACSMEN_Pos       (29U)
-#define RCC_C2APB1SMENR1_DACSMEN_Msk       (0x1UL << RCC_C2APB1SMENR1_DACSMEN_Pos)/*!< 0x20000000 */
-#define RCC_C2APB1SMENR1_DACSMEN           RCC_C2APB1SMENR1_DACSMEN_Msk
-#define RCC_C2APB1SMENR1_LPTIM1SMEN_Pos    (31U)
-#define RCC_C2APB1SMENR1_LPTIM1SMEN_Msk    (0x1UL << RCC_C2APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
-#define RCC_C2APB1SMENR1_LPTIM1SMEN        RCC_C2APB1SMENR1_LPTIM1SMEN_Msk
-
-/********************  Bit definition for RCC_C2APB1SMENR2 register  **************/
-#define RCC_C2APB1SMENR2_LPUART1SMEN_Pos    (0U)
-#define RCC_C2APB1SMENR2_LPUART1SMEN_Msk    (0x1UL << RCC_C2APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
-#define RCC_C2APB1SMENR2_LPUART1SMEN        RCC_C2APB1SMENR2_LPUART1SMEN_Msk
-#define RCC_C2APB1SMENR2_LPTIM2SMEN_Pos     (5U)
-#define RCC_C2APB1SMENR2_LPTIM2SMEN_Msk     (0x1UL << RCC_C2APB1SMENR2_LPTIM2SMEN_Pos)/*!< 0x00000020 */
-#define RCC_C2APB1SMENR2_LPTIM2SMEN         RCC_C2APB1SMENR2_LPTIM2SMEN_Msk
-#define RCC_C2APB1SMENR2_LPTIM3SMEN_Pos     (6U)
-#define RCC_C2APB1SMENR2_LPTIM3SMEN_Msk     (0x1UL << RCC_C2APB1SMENR2_LPTIM3SMEN_Pos)/*!< 0x00000040 */
-#define RCC_C2APB1SMENR2_LPTIM3SMEN         RCC_C2APB1SMENR2_LPTIM3SMEN_Msk
-
-/********************  Bit definition for RCC_C2APB2SMENR register  **************/
-#define RCC_C2APB2SMENR_ADCSMEN_Pos        (9U)
-#define RCC_C2APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_C2APB2SMENR_ADCSMEN_Pos)/*!< 0x00000200 */
-#define RCC_C2APB2SMENR_ADCSMEN            RCC_C2APB2SMENR_ADCSMEN_Msk
-#define RCC_C2APB2SMENR_TIM1SMEN_Pos       (11U)
-#define RCC_C2APB2SMENR_TIM1SMEN_Msk       (0x1UL << RCC_C2APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
-#define RCC_C2APB2SMENR_TIM1SMEN           RCC_C2APB2SMENR_TIM1SMEN_Msk
-#define RCC_C2APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_C2APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_C2APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
-#define RCC_C2APB2SMENR_SPI1SMEN           RCC_C2APB2SMENR_SPI1SMEN_Msk
-#define RCC_C2APB2SMENR_USART1SMEN_Pos     (14U)
-#define RCC_C2APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_C2APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
-#define RCC_C2APB2SMENR_USART1SMEN         RCC_C2APB2SMENR_USART1SMEN_Msk
-#define RCC_C2APB2SMENR_TIM16SMEN_Pos      (17U)
-#define RCC_C2APB2SMENR_TIM16SMEN_Msk      (0x1UL << RCC_C2APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
-#define RCC_C2APB2SMENR_TIM16SMEN          RCC_C2APB2SMENR_TIM16SMEN_Msk
-#define RCC_C2APB2SMENR_TIM17SMEN_Pos      (18U)
-#define RCC_C2APB2SMENR_TIM17SMEN_Msk      (0x1UL << RCC_C2APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
-#define RCC_C2APB2SMENR_TIM17SMEN          RCC_C2APB2SMENR_TIM17SMEN_Msk
-
-/********************  Bit definition for RCC_C2APB3SMENR register  **************/
-#define RCC_C2APB3SMENR_SUBGHZSPISMEN_Pos  (0U)
-#define RCC_C2APB3SMENR_SUBGHZSPISMEN_Msk  (0x1UL << RCC_C2APB3SMENR_SUBGHZSPISMEN_Pos)/*!< 0x00000001 */
-#define RCC_C2APB3SMENR_SUBGHZSPISMEN      RCC_C2APB3SMENR_SUBGHZSPISMEN_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions
- */
-#define RNG_VER_3_2
-
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos         (2U)
-#define RNG_CR_RNGEN_Msk         (0x1UL << RNG_CR_RNGEN_Pos)                   /*!< 0x00000004 */
-#define RNG_CR_RNGEN             RNG_CR_RNGEN_Msk
-#define RNG_CR_IE_Pos            (3U)
-#define RNG_CR_IE_Msk            (0x1UL << RNG_CR_IE_Pos)                      /*!< 0x00000008 */
-#define RNG_CR_IE                RNG_CR_IE_Msk
-#define RNG_CR_CED_Pos           (5U)
-#define RNG_CR_CED_Msk           (0x1UL << RNG_CR_CED_Pos)                     /*!< 0x00000020 */
-#define RNG_CR_CED               RNG_CR_CED_Msk
-#define RNG_CR_RNG_CONFIG3_Pos   (8U)
-#define RNG_CR_RNG_CONFIG3_Msk   (0xFUL << RNG_CR_RNG_CONFIG3_Pos)              /*!< 0x00000F00 */
-#define RNG_CR_RNG_CONFIG3       RNG_CR_RNG_CONFIG3_Msk
-#define RNG_CR_NISTC_Pos         (12U)
-#define RNG_CR_NISTC_Msk         (0x1UL << RNG_CR_NISTC_Pos)                   /*!< 0x00001000 */
-#define RNG_CR_NISTC             RNG_CR_NISTC_Msk
-#define RNG_CR_RNG_CONFIG2_Pos   (13U)
-#define RNG_CR_RNG_CONFIG2_Msk   (0x7UL << RNG_CR_RNG_CONFIG2_Pos)              /*!< 0x0000E000 */
-#define RNG_CR_RNG_CONFIG2       RNG_CR_RNG_CONFIG2_Msk
-#define RNG_CR_CLKDIV_Pos        (16U)
-#define RNG_CR_CLKDIV_Msk        (0xFUL << RNG_CR_CLKDIV_Pos)                  /*!< 0x000F0000 */
-#define RNG_CR_CLKDIV            RNG_CR_CLKDIV_Msk
-#define RNG_CR_CLKDIV_0          (0x1UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00010000 */
-#define RNG_CR_CLKDIV_1          (0x2UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00020000 */
-#define RNG_CR_CLKDIV_2          (0x4UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00040000 */
-#define RNG_CR_CLKDIV_3          (0x8UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00080000 */
-#define RNG_CR_RNG_CONFIG1_Pos   (20U)
-#define RNG_CR_RNG_CONFIG1_Msk   (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)             /*!< 0x03F00000 */
-#define RNG_CR_RNG_CONFIG1       RNG_CR_RNG_CONFIG1_Msk
-#define RNG_CR_CONDRST_Pos       (30U)
-#define RNG_CR_CONDRST_Msk       (0x1UL << RNG_CR_CONDRST_Pos)                 /*!< 0x40000000 */
-#define RNG_CR_CONDRST           RNG_CR_CONDRST_Msk
-#define RNG_CR_CONFIGLOCK_Pos    (31U)
-#define RNG_CR_CONFIGLOCK_Msk    (0x1UL << RNG_CR_CONFIGLOCK_Pos)              /*!< 0x80000000 */
-#define RNG_CR_CONFIGLOCK        RNG_CR_CONFIGLOCK_Msk
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)
-#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk
-#define RNG_SR_CECS_Pos     (1U)
-#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk
-#define RNG_SR_SECS_Pos     (2U)
-#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk
-#define RNG_SR_CEIS_Pos     (5U)
-#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk
-#define RNG_SR_SEIS_Pos     (6U)
-#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk
-
-/********************  Bits definition for RNG_DR register  *******************/
-#define RNG_DR_RNDATA_Pos        (0U)
-#define RNG_DR_RNDATA_Msk        (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos)       /*!< 0xFFFFFFFF */
-#define RNG_DR_RNDATA            RNG_DR_RNDATA_Msk
-
-/********************  Bits definition for RNG_HTCR register  *****************/
-#define RNG_HTCR_HTCFG_Pos       (0U)
-#define RNG_HTCR_HTCFG_Msk       (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)      /*!< 0xFFFFFFFF */
-#define RNG_HTCR_HTCFG           RNG_HTCR_HTCFG_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                (22U)
-#define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
-#define RTC_TR_PM                    RTC_TR_PM_Msk
-#define RTC_TR_HT_Pos                (20U)
-#define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
-#define RTC_TR_HT                    RTC_TR_HT_Msk
-#define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
-#define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                (16U)
-#define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
-#define RTC_TR_HU                    RTC_TR_HU_Msk
-#define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
-#define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
-#define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
-#define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos               (12U)
-#define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
-#define RTC_TR_MNT                   RTC_TR_MNT_Msk
-#define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
-#define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
-#define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos               (8U)
-#define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
-#define RTC_TR_MNU                   RTC_TR_MNU_Msk
-#define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
-#define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
-#define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
-#define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                (4U)
-#define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
-#define RTC_TR_ST                    RTC_TR_ST_Msk
-#define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
-#define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
-#define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                (0U)
-#define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
-#define RTC_TR_SU                    RTC_TR_SU_Msk
-#define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
-#define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
-#define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
-#define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                (20U)
-#define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
-#define RTC_DR_YT                    RTC_DR_YT_Msk
-#define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
-#define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
-#define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
-#define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                (16U)
-#define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
-#define RTC_DR_YU                    RTC_DR_YU_Msk
-#define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
-#define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
-#define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
-#define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos               (13U)
-#define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
-#define RTC_DR_WDU                   RTC_DR_WDU_Msk
-#define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
-#define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
-#define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                (12U)
-#define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
-#define RTC_DR_MT                    RTC_DR_MT_Msk
-#define RTC_DR_MU_Pos                (8U)
-#define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
-#define RTC_DR_MU                    RTC_DR_MU_Msk
-#define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
-#define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
-#define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
-#define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                (4U)
-#define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
-#define RTC_DR_DT                    RTC_DR_DT_Msk
-#define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
-#define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                (0U)
-#define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
-#define RTC_DR_DU                    RTC_DR_DU_Msk
-#define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
-#define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
-#define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
-#define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos               (0U)
-#define RTC_SSR_SS_Msk               (0xFFFFFFFFUL << RTC_SSR_SS_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_SSR_SS                   RTC_SSR_SS_Msk
-
-/********************  Bits definition for RTC_ICSR register  ******************/
-#define RTC_ICSR_RECALPF_Pos         (16U)
-#define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
-#define RTC_ICSR_BCDU_Pos            (10U)
-#define RTC_ICSR_BCDU_Msk            (0x7UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00001C00 */
-#define RTC_ICSR_BCDU                RTC_ICSR_BCDU_Msk
-#define RTC_ICSR_BCDU_0              (0x1UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00000400 */
-#define RTC_ICSR_BCDU_1              (0x2UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00000800 */
-#define RTC_ICSR_BCDU_2              (0x4UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00001000 */
-#define RTC_ICSR_BIN_Pos             (8U)
-#define RTC_ICSR_BIN_Msk             (0x3UL << RTC_ICSR_BIN_Pos)               /*!< 0x00000300 */
-#define RTC_ICSR_BIN                 RTC_ICSR_BIN_Msk
-#define RTC_ICSR_BIN_0               (0x1UL << RTC_ICSR_BIN_Pos)               /*!< 0x00000100 */
-#define RTC_ICSR_BIN_1               (0x2UL << RTC_ICSR_BIN_Pos)               /*!< 0x00000200 */
-#define RTC_ICSR_INIT_Pos            (7U)
-#define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
-#define RTC_ICSR_INITF_Pos           (6U)
-#define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
-#define RTC_ICSR_RSF_Pos             (5U)
-#define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
-#define RTC_ICSR_INITS_Pos           (4U)
-#define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
-#define RTC_ICSR_SHPF_Pos            (3U)
-#define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
-#define RTC_ICSR_WUTWF_Pos           (2U)
-#define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos        (16U)
-#define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
-#define RTC_PRER_PREDIV_S_Pos        (0U)
-#define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUTOCLR_Pos         (16U)
-#define RTC_WUTR_WUTOCLR_Msk         (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)        /*!< 0x0000FFFF */
-#define RTC_WUTR_WUTOCLR             RTC_WUTR_WUTOCLR_Msk
-#define RTC_WUTR_WUT_Pos             (0U)
-#define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_OUT2EN_Pos            (31U)
-#define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
-#define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */
-#define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
-#define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
-#define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */
-#define RTC_CR_TAMPALRM_PU_Pos       (29U)
-#define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
-#define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */
-#define RTC_CR_TAMPOE_Pos            (26U)
-#define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
-#define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */
-#define RTC_CR_TAMPTS_Pos            (25U)
-#define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
-#define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */
-#define RTC_CR_ITSE_Pos              (24U)
-#define RTC_CR_ITSE_Msk              (0x1UL << RTC_CR_ITSE_Pos)                /*!< 0x01000000 */
-#define RTC_CR_ITSE                  RTC_CR_ITSE_Msk                           /*!<Timestamp on internal event enable  */
-#define RTC_CR_COE_Pos               (23U)
-#define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
-#define RTC_CR_COE                   RTC_CR_COE_Msk
-#define RTC_CR_OSEL_Pos              (21U)
-#define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
-#define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
-#define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
-#define RTC_CR_POL_Pos               (20U)
-#define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
-#define RTC_CR_POL                   RTC_CR_POL_Msk
-#define RTC_CR_COSEL_Pos             (19U)
-#define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
-#define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
-#define RTC_CR_BKP_Pos               (18U)
-#define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                 /*!< 0x00040000 */
-#define RTC_CR_BKP                   RTC_CR_BKP_Msk
-#define RTC_CR_SUB1H_Pos             (17U)
-#define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
-#define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
-#define RTC_CR_ADD1H_Pos             (16U)
-#define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
-#define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
-#define RTC_CR_TSIE_Pos              (15U)
-#define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
-#define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
-#define RTC_CR_WUTIE_Pos             (14U)
-#define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
-#define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
-#define RTC_CR_ALRBIE_Pos            (13U)
-#define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
-#define RTC_CR_ALRAIE_Pos            (12U)
-#define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
-#define RTC_CR_TSE_Pos               (11U)
-#define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
-#define RTC_CR_TSE                   RTC_CR_TSE_Msk
-#define RTC_CR_WUTE_Pos              (10U)
-#define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
-#define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
-#define RTC_CR_ALRBE_Pos             (9U)
-#define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
-#define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
-#define RTC_CR_ALRAE_Pos             (8U)
-#define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
-#define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
-#define RTC_CR_SSRUIE_Pos            (7U)
-#define RTC_CR_SSRUIE_Msk            (0x1UL << RTC_CR_SSRUIE_Pos)              /*!< 0x00000080 */
-#define RTC_CR_SSRUIE                RTC_CR_SSRUIE_Msk
-#define RTC_CR_FMT_Pos               (6U)
-#define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
-#define RTC_CR_FMT                   RTC_CR_FMT_Msk
-#define RTC_CR_BYPSHAD_Pos           (5U)
-#define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
-#define RTC_CR_REFCKON_Pos           (4U)
-#define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
-#define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
-#define RTC_CR_TSEDGE_Pos            (3U)
-#define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
-#define RTC_CR_WUCKSEL_Pos           (0U)
-#define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
-#define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos              (0U)
-#define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
-#define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos            (15U)
-#define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
-#define RTC_CALR_CALP                RTC_CALR_CALP_Msk
-#define RTC_CALR_CALW8_Pos           (14U)
-#define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
-#define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
-#define RTC_CALR_CALW16_Pos          (13U)
-#define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
-#define RTC_CALR_LPCAL               RTC_CALR_LPCAL_Msk
-#define RTC_CALR_LPCAL_Pos           (12U)
-#define RTC_CALR_LPCAL_Msk           (0x1UL << RTC_CALR_LPCAL_Pos)             /*!< 0x00001000 */
-#define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
-#define RTC_CALR_CALM_Pos            (0U)
-#define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
-#define RTC_CALR_CALM                RTC_CALR_CALM_Msk
-#define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
-#define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
-#define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
-#define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
-#define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
-#define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
-#define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
-#define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
-#define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_ADD1S_Pos         (31U)
-#define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
-#define RTC_SHIFTR_SUBFS_Pos         (0U)
-#define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos              (22U)
-#define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
-#define RTC_TSTR_PM                  RTC_TSTR_PM_Msk                           
-#define RTC_TSTR_HT_Pos              (20U)
-#define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
-#define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
-#define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos              (16U)
-#define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
-#define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
-#define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos             (12U)
-#define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
-#define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
-#define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos             (8U)
-#define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
-#define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos              (4U)
-#define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
-#define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
-#define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos              (0U)
-#define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
-#define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
-#define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos             (13U)
-#define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk                          
-#define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos              (12U)
-#define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
-#define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
-#define RTC_TSDR_MU_Pos              (8U)
-#define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
-#define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
-#define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos              (4U)
-#define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
-#define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
-#define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos              (0U)
-#define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
-#define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
-#define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos             (0U)
-#define RTC_TSSSR_SS_Msk             (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)        /*!< 0xFFFFFFFF */
-#define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk                          
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos          (31U)
-#define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
-#define RTC_ALRMAR_WDSEL_Pos         (30U)
-#define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
-#define RTC_ALRMAR_DT_Pos            (28U)
-#define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
-#define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos            (24U)
-#define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
-#define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos          (23U)
-#define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
-#define RTC_ALRMAR_PM_Pos            (22U)
-#define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
-#define RTC_ALRMAR_HT_Pos            (20U)
-#define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
-#define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos            (16U)
-#define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
-#define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos          (15U)
-#define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
-#define RTC_ALRMAR_MNT_Pos           (12U)
-#define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
-#define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos           (8U)
-#define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
-#define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos          (7U)
-#define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
-#define RTC_ALRMAR_ST_Pos            (4U)
-#define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
-#define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos            (0U)
-#define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
-#define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_SSCLR_Pos       (31U)
-#define RTC_ALRMASSR_SSCLR_Msk       (0x1UL << RTC_ALRMASSR_SSCLR_Pos)         /*!< 0x80000000 */
-#define RTC_ALRMASSR_SSCLR           RTC_ALRMASSR_SSCLR_Msk
-#define RTC_ALRMASSR_MASKSS_Pos      (24U)
-#define RTC_ALRMASSR_MASKSS_Msk      (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
-#define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMASSR_MASKSS_4        (0x10UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMASSR_MASKSS_5        (0x20UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos          (0U)
-#define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos          (31U)
-#define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
-#define RTC_ALRMBR_WDSEL_Pos         (30U)
-#define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
-#define RTC_ALRMBR_DT_Pos            (28U)
-#define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
-#define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos            (24U)
-#define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
-#define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos          (23U)
-#define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
-#define RTC_ALRMBR_PM_Pos            (22U)
-#define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
-#define RTC_ALRMBR_HT_Pos            (20U)
-#define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
-#define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos            (16U)
-#define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
-#define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos          (15U)
-#define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
-#define RTC_ALRMBR_MNT_Pos           (12U)
-#define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
-#define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos           (8U)
-#define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
-#define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos          (7U)
-#define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
-#define RTC_ALRMBR_ST_Pos            (4U)
-#define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
-#define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos            (0U)
-#define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
-#define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_SSCLR_Pos       (31U)
-#define RTC_ALRMBSSR_SSCLR_Msk       (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)         /*!< 0x80000000 */
-#define RTC_ALRMBSSR_SSCLR           RTC_ALRMBSSR_SSCLR_Msk
-#define RTC_ALRMBSSR_MASKSS_Pos      (24U)
-#define RTC_ALRMBSSR_MASKSS_Msk      (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
-#define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMBSSR_MASKSS_4        (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBSSR_MASKSS_5        (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBSSR_SS_Pos          (0U)
-#define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
-
-/********************  Bits definition for RTC_SR register  *******************/
-#define RTC_SR_SSRUF_Pos             (6U)
-#define RTC_SR_SSRUF_Msk             (0x1UL << RTC_SR_SSRUF_Pos)               /*!< 0x00000040 */
-#define RTC_SR_SSRUF                 RTC_SR_SSRUF_Msk
-#define RTC_SR_ITSF_Pos              (5U)
-#define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                /*!< 0x00000020 */
-#define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
-#define RTC_SR_TSOVF_Pos             (4U)
-#define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */
-#define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk
-#define RTC_SR_TSF_Pos               (3U)
-#define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */
-#define RTC_SR_TSF                   RTC_SR_TSF_Msk
-#define RTC_SR_WUTF_Pos              (2U)
-#define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                /*!< 0x00000004 */
-#define RTC_SR_WUTF                  RTC_SR_WUTF_Msk
-#define RTC_SR_ALRBF_Pos             (1U)
-#define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)               /*!< 0x00000002 */
-#define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
-#define RTC_SR_ALRAF_Pos             (0U)
-#define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */
-#define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
-
-/********************  Bits definition for RTC_MISR register  *****************/
-#define RTC_MISR_SSRUMF_Pos          (6U)
-#define RTC_MISR_SSRUMF_Msk          (0x1UL << RTC_MISR_SSRUMF_Pos)            /*!< 0x00000040 */
-#define RTC_MISR_SSRUMF              RTC_MISR_SSRUMF_Msk
-#define RTC_MISR_ITSMF_Pos           (5U)
-#define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)             /*!< 0x00000020 */
-#define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
-#define RTC_MISR_TSOVMF_Pos          (4U)
-#define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */
-#define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk
-#define RTC_MISR_TSMF_Pos            (3U)
-#define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */
-#define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk
-#define RTC_MISR_WUTMF_Pos           (2U)
-#define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)             /*!< 0x00000004 */
-#define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk
-#define RTC_MISR_ALRBMF_Pos          (1U)
-#define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)            /*!< 0x00000002 */
-#define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
-#define RTC_MISR_ALRAMF_Pos          (0U)
-#define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */
-#define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
-
-/********************  Bits definition for RTC_SCR register  ******************/
-#define RTC_SCR_CSSRUF_Pos           (6U)
-#define RTC_SCR_CSSRUF_Msk           (0x1UL << RTC_SCR_CSSRUF_Pos)             /*!< 0x00000040 */
-#define RTC_SCR_CSSRUF               RTC_SCR_CSSRUF_Msk
-#define RTC_SCR_CITSF_Pos            (5U)
-#define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)              /*!< 0x00000020 */
-#define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
-#define RTC_SCR_CTSOVF_Pos           (4U)
-#define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */
-#define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk
-#define RTC_SCR_CTSF_Pos             (3U)
-#define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */
-#define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk
-#define RTC_SCR_CWUTF_Pos            (2U)
-#define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)              /*!< 0x00000004 */
-#define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk
-#define RTC_SCR_CALRBF_Pos           (1U)
-#define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)             /*!< 0x00000002 */
-#define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
-#define RTC_SCR_CALRAF_Pos           (0U)
-#define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */
-#define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
-
-/********************  Bits definition for RTC_ALRABINR register  ******************/
-#define RTC_ALRABINR_SS_Pos          (0U)
-#define RTC_ALRABINR_SS_Msk          (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)     /*!< 0xFFFFFFFF */
-#define RTC_ALRABINR_SS              RTC_ALRABINR_SS_Msk
-
-/********************  Bits definition for RTC_ALRBBINR register  ******************/
-#define RTC_ALRBBINR_SS_Pos          (0U)
-#define RTC_ALRBBINR_SS_Msk          (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)     /*!< 0xFFFFFFFF */
-#define RTC_ALRBBINR_SS              RTC_ALRBBINR_SS_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
-#define SPI_CR1_CPOL_Pos            (1U)
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
-#define SPI_CR1_MSTR_Pos            (2U)
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
-
-#define SPI_CR1_BR_Pos              (3U)
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos             (6U)
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
-#define SPI_CR1_LSBFIRST_Pos        (7U)
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
-#define SPI_CR1_SSI_Pos             (8U)
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
-#define SPI_CR1_SSM_Pos             (9U)
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
-#define SPI_CR1_RXONLY_Pos          (10U)
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
-#define SPI_CR1_CRCL_Pos            (11U)
-#define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
-#define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
-#define SPI_CR1_CRCNEXT_Pos         (12U)
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
-#define SPI_CR1_CRCEN_Pos           (13U)
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
-#define SPI_CR1_BIDIOE_Pos          (14U)
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_NSSP_Pos            (3U)
-#define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
-#define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
-#define SPI_CR2_FRF_Pos             (4U)
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-#define SPI_CR2_DS_Pos              (8U)
-#define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
-#define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
-#define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
-#define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
-#define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
-#define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
-#define SPI_CR2_FRXTH_Pos           (12U)
-#define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
-#define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
-#define SPI_CR2_LDMARX_Pos          (13U)
-#define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
-#define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
-#define SPI_CR2_LDMATX_Pos          (14U)
-#define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
-#define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
-#define SPI_SR_FRLVL_Pos            (9U)
-#define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
-#define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
-#define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
-#define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
-#define SPI_SR_FTLVL_Pos            (11U)
-#define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
-#define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
-#define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
-#define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)            /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
-#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)         /*!< 0x00001000 */
-#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)           /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)               /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)             /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Tamper and backup register (TAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for TAMP_CR1 register  *****************/
-#define TAMP_CR1_TAMP1E_Pos          (0U)
-#define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */
-#define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
-#define TAMP_CR1_TAMP2E_Pos          (1U)
-#define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */
-#define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
-#define TAMP_CR1_TAMP3E_Pos          (2U)
-#define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */
-#define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk
-#define TAMP_CR1_ITAMP3E_Pos         (18U)
-#define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */
-#define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
-#define TAMP_CR1_ITAMP5E_Pos         (20U)
-#define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */
-#define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
-#define TAMP_CR1_ITAMP6E_Pos         (21U)
-#define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x0020000 */
-#define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
-#define TAMP_CR1_ITAMP8E_Pos         (23U)
-#define TAMP_CR1_ITAMP8E_Msk         (0x1UL << TAMP_CR1_ITAMP8E_Pos)           /*!< 0x00800000 */
-#define TAMP_CR1_ITAMP8E             TAMP_CR1_ITAMP8E_Msk
-
-/********************  Bits definition for TAMP_CR2 register  *****************/
-#define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
-#define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */
-#define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
-#define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
-#define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */
-#define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
-#define TAMP_CR2_TAMP3NOERASE_Pos    (2U)
-#define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */
-#define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk
-#define TAMP_CR2_TAMP1MSK_Pos        (16U)
-#define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)          /*!< 0x00010000 */
-#define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk
-#define TAMP_CR2_TAMP2MSK_Pos        (17U)
-#define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)          /*!< 0x00020000 */
-#define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk
-#define TAMP_CR2_TAMP3MSK_Pos        (18U)
-#define TAMP_CR2_TAMP3MSK_Msk        (0x1UL << TAMP_CR2_TAMP3MSK_Pos)          /*!< 0x00040000 */
-#define TAMP_CR2_TAMP3MSK            TAMP_CR2_TAMP3MSK_Msk
-#define TAMP_CR2_BKERASE_Pos         (23U)
-#define TAMP_CR2_BKERASE_Msk         (0x1UL << TAMP_CR2_BKERASE_Pos)           /*!< 0x00800000 */
-#define TAMP_CR2_BKERASE             TAMP_CR2_BKERASE_Msk
-#define TAMP_CR2_TAMP1TRG_Pos        (24U)
-#define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */
-#define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
-#define TAMP_CR2_TAMP2TRG_Pos        (25U)
-#define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */
-#define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
-#define TAMP_CR2_TAMP3TRG_Pos        (26U)
-#define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x02000000 */
-#define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk
-
-/********************  Bits definition for TAMP_CR3 register  *****************/
-#define TAMP_CR3_ITAMP3NOER_Pos      (2U)
-#define TAMP_CR3_ITAMP3NOER_Msk      (0x1UL << TAMP_CR3_ITAMP3NOER_Pos)        /*!< 0x00000004 */
-#define TAMP_CR3_ITAMP3NOER          TAMP_CR3_ITAMP3NOER_Msk
-#define TAMP_CR3_ITAMP5NOER_Pos      (4U)
-#define TAMP_CR3_ITAMP5NOER_Msk      (0x1UL << TAMP_CR3_ITAMP5NOER_Pos)        /*!< 0x00000010 */
-#define TAMP_CR3_ITAMP5NOER          TAMP_CR3_ITAMP5NOER_Msk
-#define TAMP_CR3_ITAMP6NOER_Pos      (5U)
-#define TAMP_CR3_ITAMP6NOER_Msk      (0x1UL << TAMP_CR3_ITAMP6NOER_Pos)        /*!< 0x00000020 */
-#define TAMP_CR3_ITAMP6NOER          TAMP_CR3_ITAMP6NOER_Msk
-#define TAMP_CR3_ITAMP8NOER_Pos      (7U)
-#define TAMP_CR3_ITAMP8NOER_Msk      (0x1UL << TAMP_CR3_ITAMP8NOER_Pos)        /*!< 0x00800000 */
-#define TAMP_CR3_ITAMP8NOER          TAMP_CR3_ITAMP8NOER_Msk
-
-/********************  Bits definition for TAMP_FLTCR register  ***************/
-#define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
-#define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000007 */
-#define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
-#define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000001 */
-#define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000002 */
-#define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000004 */
-#define TAMP_FLTCR_TAMPFLT_Pos       (3U)
-#define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000018 */
-#define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
-#define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000008 */
-#define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000010 */
-#define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
-#define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000060 */
-#define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
-#define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000020 */
-#define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000040 */
-#define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
-#define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)       /*!< 0x00000080 */
-#define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
-
-/********************  Bits definition for TAMP_IER register  *****************/
-#define TAMP_IER_TAMP1IE_Pos         (0U)
-#define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */
-#define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
-#define TAMP_IER_TAMP2IE_Pos         (1U)
-#define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */
-#define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
-#define TAMP_IER_TAMP3IE_Pos         (2U)
-#define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */
-#define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk
-#define TAMP_IER_ITAMP3IE_Pos        (18U)
-#define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */
-#define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
-#define TAMP_IER_ITAMP5IE_Pos        (20U)
-#define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */
-#define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
-#define TAMP_IER_ITAMP6IE_Pos        (21U)
-#define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x0020000 */
-#define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
-#define TAMP_IER_ITAMP8IE_Pos        (23U)
-#define TAMP_IER_ITAMP8IE_Msk        (0x1UL << TAMP_IER_ITAMP8IE_Pos)          /*!< 0x00800000 */
-#define TAMP_IER_ITAMP8IE            TAMP_IER_ITAMP8IE_Msk
-
-/********************  Bits definition for TAMP_SR register  *****************/
-#define TAMP_SR_TAMP1F_Pos           (0U)
-#define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)             /*!< 0x00000001 */
-#define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
-#define TAMP_SR_TAMP2F_Pos           (1U)
-#define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)            /*!< 0x00000002 */
-#define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
-#define TAMP_SR_TAMP3F_Pos           (2U)
-#define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)             /*!< 0x00000004 */
-#define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk
-#define TAMP_SR_ITAMP3F_Pos          (18U)
-#define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)           /*!< 0x00040000 */
-#define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
-#define TAMP_SR_ITAMP5F_Pos          (20U)
-#define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)           /*!< 0x00100000 */
-#define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
-#define TAMP_SR_ITAMP6F_Pos          (21U)
-#define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)           /*!< 0x0020000 */
-#define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
-#define TAMP_SR_ITAMP8F_Pos          (23U)
-#define TAMP_SR_ITAMP8F_Msk          (0x1UL << TAMP_SR_ITAMP8F_Pos)           /*!< 0x00800000 */
-#define TAMP_SR_ITAMP8F              TAMP_SR_ITAMP8F_Msk
-
-/********************  Bits definition for TAMP_MISR register  ************ *****/
-#define TAMP_MISR_TAMP1MF_Pos        (0U)
-#define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)          /*!< 0x00000001 */
-#define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
-#define TAMP_MISR_TAMP2MF_Pos        (1U)
-#define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)          /*!< 0x00000002 */
-#define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
-#define TAMP_MISR_TAMP3MF_Pos        (2U)
-#define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)          /*!< 0x00000004 */
-#define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk
-#define TAMP_MISR_ITAMP3MF_Pos       (18U)
-#define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)           /*!< 0x00040000 */
-#define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
-#define TAMP_MISR_ITAMP5MF_Pos       (20U)
-#define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)           /*!< 0x00100000 */
-#define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
-#define TAMP_MISR_ITAMP6MF_Pos       (21U)
-#define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)           /*!< 0x0020000 */
-#define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
-#define TAMP_MISR_ITAMP8MF_Pos       (23U)
-#define TAMP_MISR_ITAMP8MF_Msk       (0x1UL << TAMP_MISR_ITAMP8MF_Pos)           /*!< 0x00800000 */
-#define TAMP_MISR_ITAMP8MF           TAMP_MISR_ITAMP8MF_Msk
-
-/********************  Bits definition for TAMP_SMISR register  ************ *****/
-#define TAMP_SMISR_TAMP1MF_Pos       (0U)
-#define TAMP_SMISR_TAMP1MF_Msk       (0x1UL << TAMP_SMISR_TAMP1MF_Pos)         /*!< 0x00000001 */
-#define TAMP_SMISR_TAMP1MF           TAMP_SMISR_TAMP1MF_Msk
-#define TAMP_SMISR_TAMP2MF_Pos       (1U)
-#define TAMP_SMISR_TAMP2MF_Msk       (0x1UL << TAMP_SMISR_TAMP2MF_Pos)         /*!< 0x00000002 */
-#define TAMP_SMISR_TAMP2MF           TAMP_SMISR_TAMP2MF_Msk
-#define TAMP_SMISR_TAMP3MF_Pos       (2U)
-#define TAMP_SMISR_TAMP3MF_Msk       (0x1UL << TAMP_SMISR_TAMP3MF_Pos)         /*!< 0x00000004 */
-#define TAMP_SMISR_TAMP3MF           TAMP_SMISR_TAMP3MF_Msk
-#define TAMP_SMISR_ITAMP3MF_Pos      (18U)
-#define TAMP_SMISR_ITAMP3MF_Msk      (0x1UL << TAMP_SMISR_ITAMP3MF_Pos)        /*!< 0x00040000 */
-#define TAMP_SMISR_ITAMP3MF          TAMP_SMISR_ITAMP3MF_Msk
-#define TAMP_SMISR_ITAMP5MF_Pos      (20U)
-#define TAMP_SMISR_ITAMP5MF_Msk      (0x1UL << TAMP_SMISR_ITAMP5MF_Pos)        /*!< 0x00100000 */
-#define TAMP_SMISR_ITAMP5MF          TAMP_SMISR_ITAMP5MF_Msk
-#define TAMP_SMISR_ITAMP6MF_Pos      (21U)
-#define TAMP_SMISR_ITAMP6MF_Msk      (0x1UL << TAMP_SMISR_ITAMP6MF_Pos)        /*!< 0x0020000 */
-#define TAMP_SMISR_ITAMP6MF          TAMP_SMISR_ITAMP6MF_Msk
-#define TAMP_SMISR_ITAMP8MF_Pos      (23U)
-#define TAMP_SMISR_ITAMP8MF_Msk      (0x1UL << TAMP_SMISR_ITAMP8MF_Pos)        /*!< 0x00800000 */
-#define TAMP_SMISR_ITAMP8MF          TAMP_SMISR_ITAMP8MF_Msk
-
-/********************  Bits definition for TAMP_SCR register  *****************/
-#define TAMP_SCR_CTAMP1F_Pos         (0U)
-#define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)           /*!< 0x00000001 */
-#define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
-#define TAMP_SCR_CTAMP2F_Pos         (1U)
-#define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)           /*!< 0x00000002 */
-#define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
-#define TAMP_SCR_CTAMP3F_Pos         (2U)
-#define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)           /*!< 0x00000004 */
-#define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk
-#define TAMP_SCR_CITAMP3F_Pos        (18U)
-#define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)          /*!< 0x00040000 */
-#define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
-#define TAMP_SCR_CITAMP5F_Pos        (20U)
-#define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)          /*!< 0x00100000 */
-#define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
-#define TAMP_SCR_CITAMP6F_Pos        (21U)
-#define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)          /*!< 0x0020000 */
-#define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
-#define TAMP_SCR_CITAMP8F_Pos        (23U)
-#define TAMP_SCR_CITAMP8F_Msk        (0x1UL << TAMP_SCR_CITAMP8F_Pos)          /*!< 0x00800000 */
-#define TAMP_SCR_CITAMP8F            TAMP_SCR_CITAMP8F_Msk
-
-/********************  Bits definition for TAMP_COUNTR register  ***************/
-#define TAMP_COUNTR_Pos               (0U)
-#define TAMP_COUNTR_Msk               (0xFFFFFFFFUL << TAMP_COUNTR_Pos)        /*!< 0xFFFFFFFF */
-#define TAMP_COUNTR                   TAMP_COUNTR_Msk
-
-/********************  Bits definition for TAMP_BKP0R register  ***************/
-#define TAMP_BKP0R_Pos               (0U)
-#define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP0R                   TAMP_BKP0R_Msk
-
-/********************  Bits definition for TAMP_BKP1R register  ****************/
-#define TAMP_BKP1R_Pos               (0U)
-#define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP1R                   TAMP_BKP1R_Msk
-
-/********************  Bits definition for TAMP_BKP2R register  ****************/
-#define TAMP_BKP2R_Pos               (0U)
-#define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP2R                   TAMP_BKP2R_Msk
-
-/********************  Bits definition for TAMP_BKP3R register  ****************/
-#define TAMP_BKP3R_Pos               (0U)
-#define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP3R                   TAMP_BKP3R_Msk
-
-/********************  Bits definition for TAMP_BKP4R register  ****************/
-#define TAMP_BKP4R_Pos               (0U)
-#define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP4R                   TAMP_BKP4R_Msk
-
-/********************  Bits definition for TAMP_BKP5R register  ****************/
-#define TAMP_BKP5R_Pos               (0U)
-#define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP5R                   TAMP_BKP5R_Msk
-
-/********************  Bits definition for TAMP_BKP6R register  ****************/
-#define TAMP_BKP6R_Pos               (0U)
-#define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP6R                   TAMP_BKP6R_Msk
-
-/********************  Bits definition for TAMP_BKP7R register  ****************/
-#define TAMP_BKP7R_Pos               (0U)
-#define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP7R                   TAMP_BKP7R_Msk
-
-/********************  Bits definition for TAMP_BKP8R register  ****************/
-#define TAMP_BKP8R_Pos               (0U)
-#define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP8R                   TAMP_BKP8R_Msk
-
-/********************  Bits definition for TAMP_BKP9R register  ****************/
-#define TAMP_BKP9R_Pos               (0U)
-#define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP9R                   TAMP_BKP9R_Msk
-
-/********************  Bits definition for TAMP_BKP10R register  ***************/
-#define TAMP_BKP10R_Pos              (0U)
-#define TAMP_BKP10R_Msk              (0xFFFFFFFFUL << TAMP_BKP10R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP10R                  TAMP_BKP10R_Msk
-
-/********************  Bits definition for TAMP_BKP11R register  ***************/
-#define TAMP_BKP11R_Pos              (0U)
-#define TAMP_BKP11R_Msk              (0xFFFFFFFFUL << TAMP_BKP11R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP11R                  TAMP_BKP11R_Msk
-
-/********************  Bits definition for TAMP_BKP12R register  ***************/
-#define TAMP_BKP12R_Pos              (0U)
-#define TAMP_BKP12R_Msk              (0xFFFFFFFFUL << TAMP_BKP12R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP12R                  TAMP_BKP12R_Msk
-
-/********************  Bits definition for TAMP_BKP13R register  ***************/
-#define TAMP_BKP13R_Pos              (0U)
-#define TAMP_BKP13R_Msk              (0xFFFFFFFFUL << TAMP_BKP13R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP13R                  TAMP_BKP13R_Msk
-
-/********************  Bits definition for TAMP_BKP14R register  ***************/
-#define TAMP_BKP14R_Pos              (0U)
-#define TAMP_BKP14R_Msk              (0xFFFFFFFFUL << TAMP_BKP14R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP14R                  TAMP_BKP14R_Msk
-
-/********************  Bits definition for TAMP_BKP15R register  ***************/
-#define TAMP_BKP15R_Pos              (0U)
-#define TAMP_BKP15R_Msk              (0xFFFFFFFFUL << TAMP_BKP15R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP15R                  TAMP_BKP15R_Msk
-
-/********************  Bits definition for TAMP_BKP16R register  ***************/
-#define TAMP_BKP16R_Pos              (0U)
-#define TAMP_BKP16R_Msk              (0xFFFFFFFFUL << TAMP_BKP16R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP16R                  TAMP_BKP16R_Msk
-
-/********************  Bits definition for TAMP_BKP17R register  ***************/
-#define TAMP_BKP17R_Pos              (0U)
-#define TAMP_BKP17R_Msk              (0xFFFFFFFFUL << TAMP_BKP17R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP17R                  TAMP_BKP17R_Msk
-
-/********************  Bits definition for TAMP_BKP18R register  ***************/
-#define TAMP_BKP18R_Pos              (0U)
-#define TAMP_BKP18R_Msk              (0xFFFFFFFFUL << TAMP_BKP18R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP18R                  TAMP_BKP18R_Msk
-
-/********************  Bits definition for TAMP_BKP19R register  ***************/
-#define TAMP_BKP19R_Pos              (0U)
-#define TAMP_BKP19R_Msk              (0xFFFFFFFFUL << TAMP_BKP19R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP19R                  TAMP_BKP19R_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  (SYSCFG memory remap register) ***********************************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos              (0U)
-#define SYSCFG_MEMRMP_MEM_MODE_Msk              (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000007 */
-#define SYSCFG_MEMRMP_MEM_MODE                  SYSCFG_MEMRMP_MEM_MODE_Msk                      /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0                (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1                (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_MEM_MODE_2                (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000004 */
-
-/*****************  Bit definition for SYSCFG_CFGR1 register  (SYSCFG configuration register 1) ****************************************************************/
-#define SYSCFG_CFGR1_BOOSTEN_Pos                (8U)
-#define SYSCFG_CFGR1_BOOSTEN_Msk                (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)             /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOSTEN                    SYSCFG_CFGR1_BOOSTEN_Msk                        /*!< I/O analog switch voltage booster enable                  */
-#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos            (16U)
-#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)         /*!< 0x00010000 */
-#define SYSCFG_CFGR1_I2C_PB6_FMP                SYSCFG_CFGR1_I2C_PB6_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB6 */
-#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos            (17U)
-#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)         /*!< 0x00020000 */
-#define SYSCFG_CFGR1_I2C_PB7_FMP                SYSCFG_CFGR1_I2C_PB7_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB7 */
-#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos            (18U)
-#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)         /*!< 0x00040000 */
-#define SYSCFG_CFGR1_I2C_PB8_FMP                SYSCFG_CFGR1_I2C_PB8_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB8 */
-#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos            (19U)
-#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)         /*!< 0x00080000 */
-#define SYSCFG_CFGR1_I2C_PB9_FMP                SYSCFG_CFGR1_I2C_PB9_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB9 */
-#define SYSCFG_CFGR1_I2C1_FMP_Pos               (20U)
-#define SYSCFG_CFGR1_I2C1_FMP_Msk               (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)            /*!< 0x00100000 */
-#define SYSCFG_CFGR1_I2C1_FMP                   SYSCFG_CFGR1_I2C1_FMP_Msk                       /*!< I2C1 Fast-mode Plus (Fm+) driving capability activation   */
-#define SYSCFG_CFGR1_I2C2_FMP_Pos               (21U)
-#define SYSCFG_CFGR1_I2C2_FMP_Msk               (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)            /*!< 0x00200000 */
-#define SYSCFG_CFGR1_I2C2_FMP                   SYSCFG_CFGR1_I2C2_FMP_Msk                       /*!< I2C2 Fast-mode Plus (Fm+) driving capability activation   */
-#define SYSCFG_CFGR1_I2C3_FMP_Pos               (22U)
-#define SYSCFG_CFGR1_I2C3_FMP_Msk               (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)            /*!< 0x00400000 */
-#define SYSCFG_CFGR1_I2C3_FMP                   SYSCFG_CFGR1_I2C3_FMP_Msk                       /*!< I2C3 Fast-mode Plus (Fm+) driving capability activation   */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  (External interrupt configuration register 1) ********************************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                (0U)
-#define SYSCFG_EXTICR1_EXTI0_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)             /*!< 0x00000007 */
-#define SYSCFG_EXTICR1_EXTI0                    SYSCFG_EXTICR1_EXTI0_Msk                        /*!< External Interrupt Line 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                (4U)
-#define SYSCFG_EXTICR1_EXTI1_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)             /*!< 0x00000070 */
-#define SYSCFG_EXTICR1_EXTI1                    SYSCFG_EXTICR1_EXTI1_Msk                        /*!< External Interrupt Line 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                (8U)
-#define SYSCFG_EXTICR1_EXTI2_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)             /*!< 0x00000700 */
-#define SYSCFG_EXTICR1_EXTI2                    SYSCFG_EXTICR1_EXTI2_Msk                        /*!< External Interrupt Line 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                (12U)
-#define SYSCFG_EXTICR1_EXTI3_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)             /*!< 0x00007000 */
-#define SYSCFG_EXTICR1_EXTI3                    SYSCFG_EXTICR1_EXTI3_Msk                        /*!< External Interrupt Line 3 configuration */
-
-/**
-  * @brief  External Interrupt Line 0 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                 (0x00000000U)   /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                 (0x00000001U)   /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                 (0x00000002U)   /*!< PC[0] pin */
-
-/**
-  * @brief  External Interrupt Line 1 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI1_PA                 (0x00000000U)   /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                 (0x00000010U)   /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                 (0x00000020U)   /*!< PC[1] pin */
-
-/**
-  * @brief  External Interrupt Line 2 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                 (0x00000000U)   /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                 (0x00000100U)   /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                 (0x00000200U)   /*!< PC[2] pin */
-
-/**
-  * @brief  External Interrupt Line 3 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                 (0x00000000U)   /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                 (0x00001000U)   /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                 (0x00002000U)   /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  (External interrupt configuration register 2) ********************************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                (0U)
-#define SYSCFG_EXTICR2_EXTI4_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)             /*!< 0x00000007 */
-#define SYSCFG_EXTICR2_EXTI4                    SYSCFG_EXTICR2_EXTI4_Msk                        /*!< External Interrupt Line 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                (4U)
-#define SYSCFG_EXTICR2_EXTI5_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)             /*!< 0x00000070 */
-#define SYSCFG_EXTICR2_EXTI5                    SYSCFG_EXTICR2_EXTI5_Msk                        /*!< External Interrupt Line 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                (8U)
-#define SYSCFG_EXTICR2_EXTI6_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)             /*!< 0x00000700 */
-#define SYSCFG_EXTICR2_EXTI6                    SYSCFG_EXTICR2_EXTI6_Msk                        /*!< External Interrupt Line 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                (12U)
-#define SYSCFG_EXTICR2_EXTI7_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)             /*!< 0x00007000 */
-#define SYSCFG_EXTICR2_EXTI7                    SYSCFG_EXTICR2_EXTI7_Msk                        /*!< External Interrupt Line 7 configuration */
-
-/**
-  * @brief  External Interrupt Line 4 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                 (0x00000000U)   /*!< PA[4] pin  */
-#define SYSCFG_EXTICR2_EXTI4_PB                 (0x00000001U)   /*!< PB[4] pin  */
-#define SYSCFG_EXTICR2_EXTI4_PC                 (0x00000002U)   /*!< PC[4] pin  */
-
-/**
-  * @brief  External Interrupt Line 5 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                 (0x00000000U)   /*!< PA[5] pin  */
-#define SYSCFG_EXTICR2_EXTI5_PB                 (0x00000010U)   /*!< PB[5] pin  */
-#define SYSCFG_EXTICR2_EXTI5_PC                 (0x00000020U)   /*!< PC[5] pin  */
-
-/**
-  * @brief  External Interrupt Line 6 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                 (0x00000000U)   /*!< PA[6] pin  */
-#define SYSCFG_EXTICR2_EXTI6_PB                 (0x00000100U)   /*!< PB[6] pin  */
-#define SYSCFG_EXTICR2_EXTI6_PC                 (0x00000200U)   /*!< PC[6] pin  */
-
-/**
-  * @brief  External Interrupt Line 7 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                 (0x00000000U)   /*!< PA[7] pin  */
-#define SYSCFG_EXTICR2_EXTI7_PB                 (0x00001000U)   /*!< PB[7] pin  */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  (External interrupt configuration register 3) ********************************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                (0U)
-#define SYSCFG_EXTICR3_EXTI8_Msk                (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)             /*!< 0x00000007 */
-#define SYSCFG_EXTICR3_EXTI8                    SYSCFG_EXTICR3_EXTI8_Msk                        /*!< External Interrupt Line 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                (4U)
-#define SYSCFG_EXTICR3_EXTI9_Msk                (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)             /*!< 0x00000070 */
-#define SYSCFG_EXTICR3_EXTI9                    SYSCFG_EXTICR3_EXTI9_Msk                        /*!< External Interrupt Line 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos               (8U)
-#define SYSCFG_EXTICR3_EXTI10_Msk               (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)            /*!< 0x00000700 */
-#define SYSCFG_EXTICR3_EXTI10                   SYSCFG_EXTICR3_EXTI10_Msk                       /*!< External Interrupt Line 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos               (12U)
-#define SYSCFG_EXTICR3_EXTI11_Msk               (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)            /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                   SYSCFG_EXTICR3_EXTI11_Msk                       /*!< External Interrupt Line 11 configuration */
-
-/**
-  * @brief  External Interrupt Line 8 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                 (0x00000000U)   /*!< PA[8] pin  */
-#define SYSCFG_EXTICR3_EXTI8_PB                 (0x00000001U)   /*!< PB[8] pin  */
-
-/**
-  * @brief  External Interrupt Line 9 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                 (0x00000000U)   /*!< PA[9] pin  */
-#define SYSCFG_EXTICR3_EXTI9_PB                 (0x00000010U)   /*!< PB[9] pin  */
-
-/**
-  * @brief  External Interrupt Line 10 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                (0x00000000U)   /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                (0x00000100U)   /*!< PB[10] pin */
-
-/**
-  * @brief  External Interrupt Line 11 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                (0x00000000U)   /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                (0x00001000U)   /*!< PB[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  (External interrupt configuration register 4) *********************************/
-#define SYSCFG_EXTICR4_EXTI12_Pos               (0U)
-#define SYSCFG_EXTICR4_EXTI12_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)            /*!< 0x00000007 */
-#define SYSCFG_EXTICR4_EXTI12                   SYSCFG_EXTICR4_EXTI12_Msk                       /*!< External Interrupt Line 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos               (4U)
-#define SYSCFG_EXTICR4_EXTI13_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)            /*!< 0x00000070 */
-#define SYSCFG_EXTICR4_EXTI13                   SYSCFG_EXTICR4_EXTI13_Msk                       /*!< External Interrupt Line 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos               (8U)
-#define SYSCFG_EXTICR4_EXTI14_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)            /*!< 0x00000700 */
-#define SYSCFG_EXTICR4_EXTI14                   SYSCFG_EXTICR4_EXTI14_Msk                       /*!< External Interrupt Line 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos               (12U)
-#define SYSCFG_EXTICR4_EXTI15_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)            /*!< 0x00007000 */
-#define SYSCFG_EXTICR4_EXTI15                   SYSCFG_EXTICR4_EXTI15_Msk                       /*!< External Interrupt Line 15 configuration */
-
-/**
-  * @brief  External Interrupt Line 12 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                (0x00000000U)   /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                (0x00000001U)   /*!< PB[12] pin */
-
-/**
-  * @brief  External Interrupt Line 13 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                (0x00000000U)   /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                (0x00000010U)   /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                (0x00000020U)   /*!< PC[13] pin */
-
-/**
-  * @brief  External Interrupt Line 14 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                (0x00000000U)   /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                (0x00000100U)   /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                (0x00000200U)   /*!< PC[14] pin */
-
-/**
-  * @brief  External Interrupt Line 15 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                (0x00000000U)   /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                (0x00001000U)   /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                (0x00002000U)   /*!< PC[15] pin */
-
-/*****************  Bit definition for SYSCFG_SCSR register  (SYSCFG SRAM control and status register) **********************************************************/
-#define SYSCFG_SCSR_SRAM2ER_Pos                 (0U)
-#define SYSCFG_SCSR_SRAM2ER_Msk                 (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)               /*!< 0x00000001 */
-#define SYSCFG_SCSR_SRAM2ER                     SYSCFG_SCSR_SRAM2ER_Msk                          /*!< SRAM2 Erase                                      */
-#define SYSCFG_SCSR_SRAMBSY_Pos                 (1U)
-#define SYSCFG_SCSR_SRAMBSY_Msk                 (0x1UL << SYSCFG_SCSR_SRAMBSY_Pos)              /*!< 0x00000002 */
-#define SYSCFG_SCSR_SRAMBSY                     SYSCFG_SCSR_SRAMBSY_Msk                         /*!< SRAM2 and SRAM1 busy by erase operation                    */
-#define SYSCFG_SCSR_PKASRAMBSY_Pos              (8U)
-#define SYSCFG_SCSR_PKASRAMBSY_Msk              (0x1UL << SYSCFG_SCSR_PKASRAMBSY_Pos)           /*!< 0x00000100 */
-#define SYSCFG_SCSR_PKASRAMBSY                  SYSCFG_SCSR_PKASRAMBSY_Msk                      /*!< PKA SRAM busy by erase operation                           */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  (SYSCFG configuration register 2) *****************************************************************/
-#define SYSCFG_CFGR2_CLL_Pos                    (0U)
-#define SYSCFG_CFGR2_CLL_Msk                    (0x1UL << SYSCFG_CFGR2_CLL_Pos)                 /*!< 0x00000001 */
-#define SYSCFG_CFGR2_CLL                        SYSCFG_CFGR2_CLL_Msk                            /*!< Cortex M4 LOCKUP (hardfault) output enable                 */
-#define SYSCFG_CFGR2_SPL_Pos                    (1U)
-#define SYSCFG_CFGR2_SPL_Msk                    (0x1UL << SYSCFG_CFGR2_SPL_Pos)                 /*!< 0x00000002 */
-#define SYSCFG_CFGR2_SPL                        SYSCFG_CFGR2_SPL_Msk                            /*!< SRAM2 Parity Lock                                          */
-#define SYSCFG_CFGR2_PVDL_Pos                   (2U)
-#define SYSCFG_CFGR2_PVDL_Msk                   (0x1UL << SYSCFG_CFGR2_PVDL_Pos)                /*!< 0x00000004 */
-#define SYSCFG_CFGR2_PVDL                       SYSCFG_CFGR2_PVDL_Msk                           /*!< PVD Lock                                                   */
-#define SYSCFG_CFGR2_ECCL_Pos                   (3U)
-#define SYSCFG_CFGR2_ECCL_Msk                   (0x1UL << SYSCFG_CFGR2_ECCL_Pos)                /*!< 0x00000008 */
-#define SYSCFG_CFGR2_ECCL                       SYSCFG_CFGR2_ECCL_Msk                           /*!< ECC Lock                                                   */
-#define SYSCFG_CFGR2_SPF_Pos                    (8U)
-#define SYSCFG_CFGR2_SPF_Msk                    (0x1UL << SYSCFG_CFGR2_SPF_Pos)                 /*!< 0x00000100 */
-#define SYSCFG_CFGR2_SPF                        SYSCFG_CFGR2_SPF_Msk                            /*!< SRAM2 Parity Lock                                          */
-
-/*****************  Bit definition for SYSCFG_SWPR register  (SYSCFG SRAM2 write protection register) ***********************************************************/
-#define SYSCFG_SWPR_PAGE0_Pos                   (0U)
-#define SYSCFG_SWPR_PAGE0_Msk                   (0x1UL << SYSCFG_SWPR_PAGE0_Pos)                /*!< 0x00000001 */
-#define SYSCFG_SWPR_PAGE0                       SYSCFG_SWPR_PAGE0_Msk                           /*!< SRAM2 Write protection page 0 (0x20008000 – 0x200083FF)    */
-#define SYSCFG_SWPR_PAGE1_Pos                   (1U)
-#define SYSCFG_SWPR_PAGE1_Msk                   (0x1UL << SYSCFG_SWPR_PAGE1_Pos)                /*!< 0x00000002 */
-#define SYSCFG_SWPR_PAGE1                       SYSCFG_SWPR_PAGE1_Msk                           /*!< SRAM2 Write protection page 1 (0x20008400 – 0x200087FF)    */
-#define SYSCFG_SWPR_PAGE2_Pos                   (2U)
-#define SYSCFG_SWPR_PAGE2_Msk                   (0x1UL << SYSCFG_SWPR_PAGE2_Pos)                /*!< 0x00000004 */
-#define SYSCFG_SWPR_PAGE2                       SYSCFG_SWPR_PAGE2_Msk                           /*!< SRAM2 Write protection page 2 (0x20008800 – 0x20008BFF)    */
-#define SYSCFG_SWPR_PAGE3_Pos                   (3U)
-#define SYSCFG_SWPR_PAGE3_Msk                   (0x1UL << SYSCFG_SWPR_PAGE3_Pos)                /*!< 0x00000008 */
-#define SYSCFG_SWPR_PAGE3                       SYSCFG_SWPR_PAGE3_Msk                           /*!< SRAM2 Write protection page 3 (0x20008C00 – 0x20008FFF)    */
-#define SYSCFG_SWPR_PAGE4_Pos                   (4U)
-#define SYSCFG_SWPR_PAGE4_Msk                   (0x1UL << SYSCFG_SWPR_PAGE4_Pos)                /*!< 0x00000010 */
-#define SYSCFG_SWPR_PAGE4                       SYSCFG_SWPR_PAGE4_Msk                           /*!< SRAM2 Write protection page 4 (0x20009000 – 0x200093FF)    */
-#define SYSCFG_SWPR_PAGE5_Pos                   (5U)
-#define SYSCFG_SWPR_PAGE5_Msk                   (0x1UL << SYSCFG_SWPR_PAGE5_Pos)                /*!< 0x00000020 */
-#define SYSCFG_SWPR_PAGE5                       SYSCFG_SWPR_PAGE5_Msk                           /*!< SRAM2 Write protection page 5 (0x20009400 – 0x200097FF)    */
-#define SYSCFG_SWPR_PAGE6_Pos                   (6U)
-#define SYSCFG_SWPR_PAGE6_Msk                   (0x1UL << SYSCFG_SWPR_PAGE6_Pos)                /*!< 0x00000040 */
-#define SYSCFG_SWPR_PAGE6                       SYSCFG_SWPR_PAGE6_Msk                           /*!< SRAM2 Write protection page 6 (0x20009800 – 0x20009BFF)    */
-#define SYSCFG_SWPR_PAGE7_Pos                   (7U)
-#define SYSCFG_SWPR_PAGE7_Msk                   (0x1UL << SYSCFG_SWPR_PAGE7_Pos)                /*!< 0x00000080 */
-#define SYSCFG_SWPR_PAGE7                       SYSCFG_SWPR_PAGE7_Msk                           /*!< SRAM2 Write protection page 7 (0x20009C00 – 0x20009FFF)    */
-#define SYSCFG_SWPR_PAGE8_Pos                   (8U)
-#define SYSCFG_SWPR_PAGE8_Msk                   (0x1UL << SYSCFG_SWPR_PAGE8_Pos)                /*!< 0x00000100 */
-#define SYSCFG_SWPR_PAGE8                       SYSCFG_SWPR_PAGE8_Msk                           /*!< SRAM2 Write protection page 8 (0x2000A000 – 0x2000A3FF)    */
-#define SYSCFG_SWPR_PAGE9_Pos                   (9U)
-#define SYSCFG_SWPR_PAGE9_Msk                   (0x1UL << SYSCFG_SWPR_PAGE9_Pos)                /*!< 0x00000200 */
-#define SYSCFG_SWPR_PAGE9                       SYSCFG_SWPR_PAGE9_Msk                           /*!< SRAM2 Write protection page 9 (0x2000A400 – 0x2000A7FF)    */
-#define SYSCFG_SWPR_PAGE10_Pos                  (10U)
-#define SYSCFG_SWPR_PAGE10_Msk                  (0x1UL << SYSCFG_SWPR_PAGE10_Pos)               /*!< 0x00000400 */
-#define SYSCFG_SWPR_PAGE10                      SYSCFG_SWPR_PAGE10_Msk                          /*!< SRAM2 Write protection page 10 (0x2000A800 – 0x2000ABFF)   */
-#define SYSCFG_SWPR_PAGE11_Pos                  (11U)
-#define SYSCFG_SWPR_PAGE11_Msk                  (0x1UL << SYSCFG_SWPR_PAGE11_Pos)               /*!< 0x00000800 */
-#define SYSCFG_SWPR_PAGE11                      SYSCFG_SWPR_PAGE11_Msk                          /*!< SRAM2 Write protection page 11 (0x2000AC00 – 0x2000AFFF)   */
-#define SYSCFG_SWPR_PAGE12_Pos                  (12U)
-#define SYSCFG_SWPR_PAGE12_Msk                  (0x1UL << SYSCFG_SWPR_PAGE12_Pos)               /*!< 0x00001000 */
-#define SYSCFG_SWPR_PAGE12                      SYSCFG_SWPR_PAGE12_Msk                          /*!< SRAM2 Write protection page 12 (0x2000B000 – 0x2000B3FF)   */
-#define SYSCFG_SWPR_PAGE13_Pos                  (13U)
-#define SYSCFG_SWPR_PAGE13_Msk                  (0x1UL << SYSCFG_SWPR_PAGE13_Pos)               /*!< 0x00002000 */
-#define SYSCFG_SWPR_PAGE13                      SYSCFG_SWPR_PAGE13_Msk                          /*!< SRAM2 Write protection page 13 (0x2000B400 – 0x2000B7FF)   */
-#define SYSCFG_SWPR_PAGE14_Pos                  (14U)
-#define SYSCFG_SWPR_PAGE14_Msk                  (0x1UL << SYSCFG_SWPR_PAGE14_Pos)               /*!< 0x00004000 */
-#define SYSCFG_SWPR_PAGE14                      SYSCFG_SWPR_PAGE14_Msk                          /*!< SRAM2 Write protection page 14 (0x2000B800 – 0x2000BBFF)   */
-#define SYSCFG_SWPR_PAGE15_Pos                  (15U)
-#define SYSCFG_SWPR_PAGE15_Msk                  (0x1UL << SYSCFG_SWPR_PAGE15_Pos)               /*!< 0x00008000 */
-#define SYSCFG_SWPR_PAGE15                      SYSCFG_SWPR_PAGE15_Msk                          /*!< SRAM2 Write protection page 15 (0x2000BC00 – 0x2000BFFF)   */
-#define SYSCFG_SWPR_PAGE16_Pos                  (16U)
-#define SYSCFG_SWPR_PAGE16_Msk                  (0x1UL << SYSCFG_SWPR_PAGE16_Pos)               /*!< 0x00010000 */
-#define SYSCFG_SWPR_PAGE16                      SYSCFG_SWPR_PAGE16_Msk                          /*!< SRAM2 Write protection page 16 (0x2000C000 – 0x2000C3FF)   */
-#define SYSCFG_SWPR_PAGE17_Pos                  (17U)
-#define SYSCFG_SWPR_PAGE17_Msk                  (0x1UL << SYSCFG_SWPR_PAGE17_Pos)               /*!< 0x00020000 */
-#define SYSCFG_SWPR_PAGE17                      SYSCFG_SWPR_PAGE17_Msk                          /*!< SRAM2 Write protection page 17 (0x2000C400 – 0x2000C7FF)   */
-#define SYSCFG_SWPR_PAGE18_Pos                  (18U)
-#define SYSCFG_SWPR_PAGE18_Msk                  (0x1UL << SYSCFG_SWPR_PAGE18_Pos)               /*!< 0x00040000 */
-#define SYSCFG_SWPR_PAGE18                      SYSCFG_SWPR_PAGE18_Msk                          /*!< SRAM2 Write protection page 18 (0x2000C800 – 0x2000CBFF)   */
-#define SYSCFG_SWPR_PAGE19_Pos                  (19U)
-#define SYSCFG_SWPR_PAGE19_Msk                  (0x1UL << SYSCFG_SWPR_PAGE19_Pos)               /*!< 0x00080000 */
-#define SYSCFG_SWPR_PAGE19                      SYSCFG_SWPR_PAGE19_Msk                          /*!< SRAM2 Write protection page 19 (0x2000CC00 – 0x2000CFFF)   */
-#define SYSCFG_SWPR_PAGE20_Pos                  (20U)
-#define SYSCFG_SWPR_PAGE20_Msk                  (0x1UL << SYSCFG_SWPR_PAGE20_Pos)               /*!< 0x00100000 */
-#define SYSCFG_SWPR_PAGE20                      SYSCFG_SWPR_PAGE20_Msk                          /*!< SRAM2 Write protection page 20 (0x2000D000 – 0x2000D3FF)   */
-#define SYSCFG_SWPR_PAGE21_Pos                  (21U)
-#define SYSCFG_SWPR_PAGE21_Msk                  (0x1UL << SYSCFG_SWPR_PAGE21_Pos)               /*!< 0x00200000 */
-#define SYSCFG_SWPR_PAGE21                      SYSCFG_SWPR_PAGE21_Msk                          /*!< SRAM2 Write protection page 21 (0x2000D400 – 0x2000D7FF)   */
-#define SYSCFG_SWPR_PAGE22_Pos                  (22U)
-#define SYSCFG_SWPR_PAGE22_Msk                  (0x1UL << SYSCFG_SWPR_PAGE22_Pos)               /*!< 0x00400000 */
-#define SYSCFG_SWPR_PAGE22                      SYSCFG_SWPR_PAGE22_Msk                          /*!< SRAM2 Write protection page 22 (0x2000D800 – 0x2000DBFF)   */
-#define SYSCFG_SWPR_PAGE23_Pos                  (23U)
-#define SYSCFG_SWPR_PAGE23_Msk                  (0x1UL << SYSCFG_SWPR_PAGE23_Pos)               /*!< 0x00800000 */
-#define SYSCFG_SWPR_PAGE23                      SYSCFG_SWPR_PAGE23_Msk                          /*!< SRAM2 Write protection page 23 (0x2000DC00 – 0x2000DFFF)   */
-#define SYSCFG_SWPR_PAGE24_Pos                  (24U)
-#define SYSCFG_SWPR_PAGE24_Msk                  (0x1UL << SYSCFG_SWPR_PAGE24_Pos)               /*!< 0x01000000 */
-#define SYSCFG_SWPR_PAGE24                      SYSCFG_SWPR_PAGE24_Msk                          /*!< SRAM2 Write protection page 24 (0x2000E000 – 0x2000E3FF)   */
-#define SYSCFG_SWPR_PAGE25_Pos                  (25U)
-#define SYSCFG_SWPR_PAGE25_Msk                  (0x1UL << SYSCFG_SWPR_PAGE25_Pos)               /*!< 0x02000000 */
-#define SYSCFG_SWPR_PAGE25                      SYSCFG_SWPR_PAGE25_Msk                          /*!< SRAM2 Write protection page 25 (0x2000E400 – 0x2000E7FF)   */
-#define SYSCFG_SWPR_PAGE26_Pos                  (26U)
-#define SYSCFG_SWPR_PAGE26_Msk                  (0x1UL << SYSCFG_SWPR_PAGE26_Pos)               /*!< 0x04000000 */
-#define SYSCFG_SWPR_PAGE26                      SYSCFG_SWPR_PAGE26_Msk                          /*!< SRAM2 Write protection page 26 (0x2000E800 – 0x2000EBFF)   */
-#define SYSCFG_SWPR_PAGE27_Pos                  (27U)
-#define SYSCFG_SWPR_PAGE27_Msk                  (0x1UL << SYSCFG_SWPR_PAGE27_Pos)               /*!< 0x08000000 */
-#define SYSCFG_SWPR_PAGE27                      SYSCFG_SWPR_PAGE27_Msk                          /*!< SRAM2 Write protection page 27 (0x2000EC00 – 0x2000EFFF)   */
-#define SYSCFG_SWPR_PAGE28_Pos                  (28U)
-#define SYSCFG_SWPR_PAGE28_Msk                  (0x1UL << SYSCFG_SWPR_PAGE28_Pos)               /*!< 0x10000000 */
-#define SYSCFG_SWPR_PAGE28                      SYSCFG_SWPR_PAGE28_Msk                          /*!< SRAM2 Write protection page 28 (0x2000F000 – 0x2000F3FF)   */
-#define SYSCFG_SWPR_PAGE29_Pos                  (29U)
-#define SYSCFG_SWPR_PAGE29_Msk                  (0x1UL << SYSCFG_SWPR_PAGE29_Pos)               /*!< 0x20000000 */
-#define SYSCFG_SWPR_PAGE29                      SYSCFG_SWPR_PAGE29_Msk                          /*!< SRAM2 Write protection page 29 (0x2000F400 – 0x2000F7FF)   */
-#define SYSCFG_SWPR_PAGE30_Pos                  (30U)
-#define SYSCFG_SWPR_PAGE30_Msk                  (0x1UL << SYSCFG_SWPR_PAGE30_Pos)               /*!< 0x40000000 */
-#define SYSCFG_SWPR_PAGE30                      SYSCFG_SWPR_PAGE30_Msk                          /*!< SRAM2 Write protection page 30 (0x2000F800 – 0x2000FBFF)   */
-#define SYSCFG_SWPR_PAGE31_Pos                  (31U)
-#define SYSCFG_SWPR_PAGE31_Msk                  (0x1UL << SYSCFG_SWPR_PAGE31_Pos)               /*!< 0x80000000 */
-#define SYSCFG_SWPR_PAGE31                      SYSCFG_SWPR_PAGE31_Msk                          /*!< SRAM2 Write protection page 31 (0x2000FC00 – 0x2000FFFF)   */
-
-/*****************  Bit definition for SYSCFG_SKR register  (SYSCFG SRAM2 key register) *************************************************************************/
-#define SYSCFG_SKR_KEY_Pos                      (0U)
-#define SYSCFG_SKR_KEY_Msk                      (0xFFUL << SYSCFG_SKR_KEY_Pos)                  /*!< 0x000000FF */
-#define SYSCFG_SKR_KEY                          SYSCFG_SKR_KEY_Msk                              /*!< SRAM2 write protection key for software erase              */
-
-/*****************  Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/
-#define SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM_Pos    (0U)
-#define SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM_Msk    (0x1UL << SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM_Pos) /*!< 0x00000001 */
-#define SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM        SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM_Msk            /*!< Enabling of interrupt from RTCSTAMPTAMPLSECSS to CPU1             */
-#define SYSCFG_IMR1_RTCSSRUIM_Pos               (2U)
-#define SYSCFG_IMR1_RTCSSRUIM_Msk               (0x1UL << SYSCFG_IMR1_RTCSSRUIM_Pos)            /*!< 0x00000004 */
-#define SYSCFG_IMR1_RTCSSRUIM                   SYSCFG_IMR1_RTCSSRUIM_Msk                       /*!< Enabling of interrupt from RTC SSRU to CPU1                       */
-#define SYSCFG_IMR1_EXTI5IM_Pos                 (21U)
-#define SYSCFG_IMR1_EXTI5IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI5IM_Pos)            /*!< 0x00200000 */
-#define SYSCFG_IMR1_EXTI5IM                     SYSCFG_IMR1_EXTI5IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1      */
-#define SYSCFG_IMR1_EXTI6IM_Pos                 (22U)
-#define SYSCFG_IMR1_EXTI6IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI6IM_Pos)            /*!< 0x00400000 */
-#define SYSCFG_IMR1_EXTI6IM                     SYSCFG_IMR1_EXTI6IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1      */
-#define SYSCFG_IMR1_EXTI7IM_Pos                 (23U)
-#define SYSCFG_IMR1_EXTI7IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI7IM_Pos)            /*!< 0x00800000 */
-#define SYSCFG_IMR1_EXTI7IM                     SYSCFG_IMR1_EXTI7IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 7 to CPU1      */
-#define SYSCFG_IMR1_EXTI8IM_Pos                 (24U)
-#define SYSCFG_IMR1_EXTI8IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI8IM_Pos)            /*!< 0x01000000 */
-#define SYSCFG_IMR1_EXTI8IM                     SYSCFG_IMR1_EXTI8IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 8 to CPU1      */
-#define SYSCFG_IMR1_EXTI9IM_Pos                 (25U)
-#define SYSCFG_IMR1_EXTI9IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI9IM_Pos)            /*!< 0x02000000 */
-#define SYSCFG_IMR1_EXTI9IM                     SYSCFG_IMR1_EXTI9IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 9 to CPU1      */
-#define SYSCFG_IMR1_EXTI10IM_Pos                (26U)
-#define SYSCFG_IMR1_EXTI10IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI10IM_Pos)           /*!< 0x04000000 */
-#define SYSCFG_IMR1_EXTI10IM                    SYSCFG_IMR1_EXTI10IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 10 to CPU1     */
-#define SYSCFG_IMR1_EXTI11IM_Pos                (27U)
-#define SYSCFG_IMR1_EXTI11IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI11IM_Pos)           /*!< 0x08000000 */
-#define SYSCFG_IMR1_EXTI11IM                    SYSCFG_IMR1_EXTI11IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 11 to CPU1     */
-#define SYSCFG_IMR1_EXTI12IM_Pos                (28U)
-#define SYSCFG_IMR1_EXTI12IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI12IM_Pos)           /*!< 0x10000000 */
-#define SYSCFG_IMR1_EXTI12IM                    SYSCFG_IMR1_EXTI12IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 12 to CPU1     */
-#define SYSCFG_IMR1_EXTI13IM_Pos                (29U)
-#define SYSCFG_IMR1_EXTI13IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI13IM_Pos)           /*!< 0x20000000 */
-#define SYSCFG_IMR1_EXTI13IM                    SYSCFG_IMR1_EXTI13IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 13 to CPU1     */
-#define SYSCFG_IMR1_EXTI14IM_Pos                (30U)
-#define SYSCFG_IMR1_EXTI14IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI14IM_Pos)           /*!< 0x40000000 */
-#define SYSCFG_IMR1_EXTI14IM                    SYSCFG_IMR1_EXTI14IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 14 to CPU1     */
-#define SYSCFG_IMR1_EXTI15IM_Pos                (31U)
-#define SYSCFG_IMR1_EXTI15IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI15IM_Pos)           /*!< 0x80000000 */
-#define SYSCFG_IMR1_EXTI15IM                    SYSCFG_IMR1_EXTI15IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 15 to CPU1     */
-
-/*****************  Bit definition for SYSCFG_IMR2 register (Interrupt masks control and status register on CPU1 - part 2) *******************************************/
-#define SYSCFG_IMR2_PVM3IM_Pos                  (18U)
-#define SYSCFG_IMR2_PVM3IM_Msk                  (0x1UL << SYSCFG_IMR2_PVM3IM_Pos)             /*!< 0x00040000 */
-#define SYSCFG_IMR2_PVM3IM                      SYSCFG_IMR2_PVM3IM_Msk                        /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1     */
-#define SYSCFG_IMR2_PVDIM_Pos                   (20U)
-#define SYSCFG_IMR2_PVDIM_Msk                   (0x1UL << SYSCFG_IMR2_PVDIM_Pos)              /*!< 0x00100000 */
-#define SYSCFG_IMR2_PVDIM                       SYSCFG_IMR2_PVDIM_Msk                         /*!< Enabling of interrupt from Power Voltage Detector to CPU1         */
-
-/*****************  Bit definition for SYSCFG_C2IMR1 register (Interrupt masks control and status register on CPU2 - part 1) *******************************************/
-#define SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Pos  (0U)
-#define SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Msk  (0x1U << SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Pos)/*!< 0x00000001 */
-#define SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM      SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Msk          /* !< Enabling of interrupt from RTC TimeStamp, RTC Tampers                                                                                                      and LSE Clock Security System to CPU2                            */
-#define SYSCFG_C2IMR1_RTCALARMIM_Pos            (1U)
-#define SYSCFG_C2IMR1_RTCALARMIM_Msk            (0x1UL << SYSCFG_C2IMR1_RTCALARMIM_Pos)         /*!< 0x00000002 */
-#define SYSCFG_C2IMR1_RTCALARMIM                SYSCFG_C2IMR1_RTCALARMIM_Msk                    /*!< Enabling of interrupt from RTC Alarms to CPU2                    */
-#define SYSCFG_C2IMR1_RTCSSRUIM_Pos             (2U)
-#define SYSCFG_C2IMR1_RTCSSRUIM_Msk             (0x1UL << SYSCFG_C2IMR1_RTCSSRUIM_Pos)          /*!< 0x00000004 */
-#define SYSCFG_C2IMR1_RTCSSRUIM                 SYSCFG_C2IMR1_RTCSSRUIM_Msk                     /*!< Enabling of interrupt from RTC SSRU to CPU2                      */
-#define SYSCFG_C2IMR1_RTCWKUPIM_Pos             (3U)
-#define SYSCFG_C2IMR1_RTCWKUPIM_Msk             (0x1UL << SYSCFG_C2IMR1_RTCWKUPIM_Pos)          /*!< 0x00000008 */
-#define SYSCFG_C2IMR1_RTCWKUPIM                 SYSCFG_C2IMR1_RTCWKUPIM_Msk                     /*!< Enabling of interrupt from RTC Wakeup to CPU2                    */
-#define SYSCFG_C2IMR1_RCCIM_Pos                 (5U)
-#define SYSCFG_C2IMR1_RCCIM_Msk                 (0x1UL << SYSCFG_C2IMR1_RCCIM_Pos)              /*!< 0x00000020 */
-#define SYSCFG_C2IMR1_RCCIM                     SYSCFG_C2IMR1_RCCIM_Msk                         /*!< Enabling of interrupt from RCC to CPU2                           */
-#define SYSCFG_C2IMR1_FLASHIM_Pos               (6U)
-#define SYSCFG_C2IMR1_FLASHIM_Msk               (0x1UL << SYSCFG_C2IMR1_FLASHIM_Pos)            /*!< 0x00000040 */
-#define SYSCFG_C2IMR1_FLASHIM                   SYSCFG_C2IMR1_FLASHIM_Msk                       /*!< Enabling of interrupt from FLASH to CPU2                         */
-#define SYSCFG_C2IMR1_PKAIM_Pos                 (8U)
-#define SYSCFG_C2IMR1_PKAIM_Msk                 (0x1UL << SYSCFG_C2IMR1_PKAIM_Pos)              /*!< 0x00000040 */
-#define SYSCFG_C2IMR1_PKAIM                     SYSCFG_C2IMR1_PKAIM_Msk                         /*!< Enabling of interrupt from PKA to CPU2                           */
-#define SYSCFG_C2IMR1_AESIM_Pos                 (10U)
-#define SYSCFG_C2IMR1_AESIM_Msk                 (0x1UL << SYSCFG_C2IMR1_AESIM_Pos)              /*!< 0x00000800 */
-#define SYSCFG_C2IMR1_AESIM                     SYSCFG_C2IMR1_AESIM_Msk                         /*!< Enabling of interrupt from AES to CPU2                          */
-#define SYSCFG_C2IMR1_COMPIM_Pos                (11U)
-#define SYSCFG_C2IMR1_COMPIM_Msk                (0x1UL << SYSCFG_C2IMR1_COMPIM_Pos)             /*!< 0x00000800 */
-#define SYSCFG_C2IMR1_COMPIM                    SYSCFG_C2IMR1_COMPIM_Msk                        /*!< Enabling of interrupt from Comparator to CPU2                    */
-#define SYSCFG_C2IMR1_ADCIM_Pos                 (12U)
-#define SYSCFG_C2IMR1_ADCIM_Msk                 (0x1UL << SYSCFG_C2IMR1_ADCIM_Pos)              /*!< 0x00001000 */
-#define SYSCFG_C2IMR1_ADCIM                     SYSCFG_C2IMR1_ADCIM_Msk                         /*!< Enabling of interrupt from Analog Digital Converter to CPU2      */
-#define SYSCFG_C2IMR1_DACIM_Pos                 (13U)
-#define SYSCFG_C2IMR1_DACIM_Msk                 (0x1UL << SYSCFG_C2IMR1_DACIM_Pos)               /*!< 0x00002000 */
-#define SYSCFG_C2IMR1_DACIM                     SYSCFG_C2IMR1_DACIM_Msk                          /*!< Enabling of interrupt from Digital Analog Converter to CPU2     */
-#define SYSCFG_C2IMR1_EXTI0IM_Pos               (16U)
-#define SYSCFG_C2IMR1_EXTI0IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI0IM_Pos)            /*!< 0x00010000 */
-#define SYSCFG_C2IMR1_EXTI0IM                   SYSCFG_C2IMR1_EXTI0IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2     */
-#define SYSCFG_C2IMR1_EXTI1IM_Pos               (17U)
-#define SYSCFG_C2IMR1_EXTI1IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI1IM_Pos)            /*!< 0x00020000 */
-#define SYSCFG_C2IMR1_EXTI1IM                   SYSCFG_C2IMR1_EXTI1IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 1 to CPU2     */
-#define SYSCFG_C2IMR1_EXTI2IM_Pos               (18U)
-#define SYSCFG_C2IMR1_EXTI2IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI2IM_Pos)            /*!< 0x00040000 */
-#define SYSCFG_C2IMR1_EXTI2IM                   SYSCFG_C2IMR1_EXTI2IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 2 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI3IM_Pos               (19U)
-#define SYSCFG_C2IMR1_EXTI3IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI3IM_Pos)            /*!< 0x00080000 */
-#define SYSCFG_C2IMR1_EXTI3IM                   SYSCFG_C2IMR1_EXTI3IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 3 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI4IM_Pos               (20U)
-#define SYSCFG_C2IMR1_EXTI4IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI4IM_Pos)            /*!< 0x00100000 */
-#define SYSCFG_C2IMR1_EXTI4IM                   SYSCFG_C2IMR1_EXTI4IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 4 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI5IM_Pos               (21U)
-#define SYSCFG_C2IMR1_EXTI5IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI5IM_Pos)            /*!< 0x00200000 */
-#define SYSCFG_C2IMR1_EXTI5IM                   SYSCFG_C2IMR1_EXTI5IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 5 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI6IM_Pos               (22U)
-#define SYSCFG_C2IMR1_EXTI6IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI6IM_Pos)            /*!< 0x00400000 */
-#define SYSCFG_C2IMR1_EXTI6IM                   SYSCFG_C2IMR1_EXTI6IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 6 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI7IM_Pos               (23U)
-#define SYSCFG_C2IMR1_EXTI7IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI7IM_Pos)            /*!< 0x00800000 */
-#define SYSCFG_C2IMR1_EXTI7IM                   SYSCFG_C2IMR1_EXTI7IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 7 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI8IM_Pos               (24U)
-#define SYSCFG_C2IMR1_EXTI8IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI8IM_Pos)            /*!< 0x01000000 */
-#define SYSCFG_C2IMR1_EXTI8IM                   SYSCFG_C2IMR1_EXTI8IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 8 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI9IM_Pos               (25U)
-#define SYSCFG_C2IMR1_EXTI9IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI9IM_Pos)            /*!< 0x02000000 */
-#define SYSCFG_C2IMR1_EXTI9IM                   SYSCFG_C2IMR1_EXTI9IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 9 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI10IM_Pos              (26U)
-#define SYSCFG_C2IMR1_EXTI10IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI10IM_Pos)           /*!< 0x04000000 */
-#define SYSCFG_C2IMR1_EXTI10IM                  SYSCFG_C2IMR1_EXTI10IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 10 to CPU2     */
-#define SYSCFG_C2IMR1_EXTI11IM_Pos              (27U)
-#define SYSCFG_C2IMR1_EXTI11IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI11IM_Pos)           /*!< 0x08000000 */
-#define SYSCFG_C2IMR1_EXTI11IM                  SYSCFG_C2IMR1_EXTI11IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 11 to CPU2     */
-#define SYSCFG_C2IMR1_EXTI12IM_Pos              (28U)
-#define SYSCFG_C2IMR1_EXTI12IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI12IM_Pos)           /*!< 0x10000000 */
-#define SYSCFG_C2IMR1_EXTI12IM                  SYSCFG_C2IMR1_EXTI12IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 12 to CPU2     */
-#define SYSCFG_C2IMR1_EXTI13IM_Pos              (29U)
-#define SYSCFG_C2IMR1_EXTI13IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI13IM_Pos)           /*!< 0x20000000 */
-#define SYSCFG_C2IMR1_EXTI13IM                  SYSCFG_C2IMR1_EXTI13IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 13 to CPU2     */
-#define SYSCFG_C2IMR1_EXTI14IM_Pos              (30U)
-#define SYSCFG_C2IMR1_EXTI14IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI14IM_Pos)           /*!< 0x40000000 */
-#define SYSCFG_C2IMR1_EXTI14IM                  SYSCFG_C2IMR1_EXTI14IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 14 to CPU2     */
-#define SYSCFG_C2IMR1_EXTI15IM_Pos              (31U)
-#define SYSCFG_C2IMR1_EXTI15IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI15IM_Pos)           /*!< 0x80000000 */
-#define SYSCFG_C2IMR1_EXTI15IM                  SYSCFG_C2IMR1_EXTI15IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 15 to CPU2     */
-
-/*****************  Bit definition for SYSCFG_C2IMR2 register (Interrupt masks control and status register on CPU2 - part 2) *******************************************/
-#define SYSCFG_C2IMR2_DMA1CH1IM_Pos             (0U)
-#define SYSCFG_C2IMR2_DMA1CH1IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH1IM_Pos)          /*!< 0x00000001 */
-#define SYSCFG_C2IMR2_DMA1CH1IM                 SYSCFG_C2IMR2_DMA1CH1IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 1 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA1CH2IM_Pos             (1U)
-#define SYSCFG_C2IMR2_DMA1CH2IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH2IM_Pos)          /*!< 0x00000002 */
-#define SYSCFG_C2IMR2_DMA1CH2IM                 SYSCFG_C2IMR2_DMA1CH2IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 2 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA1CH3IM_Pos             (2U)
-#define SYSCFG_C2IMR2_DMA1CH3IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH3IM_Pos)          /*!< 0x00000004 */
-#define SYSCFG_C2IMR2_DMA1CH3IM                 SYSCFG_C2IMR2_DMA1CH3IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 3 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA1CH4IM_Pos             (3U)
-#define SYSCFG_C2IMR2_DMA1CH4IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH4IM_Pos)          /*!< 0x00000008 */
-#define SYSCFG_C2IMR2_DMA1CH4IM                 SYSCFG_C2IMR2_DMA1CH4IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 4 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA1CH5IM_Pos             (4U)
-#define SYSCFG_C2IMR2_DMA1CH5IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH5IM_Pos)          /*!< 0x00000010 */
-#define SYSCFG_C2IMR2_DMA1CH5IM                 SYSCFG_C2IMR2_DMA1CH5IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 5 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA1CH6IM_Pos             (5U)
-#define SYSCFG_C2IMR2_DMA1CH6IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH6IM_Pos)          /*!< 0x00000020 */
-#define SYSCFG_C2IMR2_DMA1CH6IM                 SYSCFG_C2IMR2_DMA1CH6IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 6 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA1CH7IM_Pos             (6U)
-#define SYSCFG_C2IMR2_DMA1CH7IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH7IM_Pos)          /*!< 0x00000040 */
-#define SYSCFG_C2IMR2_DMA1CH7IM                 SYSCFG_C2IMR2_DMA1CH7IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 7 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA2CH1IM_Pos             (8U)
-#define SYSCFG_C2IMR2_DMA2CH1IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA2CH1IM_Pos)          /*!< 0x00000100 */
-#define SYSCFG_C2IMR2_DMA2CH1IM                 SYSCFG_C2IMR2_DMA2CH1IM_Msk                     /*!< Enabling of interrupt from DMA2 Channel 1 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA2CH2IM_Pos             (9U)
-#define SYSCFG_C2IMR2_DMA2CH2IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA2CH2IM_Pos)          /*!< 0x00000200 */
-#define SYSCFG_C2IMR2_DMA2CH2IM                 SYSCFG_C2IMR2_DMA2CH2IM_Msk                     /*!< Enabling of interrupt from DMA2 Channel 2 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA2CH3IM_Pos             (10U)
-#define SYSCFG_C2IMR2_DMA2CH3IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA2CH3IM_Pos)          /*!< 0x00000400 */
-#define SYSCFG_C2IMR2_DMA2CH3IM                 SYSCFG_C2IMR2_DMA2CH3IM_Msk                     /*!< Enabling of interrupt from DMA2 Channel 3 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA2CH4IM_Pos             (11U)
-#define SYSCFG_C2IMR2_DMA2CH4IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA2CH4IM_Pos)          /*!< 0x00000800 */
-#define SYSCFG_C2IMR2_DMA2CH4IM                 SYSCFG_C2IMR2_DMA2CH4IM_Msk                     /*!< Enabling of interrupt from DMA2 Channel 4 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA2CH5IM_Pos             (12U)
-#define SYSCFG_C2IMR2_DMA2CH5IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA2CH5IM_Pos)          /*!< 0x00001000 */
-#define SYSCFG_C2IMR2_DMA2CH5IM                 SYSCFG_C2IMR2_DMA2CH5IM_Msk                     /*!< Enabling of interrupt from DMA2 Channel 5 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA2CH6IM_Pos             (13U)
-#define SYSCFG_C2IMR2_DMA2CH6IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA2CH6IM_Pos)          /*!< 0x00002000 */
-#define SYSCFG_C2IMR2_DMA2CH6IM                 SYSCFG_C2IMR2_DMA2CH6IM_Msk                     /*!< Enabling of interrupt from DMA2 Channel 6 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA2CH7IM_Pos             (14U)
-#define SYSCFG_C2IMR2_DMA2CH7IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA2CH7IM_Pos)          /*!< 0x00004000 */
-#define SYSCFG_C2IMR2_DMA2CH7IM                 SYSCFG_C2IMR2_DMA2CH7IM_Msk                     /*!< Enabling of interrupt from DMA2 Channel 7 to CPU2                 */
-#define SYSCFG_C2IMR2_DMAMUX1IM_Pos             (15U)
-#define SYSCFG_C2IMR2_DMAMUX1IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMAMUX1IM_Pos)          /*!< 0x00008000 */
-#define SYSCFG_C2IMR2_DMAMUX1IM                 SYSCFG_C2IMR2_DMAMUX1IM_Msk                     /*!< Enabling of interrupt from DMAMUX1 to CPU2                        */
-#define SYSCFG_C2IMR2_PVM3IM_Pos                (18U)
-#define SYSCFG_C2IMR2_PVM3IM_Msk                (0x1UL << SYSCFG_C2IMR2_PVM3IM_Pos)             /*!< 0x00040000 */
-#define SYSCFG_C2IMR2_PVM3IM                    SYSCFG_C2IMR2_PVM3IM_Msk                        /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2     */
-#define SYSCFG_C2IMR2_PVDIM_Pos                 (20U)
-#define SYSCFG_C2IMR2_PVDIM_Msk                 (0x1UL << SYSCFG_C2IMR2_PVDIM_Pos)              /*!< 0x00100000 */
-#define SYSCFG_C2IMR2_PVDIM                     SYSCFG_C2IMR2_PVDIM_Msk                         /*!< Enabling of interrupt from Power Voltage Detector to CPU2         */
-
-/**************************************  Bit definition for SYSCFG_RFDCR register (SYSCFG radio debug control register) ************************************************/
-#define SYSCFG_RFDCR_RFTBSEL_Pos                (0U)
-#define SYSCFG_RFDCR_RFTBSEL_Msk                (0x1UL << SYSCFG_RFDCR_RFTBSEL_Pos)             /*!< 0x00000001 */
-#define SYSCFG_RFDCR_RFTBSEL                    SYSCFG_RFDCR_RFTBSEL_Msk                        /*!< Radio debug test bus selection                                    */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface (I2C)              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK_Pos          (8U)
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
-#define I2C_OAR2_OA2NOMASK           (0x00000000UL)                            /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*         Inter-Processor Communication Controller (IPCC)                    */
-/*                                                                            */
-/******************************************************************************/
-
-/**********************  Bit definition for IPCC_C1CR register  ***************/
-#define IPCC_C1CR_RXOIE_Pos      (0U)
-#define IPCC_C1CR_RXOIE_Msk      (0x1UL << IPCC_C1CR_RXOIE_Pos)                /*!< 0x00000001 */
-#define IPCC_C1CR_RXOIE          IPCC_C1CR_RXOIE_Msk                           /*!< Processor M4 Receive channel occupied interrupt enable */
-#define IPCC_C1CR_TXFIE_Pos      (16U)
-#define IPCC_C1CR_TXFIE_Msk      (0x1UL << IPCC_C1CR_TXFIE_Pos)                /*!< 0x00010000 */
-#define IPCC_C1CR_TXFIE          IPCC_C1CR_TXFIE_Msk                           /*!< Processor M4 Transmit channel free interrupt enable */
-
-/**********************  Bit definition for IPCC_C1MR register  **************/
-#define IPCC_C1MR_CH1OM_Pos      (0U)
-#define IPCC_C1MR_CH1OM_Msk      (0x1UL << IPCC_C1MR_CH1OM_Pos)                /*!< 0x00000001 */
-#define IPCC_C1MR_CH1OM          IPCC_C1MR_CH1OM_Msk                           /*!< M4 Channel1 occupied interrupt mask */
-#define IPCC_C1MR_CH2OM_Pos      (1U)
-#define IPCC_C1MR_CH2OM_Msk      (0x1UL << IPCC_C1MR_CH2OM_Pos)                /*!< 0x00000002 */
-#define IPCC_C1MR_CH2OM          IPCC_C1MR_CH2OM_Msk                           /*!< M4 Channel2 occupied interrupt mask */
-#define IPCC_C1MR_CH3OM_Pos      (2U)
-#define IPCC_C1MR_CH3OM_Msk      (0x1UL << IPCC_C1MR_CH3OM_Pos)                /*!< 0x00000004 */
-#define IPCC_C1MR_CH3OM          IPCC_C1MR_CH3OM_Msk                           /*!< M4 Channel3 occupied interrupt mask */
-#define IPCC_C1MR_CH4OM_Pos      (3U)
-#define IPCC_C1MR_CH4OM_Msk      (0x1UL << IPCC_C1MR_CH4OM_Pos)                /*!< 0x00000008 */
-#define IPCC_C1MR_CH4OM          IPCC_C1MR_CH4OM_Msk                           /*!< M4 Channel4 occupied interrupt mask */
-#define IPCC_C1MR_CH5OM_Pos      (4U)
-#define IPCC_C1MR_CH5OM_Msk      (0x1UL << IPCC_C1MR_CH5OM_Pos)                /*!< 0x00000010 */
-#define IPCC_C1MR_CH5OM          IPCC_C1MR_CH5OM_Msk                           /*!< M4 Channel5 occupied interrupt mask */
-#define IPCC_C1MR_CH6OM_Pos      (5U)
-#define IPCC_C1MR_CH6OM_Msk      (0x1UL << IPCC_C1MR_CH6OM_Pos)                /*!< 0x00000020 */
-#define IPCC_C1MR_CH6OM          IPCC_C1MR_CH6OM_Msk                           /*!< M4 Channel6 occupied interrupt mask */
-
-#define IPCC_C1MR_CH1FM_Pos      (16U)
-#define IPCC_C1MR_CH1FM_Msk      (0x1UL << IPCC_C1MR_CH1FM_Pos)                /*!< 0x00010000 */
-#define IPCC_C1MR_CH1FM          IPCC_C1MR_CH1FM_Msk                           /*!< M4 Transmit Channel1 free interrupt mask */
-#define IPCC_C1MR_CH2FM_Pos      (17U)
-#define IPCC_C1MR_CH2FM_Msk      (0x1UL << IPCC_C1MR_CH2FM_Pos)                /*!< 0x00020000 */
-#define IPCC_C1MR_CH2FM          IPCC_C1MR_CH2FM_Msk                           /*!< M4 Transmit Channel2 free interrupt mask */
-#define IPCC_C1MR_CH3FM_Pos      (18U)
-#define IPCC_C1MR_CH3FM_Msk      (0x1UL << IPCC_C1MR_CH3FM_Pos)                /*!< 0x00040000 */
-#define IPCC_C1MR_CH3FM          IPCC_C1MR_CH3FM_Msk                           /*!< M4 Transmit Channel3 free interrupt mask */
-#define IPCC_C1MR_CH4FM_Pos      (19U)
-#define IPCC_C1MR_CH4FM_Msk      (0x1UL << IPCC_C1MR_CH4FM_Pos)                /*!< 0x00080000 */
-#define IPCC_C1MR_CH4FM          IPCC_C1MR_CH4FM_Msk                           /*!< M4 Transmit Channel4 free interrupt mask */
-#define IPCC_C1MR_CH5FM_Pos      (20U)
-#define IPCC_C1MR_CH5FM_Msk      (0x1UL << IPCC_C1MR_CH5FM_Pos)                /*!< 0x00100000 */
-#define IPCC_C1MR_CH5FM          IPCC_C1MR_CH5FM_Msk                           /*!< M4 Transmit Channel5 free interrupt mask */
-#define IPCC_C1MR_CH6FM_Pos      (21U)
-#define IPCC_C1MR_CH6FM_Msk      (0x1UL << IPCC_C1MR_CH6FM_Pos)                /*!< 0x00200000 */
-#define IPCC_C1MR_CH6FM          IPCC_C1MR_CH6FM_Msk                           /*!< M4 Transmit Channel6 free interrupt mask */
-
-/**********************  Bit definition for IPCC_C1SCR register  ***************/
-#define IPCC_C1SCR_CH1C_Pos      (0U)
-#define IPCC_C1SCR_CH1C_Msk      (0x1UL << IPCC_C1SCR_CH1C_Pos)                /*!< 0x00000001 */
-#define IPCC_C1SCR_CH1C          IPCC_C1SCR_CH1C_Msk                           /*!< M4 receive Channel1 status clear */
-#define IPCC_C1SCR_CH2C_Pos      (1U)
-#define IPCC_C1SCR_CH2C_Msk      (0x1UL << IPCC_C1SCR_CH2C_Pos)                /*!< 0x00000002 */
-#define IPCC_C1SCR_CH2C          IPCC_C1SCR_CH2C_Msk                           /*!< M4 receive Channel2 status clear */
-#define IPCC_C1SCR_CH3C_Pos      (2U)
-#define IPCC_C1SCR_CH3C_Msk      (0x1UL << IPCC_C1SCR_CH3C_Pos)                /*!< 0x00000004 */
-#define IPCC_C1SCR_CH3C          IPCC_C1SCR_CH3C_Msk                           /*!< M4 receive Channel3 status clear */
-#define IPCC_C1SCR_CH4C_Pos      (3U)
-#define IPCC_C1SCR_CH4C_Msk      (0x1UL << IPCC_C1SCR_CH4C_Pos)                /*!< 0x00000008 */
-#define IPCC_C1SCR_CH4C          IPCC_C1SCR_CH4C_Msk                           /*!< M4 receive Channel4 status clear */
-#define IPCC_C1SCR_CH5C_Pos      (4U)
-#define IPCC_C1SCR_CH5C_Msk      (0x1UL << IPCC_C1SCR_CH5C_Pos)                /*!< 0x00000010 */
-#define IPCC_C1SCR_CH5C          IPCC_C1SCR_CH5C_Msk                           /*!< M4 receive Channel5 status clear */
-#define IPCC_C1SCR_CH6C_Pos      (5U)
-#define IPCC_C1SCR_CH6C_Msk      (0x1UL << IPCC_C1SCR_CH6C_Pos)                /*!< 0x00000020 */
-#define IPCC_C1SCR_CH6C          IPCC_C1SCR_CH6C_Msk                           /*!< M4 receive Channel6 status clear */
-
-#define IPCC_C1SCR_CH1S_Pos      (16U)
-#define IPCC_C1SCR_CH1S_Msk      (0x1UL << IPCC_C1SCR_CH1S_Pos)                /*!< 0x00010000 */
-#define IPCC_C1SCR_CH1S          IPCC_C1SCR_CH1S_Msk                           /*!< M4 transmit Channel1 status set */
-#define IPCC_C1SCR_CH2S_Pos      (17U)
-#define IPCC_C1SCR_CH2S_Msk      (0x1UL << IPCC_C1SCR_CH2S_Pos)                /*!< 0x00020000 */
-#define IPCC_C1SCR_CH2S          IPCC_C1SCR_CH2S_Msk                           /*!< M4 transmit Channel2 status set  */
-#define IPCC_C1SCR_CH3S_Pos      (18U)
-#define IPCC_C1SCR_CH3S_Msk      (0x1UL << IPCC_C1SCR_CH3S_Pos)                /*!< 0x00040000 */
-#define IPCC_C1SCR_CH3S          IPCC_C1SCR_CH3S_Msk                           /*!< M4 transmit Channel3 status set  */
-#define IPCC_C1SCR_CH4S_Pos      (19U)
-#define IPCC_C1SCR_CH4S_Msk      (0x1UL << IPCC_C1SCR_CH4S_Pos)                /*!< 0x00080000 */
-#define IPCC_C1SCR_CH4S          IPCC_C1SCR_CH4S_Msk                           /*!< M4 transmit Channel4 status set  */
-#define IPCC_C1SCR_CH5S_Pos      (20U)
-#define IPCC_C1SCR_CH5S_Msk      (0x1UL << IPCC_C1SCR_CH5S_Pos)                /*!< 0x00100000 */
-#define IPCC_C1SCR_CH5S          IPCC_C1SCR_CH5S_Msk                           /*!< M4 transmit Channel5 status set  */
-#define IPCC_C1SCR_CH6S_Pos      (21U)
-#define IPCC_C1SCR_CH6S_Msk      (0x1UL << IPCC_C1SCR_CH6S_Pos)                /*!< 0x00200000 */
-#define IPCC_C1SCR_CH6S          IPCC_C1SCR_CH6S_Msk                           /*!< M4 transmit Channel6 status set  */
-
-/**********************  Bit definition for IPCC_C1TOC2SR register  ***************/
-#define IPCC_C1TOC2SR_CH1F_Pos    (0U)
-#define IPCC_C1TOC2SR_CH1F_Msk    (0x1UL << IPCC_C1TOC2SR_CH1F_Pos)            /*!< 0x00000001 */
-#define IPCC_C1TOC2SR_CH1F        IPCC_C1TOC2SR_CH1F_Msk                       /*!< M4 transmit to M4 receive Channel1 status flag before masking */
-#define IPCC_C1TOC2SR_CH2F_Pos    (1U)
-#define IPCC_C1TOC2SR_CH2F_Msk    (0x1UL << IPCC_C1TOC2SR_CH2F_Pos)            /*!< 0x00000002 */
-#define IPCC_C1TOC2SR_CH2F        IPCC_C1TOC2SR_CH2F_Msk                       /*!< M4 transmit to M4 receive Channel2 status flag before masking */
-#define IPCC_C1TOC2SR_CH3F_Pos    (2U)
-#define IPCC_C1TOC2SR_CH3F_Msk    (0x1UL << IPCC_C1TOC2SR_CH3F_Pos)            /*!< 0x00000004 */
-#define IPCC_C1TOC2SR_CH3F        IPCC_C1TOC2SR_CH3F_Msk                       /*!< M4 transmit to M4 receive Channel3 status flag before masking */
-#define IPCC_C1TOC2SR_CH4F_Pos    (3U)
-#define IPCC_C1TOC2SR_CH4F_Msk    (0x1UL << IPCC_C1TOC2SR_CH4F_Pos)            /*!< 0x00000008 */
-#define IPCC_C1TOC2SR_CH4F        IPCC_C1TOC2SR_CH4F_Msk                       /*!< M4 transmit to M4 receive Channel4 status flag before masking */
-#define IPCC_C1TOC2SR_CH5F_Pos    (4U)
-#define IPCC_C1TOC2SR_CH5F_Msk    (0x1UL << IPCC_C1TOC2SR_CH5F_Pos)            /*!< 0x00000010 */
-#define IPCC_C1TOC2SR_CH5F        IPCC_C1TOC2SR_CH5F_Msk                       /*!< M4 transmit to M4 receive Channel5 status flag before masking */
-#define IPCC_C1TOC2SR_CH6F_Pos    (5U)
-#define IPCC_C1TOC2SR_CH6F_Msk    (0x1UL << IPCC_C1TOC2SR_CH6F_Pos)            /*!< 0x00000020 */
-#define IPCC_C1TOC2SR_CH6F        IPCC_C1TOC2SR_CH6F_Msk                       /*!< M4 transmit to M4 receive Channel6 status flag before masking */
-
-/**********************  Bit definition for IPCC_C2CR register  ***************/
-#define IPCC_C2CR_RXOIE_Pos      (0U)
-#define IPCC_C2CR_RXOIE_Msk      (0x1UL << IPCC_C2CR_RXOIE_Pos)                /*!< 0x00000001 */
-#define IPCC_C2CR_RXOIE          IPCC_C2CR_RXOIE_Msk                           /*!< Processor M0+ Receive channel occupied interrupt enable */
-#define IPCC_C2CR_TXFIE_Pos      (16U)
-#define IPCC_C2CR_TXFIE_Msk      (0x1UL << IPCC_C2CR_TXFIE_Pos)                /*!< 0x00010000 */
-#define IPCC_C2CR_TXFIE          IPCC_C2CR_TXFIE_Msk                           /*!< Processor M0+ Transmit channel free interrupt enable */
-
-/**********************  Bit definition for IPCC_C2MR register  ***************/
-#define IPCC_C2MR_CH1OM_Pos      (0U)
-#define IPCC_C2MR_CH1OM_Msk      (0x1UL << IPCC_C2MR_CH1OM_Pos)                /*!< 0x00000001 */
-#define IPCC_C2MR_CH1OM          IPCC_C2MR_CH1OM_Msk                           /*!< M0+ Channel1 occupied interrupt mask */
-#define IPCC_C2MR_CH2OM_Pos      (1U)
-#define IPCC_C2MR_CH2OM_Msk      (0x1UL << IPCC_C2MR_CH2OM_Pos)                /*!< 0x00000002 */
-#define IPCC_C2MR_CH2OM          IPCC_C2MR_CH2OM_Msk                           /*!< M0+ Channel2 occupied interrupt mask */
-#define IPCC_C2MR_CH3OM_Pos      (2U)
-#define IPCC_C2MR_CH3OM_Msk      (0x1UL << IPCC_C2MR_CH3OM_Pos)                /*!< 0x00000004 */
-#define IPCC_C2MR_CH3OM          IPCC_C2MR_CH3OM_Msk                           /*!< M0+ Channel3 occupied interrupt mask */
-#define IPCC_C2MR_CH4OM_Pos      (3U)
-#define IPCC_C2MR_CH4OM_Msk      (0x1UL << IPCC_C2MR_CH4OM_Pos)                /*!< 0x00000008 */
-#define IPCC_C2MR_CH4OM          IPCC_C2MR_CH4OM_Msk                           /*!< M0+ Channel4 occupied interrupt mask */
-#define IPCC_C2MR_CH5OM_Pos      (4U)
-#define IPCC_C2MR_CH5OM_Msk      (0x1UL << IPCC_C2MR_CH5OM_Pos)                /*!< 0x00000010 */
-#define IPCC_C2MR_CH5OM          IPCC_C2MR_CH5OM_Msk                           /*!< M0+ Channel5 occupied interrupt mask */
-#define IPCC_C2MR_CH6OM_Pos      (5U)
-#define IPCC_C2MR_CH6OM_Msk      (0x1UL << IPCC_C2MR_CH6OM_Pos)                /*!< 0x00000020 */
-#define IPCC_C2MR_CH6OM          IPCC_C2MR_CH6OM_Msk                           /*!< M0+ Channel6 occupied interrupt mask */
-
-#define IPCC_C2MR_CH1FM_Pos      (16U)
-#define IPCC_C2MR_CH1FM_Msk      (0x1UL << IPCC_C2MR_CH1FM_Pos)                /*!< 0x00010000 */
-#define IPCC_C2MR_CH1FM          IPCC_C2MR_CH1FM_Msk                           /*!< M0+ Transmit Channel1 free interrupt mask */
-#define IPCC_C2MR_CH2FM_Pos      (17U)
-#define IPCC_C2MR_CH2FM_Msk      (0x1UL << IPCC_C2MR_CH2FM_Pos)                /*!< 0x00020000 */
-#define IPCC_C2MR_CH2FM          IPCC_C2MR_CH2FM_Msk                           /*!< M0+ Transmit Channel2 free interrupt mask */
-#define IPCC_C2MR_CH3FM_Pos      (18U)
-#define IPCC_C2MR_CH3FM_Msk      (0x1UL << IPCC_C2MR_CH3FM_Pos)                /*!< 0x00040000 */
-#define IPCC_C2MR_CH3FM          IPCC_C2MR_CH3FM_Msk                           /*!< M0+ Transmit Channel3 free interrupt mask */
-#define IPCC_C2MR_CH4FM_Pos      (19U)
-#define IPCC_C2MR_CH4FM_Msk      (0x1UL << IPCC_C2MR_CH4FM_Pos)                /*!< 0x00080000 */
-#define IPCC_C2MR_CH4FM          IPCC_C2MR_CH4FM_Msk                           /*!< M0+ Transmit Channel4 free interrupt mask */
-#define IPCC_C2MR_CH5FM_Pos      (20U)
-#define IPCC_C2MR_CH5FM_Msk      (0x1UL << IPCC_C2MR_CH5FM_Pos)                /*!< 0x00100000 */
-#define IPCC_C2MR_CH5FM          IPCC_C2MR_CH5FM_Msk                           /*!< M0+ Transmit Channel5 free interrupt mask */
-#define IPCC_C2MR_CH6FM_Pos      (21U)
-#define IPCC_C2MR_CH6FM_Msk      (0x1UL << IPCC_C2MR_CH6FM_Pos)                /*!< 0x00200000 */
-#define IPCC_C2MR_CH6FM          IPCC_C2MR_CH6FM_Msk                           /*!< M0+ Transmit Channel6 free interrupt mask */
-
-/**********************  Bit definition for IPCC_C2SCR register  ***************/
-#define IPCC_C2SCR_CH1C_Pos      (0U)
-#define IPCC_C2SCR_CH1C_Msk      (0x1UL << IPCC_C2SCR_CH1C_Pos)                /*!< 0x00000001 */
-#define IPCC_C2SCR_CH1C          IPCC_C2SCR_CH1C_Msk                           /*!< M0+ receive Channel1 status clear */
-#define IPCC_C2SCR_CH2C_Pos      (1U)
-#define IPCC_C2SCR_CH2C_Msk      (0x1UL << IPCC_C2SCR_CH2C_Pos)                /*!< 0x00000002 */
-#define IPCC_C2SCR_CH2C          IPCC_C2SCR_CH2C_Msk                           /*!< M0+ receive Channel2 status clear */
-#define IPCC_C2SCR_CH3C_Pos      (2U)
-#define IPCC_C2SCR_CH3C_Msk      (0x1UL << IPCC_C2SCR_CH3C_Pos)                /*!< 0x00000004 */
-#define IPCC_C2SCR_CH3C          IPCC_C2SCR_CH3C_Msk                           /*!< M0+ receive Channel3 status clear */
-#define IPCC_C2SCR_CH4C_Pos      (3U)
-#define IPCC_C2SCR_CH4C_Msk      (0x1UL << IPCC_C2SCR_CH4C_Pos)                /*!< 0x00000008 */
-#define IPCC_C2SCR_CH4C          IPCC_C2SCR_CH4C_Msk                           /*!< M0+ receive Channel4 status clear */
-#define IPCC_C2SCR_CH5C_Pos      (4U)
-#define IPCC_C2SCR_CH5C_Msk      (0x1UL << IPCC_C2SCR_CH5C_Pos)                /*!< 0x00000010 */
-#define IPCC_C2SCR_CH5C          IPCC_C2SCR_CH5C_Msk                           /*!< M0+ receive Channel5 status clear */
-#define IPCC_C2SCR_CH6C_Pos      (5U)
-#define IPCC_C2SCR_CH6C_Msk      (0x1UL << IPCC_C2SCR_CH6C_Pos)                /*!< 0x00000020 */
-#define IPCC_C2SCR_CH6C          IPCC_C2SCR_CH6C_Msk                           /*!< M0+ receive Channel6 status clear */
-
-#define IPCC_C2SCR_CH1S_Pos      (16U)
-#define IPCC_C2SCR_CH1S_Msk      (0x1UL << IPCC_C2SCR_CH1S_Pos)                /*!< 0x00010000 */
-#define IPCC_C2SCR_CH1S          IPCC_C2SCR_CH1S_Msk                           /*!< M0+ transmit Channel1 status set  */
-#define IPCC_C2SCR_CH2S_Pos      (17U)
-#define IPCC_C2SCR_CH2S_Msk      (0x1UL << IPCC_C2SCR_CH2S_Pos)                /*!< 0x00020000 */
-#define IPCC_C2SCR_CH2S          IPCC_C2SCR_CH2S_Msk                           /*!< M0+ transmit Channel2 status set  */
-#define IPCC_C2SCR_CH3S_Pos      (18U)
-#define IPCC_C2SCR_CH3S_Msk      (0x1UL << IPCC_C2SCR_CH3S_Pos)                /*!< 0x00040000 */
-#define IPCC_C2SCR_CH3S          IPCC_C2SCR_CH3S_Msk                           /*!< M0+ transmit Channel3 status set  */
-#define IPCC_C2SCR_CH4S_Pos      (19U)
-#define IPCC_C2SCR_CH4S_Msk      (0x1UL << IPCC_C2SCR_CH4S_Pos)                /*!< 0x00080000 */
-#define IPCC_C2SCR_CH4S          IPCC_C2SCR_CH4S_Msk                           /*!< M0+ transmit Channel4 status set  */
-#define IPCC_C2SCR_CH5S_Pos      (20U)
-#define IPCC_C2SCR_CH5S_Msk      (0x1UL << IPCC_C2SCR_CH5S_Pos)                /*!< 0x00100000 */
-#define IPCC_C2SCR_CH5S          IPCC_C2SCR_CH5S_Msk                           /*!< M0+ transmit Channel5 status set  */
-#define IPCC_C2SCR_CH6S_Pos      (21U)
-#define IPCC_C2SCR_CH6S_Msk      (0x1UL << IPCC_C2SCR_CH6S_Pos)                /*!< 0x00200000 */
-#define IPCC_C2SCR_CH6S          IPCC_C2SCR_CH6S_Msk                           /*!< M0+ transmit Channel6 status set  */
-
-/**********************  Bit definition for IPCC_C2TOC1SR register  ***************/
-#define IPCC_C2TOC1SR_CH1F_Pos    (0U)
-#define IPCC_C2TOC1SR_CH1F_Msk    (0x1UL << IPCC_C2TOC1SR_CH1F_Pos)            /*!< 0x00000001 */
-#define IPCC_C2TOC1SR_CH1F        IPCC_C2TOC1SR_CH1F_Msk                       /*!< M0+ transmit to M0 receive Channel1 status flag before masking */
-#define IPCC_C2TOC1SR_CH2F_Pos    (1U)
-#define IPCC_C2TOC1SR_CH2F_Msk    (0x1UL << IPCC_C2TOC1SR_CH2F_Pos)            /*!< 0x00000002 */
-#define IPCC_C2TOC1SR_CH2F        IPCC_C2TOC1SR_CH2F_Msk                       /*!< M0+ transmit to M0 receive Channel2 status flag before masking */
-#define IPCC_C2TOC1SR_CH3F_Pos    (2U)
-#define IPCC_C2TOC1SR_CH3F_Msk    (0x1UL << IPCC_C2TOC1SR_CH3F_Pos)            /*!< 0x00000004 */
-#define IPCC_C2TOC1SR_CH3F        IPCC_C2TOC1SR_CH3F_Msk                       /*!< M0+ transmit to M0 receive Channel3 status flag before masking */
-#define IPCC_C2TOC1SR_CH4F_Pos    (3U)
-#define IPCC_C2TOC1SR_CH4F_Msk    (0x1UL << IPCC_C2TOC1SR_CH4F_Pos)            /*!< 0x00000008 */
-#define IPCC_C2TOC1SR_CH4F        IPCC_C2TOC1SR_CH4F_Msk                       /*!< M0+ transmit to M0 receive Channel4 status flag before masking */
-#define IPCC_C2TOC1SR_CH5F_Pos    (4U)
-#define IPCC_C2TOC1SR_CH5F_Msk    (0x1UL << IPCC_C2TOC1SR_CH5F_Pos)            /*!< 0x00000010 */
-#define IPCC_C2TOC1SR_CH5F        IPCC_C2TOC1SR_CH5F_Msk                       /*!< M0+ transmit to M0 receive Channel5 status flag before masking */
-#define IPCC_C2TOC1SR_CH6F_Pos    (5U)
-#define IPCC_C2TOC1SR_CH6F_Msk    (0x1UL << IPCC_C2TOC1SR_CH6F_Pos)            /*!< 0x00000020 */
-#define IPCC_C2TOC1SR_CH6F        IPCC_C2TOC1SR_CH6F_Msk                       /*!< M0+ transmit to M0 receive Channel6 status flag before masking */
-
-/**********************  Bit definition for IPCC_C1CR register  ***************/
-#define IPCC_CR_RXOIE_Pos         IPCC_C1CR_RXOIE_Pos
-#define IPCC_CR_RXOIE_Msk         IPCC_C1CR_RXOIE_Msk
-#define IPCC_CR_RXOIE             IPCC_C1CR_RXOIE
-#define IPCC_CR_TXFIE_Pos         IPCC_C1CR_TXFIE_Pos
-#define IPCC_CR_TXFIE_Msk         IPCC_C1CR_TXFIE_Msk
-#define IPCC_CR_TXFIE             IPCC_C1CR_TXFIE
-
-/**********************  Bit definition for IPCC_C1MR register  **************/
-#define IPCC_MR_CH1OM_Pos         IPCC_C1MR_CH1OM_Pos
-#define IPCC_MR_CH1OM_Msk         IPCC_C1MR_CH1OM_Msk
-#define IPCC_MR_CH1OM             IPCC_C1MR_CH1OM
-#define IPCC_MR_CH2OM_Pos         IPCC_C1MR_CH2OM_Pos
-#define IPCC_MR_CH2OM_Msk         IPCC_C1MR_CH2OM_Msk
-#define IPCC_MR_CH2OM             IPCC_C1MR_CH2OM
-#define IPCC_MR_CH3OM_Pos         IPCC_C1MR_CH3OM_Pos
-#define IPCC_MR_CH3OM_Msk         IPCC_C1MR_CH3OM_Msk
-#define IPCC_MR_CH3OM             IPCC_C1MR_CH3OM
-#define IPCC_MR_CH4OM_Pos         IPCC_C1MR_CH4OM_Pos
-#define IPCC_MR_CH4OM_Msk         IPCC_C1MR_CH4OM_Msk
-#define IPCC_MR_CH4OM             IPCC_C1MR_CH4OM
-#define IPCC_MR_CH5OM_Pos         IPCC_C1MR_CH5OM_Pos
-#define IPCC_MR_CH5OM_Msk         IPCC_C1MR_CH5OM_Msk
-#define IPCC_MR_CH5OM             IPCC_C1MR_CH5OM
-#define IPCC_MR_CH6OM_Pos         IPCC_C1MR_CH6OM_Pos
-#define IPCC_MR_CH6OM_Msk         IPCC_C1MR_CH6OM_Msk
-#define IPCC_MR_CH6OM             IPCC_C1MR_CH6OM
-
-#define IPCC_MR_CH1FM_Pos         IPCC_C1MR_CH1FM_Pos
-#define IPCC_MR_CH1FM_Msk         IPCC_C1MR_CH1FM_Msk
-#define IPCC_MR_CH1FM             IPCC_C1MR_CH1FM
-#define IPCC_MR_CH2FM_Pos         IPCC_C1MR_CH2FM_Pos
-#define IPCC_MR_CH2FM_Msk         IPCC_C1MR_CH2FM_Msk
-#define IPCC_MR_CH2FM             IPCC_C1MR_CH2FM
-#define IPCC_MR_CH3FM_Pos         IPCC_C1MR_CH3FM_Pos
-#define IPCC_MR_CH3FM_Msk         IPCC_C1MR_CH3FM_Msk
-#define IPCC_MR_CH3FM             IPCC_C1MR_CH3FM
-#define IPCC_MR_CH4FM_Pos         IPCC_C1MR_CH4FM_Pos
-#define IPCC_MR_CH4FM_Msk         IPCC_C1MR_CH4FM_Msk
-#define IPCC_MR_CH4FM             IPCC_C1MR_CH4FM
-#define IPCC_MR_CH5FM_Pos         IPCC_C1MR_CH5FM_Pos
-#define IPCC_MR_CH5FM_Msk         IPCC_C1MR_CH5FM_Msk
-#define IPCC_MR_CH5FM             IPCC_C1MR_CH5FM
-#define IPCC_MR_CH6FM_Pos         IPCC_C1MR_CH6FM_Pos
-#define IPCC_MR_CH6FM_Msk         IPCC_C1MR_CH6FM_Msk
-#define IPCC_MR_CH6FM             IPCC_C1MR_CH6FM
-
-/**********************  Bit definition for IPCC_C1SCR register  ***************/
-#define IPCC_SCR_CH1C_Pos         IPCC_C1SCR_CH1C_Pos
-#define IPCC_SCR_CH1C_Msk         IPCC_C1SCR_CH1C_Msk
-#define IPCC_SCR_CH1C             IPCC_C1SCR_CH1C
-#define IPCC_SCR_CH2C_Pos         IPCC_C1SCR_CH2C_Pos
-#define IPCC_SCR_CH2C_Msk         IPCC_C1SCR_CH2C_Msk
-#define IPCC_SCR_CH2C             IPCC_C1SCR_CH2C
-#define IPCC_SCR_CH3C_Pos         IPCC_C1SCR_CH3C_Pos
-#define IPCC_SCR_CH3C_Msk         IPCC_C1SCR_CH3C_Msk
-#define IPCC_SCR_CH3C             IPCC_C1SCR_CH3C
-#define IPCC_SCR_CH4C_Pos         IPCC_C1SCR_CH4C_Pos
-#define IPCC_SCR_CH4C_Msk         IPCC_C1SCR_CH4C_Msk
-#define IPCC_SCR_CH4C             IPCC_C1SCR_CH4C
-#define IPCC_SCR_CH5C_Pos         IPCC_C1SCR_CH5C_Pos
-#define IPCC_SCR_CH5C_Msk         IPCC_C1SCR_CH5C_Msk
-#define IPCC_SCR_CH5C             IPCC_C1SCR_CH5C
-#define IPCC_SCR_CH6C_Pos         IPCC_C1SCR_CH6C_Pos
-#define IPCC_SCR_CH6C_Msk         IPCC_C1SCR_CH6C_Msk
-#define IPCC_SCR_CH6C             IPCC_C1SCR_CH6C
-
-#define IPCC_SCR_CH1S_Pos         IPCC_C1SCR_CH1S_Pos
-#define IPCC_SCR_CH1S_Msk         IPCC_C1SCR_CH1S_Msk
-#define IPCC_SCR_CH1S             IPCC_C1SCR_CH1S
-#define IPCC_SCR_CH2S_Pos         IPCC_C1SCR_CH2S_Pos
-#define IPCC_SCR_CH2S_Msk         IPCC_C1SCR_CH2S_Msk
-#define IPCC_SCR_CH2S             IPCC_C1SCR_CH2S
-#define IPCC_SCR_CH3S_Pos         IPCC_C1SCR_CH3S_Pos
-#define IPCC_SCR_CH3S_Msk         IPCC_C1SCR_CH3S_Msk
-#define IPCC_SCR_CH3S             IPCC_C1SCR_CH3S
-#define IPCC_SCR_CH4S_Pos         IPCC_C1SCR_CH4S_Pos
-#define IPCC_SCR_CH4S_Msk         IPCC_C1SCR_CH4S_Msk
-#define IPCC_SCR_CH4S             IPCC_C1SCR_CH4S
-#define IPCC_SCR_CH5S_Pos         IPCC_C1SCR_CH5S_Pos
-#define IPCC_SCR_CH5S_Msk         IPCC_C1SCR_CH5S_Msk
-#define IPCC_SCR_CH5S             IPCC_C1SCR_CH5S
-#define IPCC_SCR_CH6S_Pos         IPCC_C1SCR_CH6S_Pos
-#define IPCC_SCR_CH6S_Msk         IPCC_C1SCR_CH6S_Msk
-#define IPCC_SCR_CH6S             IPCC_C1SCR_CH6S
-
-/**********************  Bit definition for IPCC_C1TOC2SR register  ***************/
-#define IPCC_SR_CH1F_Pos          IPCC_C1TOC2SR_CH1F_Pos
-#define IPCC_SR_CH1F_Msk          IPCC_C1TOC2SR_CH1F_Msk
-#define IPCC_SR_CH1F              IPCC_C1TOC2SR_CH1F
-#define IPCC_SR_CH2F_Pos          IPCC_C1TOC2SR_CH2F_Pos
-#define IPCC_SR_CH2F_Msk          IPCC_C1TOC2SR_CH2F_Msk
-#define IPCC_SR_CH2F              IPCC_C1TOC2SR_CH2F
-#define IPCC_SR_CH3F_Pos          IPCC_C1TOC2SR_CH3F_Pos
-#define IPCC_SR_CH3F_Msk          IPCC_C1TOC2SR_CH3F_Msk
-#define IPCC_SR_CH3F              IPCC_C1TOC2SR_CH3F
-#define IPCC_SR_CH4F_Pos          IPCC_C1TOC2SR_CH4F_Pos
-#define IPCC_SR_CH4F_Msk          IPCC_C1TOC2SR_CH4F_Msk
-#define IPCC_SR_CH4F              IPCC_C1TOC2SR_CH4F
-#define IPCC_SR_CH5F_Pos          IPCC_C1TOC2SR_CH5F_Pos
-#define IPCC_SR_CH5F_Msk          IPCC_C1TOC2SR_CH5F_Msk
-#define IPCC_SR_CH5F              IPCC_C1TOC2SR_CH5F
-#define IPCC_SR_CH6F_Pos          IPCC_C1TOC2SR_CH6F_Pos
-#define IPCC_SR_CH6F_Msk          IPCC_C1TOC2SR_CH6F_Msk
-#define IPCC_SR_CH6F              IPCC_C1TOC2SR_CH6F
-
-/******************** Number of IPCC channels ******************************/
-#define IPCC_CHANNEL_NUMBER       6U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 VREFBUF                                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for VREFBUF_CSR register  ****************/
-#define VREFBUF_CSR_ENVR_Pos    (0U)
-#define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                /*!< 0x00000001 */
-#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
-#define VREFBUF_CSR_HIZ_Pos     (1U)
-#define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                 /*!< 0x00000002 */
-#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
-#define VREFBUF_CSR_VRS_Pos     (2U)
-#define VREFBUF_CSR_VRS_Msk     (0x1UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000004 */
-#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference buffer ready  */
-#define VREFBUF_CSR_VRR_Pos     (3U)
-#define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                 /*!< 0x00000008 */
-#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference scale         */
-
-/*******************  Bit definition for VREFBUF_CCR register  ******************/
-#define VREFBUF_CCR_TRIM_Pos    (0U)
-#define VREFBUF_CCR_TRIM_Msk    (0x3FUL << VREFBUF_CCR_TRIM_Pos)               /*!< 0x0000003F */
-#define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
-
-#define WWDG_CR_WDGA_Pos        (7U)
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
-
-#define WWDG_CFR_EWI_Pos        (9U)
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
-
-#define WWDG_CFR_WDGTB_Pos      (11U)
-#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000800 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00001000 */
-#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00002000 */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
-
-
-#if defined(CORE_CM0PLUS)
-#else
-/******************************************************************************/
-/*                                                                            */
-/*                                Debug MCU                                   */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                          (0U)
-#define DBGMCU_IDCODE_DEV_ID_Msk                          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                              DBGMCU_IDCODE_DEV_ID_Msk
-#define DBGMCU_IDCODE_REV_ID_Pos                          (16U)
-#define DBGMCU_IDCODE_REV_ID_Msk                          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                              DBGMCU_IDCODE_REV_ID_Msk
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                           (0U)
-#define DBGMCU_CR_DBG_SLEEP_Msk                           (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)  /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                               DBGMCU_CR_DBG_SLEEP_Msk
-#define DBGMCU_CR_DBG_STOP_Pos                            (1U)
-#define DBGMCU_CR_DBG_STOP_Msk                            (0x1UL << DBGMCU_CR_DBG_STOP_Pos)   /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                                DBGMCU_CR_DBG_STOP_Msk
-#define DBGMCU_CR_DBG_STANDBY_Pos                         (2U)
-#define DBGMCU_CR_DBG_STANDBY_Msk                         (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                             DBGMCU_CR_DBG_STANDBY_Msk
-
-/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos                 (0U)
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)  /*!< 0x00000001 */
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP                     DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos                  (10U)
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk                  (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)   /*!< 0x00000400 */
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP                      DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos                 (11U)
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)  /*!< 0x00000800 */
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP                     DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos                 (12U)
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)  /*!< 0x00001000 */
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP                     DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos                 (21U)
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)  /*!< 0x00200000 */
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP                     DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos                 (22U)
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)  /*!< 0x00400000 */
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP                     DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos                 (23U)
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)  /*!< 0x00800000 */
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP                     DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos               (31U)
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk               (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP                   DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
-
-/********************  Bit definition for DBGMCU_C2APB1FZR1 register  ***********/
-#define DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Pos               (0U)
-#define DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Msk               (0x1UL << DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Pos)  /*!< 0x00000001 */
-#define DBGMCU_C2APB1FZR1_DBG_TIM2_STOP                   DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Msk
-#define DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Pos                (10U)
-#define DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Msk                (0x1UL << DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Pos)   /*!< 0x00000400 */
-#define DBGMCU_C2APB1FZR1_DBG_RTC_STOP                    DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Msk
-#define DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Pos               (12U)
-#define DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Msk               (0x1UL << DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Pos)  /*!< 0x00001000 */
-#define DBGMCU_C2APB1FZR1_DBG_IWDG_STOP                   DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Msk
-#define DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Pos               (21U)
-#define DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Msk               (0x1UL << DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Pos)  /*!< 0x00200000 */
-#define DBGMCU_C2APB1FZR1_DBG_I2C1_STOP                   DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Msk
-#define DBGMCU_C2APB1FZR1_DBG_I2C2_STOP_Pos               (22U)
-#define DBGMCU_C2APB1FZR1_DBG_I2C2_STOP_Msk               (0x1UL << DBGMCU_C2APB1FZR1_DBG_I2C2_STOP_Pos)  /*!< 0x00400000 */
-#define DBGMCU_C2APB1FZR1_DBG_I2C2_STOP                   DBGMCU_C2APB1FZR1_DBG_I2C2_STOP_Msk
-#define DBGMCU_C2APB1FZR1_DBG_I2C3_STOP_Pos               (23U)
-#define DBGMCU_C2APB1FZR1_DBG_I2C3_STOP_Msk               (0x1UL << DBGMCU_C2APB1FZR1_DBG_I2C3_STOP_Pos)  /*!< 0x00800000 */
-#define DBGMCU_C2APB1FZR1_DBG_I2C3_STOP                   DBGMCU_C2APB1FZR1_DBG_I2C3_STOP_Msk
-#define DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Pos             (31U)
-#define DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Msk             (0x1UL << DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
-#define DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP                 DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Msk
-
-/********************  Bit definition for DBGMCU_APB1FZR2 register  ***********/
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos               (5U)
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk               (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)/*!< 0x00000020 */
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP                   DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
-#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Pos               (6U)
-#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk               (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Pos)/*!< 0x00000040 */
-#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP                   DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk
-
-/********************  Bit definition for DBGMCU_C2APB1FZR2 register  ***********/
-#define DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Pos             (5U)
-#define DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Msk             (0x1UL << DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Pos)/*!< 0x00000020 */
-#define DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP                 DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Msk
-#define DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP_Pos             (6U)
-#define DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP_Msk             (0x1UL << DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP_Pos)/*!< 0x00000040 */
-#define DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP                 DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP_Msk
-
-/********************  Bit definition for DBGMCU_APB2FZR register  ************/
-#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos                  (11U)
-#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk                  (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)/*!< 0x000000800 */
-#define DBGMCU_APB2FZR_DBG_TIM1_STOP                      DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk
-#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos                 (17U)
-#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk                 (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
-#define DBGMCU_APB2FZR_DBG_TIM16_STOP                     DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk
-#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos                 (18U)
-#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk                 (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
-#define DBGMCU_APB2FZR_DBG_TIM17_STOP                     DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk
-
-/********************  Bit definition for DBGMCU_C2APB2FZR register  ************/
-#define DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Pos                (11U)
-#define DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Msk                (0x1UL << DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Pos)/*!< 0x000000800 */
-#define DBGMCU_C2APB2FZR_DBG_TIM1_STOP                    DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Msk
-#define DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Pos               (17U)
-#define DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Msk               (0x1UL << DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
-#define DBGMCU_C2APB2FZR_DBG_TIM16_STOP                   DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Msk
-#define DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Pos               (18U)
-#define DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Msk               (0x1UL << DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
-#define DBGMCU_C2APB2FZR_DBG_TIM17_STOP                   DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Msk
-
-#endif
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
-
-#define TIM_CR1_UIFREMAP_Pos      (11U)
-#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
-#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCPC_Pos          (0U)
-#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
-#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS_Pos          (2U)
-#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
-#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS_Pos          (3U)
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-#define TIM_CR2_OIS1_Pos          (8U)
-#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
-#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N_Pos         (9U)
-#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
-#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2_Pos          (10U)
-#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
-#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N_Pos         (11U)
-#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
-#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3_Pos          (12U)
-#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
-#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N_Pos         (13U)
-#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
-#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4_Pos          (14U)
-#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
-#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS5_Pos          (16U)
-#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
-#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
-#define TIM_CR2_OIS6_Pos          (18U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
-#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
-
-#define TIM_CR2_MMS2_Pos          (20U)
-#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
-#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
-#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
-#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
-#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)
-#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
-#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
-
-#define TIM_SMCR_OCCS_Pos         (3U)
-#define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
-#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos           (4U)
-#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
-#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
-#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
-
-#define TIM_SMCR_MSM_Pos          (7U)
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE_Pos        (5U)
-#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
-#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_BIE_Pos          (7U)
-#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
-#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE_Pos        (13U)
-#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
-#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF_Pos          (5U)
-#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
-#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF_Pos            (7U)
-#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
-#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
-#define TIM_SR_B2IF_Pos           (8U)
-#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
-#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-#define TIM_SR_SBIF_Pos           (13U)
-#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
-#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
-#define TIM_SR_CC5IF_Pos          (16U)
-#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
-#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
-#define TIM_SR_CC6IF_Pos          (17U)
-#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
-#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
-
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG_Pos          (5U)
-#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
-#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG_Pos            (6U)
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-#define TIM_EGR_BG_Pos            (7U)
-#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
-#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
-#define TIM_EGR_B2G_Pos           (8U)
-#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
-#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)
-#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
-#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)
-#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
-#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-#define TIM_CCMR1_IC1PSC_Pos      (2U)
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
-#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-#define TIM_CCMR2_IC3PSC_Pos      (2U)
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR3 register  *******************/
-#define TIM_CCMR3_OC5FE_Pos       (2U)
-#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
-#define TIM_CCMR3_OC5PE_Pos       (3U)
-#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
-#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
-
-#define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
-#define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
-#define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
-#define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
-#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
-
-#define TIM_CCMR3_OC5CE_Pos       (7U)
-#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
-#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
-
-#define TIM_CCMR3_OC6FE_Pos       (10U)
-#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
-#define TIM_CCMR3_OC6PE_Pos       (11U)
-#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
-#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
-
-#define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
-#define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
-#define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
-#define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
-
-#define TIM_CCMR3_OC6CE_Pos       (15U)
-#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
-#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE_Pos        (2U)
-#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
-#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP_Pos        (3U)
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE_Pos        (6U)
-#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
-#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP_Pos        (7U)
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE_Pos        (10U)
-#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
-#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP_Pos        (11U)
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-#define TIM_CCER_CC5E_Pos         (16U)
-#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
-#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
-#define TIM_CCER_CC5P_Pos         (17U)
-#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
-#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
-#define TIM_CCER_CC6E_Pos         (20U)
-#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
-#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
-#define TIM_CCER_CC6P_Pos         (21U)
-#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
-#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)
-#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-#define TIM_CNT_UIFCPY_Pos        (31U)
-#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
-#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)
-#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define TIM_RCR_REP_Pos           (0U)
-#define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
-#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)
-#define TIM_CCR1_CCR1_Msk         (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)
-#define TIM_CCR2_CCR2_Msk         (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)
-#define TIM_CCR3_CCR3_Msk         (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)
-#define TIM_CCR4_CCR4_Msk         (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_CCR5 register  *******************/
-#define TIM_CCR5_CCR5_Pos         (0U)
-#define TIM_CCR5_CCR5_Msk         (0xFFFFUL << TIM_CCR5_CCR5_Pos)              /*!< 0x0000FFFF */
-#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
-#define TIM_CCR5_GC5C1_Pos        (29U)
-#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
-#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
-#define TIM_CCR5_GC5C2_Pos        (30U)
-#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
-#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
-#define TIM_CCR5_GC5C3_Pos        (31U)
-#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
-#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
-
-/*******************  Bit definition for TIM_CCR6 register  *******************/
-#define TIM_CCR6_CCR6_Pos         (0U)
-#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
-#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define TIM_BDTR_DTG_Pos          (0U)
-#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
-#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
-#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
-#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
-#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
-#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
-#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
-#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
-#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
-
-#define TIM_BDTR_LOCK_Pos         (8U)
-#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
-#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
-#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
-
-#define TIM_BDTR_OSSI_Pos         (10U)
-#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
-#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR_Pos         (11U)
-#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
-#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE_Pos          (12U)
-#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
-#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
-#define TIM_BDTR_BKP_Pos          (13U)
-#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
-#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
-#define TIM_BDTR_AOE_Pos          (14U)
-#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
-#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
-#define TIM_BDTR_MOE_Pos          (15U)
-#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
-#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
-
-#define TIM_BDTR_BKF_Pos          (16U)
-#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
-#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
-#define TIM_BDTR_BK2F_Pos         (20U)
-#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
-#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
-
-#define TIM_BDTR_BK2E_Pos         (24U)
-#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
-#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
-#define TIM_BDTR_BK2P_Pos         (25U)
-#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
-#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
-
-
-#define TIM_BDTR_BKDSRM_Pos       (26U)
-#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
-#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
-#define TIM_BDTR_BK2DSRM_Pos      (27U)
-#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
-#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
-
-#define TIM_BDTR_BKBID_Pos        (28U)
-#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
-#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
-#define TIM_BDTR_BK2BID_Pos       (29U)
-#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
-#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM1_OR1 register  ******************/
-#define TIM1_OR1_ETR_ADC_RMP_Pos   (0U)
-#define TIM1_OR1_ETR_ADC_RMP_Msk   (0x3UL << TIM1_OR1_ETR_ADC_RMP_Pos)         /*!< 0x00000003 */
-#define TIM1_OR1_ETR_ADC_RMP       TIM1_OR1_ETR_ADC_RMP_Msk                    /*!< TIM1_ETR_ADC remapping capability */
-#define TIM1_OR1_ETR_ADC_RMP_0     (0x1UL << TIM1_OR1_ETR_ADC_RMP_Pos)         /*!< 0x00000001 */
-#define TIM1_OR1_ETR_ADC_RMP_1     (0x2UL << TIM1_OR1_ETR_ADC_RMP_Pos)         /*!< 0x00000002 */
-#define TIM1_OR1_TI1_RMP_Pos       (4U)
-#define TIM1_OR1_TI1_RMP_Msk       (0x1UL << TIM1_OR1_TI1_RMP_Pos)             /*!< 0x00000010 */
-#define TIM1_OR1_TI1_RMP           TIM1_OR1_TI1_RMP_Msk                        /*!< Input Capture 1 remap*/
-
-/*******************  Bit definition for TIM2_OR1 register  ******************/
-#define TIM2_OR1_TI4_RMP_Pos       (2U)
-#define TIM2_OR1_TI4_RMP_Msk       (0x3UL << TIM2_OR1_TI4_RMP_Pos)             /*!< 0x0000000C */
-#define TIM2_OR1_TI4_RMP           TIM2_OR1_TI4_RMP_Msk                        /*!< TI4 RMA[1:0]Input capture 4 remap*/
-#define TIM2_OR1_TI4_RMP_0         (0x1UL << TIM2_OR1_TI4_RMP_Pos)             /*!< 0x00000004 */
-#define TIM2_OR1_TI4_RMP_1         (0x2UL << TIM2_OR1_TI4_RMP_Pos)             /*!< 0x00000008 */
-#define TIM2_OR1_ETR_RMP_Pos       (1U)
-#define TIM2_OR1_ETR_RMP_Msk       (0x1UL << TIM2_OR1_ETR_RMP_Pos)             /*!< 0x00000002 */
-#define TIM2_OR1_ETR_RMP           TIM2_OR1_ETR_RMP_Msk                        /*!< External trigger remap*/
-
-/*******************  Bit definition for TIM16_OR1 register  *****************/
-#define TIM16_OR1_TI1_RMP_Pos      (0U)
-#define TIM16_OR1_TI1_RMP_Msk      (0x3UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000003 */
-#define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<Timer 16 input 1 connection. */
-#define TIM16_OR1_TI1_RMP_0        (0x1UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */
-#define TIM16_OR1_TI1_RMP_1        (0x2UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */
-
-/*******************  Bit definition for TIM17_OR1 register  *****************/
-#define TIM17_OR1_TI1_RMP_Pos      (0U)
-#define TIM17_OR1_TI1_RMP_Msk      (0x3UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000003 */
-#define TIM17_OR1_TI1_RMP          TIM17_OR1_TI1_RMP_Msk                       /*!<Timer 17 input 1 connection. */
-#define TIM17_OR1_TI1_RMP_0        (0x1UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */
-#define TIM17_OR1_TI1_RMP_1        (0x2UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */
-
-/*******************  Bit definition for TIM1_AF1 register  *******************/
-#define TIM1_AF1_BKINE_Pos        (0U)
-#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
-#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
-#define TIM1_AF1_BKCMP1E_Pos      (1U)                                         
-#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
-#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
-#define TIM1_AF1_BKCMP2E_Pos      (2U)                                         
-#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
-#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
-#define TIM1_AF1_BKINP_Pos        (9U)                                         
-#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
-#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
-#define TIM1_AF1_BKCMP1P_Pos      (10U)                                        
-#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
-#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
-#define TIM1_AF1_BKCMP2P_Pos      (11U)                                        
-#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
-#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
-#define TIM1_AF1_ETRSEL_Pos       (14U)                                        
-#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
-#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
-#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
-#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
-#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
-#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
-
-/*******************  Bit definition for TIM2_AF1 register  *******************/
-#define TIM2_AF1_ETRSEL_Pos       (14U)
-#define TIM2_AF1_ETRSEL_Msk       (0xFUL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
-#define TIM2_AF1_ETRSEL           (0x00003C000)                                /*!< External trigger source selection */
-#define TIM2_AF1_ETRSEL_0         (0x000004000)                                /*!< Bit_0 */
-#define TIM2_AF1_ETRSEL_1         (0x000008000)                                /*!< Bit_1 */
-#define TIM2_AF1_ETRSEL_2         (0x000010000)                                /*!< Bit_2 */
-#define TIM2_AF1_ETRSEL_3         (0x000020000)                                /*!< Bit_3 */
-
-/*******************  Bit definition for TIM16_AF1 register  *******************/
-#define TIM16_AF1_BKINE_Pos       (0U)
-#define TIM16_AF1_BKINE_Msk       (0x1UL << TIM16_AF1_BKINE_Pos)               /*!< 0x00000001 */
-#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BRK BKIN input enable */
-#define TIM16_AF1_BKCMP1E_Pos     (1U)
-#define TIM16_AF1_BKCMP1E_Msk     (0x1UL << TIM16_AF1_BKCMP1E_Pos)             /*!< 0x00000002 */
-#define TIM16_AF1_BKCMP1E         TIM16_AF1_BKCMP1E_Msk                        /*!<BRK COMP1 enable */
-#define TIM16_AF1_BKCMP2E_Pos     (2U)                                         
-#define TIM16_AF1_BKCMP2E_Msk     (0x1UL << TIM16_AF1_BKCMP2E_Pos)             /*!< 0x00000004 */
-#define TIM16_AF1_BKCMP2E         TIM16_AF1_BKCMP2E_Msk                        /*!<BRK COMP2 enable */
-#define TIM16_AF1_BKINP_Pos       (9U)                                         
-#define TIM16_AF1_BKINP_Msk       (0x1UL << TIM16_AF1_BKINP_Pos)               /*!< 0x00000200 */
-#define TIM16_AF1_BKINP           TIM16_AF1_BKINP_Msk                          /*!<BRK BKIN2 input polarity */
-#define TIM16_AF1_BKCMP1P_Pos     (10U)                                        
-#define TIM16_AF1_BKCMP1P_Msk     (0x1UL << TIM16_AF1_BKCMP1P_Pos)             /*!< 0x00000400 */
-#define TIM16_AF1_BKCMP1P         TIM16_AF1_BKCMP1P_Msk                        /*!<BRK COMP1 input polarity */
-#define TIM16_AF1_BKCMP2P_Pos     (11U)                                        
-#define TIM16_AF1_BKCMP2P_Msk     (0x1UL << TIM16_AF1_BKCMP2P_Pos)             /*!< 0x00000800 */
-#define TIM16_AF1_BKCMP2P         TIM16_AF1_BKCMP2P_Msk                        /*!<BRK COMP2 input polarity */
-
-/*******************  Bit definition for TIM17_AF1 register  *******************/
-#define TIM17_AF1_BKINE_Pos       (0U)
-#define TIM17_AF1_BKINE_Msk       (0x1UL << TIM17_AF1_BKINE_Pos)               /*!< 0x00000001 */
-#define TIM17_AF1_BKINE           TIM17_AF1_BKINE_Msk                          /*!<BRK BKIN input enable */
-#define TIM17_AF1_BKCMP1E_Pos     (1U)
-#define TIM17_AF1_BKCMP1E_Msk     (0x1UL << TIM17_AF1_BKCMP1E_Pos)             /*!< 0x00000002 */
-#define TIM17_AF1_BKCMP1E         TIM17_AF1_BKCMP1E_Msk                        /*!<BRK COMP1 enable */
-#define TIM17_AF1_BKCMP2E_Pos     (2U)                                         
-#define TIM17_AF1_BKCMP2E_Msk     (0x1UL << TIM17_AF1_BKCMP2E_Pos)             /*!< 0x00000004 */
-#define TIM17_AF1_BKCMP2E         TIM17_AF1_BKCMP2E_Msk                        /*!<BRK COMP2 enable */
-#define TIM17_AF1_BKINP_Pos       (9U)                                         
-#define TIM17_AF1_BKINP_Msk       (0x1UL << TIM17_AF1_BKINP_Pos)               /*!< 0x00000200 */
-#define TIM17_AF1_BKINP           TIM17_AF1_BKINP_Msk                          /*!<BRK BKIN2 input polarity */
-#define TIM17_AF1_BKCMP1P_Pos     (10U)                                        
-#define TIM17_AF1_BKCMP1P_Msk     (0x1UL << TIM17_AF1_BKCMP1P_Pos)             /*!< 0x00000400 */
-#define TIM17_AF1_BKCMP1P         TIM17_AF1_BKCMP1P_Msk                        /*!<BRK COMP1 input polarity */
-#define TIM17_AF1_BKCMP2P_Pos     (11U)                                        
-#define TIM17_AF1_BKCMP2P_Msk     (0x1UL << TIM17_AF1_BKCMP2P_Pos)             /*!< 0x00000800 */
-#define TIM17_AF1_BKCMP2P         TIM17_AF1_BKCMP2P_Msk                        /*!<BRK COMP2 input polarity */
-
-/*******************  Bit definition for TIM1_AF2 register  *******************/
-#define TIM1_AF2_BK2INE_Pos       (0U)
-#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */
-#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BRK2 BKIN2 input enable */
-#define TIM1_AF2_BK2CMP1E_Pos     (1U)                                         
-#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
-#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BRK2 COMP1 enable */
-#define TIM1_AF2_BK2CMP2E_Pos     (2U)                                         
-#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
-#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BRK2 COMP2 enable */
-#define TIM1_AF2_BK2INP_Pos       (9U)                                         
-#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */
-#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRK2 BKIN2 input polarity */
-#define TIM1_AF2_BK2CMP1P_Pos     (10U)                                        
-#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
-#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BRK2 COMP1 input polarity */
-#define TIM1_AF2_BK2CMP2P_Pos     (11U)                                        
-#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
-#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BRK2 COMP2 input polarity */
-
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/*!< Root Secure Service Library */
-/*!< HDP Area constant definition */
-#define RSSLIB_HDP_AREA_Pos       (0U)
-#define RSSLIB_HDP_AREA_Msk       (0x3UL << RSSLIB_HDP_AREA_Pos)
-#define RSSLIB_HDP_AREA1_Msk      (0x1UL << RSSLIB_HDP_AREA_Pos)
-#define RSSLIB_HDP_AREA1          RSSLIB_HDP_AREA1_Msk
-
-/**
-  * @brief  Prototype of RSSLIB Close and exit HDP Function
-  * @detail This function close the requested hdp area passed in input
-  *         parameter and jump to the reset handler present within the
-  *         Vector table. The function does not return on successful execution.
-  * @param  HdpArea notifies which hdp area to close.
-  * @param  pointer on the vector table containing the reset handler the function
-  *         jumps to.
-  * @retval No return value.
-  */
-typedef void (*RSSLIB_S_CloseExitHDP_t)(uint32_t hdp_area, uint32_t jump_addr);
-
-/**
-  * @brief RSSLib function pointer structure
-  */
-typedef struct
-{
-  RSSLIB_S_CloseExitHDP_t CloseExitHDP;
-}RSSLIB_pFunc_TypeDef;
-
-#define RSSLIB_PFUNC                  ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE)
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC_COMMON)
-
-/******************************* AES Instances ********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5) || \
-                                       ((INSTANCE) == DMA2_Channel6) || \
-                                       ((INSTANCE) == DMA2_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************* GPIO AF Instances ****************************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************* SMBUS Instances ******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************* IPCC Instances ********************************/
-#define IS_IPCC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IPCC)
-
-/******************************** HSEM Instances *******************************/
-#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
-
-#define HSEM_CPU1_COREID   (0x00000004U) /* Semaphore Core ID */
-#define HSEM_CPU2_COREID   (0x00000008U) /* Semaphore Core ID */
-
-#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/
-#define HSEM_SEMID_MAX     (15U)      /* HSEM ID Max */
-
-#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */
-#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */
-
-#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */
-#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */
-
-/******************************** PKA Instances *******************************/
-#define IS_PKA_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == PKA)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
-
-/****************************** RTC Instances *********************************/
-#define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SUBGHZSPI))
-
-/******************************** SUBGHZSPI Instances *************************/
-#define IS_SUBGHZ_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SUBGHZSPI)
-#define IS_SUBGHZ_MODULATION_SUPPORTED(COMMAND,PACKET_TYPE)  \
-                                   ((((COMMAND) != RADIO_SET_PACKETTYPE)) || \
-                                    (((COMMAND) == RADIO_SET_PACKETTYPE)  && \
-                                    (((PACKET_TYPE) == 0x00)              || \
-                                     ((PACKET_TYPE) > 0x01 ))))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
-                                         ((INSTANCE) == LPTIM2) || \
-                                         ((INSTANCE) == LPTIM3))
-
-/****************** LPTIM Instances : Encoder mode ****************************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM16)  || \
-                                         ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting 32 bits counter ****************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : supporting the break function *************/
-#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
-                                            ((INSTANCE) == TIM16)   || \
-                                            ((INSTANCE) == TIM17))
-
-/************** TIM Instances : supporting Break source selection *************/
-#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                               ((INSTANCE) == TIM16)  || \
-                                               ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting 2 break inputs *****************/
-#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM16)  || \
-                                         ((INSTANCE) == TIM17))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : at least 5 capture/compare channels *******/
-#define IS_TIM_CC5_INSTANCE(INSTANCE)      ((INSTANCE) == TIM1)
-
-/****************** TIM Instances : at least 6 capture/compare channels *******/
-#define IS_TIM_CC6_INSTANCE(INSTANCE)      ((INSTANCE) == TIM1)
-
-/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/******************* TIM Instances : Timer input selection ********************/
-#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM16)   || \
-                                         ((INSTANCE) == TIM17))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-        ((((INSTANCE) == TIM1) &&                  \
-           (((CHANNEL) == TIM_CHANNEL_1) ||          \
-            ((CHANNEL) == TIM_CHANNEL_2) ||          \
-            ((CHANNEL) == TIM_CHANNEL_3) ||          \
-            ((CHANNEL) == TIM_CHANNEL_4) ||          \
-            ((CHANNEL) == TIM_CHANNEL_5) ||          \
-            ((CHANNEL) == TIM_CHANNEL_6)))           \
-           ||                                        \
-           (((INSTANCE) == TIM2) &&                  \
-           (((CHANNEL) == TIM_CHANNEL_1) ||          \
-            ((CHANNEL) == TIM_CHANNEL_2) ||          \
-            ((CHANNEL) == TIM_CHANNEL_3) ||          \
-            ((CHANNEL) == TIM_CHANNEL_4)))           \
-           ||                                        \
-           (((INSTANCE) == TIM16) &&                 \
-           (((CHANNEL) == TIM_CHANNEL_1)))           \
-           ||                                        \
-           (((INSTANCE) == TIM17) &&                 \
-            (((CHANNEL) == TIM_CHANNEL_1))))
-
-/****************** TIM Instances : supporting complementary output(s) ********/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM17) &&                   \
-     ((CHANNEL) == TIM_CHANNEL_1))              \
-    ||                                          \
-    (((INSTANCE) == TIM16) &&                   \
-     ((CHANNEL) == TIM_CHANNEL_1)))
-
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
-                                                    ((INSTANCE) == TIM2)    || \
-                                                    ((INSTANCE) == TIM16)   || \
-                                                    ((INSTANCE) == TIM17))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
-#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/****************** TIM Instances : supporting commutation event generation ***/
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
-                                                     ((INSTANCE) == TIM16)   || \
-                                                     ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting counting mode selection ********/
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
-                                                      ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting Hall sensor interface **********/
-#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/**************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2))
-
-/************* TIM Instances : supporting ETR source selection ***************/
-#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                             ((INSTANCE) == TIM2))
-
-/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting OCxREF clear *******************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
-                                                       ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM16) || \
-                                            ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting repetition counter *************/
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
-                                                       ((INSTANCE) == TIM16) || \
-                                                       ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
-#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2))
-
-/************ TIM Instances : Advanced timers  ********************************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* USART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/****************** UART Instances : Auto Baud Rate detection ****************/
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : SPI Slave selection mode ***************/
-#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                              ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_FIFO_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
-                                             ((INSTANCE) == USART2) || \
-                                             ((INSTANCE) == LPUART1))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32WL54xx_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Include/stm32wl55xx.h

@@ -1,11457 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wl55xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex Device Peripheral Access Layer Header File.
-  *          This file contains all the peripheral register's definitions, bits
-  *          definitions and memory mapping for stm32wl55xx devices.
-  *
-  *          This file contains:selected
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2020(-2021) STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32wl55xx
-  * @{
-  */
-
-#ifndef __STM32WL55xx_H
-#define __STM32WL55xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-#define DUAL_CORE
-
-
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief stm32wl55xx Interrupt Number Definition, according to the selected device
- *        in @ref Library_configuration_section
- */
-#if defined(CORE_CM0PLUS)
-  /*!< Interrupt Number Definition for M0 */
-  typedef enum
-  {
-  /******  Cortex-M0 Processor Exceptions Numbers ****************************************************************/
-    NonMaskableInt_IRQn          = -14,    /*!< Non Maskable Interrupt                                            */
-    HardFault_IRQn               = -13,    /*!< Cortex-M0+ Hard Fault Interrupt                                   */
-    SVC_IRQn                     = -5,     /*!< Cortex-M0+ SV Call Interrupt                                      */
-    PendSV_IRQn                  = -2,     /*!< Cortex-M0+ Pend SV Interrupt                                      */
-    SysTick_IRQn                 = -1,     /*!< Cortex-M0+ System Tick Interrupt                                  */
-
-  /*************  STM32WLxx specific Interrupt Numbers on M0 core ************************************************/
-    TZIC_ILA_IRQn                = 0,      /*!< Security Interrupt controller illegal access interrupt            */
-    PVD_PVM_IRQn                 = 1,      /*!< PVD and PVM detector                                              */
-    RTC_LSECSS_IRQn              = 2,      /*!< RTC Wakeup + RTC Tamper and RTC TimeStamp + RTC Alarms (A & B) and*/
-                                           /*!< RTC SSRU Interrupts and LSECSS Interrupts                         */
-    RCC_FLASH_C1SEV_IRQn         = 3,      /*!< RCC Interrupt, FLASH interrupt and CPU1 SEV                       */
-    EXTI1_0_IRQn                 = 4,      /*!< EXTI Line 1:0 Interrupt                                           */
-    EXTI3_2_IRQn                 = 5,      /*!< EXTI Line 3:2 Interrupt                                           */
-    EXTI15_4_IRQn                = 6,      /*!< EXTI Line 15:4 interrupt                                          */
-    ADC_COMP_DAC_IRQn            = 7,      /*!< ADC, COMP1, COMP2, DAC interrupts                                 */
-    DMA1_Channel1_2_3_IRQn       = 8,      /*!< DMA1 Channels 1,2,3 Interrupt                                     */
-    DMA1_Channel4_5_6_7_IRQn     = 9,      /*!< DMA1 Channels 4,5,6,7 Interrupt                                   */
-    DMA2_DMAMUX1_OVR_IRQn        = 10,     /*!< DMA2 Channels[1..7] and DMAMUX1 Overrun Interrupt                 */
-    LPTIM1_IRQn                  = 11,     /*!< LPTIM1 Global Interrupt                                           */
-    LPTIM2_IRQn                  = 12,     /*!< LPTIM2 Global Interrupt                                           */
-    LPTIM3_IRQn                  = 13,     /*!< LPTIM3 Global Interrupt                                           */
-    TIM1_IRQn                    = 14,     /*!< TIM1 Global Interrupt                                             */
-    TIM2_IRQn                    = 15,     /*!< TIM2 Global Interrupt                                             */
-    TIM16_IRQn                   = 16,     /*!< TIM16 Global Interrupt                                            */
-    TIM17_IRQn                   = 17,     /*!< TIM17 Global Interrupt                                            */
-    IPCC_C2_RX_C2_TX_IRQn        = 18,     /*!< IPCC RX Occupied and TX Free Interrupt                            */
-    HSEM_IRQn                    = 19,     /*!< HSEM Interrupt                                                    */
-    RNG_IRQn                     = 20,     /*!< RNG Interrupt                                                     */
-    AES_PKA_IRQn                 = 21,     /*!< AES and PKA Interrupt                                             */
-    I2C1_IRQn                    = 22,     /*!< I2C1 Event and Error Interrupt                                    */
-    I2C2_IRQn                    = 23,     /*!< I2C2 Event and Error Interrupt                                    */
-    I2C3_IRQn                    = 24,     /*!< I2C3 Event and Error Interrupt                                    */
-    SPI1_IRQn                    = 25,     /*!< SPI1 Interrupt                                                    */
-    SPI2_IRQn                    = 26,     /*!< SPI2 Interrupt                                                    */
-    USART1_IRQn                  = 27,     /*!< USART1 Interrupt                                                  */
-    USART2_IRQn                  = 28,     /*!< USART2 Interrupt                                                  */
-    LPUART1_IRQn                 = 29,     /*!< LPUART1 Interrupt                                                 */
-    SUBGHZSPI_IRQn               = 30,     /*!< SUBGHZSPI Interrupt                                               */
-    SUBGHZ_Radio_IRQn            = 31,     /*!< SUBGHZ Radio Interrupt                                            */
-  } IRQn_Type;
-#else /* CORE_CM4 */
-/*!< Interrupt Number Definition for M4 */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn                 = -14,    /*!< Non Maskable Interrupt                                            */
-  HardFault_IRQn                      = -13,    /*!< Cortex-M4 Hard Fault Interrupt                                    */
-  MemoryManagement_IRQn               = -12,    /*!< Cortex-M4 Memory Management Interrupt                             */
-  BusFault_IRQn                       = -11,    /*!< Cortex-M4 Bus Fault Interrupt                                     */
-  UsageFault_IRQn                     = -10,    /*!< Cortex-M4 Usage Fault Interrupt                                   */
-  SVCall_IRQn                         = -5,     /*!< Cortex-M4 SV Call Interrupt                                       */
-  DebugMonitor_IRQn                   = -4,     /*!< Cortex-M4 Debug Monitor Interrupt                                 */
-  PendSV_IRQn                         = -2,     /*!< Cortex-M4 Pend SV Interrupt                                       */
-  SysTick_IRQn                        = -1,     /*!< Cortex-M4 System Tick Interrupt                                   */
-
-/*************  STM32WLxx specific Interrupt Numbers on M4 core ************************************************/
-  WWDG_IRQn                           = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_PVM_IRQn                        = 1,      /*!< PVD and PVM detector                                              */
-  TAMP_STAMP_LSECSS_SSRU_IRQn         = 2,      /*!< RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts         */
-  RTC_WKUP_IRQn                       = 3,      /*!< RTC Wakeup Interrupt                                              */
-  FLASH_IRQn                          = 4,      /*!< FLASH (CFI)  global Interrupt                                     */
-  RCC_IRQn                            = 5,      /*!< RCC Interrupt                                                     */
-  EXTI0_IRQn                          = 6,      /*!< EXTI Line 0 Interrupt                                             */
-  EXTI1_IRQn                          = 7,      /*!< EXTI Line 1 Interrupt                                             */
-  EXTI2_IRQn                          = 8,      /*!< EXTI Line 2 Interrupt                                             */
-  EXTI3_IRQn                          = 9,      /*!< EXTI Line 3 Interrupt                                             */
-  EXTI4_IRQn                          = 10,     /*!< EXTI Line 4 Interrupt                                             */
-  DMA1_Channel1_IRQn                  = 11,     /*!< DMA1 Channel 1 Interrupt                                          */
-  DMA1_Channel2_IRQn                  = 12,     /*!< DMA1 Channel 2 Interrupt                                          */
-  DMA1_Channel3_IRQn                  = 13,     /*!< DMA1 Channel 3 Interrupt                                          */
-  DMA1_Channel4_IRQn                  = 14,     /*!< DMA1 Channel 4 Interrupt                                          */
-  DMA1_Channel5_IRQn                  = 15,     /*!< DMA1 Channel 5 Interrupt                                          */
-  DMA1_Channel6_IRQn                  = 16,     /*!< DMA1 Channel 6 Interrupt                                          */
-  DMA1_Channel7_IRQn                  = 17,     /*!< DMA1 Channel 7 Interrupt                                          */
-  ADC_IRQn                            = 18,     /*!< ADC Interrupt                                                     */
-  DAC_IRQn                            = 19,     /*!< DAC Interrupt                                                     */
-  C2SEV_PWR_C2H_IRQn                  = 20,     /*!< CPU2 SEV Interrupt                                                */
-  COMP_IRQn                           = 21,     /*!< COMP1 and COMP2 Interrupts                                        */
-  EXTI9_5_IRQn                        = 22,     /*!< EXTI Lines [9:5] Interrupt                                        */
-  TIM1_BRK_IRQn                       = 23,     /*!< TIM1 Break Interrupt                                              */
-  TIM1_UP_IRQn                        = 24,     /*!< TIM1 Update Interrupt                                             */
-  TIM1_TRG_COM_IRQn                   = 25,     /*!< TIM1 Trigger and Communication Interrupts                         */
-  TIM1_CC_IRQn                        = 26,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                           = 27,     /*!< TIM2 Global Interrupt                                             */
-  TIM16_IRQn                          = 28,     /*!< TIM16 Global Interrupt                                            */
-  TIM17_IRQn                          = 29,     /*!< TIM17 Global Interrupt                                            */
-  I2C1_EV_IRQn                        = 30,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                        = 31,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                        = 32,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                        = 33,     /*!< I2C2 Error Interrupt                                              */
-  SPI1_IRQn                           = 34,     /*!< SPI1 Interrupt                                                    */
-  SPI2_IRQn                           = 35,     /*!< SPI2 Interrupt                                                    */
-  USART1_IRQn                         = 36,     /*!< USART1 Interrupt                                                  */
-  USART2_IRQn                         = 37,     /*!< USART2 Interrupt                                                  */
-  LPUART1_IRQn                        = 38,     /*!< LPUART1 Interrupt                                                 */
-  LPTIM1_IRQn                         = 39,     /*!< LPTIM1 Global Interrupt                                           */
-  LPTIM2_IRQn                         = 40,     /*!< LPTIM2 Global Interrupt                                           */
-  EXTI15_10_IRQn                      = 41,     /*!< EXTI Lines [15:10] Interrupt                                      */
-  RTC_Alarm_IRQn                      = 42,     /*!< RTC Alarms (A and B) Interrupt                                    */
-  LPTIM3_IRQn                         = 43,     /*!< LPTIM3 Global Interrupt                                           */
-  SUBGHZSPI_IRQn                      = 44,     /*!< SUBGHZSPI Interrupt                                               */
-  IPCC_C1_RX_IRQn                     = 45,     /*!< IPCC RX Occupied Interrupt                                        */
-  IPCC_C1_TX_IRQn                     = 46,     /*!< IPCC TX Free Interrupt                                            */
-  HSEM_IRQn                           = 47,     /*!< HSEM Interrupt                                                    */
-  I2C3_EV_IRQn                        = 48,     /*!< I2C3 Event Interrupt                                              */
-  I2C3_ER_IRQn                        = 49,     /*!< I2C3 Error Interrupt                                              */
-  SUBGHZ_Radio_IRQn                   = 50,     /*!< SUBGHZ Radio Interrupt                                            */
-  AES_IRQn                            = 51,     /*!< AES Interrupt                                                     */
-  RNG_IRQn                            = 52,     /*!< RNG Interrupt                                                     */
-  PKA_IRQn                            = 53,     /*!< PKA Interrupt                                                     */
-  DMA2_Channel1_IRQn                  = 54,     /*!< DMA2 Channel 1 Interrupt                                          */
-  DMA2_Channel2_IRQn                  = 55,     /*!< DMA2 Channel 2 Interrupt                                          */
-  DMA2_Channel3_IRQn                  = 56,     /*!< DMA2 Channel 3 Interrupt                                          */
-  DMA2_Channel4_IRQn                  = 57,     /*!< DMA2 Channel 4 Interrupt                                          */
-  DMA2_Channel5_IRQn                  = 58,     /*!< DMA2 Channel 5 Interrupt                                          */
-  DMA2_Channel6_IRQn                  = 59,     /*!< DMA2 Channel 6 Interrupt                                          */
-  DMA2_Channel7_IRQn                  = 60,     /*!< DMA2 Channel 7 Interrupt                                          */
-  DMAMUX1_OVR_IRQn                    = 61      /*!< DMAMUX1 overrun Interrupt                                         */
-} IRQn_Type;
-/**
-  * @}
-  */
-#endif
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
-  */
-#define __CM0PLUS_REV             1U /*!< Core Revision r0p1                            */
-#define __MPU_PRESENT             1U /*!< M0 provides an MPU                            */
-#define __VTOR_PRESENT            1U /*!< Vector Table Register supported               */
-#define __NVIC_PRIO_BITS          2U /*!< M0 core uses 2 Bits for the Priority Levels   */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             0U /*!< FPU not present                               */
-
-#include "core_cm0plus.h"            /* Cortex-M0+ processor and core peripherals */
-
-#else /* CORE_CM4*/
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
-  */
-#define __CM4_REV                 1U /*!< Core Revision r0p1                            */
-#define __MPU_PRESENT             1U /*!< M4 provides an MPU                            */
-#define __VTOR_PRESENT            1U /*!< Vector Table Register supported               */
-#define __NVIC_PRIO_BITS          4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             0U /*!< FPU not present                                   */
-
-#include "core_cm4.h"                /* Cortex-M4 processor and core peripherals */
-
-#endif
-
-#include "system_stm32wlxx.h"
-#include <stdint.h>
-
-/**
-  * @}
-  */
-
-
-
-
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */
-
-/**
-  * @brief Analog to Digital Converter
-  */
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
-  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
-  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC configuration register 1,                  Address offset: 0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR;         /*!< ADC sampling time register,                    Address offset: 0x14 */
-       uint32_t RESERVED1;    /*!< Reserved,                                                      0x18 */
-       uint32_t RESERVED2;    /*!< Reserved,                                                      0x1C */
-  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
-  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC group regular sequencer register,          Address offset: 0x28 */
-  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x2C */
-       uint32_t RESERVED3[4]; /*!< Reserved,                                               0x30 - 0x3C */
-  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
-       uint32_t RESERVED4[23];/*!< Reserved,                                               0x44 - 0x9C */
-  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
-  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 configuration register,  Address offset: 0xA4 */
-       uint32_t RESERVED5[3]; /*!< Reserved,                                               0xA8 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC Calibration factor register,               Address offset: 0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/**
-  * @brief AES hardware accelerator
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;          /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;        /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;       /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;       /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;       /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;       /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;       /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;        /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;        /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;        /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;        /*!< AES initialization vector register 3,        Address offset: 0x2C */
-  __IO uint32_t KEYR4;       /*!< AES key register 4,                          Address offset: 0x30 */
-  __IO uint32_t KEYR5;       /*!< AES key register 5,                          Address offset: 0x34 */
-  __IO uint32_t KEYR6;       /*!< AES key register 6,                          Address offset: 0x38 */
-  __IO uint32_t KEYR7;       /*!< AES key register 7,                          Address offset: 0x3C */
-  __IO uint32_t SUSP0R;      /*!< AES Suspend register 0,                      Address offset: 0x40 */
-  __IO uint32_t SUSP1R;      /*!< AES Suspend register 1,                      Address offset: 0x44 */
-  __IO uint32_t SUSP2R;      /*!< AES Suspend register 2,                      Address offset: 0x48 */
-  __IO uint32_t SUSP3R;      /*!< AES Suspend register 3,                      Address offset: 0x4C */
-  __IO uint32_t SUSP4R;      /*!< AES Suspend register 4,                      Address offset: 0x50 */
-  __IO uint32_t SUSP5R;      /*!< AES Suspend register 5,                      Address offset: 0x54 */
-  __IO uint32_t SUSP6R;      /*!< AES Suspend register 6,                      Address offset: 0x58 */
-  __IO uint32_t SUSP7R;      /*!< AES Suspend register 7,                      Address offset: 0x6C */
-} AES_TypeDef;
-
-/**
-  * @brief Comparator
-  */
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register,               Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/**
-  * @brief CRC calculation unit
-  */
-typedef struct
-{
-  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
-  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
-       uint32_t RESERVED2;   /*!< Reserved,                                                    0x0C */
-  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
-  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Digital to Analog Converter
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-       uint32_t RESERVED1;   /*!< Reserved                                                 Address offset: 0x14 */
-       uint32_t RESERVED2;   /*!< Reserved                                                 Address offset: 0x18 */
-       uint32_t RESERVED3;   /*!< Reserved                                                 Address offset: 0x1C */
-  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-       uint32_t RESERVED4;   /*!< Reserved                                                 Address offset: 0x30 */
-  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
-  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
-  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
-  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
-       uint32_t RESERVED5;   /*!< Reserved                                                 Address offset: 0x44 */
-  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
-  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
-} DAC_TypeDef;
-
-#if defined(CORE_CM0PLUS)
-#else
-/**
-  * @brief Debug MCU
-  */
-typedef struct
-{
-  __IO uint32_t IDCODE;      /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;          /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  uint32_t RESERVED1[13];    /*!< Reserved,                                               0x08-0x38 */
-  __IO uint32_t APB1FZR1;    /*!< Debug MCU CPU1 APB1 freeze register,         Address offset: 0x3C */
-  __IO uint32_t C2APB1FZR1;  /*!< Debug MCU CPU2 APB1 freeze register,         Address offset: 0x40 */
-  __IO uint32_t APB1FZR2;    /*!< Debug MCU CPU1 APB1 freeze register,         Address offset: 0x44 */
-  __IO uint32_t C2APB1FZR2;  /*!< Debug MCU CPU2 APB1 freeze register,         Address offset: 0x48 */
-  __IO uint32_t APB2FZR;     /*!< Debug MCU CPU1 APB2 freeze register,         Address offset: 0x4C */
-  __IO uint32_t C2APB2FZR;   /*!< Debug MCU CPU2 APB2 freeze register,         Address offset: 0x50 */
-} DBGMCU_TypeDef;
-#endif
-
-/**
-  * @brief DMA Controller
-  */
-typedef struct
-{
-  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
-  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
-} DMA_TypeDef;
-
-/**
-  * @brief DMA Multiplexer
-  */
-typedef struct
-{
-  __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
-}DMAMUX_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t   CSR;       /*!< DMA Channel Status Register                    Address offset: 0x0080   */
-  __IO uint32_t   CFR;       /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
-}DMAMUX_ChannelStatus_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
-}DMAMUX_RequestGen_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
-  __IO uint32_t   RGCFR;       /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
-}DMAMUX_RequestGenStatus_TypeDef;
-
-/**
-  * @brief Async Interrupts and Events Controller
-  */
-typedef struct
-{
-  __IO uint32_t RTSR1;          /*!< EXTI rising trigger selection register [31:0],            Address offset: 0x00 */
-  __IO uint32_t FTSR1;          /*!< EXTI falling trigger selection register [31:0],           Address offset: 0x04 */
-  __IO uint32_t SWIER1;         /*!< EXTI software interrupt event register [31:0],            Address offset: 0x08 */
-  __IO uint32_t PR1;            /*!< EXTI pending register [31:0],                             Address offset: 0x0C */
-  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                                 Address offset: 0x10 - 0x1C */
-  __IO uint32_t RTSR2;          /*!< EXTI rising trigger selection register [31:0],            Address offset: 0x20 */
-  __IO uint32_t FTSR2;          /*!< EXTI falling trigger selection register [31:0],           Address offset: 0x24 */
-  __IO uint32_t SWIER2;         /*!< EXTI software interrupt event register [31:0],            Address offset: 0x28 */
-  __IO uint32_t PR2;            /*!< EXTI pending register [31:0],                             Address offset: 0x2C */
-  __IO uint32_t RESERVED2[4];   /*!< Reserved,                                                 Address offset: 0x30 - 0x3C */
-  __IO uint32_t RESERVED3[8];   /*!< Reserved,                                                 Address offset: 0x40 - 0x5C */
-  __IO uint32_t RESERVED4[8];   /*!< Reserved,                                                 Address offset: 0x60 - 0x7C */
-  __IO uint32_t IMR1;           /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
-  __IO uint32_t EMR1;           /*!< EXTI wakeup with event mask register for cpu1 [31:0],     Address offset: 0x84 */
-  __IO uint32_t RESERVED5[2];   /*!< Reserved,                                                 Address offset: 0x88 - 0x8C */
-  __IO uint32_t IMR2;           /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
-  __IO uint32_t EMR2;           /*!< EXTI wakeup with event mask register for cpu1 [31:0],     Address offset: 0x94 */
-  __IO uint32_t RESERVED8[10];  /*!< Reserved,                                                 Address offset: 0x98 - 0xBC */
-  __IO uint32_t C2IMR1;         /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xC0 */
-  __IO uint32_t C2EMR1;         /*!< EXTI wakeup with event mask register for cpu2 [31:0],     Address offset: 0xC4 */
-  __IO uint32_t RESERVED9[2];   /*!< Reserved,                                                 Address offset: 0xC8 - 0xCC */
-  __IO uint32_t C2IMR2;         /*!< EXTI wakeup with interrupt mask register for cpu2 [31:0], Address offset: 0xD0 */
-  __IO uint32_t C2EMR2;         /*!< EXTI wakeup with event mask register for cpu2 [31:0],     Address offset: 0xD4 */
-}EXTI_TypeDef;
-
-/**
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< FLASH Access control register,                      Address offset: 0x00      */
-  __IO uint32_t ACR2;          /*!< FLASH Access control register 2,                    Address offset: 0x04      */
-  __IO uint32_t KEYR;          /*!< FLASH Key register,                                 Address offset: 0x08      */
-  __IO uint32_t OPTKEYR;       /*!< FLASH Option Key register,                          Address offset: 0x0C      */
-  __IO uint32_t SR;            /*!< FLASH Status register,                              Address offset: 0x10      */
-  __IO uint32_t CR;            /*!< FLASH Control register,                             Address offset: 0x14      */
-  __IO uint32_t ECCR;          /*!< FLASH ECC register,                                 Address offset: 0x18      */
-  uint32_t RESERVED1;          /*!< Reserved,                                           Address offset: 0x1C      */
-  __IO uint32_t OPTR;          /*!< FLASH Option register,                              Address offset: 0x20      */
-  __IO uint32_t PCROP1ASR;     /*!< FLASH Bank 1 PCROP area A Start address register,   Address offset: 0x24      */
-  __IO uint32_t PCROP1AER;     /*!< FLASH Bank 1 PCROP area A End address register,     Address offset: 0x28      */
-  __IO uint32_t WRP1AR;        /*!< FLASH Bank 1 WRP area A address register,           Address offset: 0x2C      */
-  __IO uint32_t WRP1BR;        /*!< FLASH Bank 1 WRP area B address register,           Address offset: 0x30      */
-  __IO uint32_t PCROP1BSR;     /*!< FLASH Bank 1 PCROP area B Start address register,   Address offset: 0x34      */
-  __IO uint32_t PCROP1BER;     /*!< FLASH Bank 1 PCROP area B End address register,     Address offset: 0x38      */
-  __IO uint32_t IPCCBR;        /*!< FLASH IPCC data buffer address,                     Address offset: 0x3C      */
-  uint32_t RESERVED2[7];       /*!< Reserved,                                           Address offset: 0x40-0x58 */
-  __IO uint32_t C2ACR;         /*!< FLASH Core MO+ Access Control Register ,            Address offset: 0x5C      */
-  __IO uint32_t C2SR;          /*!< FLASH Core MO+ Status Register,                     Address offset: 0x60      */
-  __IO uint32_t C2CR;          /*!< FLASH Core MO+ Control register,                    Address offset: 0x64      */
-  uint32_t RESERVED3[6];       /*!< Reserved,                                           Address offset: 0x68-0x7C */
-  __IO uint32_t SFR;           /*!< FLASH secure start address,                         Address offset: 0x80      */
-  __IO uint32_t SRRVR;         /*!< FlASH secure SRAM2 start addr and CPU2 reset vector Address offset: 0x84      */
-} FLASH_TypeDef;
-
-/**
-  * @brief General Purpose I/O
-  */
-typedef struct
-{
-  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
-  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/**
-  * @brief Global Security Controller
-  */
-typedef struct{
-  __IO uint32_t CR;             /*!< TZSC control register,                             Address offset: 0x00       */
-       uint32_t RESERVED1[3];   /*!< Reserved1,                                         Address offset: 0x04-0x0C  */
-  __IO uint32_t SECCFGR1;       /*!< TZSC secure configuration register 1,              Address offset: 0x10       */
-       uint32_t RESERVED2[3];   /*!< Reserved2,                                         Address offset: 0x14-0x1C  */
-  __IO uint32_t PRIVCFGR1;      /*!< TZSC privilege configuration register 1,           Address offset: 0x20       */
-       uint32_t RESERVED3[67];  /*!< Reserved3,                                         Address offset: 0x24-0x12C */
-  __IO uint32_t MPCWM1_UPWMR;   /*!< TZSC Unprivileged Water Mark 1 register,           Address offset: 0x130      */
-  __IO uint32_t MPCWM1_UPWWMR;  /*!< TZSC Unprivileged Writable Water Mark 1 register,  Address offset: 0x134      */
-  __IO uint32_t MPCWM2_UPWMR;   /*!< TZSC Unprivileged Water Mark 2 register,           Address offset: 0x138      */
-       uint32_t RESERVED4;      /*!< Reserved4,                                         Address offset: 0x13C      */
-  __IO uint32_t MPCWM3_UPWMR;   /*!< TZSC Unprivileged Water Mark 2 register,           Address offset: 0x140      */
-} GTZC_TZSC_TypeDef;
-
-typedef struct{
-  __IO uint32_t IER1;           /*!< TZIC interrupt enable register 1,    Address offset: 0x00 */
-  uint32_t RESERVED1[3];        /*!< Reserved1,                           Address offset: 0x0C */
-  __IO uint32_t MISR1;          /*!< TZIC interrupt status register 1,    Address offset: 0x10 */
-  uint32_t RESERVED2[3];        /*!< Reserved2,                           Address offset: 0x1C */
-  __IO uint32_t ICR1;           /*!< TZIC interrupt clear register 1,     Address offset: 0x20 */
-} GTZC_TZIC_TypeDef;
-
-/**
-  * @brief HW Semaphore HSEM
-  */
-typedef struct
-{
-  __IO uint32_t R[16];      /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-3Ch  */
-   uint32_t  Reserved1[16]; /*!< Reserved                                        Address offset: 40h-7Ch  */
-  __IO uint32_t RLR[16];    /*!< HSEM 1-step read lock registers,                Address offset: 80h-BCh  */
-   uint32_t  Reserved2[16]; /*!< Reserved                                        Address offset: C0h-FCh  */
-  __IO uint32_t C1IER;      /*!< HSEM CPU1 interrupt enable register ,           Address offset: 100h     */
-  __IO uint32_t C1ICR;      /*!< HSEM CPU1 interrupt clear register ,            Address offset: 104h     */
-  __IO uint32_t C1ISR;      /*!< HSEM CPU1 interrupt status register ,           Address offset: 108h     */
-  __IO uint32_t C1MISR;     /*!< HSEM CPU1 masked interrupt status register ,    Address offset: 10Ch     */
-  __IO uint32_t C2IER;      /*!< HSEM CPU2 interrupt enable register ,           Address offset: 110h     */
-  __IO uint32_t C2ICR;      /*!< HSEM CPU2 interrupt clear register ,            Address offset: 114h     */
-  __IO uint32_t C2ISR;      /*!< HSEM CPU2 interrupt status register ,           Address offset: 118h     */
-  __IO uint32_t C2MISR;     /*!< HSEM CPU2 masked interrupt status register ,    Address offset: 11Ch     */
-   uint32_t  Reserved[8];   /*!< Reserved                                        Address offset: 120h-13Ch*/
-  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                 Address offset: 140h     */
-  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,             Address offset: 144h     */
-} HSEM_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */
-  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */
-  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */
-  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */
-} HSEM_Common_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
-} I2C_TypeDef;
-
-/**
-  * @brief Inter-Processor Communication
-  */
-typedef struct
-{
-  __IO uint32_t C1CR;             /*!< Inter-Processor Communication: C1 control register,                  Address offset: 0x000 */
-  __IO uint32_t C1MR ;            /*!< Inter-Processor Communication: C1 mask register,                     Address offset: 0x004 */
-  __IO uint32_t C1SCR;            /*!< Inter-Processor Communication: C1 status set clear register,         Address offset: 0x008 */
-  __IO uint32_t C1TOC2SR;         /*!< Inter-Processor Communication: C1 to processor M4  status register,  Address offset: 0x00C */
-  __IO uint32_t C2CR;             /*!< Inter-Processor Communication: C2 control register,                  Address offset: 0x010 */
-  __IO uint32_t C2MR ;            /*!< Inter-Processor Communication: C2 mask register,                     Address offset: 0x014 */
-  __IO uint32_t C2SCR;            /*!< Inter-Processor Communication: C2 status set clear register,         Address offset: 0x018 */
-  __IO uint32_t C2TOC1SR;         /*!< Inter-Processor Communication: C2 to processor M4 status register,   Address offset: 0x01C */
-} IPCC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CR;               /*!< Control register,                                                    Address offset: 0x000 */
-  __IO uint32_t MR;               /*!< Mask register,                                                       Address offset: 0x004 */
-  __IO uint32_t SCR;              /*!< Status set clear register,                                           Address offset: 0x008 */
-  __IO uint32_t SR;               /*!< Status register,                                                     Address offset: 0x00C */
-} IPCC_CommonTypeDef;
-
-/**
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/**
-  * @brief LPTIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
-  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
-  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
-  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
-  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
-  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
-  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
-  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
-  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
-  __IO uint32_t RESERVED;    /*!< Reserved,                                           Address offset: 0x24 */
-  __IO uint32_t RCR;         /*!< LPTIM repetition register,                          Address offset: 0x28 */
-} LPTIM_TypeDef;
-
-/**
-  * @brief Public Key Accelerator (PKA)
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< PKA control register,                 Address offset: 0x00 */
-  __IO uint32_t SR;          /*!< PKA status register,                  Address offset: 0x04 */
-  __IO uint32_t CLRFR;       /*!< PKA clear flag register,              Address offset: 0x08 */
-  uint32_t  Reserved1[253];  /*!< Reserved                              Address offset: 0x000C-0x03FC*/
-  __IO uint32_t RAM[894];    /*!< PKA RAM,                              Address offset: 0x0400-0x11F4 */
-} PKA_TypeDef;
-
-/**
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< PWR Power Control Register 1,                     Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< PWR Power Control Register 2,                     Address offset: 0x04 */
-  __IO uint32_t CR3;          /*!< PWR Power Control Register 3,                     Address offset: 0x08 */
-  __IO uint32_t CR4;          /*!< PWR Power Control Register 4,                     Address offset: 0x0C */
-  __IO uint32_t SR1;          /*!< PWR Power Status Register 1,                      Address offset: 0x10 */
-  __IO uint32_t SR2;          /*!< PWR Power Status Register 2,                      Address offset: 0x14 */
-  __IO uint32_t SCR;          /*!< PWR Power Status Reset Register,                  Address offset: 0x18 */
-  __IO uint32_t CR5;          /*!< PWR Power Control Register 5,                     Address offset: 0x1C */
-  __IO uint32_t PUCRA;        /*!< PWR Pull-Up Control Register of port A,           Address offset: 0x20 */
-  __IO uint32_t PDCRA;        /*!< PWR Pull-Down Control Register of port A,         Address offset: 0x24 */
-  __IO uint32_t PUCRB;        /*!< PWR Pull-Up Control Register of port B,           Address offset: 0x28 */
-  __IO uint32_t PDCRB;        /*!< PWR Pull-Down Control Register of port B,         Address offset: 0x2C */
-  __IO uint32_t PUCRC;        /*!< PWR Pull-Up Control Register of port C,           Address offset: 0x30 */
-  __IO uint32_t PDCRC;        /*!< PWR Pull-Down Control Register of port C,         Address offset: 0x34 */
-       uint32_t RESERVED0[8]; /*!< Reserved,                                         Address offset: 0x38-0x54 */
-  __IO uint32_t PUCRH;        /*!< PWR Pull-Up Control Register of port H,           Address offset: 0x58 */
-  __IO uint32_t PDCRH;        /*!< PWR Pull-Down Control Register of port H,         Address offset: 0x5C */
-       uint32_t RESERVED1[8]; /*!< Reserved,                                         Address offset: 0x60-0x7C */
-  __IO uint32_t C2CR1;        /*!< PWR Power Control Register 1 for CPU2,            Address offset: 0x80 */
-  __IO uint32_t C2CR3;        /*!< PWR Power Control Register 3 for CPU2,            Address offset: 0x84 */
-  __IO uint32_t EXTSCR;       /*!< PWR Power Status Reset Register for CPU2,         Address offset: 0x88 */
-  __IO uint32_t SECCFGR;      /*!< PWR Security Configuration Register,              Address offset: 0x8C */
-  __IO uint32_t SUBGHZSPICR;  /*!< PWR SUBGHZSPI Control Register,                   Address offset: 0x90 */
-       uint32_t RESERVED2;    /*!< Reserved,                                         Address offset: 0x94 */
-  __IO uint32_t RSSCMDR;      /*!< PWR RSS Command Register,                         Address offset: 0x98 */
-} PWR_TypeDef;
-
-/**
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;           /*!< RCC clock  Control Register,                                                    Address offset: 0x00 */
-  __IO uint32_t ICSCR;        /*!< RCC Internal Clock Sources Calibration Register,                                Address offset: 0x04 */
-  __IO uint32_t CFGR;         /*!< RCC Clocks Configuration Register,                                              Address offset: 0x08 */
-  __IO uint32_t PLLCFGR;      /*!< RCC System PLL configuration Register,                                          Address offset: 0x0C */
-uint32_t RESERVED0;           /*!< Reserved,                                                                       Address offset: 0x10 */
-uint32_t RESERVED1;           /*!< Reserved,                                                                       Address offset: 0x14 */
-  __IO uint32_t CIER;         /*!< RCC Clock Interrupt Enable Register,                                            Address offset: 0x18 */
-  __IO uint32_t CIFR;         /*!< RCC Clock Interrupt Flag Register,                                              Address offset: 0x1C */
-  __IO uint32_t CICR;         /*!< RCC Clock Interrupt Clear Register,                                             Address offset: 0x20 */
-uint32_t RESERVED2;           /*!< Reserved,                                                                       Address offset: 0x24 */
-  __IO uint32_t AHB1RSTR;     /*!< RCC AHB1 peripheral reset register,                                             Address offset: 0x28 */
-  __IO uint32_t AHB2RSTR;     /*!< RCC AHB2 peripheral reset register,                                             Address offset: 0x2C */
-  __IO uint32_t AHB3RSTR;     /*!< RCC AHB3 peripheral reset register,                                             Address offset: 0x30 */
-uint32_t RESERVED3;           /*!< Reserved,                                                                       Address offset: 0x34 */
-  __IO uint32_t APB1RSTR1;    /*!< RCC APB1 peripheral reset register 1,                                           Address offset: 0x38 */
-  __IO uint32_t APB1RSTR2;    /*!< RCC APB1 peripheral reset register 2,                                           Address offset: 0x3C */
-  __IO uint32_t APB2RSTR;     /*!< RCC APB2 peripheral reset register,                                             Address offset: 0x40 */
-  __IO uint32_t APB3RSTR;     /*!< RCC APB3 peripheral reset register,                                             Address offset: 0x44 */
-  __IO uint32_t AHB1ENR;      /*!< RCC AHB1 peripheral clocks enable register,                                     Address offset: 0x48 */
-  __IO uint32_t AHB2ENR;      /*!< RCC AHB2 peripheral clocks enable register,                                     Address offset: 0x4C */
-  __IO uint32_t AHB3ENR;      /*!< RCC AHB3 peripheral clocks enable register,                                     Address offset: 0x50 */
-uint32_t RESERVED4;           /*!< Reserved,                                                                       Address offset: 0x54 */
-  __IO uint32_t APB1ENR1;     /*!< RCC APB1 peripheral clocks enable register 1,                                   Address offset: 0x58 */
-  __IO uint32_t APB1ENR2;     /*!< RCC APB1 peripheral clocks enable register 2,                                   Address offset: 0x5C */
-  __IO uint32_t APB2ENR;      /*!< RCC APB2 peripheral clocks enable register,                                     Address offset: 0x60 */
-  __IO uint32_t APB3ENR;      /*!< RCC APB3 peripheral clocks enable register,                                     Address offset: 0x64 */
-  __IO uint32_t AHB1SMENR;    /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,             Address offset: 0x68 */
-  __IO uint32_t AHB2SMENR;    /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,             Address offset: 0x6C */
-  __IO uint32_t AHB3SMENR;    /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
-uint32_t RESERVED5;           /*!< Reserved,                                                                       Address offset: 0x74 */
-  __IO uint32_t APB1SMENR1;   /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1,      Address offset: 0x78 */
-  __IO uint32_t APB1SMENR2;   /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2,      Address offset: 0x7C */
-  __IO uint32_t APB2SMENR;    /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register,        Address offset: 0x80 */
-  __IO uint32_t APB3SMENR;    /*!< RCC APB3 peripheral clocks enable in sleep mode and stop modes register,        Address offset: 0x84 */
-  __IO uint32_t CCIPR;        /*!< RCC Peripherals Clock Configuration Independent Register,                       Address offset: 0x88 */
-uint32_t RESERVED6;           /*!< Reserved,                                                                       Address offset: 0x8C */
-  __IO uint32_t BDCR;         /*!< RCC Backup Domain Control Register,                                             Address offset: 0x90 */
-  __IO uint32_t CSR;          /*!< RCC Control and Status Register,                                                Address offset: 0x94 */
-uint32_t RESERVED7[28];       /*!< Reserved,                                                                       Address offset: 0x98-0x104 */
-  __IO uint32_t EXTCFGR;      /*!< RCC Extended Clock Recovery Register,                                           Address offset: 0x108 */
-  __IO uint32_t RESERVED8[15]; /*!< Reserved,                                                                      Address offset: 0x10C-0x144 */
-  __IO uint32_t C2AHB1ENR;   /*!< RRCC AHB1 peripheral CPU2 clocks enable register,                                Address offset: 0x148 */
-  __IO uint32_t C2AHB2ENR;   /*!< RCC AHB2 peripheral CPU2 clocks enable register,                                 Address offset: 0x14C */
-  __IO uint32_t C2AHB3ENR;   /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable register,,                         Address offset: 0x150 */
-uint32_t RESERVED9;           /*!< Reserved,                                                                       Address offset: 0x154 */
-  __IO uint32_t C2APB1ENR1;  /*!< RCC APB1 peripheral CPU2 clocks enable register 1,                               Address offset: 0x158 */
-  __IO uint32_t C2APB1ENR2;  /*!< RCC APB1 peripheral CPU2 clocks enable register 2,                               Address offset: 0x15C */
-  __IO uint32_t C2APB2ENR;   /*!< RCC APB2 peripheral CPU2 clocks enable register 1,                               Address offset: 0x160 */
-  __IO uint32_t C2APB3ENR;   /*!< RCC APB3 peripheral CPU2 clocks enable register 1,                               Address offset: 0x164 */
-  __IO uint32_t C2AHB1SMENR; /*!< RCC AHB1 peripheral CPU2 clocks enable in sleep and stop modes register,         Address offset: 0x168 */
-  __IO uint32_t C2AHB2SMENR; /*!< RCC AHB2 peripheral CPU2 clocks enable in sleep and stop modes register,         Address offset: 0x16C */
-  __IO uint32_t C2AHB3SMENR; /*!< RCC AHB3 & AHB4 peripheral CPU2 clocks enable in sleep and stop modes register,  Address offset: 0x170 */
-uint32_t RESERVED10;          /*!< Reserved,                                                                                             */
-  __IO uint32_t C2APB1SMENR1;/*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 1,  Address offset: 0x178 */
-  __IO uint32_t C2APB1SMENR2;/*!< RCC APB1 peripheral CPU2 clocks enable in sleep mode and stop modes register 2,  Address offset: 0x17C */
-  __IO uint32_t C2APB2SMENR; /*!< RCC APB2 peripheral CPU2 clocks enable in sleep mode and stop modes register,    Address offset: 0x180 */
-  __IO uint32_t C2APB3SMENR; /*!< RCC APB3 peripheral CPU2 clocks enable in sleep mode and stop modes register,    Address offset: 0x184 */
-} RCC_TypeDef;
-
-/**
-  * @brief RNG
-  */
-typedef struct
-{
-  __IO uint32_t CR;        /*!< RNG control register,             Address offset: 0x00 */
-  __IO uint32_t SR;        /*!< RNG status register,              Address offset: 0x04 */
-  __IO uint32_t DR;        /*!< RNG data register,                Address offset: 0x08 */
-  uint32_t      RESERVED0; /*!< Reserved,                         Address offset: 0x0C */
-  __IO uint32_t HTCR;      /*!< RNG health test control register, Address offset: 0x10 */
-} RNG_TypeDef;
-
-/**
-  * @brief RTC Specific device feature definitions
-  */
-#define RTC_BACKUP_NB       20u
-#define RTC_TAMP_NB         3u
-
-/**
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
-  __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
-  __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
-  __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
-  __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
-  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
-  __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
-       uint32_t RESERVED0;   /*!< Reserved,                                       Address offset: 0x1C */
-       uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x20 */
-  __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
-  __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
-  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
-  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
-  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
-  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
-       uint32_t RESERVED2;   /*!< Reserved,                                       Address offset: 0x3C */
-  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
-  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
-  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
-  __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
-  __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
-       uint32_t RESERVED3;   /*!< Reserved,                                       Address offset: 0x58 */
-  __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
-       uint32_t RESERVED4[4];/*!< Reserved,                                       Address offset: 0x58 */
-  __IO uint32_t ALRABINR;/*!< RTC alarm A binary mode register,                   Address offset: 0x70 */
-  __IO uint32_t ALRBBINR;/*!< RTC alarm B binary mode register,                   Address offset: 0x74 */
-} RTC_TypeDef;
-
-/**
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/**
-  * @brief System configuration controller
-  */
-typedef struct
-{
-  __IO uint32_t MEMRMP;            /*!< SYSCFG memory remap register                                            Address offset: 0x00       */
-  __IO uint32_t CFGR1;             /*!< SYSCFG configuration register 1,                                        Address offset: 0x04       */
-  __IO uint32_t EXTICR[4];         /*!< SYSCFG external interrupt configuration registers,                      Address offset: 0x08-0x14  */
-  __IO uint32_t SCSR;              /*!< SYSCFG SRAM2 control and status register,                               Address offset: 0x18       */
-  __IO uint32_t CFGR2;             /*!< SYSCFG configuration register 2,                                        Address offset: 0x1C       */
-  __IO uint32_t SWPR;              /*!< SYSCFG SRAM2 write protection register part,                            Address offset: 0x20       */
-  __IO uint32_t SKR;               /*!< SYSCFG SRAM2 key register,                                              Address offset: 0x24       */
-       uint32_t RESERVED1[54];     /*!< Reserved,                                                               Address offset: 0x28-0xFC  */
-  __IO uint32_t IMR1;              /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 1, Address offset: 0x100      */
-  __IO uint32_t IMR2;              /*!< SYSCFG CPU1 (CORTEX M4) interrupt masks control-status register part 2, Address offset: 0x104      */
-  __IO uint32_t C2IMR1;            /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 1, Address offset: 0x108      */
-  __IO uint32_t C2IMR2;            /*!< SYSCFG CPU2 (CORTEX M0) interrupt masks control-status register part 2, Address offset: 0x10C      */
-       uint32_t RESERVED2[62];     /*!< Reserved,                                                               Address offset: 0x110-0x204*/
-  __IO uint32_t RFDCR;             /*!< SYSCFG CPU2 radio debug control register,                               Address offset: 0x208      */
-} SYSCFG_TypeDef;
-
-/**
-  * @brief Tamper and backup registers
-  */
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TAMP configuration register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TAMP configuration register 2,            Address offset: 0x04 */
-  __IO uint32_t CR3;         /*!< TAMP configuration register 3,            Address offset: 0x08 */
-  __IO uint32_t FLTCR;       /*!< TAMP filter control register,             Address offset: 0x0C */
-       uint32_t RESERVED0[7];/*!< Reserved,                                 Address offset: 0x10 */
-  __IO uint32_t IER;         /*!< TAMP interrupt enable register,           Address offset: 0x2C */
-  __IO uint32_t SR;          /*!< TAMP status register,                     Address offset: 0x30 */
-  __IO uint32_t MISR;        /*!< TAMP masked interrupt status register,    Address offset: 0x34 */
-       uint32_t RESERVED1;   /*!< Reserved,                                 Address offset: 0x38 */
-  __IO uint32_t SCR;         /*!< TAMP status clear register,               Address offset: 0x3C */
-  __IO uint32_t COUNTR;      /*!< TAMP monotonic counter register,          Address offset: 0x40 */
-       uint32_t RESERVED2[47];/*!< Reserved,                                Address offset: 0x54 -- 0xFC */
-  __IO uint32_t BKP0R;       /*!< TAMP backup register 0,                   Address offset: 0x100 */
-  __IO uint32_t BKP1R;       /*!< TAMP backup register 1,                   Address offset: 0x104 */
-  __IO uint32_t BKP2R;       /*!< TAMP backup register 2,                   Address offset: 0x108 */
-  __IO uint32_t BKP3R;       /*!< TAMP backup register 3,                   Address offset: 0x10C */
-  __IO uint32_t BKP4R;       /*!< TAMP backup register 4,                   Address offset: 0x110 */
-  __IO uint32_t BKP5R;       /*!< TAMP backup register 5,                   Address offset: 0x114 */
-  __IO uint32_t BKP6R;       /*!< TAMP backup register 6,                   Address offset: 0x118 */
-  __IO uint32_t BKP7R;       /*!< TAMP backup register 7,                   Address offset: 0x11C */
-  __IO uint32_t BKP8R;       /*!< TAMP backup register 8,                   Address offset: 0x120 */
-  __IO uint32_t BKP9R;       /*!< TAMP backup register 9,                   Address offset: 0x124 */
-  __IO uint32_t BKP10R;      /*!< TAMP backup register 10,                  Address offset: 0x128 */
-  __IO uint32_t BKP11R;      /*!< TAMP backup register 11,                  Address offset: 0x12C */
-  __IO uint32_t BKP12R;      /*!< TAMP backup register 12,                  Address offset: 0x130 */
-  __IO uint32_t BKP13R;      /*!< TAMP backup register 13,                  Address offset: 0x134 */
-  __IO uint32_t BKP14R;      /*!< TAMP backup register 14,                  Address offset: 0x138 */
-  __IO uint32_t BKP15R;      /*!< TAMP backup register 15,                  Address offset: 0x13C */
-  __IO uint32_t BKP16R;      /*!< TAMP backup register 16,                  Address offset: 0x140 */
-  __IO uint32_t BKP17R;      /*!< TAMP backup register 17,                  Address offset: 0x144 */
-  __IO uint32_t BKP18R;      /*!< TAMP backup register 18,                  Address offset: 0x148 */
-  __IO uint32_t BKP19R;      /*!< TAMP backup register 19,                  Address offset: 0x14C */
-} TAMP_TypeDef;
-
-/**
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler register,                   Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
-  __IO uint32_t OR1;         /*!< TIM option register                       Address offset: 0x50 */
-  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
-  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
-  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
-  __IO uint32_t AF1;         /*!< TIM Alternate function option register 1, Address offset: 0x60 */
-  __IO uint32_t AF2;         /*!< TIM Alternate function option register 2, Address offset: 0x64 */
-} TIM_TypeDef;
-
-/**
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;               /*!< USART Control register 1,                 Address offset: 0x00  */
-  __IO uint32_t CR2;               /*!< USART Control register 2,                 Address offset: 0x04  */
-  __IO uint32_t CR3;               /*!< USART Control register 3,                 Address offset: 0x08  */
-  __IO uint32_t BRR;               /*!< USART Baud rate register,                 Address offset: 0x0C  */
-  __IO uint32_t GTPR;              /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
-  __IO uint32_t RTOR;              /*!< USART Receiver Time Out register,         Address offset: 0x14  */
-  __IO uint32_t RQR;               /*!< USART Request register,                   Address offset: 0x18  */
-  __IO uint32_t ISR;               /*!< USART Interrupt and status register,      Address offset: 0x1C  */
-  __IO uint32_t ICR;               /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
-  __IO uint32_t RDR;               /*!< USART Receive Data register,              Address offset: 0x24  */
-  __IO uint32_t TDR;               /*!< USART Transmit Data register,             Address offset: 0x28  */
-  __IO uint32_t PRESC;             /*!< USART Prescaler register,                 Address offset: 0x2C  */
-} USART_TypeDef;
-
-/**
-  * @brief VREFBUF
-  */
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
-  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
-} VREFBUF_TypeDef;
-
-/**
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-/*!< Boundary memory map */
-#define FLASH_BASE              0x08000000UL   /*!< FLASH(up to 256 KB) base address */
-#define SYSTEM_FLASH_BASE       0x1FFF0000UL   /*!< System FLASH(28Kb) base address */
-#define SRAM1_BASE              0x20000000UL   /*!< SRAM1(up to 32 KB) base address */
-#define SRAM2_BASE              0x20008000UL   /*!< SRAM2(up to 32 KB) base address */
-#define PERIPH_BASE             0x40000000UL   /*!< Peripheral base address */
-
-#define FLASH_SIZE              (((*((uint32_t *)FLASHSIZE_BASE)) & 0xFFFFU) << 10U)
-#define SRAM1_SIZE              0x00008000UL   /*!< SRAM1 default size : 32 kB */
-#define SRAM2_SIZE              0x00008000UL   /*!< SRAM2 default size : 32 kB  */
-
-/*!< Memory, OTP and Option bytes */
-#define RSSLIB_PFUNC_BASE       (SYSTEM_FLASH_BASE + 0x00003A00UL) /*!< RSS area                                      */
-#define OTP_AREA_BASE           (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 – 0x1FFF73FF)      */
-#define ENGI_BYTES_BASE         (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 – 0x1FFF77FF)    */
-#define OPTION_BYTES_BASE       (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 – 0x1FFF7FFF)  */
-
-/*!< Device Electronic Signature */
-#define PACKAGE_BASE            (ENGI_BYTES_BASE + 0x00000100UL) /*!< Package data register base address     */
-#define UID64_BASE              (ENGI_BYTES_BASE + 0x00000180UL) /*!< 64-bit Unique device Identification    */
-#define UID_BASE                (ENGI_BYTES_BASE + 0x00000190UL) /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE          (ENGI_BYTES_BASE + 0x000001E0UL) /*!< Flash size data register base address  */
-
-#define SYSTEM_MEMORY_END_ADDR  (0x1FFF6FFFUL)   /*!< System Memory : 28KB (0x1FFF0000 – 0x1FFF6FFF)  */
-#define OTP_AREA_END_ADDR       (0x1FFF73FFUL)   /*!< OTP area : 1KB (0x1FFF7000 – 0x1FFF73FF)        */
-#define ENGI_BYTE_END_ADDR      (0x1FFF77FFUL)   /*!< Engi Bytes : 1kB (0x1FFF7400 – 0x1FFF77FF)      */
-#define OPTION_BYTE_END_ADDR    (0x1FFF7FFFUL)   /*!< Option Bytes : 2KB (0x1FFF7800 – 0x1FFF7FFF)    */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE         PERIPH_BASE
-#define APB2PERIPH_BASE         (PERIPH_BASE + 0x00010000UL)
-#define AHB1PERIPH_BASE         (PERIPH_BASE + 0x00020000UL)
-#define AHB2PERIPH_BASE         (PERIPH_BASE + 0x08000000UL)
-#define AHB3PERIPH_BASE         (PERIPH_BASE + 0x18000000UL)
-#define APB3PERIPH_BASE         (PERIPH_BASE + 0x18010000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE               (APB1PERIPH_BASE + 0x00000000UL)
-#define RTC_BASE                (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE               (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE               (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE               (APB1PERIPH_BASE + 0x00003800UL)
-#define USART2_BASE             (APB1PERIPH_BASE + 0x00004400UL)
-#define I2C1_BASE               (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE               (APB1PERIPH_BASE + 0x00005800UL)
-#define I2C3_BASE               (APB1PERIPH_BASE + 0x00005C00UL)
-#define DAC_BASE                (APB1PERIPH_BASE + 0x00007400UL)
-#define LPTIM1_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define LPUART1_BASE            (APB1PERIPH_BASE + 0x00008000UL)
-#define LPTIM2_BASE             (APB1PERIPH_BASE + 0x00009400UL)
-#define LPTIM3_BASE             (APB1PERIPH_BASE + 0x00009800UL)
-#define TAMP_BASE               (APB1PERIPH_BASE + 0x0000B000UL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE             (APB2PERIPH_BASE + 0x00000000UL)
-#define VREFBUF_BASE            (APB2PERIPH_BASE + 0x00000030UL)
-#define COMP1_BASE              (APB2PERIPH_BASE + 0x00000200UL)
-#define COMP2_BASE              (APB2PERIPH_BASE + 0x00000204UL)
-#define ADC_BASE                (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_COMMON_BASE         (APB2PERIPH_BASE + 0x00002708UL)
-#define TIM1_BASE               (APB2PERIPH_BASE + 0x00002C00UL)
-#define SPI1_BASE               (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE             (APB2PERIPH_BASE + 0x00003800UL)
-#define TIM16_BASE              (APB2PERIPH_BASE + 0x00004400UL)
-#define TIM17_BASE              (APB2PERIPH_BASE + 0x00004800UL)
-
-/*!< AHB1 peripherals */
-#define DMA1_BASE               (AHB1PERIPH_BASE + 0x00000000UL)
-#define DMA2_BASE               (AHB1PERIPH_BASE + 0x00000400UL)
-#define DMAMUX1_BASE            (AHB1PERIPH_BASE + 0x00000800UL)
-#define CRC_BASE                (AHB1PERIPH_BASE + 0x00003000UL)
-
-#define DMA1_Channel1_BASE       (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE       (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE       (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE       (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE       (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE       (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE       (DMA1_BASE + 0x00000080UL)
-
-#define DMA2_Channel1_BASE       (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE       (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE       (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE       (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE       (DMA2_BASE + 0x00000058UL)
-#define DMA2_Channel6_BASE       (DMA2_BASE + 0x0000006CUL)
-#define DMA2_Channel7_BASE       (DMA2_BASE + 0x00000080UL)
-
-#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
-#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x00000004UL)
-#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x00000008UL)
-#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x0000000CUL)
-#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x00000010UL)
-#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x00000014UL)
-#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x00000018UL)
-#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x0000001CUL)
-#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x00000020UL)
-#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x00000024UL)
-#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x00000028UL)
-#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x0000002CUL)
-#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x00000030UL)
-#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x00000034UL)
-
-#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x00000100UL)
-#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x00000104UL)
-#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x00000108UL)
-#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x0000010CUL)
-
-#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x00000080UL)
-#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x00000140UL)
-
-/*!< AHB2 peripherals */
-#define IOPORT_BASE             (AHB2PERIPH_BASE + 0x00000000UL)
-#define GPIOA_BASE              (IOPORT_BASE + 0x00000000UL)
-#define GPIOB_BASE              (IOPORT_BASE + 0x00000400UL)
-#define GPIOC_BASE              (IOPORT_BASE + 0x00000800UL)
-#define GPIOH_BASE              (IOPORT_BASE + 0x00001C00UL)
-
-/*!< AHB3 peripherals */
-#define PWR_BASE                (AHB3PERIPH_BASE + 0x00000400UL)
-#define EXTI_BASE               (AHB3PERIPH_BASE + 0x00000800UL)
-#define IPCC_BASE               (AHB3PERIPH_BASE + 0x00000C00UL)
-#define RCC_BASE                (AHB3PERIPH_BASE + 0x00000000UL)
-#define RNG_BASE                (AHB3PERIPH_BASE + 0x00001000UL)
-#define HSEM_BASE               (AHB3PERIPH_BASE + 0x00001400UL)
-#define AES_BASE                (AHB3PERIPH_BASE + 0x00001800UL)
-#define PKA_BASE                (AHB3PERIPH_BASE + 0x00002000UL)
-#define FLASH_REG_BASE          (AHB3PERIPH_BASE + 0x00004000UL)
-#define GTZC_TZSC_BASE          (AHB3PERIPH_BASE + 0x00004400UL)
-#define GTZC_TZIC_BASE          (AHB3PERIPH_BASE + 0x00004800UL)
-
-/*!< APB3 peripherals */
-#define SUBGHZSPI_BASE          (APB3PERIPH_BASE + 0x00000000UL)
-
-#if defined(CORE_CM0PLUS)
-#else
-/*!< Peripherals available on CPU1 external PPB bus */
-#define DBGMCU_BASE             (0xE0042000UL)
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_declaration
-  * @{
-  */
-
-/* Peripherals available on APB1 bus */
-#define TIM2                    ((TIM_TypeDef *) TIM2_BASE)
-#define IWDG                    ((IWDG_TypeDef *) IWDG_BASE)
-#define WWDG                    ((WWDG_TypeDef *) WWDG_BASE)
-#define DAC                     ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1                  ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define LPTIM2                  ((LPTIM_TypeDef *) LPTIM2_BASE)
-#define LPTIM3                  ((LPTIM_TypeDef *) LPTIM3_BASE)
-#define RTC                     ((RTC_TypeDef *) RTC_BASE)
-#define SPI2                    ((SPI_TypeDef *) SPI2_BASE)
-#define I2C1                    ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                    ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                    ((I2C_TypeDef *) I2C3_BASE)
-#define TAMP                    ((TAMP_TypeDef *) TAMP_BASE)
-#define USART2                  ((USART_TypeDef *) USART2_BASE)
-#define LPUART1                 ((USART_TypeDef *) LPUART1_BASE)
-
-/* Peripherals available on APB2 bus */
-#define SYSCFG                  ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define VREFBUF                 ((VREFBUF_TypeDef *) VREFBUF_BASE)
-#define COMP1                   ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2                   ((COMP_TypeDef *) COMP2_BASE)
-#define COMP12_COMMON           ((COMP_Common_TypeDef *) COMP2_BASE)
-#define TIM1                    ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1                    ((SPI_TypeDef *) SPI1_BASE)
-#define ADC                     ((ADC_TypeDef *) ADC_BASE)
-#define ADC_COMMON              ((ADC_Common_TypeDef *) ADC_COMMON_BASE)
-#define TIM16                   ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17                   ((TIM_TypeDef *) TIM17_BASE)
-#define USART1                  ((USART_TypeDef *) USART1_BASE)
-
-/* Peripherals available on AHB1 bus */
-#define DMA1                    ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1           ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2           ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3           ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4           ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5           ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6           ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7           ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-
-#define DMA2                    ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1           ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2           ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3           ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4           ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5           ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DMA2_Channel6           ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
-#define DMA2_Channel7           ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
-
-#define DMAMUX1                 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
-#define DMAMUX1_Channel0        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
-#define DMAMUX1_Channel1        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
-#define DMAMUX1_Channel2        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
-#define DMAMUX1_Channel3        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
-#define DMAMUX1_Channel4        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
-#define DMAMUX1_Channel5        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
-#define DMAMUX1_Channel6        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
-#define DMAMUX1_Channel7        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
-#define DMAMUX1_Channel8        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
-#define DMAMUX1_Channel9        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
-#define DMAMUX1_Channel10       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
-#define DMAMUX1_Channel11       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
-#define DMAMUX1_Channel12       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
-#define DMAMUX1_Channel13       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
-
-#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
-#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
-#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
-#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
-
-#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
-#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
-
-#define CRC                     ((CRC_TypeDef *) CRC_BASE)
-
-/* Peripherals available on AHB2 bus */
-#define GPIOA                   ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB                   ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC                   ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOH                   ((GPIO_TypeDef *) GPIOH_BASE)
-
-/* Peripherals available on AH3 bus */
-#define AES                     ((AES_TypeDef *) AES_BASE)
-
-#define EXTI                    ((EXTI_TypeDef *) EXTI_BASE)
-#define IPCC                    ((IPCC_TypeDef *) IPCC_BASE)
-#define IPCC_C1                 ((IPCC_CommonTypeDef *) IPCC_BASE)
-#define IPCC_C2                 ((IPCC_CommonTypeDef *) (IPCC_BASE + 0x10U))
-#define RCC                     ((RCC_TypeDef *) RCC_BASE)
-#define PWR                     ((PWR_TypeDef *) PWR_BASE)
-#define RNG                     ((RNG_TypeDef *) RNG_BASE)
-#define HSEM                    ((HSEM_TypeDef *) HSEM_BASE)
-#if defined(CORE_CM0PLUS)
-#define HSEM_COMMON             ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110U))
-#else
-#define HSEM_COMMON             ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U))
-#endif
-#define PKA                     ((PKA_TypeDef *) PKA_BASE)
-#define FLASH                   ((FLASH_TypeDef *) FLASH_REG_BASE)
-#define GTZC_TZSC               ((GTZC_TZSC_TypeDef *) GTZC_TZSC_BASE)
-#define GTZC_TZIC               ((GTZC_TZIC_TypeDef *) GTZC_TZIC_BASE)
-
-/* Peripherals available on APB3 bus */
-#define SUBGHZSPI               ((SPI_TypeDef *) SUBGHZSPI_BASE)
-
-#if defined(CORE_CM0PLUS)
-#else
-/* Peripherals available on CPU1 external PPB bus */
-#define DBGMCU                  ((DBGMCU_TypeDef *) DBGMCU_BASE)
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-/** @addtogroup Hardware_Constant_Definition
-  * @{
-  */
-#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_ISR register  *******************/
-#define ADC_ISR_ADRDY_Pos              (0U)
-#define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
-#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
-#define ADC_ISR_EOSMP_Pos              (1U)
-#define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
-#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
-#define ADC_ISR_EOC_Pos                (2U)
-#define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
-#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
-#define ADC_ISR_EOS_Pos                (3U)
-#define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
-#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
-#define ADC_ISR_OVR_Pos                (4U)
-#define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
-#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
-#define ADC_ISR_AWD1_Pos               (7U)
-#define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
-#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
-#define ADC_ISR_AWD2_Pos               (8U)
-#define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
-#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
-#define ADC_ISR_AWD3_Pos               (9U)
-#define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
-#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
-#define ADC_ISR_EOCAL_Pos              (11U)
-#define ADC_ISR_EOCAL_Msk              (0x1UL << ADC_ISR_EOCAL_Pos)            /*!< 0x00000800 */
-#define ADC_ISR_EOCAL                  ADC_ISR_EOCAL_Msk                       /*!< ADC end of calibration flag */
-#define ADC_ISR_CCRDY_Pos              (13U)
-#define ADC_ISR_CCRDY_Msk              (0x1UL << ADC_ISR_CCRDY_Pos)            /*!< 0x00002000 */
-#define ADC_ISR_CCRDY                  ADC_ISR_CCRDY_Msk                       /*!< ADC channel configuration ready flag */
-
-/********************  Bit definition for ADC_IER register  *******************/
-#define ADC_IER_ADRDYIE_Pos            (0U)
-#define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
-#define ADC_IER_EOSMPIE_Pos            (1U)
-#define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
-#define ADC_IER_EOCIE_Pos              (2U)
-#define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
-#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
-#define ADC_IER_EOSIE_Pos              (3U)
-#define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
-#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
-#define ADC_IER_OVRIE_Pos              (4U)
-#define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
-#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
-#define ADC_IER_AWD1IE_Pos             (7U)
-#define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
-#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
-#define ADC_IER_AWD2IE_Pos             (8U)
-#define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
-#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
-#define ADC_IER_AWD3IE_Pos             (9U)
-#define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
-#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
-#define ADC_IER_EOCALIE_Pos            (11U)
-#define ADC_IER_EOCALIE_Msk            (0x1UL << ADC_IER_EOCALIE_Pos)          /*!< 0x00000800 */
-#define ADC_IER_EOCALIE                ADC_IER_EOCALIE_Msk                     /*!< ADC end of calibration interrupt */
-#define ADC_IER_CCRDYIE_Pos            (13U)
-#define ADC_IER_CCRDYIE_Msk            (0x1UL << ADC_IER_CCRDYIE_Pos)          /*!< 0x00002000 */
-#define ADC_IER_CCRDYIE                ADC_IER_CCRDYIE_Msk                     /*!< ADC channel configuration ready interrupt */
-
-/********************  Bit definition for ADC_CR register  ********************/
-#define ADC_CR_ADEN_Pos                (0U)
-#define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
-#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
-#define ADC_CR_ADDIS_Pos               (1U)
-#define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
-#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
-#define ADC_CR_ADSTART_Pos             (2U)
-#define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
-#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
-#define ADC_CR_ADSTP_Pos               (4U)
-#define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
-#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
-#define ADC_CR_ADVREGEN_Pos            (28U)
-#define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
-#define ADC_CR_ADCAL_Pos               (31U)
-#define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
-#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
-
-/********************  Bit definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_DMAEN_Pos            (0U)
-#define ADC_CFGR1_DMAEN_Msk            (0x1UL << ADC_CFGR1_DMAEN_Pos)          /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN                ADC_CFGR1_DMAEN_Msk                     /*!< ADC DMA transfer enable */
-#define ADC_CFGR1_DMACFG_Pos           (1U)
-#define ADC_CFGR1_DMACFG_Msk           (0x1UL << ADC_CFGR1_DMACFG_Pos)         /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG               ADC_CFGR1_DMACFG_Msk                    /*!< ADC DMA transfer configuration */
-
-#define ADC_CFGR1_SCANDIR_Pos          (2U)
-#define ADC_CFGR1_SCANDIR_Msk          (0x1UL << ADC_CFGR1_SCANDIR_Pos)        /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR              ADC_CFGR1_SCANDIR_Msk                   /*!< ADC group regular sequencer scan direction */
-
-#define ADC_CFGR1_RES_Pos              (3U)
-#define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000018 */
-#define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
-#define ADC_CFGR1_RES_0                (0x1UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1                (0x2UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000010 */
-
-#define ADC_CFGR1_ALIGN_Pos            (5U)
-#define ADC_CFGR1_ALIGN_Msk            (0x1UL << ADC_CFGR1_ALIGN_Pos)          /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN                ADC_CFGR1_ALIGN_Msk                     /*!< ADC data alignement */
-
-#define ADC_CFGR1_EXTSEL_Pos           (6U)
-#define ADC_CFGR1_EXTSEL_Msk           (0x7UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
-#define ADC_CFGR1_EXTSEL_0             (0x1UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1             (0x2UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2             (0x4UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000100 */
-
-#define ADC_CFGR1_EXTEN_Pos            (10U)
-#define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
-#define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */
-
-#define ADC_CFGR1_OVRMOD_Pos           (12U)
-#define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
-#define ADC_CFGR1_CONT_Pos             (13U)
-#define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
-#define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
-#define ADC_CFGR1_WAIT_Pos             (14U)
-#define ADC_CFGR1_WAIT_Msk             (0x1UL << ADC_CFGR1_WAIT_Pos)           /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT                 ADC_CFGR1_WAIT_Msk                      /*!< ADC low power auto wait */
-#define ADC_CFGR1_AUTOFF_Pos           (15U)
-#define ADC_CFGR1_AUTOFF_Msk           (0x1UL << ADC_CFGR1_AUTOFF_Pos)         /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF               ADC_CFGR1_AUTOFF_Msk                    /*!< ADC low power auto power off */
-#define ADC_CFGR1_DISCEN_Pos           (16U)
-#define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CFGR1_CHSELRMOD_Pos        (21U)
-#define ADC_CFGR1_CHSELRMOD_Msk        (0x1UL << ADC_CFGR1_CHSELRMOD_Pos)      /*!< 0x00200000 */
-#define ADC_CFGR1_CHSELRMOD            ADC_CFGR1_CHSELRMOD_Msk                 /*!< ADC group regular sequencer mode */
-
-#define ADC_CFGR1_AWD1SGL_Pos          (22U)
-#define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
-#define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CFGR1_AWD1EN_Pos           (23U)
-#define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
-#define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CFGR1_AWD1CH_Pos           (26U)
-#define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
-#define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
-#define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
-#define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
-#define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
-#define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */
-
-/********************  Bit definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_OVSE_Pos             (0U)
-#define ADC_CFGR2_OVSE_Msk             (0x1UL << ADC_CFGR2_OVSE_Pos)           /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE                 ADC_CFGR2_OVSE_Msk                      /*!< ADC oversampler enable on scope ADC group regular */
-
-#define ADC_CFGR2_OVSR_Pos             (2U)
-#define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
-#define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
-
-#define ADC_CFGR2_OVSS_Pos             (5U)
-#define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
-#define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
-
-#define ADC_CFGR2_TOVS_Pos             (9U)
-#define ADC_CFGR2_TOVS_Msk             (0x1UL << ADC_CFGR2_TOVS_Pos)           /*!< 0x00000200 */
-#define ADC_CFGR2_TOVS                 ADC_CFGR2_TOVS_Msk                      /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
-
-#define ADC_CFGR2_LFTRIG_Pos           (29U)
-#define ADC_CFGR2_LFTRIG_Msk           (0x1UL << ADC_CFGR2_LFTRIG_Pos)         /*!< 0x20000000 */
-#define ADC_CFGR2_LFTRIG               ADC_CFGR2_LFTRIG_Msk                    /*!< ADC low frequency trigger mode */
-
-#define ADC_CFGR2_CKMODE_Pos           (30U)
-#define ADC_CFGR2_CKMODE_Msk           (0x3UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE               ADC_CFGR2_CKMODE_Msk                    /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
-#define ADC_CFGR2_CKMODE_1             (0x2UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x80000000 */
-#define ADC_CFGR2_CKMODE_0             (0x1UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x40000000 */
-
-/********************  Bit definition for ADC_SMPR register  ******************/
-#define ADC_SMPR_SMP1_Pos              (0U)
-#define ADC_SMPR_SMP1_Msk              (0x7UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000007 */
-#define ADC_SMPR_SMP1                  ADC_SMPR_SMP1_Msk                       /*!< ADC group of channels sampling time 1 */
-#define ADC_SMPR_SMP1_0                (0x1UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000001 */
-#define ADC_SMPR_SMP1_1                (0x2UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000002 */
-#define ADC_SMPR_SMP1_2                (0x4UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000004 */
-
-#define ADC_SMPR_SMP2_Pos              (4U)
-#define ADC_SMPR_SMP2_Msk              (0x7UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000070 */
-#define ADC_SMPR_SMP2                  ADC_SMPR_SMP2_Msk                       /*!< ADC group of channels sampling time 2 */
-#define ADC_SMPR_SMP2_0                (0x1UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000010 */
-#define ADC_SMPR_SMP2_1                (0x2UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000020 */
-#define ADC_SMPR_SMP2_2                (0x4UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000040 */
-
-#define ADC_SMPR_SMPSEL_Pos            (8U)
-#define ADC_SMPR_SMPSEL_Msk            (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos)      /*!< 0x03FFFF00 */
-#define ADC_SMPR_SMPSEL                ADC_SMPR_SMPSEL_Msk                     /*!< ADC all channels sampling time selection */
-#define ADC_SMPR_SMPSEL0_Pos           (8U)
-#define ADC_SMPR_SMPSEL0_Msk           (0x1UL << ADC_SMPR_SMPSEL0_Pos)         /*!< 0x00000100 */
-#define ADC_SMPR_SMPSEL0               ADC_SMPR_SMPSEL0_Msk                    /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR_SMPSEL1_Pos           (9U)
-#define ADC_SMPR_SMPSEL1_Msk           (0x1UL << ADC_SMPR_SMPSEL1_Pos)         /*!< 0x00000200 */
-#define ADC_SMPR_SMPSEL1               ADC_SMPR_SMPSEL1_Msk                    /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR_SMPSEL2_Pos           (10U)
-#define ADC_SMPR_SMPSEL2_Msk           (0x1UL << ADC_SMPR_SMPSEL2_Pos)         /*!< 0x00000400 */
-#define ADC_SMPR_SMPSEL2               ADC_SMPR_SMPSEL2_Msk                    /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR_SMPSEL3_Pos           (11U)
-#define ADC_SMPR_SMPSEL3_Msk           (0x1UL << ADC_SMPR_SMPSEL3_Pos)         /*!< 0x00000800 */
-#define ADC_SMPR_SMPSEL3               ADC_SMPR_SMPSEL3_Msk                    /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR_SMPSEL4_Pos           (12U)
-#define ADC_SMPR_SMPSEL4_Msk           (0x1UL << ADC_SMPR_SMPSEL4_Pos)         /*!< 0x00001000 */
-#define ADC_SMPR_SMPSEL4               ADC_SMPR_SMPSEL4_Msk                    /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR_SMPSEL5_Pos           (13U)
-#define ADC_SMPR_SMPSEL5_Msk           (0x1UL << ADC_SMPR_SMPSEL5_Pos)         /*!< 0x00002000 */
-#define ADC_SMPR_SMPSEL5               ADC_SMPR_SMPSEL5_Msk                    /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR_SMPSEL6_Pos           (14U)
-#define ADC_SMPR_SMPSEL6_Msk           (0x1UL << ADC_SMPR_SMPSEL6_Pos)         /*!< 0x00004000 */
-#define ADC_SMPR_SMPSEL6               ADC_SMPR_SMPSEL6_Msk                    /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR_SMPSEL7_Pos           (15U)
-#define ADC_SMPR_SMPSEL7_Msk           (0x1UL << ADC_SMPR_SMPSEL7_Pos)         /*!< 0x00008000 */
-#define ADC_SMPR_SMPSEL7               ADC_SMPR_SMPSEL7_Msk                    /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR_SMPSEL8_Pos           (16U)
-#define ADC_SMPR_SMPSEL8_Msk           (0x1UL << ADC_SMPR_SMPSEL8_Pos)         /*!< 0x00010000 */
-#define ADC_SMPR_SMPSEL8               ADC_SMPR_SMPSEL8_Msk                    /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR_SMPSEL9_Pos           (17U)
-#define ADC_SMPR_SMPSEL9_Msk           (0x1UL << ADC_SMPR_SMPSEL9_Pos)         /*!< 0x00020000 */
-#define ADC_SMPR_SMPSEL9               ADC_SMPR_SMPSEL9_Msk                    /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR_SMPSEL10_Pos          (18U)
-#define ADC_SMPR_SMPSEL10_Msk          (0x1UL << ADC_SMPR_SMPSEL10_Pos)        /*!< 0x00040000 */
-#define ADC_SMPR_SMPSEL10              ADC_SMPR_SMPSEL10_Msk                   /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR_SMPSEL11_Pos          (19U)
-#define ADC_SMPR_SMPSEL11_Msk          (0x1UL << ADC_SMPR_SMPSEL11_Pos)        /*!< 0x00080000 */
-#define ADC_SMPR_SMPSEL11              ADC_SMPR_SMPSEL11_Msk                   /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR_SMPSEL12_Pos          (20U)
-#define ADC_SMPR_SMPSEL12_Msk          (0x1UL << ADC_SMPR_SMPSEL12_Pos)        /*!< 0x00100000 */
-#define ADC_SMPR_SMPSEL12              ADC_SMPR_SMPSEL12_Msk                   /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR_SMPSEL13_Pos          (21U)
-#define ADC_SMPR_SMPSEL13_Msk          (0x1UL << ADC_SMPR_SMPSEL13_Pos)        /*!< 0x00200000 */
-#define ADC_SMPR_SMPSEL13              ADC_SMPR_SMPSEL13_Msk                   /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR_SMPSEL14_Pos          (22U)
-#define ADC_SMPR_SMPSEL14_Msk          (0x1UL << ADC_SMPR_SMPSEL14_Pos)        /*!< 0x00400000 */
-#define ADC_SMPR_SMPSEL14              ADC_SMPR_SMPSEL14_Msk                   /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR_SMPSEL15_Pos          (23U)
-#define ADC_SMPR_SMPSEL15_Msk          (0x1UL << ADC_SMPR_SMPSEL15_Pos)        /*!< 0x00800000 */
-#define ADC_SMPR_SMPSEL15              ADC_SMPR_SMPSEL15_Msk                   /*!< ADC channel 15 sampling time selection */
-#define ADC_SMPR_SMPSEL16_Pos          (24U)
-#define ADC_SMPR_SMPSEL16_Msk          (0x1UL << ADC_SMPR_SMPSEL16_Pos)        /*!< 0x01000000 */
-#define ADC_SMPR_SMPSEL16              ADC_SMPR_SMPSEL16_Msk                   /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR_SMPSEL17_Pos          (25U)
-#define ADC_SMPR_SMPSEL17_Msk          (0x1UL << ADC_SMPR_SMPSEL17_Pos)        /*!< 0x02000000 */
-#define ADC_SMPR_SMPSEL17              ADC_SMPR_SMPSEL17_Msk                   /*!< ADC channel 17 sampling time selection */
-
-/********************  Bit definition for ADC_TR1 register  *******************/
-#define ADC_TR1_LT1_Pos                (0U)
-#define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
-#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
-#define ADC_TR1_LT1_0                  (0x001UL << ADC_TR1_LT1_Pos)            /*!< 0x00000001 */
-#define ADC_TR1_LT1_1                  (0x002UL << ADC_TR1_LT1_Pos)            /*!< 0x00000002 */
-#define ADC_TR1_LT1_2                  (0x004UL << ADC_TR1_LT1_Pos)            /*!< 0x00000004 */
-#define ADC_TR1_LT1_3                  (0x008UL << ADC_TR1_LT1_Pos)            /*!< 0x00000008 */
-#define ADC_TR1_LT1_4                  (0x010UL << ADC_TR1_LT1_Pos)            /*!< 0x00000010 */
-#define ADC_TR1_LT1_5                  (0x020UL << ADC_TR1_LT1_Pos)            /*!< 0x00000020 */
-#define ADC_TR1_LT1_6                  (0x040UL << ADC_TR1_LT1_Pos)            /*!< 0x00000040 */
-#define ADC_TR1_LT1_7                  (0x080UL << ADC_TR1_LT1_Pos)            /*!< 0x00000080 */
-#define ADC_TR1_LT1_8                  (0x100UL << ADC_TR1_LT1_Pos)            /*!< 0x00000100 */
-#define ADC_TR1_LT1_9                  (0x200UL << ADC_TR1_LT1_Pos)            /*!< 0x00000200 */
-#define ADC_TR1_LT1_10                 (0x400UL << ADC_TR1_LT1_Pos)            /*!< 0x00000400 */
-#define ADC_TR1_LT1_11                 (0x800UL << ADC_TR1_LT1_Pos)            /*!< 0x00000800 */
-
-#define ADC_TR1_HT1_Pos                (16U)
-#define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
-#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
-#define ADC_TR1_HT1_0                  (0x001UL << ADC_TR1_HT1_Pos)            /*!< 0x00010000 */
-#define ADC_TR1_HT1_1                  (0x002UL << ADC_TR1_HT1_Pos)            /*!< 0x00020000 */
-#define ADC_TR1_HT1_2                  (0x004UL << ADC_TR1_HT1_Pos)            /*!< 0x00040000 */
-#define ADC_TR1_HT1_3                  (0x008UL << ADC_TR1_HT1_Pos)            /*!< 0x00080000 */
-#define ADC_TR1_HT1_4                  (0x010UL << ADC_TR1_HT1_Pos)            /*!< 0x00100000 */
-#define ADC_TR1_HT1_5                  (0x020UL << ADC_TR1_HT1_Pos)            /*!< 0x00200000 */
-#define ADC_TR1_HT1_6                  (0x040UL << ADC_TR1_HT1_Pos)            /*!< 0x00400000 */
-#define ADC_TR1_HT1_7                  (0x080UL << ADC_TR1_HT1_Pos)            /*!< 0x00800000 */
-#define ADC_TR1_HT1_8                  (0x100UL << ADC_TR1_HT1_Pos)            /*!< 0x01000000 */
-#define ADC_TR1_HT1_9                  (0x200UL << ADC_TR1_HT1_Pos)            /*!< 0x02000000 */
-#define ADC_TR1_HT1_10                 (0x400UL << ADC_TR1_HT1_Pos)            /*!< 0x04000000 */
-#define ADC_TR1_HT1_11                 (0x800UL << ADC_TR1_HT1_Pos)            /*!< 0x08000000 */
-
-/********************  Bit definition for ADC_TR2 register  *******************/
-#define ADC_TR2_LT2_Pos                (0U)
-#define ADC_TR2_LT2_Msk                (0xFFFUL << ADC_TR2_LT2_Pos)            /*!< 0x00000FFF */
-#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
-#define ADC_TR2_LT2_0                  (0x001UL << ADC_TR2_LT2_Pos)            /*!< 0x00000001 */
-#define ADC_TR2_LT2_1                  (0x002UL << ADC_TR2_LT2_Pos)            /*!< 0x00000002 */
-#define ADC_TR2_LT2_2                  (0x004UL << ADC_TR2_LT2_Pos)            /*!< 0x00000004 */
-#define ADC_TR2_LT2_3                  (0x008UL << ADC_TR2_LT2_Pos)            /*!< 0x00000008 */
-#define ADC_TR2_LT2_4                  (0x010UL << ADC_TR2_LT2_Pos)            /*!< 0x00000010 */
-#define ADC_TR2_LT2_5                  (0x020UL << ADC_TR2_LT2_Pos)            /*!< 0x00000020 */
-#define ADC_TR2_LT2_6                  (0x040UL << ADC_TR2_LT2_Pos)            /*!< 0x00000040 */
-#define ADC_TR2_LT2_7                  (0x080UL << ADC_TR2_LT2_Pos)            /*!< 0x00000080 */
-#define ADC_TR2_LT2_8                  (0x100UL << ADC_TR2_LT2_Pos)            /*!< 0x00000100 */
-#define ADC_TR2_LT2_9                  (0x200UL << ADC_TR2_LT2_Pos)            /*!< 0x00000200 */
-#define ADC_TR2_LT2_10                 (0x400UL << ADC_TR2_LT2_Pos)            /*!< 0x00000400 */
-#define ADC_TR2_LT2_11                 (0x800UL << ADC_TR2_LT2_Pos)            /*!< 0x00000800 */
-
-#define ADC_TR2_HT2_Pos                (16U)
-#define ADC_TR2_HT2_Msk                (0xFFFUL << ADC_TR2_HT2_Pos)            /*!< 0x0FFF0000 */
-#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
-#define ADC_TR2_HT2_0                  (0x001UL << ADC_TR2_HT2_Pos)            /*!< 0x00010000 */
-#define ADC_TR2_HT2_1                  (0x002UL << ADC_TR2_HT2_Pos)            /*!< 0x00020000 */
-#define ADC_TR2_HT2_2                  (0x004UL << ADC_TR2_HT2_Pos)            /*!< 0x00040000 */
-#define ADC_TR2_HT2_3                  (0x008UL << ADC_TR2_HT2_Pos)            /*!< 0x00080000 */
-#define ADC_TR2_HT2_4                  (0x010UL << ADC_TR2_HT2_Pos)            /*!< 0x00100000 */
-#define ADC_TR2_HT2_5                  (0x020UL << ADC_TR2_HT2_Pos)            /*!< 0x00200000 */
-#define ADC_TR2_HT2_6                  (0x040UL << ADC_TR2_HT2_Pos)            /*!< 0x00400000 */
-#define ADC_TR2_HT2_7                  (0x080UL << ADC_TR2_HT2_Pos)            /*!< 0x00800000 */
-#define ADC_TR2_HT2_8                  (0x100UL << ADC_TR2_HT2_Pos)            /*!< 0x01000000 */
-#define ADC_TR2_HT2_9                  (0x200UL << ADC_TR2_HT2_Pos)            /*!< 0x02000000 */
-#define ADC_TR2_HT2_10                 (0x400UL << ADC_TR2_HT2_Pos)            /*!< 0x04000000 */
-#define ADC_TR2_HT2_11                 (0x800UL << ADC_TR2_HT2_Pos)            /*!< 0x08000000 */
-
-/********************  Bit definition for ADC_CHSELR register  ****************/
-#define ADC_CHSELR_CHSEL_Pos           (0U)
-#define ADC_CHSELR_CHSEL_Msk           (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos)     /*!< 0x0003FFFF */
-#define ADC_CHSELR_CHSEL               ADC_CHSELR_CHSEL_Msk                    /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL17_Pos         (17U)
-#define ADC_CHSELR_CHSEL17_Msk         (0x1UL << ADC_CHSELR_CHSEL17_Pos)       /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17             ADC_CHSELR_CHSEL17_Msk                  /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL16_Pos         (16U)
-#define ADC_CHSELR_CHSEL16_Msk         (0x1UL << ADC_CHSELR_CHSEL16_Pos)       /*!< 0x00010000 */
-#define ADC_CHSELR_CHSEL16             ADC_CHSELR_CHSEL16_Msk                  /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL15_Pos         (15U)
-#define ADC_CHSELR_CHSEL15_Msk         (0x1UL << ADC_CHSELR_CHSEL15_Pos)       /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15             ADC_CHSELR_CHSEL15_Msk                  /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL14_Pos         (14U)
-#define ADC_CHSELR_CHSEL14_Msk         (0x1UL << ADC_CHSELR_CHSEL14_Pos)       /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14             ADC_CHSELR_CHSEL14_Msk                  /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL13_Pos         (13U)
-#define ADC_CHSELR_CHSEL13_Msk         (0x1UL << ADC_CHSELR_CHSEL13_Pos)       /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13             ADC_CHSELR_CHSEL13_Msk                  /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL12_Pos         (12U)
-#define ADC_CHSELR_CHSEL12_Msk         (0x1UL << ADC_CHSELR_CHSEL12_Pos)       /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12             ADC_CHSELR_CHSEL12_Msk                  /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL11_Pos         (11U)
-#define ADC_CHSELR_CHSEL11_Msk         (0x1UL << ADC_CHSELR_CHSEL11_Pos)       /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11             ADC_CHSELR_CHSEL11_Msk                  /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL10_Pos         (10U)
-#define ADC_CHSELR_CHSEL10_Msk         (0x1UL << ADC_CHSELR_CHSEL10_Pos)       /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10             ADC_CHSELR_CHSEL10_Msk                  /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL9_Pos          (9U)
-#define ADC_CHSELR_CHSEL9_Msk          (0x1UL << ADC_CHSELR_CHSEL9_Pos)        /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9              ADC_CHSELR_CHSEL9_Msk                   /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL8_Pos          (8U)
-#define ADC_CHSELR_CHSEL8_Msk          (0x1UL << ADC_CHSELR_CHSEL8_Pos)        /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8              ADC_CHSELR_CHSEL8_Msk                   /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL7_Pos          (7U)
-#define ADC_CHSELR_CHSEL7_Msk          (0x1UL << ADC_CHSELR_CHSEL7_Pos)        /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7              ADC_CHSELR_CHSEL7_Msk                   /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL6_Pos          (6U)
-#define ADC_CHSELR_CHSEL6_Msk          (0x1UL << ADC_CHSELR_CHSEL6_Pos)        /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6              ADC_CHSELR_CHSEL6_Msk                   /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL5_Pos          (5U)
-#define ADC_CHSELR_CHSEL5_Msk          (0x1UL << ADC_CHSELR_CHSEL5_Pos)        /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5              ADC_CHSELR_CHSEL5_Msk                   /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL4_Pos          (4U)
-#define ADC_CHSELR_CHSEL4_Msk          (0x1UL << ADC_CHSELR_CHSEL4_Pos)        /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4              ADC_CHSELR_CHSEL4_Msk                   /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL3_Pos          (3U)
-#define ADC_CHSELR_CHSEL3_Msk          (0x1UL << ADC_CHSELR_CHSEL3_Pos)        /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3              ADC_CHSELR_CHSEL3_Msk                   /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL2_Pos          (2U)
-#define ADC_CHSELR_CHSEL2_Msk          (0x1UL << ADC_CHSELR_CHSEL2_Pos)        /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2              ADC_CHSELR_CHSEL2_Msk                   /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL1_Pos          (1U)
-#define ADC_CHSELR_CHSEL1_Msk          (0x1UL << ADC_CHSELR_CHSEL1_Pos)        /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1              ADC_CHSELR_CHSEL1_Msk                   /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL0_Pos          (0U)
-#define ADC_CHSELR_CHSEL0_Msk          (0x1UL << ADC_CHSELR_CHSEL0_Pos)        /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0              ADC_CHSELR_CHSEL0_Msk                   /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
-
-#define ADC_CHSELR_SQ_ALL_Pos          (0U)
-#define ADC_CHSELR_SQ_ALL_Msk          (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
-#define ADC_CHSELR_SQ_ALL              ADC_CHSELR_SQ_ALL_Msk                   /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
-
-#define ADC_CHSELR_SQ8_Pos             (28U)
-#define ADC_CHSELR_SQ8_Msk             (0xFUL << ADC_CHSELR_SQ8_Pos)           /*!< 0xF0000000 */
-#define ADC_CHSELR_SQ8                 ADC_CHSELR_SQ8_Msk                      /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ8_0               (0x1UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x10000000 */
-#define ADC_CHSELR_SQ8_1               (0x2UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x20000000 */
-#define ADC_CHSELR_SQ8_2               (0x4UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x40000000 */
-#define ADC_CHSELR_SQ8_3               (0x8UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x80000000 */
-
-#define ADC_CHSELR_SQ7_Pos             (24U)
-#define ADC_CHSELR_SQ7_Msk             (0xFUL << ADC_CHSELR_SQ7_Pos)           /*!< 0x0F000000 */
-#define ADC_CHSELR_SQ7                 ADC_CHSELR_SQ7_Msk                      /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ7_0               (0x1UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x01000000 */
-#define ADC_CHSELR_SQ7_1               (0x2UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x02000000 */
-#define ADC_CHSELR_SQ7_2               (0x4UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x04000000 */
-#define ADC_CHSELR_SQ7_3               (0x8UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x08000000 */
-
-#define ADC_CHSELR_SQ6_Pos             (20U)
-#define ADC_CHSELR_SQ6_Msk             (0xFUL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00F00000 */
-#define ADC_CHSELR_SQ6                 ADC_CHSELR_SQ6_Msk                      /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ6_0               (0x1UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00100000 */
-#define ADC_CHSELR_SQ6_1               (0x2UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00200000 */
-#define ADC_CHSELR_SQ6_2               (0x4UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00400000 */
-#define ADC_CHSELR_SQ6_3               (0x8UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00800000 */
-
-#define ADC_CHSELR_SQ5_Pos             (16U)
-#define ADC_CHSELR_SQ5_Msk             (0xFUL << ADC_CHSELR_SQ5_Pos)           /*!< 0x000F0000 */
-#define ADC_CHSELR_SQ5                 ADC_CHSELR_SQ5_Msk                      /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ5_0               (0x1UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00010000 */
-#define ADC_CHSELR_SQ5_1               (0x2UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00020000 */
-#define ADC_CHSELR_SQ5_2               (0x4UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00040000 */
-#define ADC_CHSELR_SQ5_3               (0x8UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00080000 */
-
-#define ADC_CHSELR_SQ4_Pos             (12U)
-#define ADC_CHSELR_SQ4_Msk             (0xFUL << ADC_CHSELR_SQ4_Pos)           /*!< 0x0000F000 */
-#define ADC_CHSELR_SQ4                 ADC_CHSELR_SQ4_Msk                      /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ4_0               (0x1UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00001000 */
-#define ADC_CHSELR_SQ4_1               (0x2UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00002000 */
-#define ADC_CHSELR_SQ4_2               (0x4UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00004000 */
-#define ADC_CHSELR_SQ4_3               (0x8UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00008000 */
-
-#define ADC_CHSELR_SQ3_Pos             (8U)
-#define ADC_CHSELR_SQ3_Msk             (0xFUL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000F00 */
-#define ADC_CHSELR_SQ3                 ADC_CHSELR_SQ3_Msk                      /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ3_0               (0x1UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000100 */
-#define ADC_CHSELR_SQ3_1               (0x2UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000200 */
-#define ADC_CHSELR_SQ3_2               (0x4UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000400 */
-#define ADC_CHSELR_SQ3_3               (0x8UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000800 */
-
-#define ADC_CHSELR_SQ2_Pos             (4U)
-#define ADC_CHSELR_SQ2_Msk             (0xFUL << ADC_CHSELR_SQ2_Pos)           /*!< 0x000000F0 */
-#define ADC_CHSELR_SQ2                 ADC_CHSELR_SQ2_Msk                      /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ2_0               (0x1UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000010 */
-#define ADC_CHSELR_SQ2_1               (0x2UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000020 */
-#define ADC_CHSELR_SQ2_2               (0x4UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000040 */
-#define ADC_CHSELR_SQ2_3               (0x8UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000080 */
-
-#define ADC_CHSELR_SQ1_Pos             (0U)
-#define ADC_CHSELR_SQ1_Msk             (0xFUL << ADC_CHSELR_SQ1_Pos)           /*!< 0x0000000F */
-#define ADC_CHSELR_SQ1                 ADC_CHSELR_SQ1_Msk                      /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ1_0               (0x1UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000001 */
-#define ADC_CHSELR_SQ1_1               (0x2UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000002 */
-#define ADC_CHSELR_SQ1_2               (0x4UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000004 */
-#define ADC_CHSELR_SQ1_3               (0x8UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000008 */
-
-/********************  Bit definition for ADC_TR3 register  *******************/
-#define ADC_TR3_LT3_Pos                (0U)
-#define ADC_TR3_LT3_Msk                (0xFFFUL << ADC_TR3_LT3_Pos)            /*!< 0x00000FFF */
-#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
-#define ADC_TR3_LT3_0                  (0x001UL << ADC_TR3_LT3_Pos)            /*!< 0x00000001 */
-#define ADC_TR3_LT3_1                  (0x002UL << ADC_TR3_LT3_Pos)            /*!< 0x00000002 */
-#define ADC_TR3_LT3_2                  (0x004UL << ADC_TR3_LT3_Pos)            /*!< 0x00000004 */
-#define ADC_TR3_LT3_3                  (0x008UL << ADC_TR3_LT3_Pos)            /*!< 0x00000008 */
-#define ADC_TR3_LT3_4                  (0x010UL << ADC_TR3_LT3_Pos)            /*!< 0x00000010 */
-#define ADC_TR3_LT3_5                  (0x020UL << ADC_TR3_LT3_Pos)            /*!< 0x00000020 */
-#define ADC_TR3_LT3_6                  (0x040UL << ADC_TR3_LT3_Pos)            /*!< 0x00000040 */
-#define ADC_TR3_LT3_7                  (0x080UL << ADC_TR3_LT3_Pos)            /*!< 0x00000080 */
-#define ADC_TR3_LT3_8                  (0x100UL << ADC_TR3_LT3_Pos)            /*!< 0x00000100 */
-#define ADC_TR3_LT3_9                  (0x200UL << ADC_TR3_LT3_Pos)            /*!< 0x00000200 */
-#define ADC_TR3_LT3_10                 (0x400UL << ADC_TR3_LT3_Pos)            /*!< 0x00000400 */
-#define ADC_TR3_LT3_11                 (0x800UL << ADC_TR3_LT3_Pos)            /*!< 0x00000800 */
-
-#define ADC_TR3_HT3_Pos                (16U)
-#define ADC_TR3_HT3_Msk                (0xFFFUL << ADC_TR3_HT3_Pos)            /*!< 0x0FFF0000 */
-#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
-#define ADC_TR3_HT3_0                  (0x001UL << ADC_TR3_HT3_Pos)            /*!< 0x00010000 */
-#define ADC_TR3_HT3_1                  (0x002UL << ADC_TR3_HT3_Pos)            /*!< 0x00020000 */
-#define ADC_TR3_HT3_2                  (0x004UL << ADC_TR3_HT3_Pos)            /*!< 0x00040000 */
-#define ADC_TR3_HT3_3                  (0x008UL << ADC_TR3_HT3_Pos)            /*!< 0x00080000 */
-#define ADC_TR3_HT3_4                  (0x010UL << ADC_TR3_HT3_Pos)            /*!< 0x00100000 */
-#define ADC_TR3_HT3_5                  (0x020UL << ADC_TR3_HT3_Pos)            /*!< 0x00200000 */
-#define ADC_TR3_HT3_6                  (0x040UL << ADC_TR3_HT3_Pos)            /*!< 0x00400000 */
-#define ADC_TR3_HT3_7                  (0x080UL << ADC_TR3_HT3_Pos)            /*!< 0x00800000 */
-#define ADC_TR3_HT3_8                  (0x100UL << ADC_TR3_HT3_Pos)            /*!< 0x01000000 */
-#define ADC_TR3_HT3_9                  (0x200UL << ADC_TR3_HT3_Pos)            /*!< 0x02000000 */
-#define ADC_TR3_HT3_10                 (0x400UL << ADC_TR3_HT3_Pos)            /*!< 0x04000000 */
-#define ADC_TR3_HT3_11                 (0x800UL << ADC_TR3_HT3_Pos)            /*!< 0x08000000 */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                (0U)
-#define ADC_DR_DATA_Msk                (0xFFFFUL << ADC_DR_DATA_Pos)           /*!< 0x0000FFFF */
-#define ADC_DR_DATA                    ADC_DR_DATA_Msk                         /*!< ADC group regular conversion data */
-#define ADC_DR_DATA_0                  (0x0001UL << ADC_DR_DATA_Pos)           /*!< 0x00000001 */
-#define ADC_DR_DATA_1                  (0x0002UL << ADC_DR_DATA_Pos)           /*!< 0x00000002 */
-#define ADC_DR_DATA_2                  (0x0004UL << ADC_DR_DATA_Pos)           /*!< 0x00000004 */
-#define ADC_DR_DATA_3                  (0x0008UL << ADC_DR_DATA_Pos)           /*!< 0x00000008 */
-#define ADC_DR_DATA_4                  (0x0010UL << ADC_DR_DATA_Pos)           /*!< 0x00000010 */
-#define ADC_DR_DATA_5                  (0x0020UL << ADC_DR_DATA_Pos)           /*!< 0x00000020 */
-#define ADC_DR_DATA_6                  (0x0040UL << ADC_DR_DATA_Pos)           /*!< 0x00000040 */
-#define ADC_DR_DATA_7                  (0x0080UL << ADC_DR_DATA_Pos)           /*!< 0x00000080 */
-#define ADC_DR_DATA_8                  (0x0100UL << ADC_DR_DATA_Pos)           /*!< 0x00000100 */
-#define ADC_DR_DATA_9                  (0x0200UL << ADC_DR_DATA_Pos)           /*!< 0x00000200 */
-#define ADC_DR_DATA_10                 (0x0400UL << ADC_DR_DATA_Pos)           /*!< 0x00000400 */
-#define ADC_DR_DATA_11                 (0x0800UL << ADC_DR_DATA_Pos)           /*!< 0x00000800 */
-#define ADC_DR_DATA_12                 (0x1000UL << ADC_DR_DATA_Pos)           /*!< 0x00001000 */
-#define ADC_DR_DATA_13                 (0x2000UL << ADC_DR_DATA_Pos)           /*!< 0x00002000 */
-#define ADC_DR_DATA_14                 (0x4000UL << ADC_DR_DATA_Pos)           /*!< 0x00004000 */
-#define ADC_DR_DATA_15                 (0x8000UL << ADC_DR_DATA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for ADC_AWD2CR register  ****************/
-#define ADC_AWD2CR_AWD2CH_Pos          (0U)
-#define ADC_AWD2CR_AWD2CH_Msk          (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0003FFFF */
-#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
-#define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
-#define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
-#define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
-#define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
-#define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
-#define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
-#define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
-#define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
-#define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
-#define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
-#define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
-#define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
-#define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
-#define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
-#define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
-#define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
-#define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
-#define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
-
-/********************  Bit definition for ADC_AWD3CR register  ****************/
-#define ADC_AWD3CR_AWD3CH_Pos          (0U)
-#define ADC_AWD3CR_AWD3CH_Msk          (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0003FFFF */
-#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
-#define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
-#define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
-#define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
-#define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
-#define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
-#define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
-#define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
-#define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
-#define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
-#define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
-#define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
-#define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
-#define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
-#define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
-#define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
-#define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
-#define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
-#define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
-
-/********************  Bit definition for ADC_CALFACT register  ***************/
-#define ADC_CALFACT_CALFACT_Pos        (0U)
-#define ADC_CALFACT_CALFACT_Msk        (0x7FUL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT            ADC_CALFACT_CALFACT_Msk                 /*!< ADC calibration factor in single-ended mode */
-#define ADC_CALFACT_CALFACT_0          (0x01UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000001 */
-#define ADC_CALFACT_CALFACT_1          (0x02UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000002 */
-#define ADC_CALFACT_CALFACT_2          (0x04UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000004 */
-#define ADC_CALFACT_CALFACT_3          (0x08UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000008 */
-#define ADC_CALFACT_CALFACT_4          (0x10UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000010 */
-#define ADC_CALFACT_CALFACT_5          (0x20UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000020 */
-#define ADC_CALFACT_CALFACT_6          (0x40UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000040 */
-
-/*************************  ADC Common registers  *****************************/
-/********************  Bit definition for ADC_CCR register  *******************/
-#define ADC_CCR_PRESC_Pos              (18U)
-#define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
-#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
-#define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
-
-#define ADC_CCR_VREFEN_Pos             (22U)
-#define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
-#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
-#define ADC_CCR_TSEN_Pos               (23U)
-#define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
-#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
-#define ADC_CCR_VBATEN_Pos             (24U)
-#define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
-#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/**********************  Bit definition for COMP_CSR register  ****************/
-#define COMP_CSR_EN_Pos            (0U)
-#define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
-#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
-
-#define COMP_CSR_PWRMODE_Pos       (2U)
-#define COMP_CSR_PWRMODE_Msk       (0x3UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x0000000C */
-#define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
-#define COMP_CSR_PWRMODE_0         (0x1UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000004 */
-#define COMP_CSR_PWRMODE_1         (0x2UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000008 */
-
-#define COMP_CSR_INMSEL_Pos        (4U)
-#define COMP_CSR_INMSEL_Msk        (0x7UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */
-#define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
-#define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
-#define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
-#define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
-
-#define COMP_CSR_INPSEL_Pos        (7U)
-#define COMP_CSR_INPSEL_Msk        (0x3UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000180 */
-#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
-#define COMP_CSR_INPSEL_0          (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000080 */
-#define COMP_CSR_INPSEL_1          (0x2UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
-
-#define COMP_CSR_WINMODE_Pos       (9U)
-#define COMP_CSR_WINMODE_Msk       (0x1UL << COMP_CSR_WINMODE_Pos)             /*!< 0x00000200 */
-#define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_POLARITY_Pos      (15U)
-#define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
-#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
-
-#define COMP_CSR_HYST_Pos          (16U)
-#define COMP_CSR_HYST_Msk          (0x3UL << COMP_CSR_HYST_Pos)                /*!< 0x00030000 */
-#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
-#define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
-#define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
-
-#define COMP_CSR_BLANKING_Pos      (18U)
-#define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x001C0000 */
-#define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
-#define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00040000 */
-#define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */
-#define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */
-
-#define COMP_CSR_BRGEN_Pos         (22U)
-#define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */
-#define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
-#define COMP_CSR_SCALEN_Pos        (23U)
-#define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */
-#define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
-
-#define COMP_CSR_INMESEL_Pos       (25U)
-#define COMP_CSR_INMESEL_Msk       (0x3UL << COMP_CSR_INMESEL_Pos)             /*!< 0x06000000 */
-#define COMP_CSR_INMESEL           COMP_CSR_INMESEL_Msk                        /*!< Comparator input minus extended selection */
-#define COMP_CSR_INMESEL_0         (0x1UL << COMP_CSR_INMESEL_Pos)             /*!< 0x02000000 */
-#define COMP_CSR_INMESEL_1         (0x2UL << COMP_CSR_INMESEL_Pos)             /*!< 0x04000000 */
-
-#define COMP_CSR_VALUE_Pos         (30U)
-#define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
-#define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
-
-#define COMP_CSR_LOCK_Pos          (31U)
-#define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
-#define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)
-#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
-#define DAC_CR_TEN1_Pos             (1U)
-#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (2U)
-#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000004 */
-#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */
-#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */
-#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)
-#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)
-#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)
-#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)
-#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
-#define DAC_CR_CEN1_Pos             (14U)
-#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
-#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos    (0U)
-#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos    (4U)
-#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos     (0U)
-#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos       (0U)
-#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)
-#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_CAL_FLAG1_Pos        (14U)
-#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
-#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
-#define DAC_SR_BWST1_Pos            (15U)
-#define DAC_SR_BWST1_Msk            (0x1UL << DAC_SR_BWST1_Pos)                /*!< 0x00008000 */
-#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
-
-/*******************  Bit definition for DAC_CCR register  ********************/
-#define DAC_CCR_OTRIM1_Pos          (0U)
-#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
-#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
-
-/*******************  Bit definition for DAC_MCR register  *******************/
-#define DAC_MCR_MODE1_Pos           (0U)
-#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
-#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
-#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */
-#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */
-#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */
-
-/******************  Bit definition for DAC_SHSR1 register  ******************/
-#define DAC_SHSR1_TSAMPLE1_Pos      (0U)
-#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
-#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
-
-/******************  Bit definition for DAC_SHHR register  ******************/
-#define DAC_SHHR_THOLD1_Pos         (0U)
-#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
-#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
-
-/******************  Bit definition for DAC_SHRR register  ******************/
-#define DAC_SHRR_TREFRESH1_Pos      (0U)
-#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
-#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-#define LPTIM_ISR_UE_Pos            (7U)
-#define LPTIM_ISR_UE_Msk            (0x1UL << LPTIM_ISR_UE_Pos)                /*!< 0x00000080 */
-#define LPTIM_ISR_UE                LPTIM_ISR_UE_Msk                           /*!< Update event occurrence */
-#define LPTIM_ISR_REPOK_Pos         (8U)
-#define LPTIM_ISR_REPOK_Msk         (0x1UL << LPTIM_ISR_REPOK_Pos)              /*!< 0x00000100 */
-#define LPTIM_ISR_REPOK             LPTIM_ISR_REPOK_Msk                         /*!< Repetition register update OK */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-#define LPTIM_ICR_UECF_Pos          (7U)
-#define LPTIM_ICR_UECF_Msk          (0x1UL << LPTIM_ICR_UECF_Pos)              /*!< 0x00000080 */
-#define LPTIM_ICR_UECF              LPTIM_ICR_UECF_Msk                         /*!< Update event Clear Flag */
-#define LPTIM_ICR_REPOKCF_Pos       (8U)
-#define LPTIM_ICR_REPOKCF_Msk       (0x1UL << LPTIM_ICR_REPOKCF_Pos)           /*!< 0x00000100 */
-#define LPTIM_ICR_REPOKCF           LPTIM_ICR_REPOKCF_Msk                      /*!< Repetition register update OK Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-#define LPTIM_IER_UEIE_Pos          (7U)
-#define LPTIM_IER_UEIE_Msk          (0x1UL << LPTIM_IER_UEIE_Pos)              /*!< 0x00000080 */
-#define LPTIM_IER_UEIE              LPTIM_IER_UEIE_Msk                         /*!< Update event Interrupt Enable */
-#define LPTIM_IER_REPOKIE_Pos       (8U)
-#define LPTIM_IER_REPOKIE_Msk       (0x1UL << LPTIM_IER_REPOKIE_Pos)           /*!< 0x00000100 */
-#define LPTIM_IER_REPOKIE           LPTIM_IER_REPOKIE_Msk                      /*!< Repetition register update OK Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-#define LPTIM_CR_COUNTRST_Pos       (3U)
-#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
-#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
-#define LPTIM_CR_RSTARE_Pos         (4U)
-#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
-#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************  Bit definition for LPTIM_OR register  ********************/
-#define LPTIM_OR_OR_Pos             (0U)
-#define LPTIM_OR_OR_Msk             (0x3UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000003 */
-#define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
-#define LPTIM_OR_OR_0               (0x1UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000001 */
-#define LPTIM_OR_OR_1               (0x2UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000002 */
-
-/******************  Bit definition for LPTIM_RCR register  *******************/
-#define LPTIM_RCR_REP_Pos           (0U)
-#define LPTIM_RCR_REP_Msk           (0xFFUL << LPTIM_RCR_REP_Pos)              /*!< 0x000000FF */
-#define LPTIM_RCR_REP               LPTIM_RCR_REP_Msk                          /*!<Repetition Counter Value */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos             (0U)
-#define USART_CR1_UE_Msk             (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                 USART_CR1_UE_Msk                          /*!< USART Enable */
-#define USART_CR1_UESM_Pos           (1U)
-#define USART_CR1_UESM_Msk           (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM               USART_CR1_UESM_Msk                        /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos             (2U)
-#define USART_CR1_RE_Msk             (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                 USART_CR1_RE_Msk                          /*!< Receiver Enable */
-#define USART_CR1_TE_Pos             (3U)
-#define USART_CR1_TE_Msk             (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                 USART_CR1_TE_Msk                          /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos         (4U)
-#define USART_CR1_IDLEIE_Msk         (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE             USART_CR1_IDLEIE_Msk                      /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_RXFNEIE_Pos   (5U)
-#define USART_CR1_RXNEIE_RXFNEIE_Msk   (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
-#define USART_CR1_RXNEIE_RXFNEIE       USART_CR1_RXNEIE_RXFNEIE_Msk            /*!< RXNE/RXFIFO not empty Interrupt Enable */
-#define USART_CR1_TCIE_Pos           (6U)
-#define USART_CR1_TCIE_Msk           (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE               USART_CR1_TCIE_Msk                        /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_TXFNFIE_Pos  (7U)
-#define USART_CR1_TXEIE_TXFNFIE_Msk   (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)   /*!< 0x00000080 */
-#define USART_CR1_TXEIE_TXFNFIE       USART_CR1_TXEIE_TXFNFIE_Msk              /*!< TXE/TXFIFO not full Interrupt Enable */
-#define USART_CR1_PEIE_Pos           (8U)
-#define USART_CR1_PEIE_Msk           (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE               USART_CR1_PEIE_Msk                        /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos             (9U)
-#define USART_CR1_PS_Msk             (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                 USART_CR1_PS_Msk                          /*!< Parity Selection */
-#define USART_CR1_PCE_Pos            (10U)
-#define USART_CR1_PCE_Msk            (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                USART_CR1_PCE_Msk                         /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos           (11U)
-#define USART_CR1_WAKE_Msk           (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE               USART_CR1_WAKE_Msk                        /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos              (12U)
-#define USART_CR1_M_Msk              (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                  USART_CR1_M_Msk                           /*!< Word length */
-#define USART_CR1_M0_Pos             (12U)
-#define USART_CR1_M0_Msk             (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                 USART_CR1_M0_Msk                          /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos            (13U)
-#define USART_CR1_MME_Msk            (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                USART_CR1_MME_Msk                         /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos           (14U)
-#define USART_CR1_CMIE_Msk           (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE               USART_CR1_CMIE_Msk                        /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos          (15U)
-#define USART_CR1_OVER8_Msk          (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8              USART_CR1_OVER8_Msk                       /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos           (16U)
-#define USART_CR1_DEDT_Msk           (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT               USART_CR1_DEDT_Msk                        /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0             (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1             (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2             (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3             (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4             (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos           (21U)
-#define USART_CR1_DEAT_Msk           (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT               USART_CR1_DEAT_Msk                        /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0             (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1             (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2             (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3             (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4             (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos          (26U)
-#define USART_CR1_RTOIE_Msk          (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE              USART_CR1_RTOIE_Msk                       /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos          (27U)
-#define USART_CR1_EOBIE_Msk          (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE              USART_CR1_EOBIE_Msk                       /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos             (28U)
-#define USART_CR1_M1_Msk             (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                 USART_CR1_M1_Msk                          /*!< Word length - Bit 1 */
-#define USART_CR1_FIFOEN_Pos         (29U)
-#define USART_CR1_FIFOEN_Msk         (0x1UL << USART_CR1_FIFOEN_Pos)           /*!< 0x20000000 */
-#define USART_CR1_FIFOEN             USART_CR1_FIFOEN_Msk                      /*!< FIFO mode enable */
-#define USART_CR1_TXFEIE_Pos         (30U)
-#define USART_CR1_TXFEIE_Msk         (0x1UL << USART_CR1_TXFEIE_Pos)           /*!< 0x40000000 */
-#define USART_CR1_TXFEIE             USART_CR1_TXFEIE_Msk                      /*!< TXFIFO empty interrupt enable */
-#define USART_CR1_RXFFIE_Pos         (31U)
-#define USART_CR1_RXFFIE_Msk         (0x1UL << USART_CR1_RXFFIE_Pos)           /*!< 0x80000000 */
-#define USART_CR1_RXFFIE             USART_CR1_RXFFIE_Msk                      /*!< RXFIFO Full interrupt enable */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_SLVEN_Pos          (0U)
-#define USART_CR2_SLVEN_Msk          (0x1UL << USART_CR2_SLVEN_Pos)            /*!< 0x00000001 */
-#define USART_CR2_SLVEN              USART_CR2_SLVEN_Msk                       /*!< Synchronous Slave mode enable */
-#define USART_CR2_DIS_NSS_Pos        (3U)
-#define USART_CR2_DIS_NSS_Msk        (0x1UL << USART_CR2_DIS_NSS_Pos)          /*!< 0x00000008 */
-#define USART_CR2_DIS_NSS            USART_CR2_DIS_NSS_Msk                     /*!< NSS input pin disable for SPI slave selection */
-#define USART_CR2_ADDM7_Pos          (4U)
-#define USART_CR2_ADDM7_Msk          (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7              USART_CR2_ADDM7_Msk                       /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos           (5U)
-#define USART_CR2_LBDL_Msk           (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL               USART_CR2_LBDL_Msk                        /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos          (6U)
-#define USART_CR2_LBDIE_Msk          (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE              USART_CR2_LBDIE_Msk                       /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos           (8U)
-#define USART_CR2_LBCL_Msk           (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL               USART_CR2_LBCL_Msk                        /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos           (9U)
-#define USART_CR2_CPHA_Msk           (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA               USART_CR2_CPHA_Msk                        /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos           (10U)
-#define USART_CR2_CPOL_Msk           (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL               USART_CR2_CPOL_Msk                        /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos          (11U)
-#define USART_CR2_CLKEN_Msk          (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN              USART_CR2_CLKEN_Msk                       /*!< Clock Enable */
-#define USART_CR2_STOP_Pos           (12U)
-#define USART_CR2_STOP_Msk           (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP               USART_CR2_STOP_Msk                        /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0             (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1             (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos          (14U)
-#define USART_CR2_LINEN_Msk          (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN              USART_CR2_LINEN_Msk                       /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos           (15U)
-#define USART_CR2_SWAP_Msk           (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP               USART_CR2_SWAP_Msk                        /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos          (16U)
-#define USART_CR2_RXINV_Msk          (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV              USART_CR2_RXINV_Msk                       /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos          (17U)
-#define USART_CR2_TXINV_Msk          (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV              USART_CR2_TXINV_Msk                       /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos        (18U)
-#define USART_CR2_DATAINV_Msk        (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV            USART_CR2_DATAINV_Msk                     /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos       (19U)
-#define USART_CR2_MSBFIRST_Msk       (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST           USART_CR2_MSBFIRST_Msk                    /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos          (20U)
-#define USART_CR2_ABREN_Msk          (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN              USART_CR2_ABREN_Msk                       /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos        (21U)
-#define USART_CR2_ABRMODE_Msk        (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE            USART_CR2_ABRMODE_Msk                     /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0          (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1          (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos          (23U)
-#define USART_CR2_RTOEN_Msk          (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN              USART_CR2_RTOEN_Msk                       /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos            (24U)
-#define USART_CR2_ADD_Msk            (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                USART_CR2_ADD_Msk                         /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos            (0U)
-#define USART_CR3_EIE_Msk            (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                USART_CR3_EIE_Msk                         /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos           (1U)
-#define USART_CR3_IREN_Msk           (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN               USART_CR3_IREN_Msk                        /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos           (2U)
-#define USART_CR3_IRLP_Msk           (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP               USART_CR3_IRLP_Msk                        /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos          (3U)
-#define USART_CR3_HDSEL_Msk          (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL              USART_CR3_HDSEL_Msk                       /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos           (4U)
-#define USART_CR3_NACK_Msk           (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK               USART_CR3_NACK_Msk                        /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos           (5U)
-#define USART_CR3_SCEN_Msk           (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN               USART_CR3_SCEN_Msk                        /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos           (6U)
-#define USART_CR3_DMAR_Msk           (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR               USART_CR3_DMAR_Msk                        /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos           (7U)
-#define USART_CR3_DMAT_Msk           (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT               USART_CR3_DMAT_Msk                        /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos           (8U)
-#define USART_CR3_RTSE_Msk           (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE               USART_CR3_RTSE_Msk                        /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos           (9U)
-#define USART_CR3_CTSE_Msk           (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE               USART_CR3_CTSE_Msk                        /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos          (10U)
-#define USART_CR3_CTSIE_Msk          (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE              USART_CR3_CTSIE_Msk                       /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos         (11U)
-#define USART_CR3_ONEBIT_Msk         (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT             USART_CR3_ONEBIT_Msk                      /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos         (12U)
-#define USART_CR3_OVRDIS_Msk         (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS             USART_CR3_OVRDIS_Msk                      /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos           (13U)
-#define USART_CR3_DDRE_Msk           (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE               USART_CR3_DDRE_Msk                        /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos            (14U)
-#define USART_CR3_DEM_Msk            (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                USART_CR3_DEM_Msk                         /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos            (15U)
-#define USART_CR3_DEP_Msk            (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                USART_CR3_DEP_Msk                         /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos        (17U)
-#define USART_CR3_SCARCNT_Msk        (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT            USART_CR3_SCARCNT_Msk                     /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0          (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1          (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2          (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos            (20U)
-#define USART_CR3_WUS_Msk            (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                USART_CR3_WUS_Msk                         /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0              (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1              (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos          (22U)
-#define USART_CR3_WUFIE_Msk          (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE              USART_CR3_WUFIE_Msk                       /*!< Wake Up Interrupt Enable */
-#define USART_CR3_TXFTIE_Pos         (23U)
-#define USART_CR3_TXFTIE_Msk         (0x1UL << USART_CR3_TXFTIE_Pos)           /*!< 0x00800000 */
-#define USART_CR3_TXFTIE             USART_CR3_TXFTIE_Msk                      /*!< TXFIFO threshold interrupt enable */
-#define USART_CR3_TCBGTIE_Pos        (24U)
-#define USART_CR3_TCBGTIE_Msk        (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
-#define USART_CR3_TCBGTIE            USART_CR3_TCBGTIE_Msk                     /*!< Transmission Complete Before Guard Time Interrupt Enable */
-#define USART_CR3_RXFTCFG_Pos        (25U)
-#define USART_CR3_RXFTCFG_Msk        (0x7UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x0E000000 */
-#define USART_CR3_RXFTCFG            USART_CR3_RXFTCFG_Msk                     /*!< RXFIFO FIFO threshold configuration */
-#define USART_CR3_RXFTCFG_0          (0x1UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x02000000 */
-#define USART_CR3_RXFTCFG_1          (0x2UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x04000000 */
-#define USART_CR3_RXFTCFG_2          (0x4UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x08000000 */
-#define USART_CR3_RXFTIE_Pos         (28U)
-#define USART_CR3_RXFTIE_Msk         (0x1UL << USART_CR3_RXFTIE_Pos)           /*!< 0x10000000 */
-#define USART_CR3_RXFTIE             USART_CR3_RXFTIE_Msk                      /*!< RXFIFO threshold interrupt enable */
-#define USART_CR3_TXFTCFG_Pos        (29U)
-#define USART_CR3_TXFTCFG_Msk        (0x7UL << USART_CR3_TXFTCFG_Pos)          /*!< 0xE0000000 */
-#define USART_CR3_TXFTCFG            USART_CR3_TXFTCFG_Msk                     /*!< TXFIFO threshold configuration */
-#define USART_CR3_TXFTCFG_0          (0x1UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x20000000 */
-#define USART_CR3_TXFTCFG_1          (0x2UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x40000000 */
-#define USART_CR3_TXFTCFG_2          (0x4UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x80000000 */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_BRR                ((uint16_t)0xFFFF)                        /*!< USART  Baud rate register [15:0] */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos           (0U)
-#define USART_GTPR_PSC_Msk           (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC               USART_GTPR_PSC_Msk                        /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos            (8U)
-#define USART_GTPR_GT_Msk            (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                USART_GTPR_GT_Msk                         /*!< GT[7:0] bits (Guard time value) */
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos           (0U)
-#define USART_RTOR_RTO_Msk           (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO               USART_RTOR_RTO_Msk                        /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos          (24U)
-#define USART_RTOR_BLEN_Msk          (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN              USART_RTOR_BLEN_Msk                       /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ        ((uint16_t)0x0001)                              /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ        ((uint16_t)0x0002)                              /*!< Send Break Request */
-#define USART_RQR_MMRQ         ((uint16_t)0x0004)                              /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ        ((uint16_t)0x0008)                              /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ        ((uint16_t)0x0010)                              /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos             (0U)
-#define USART_ISR_PE_Msk             (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                 USART_ISR_PE_Msk                          /*!< Parity Error */
-#define USART_ISR_FE_Pos             (1U)
-#define USART_ISR_FE_Msk             (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                 USART_ISR_FE_Msk                          /*!< Framing Error */
-#define USART_ISR_NE_Pos             (2U)
-#define USART_ISR_NE_Msk             (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                 USART_ISR_NE_Msk                          /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos            (3U)
-#define USART_ISR_ORE_Msk            (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                USART_ISR_ORE_Msk                         /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos           (4U)
-#define USART_ISR_IDLE_Msk           (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE               USART_ISR_IDLE_Msk                        /*!< IDLE line detected */
-#define USART_ISR_RXNE_RXFNE_Pos     (5U)
-#define USART_ISR_RXNE_RXFNE_Msk     (0x1UL << USART_ISR_RXNE_RXFNE_Pos)      /*!< 0x00000020 */
-#define USART_ISR_RXNE_RXFNE         USART_ISR_RXNE_RXFNE_Msk                /*!< Read Data Register Not Empty/RXFIFO Not Empty */
-#define USART_ISR_TC_Pos             (6U)
-#define USART_ISR_TC_Msk             (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                 USART_ISR_TC_Msk                          /*!< Transmission Complete */
-#define USART_ISR_TXE_TXFNF_Pos      (7U)
-#define USART_ISR_TXE_TXFNF_Msk      (0x1UL << USART_ISR_TXE_TXFNF_Pos)       /*!< 0x00000080 */
-#define USART_ISR_TXE_TXFNF          USART_ISR_TXE_TXFNF_Msk                  /*!< Transmit Data Register Empty/TXFIFO Not Full */
-#define USART_ISR_LBDF_Pos           (8U)
-#define USART_ISR_LBDF_Msk           (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF               USART_ISR_LBDF_Msk                        /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos          (9U)
-#define USART_ISR_CTSIF_Msk          (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF              USART_ISR_CTSIF_Msk                       /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos            (10U)
-#define USART_ISR_CTS_Msk            (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                USART_ISR_CTS_Msk                         /*!< CTS flag */
-#define USART_ISR_RTOF_Pos           (11U)
-#define USART_ISR_RTOF_Msk           (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF               USART_ISR_RTOF_Msk                        /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos           (12U)
-#define USART_ISR_EOBF_Msk           (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF               USART_ISR_EOBF_Msk                        /*!< End Of Block Flag */
-#define USART_ISR_UDR_Pos            (13U)
-#define USART_ISR_UDR_Msk            (0x1UL << USART_ISR_UDR_Pos)              /*!< 0x00002000 */
-#define USART_ISR_UDR                 USART_ISR_UDR_Msk                        /*!< SPI Slave Underrun Error Flag */
-#define USART_ISR_ABRE_Pos           (14U)
-#define USART_ISR_ABRE_Msk           (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE               USART_ISR_ABRE_Msk                        /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos           (15U)
-#define USART_ISR_ABRF_Msk           (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF               USART_ISR_ABRF_Msk                        /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos           (16U)
-#define USART_ISR_BUSY_Msk           (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY               USART_ISR_BUSY_Msk                        /*!< Busy Flag */
-#define USART_ISR_CMF_Pos            (17U)
-#define USART_ISR_CMF_Msk            (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                USART_ISR_CMF_Msk                         /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos           (18U)
-#define USART_ISR_SBKF_Msk           (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF               USART_ISR_SBKF_Msk                        /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos            (19U)
-#define USART_ISR_RWU_Msk            (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                USART_ISR_RWU_Msk                         /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos            (20U)
-#define USART_ISR_WUF_Msk            (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                USART_ISR_WUF_Msk                         /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos          (21U)
-#define USART_ISR_TEACK_Msk          (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK              USART_ISR_TEACK_Msk                       /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos          (22U)
-#define USART_ISR_REACK_Msk          (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK              USART_ISR_REACK_Msk                       /*!< Receive Enable Acknowledge Flag */
-#define USART_ISR_TXFE_Pos           (23U)
-#define USART_ISR_TXFE_Msk           (0x1UL << USART_ISR_TXFE_Pos)             /*!< 0x00800000 */
-#define USART_ISR_TXFE               USART_ISR_TXFE_Msk                        /*!< TXFIFO Empty Flag */
-#define USART_ISR_RXFF_Pos           (24U)
-#define USART_ISR_RXFF_Msk           (0x1UL << USART_ISR_RXFF_Pos)             /*!< 0x01000000 */
-#define USART_ISR_RXFF               USART_ISR_RXFF_Msk                        /*!< RXFIFO Full Flag */
-#define USART_ISR_TCBGT_Pos          (25U)
-#define USART_ISR_TCBGT_Msk          (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
-#define USART_ISR_TCBGT              USART_ISR_TCBGT_Msk                       /*!< Transmission Complete Before Guard Time Completion Flag */
-#define USART_ISR_RXFT_Pos           (26U)
-#define USART_ISR_RXFT_Msk           (0x1UL << USART_ISR_RXFT_Pos)             /*!< 0x04000000 */
-#define USART_ISR_RXFT               USART_ISR_RXFT_Msk                        /*!< RXFIFO Threshold Flag */
-#define USART_ISR_TXFT_Pos           (27U)
-#define USART_ISR_TXFT_Msk           (0x1UL << USART_ISR_TXFT_Pos)             /*!< 0x08000000 */
-#define USART_ISR_TXFT               USART_ISR_TXFT_Msk                        /*!< TXFIFO Threshold Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos           (0U)
-#define USART_ICR_PECF_Msk           (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF               USART_ICR_PECF_Msk                        /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos           (1U)
-#define USART_ICR_FECF_Msk           (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF               USART_ICR_FECF_Msk                        /*!< Framing Error Clear Flag */
-#define USART_ICR_NECF_Pos           (2U)
-#define USART_ICR_NECF_Msk           (0x1UL << USART_ICR_NECF_Pos)             /*!< 0x00000004 */
-#define USART_ICR_NECF               USART_ICR_NECF_Msk                        /*!< Noise Error detected Clear Flag */
-#define USART_ICR_ORECF_Pos          (3U)
-#define USART_ICR_ORECF_Msk          (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF              USART_ICR_ORECF_Msk                       /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos         (4U)
-#define USART_ICR_IDLECF_Msk         (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF             USART_ICR_IDLECF_Msk                      /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TXFECF_Pos         (5U)
-#define USART_ICR_TXFECF_Msk         (0x1UL << USART_ICR_TXFECF_Pos)           /*!< 0x00000020 */
-#define USART_ICR_TXFECF             USART_ICR_TXFECF_Msk                      /*!< TXFIFO Empty Clear Flag */
-#define USART_ICR_TCCF_Pos           (6U)
-#define USART_ICR_TCCF_Msk           (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF               USART_ICR_TCCF_Msk                        /*!< Transmission Complete Clear Flag */
-#define USART_ICR_TCBGTCF_Pos        (7U)
-#define USART_ICR_TCBGTCF_Msk        (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
-#define USART_ICR_TCBGTCF            USART_ICR_TCBGTCF_Msk                     /*!< Transmission Complete Before Guard Time Clear Flag */
-#define USART_ICR_LBDCF_Pos          (8U)
-#define USART_ICR_LBDCF_Msk          (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF              USART_ICR_LBDCF_Msk                       /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos          (9U)
-#define USART_ICR_CTSCF_Msk          (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF              USART_ICR_CTSCF_Msk                       /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos          (11U)
-#define USART_ICR_RTOCF_Msk          (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF              USART_ICR_RTOCF_Msk                       /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos          (12U)
-#define USART_ICR_EOBCF_Msk          (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF              USART_ICR_EOBCF_Msk                       /*!< End Of Block Clear Flag */
-#define USART_ICR_UDRCF_Pos          (13U)
-#define USART_ICR_UDRCF_Msk          (0x1UL << USART_ICR_UDRCF_Pos)            /*!< 0x00002000 */
-#define USART_ICR_UDRCF              USART_ICR_UDRCF_Msk                       /*!< SPI Slave Underrun Clear Flag */
-#define USART_ICR_CMCF_Pos           (17U)
-#define USART_ICR_CMCF_Msk           (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF               USART_ICR_CMCF_Msk                        /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos           (20U)
-#define USART_ICR_WUCF_Msk           (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF               USART_ICR_WUCF_Msk                        /*!< Wake Up from stop mode Clear Flag */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)           /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)           /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/*******************  Bit definition for USART_PRESC register  ****************/
-#define USART_PRESC_PRESCALER_Pos    (0U)
-#define USART_PRESC_PRESCALER_Msk    (0xFUL << USART_PRESC_PRESCALER_Pos)      /*!< 0x0000000F */
-#define USART_PRESC_PRESCALER        USART_PRESC_PRESCALER_Msk                 /*!< PRESCALER[3:0] bits (Clock prescaler) */
-#define USART_PRESC_PRESCALER_0      (0x1UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000001 */
-#define USART_PRESC_PRESCALER_1      (0x2UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000002 */
-#define USART_PRESC_PRESCALER_2      (0x4UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000004 */
-#define USART_PRESC_PRESCALER_3      (0x8UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000008 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos          (0U)
-#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)                   /*!< 0x000000FF */
-#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bits data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos            (0U)
-#define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                      /*!< 0x00000001 */
-#define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos      (1U)
-#define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000006 */
-#define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
-#define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos          (3U)
-#define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                    /*!< 0x00000018 */
-#define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                    /*!< 0x00000008 */
-#define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                    /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos         (5U)
-#define AES_CR_CHMOD_Msk         (0x803UL << AES_CR_CHMOD_Pos)                 /*!< 0x00010060 */
-#define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0           (0x001UL << AES_CR_CHMOD_Pos)                 /*!< 0x00000020 */
-#define AES_CR_CHMOD_1           (0x002UL << AES_CR_CHMOD_Pos)                 /*!< 0x00000040 */
-#define AES_CR_CHMOD_2           (0x800UL << AES_CR_CHMOD_Pos)                 /*!< 0x00010000 */
-
-#define AES_CR_CCFC_Pos          (7U)
-#define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                    /*!< 0x00000080 */
-#define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos          (8U)
-#define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                    /*!< 0x00000100 */
-#define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
-#define AES_CR_CCFIE_Pos         (9U)
-#define AES_CR_CCFIE_Msk         (0x1UL << AES_CR_CCFIE_Pos)                   /*!< 0x00000200 */
-#define AES_CR_CCFIE             AES_CR_CCFIE_Msk                              /*!< Computation Complete Flag Interrupt Enable */
-#define AES_CR_ERRIE_Pos         (10U)
-#define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                   /*!< 0x00000400 */
-#define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos       (11U)
-#define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                 /*!< 0x00000800 */
-#define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< Enable data input phase DMA management  */
-#define AES_CR_DMAOUTEN_Pos      (12U)
-#define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< Enable data output phase DMA management */
-
-#define AES_CR_GCMPH_Pos         (13U)
-#define AES_CR_GCMPH_Msk         (0x3UL << AES_CR_GCMPH_Pos)                   /*!< 0x00006000 */
-#define AES_CR_GCMPH             AES_CR_GCMPH_Msk                              /*!< GCM Phase */
-#define AES_CR_GCMPH_0           (0x1UL << AES_CR_GCMPH_Pos)                   /*!< 0x00002000 */
-#define AES_CR_GCMPH_1           (0x2UL << AES_CR_GCMPH_Pos)                   /*!< 0x00004000 */
-
-#define AES_CR_KEYSIZE_Pos       (18U)
-#define AES_CR_KEYSIZE_Msk       (0x1UL << AES_CR_KEYSIZE_Pos)                 /*!< 0x00040000 */
-#define AES_CR_KEYSIZE           AES_CR_KEYSIZE_Msk                            /*!< Key size selection */
-
-#define AES_CR_NPBLB_Pos         (20U)
-#define AES_CR_NPBLB_Msk         (0xFUL << AES_CR_NPBLB_Pos)                   /*!< 0x00F00000 */
-#define AES_CR_NPBLB             AES_CR_NPBLB_Msk                              /*!< Number of padding bytes in last payload block */
-#define AES_CR_NPBLB_0           (0x1UL << AES_CR_NPBLB_Pos)                   /*!< 0x00100000 */
-#define AES_CR_NPBLB_1           (0x2UL << AES_CR_NPBLB_Pos)                   /*!< 0x00200000 */
-#define AES_CR_NPBLB_2           (0x4UL << AES_CR_NPBLB_Pos)                   /*!< 0x00400000 */
-#define AES_CR_NPBLB_3           (0x8UL << AES_CR_NPBLB_Pos)                   /*!< 0x00800000 */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos           (0U)
-#define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                     /*!< 0x00000001 */
-#define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos         (1U)
-#define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                   /*!< 0x00000002 */
-#define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos         (2U)
-#define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                   /*!< 0x00000004 */
-#define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
-#define AES_SR_BUSY_Pos          (3U)
-#define AES_SR_BUSY_Msk          (0x1UL << AES_SR_BUSY_Pos)                    /*!< 0x00000008 */
-#define AES_SR_BUSY              AES_SR_BUSY_Msk                               /*!< Busy Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos             (0U)
-#define AES_DINR_Msk             (0xFFFFFFFFUL << AES_DINR_Pos)                /*!< 0xFFFFFFFF */
-#define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos            (0U)
-#define AES_DOUTR_Msk            (0xFFFFFFFFUL << AES_DOUTR_Pos)               /*!< 0xFFFFFFFF */
-#define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos            (0U)
-#define AES_KEYR0_Msk            (0xFFFFFFFFUL << AES_KEYR0_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos            (0U)
-#define AES_KEYR1_Msk            (0xFFFFFFFFUL << AES_KEYR1_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos            (0U)
-#define AES_KEYR2_Msk            (0xFFFFFFFFUL << AES_KEYR2_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos            (0U)
-#define AES_KEYR3_Msk            (0xFFFFFFFFUL << AES_KEYR3_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_KEYR4 register  ******************/
-#define AES_KEYR4_Pos            (0U)
-#define AES_KEYR4_Msk            (0xFFFFFFFFUL << AES_KEYR4_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR4                AES_KEYR4_Msk                                 /*!< AES Key Register 4 */
-
-/*******************  Bit definition for AES_KEYR5 register  ******************/
-#define AES_KEYR5_Pos            (0U)
-#define AES_KEYR5_Msk            (0xFFFFFFFFUL << AES_KEYR5_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR5                AES_KEYR5_Msk                                 /*!< AES Key Register 5 */
-
-/*******************  Bit definition for AES_KEYR6 register  ******************/
-#define AES_KEYR6_Pos            (0U)
-#define AES_KEYR6_Msk            (0xFFFFFFFFUL << AES_KEYR6_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR6                AES_KEYR6_Msk                                 /*!< AES Key Register 6 */
-
-/*******************  Bit definition for AES_KEYR7 register  ******************/
-#define AES_KEYR7_Pos            (0U)
-#define AES_KEYR7_Msk            (0xFFFFFFFFUL << AES_KEYR7_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR7                AES_KEYR7_Msk                                 /*!< AES Key Register 7 */
-
-/*******************  Bit definition for AES_IVR0 register   ******************/
-#define AES_IVR0_Pos             (0U)
-#define AES_IVR0_Msk             (0xFFFFFFFFUL << AES_IVR0_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register   ******************/
-#define AES_IVR1_Pos             (0U)
-#define AES_IVR1_Msk             (0xFFFFFFFFUL << AES_IVR1_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register   ******************/
-#define AES_IVR2_Pos             (0U)
-#define AES_IVR2_Msk             (0xFFFFFFFFUL << AES_IVR2_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register   ******************/
-#define AES_IVR3_Pos             (0U)
-#define AES_IVR3_Msk             (0xFFFFFFFFUL << AES_IVR3_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
-
-/*******************  Bit definition for AES_SUSP0R register  ******************/
-#define AES_SUSP0R_Pos           (0U)
-#define AES_SUSP0R_Msk           (0xFFFFFFFFUL << AES_SUSP0R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP0R               AES_SUSP0R_Msk                                /*!< AES Suspend registers 0 */
-
-/*******************  Bit definition for AES_SUSP1R register  ******************/
-#define AES_SUSP1R_Pos           (0U)
-#define AES_SUSP1R_Msk           (0xFFFFFFFFUL << AES_SUSP1R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP1R               AES_SUSP1R_Msk                                /*!< AES Suspend registers 1 */
-
-/*******************  Bit definition for AES_SUSP2R register  ******************/
-#define AES_SUSP2R_Pos           (0U)
-#define AES_SUSP2R_Msk           (0xFFFFFFFFUL << AES_SUSP2R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP2R               AES_SUSP2R_Msk                                /*!< AES Suspend registers 2 */
-
-/*******************  Bit definition for AES_SUSP3R register  ******************/
-#define AES_SUSP3R_Pos           (0U)
-#define AES_SUSP3R_Msk           (0xFFFFFFFFUL << AES_SUSP3R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP3R               AES_SUSP3R_Msk                                /*!< AES Suspend registers 3 */
-
-/*******************  Bit definition for AES_SUSP4R register  ******************/
-#define AES_SUSP4R_Pos           (0U)
-#define AES_SUSP4R_Msk           (0xFFFFFFFFUL << AES_SUSP4R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP4R               AES_SUSP4R_Msk                                /*!< AES Suspend registers 4 */
-
-/*******************  Bit definition for AES_SUSP5R register  ******************/
-#define AES_SUSP5R_Pos           (0U)
-#define AES_SUSP5R_Msk           (0xFFFFFFFFUL << AES_SUSP5R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP5R               AES_SUSP5R_Msk                                /*!< AES Suspend registers 5 */
-
-/*******************  Bit definition for AES_SUSP6R register  ******************/
-#define AES_SUSP6R_Pos           (0U)
-#define AES_SUSP6R_Msk           (0xFFFFFFFFUL << AES_SUSP6R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP6R               AES_SUSP6R_Msk                                /*!< AES Suspend registers 6 */
-
-/*******************  Bit definition for AES_SUSP7R register  ******************/
-#define AES_SUSP7R_Pos           (0U)
-#define AES_SUSP7R_Msk           (0xFFFFFFFFUL << AES_SUSP7R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP7R               AES_SUSP7R_Msk                                /*!< AES Suspend registers 7 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos      (1U)
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos      (2U)
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos      (3U)
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos       (4U)
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos      (5U)
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos      (6U)
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos      (7U)
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos       (8U)
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos      (9U)
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos      (10U)
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos      (11U)
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos       (12U)
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos      (13U)
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos      (14U)
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos      (15U)
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos       (16U)
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos      (17U)
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos      (18U)
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos      (19U)
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos       (20U)
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos    (1U)
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos    (2U)
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos    (3U)
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos     (4U)
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos    (5U)
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos    (6U)
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos    (7U)
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos     (8U)
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos    (9U)
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos    (10U)
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos    (11U)
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos     (12U)
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos    (13U)
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos    (14U)
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos    (15U)
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos     (16U)
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos    (17U)
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos    (18U)
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos    (19U)
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos     (20U)
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-#define DMA_CCR_SECM_Pos       (17U)
-#define DMA_CCR_SECM_Msk       (0x1UL << DMA_CCR_SECM_Pos)                    /*!< 0x00020000 */
-#define DMA_CCR_SECM           DMA_CCR_SECM_Msk                               /*!< Secure mode                          */
-#define DMA_CCR_SSEC_Pos       (18U)
-#define DMA_CCR_SSEC_Msk       (0x1UL << DMA_CCR_SSEC_Pos)                    /*!< 0x00040000 */
-#define DMA_CCR_SSEC           DMA_CCR_SSEC_Msk                               /*!< Security of the DMA transfer from the source, only accessible write, read by CM0PLUS    */
-#define DMA_CCR_DSEC_Pos       (19U)
-#define DMA_CCR_DSEC_Msk       (0x1UL << DMA_CCR_DSEC_Pos)                    /*!< 0x00080000 */
-#define DMA_CCR_DSEC           DMA_CCR_DSEC_Msk                               /*!< Security of the DMA transfer to the destination, only accessible write, read by CM0PLUS */
-#define DMA_CCR_PRIV_Pos       (20U)
-#define DMA_CCR_PRIV_Msk       (0x1UL << DMA_CCR_PRIV_Pos)                    /*!< 0x00100000 */
-#define DMA_CCR_PRIV           DMA_CCR_PRIV_Msk                               /*!< Privileged mode                      */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)
-#define DMA_CNDTR_NDT_Msk      (0x3FFFFUL << DMA_CNDTR_NDT_Pos)                /*!< 0x0003FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMAMUX Controller                              */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMAMUX_CxCR register  **************/
-#define DMAMUX_CxCR_DMAREQ_ID_Pos              (0U)
-#define DMAMUX_CxCR_DMAREQ_ID_Msk              (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x0000007F */
-#define DMAMUX_CxCR_DMAREQ_ID                  DMAMUX_CxCR_DMAREQ_ID_Msk       /*!< DMA Request ID                       */
-#define DMAMUX_CxCR_DMAREQ_ID_0                (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
-#define DMAMUX_CxCR_DMAREQ_ID_1                (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
-#define DMAMUX_CxCR_DMAREQ_ID_2                (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
-#define DMAMUX_CxCR_DMAREQ_ID_3                (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
-#define DMAMUX_CxCR_DMAREQ_ID_4                (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
-#define DMAMUX_CxCR_DMAREQ_ID_5                (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
-#define DMAMUX_CxCR_DMAREQ_ID_6                (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
-#define DMAMUX_CxCR_SOIE_Pos                   (8U)
-#define DMAMUX_CxCR_SOIE_Msk                   (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
-#define DMAMUX_CxCR_SOIE                       DMAMUX_CxCR_SOIE_Msk            /*!< Synchro overrun interrupt enable     */
-#define DMAMUX_CxCR_EGE_Pos                    (9U)
-#define DMAMUX_CxCR_EGE_Msk                    (0x1UL << DMAMUX_CxCR_EGE_Pos)  /*!< 0x00000200 */
-#define DMAMUX_CxCR_EGE                        DMAMUX_CxCR_EGE_Msk             /*!< Event generation interrupt enable    */
-#define DMAMUX_CxCR_SE_Pos                     (16U)
-#define DMAMUX_CxCR_SE_Msk                     (0x1UL << DMAMUX_CxCR_SE_Pos)   /*!< 0x00010000 */
-#define DMAMUX_CxCR_SE                         DMAMUX_CxCR_SE_Msk              /*!< Synchronization enable               */
-#define DMAMUX_CxCR_SPOL_Pos                   (17U)
-#define DMAMUX_CxCR_SPOL_Msk                   (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
-#define DMAMUX_CxCR_SPOL                       DMAMUX_CxCR_SPOL_Msk            /*!< Synchronization polarity             */
-#define DMAMUX_CxCR_SPOL_0                     (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
-#define DMAMUX_CxCR_SPOL_1                     (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
-#define DMAMUX_CxCR_NBREQ_Pos                  (19U)
-#define DMAMUX_CxCR_NBREQ_Msk                  (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
-#define DMAMUX_CxCR_NBREQ                      DMAMUX_CxCR_NBREQ_Msk           /*!< Number of request                    */
-#define DMAMUX_CxCR_NBREQ_0                    (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
-#define DMAMUX_CxCR_NBREQ_1                    (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
-#define DMAMUX_CxCR_NBREQ_2                    (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
-#define DMAMUX_CxCR_NBREQ_3                    (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
-#define DMAMUX_CxCR_NBREQ_4                    (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
-#define DMAMUX_CxCR_SYNC_ID_Pos                (24U)
-#define DMAMUX_CxCR_SYNC_ID_Msk                (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
-#define DMAMUX_CxCR_SYNC_ID                    DMAMUX_CxCR_SYNC_ID_Msk         /*!< Synchronization ID                   */
-#define DMAMUX_CxCR_SYNC_ID_0                  (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
-#define DMAMUX_CxCR_SYNC_ID_1                  (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
-#define DMAMUX_CxCR_SYNC_ID_2                  (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
-#define DMAMUX_CxCR_SYNC_ID_3                  (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
-#define DMAMUX_CxCR_SYNC_ID_4                  (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
-
-/*******************  Bits definition for DMAMUX_CSR register  **************/
-#define DMAMUX_CSR_SOF0_Pos                    (0U)
-#define DMAMUX_CSR_SOF0_Msk                    (0x1UL << DMAMUX_CSR_SOF0_Pos)  /*!< 0x00000001 */
-#define DMAMUX_CSR_SOF0                        DMAMUX_CSR_SOF0_Msk             /*!< Synchronization Overrun Flag 0       */
-#define DMAMUX_CSR_SOF1_Pos                    (1U)
-#define DMAMUX_CSR_SOF1_Msk                    (0x1UL << DMAMUX_CSR_SOF1_Pos)  /*!< 0x00000002 */
-#define DMAMUX_CSR_SOF1                        DMAMUX_CSR_SOF1_Msk             /*!< Synchronization Overrun Flag 1       */
-#define DMAMUX_CSR_SOF2_Pos                    (2U)
-#define DMAMUX_CSR_SOF2_Msk                    (0x1UL << DMAMUX_CSR_SOF2_Pos)  /*!< 0x00000004 */
-#define DMAMUX_CSR_SOF2                        DMAMUX_CSR_SOF2_Msk             /*!< Synchronization Overrun Flag 2       */
-#define DMAMUX_CSR_SOF3_Pos                    (3U)
-#define DMAMUX_CSR_SOF3_Msk                    (0x1UL << DMAMUX_CSR_SOF3_Pos)  /*!< 0x00000008 */
-#define DMAMUX_CSR_SOF3                        DMAMUX_CSR_SOF3_Msk             /*!< Synchronization Overrun Flag 3       */
-#define DMAMUX_CSR_SOF4_Pos                    (4U)
-#define DMAMUX_CSR_SOF4_Msk                    (0x1UL << DMAMUX_CSR_SOF4_Pos)  /*!< 0x00000010 */
-#define DMAMUX_CSR_SOF4                        DMAMUX_CSR_SOF4_Msk             /*!< Synchronization Overrun Flag 4       */
-#define DMAMUX_CSR_SOF5_Pos                    (5U)
-#define DMAMUX_CSR_SOF5_Msk                    (0x1UL << DMAMUX_CSR_SOF5_Pos)  /*!< 0x00000020 */
-#define DMAMUX_CSR_SOF5                        DMAMUX_CSR_SOF5_Msk             /*!< Synchronization Overrun Flag 5       */
-#define DMAMUX_CSR_SOF6_Pos                    (6U)
-#define DMAMUX_CSR_SOF6_Msk                    (0x1UL << DMAMUX_CSR_SOF6_Pos)  /*!< 0x00000040 */
-#define DMAMUX_CSR_SOF6                        DMAMUX_CSR_SOF6_Msk             /*!< Synchronization Overrun Flag 6       */
-#define DMAMUX_CSR_SOF7_Pos                    (7U)
-#define DMAMUX_CSR_SOF7_Msk                    (0x1UL << DMAMUX_CSR_SOF7_Pos)  /*!< 0x00000080 */
-#define DMAMUX_CSR_SOF7                        DMAMUX_CSR_SOF7_Msk             /*!< Synchronization Overrun Flag 7       */
-#define DMAMUX_CSR_SOF8_Pos                    (8U)
-#define DMAMUX_CSR_SOF8_Msk                    (0x1UL << DMAMUX_CSR_SOF8_Pos)  /*!< 0x00000100 */
-#define DMAMUX_CSR_SOF8                        DMAMUX_CSR_SOF8_Msk             /*!< Synchronization Overrun Flag 8       */
-#define DMAMUX_CSR_SOF9_Pos                    (9U)
-#define DMAMUX_CSR_SOF9_Msk                    (0x1UL << DMAMUX_CSR_SOF9_Pos)  /*!< 0x00000200 */
-#define DMAMUX_CSR_SOF9                        DMAMUX_CSR_SOF9_Msk             /*!< Synchronization Overrun Flag 9       */
-#define DMAMUX_CSR_SOF10_Pos                   (10U)
-#define DMAMUX_CSR_SOF10_Msk                   (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
-#define DMAMUX_CSR_SOF10                       DMAMUX_CSR_SOF10_Msk            /*!< Synchronization Overrun Flag 10      */
-#define DMAMUX_CSR_SOF11_Pos                   (11U)
-#define DMAMUX_CSR_SOF11_Msk                   (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
-#define DMAMUX_CSR_SOF11                       DMAMUX_CSR_SOF11_Msk            /*!< Synchronization Overrun Flag 11      */
-#define DMAMUX_CSR_SOF12_Pos                   (12U)
-#define DMAMUX_CSR_SOF12_Msk                   (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
-#define DMAMUX_CSR_SOF12                       DMAMUX_CSR_SOF12_Msk            /*!< Synchronization Overrun Flag 12      */
-#define DMAMUX_CSR_SOF13_Pos                   (13U)
-#define DMAMUX_CSR_SOF13_Msk                   (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
-#define DMAMUX_CSR_SOF13                       DMAMUX_CSR_SOF13_Msk            /*!< Synchronization Overrun Flag 13      */
-
-/********************  Bits definition for DMAMUX_CFR register  **************/
-#define DMAMUX_CFR_CSOF0_Pos                   (0U)
-#define DMAMUX_CFR_CSOF0_Msk                   (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
-#define DMAMUX_CFR_CSOF0                       DMAMUX_CFR_CSOF0_Msk            /*!< Clear Overrun Flag 0                 */
-#define DMAMUX_CFR_CSOF1_Pos                   (1U)
-#define DMAMUX_CFR_CSOF1_Msk                   (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
-#define DMAMUX_CFR_CSOF1                       DMAMUX_CFR_CSOF1_Msk            /*!< Clear Overrun Flag 1                 */
-#define DMAMUX_CFR_CSOF2_Pos                   (2U)
-#define DMAMUX_CFR_CSOF2_Msk                   (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
-#define DMAMUX_CFR_CSOF2                       DMAMUX_CFR_CSOF2_Msk            /*!< Clear Overrun Flag 2                 */
-#define DMAMUX_CFR_CSOF3_Pos                   (3U)
-#define DMAMUX_CFR_CSOF3_Msk                   (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
-#define DMAMUX_CFR_CSOF3                       DMAMUX_CFR_CSOF3_Msk            /*!< Clear Overrun Flag 3                 */
-#define DMAMUX_CFR_CSOF4_Pos                   (4U)
-#define DMAMUX_CFR_CSOF4_Msk                   (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
-#define DMAMUX_CFR_CSOF4                       DMAMUX_CFR_CSOF4_Msk            /*!< Clear Overrun Flag 4                 */
-#define DMAMUX_CFR_CSOF5_Pos                   (5U)
-#define DMAMUX_CFR_CSOF5_Msk                   (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
-#define DMAMUX_CFR_CSOF5                       DMAMUX_CFR_CSOF5_Msk            /*!< Clear Overrun Flag 5                 */
-#define DMAMUX_CFR_CSOF6_Pos                   (6U)
-#define DMAMUX_CFR_CSOF6_Msk                   (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
-#define DMAMUX_CFR_CSOF6                       DMAMUX_CFR_CSOF6_Msk            /*!< Clear Overrun Flag 6                 */
-#define DMAMUX_CFR_CSOF7_Pos                   (7U)
-#define DMAMUX_CFR_CSOF7_Msk                   (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
-#define DMAMUX_CFR_CSOF7                       DMAMUX_CFR_CSOF7_Msk            /*!< Clear Overrun Flag 7                 */
-#define DMAMUX_CFR_CSOF8_Pos                   (8U)
-#define DMAMUX_CFR_CSOF8_Msk                   (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
-#define DMAMUX_CFR_CSOF8                       DMAMUX_CFR_CSOF8_Msk            /*!< Clear Overrun Flag 8                 */
-#define DMAMUX_CFR_CSOF9_Pos                   (9U)
-#define DMAMUX_CFR_CSOF9_Msk                   (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
-#define DMAMUX_CFR_CSOF9                       DMAMUX_CFR_CSOF9_Msk            /*!< Clear Overrun Flag 9                 */
-#define DMAMUX_CFR_CSOF10_Pos                  (10U)
-#define DMAMUX_CFR_CSOF10_Msk                  (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
-#define DMAMUX_CFR_CSOF10                      DMAMUX_CFR_CSOF10_Msk           /*!< Clear Overrun Flag 10                */
-#define DMAMUX_CFR_CSOF11_Pos                  (11U)
-#define DMAMUX_CFR_CSOF11_Msk                  (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
-#define DMAMUX_CFR_CSOF11                      DMAMUX_CFR_CSOF11_Msk           /*!< Clear Overrun Flag 11                */
-#define DMAMUX_CFR_CSOF12_Pos                  (12U)
-#define DMAMUX_CFR_CSOF12_Msk                  (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
-#define DMAMUX_CFR_CSOF12                      DMAMUX_CFR_CSOF12_Msk           /*!< Clear Overrun Flag 12                */
-#define DMAMUX_CFR_CSOF13_Pos                  (13U)
-#define DMAMUX_CFR_CSOF13_Msk                  (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
-#define DMAMUX_CFR_CSOF13                      DMAMUX_CFR_CSOF13_Msk           /*!< Clear Overrun Flag 13                */
-
-/********************  Bits definition for DMAMUX_RGxCR register  ************/
-#define DMAMUX_RGxCR_SIG_ID_Pos                (0U)
-#define DMAMUX_RGxCR_SIG_ID_Msk                (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
-#define DMAMUX_RGxCR_SIG_ID                    DMAMUX_RGxCR_SIG_ID_Msk         /*!< Signal ID                            */
-#define DMAMUX_RGxCR_SIG_ID_0                  (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
-#define DMAMUX_RGxCR_SIG_ID_1                  (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
-#define DMAMUX_RGxCR_SIG_ID_2                  (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
-#define DMAMUX_RGxCR_SIG_ID_3                  (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
-#define DMAMUX_RGxCR_SIG_ID_4                  (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
-#define DMAMUX_RGxCR_OIE_Pos                   (8U)
-#define DMAMUX_RGxCR_OIE_Msk                   (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
-#define DMAMUX_RGxCR_OIE                       DMAMUX_RGxCR_OIE_Msk            /*!< Overrun interrupt enable             */
-#define DMAMUX_RGxCR_GE_Pos                    (16U)
-#define DMAMUX_RGxCR_GE_Msk                    (0x1UL << DMAMUX_RGxCR_GE_Pos)  /*!< 0x00010000 */
-#define DMAMUX_RGxCR_GE                        DMAMUX_RGxCR_GE_Msk             /*!< Generation enable                    */
-#define DMAMUX_RGxCR_GPOL_Pos                  (17U)
-#define DMAMUX_RGxCR_GPOL_Msk                  (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
-#define DMAMUX_RGxCR_GPOL                      DMAMUX_RGxCR_GPOL_Msk           /*!< Generation polarity                  */
-#define DMAMUX_RGxCR_GPOL_0                    (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
-#define DMAMUX_RGxCR_GPOL_1                    (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
-#define DMAMUX_RGxCR_GNBREQ_Pos                (19U)
-#define DMAMUX_RGxCR_GNBREQ_Msk                (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
-#define DMAMUX_RGxCR_GNBREQ                    DMAMUX_RGxCR_GNBREQ_Msk          /*!< Number of request                    */
-#define DMAMUX_RGxCR_GNBREQ_0                  (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
-#define DMAMUX_RGxCR_GNBREQ_1                  (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
-#define DMAMUX_RGxCR_GNBREQ_2                  (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
-#define DMAMUX_RGxCR_GNBREQ_3                  (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
-#define DMAMUX_RGxCR_GNBREQ_4                  (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
-
-/********************  Bits definition for DMAMUX_RGSR register  **************/
-#define DMAMUX_RGSR_OF0_Pos                    (0U)
-#define DMAMUX_RGSR_OF0_Msk                    (0x1UL << DMAMUX_RGSR_OF0_Pos)  /*!< 0x00000001 */
-#define DMAMUX_RGSR_OF0                        DMAMUX_RGSR_OF0_Msk             /*!< Overrun flag 0                       */
-#define DMAMUX_RGSR_OF1_Pos                    (1U)
-#define DMAMUX_RGSR_OF1_Msk                    (0x1UL << DMAMUX_RGSR_OF1_Pos)  /*!< 0x00000002 */
-#define DMAMUX_RGSR_OF1                        DMAMUX_RGSR_OF1_Msk             /*!< Overrun flag 1                       */
-#define DMAMUX_RGSR_OF2_Pos                    (2U)
-#define DMAMUX_RGSR_OF2_Msk                    (0x1UL << DMAMUX_RGSR_OF2_Pos)  /*!< 0x00000004 */
-#define DMAMUX_RGSR_OF2                        DMAMUX_RGSR_OF2_Msk             /*!< Overrun flag 2                       */
-#define DMAMUX_RGSR_OF3_Pos                    (3U)
-#define DMAMUX_RGSR_OF3_Msk                    (0x1UL << DMAMUX_RGSR_OF3_Pos)  /*!< 0x00000008 */
-#define DMAMUX_RGSR_OF3                        DMAMUX_RGSR_OF3_Msk             /*!< Overrun flag 3                       */
-
-/********************  Bits definition for DMAMUX_RGCFR register  **************/
-#define DMAMUX_RGCFR_COF0_Pos                  (0U)
-#define DMAMUX_RGCFR_COF0_Msk                  (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
-#define DMAMUX_RGCFR_COF0                      DMAMUX_RGCFR_COF0_Msk           /*!< Clear Overrun flag 0                 */
-#define DMAMUX_RGCFR_COF1_Pos                  (1U)
-#define DMAMUX_RGCFR_COF1_Msk                  (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
-#define DMAMUX_RGCFR_COF1                      DMAMUX_RGCFR_COF1_Msk           /*!< Clear Overrun flag 1                 */
-#define DMAMUX_RGCFR_COF2_Pos                  (2U)
-#define DMAMUX_RGCFR_COF2_Msk                  (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
-#define DMAMUX_RGCFR_COF2                      DMAMUX_RGCFR_COF2_Msk           /*!< Clear Overrun flag 2                 */
-#define DMAMUX_RGCFR_COF3_Pos                  (3U)
-#define DMAMUX_RGCFR_COF3_Msk                  (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
-#define DMAMUX_RGCFR_COF3                      DMAMUX_RGCFR_COF3_Msk           /*!< Clear Overrun flag 3                 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Asynchronous Interrupt/Event Controller                 */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for EXTI_RTSR1 register  ******************/
-#define EXTI_RTSR1_RT0_Pos       (0U)
-#define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */
-#define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR1_RT1_Pos       (1U)
-#define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */
-#define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR1_RT2_Pos       (2U)
-#define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */
-#define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR1_RT3_Pos       (3U)
-#define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */
-#define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR1_RT4_Pos       (4U)
-#define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */
-#define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR1_RT5_Pos       (5U)
-#define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */
-#define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR1_RT6_Pos       (6U)
-#define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */
-#define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR1_RT7_Pos       (7U)
-#define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */
-#define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR1_RT8_Pos       (8U)
-#define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */
-#define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR1_RT9_Pos       (9U)
-#define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */
-#define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR1_RT10_Pos      (10U)
-#define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */
-#define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR1_RT11_Pos      (11U)
-#define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */
-#define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR1_RT12_Pos      (12U)
-#define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */
-#define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR1_RT13_Pos      (13U)
-#define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */
-#define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR1_RT14_Pos      (14U)
-#define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */
-#define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR1_RT15_Pos      (15U)
-#define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */
-#define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR1_RT16_Pos      (16U)
-#define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */
-#define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR1_RT21_Pos      (21U)
-#define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */
-#define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR1_RT22_Pos      (22U)
-#define EXTI_RTSR1_RT22_Msk      (0x1UL << EXTI_RTSR1_RT22_Pos)                /*!< 0x00400000 */
-#define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR1 register  ******************/
-#define EXTI_FTSR1_FT0_Pos       (0U)
-#define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */
-#define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR1_FT1_Pos       (1U)
-#define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */
-#define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR1_FT2_Pos       (2U)
-#define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */
-#define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR1_FT3_Pos       (3U)
-#define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */
-#define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR1_FT4_Pos       (4U)
-#define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */
-#define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR1_FT5_Pos       (5U)
-#define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */
-#define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR1_FT6_Pos       (6U)
-#define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */
-#define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR1_FT7_Pos       (7U)
-#define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */
-#define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR1_FT8_Pos       (8U)
-#define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */
-#define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR1_FT9_Pos       (9U)
-#define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */
-#define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR1_FT10_Pos      (10U)
-#define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */
-#define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR1_FT11_Pos      (11U)
-#define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */
-#define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR1_FT12_Pos      (12U)
-#define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */
-#define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR1_FT13_Pos      (13U)
-#define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */
-#define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR1_FT14_Pos      (14U)
-#define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */
-#define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR1_FT15_Pos      (15U)
-#define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */
-#define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR1_FT16_Pos      (16U)
-#define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */
-#define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR1_FT21_Pos      (21U)
-#define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */
-#define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR1_FT22_Pos      (22U)
-#define EXTI_FTSR1_FT22_Msk      (0x1UL << EXTI_FTSR1_FT22_Pos)                /*!< 0x00400000 */
-#define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER1 register  *****************/
-#define EXTI_SWIER1_SWI0_Pos     (0U)
-#define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */
-#define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER1_SWI1_Pos     (1U)
-#define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */
-#define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER1_SWI2_Pos     (2U)
-#define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */
-#define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER1_SWI3_Pos     (3U)
-#define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */
-#define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER1_SWI4_Pos     (4U)
-#define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */
-#define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER1_SWI5_Pos     (5U)
-#define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */
-#define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER1_SWI6_Pos     (6U)
-#define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */
-#define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER1_SWI7_Pos     (7U)
-#define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */
-#define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER1_SWI8_Pos     (8U)
-#define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */
-#define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER1_SWI9_Pos     (9U)
-#define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */
-#define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER1_SWI10_Pos    (10U)
-#define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */
-#define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER1_SWI11_Pos    (11U)
-#define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */
-#define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER1_SWI12_Pos    (12U)
-#define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */
-#define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER1_SWI13_Pos    (13U)
-#define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */
-#define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER1_SWI14_Pos    (14U)
-#define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */
-#define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER1_SWI15_Pos    (15U)
-#define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */
-#define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER1_SWI16_Pos    (16U)
-#define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */
-#define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER1_SWI21_Pos    (21U)
-#define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */
-#define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER1_SWI22_Pos    (22U)
-#define EXTI_SWIER1_SWI22_Msk    (0x1UL << EXTI_SWIER1_SWI22_Pos)              /*!< 0x00400000 */
-#define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR1 register  *******************/
-#define EXTI_PR1_PIF0_Pos        (0U)
-#define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */
-#define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
-#define EXTI_PR1_PIF1_Pos        (1U)
-#define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */
-#define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
-#define EXTI_PR1_PIF2_Pos        (2U)
-#define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */
-#define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
-#define EXTI_PR1_PIF3_Pos        (3U)
-#define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */
-#define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
-#define EXTI_PR1_PIF4_Pos        (4U)
-#define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */
-#define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
-#define EXTI_PR1_PIF5_Pos        (5U)
-#define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */
-#define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
-#define EXTI_PR1_PIF6_Pos        (6U)
-#define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */
-#define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
-#define EXTI_PR1_PIF7_Pos        (7U)
-#define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */
-#define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
-#define EXTI_PR1_PIF8_Pos        (8U)
-#define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */
-#define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
-#define EXTI_PR1_PIF9_Pos        (9U)
-#define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */
-#define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
-#define EXTI_PR1_PIF10_Pos       (10U)
-#define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */
-#define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
-#define EXTI_PR1_PIF11_Pos       (11U)
-#define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */
-#define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
-#define EXTI_PR1_PIF12_Pos       (12U)
-#define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */
-#define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
-#define EXTI_PR1_PIF13_Pos       (13U)
-#define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */
-#define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
-#define EXTI_PR1_PIF14_Pos       (14U)
-#define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */
-#define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
-#define EXTI_PR1_PIF15_Pos       (15U)
-#define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */
-#define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
-#define EXTI_PR1_PIF16_Pos       (16U)
-#define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */
-#define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
-#define EXTI_PR1_PIF21_Pos       (21U)
-#define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */
-#define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
-#define EXTI_PR1_PIF22_Pos       (22U)
-#define EXTI_PR1_PIF22_Msk       (0x1UL << EXTI_PR1_PIF22_Pos)                 /*!< 0x00400000 */
-#define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
-
-/******************  Bit definition for EXTI_RTSR2 register  ******************/
-#define EXTI_RTSR2_RT34_Pos      (2U)
-#define EXTI_RTSR2_RT34_Msk      (0x1UL << EXTI_RTSR2_RT34_Pos)                /*!< 0x00000004 */
-#define EXTI_RTSR2_RT34          EXTI_RTSR2_RT34_Msk                           /*!< Rising trigger event configuration bit of line 34 */
-#define EXTI_RTSR2_RT40_Pos      (8U)
-#define EXTI_RTSR2_RT40_Msk      (0x1UL << EXTI_RTSR2_RT40_Pos)                /*!< 0x00000100 */
-#define EXTI_RTSR2_RT40          EXTI_RTSR2_RT40_Msk                           /*!< Rising trigger event configuration bit of line 40 */
-#define EXTI_RTSR2_RT41_Pos      (9U)
-#define EXTI_RTSR2_RT41_Msk      (0x1UL << EXTI_RTSR2_RT41_Pos)                /*!< 0x00000200 */
-#define EXTI_RTSR2_RT41          EXTI_RTSR2_RT41_Msk                           /*!< Rising trigger event configuration bit of line 41 */
-#define EXTI_RTSR2_RT45_Pos      (13U)
-#define EXTI_RTSR2_RT45_Msk      (0x1UL << EXTI_RTSR2_RT45_Pos)                /*!< 0x00002000 */
-#define EXTI_RTSR2_RT45          EXTI_RTSR2_RT45_Msk                           /*!< Rising trigger event configuration bit of line 45 */
-
-/******************  Bit definition for EXTI_FTSR2 register  ******************/
-#define EXTI_FTSR2_FT34_Pos      (2U)
-#define EXTI_FTSR2_FT34_Msk      (0x1UL << EXTI_FTSR2_FT34_Pos)                /*!< 0x00000004 */
-#define EXTI_FTSR2_FT34          EXTI_FTSR2_FT34_Msk                           /*!< Falling trigger event configuration bit of line 34 */
-#define EXTI_FTSR2_FT40_Pos      (8U)
-#define EXTI_FTSR2_FT40_Msk      (0x1UL << EXTI_FTSR2_FT40_Pos)                /*!< 0x00000100 */
-#define EXTI_FTSR2_FT40          EXTI_FTSR2_FT40_Msk                           /*!< Falling trigger event configuration bit of line 40 */
-#define EXTI_FTSR2_FT41_Pos      (9U)
-#define EXTI_FTSR2_FT41_Msk      (0x1UL << EXTI_FTSR2_FT41_Pos)                /*!< 0x00000200 */
-#define EXTI_FTSR2_FT41          EXTI_FTSR2_FT41_Msk                           /*!< Falling trigger event configuration bit of line 41 */
-#define EXTI_FTSR2_FT45_Pos      (13U)
-#define EXTI_FTSR2_FT45_Msk      (0x1UL << EXTI_FTSR2_FT45_Pos)                /*!< 0x00002000 */
-#define EXTI_FTSR2_FT45          EXTI_FTSR2_FT45_Msk                           /*!< Falling trigger event configuration bit of line 45 */
-
-/******************  Bit definition for EXTI_SWIER2 register  *****************/
-#define EXTI_SWIER2_SWI34_Pos    (2U)
-#define EXTI_SWIER2_SWI34_Msk    (0x1UL << EXTI_SWIER2_SWI34_Pos)              /*!< 0x00000004 */
-#define EXTI_SWIER2_SWI34        EXTI_SWIER2_SWI34_Msk                         /*!< Software Interrupt on line 34 */
-#define EXTI_SWIER2_SWI40_Pos    (8U)
-#define EXTI_SWIER2_SWI40_Msk    (0x1UL << EXTI_SWIER2_SWI40_Pos)              /*!< 0x00000100 */
-#define EXTI_SWIER2_SWI40        EXTI_SWIER2_SWI40_Msk                         /*!< Software Interrupt on line 40 */
-#define EXTI_SWIER2_SWI41_Pos    (9U)
-#define EXTI_SWIER2_SWI41_Msk    (0x1UL << EXTI_SWIER2_SWI41_Pos)              /*!< 0x00000200 */
-#define EXTI_SWIER2_SWI41        EXTI_SWIER2_SWI41_Msk                         /*!< Software Interrupt on line 41 */
-#define EXTI_SWIER2_SWI45_Pos    (13U)
-#define EXTI_SWIER2_SWI45_Msk    (0x1UL << EXTI_SWIER2_SWI45_Pos)              /*!< 0x00002000 */
-#define EXTI_SWIER2_SWI45        EXTI_SWIER2_SWI45_Msk                         /*!< Software Interrupt on line 45 */
-
-/*******************  Bit definition for EXTI_PR2 register  *******************/
-#define EXTI_PR2_PIF34_Pos       (2U)
-#define EXTI_PR2_PIF34_Msk       (0x1UL << EXTI_PR2_PIF34_Pos)                 /*!< 0x00000004 */
-#define EXTI_PR2_PIF34           EXTI_PR2_PIF34_Msk                            /*!< Pending bit for line 34 */
-#define EXTI_PR2_PIF40_Pos       (8U)
-#define EXTI_PR2_PIF40_Msk       (0x1UL << EXTI_PR2_PIF40_Pos)                 /*!< 0x00000100 */
-#define EXTI_PR2_PIF40           EXTI_PR2_PIF40_Msk                            /*!< Pending bit for line 40 */
-#define EXTI_PR2_PIF41_Pos       (9U)
-#define EXTI_PR2_PIF41_Msk       (0x1UL << EXTI_PR2_PIF41_Pos)                 /*!< 0x00000200 */
-#define EXTI_PR2_PIF41           EXTI_PR2_PIF41_Msk                            /*!< Pending bit for line 41 */
-#define EXTI_PR2_PIF45_Pos       (13U)
-#define EXTI_PR2_PIF45_Msk       (0x1UL << EXTI_PR2_PIF45_Pos)                 /*!< 0x00002000 */
-#define EXTI_PR2_PIF45           EXTI_PR2_PIF45_Msk                            /*!< Pending bit for line 45 */
-
-/********************  Bits definition for EXTI_IMR1 register  **************/
-#define EXTI_IMR1_IM0_Pos        (0U)
-#define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */
-#define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< CPU1 Interrupt Mask on line 0 */
-#define EXTI_IMR1_IM1_Pos        (1U)
-#define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */
-#define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< CPU1 Interrupt Mask on line 1 */
-#define EXTI_IMR1_IM2_Pos        (2U)
-#define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */
-#define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< CPU1 Interrupt Mask on line 2 */
-#define EXTI_IMR1_IM3_Pos        (3U)
-#define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */
-#define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< CPU1 Interrupt Mask on line 3 */
-#define EXTI_IMR1_IM4_Pos        (4U)
-#define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */
-#define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< CPU1 Interrupt Mask on line 4 */
-#define EXTI_IMR1_IM5_Pos        (5U)
-#define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */
-#define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< CPU1 Interrupt Mask on line 5 */
-#define EXTI_IMR1_IM6_Pos        (6U)
-#define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */
-#define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< CPU1 Interrupt Mask on line 6 */
-#define EXTI_IMR1_IM7_Pos        (7U)
-#define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */
-#define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< CPU1 Interrupt Mask on line 7 */
-#define EXTI_IMR1_IM8_Pos        (8U)
-#define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */
-#define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< CPU1 Interrupt Mask on line 8 */
-#define EXTI_IMR1_IM9_Pos        (9U)
-#define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */
-#define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< CPU1 Interrupt Mask on line 9 */
-#define EXTI_IMR1_IM10_Pos       (10U)
-#define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */
-#define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< CPU1 Interrupt Mask on line 10 */
-#define EXTI_IMR1_IM11_Pos       (11U)
-#define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */
-#define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< CPU1 Interrupt Mask on line 11 */
-#define EXTI_IMR1_IM12_Pos       (12U)
-#define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */
-#define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< CPU1 Interrupt Mask on line 12 */
-#define EXTI_IMR1_IM13_Pos       (13U)
-#define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */
-#define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< CPU1 Interrupt Mask on line 13 */
-#define EXTI_IMR1_IM14_Pos       (14U)
-#define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */
-#define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< CPU1 Interrupt Mask on line 14 */
-#define EXTI_IMR1_IM15_Pos       (15U)
-#define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */
-#define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< CPU1 Interrupt Mask on line 15 */
-#define EXTI_IMR1_IM16_Pos       (16U)
-#define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */
-#define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< CPU1 Interrupt Mask on line 16 */
-#define EXTI_IMR1_IM17_Pos       (17U)
-#define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */
-#define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< CPU1 Interrupt Mask on line 17 */
-#define EXTI_IMR1_IM18_Pos       (18U)
-#define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */
-#define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< CPU1 Interrupt Mask on line 18 */
-#define EXTI_IMR1_IM19_Pos       (19U)
-#define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */
-#define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< CPU1 Interrupt Mask on line 19 */
-#define EXTI_IMR1_IM20_Pos       (20U)
-#define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */
-#define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< CPU1 Interrupt Mask on line 20 */
-#define EXTI_IMR1_IM21_Pos       (21U)
-#define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */
-#define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< CPU1 Interrupt Mask on line 21 */
-#define EXTI_IMR1_IM22_Pos       (22U)
-#define EXTI_IMR1_IM22_Msk       (0x1UL << EXTI_IMR1_IM22_Pos)                 /*!< 0x00400000 */
-#define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< CPU1 Interrupt Mask on line 22 */
-#define EXTI_IMR1_IM23_Pos       (23U)
-#define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */
-#define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< CPU1 Interrupt Mask on line 23 */
-#define EXTI_IMR1_IM24_Pos       (24U)
-#define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */
-#define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< CPU1 Interrupt Mask on line 24 */
-#define EXTI_IMR1_IM25_Pos       (25U)
-#define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */
-#define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< CPU1 Interrupt Mask on line 25 */
-#define EXTI_IMR1_IM26_Pos       (26U)
-#define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */
-#define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< CPU1 Interrupt Mask on line 26 */
-#define EXTI_IMR1_IM27_Pos       (27U)
-#define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */
-#define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< CPU1 Interrupt Mask on line 27 */
-#define EXTI_IMR1_IM28_Pos       (28U)
-#define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */
-#define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< CPU1 Interrupt Mask on line 28 */
-#define EXTI_IMR1_IM29_Pos       (29U)
-#define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */
-#define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< CPU1 Interrupt Mask on line 29 */
-#define EXTI_IMR1_IM30_Pos       (30U)
-#define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */
-#define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< CPU1 Interrupt Mask on line 30 */
-#define EXTI_IMR1_IM31_Pos       (31U)
-#define EXTI_IMR1_IM31_Msk       (0x1UL << EXTI_IMR1_IM31_Pos)                 /*!< 0x80000000 */
-#define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< CPU1 Interrupt Mask on line 31 */
-
-/********************  Bits definition for EXTI_EMR1 register  **************/
-#define EXTI_EMR1_EM0_Pos        (0U)
-#define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */
-#define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< CPU1 Event Mask on line 0 */
-#define EXTI_EMR1_EM1_Pos        (1U)
-#define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */
-#define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< CPU1 Event Mask on line 1 */
-#define EXTI_EMR1_EM2_Pos        (2U)
-#define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */
-#define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< CPU1 Event Mask on line 2 */
-#define EXTI_EMR1_EM3_Pos        (3U)
-#define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */
-#define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< CPU1 Event Mask on line 3 */
-#define EXTI_EMR1_EM4_Pos        (4U)
-#define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */
-#define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< CPU1 Event Mask on line 4 */
-#define EXTI_EMR1_EM5_Pos        (5U)
-#define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */
-#define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< CPU1 Event Mask on line 5 */
-#define EXTI_EMR1_EM6_Pos        (6U)
-#define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */
-#define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< CPU1 Event Mask on line 6 */
-#define EXTI_EMR1_EM7_Pos        (7U)
-#define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */
-#define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< CPU1 Event Mask on line 7 */
-#define EXTI_EMR1_EM8_Pos        (8U)
-#define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */
-#define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< CPU1 Event Mask on line 8 */
-#define EXTI_EMR1_EM9_Pos        (9U)
-#define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */
-#define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< CPU1 Event Mask on line 9 */
-#define EXTI_EMR1_EM10_Pos       (10U)
-#define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */
-#define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< CPU1 Event Mask on line 10 */
-#define EXTI_EMR1_EM11_Pos       (11U)
-#define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */
-#define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< CPU1 Event Mask on line 11 */
-#define EXTI_EMR1_EM12_Pos       (12U)
-#define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */
-#define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< CPU1 Event Mask on line 12 */
-#define EXTI_EMR1_EM13_Pos       (13U)
-#define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */
-#define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< CPU1 Event Mask on line 13 */
-#define EXTI_EMR1_EM14_Pos       (14U)
-#define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */
-#define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< CPU1 Event Mask on line 14 */
-#define EXTI_EMR1_EM15_Pos       (15U)
-#define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */
-#define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< CPU1 Event Mask on line 15 */
-#define EXTI_EMR1_EM17_Pos       (17U)
-#define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */
-#define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< CPU1 Event Mask on line 17 */
-#define EXTI_EMR1_EM19_Pos       (19U)
-#define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */
-#define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< CPU1 Event Mask on line 19 */
-#define EXTI_EMR1_EM20_Pos       (20U)
-#define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */
-#define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< CPU1 Event Mask on line 20 */
-#define EXTI_EMR1_EM21_Pos       (21U)
-#define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */
-#define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< CPU1 Event Mask on line 21 */
-#define EXTI_EMR1_EM22_Pos       (22U)
-#define EXTI_EMR1_EM22_Msk       (0x1UL << EXTI_EMR1_EM22_Pos)                 /*!< 0x00400000 */
-#define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< CPU1 Event Mask on line 22 */
-
-/********************  Bits definition for EXTI_IMR2 register  **************/
-#define EXTI_IMR2_IM34_Pos       (2U)
-#define EXTI_IMR2_IM34_Msk       (0x1UL << EXTI_IMR2_IM34_Pos)                 /*!< 0x00000004 */
-#define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< CPU1 Interrupt Mask on line 34 */
-#define EXTI_IMR2_IM36_Pos       (4U)
-#define EXTI_IMR2_IM36_Msk       (0x1UL << EXTI_IMR2_IM36_Pos)                 /*!< 0x00000010 */
-#define EXTI_IMR2_IM36           EXTI_IMR2_IM36_Msk                            /*!< CPU1 Interrupt Mask on line 36 */
-#define EXTI_IMR2_IM37_Pos       (5U)
-#define EXTI_IMR2_IM37_Msk       (0x1UL << EXTI_IMR2_IM37_Pos)                 /*!< 0x00000020 */
-#define EXTI_IMR2_IM37           EXTI_IMR2_IM37_Msk                            /*!< CPU1 Interrupt Mask on line 37 */
-#define EXTI_IMR2_IM38_Pos       (6U)
-#define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */
-#define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< CPU1 Interrupt Mask on line 38 */
-#define EXTI_IMR2_IM39_Pos       (7U)
-#define EXTI_IMR2_IM39_Msk       (0x1UL << EXTI_IMR2_IM39_Pos)                 /*!< 0x00000080 */
-#define EXTI_IMR2_IM39           EXTI_IMR2_IM39_Msk                            /*!< CPU1 Interrupt Mask on line 39 */
-#define EXTI_IMR2_IM40_Pos       (8U)
-#define EXTI_IMR2_IM40_Msk       (0x1UL << EXTI_IMR2_IM40_Pos)                 /*!< 0x00000100 */
-#define EXTI_IMR2_IM40           EXTI_IMR2_IM40_Msk                            /*!< CPU1 Interrupt Mask on line 40 */
-#define EXTI_IMR2_IM41_Pos       (9U)
-#define EXTI_IMR2_IM41_Msk       (0x1UL << EXTI_IMR2_IM41_Pos)                 /*!< 0x00000200 */
-#define EXTI_IMR2_IM41           EXTI_IMR2_IM41_Msk                            /*!< CPU1 Interrupt Mask on line 41 */
-#define EXTI_IMR2_IM42_Pos       (10U)
-#define EXTI_IMR2_IM42_Msk       (0x1UL << EXTI_IMR2_IM42_Pos)                 /*!< 0x00000400 */
-#define EXTI_IMR2_IM42           EXTI_IMR2_IM42_Msk                            /*!< CPU1 Interrupt Mask on line 42 */
-#define EXTI_IMR2_IM43_Pos       (11U)
-#define EXTI_IMR2_IM43_Msk       (0x1UL << EXTI_IMR2_IM43_Pos)                 /*!< 0x00000800 */
-#define EXTI_IMR2_IM43           EXTI_IMR2_IM43_Msk                            /*!< CPU1 Interrupt Mask on line 43 */
-#define EXTI_IMR2_IM44_Pos       (12U)
-#define EXTI_IMR2_IM44_Msk       (0x1UL << EXTI_IMR2_IM44_Pos)                 /*!< 0x00001000 */
-#define EXTI_IMR2_IM44           EXTI_IMR2_IM44_Msk                            /*!< CPU1 Interrupt Mask on line 44 */
-#define EXTI_IMR2_IM45_Pos       (13U)
-#define EXTI_IMR2_IM45_Msk       (0x1UL << EXTI_IMR2_IM45_Pos)                 /*!< 0x00002000 */
-#define EXTI_IMR2_IM45           EXTI_IMR2_IM45_Msk                            /*!< CPU1 Interrupt Mask on line 45 */
-#define EXTI_IMR2_IM46_Pos       (14U)
-#define EXTI_IMR2_IM46_Msk       (0x1UL << EXTI_IMR2_IM46_Pos)                 /*!< 0x00004000 */
-#define EXTI_IMR2_IM46           EXTI_IMR2_IM46_Msk                            /*!< CPU1 Interrupt Mask on line 46 */
-
-/********************  Bits definition for EXTI_EMR2 register  **************/
-#define EXTI_EMR2_EM40_Pos       (8U)
-#define EXTI_EMR2_EM40_Msk       (0x1UL << EXTI_EMR2_EM40_Pos)                 /*!< 0x00000100 */
-#define EXTI_EMR2_EM40           EXTI_EMR2_EM40_Msk                            /*!< CPU1 Event Mask on line 40 */
-#define EXTI_EMR2_EM41_Pos       (9U)
-#define EXTI_EMR2_EM41_Msk       (0x1UL << EXTI_EMR2_EM41_Pos)                 /*!< 0x00000200 */
-#define EXTI_EMR2_EM41           EXTI_EMR2_EM41_Msk                            /*!< CPU1 Event Mask on line 41 */
-
-/********************  Bits definition for EXTI_C2IMR1 register  **************/
-#define EXTI_C2IMR1_IM0_Pos      (0U)
-#define EXTI_C2IMR1_IM0_Msk      (0x1UL << EXTI_C2IMR1_IM0_Pos)                /*!< 0x00000001 */
-#define EXTI_C2IMR1_IM0          EXTI_C2IMR1_IM0_Msk                           /*!< CPU2 Interrupt Mask on line 0 */
-#define EXTI_C2IMR1_IM1_Pos      (1U)
-#define EXTI_C2IMR1_IM1_Msk      (0x1UL << EXTI_C2IMR1_IM1_Pos)                /*!< 0x00000002 */
-#define EXTI_C2IMR1_IM1          EXTI_C2IMR1_IM1_Msk                           /*!< CPU2 Interrupt Mask on line 1 */
-#define EXTI_C2IMR1_IM2_Pos      (2U)
-#define EXTI_C2IMR1_IM2_Msk      (0x1UL << EXTI_C2IMR1_IM2_Pos)                /*!< 0x00000004 */
-#define EXTI_C2IMR1_IM2          EXTI_C2IMR1_IM2_Msk                           /*!< CPU2 Interrupt Mask on line 2 */
-#define EXTI_C2IMR1_IM3_Pos      (3U)
-#define EXTI_C2IMR1_IM3_Msk      (0x1UL << EXTI_C2IMR1_IM3_Pos)                /*!< 0x00000008 */
-#define EXTI_C2IMR1_IM3          EXTI_C2IMR1_IM3_Msk                           /*!< CPU2 Interrupt Mask on line 3 */
-#define EXTI_C2IMR1_IM4_Pos      (4U)
-#define EXTI_C2IMR1_IM4_Msk      (0x1UL << EXTI_C2IMR1_IM4_Pos)                /*!< 0x00000010 */
-#define EXTI_C2IMR1_IM4          EXTI_C2IMR1_IM4_Msk                           /*!< CPU2 Interrupt Mask on line 4 */
-#define EXTI_C2IMR1_IM5_Pos      (5U)
-#define EXTI_C2IMR1_IM5_Msk      (0x1UL << EXTI_C2IMR1_IM5_Pos)                /*!< 0x00000020 */
-#define EXTI_C2IMR1_IM5          EXTI_C2IMR1_IM5_Msk                           /*!< CPU2 Interrupt Mask on line 5 */
-#define EXTI_C2IMR1_IM6_Pos      (6U)
-#define EXTI_C2IMR1_IM6_Msk      (0x1UL << EXTI_C2IMR1_IM6_Pos)                /*!< 0x00000040 */
-#define EXTI_C2IMR1_IM6          EXTI_C2IMR1_IM6_Msk                           /*!< CPU2 Interrupt Mask on line 6 */
-#define EXTI_C2IMR1_IM7_Pos      (7U)
-#define EXTI_C2IMR1_IM7_Msk      (0x1UL << EXTI_C2IMR1_IM7_Pos)                /*!< 0x00000080 */
-#define EXTI_C2IMR1_IM7          EXTI_C2IMR1_IM7_Msk                           /*!< CPU2 Interrupt Mask on line 7 */
-#define EXTI_C2IMR1_IM8_Pos      (8U)
-#define EXTI_C2IMR1_IM8_Msk      (0x1UL << EXTI_C2IMR1_IM8_Pos)                /*!< 0x00000100 */
-#define EXTI_C2IMR1_IM8          EXTI_C2IMR1_IM8_Msk                           /*!< CPU2 Interrupt Mask on line 8 */
-#define EXTI_C2IMR1_IM9_Pos      (9U)
-#define EXTI_C2IMR1_IM9_Msk      (0x1UL << EXTI_C2IMR1_IM9_Pos)                /*!< 0x00000200 */
-#define EXTI_C2IMR1_IM9          EXTI_C2IMR1_IM9_Msk                           /*!< CPU2 Interrupt Mask on line 9 */
-#define EXTI_C2IMR1_IM10_Pos     (10U)
-#define EXTI_C2IMR1_IM10_Msk     (0x1UL << EXTI_C2IMR1_IM10_Pos)               /*!< 0x00000400 */
-#define EXTI_C2IMR1_IM10         EXTI_C2IMR1_IM10_Msk                          /*!< CPU2 Interrupt Mask on line 10 */
-#define EXTI_C2IMR1_IM11_Pos     (11U)
-#define EXTI_C2IMR1_IM11_Msk     (0x1UL << EXTI_C2IMR1_IM11_Pos)               /*!< 0x00000800 */
-#define EXTI_C2IMR1_IM11         EXTI_C2IMR1_IM11_Msk                          /*!< CPU2 Interrupt Mask on line 11 */
-#define EXTI_C2IMR1_IM12_Pos     (12U)
-#define EXTI_C2IMR1_IM12_Msk     (0x1UL << EXTI_C2IMR1_IM12_Pos)               /*!< 0x00001000 */
-#define EXTI_C2IMR1_IM12         EXTI_C2IMR1_IM12_Msk                          /*!< CPU2 Interrupt Mask on line 12 */
-#define EXTI_C2IMR1_IM13_Pos     (13U)
-#define EXTI_C2IMR1_IM13_Msk     (0x1UL << EXTI_C2IMR1_IM13_Pos)               /*!< 0x00002000 */
-#define EXTI_C2IMR1_IM13         EXTI_C2IMR1_IM13_Msk                          /*!< CPU2 Interrupt Mask on line 13 */
-#define EXTI_C2IMR1_IM14_Pos     (14U)
-#define EXTI_C2IMR1_IM14_Msk     (0x1UL << EXTI_C2IMR1_IM14_Pos)               /*!< 0x00004000 */
-#define EXTI_C2IMR1_IM14         EXTI_C2IMR1_IM14_Msk                          /*!< CPU2 Interrupt Mask on line 14 */
-#define EXTI_C2IMR1_IM15_Pos     (15U)
-#define EXTI_C2IMR1_IM15_Msk     (0x1UL << EXTI_C2IMR1_IM15_Pos)               /*!< 0x00008000 */
-#define EXTI_C2IMR1_IM15         EXTI_C2IMR1_IM15_Msk                          /*!< CPU2 Interrupt Mask on line 15 */
-#define EXTI_C2IMR1_IM16_Pos     (16U)
-#define EXTI_C2IMR1_IM16_Msk     (0x1UL << EXTI_C2IMR1_IM16_Pos)               /*!< 0x00010000 */
-#define EXTI_C2IMR1_IM16         EXTI_C2IMR1_IM16_Msk                          /*!< CPU2 Interrupt Mask on line 16 */
-#define EXTI_C2IMR1_IM17_Pos     (17U)
-#define EXTI_C2IMR1_IM17_Msk     (0x1UL << EXTI_C2IMR1_IM17_Pos)               /*!< 0x00020000 */
-#define EXTI_C2IMR1_IM17         EXTI_C2IMR1_IM17_Msk                          /*!< CPU2 Interrupt Mask on line 17 */
-#define EXTI_C2IMR1_IM18_Pos     (18U)
-#define EXTI_C2IMR1_IM18_Msk     (0x1UL << EXTI_C2IMR1_IM18_Pos)               /*!< 0x00040000 */
-#define EXTI_C2IMR1_IM18         EXTI_C2IMR1_IM18_Msk                          /*!< CPU2 Interrupt Mask on line 18 */
-#define EXTI_C2IMR1_IM19_Pos     (19U)
-#define EXTI_C2IMR1_IM19_Msk     (0x1UL << EXTI_C2IMR1_IM19_Pos)               /*!< 0x00080000 */
-#define EXTI_C2IMR1_IM19         EXTI_C2IMR1_IM19_Msk                          /*!< CPU2 Interrupt Mask on line 19 */
-#define EXTI_C2IMR1_IM20_Pos     (20U)
-#define EXTI_C2IMR1_IM20_Msk     (0x1UL << EXTI_C2IMR1_IM20_Pos)               /*!< 0x00100000 */
-#define EXTI_C2IMR1_IM20         EXTI_C2IMR1_IM20_Msk                          /*!< CPU2 Interrupt Mask on line 20 */
-#define EXTI_C2IMR1_IM21_Pos     (21U)
-#define EXTI_C2IMR1_IM21_Msk     (0x1UL << EXTI_C2IMR1_IM21_Pos)               /*!< 0x00200000 */
-#define EXTI_C2IMR1_IM21         EXTI_C2IMR1_IM21_Msk                          /*!< CPU2 Interrupt Mask on line 21 */
-#define EXTI_C2IMR1_IM22_Pos     (22U)
-#define EXTI_C2IMR1_IM22_Msk     (0x1UL << EXTI_C2IMR1_IM22_Pos)               /*!< 0x00400000 */
-#define EXTI_C2IMR1_IM22         EXTI_C2IMR1_IM22_Msk                          /*!< CPU2 Interrupt Mask on line 22 */
-#define EXTI_C2IMR1_IM23_Pos     (23U)
-#define EXTI_C2IMR1_IM23_Msk     (0x1UL << EXTI_C2IMR1_IM23_Pos)               /*!< 0x00800000 */
-#define EXTI_C2IMR1_IM23         EXTI_C2IMR1_IM23_Msk                          /*!< CPU2 Interrupt Mask on line 23 */
-#define EXTI_C2IMR1_IM24_Pos     (24U)
-#define EXTI_C2IMR1_IM24_Msk     (0x1UL << EXTI_C2IMR1_IM24_Pos)               /*!< 0x01000000 */
-#define EXTI_C2IMR1_IM24         EXTI_C2IMR1_IM24_Msk                          /*!< CPU2 Interrupt Mask on line 24 */
-#define EXTI_C2IMR1_IM25_Pos     (25U)
-#define EXTI_C2IMR1_IM25_Msk     (0x1UL << EXTI_C2IMR1_IM25_Pos)               /*!< 0x02000000 */
-#define EXTI_C2IMR1_IM25         EXTI_C2IMR1_IM25_Msk                          /*!< CPU2 Interrupt Mask on line 25 */
-#define EXTI_C2IMR1_IM26_Pos     (26U)
-#define EXTI_C2IMR1_IM26_Msk     (0x1UL << EXTI_C2IMR1_IM26_Pos)               /*!< 0x04000000 */
-#define EXTI_C2IMR1_IM26         EXTI_C2IMR1_IM26_Msk                          /*!< CPU2 Interrupt Mask on line 26 */
-#define EXTI_C2IMR1_IM27_Pos     (27U)
-#define EXTI_C2IMR1_IM27_Msk     (0x1UL << EXTI_C2IMR1_IM27_Pos)               /*!< 0x08000000 */
-#define EXTI_C2IMR1_IM27         EXTI_C2IMR1_IM27_Msk                          /*!< CPU2 Interrupt Mask on line 27 */
-#define EXTI_C2IMR1_IM28_Pos     (28U)
-#define EXTI_C2IMR1_IM28_Msk     (0x1UL << EXTI_C2IMR1_IM28_Pos)               /*!< 0x10000000 */
-#define EXTI_C2IMR1_IM28         EXTI_C2IMR1_IM28_Msk                          /*!< CPU2 Interrupt Mask on line 28 */
-#define EXTI_C2IMR1_IM29_Pos     (29U)
-#define EXTI_C2IMR1_IM29_Msk     (0x1UL << EXTI_C2IMR1_IM29_Pos)               /*!< 0x20000000 */
-#define EXTI_C2IMR1_IM29         EXTI_C2IMR1_IM29_Msk                          /*!< CPU2 Interrupt Mask on line 29 */
-#define EXTI_C2IMR1_IM30_Pos     (30U)
-#define EXTI_C2IMR1_IM30_Msk     (0x1UL << EXTI_C2IMR1_IM30_Pos)               /*!< 0x40000000 */
-#define EXTI_C2IMR1_IM30         EXTI_C2IMR1_IM30_Msk                          /*!< CPU2 Interrupt Mask on line 30 */
-#define EXTI_C2IMR1_IM31_Pos     (31U)
-#define EXTI_C2IMR1_IM31_Msk     (0x1UL << EXTI_C2IMR1_IM31_Pos)               /*!< 0x80000000 */
-#define EXTI_C2IMR1_IM31         EXTI_C2IMR1_IM31_Msk                          /*!< CPU2 Interrupt Mask on line 31 */
-
-/********************  Bits definition for EXTI_C2EMR1 register  **************/
-#define EXTI_C2EMR1_EM0_Pos      (0U)
-#define EXTI_C2EMR1_EM0_Msk      (0x1UL << EXTI_C2EMR1_EM0_Pos)                /*!< 0x00000001 */
-#define EXTI_C2EMR1_EM0          EXTI_C2EMR1_EM0_Msk                           /*!< CPU2 Event Mask on line 0 */
-#define EXTI_C2EMR1_EM1_Pos      (1U)
-#define EXTI_C2EMR1_EM1_Msk      (0x1UL << EXTI_C2EMR1_EM1_Pos)                /*!< 0x00000002 */
-#define EXTI_C2EMR1_EM1          EXTI_C2EMR1_EM1_Msk                           /*!< CPU2 Event Mask on line 1 */
-#define EXTI_C2EMR1_EM2_Pos      (2U)
-#define EXTI_C2EMR1_EM2_Msk      (0x1UL << EXTI_C2EMR1_EM2_Pos)                /*!< 0x00000004 */
-#define EXTI_C2EMR1_EM2          EXTI_C2EMR1_EM2_Msk                           /*!< CPU2 Event Mask on line 2 */
-#define EXTI_C2EMR1_EM3_Pos      (3U)
-#define EXTI_C2EMR1_EM3_Msk      (0x1UL << EXTI_C2EMR1_EM3_Pos)                /*!< 0x00000008 */
-#define EXTI_C2EMR1_EM3          EXTI_C2EMR1_EM3_Msk                           /*!< CPU2 Event Mask on line 3 */
-#define EXTI_C2EMR1_EM4_Pos      (4U)
-#define EXTI_C2EMR1_EM4_Msk      (0x1UL << EXTI_C2EMR1_EM4_Pos)                /*!< 0x00000010 */
-#define EXTI_C2EMR1_EM4          EXTI_C2EMR1_EM4_Msk                           /*!< CPU2 Event Mask on line 4 */
-#define EXTI_C2EMR1_EM5_Pos      (5U)
-#define EXTI_C2EMR1_EM5_Msk      (0x1UL << EXTI_C2EMR1_EM5_Pos)                /*!< 0x00000020 */
-#define EXTI_C2EMR1_EM5          EXTI_C2EMR1_EM5_Msk                           /*!< CPU2 Event Mask on line 5 */
-#define EXTI_C2EMR1_EM6_Pos      (6U)
-#define EXTI_C2EMR1_EM6_Msk      (0x1UL << EXTI_C2EMR1_EM6_Pos)                /*!< 0x00000040 */
-#define EXTI_C2EMR1_EM6          EXTI_C2EMR1_EM6_Msk                           /*!< CPU2 Event Mask on line 6 */
-#define EXTI_C2EMR1_EM7_Pos      (7U)
-#define EXTI_C2EMR1_EM7_Msk      (0x1UL << EXTI_C2EMR1_EM7_Pos)                /*!< 0x00000080 */
-#define EXTI_C2EMR1_EM7          EXTI_C2EMR1_EM7_Msk                           /*!< CPU2 Event Mask on line 7 */
-#define EXTI_C2EMR1_EM8_Pos      (8U)
-#define EXTI_C2EMR1_EM8_Msk      (0x1UL << EXTI_C2EMR1_EM8_Pos)                /*!< 0x00000100 */
-#define EXTI_C2EMR1_EM8          EXTI_C2EMR1_EM8_Msk                           /*!< CPU2 Event Mask on line 8 */
-#define EXTI_C2EMR1_EM9_Pos      (9U)
-#define EXTI_C2EMR1_EM9_Msk      (0x1UL << EXTI_C2EMR1_EM9_Pos)                /*!< 0x00000200 */
-#define EXTI_C2EMR1_EM9          EXTI_C2EMR1_EM9_Msk                           /*!< CPU2 Event Mask on line 9 */
-#define EXTI_C2EMR1_EM10_Pos     (10U)
-#define EXTI_C2EMR1_EM10_Msk     (0x1UL << EXTI_C2EMR1_EM10_Pos)               /*!< 0x00000400 */
-#define EXTI_C2EMR1_EM10         EXTI_C2EMR1_EM10_Msk                          /*!< CPU2 Event Mask on line 10 */
-#define EXTI_C2EMR1_EM11_Pos     (11U)
-#define EXTI_C2EMR1_EM11_Msk     (0x1UL << EXTI_C2EMR1_EM11_Pos)               /*!< 0x00000800 */
-#define EXTI_C2EMR1_EM11         EXTI_C2EMR1_EM11_Msk                          /*!< CPU2 Event Mask on line 11 */
-#define EXTI_C2EMR1_EM12_Pos     (12U)
-#define EXTI_C2EMR1_EM12_Msk     (0x1UL << EXTI_C2EMR1_EM12_Pos)               /*!< 0x00001000 */
-#define EXTI_C2EMR1_EM12         EXTI_C2EMR1_EM12_Msk                          /*!< CPU2 Event Mask on line 12 */
-#define EXTI_C2EMR1_EM13_Pos     (13U)
-#define EXTI_C2EMR1_EM13_Msk     (0x1UL << EXTI_C2EMR1_EM13_Pos)               /*!< 0x00002000 */
-#define EXTI_C2EMR1_EM13         EXTI_C2EMR1_EM13_Msk                          /*!< CPU2 Event Mask on line 13 */
-#define EXTI_C2EMR1_EM14_Pos     (14U)
-#define EXTI_C2EMR1_EM14_Msk     (0x1UL << EXTI_C2EMR1_EM14_Pos)               /*!< 0x00004000 */
-#define EXTI_C2EMR1_EM14         EXTI_C2EMR1_EM14_Msk                          /*!< CPU2 Event Mask on line 14 */
-#define EXTI_C2EMR1_EM15_Pos     (15U)
-#define EXTI_C2EMR1_EM15_Msk     (0x1UL << EXTI_C2EMR1_EM15_Pos)               /*!< 0x00008000 */
-#define EXTI_C2EMR1_EM15         EXTI_C2EMR1_EM15_Msk                          /*!< CPU2 Event Mask on line 15 */
-#define EXTI_C2EMR1_EM17_Pos     (17U)
-#define EXTI_C2EMR1_EM17_Msk     (0x1UL << EXTI_C2EMR1_EM17_Pos)               /*!< 0x00020000 */
-#define EXTI_C2EMR1_EM17         EXTI_C2EMR1_EM17_Msk                          /*!< CPU2 Event Mask on line 17 */
-#define EXTI_C2EMR1_EM19_Pos     (19U)
-#define EXTI_C2EMR1_EM19_Msk     (0x1UL << EXTI_C2EMR1_EM19_Pos)               /*!< 0x00080000 */
-#define EXTI_C2EMR1_EM19         EXTI_C2EMR1_EM19_Msk                          /*!< CPU2 Event Mask on line 19 */
-#define EXTI_C2EMR1_EM20_Pos     (20U)
-#define EXTI_C2EMR1_EM20_Msk     (0x1UL << EXTI_C2EMR1_EM20_Pos)               /*!< 0x00100000 */
-#define EXTI_C2EMR1_EM20         EXTI_C2EMR1_EM20_Msk                          /*!< CPU2 Event Mask on line 20 */
-#define EXTI_C2EMR1_EM21_Pos     (21U)
-#define EXTI_C2EMR1_EM21_Msk     (0x1UL << EXTI_C2EMR1_EM21_Pos)               /*!< 0x00200000 */
-#define EXTI_C2EMR1_EM21         EXTI_C2EMR1_EM21_Msk                          /*!< CPU2 Event Mask on line 21 */
-#define EXTI_C2EMR1_EM22_Pos     (22U)
-#define EXTI_C2EMR1_EM22_Msk     (0x1UL << EXTI_C2EMR1_EM22_Pos)               /*!< 0x00400000 */
-#define EXTI_C2EMR1_EM22         EXTI_C2EMR1_EM22_Msk                          /*!< CPU2 Event Mask on line 22 */
-
-/********************  Bits definition for EXTI_C2IMR2 register  **************/
-#define EXTI_C2IMR2_IM34_Pos     (2U)
-#define EXTI_C2IMR2_IM34_Msk     (0x1UL << EXTI_C2IMR2_IM34_Pos)               /*!< 0x00000004 */
-#define EXTI_C2IMR2_IM34         EXTI_C2IMR2_IM34_Msk                          /*!< CPU2 Interrupt Mask on line 34 */
-#define EXTI_C2IMR2_IM36_Pos     (4U)
-#define EXTI_C2IMR2_IM36_Msk     (0x1UL << EXTI_C2IMR2_IM36_Pos)               /*!< 0x00000010 */
-#define EXTI_C2IMR2_IM36         EXTI_C2IMR2_IM36_Msk                          /*!< CPU2 Interrupt Mask on line 36 */
-#define EXTI_C2IMR2_IM37_Pos     (5U)
-#define EXTI_C2IMR2_IM37_Msk     (0x1UL << EXTI_C2IMR2_IM37_Pos)               /*!< 0x00000020 */
-#define EXTI_C2IMR2_IM37         EXTI_C2IMR2_IM37_Msk                          /*!< CPU2 Interrupt Mask on line 37 */
-#define EXTI_C2IMR2_IM38_Pos     (6U)
-#define EXTI_C2IMR2_IM38_Msk     (0x1UL << EXTI_C2IMR2_IM38_Pos)               /*!< 0x00000040 */
-#define EXTI_C2IMR2_IM38         EXTI_C2IMR2_IM38_Msk                          /*!< CPU2 Interrupt Mask on line 38 */
-#define EXTI_C2IMR2_IM39_Pos     (7U)
-#define EXTI_C2IMR2_IM39_Msk     (0x1UL << EXTI_C2IMR2_IM39_Pos)               /*!< 0x00000080 */
-#define EXTI_C2IMR2_IM39         EXTI_C2IMR2_IM39_Msk                          /*!< CPU2 Interrupt Mask on line 39 */
-#define EXTI_C2IMR2_IM40_Pos     (8U)
-#define EXTI_C2IMR2_IM40_Msk     (0x1UL << EXTI_C2IMR2_IM40_Pos)               /*!< 0x00000100 */
-#define EXTI_C2IMR2_IM40         EXTI_C2IMR2_IM40_Msk                          /*!< CPU2 Interrupt Mask on line 40 */
-#define EXTI_C2IMR2_IM41_Pos     (9U)
-#define EXTI_C2IMR2_IM41_Msk     (0x1UL << EXTI_C2IMR2_IM41_Pos)               /*!< 0x00000200 */
-#define EXTI_C2IMR2_IM41         EXTI_C2IMR2_IM41_Msk                          /*!< CPU2 Interrupt Mask on line 41 */
-#define EXTI_C2IMR2_IM42_Pos     (10U)
-#define EXTI_C2IMR2_IM42_Msk     (0x1UL << EXTI_C2IMR2_IM42_Pos)               /*!< 0x00000400 */
-#define EXTI_C2IMR2_IM42         EXTI_C2IMR2_IM42_Msk                          /*!< CPU2 Interrupt Mask on line 42 */
-#define EXTI_C2IMR2_IM43_Pos     (11U)
-#define EXTI_C2IMR2_IM43_Msk     (0x1UL << EXTI_C2IMR2_IM43_Pos)               /*!< 0x00000800 */
-#define EXTI_C2IMR2_IM43         EXTI_C2IMR2_IM43_Msk                          /*!< CPU2 Interrupt Mask on line 43 */
-#define EXTI_C2IMR2_IM44_Pos     (12U)
-#define EXTI_C2IMR2_IM44_Msk     (0x1UL << EXTI_C2IMR2_IM44_Pos)               /*!< 0x00001000 */
-#define EXTI_C2IMR2_IM44         EXTI_C2IMR2_IM44_Msk                          /*!< CPU2 Interrupt Mask on line 44 */
-#define EXTI_C2IMR2_IM45_Pos     (13U)
-#define EXTI_C2IMR2_IM45_Msk     (0x1UL << EXTI_C2IMR2_IM45_Pos)               /*!< 0x00002000 */
-#define EXTI_C2IMR2_IM45         EXTI_C2IMR2_IM45_Msk                          /*!< CPU2 Interrupt Mask on line 45 */
-#define EXTI_C2IMR2_IM46_Pos     (14U)
-#define EXTI_C2IMR2_IM46_Msk     (0x1UL << EXTI_C2IMR2_IM46_Pos)               /*!< 0x00004000 */
-#define EXTI_C2IMR2_IM46         EXTI_C2IMR2_IM46_Msk                          /*!< CPU2 Interrupt Mask on line 46 */
-
-/********************  Bits definition for EXTI_C2EMR2 register  **************/
-#define EXTI_C2EMR2_EM40_Pos     (8U)
-#define EXTI_C2EMR2_EM40_Msk     (0x1UL << EXTI_C2EMR2_EM40_Pos)               /*!< 0x00000100 */
-#define EXTI_C2EMR2_EM40         EXTI_C2EMR2_EM40_Msk                          /*!< CPU2 Event Mask on line 40 */
-#define EXTI_C2EMR2_EM41_Pos     (9U)
-#define EXTI_C2EMR2_EM41_Msk     (0x1UL << EXTI_C2EMR2_EM41_Pos)               /*!< 0x00000200 */
-#define EXTI_C2EMR2_EM41         EXTI_C2EMR2_EM41_Msk                          /*!< CPU2 Event Mask on line 41 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Global Security Control                            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for registers x = 0  ********************/
-#define GTZC_CFGR1_TZIC_Pos                 (0U)
-#define GTZC_CFGR1_TZIC_Msk                 (0x01UL << GTZC_CFGR1_TZIC_Pos)     /*!< 0x00000001 */
-#define GTZC_CFGR1_TZSC_Pos                 (1U)
-#define GTZC_CFGR1_TZSC_Msk                 (0x01UL << GTZC_CFGR1_TZSC_Pos)     /*!< 0x00000002 */
-#define GTZC_CFGR1_AES_Pos                  (2U)
-#define GTZC_CFGR1_AES_Msk                  (0x01UL << GTZC_CFGR1_AES_Pos)      /*!< 0x00000004 */
-#define GTZC_CFGR1_RNG_Pos                  (3U)
-#define GTZC_CFGR1_RNG_Msk                  (0x01UL << GTZC_CFGR1_RNG_Pos)      /*!< 0x00000008 */
-#define GTZC_CFGR1_SUBGHZSPI_Pos            (4U)
-#define GTZC_CFGR1_SUBGHZSPI_Msk            (0x01UL << GTZC_CFGR1_SUBGHZSPI_Pos)/*!< 0x00000010 */
-#define GTZC_CFGR1_PWR_Pos                  (5U)
-#define GTZC_CFGR1_PWR_Msk                  (0x01UL << GTZC_CFGR1_PWR_Pos)      /*!< 0x00000020 */
-#define GTZC_CFGR1_FLASHIF_Pos              (6U)
-#define GTZC_CFGR1_FLASHIF_Msk              (0x01UL << GTZC_CFGR1_FLASHIF_Pos)  /*!< 0x00000040 */
-#define GTZC_CFGR1_DMA1_Pos                 (7U)
-#define GTZC_CFGR1_DMA1_Msk                 (0x01UL << GTZC_CFGR1_DMA1_Pos)     /*!< 0x00000080 */
-#define GTZC_CFGR1_DMA2_Pos                 (8U)
-#define GTZC_CFGR1_DMA2_Msk                 (0x01UL << GTZC_CFGR1_DMA2_Pos)     /*!< 0x00000100 */
-#define GTZC_CFGR1_DMAMUX_Pos               (9U)
-#define GTZC_CFGR1_DMAMUX_Msk               (0x01UL << GTZC_CFGR1_DMAMUX_Pos)   /*!< 0x00000200 */
-#define GTZC_CFGR1_FLASH_Pos                (10U)
-#define GTZC_CFGR1_FLASH_Msk                (0x01UL << GTZC_CFGR1_FLASH_Pos)    /*!< 0x00000400 */
-#define GTZC_CFGR1_SRAM1_Pos                (11U)
-#define GTZC_CFGR1_SRAM1_Msk                (0x01UL << GTZC_CFGR1_SRAM1_Pos)    /*!< 0x00000800 */
-#define GTZC_CFGR1_SRAM2_Pos                (12U)
-#define GTZC_CFGR1_SRAM2_Msk                (0x01UL << GTZC_CFGR1_SRAM2_Pos)    /*!< 0x00001000 */
-#define GTZC_CFGR1_PKA_Pos                  (13U)
-#define GTZC_CFGR1_PKA_Msk                  (0x01UL << GTZC_CFGR1_PKA_Pos)      /*!< 0x00002000 */
-
-/*******************  Bits definition for TZSC_CR register  *******************/
-#define TZSC_CR_LCK_Pos                     (0U)
-#define TZSC_CR_LCK_Msk                     (0x01UL << TZSC_CR_LCK_Pos)         /*!< 0x00000001 */
-
-/*******************  Bits definition for TZSC_SECCFGR1 register  *************/
-#define TZSC_SECCFGR1_ALL_Pos               (0U)
-#define TZSC_SECCFGR1_ALL_Msk               (0x0000200CU)                       /*!< 0x0000200C */
-#define TZSC_SECCFGR1_AESSEC_Pos            GTZC_CFGR1_AES_Pos                  /*!< AES Secure enable */
-#define TZSC_SECCFGR1_AESSEC_Msk            GTZC_CFGR1_AES_Msk                  /*!< 0x00000001 */
-#define TZSC_SECCFGR1_RNGSEC_Pos            GTZC_CFGR1_RNG_Pos                  /*!< RNG Secure enable */
-#define TZSC_SECCFGR1_RNGSEC_Msk            GTZC_CFGR1_RNG_Msk                  /*!< 0x00000002 */
-#define TZSC_SECCFGR1_PKASEC_Pos            GTZC_CFGR1_PKA_Pos                  /*!< PKA Secure enable */
-#define TZSC_SECCFGR1_PKASEC_Msk            GTZC_CFGR1_PKA_Msk                  /*!< 0x00000008 */
-
-/*******************  Bits definition for TZSC_PRIVCFGR1 register  ************/
-#define TZSC_PRIVCFGR1_ALL_Pos              (0U)
-#define TZSC_PRIVCFGR1_ALL_Msk              (0x0000201CU)                       /*!< 0x0000201C */
-#define TZSC_PRIVCFGR1_AESPRIV_Pos          GTZC_CFGR1_AES_Pos                  /*!< AES Privileged enable */
-#define TZSC_PRIVCFGR1_AESPRIV_Msk          GTZC_CFGR1_AES_Msk                  /*!< 0x00000001 */
-#define TZSC_PRIVCFGR1_RNGPRIV_Pos          GTZC_CFGR1_RNG_Pos                  /*!< RNG Privileged enable */
-#define TZSC_PRIVCFGR1_RNGPRIV_Msk          GTZC_CFGR1_RNG_Msk                  /*!< 0x00000002 */
-#define TZSC_PRIVCFGR1_SUBGHZSPIPRIV_Pos    GTZC_CFGR1_SUBGHZSPI_Pos            /*!< SUBGHZSPI Privileged enable */
-#define TZSC_PRIVCFGR1_SUBGHZSPIPRIV_Msk    GTZC_CFGR1_SUBGHZSPI_Msk            /*!< 0x00000004 */
-#define TZSC_PRIVCFGR1_PKAPRIV_Pos          GTZC_CFGR1_PKA_Pos                  /*!< PKA Privileged enable */
-#define TZSC_PRIVCFGR1_PKAPRIV_Msk          GTZC_CFGR1_PKA_Msk                  /*!< 0x00000008 */
-
-/*******************  Bits definition for TZSC_MPCWM1_UPWMR register  *********/
-#define TZSC_MPCWM1_UPWMR_LGTH_Pos          (16U)                                     /*!< User Flash Unprivileged area */
-#define TZSC_MPCWM1_UPWMR_LGTH_Msk          (0x0FFFUL << TZSC_MPCWM1_UPWMR_LGTH_Pos)  /*!< 0x0FFF0000 */
-
-/*******************  Bits definition for TZSC_MPCWM1_UPWWMR register  ********/
-#define TZSC_MPCWM1_UPWWMR_LGTH_Pos         (16U)                                     /*!< User Flash Flash Unprivileged Writable area */
-#define TZSC_MPCWM1_UPWWMR_LGTH_Msk         (0x0FFFUL << TZSC_MPCWM1_UPWWMR_LGTH_Pos) /*!< 0x0FFF0000 */
-
-/*******************  Bits definition for TZSC_MPCWM2_UPWMR register  *********/
-#define TZSC_MPCWM2_UPWMR_LGTH_Pos          (16U)                                     /*!< User SRAM1 Unprivileged area */
-#define TZSC_MPCWM2_UPWMR_LGTH_Msk          (0x0FFFUL << TZSC_MPCWM2_UPWMR_LGTH_Pos)  /*!< 0x0FFF0000 */
-
-/*******************  Bits definition for TZSC_MPCWM3_UPWMR register  *********/
-#define TZSC_MPCWM3_UPWMR_LGTH_Pos          (16U)                                     /*!< User Flash Unprivileged area */
-#define TZSC_MPCWM3_UPWMR_LGTH_Msk          (0x0FFFUL << TZSC_MPCWM3_UPWMR_LGTH_Pos)  /*!< 0x0FFF0000 */
-
-
-/*******************  Bits definition for TZIC_IMR0 register  *****************/
-#define TZIC_IER1_ALL_Msk                   0x00003FFFu
-#define TZIC_IER1_TZICIE_Pos                GTZC_CFGR1_TZIC_Pos
-#define TZIC_IER1_TZICIE_Msk                GTZC_CFGR1_TZIC_Msk                  /*!< 0x00000001 */
-#define TZIC_IER1_TZSCIE_Pos                GTZC_CFGR1_TZSC_Pos
-#define TZIC_IER1_TZSCIE_Msk                GTZC_CFGR1_TZSC_Msk                  /*!< 0x00000002 */
-#define TZIC_IER1_AESIE_Pos                 GTZC_CFGR1_AES_Pos
-#define TZIC_IER1_AESIE_Msk                 GTZC_CFGR1_AES_Msk                   /*!< 0x00000004 */
-#define TZIC_IER1_RNGIE_Pos                 GTZC_CFGR1_RNG_Pos
-#define TZIC_IER1_RNGIE_Msk                 GTZC_CFGR1_RNG_Msk                   /*!< 0x00000008 */
-#define TZIC_IER1_SUBGHZSPIIE_Pos           GTZC_CFGR1_SUBGHZSPI_Pos
-#define TZIC_IER1_SUBGHZSPIIE_Msk           GTZC_CFGR1_SUBGHZSPI_Msk             /*!< 0x00000010 */
-#define TZIC_IER1_PWRIE_Pos                 GTZC_CFGR1_PWR_Pos
-#define TZIC_IER1_PWRIE_Msk                 GTZC_CFGR1_PWR_Msk                   /*!< 0x00000020 */
-#define TZIC_IER1_FLASHIFIE_Pos             GTZC_CFGR1_FLASHIF_Pos
-#define TZIC_IER1_FLASHIFIE_Msk             GTZC_CFGR1_FLASHIF_Msk               /*!< 0x00000040 */
-#define TZIC_IER1_DMA1IE_Pos                GTZC_CFGR1_DMA1_Pos
-#define TZIC_IER1_DMA1IE_Msk                GTZC_CFGR1_DMA1_Msk                  /*!< 0x00000080 */
-#define TZIC_IER1_DMA2IE_Pos                GTZC_CFGR1_DMA2_Pos
-#define TZIC_IER1_DMA2IE_Msk                GTZC_CFGR1_DMA2_Msk                  /*!< 0x00000100 */
-#define TZIC_IER1_DMAMUXIE_Pos              GTZC_CFGR1_DMAMUX_Pos
-#define TZIC_IER1_DMAMUXIE_Msk              GTZC_CFGR1_DMAMUX_Msk                /*!< 0x00000200 */
-#define TZIC_IER1_FLASHIE_Pos               GTZC_CFGR1_FLASH_Pos
-#define TZIC_IER1_FLASHIE_Msk               GTZC_CFGR1_FLASH_Msk                 /*!< 0x00000400 */
-#define TZIC_IER1_SRAM1IE_Pos               GTZC_CFGR1_SRAM1_Pos
-#define TZIC_IER1_SRAM1IE_Msk               GTZC_CFGR1_SRAM1_Msk                 /*!< 0x00000800 */
-#define TZIC_IER1_SRAM2IE_Pos               GTZC_CFGR1_SRAM2_Pos
-#define TZIC_IER1_SRAM2IE_Msk               GTZC_CFGR1_SRAM2_Msk                 /*!< 0x00001000 */
-#define TZIC_IER1_PKAIE_Pos                 GTZC_CFGR1_PKA_Pos
-#define TZIC_IER1_PKAIE_Msk                 GTZC_CFGR1_PKA_Msk                   /*!< 0x00002000 */
-
-/*******************  Bits definition for TZIC_MISR1 register  ****************/
-#define TZIC_MISR1_TZICMF_Pos               GTZC_CFGR1_TZIC_Pos
-#define TZIC_MISR1_TZICMF_Msk               GTZC_CFGR1_TZIC_Msk                  /*!< 0x00000001 */
-#define TZIC_MISR1_TZSCMF_Pos               GTZC_CFGR1_TZSC_Pos
-#define TZIC_MISR1_TZSCMF_Msk               GTZC_CFGR1_TZSC_Msk                  /*!< 0x00000002 */
-#define TZIC_MISR1_AESMF_Pos                GTZC_CFGR1_AES_Pos
-#define TZIC_MISR1_AESMF_Msk                GTZC_CFGR1_AES_Msk                   /*!< 0x00000004 */
-#define TZIC_MISR1_RNGMF_Pos                GTZC_CFGR1_RNG_Pos
-#define TZIC_MISR1_RNGMF_Msk                GTZC_CFGR1_RNG_Msk                   /*!< 0x00000008 */
-#define TZIC_MISR1_SUBGHZSPIMF_Pos          GTZC_CFGR1_SUBGHZSPI_Pos
-#define TZIC_MISR1_SUBGHZSPIMF_Msk          GTZC_CFGR1_SUBGHZSPI_Msk             /*!< 0x00000010 */
-#define TZIC_MISR1_PWRMF_Pos                GTZC_CFGR1_PWR_Pos
-#define TZIC_MISR1_PWRMF_Msk                GTZC_CFGR1_PWR_Msk                   /*!< 0x00000020 */
-#define TZIC_MISR1_FLASHIFMF_Pos            GTZC_CFGR1_FLASHIF_Pos
-#define TZIC_MISR1_FLASHIFMF_Msk            GTZC_CFGR1_FLASHIF_Msk               /*!< 0x00000040 */
-#define TZIC_MISR1_DMA1MF_Pos               GTZC_CFGR1_DMA1_Pos
-#define TZIC_MISR1_DMA1MF_Msk               GTZC_CFGR1_DMA1_Msk                  /*!< 0x00000080 */
-#define TZIC_MISR1_DMA2MF_Pos               GTZC_CFGR1_DMA2_Pos
-#define TZIC_MISR1_DMA2MF_Msk               GTZC_CFGR1_DMA2_Msk                  /*!< 0x00000100 */
-#define TZIC_MISR1_DMAMUXMF_Pos             GTZC_CFGR1_DMAMUX_Pos
-#define TZIC_MISR1_DMAMUXMF_Msk             GTZC_CFGR1_DMAMUX_Msk                /*!< 0x00000200 */
-#define TZIC_MISR1_FLASHMF_Pos              GTZC_CFGR1_FLASH_Pos
-#define TZIC_MISR1_FLASHMF_Msk              GTZC_CFGR1_FLASH_Msk                 /*!< 0x00000400 */
-#define TZIC_MISR1_SRAM1MF_Pos              GTZC_CFGR1_SRAM1_Pos
-#define TZIC_MISR1_SRAM1MF_Msk              GTZC_CFGR1_SRAM1_Msk                 /*!< 0x00000800 */
-#define TZIC_MISR1_SRAM2MF_Pos              GTZC_CFGR1_SRAM2_Pos
-#define TZIC_MISR1_SRAM2MF_Msk              GTZC_CFGR1_SRAM2_Msk                 /*!< 0x00001000 */
-#define TZIC_MISR1_PKAMF_Pos                GTZC_CFGR1_PKA_Pos
-#define TZIC_MISR1_PKAMF_Msk                GTZC_CFGR1_PKA_Msk                   /*!< 0x00002000 */
-
-/*******************  Bits definition for TZIC_IFCR0 register  ****************/
-#define TZIC_ICR1_TZICCF_Pos                GTZC_CFGR1_TZIC_Pos
-#define TZIC_ICR1_TZICCF_Msk                GTZC_CFGR1_TZIC_Msk                  /*!< 0x00000001 */
-#define TZIC_ICR1_TZSCCF_Pos                GTZC_CFGR1_TZSC_Pos
-#define TZIC_ICR1_TZSCCF_Msk                GTZC_CFGR1_TZSC_Msk                  /*!< 0x00000002 */
-#define TZIC_ICR1_AESCF_Pos                 GTZC_CFGR1_AES_Pos
-#define TZIC_ICR1_AESCF_Msk                 GTZC_CFGR1_AES_Msk                   /*!< 0x00000004 */
-#define TZIC_ICR1_RNGCF_Pos                 GTZC_CFGR1_RNG_Pos
-#define TZIC_ICR1_RNGCF_Msk                 GTZC_CFGR1_RNG_Msk                   /*!< 0x00000008 */
-#define TZIC_ICR1_SUBGHZSPICF_Pos           GTZC_CFGR1_SUBGHZSPI_Pos
-#define TZIC_ICR1_SUBGHZSPICF_Msk           GTZC_CFGR1_SUBGHZSPI_Msk             /*!< 0x00000010 */
-#define TZIC_ICR1_PWRCF_Pos                 GTZC_CFGR1_PWR_Pos
-#define TZIC_ICR1_PWRCF_Msk                 GTZC_CFGR1_PWR_Msk                   /*!< 0x00000020 */
-#define TZIC_ICR1_FLASHIFCF_Pos             GTZC_CFGR1_FLASHIF_Pos
-#define TZIC_ICR1_FLASHIFCF_Msk             GTZC_CFGR1_FLASHIF_Msk               /*!< 0x00000040 */
-#define TZIC_ICR1_DMA1CF_Pos                GTZC_CFGR1_DMA1_Pos
-#define TZIC_ICR1_DMA1CF_Msk                GTZC_CFGR1_DMA1_Msk                  /*!< 0x00000080 */
-#define TZIC_ICR1_DMA2CF_Pos                GTZC_CFGR1_DMA2_Pos
-#define TZIC_ICR1_DMA2CF_Msk                GTZC_CFGR1_DMA2_Msk                  /*!< 0x00000100 */
-#define TZIC_ICR1_DMAMUXCF_Pos              GTZC_CFGR1_DMAMUX_Pos
-#define TZIC_ICR1_DMAMUXCF_Msk              GTZC_CFGR1_DMAMUX_Msk                /*!< 0x00000200 */
-#define TZIC_ICR1_FLASHCF_Pos               GTZC_CFGR1_FLASH_Pos
-#define TZIC_ICR1_FLASHCF_Msk               GTZC_CFGR1_FLASH_Msk                 /*!< 0x00000400 */
-#define TZIC_ICR1_SRAM1CF_Pos               GTZC_CFGR1_SRAM1_Pos
-#define TZIC_ICR1_SRAM1CF_Msk               GTZC_CFGR1_SRAM1_Msk                 /*!< 0x00000800 */
-#define TZIC_ICR1_SRAM2CF_Pos               GTZC_CFGR1_SRAM2_Pos
-#define TZIC_ICR1_SRAM2CF_Msk               GTZC_CFGR1_SRAM2_Msk                 /*!< 0x00001000 */
-#define TZIC_ICR1_PKACF_Pos                 GTZC_CFGR1_PKA_Pos
-#define TZIC_ICR1_PKACF_Msk                 GTZC_CFGR1_PKA_Msk                   /*!< 0x00002000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY_Pos               (0U)
-#define FLASH_ACR_LATENCY_Msk               (0x7UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000007 */
-#define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk              /*!< Latency                                             */
-#define FLASH_ACR_LATENCY_0                 (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY_1                 (0x2UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN_Pos                (8U)
-#define FLASH_ACR_PRFTEN_Msk                (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000100 */
-#define FLASH_ACR_PRFTEN                    FLASH_ACR_PRFTEN_Msk               /*!< Prefetch enable                                     */
-#define FLASH_ACR_ICEN_Pos                  (9U)
-#define FLASH_ACR_ICEN_Msk                  (0x1UL << FLASH_ACR_ICEN_Pos)      /*!< 0x00000200 */
-#define FLASH_ACR_ICEN                      FLASH_ACR_ICEN_Msk                 /*!< Instruction cache enable                            */
-#define FLASH_ACR_DCEN_Pos                  (10U)
-#define FLASH_ACR_DCEN_Msk                  (0x1UL << FLASH_ACR_DCEN_Pos)      /*!< 0x00000400 */
-#define FLASH_ACR_DCEN                      FLASH_ACR_DCEN_Msk                 /*!< Data cache enable                                   */
-#define FLASH_ACR_ICRST_Pos                 (11U)
-#define FLASH_ACR_ICRST_Msk                 (0x1UL << FLASH_ACR_ICRST_Pos)     /*!< 0x00000800 */
-#define FLASH_ACR_ICRST                     FLASH_ACR_ICRST_Msk                /*!< Instruction cache reset                             */
-#define FLASH_ACR_DCRST_Pos                 (12U)
-#define FLASH_ACR_DCRST_Msk                 (0x1UL << FLASH_ACR_DCRST_Pos)     /*!< 0x00001000 */
-#define FLASH_ACR_DCRST                     FLASH_ACR_DCRST_Msk                /*!< Data cache reset                                    */
-#define FLASH_ACR_PES_Pos                   (15U)
-#define FLASH_ACR_PES_Msk                   (0x1UL << FLASH_ACR_PES_Pos)       /*!< 0x00008000 */
-#define FLASH_ACR_PES                       FLASH_ACR_PES_Msk                  /*!< Program/erase suspend request                       */
-#define FLASH_ACR_EMPTY_Pos                 (16U)
-#define FLASH_ACR_EMPTY_Msk                 (0x1UL << FLASH_ACR_EMPTY_Pos)     /*!< 0x00010000 */
-#define FLASH_ACR_EMPTY                     FLASH_ACR_EMPTY_Msk                /*!< Flash use area empty                                */
-
-/*******************  Bits definition for FLASH_ACR2 register  ****************/
-#define FLASH_ACR2_PRIVMODE_Pos             (0U)
-#define FLASH_ACR2_PRIVMODE_Msk             (0x1UL << FLASH_ACR2_PRIVMODE_Pos) /*!< 0x00000001 */
-#define FLASH_ACR2_PRIVMODE                 FLASH_ACR2_PRIVMODE_Msk            /*!< CFI privileged mode                                 */
-#define FLASH_ACR2_HDPADIS_Pos              (1U)
-#define FLASH_ACR2_HDPADIS_Msk              (0x1UL << FLASH_ACR2_HDPADIS_Pos)    /*!< 0x00000002 */
-#define FLASH_ACR2_HDPADIS                  FLASH_ACR2_HDPADIS_Msk               /*!< Flash User Hide Protection area access disable    */
-#define FLASH_ACR2_C2SWDBGEN_Pos            (2U)
-#define FLASH_ACR2_C2SWDBGEN_Msk            (0x1UL << FLASH_ACR2_C2SWDBGEN_Pos)/*!< 0x00000004 */
-#define FLASH_ACR2_C2SWDBGEN                FLASH_ACR2_C2SWDBGEN_Msk           /*!< CPU2 Software debug enable                          */
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP_Pos                    (0U)
-#define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                   /*!< End of Operation                                    */
-#define FLASH_SR_OPERR_Pos                  (1U)
-#define FLASH_SR_OPERR_Msk                  (0x1UL << FLASH_SR_OPERR_Pos)      /*!< 0x00000002 */
-#define FLASH_SR_OPERR                      FLASH_SR_OPERR_Msk                 /*!< Operation error                                     */
-#define FLASH_SR_PROGERR_Pos                (3U)
-#define FLASH_SR_PROGERR_Msk                (0x1UL << FLASH_SR_PROGERR_Pos)    /*!< 0x00000008 */
-#define FLASH_SR_PROGERR                    FLASH_SR_PROGERR_Msk               /*!< Programming error                                   */
-#define FLASH_SR_WRPERR_Pos                 (4U)
-#define FLASH_SR_WRPERR_Msk                 (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000010 */
-#define FLASH_SR_WRPERR                     FLASH_SR_WRPERR_Msk                /*!< Write protection error                              */
-#define FLASH_SR_PGAERR_Pos                 (5U)
-#define FLASH_SR_PGAERR_Msk                 (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000020 */
-#define FLASH_SR_PGAERR                     FLASH_SR_PGAERR_Msk                /*!< Programming alignment error                         */
-#define FLASH_SR_SIZERR_Pos                 (6U)
-#define FLASH_SR_SIZERR_Msk                 (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000040 */
-#define FLASH_SR_SIZERR                     FLASH_SR_SIZERR_Msk                /*!< Size error                                          */
-#define FLASH_SR_PGSERR_Pos                 (7U)
-#define FLASH_SR_PGSERR_Msk                 (0x1UL << FLASH_SR_PGSERR_Pos)     /*!< 0x00000080 */
-#define FLASH_SR_PGSERR                     FLASH_SR_PGSERR_Msk                /*!< Programming sequence error                          */
-#define FLASH_SR_MISERR_Pos                 (8U)
-#define FLASH_SR_MISERR_Msk                 (0x1UL << FLASH_SR_MISERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_MISERR                     FLASH_SR_MISERR_Msk                /*!< Fast programming data miss error                    */
-#define FLASH_SR_FASTERR_Pos                (9U)
-#define FLASH_SR_FASTERR_Msk                (0x1UL << FLASH_SR_FASTERR_Pos)    /*!< 0x00000200 */
-#define FLASH_SR_FASTERR                    FLASH_SR_FASTERR_Msk               /*!< Fast programming error                              */
-#define FLASH_SR_OPTNV_Pos                  (13U)
-#define FLASH_SR_OPTNV_Msk                  (0x1UL << FLASH_SR_OPTNV_Pos)     /*!< 0x00002000 */
-#define FLASH_SR_OPTNV                      FLASH_SR_OPTNV_Msk                /*!< User option OPTVAL indication                       */
-#define FLASH_SR_RDERR_Pos                  (14U)
-#define FLASH_SR_RDERR_Msk                  (0x1UL << FLASH_SR_RDERR_Pos)      /*!< 0x00004000 */
-#define FLASH_SR_RDERR                      FLASH_SR_RDERR_Msk                 /*!< PCROP read error                                    */
-#define FLASH_SR_OPTVERR_Pos                (15U)
-#define FLASH_SR_OPTVERR_Msk                (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00008000 */
-#define FLASH_SR_OPTVERR                    FLASH_SR_OPTVERR_Msk               /*!< Option validity error                               */
-#define FLASH_SR_BSY_Pos                    (16U)
-#define FLASH_SR_BSY_Msk                    (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00010000 */
-#define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                   /*!< Flash Busy                                          */
-#define FLASH_SR_CFGBSY_Pos                 (18U)
-#define FLASH_SR_CFGBSY_Msk                 (0x1UL << FLASH_SR_CFGBSY_Pos)     /*!< 0x00040000 */
-#define FLASH_SR_CFGBSY                     FLASH_SR_CFGBSY_Msk                /*!< Programming or erase configuration busy             */
-#define FLASH_SR_PESD_Pos                   (19U)
-#define FLASH_SR_PESD_Msk                   (0x1UL << FLASH_SR_PESD_Pos)       /*!< 0x00080000 */
-#define FLASH_SR_PESD                       FLASH_SR_PESD_Msk                  /*!< Programming/erase operation suspended               */
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG_Pos                     (0U)
-#define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)         /*!< 0x00000001 */
-#define FLASH_CR_PG                         FLASH_CR_PG_Msk                    /*!< Flash programming                                   */
-#define FLASH_CR_PER_Pos                    (1U)
-#define FLASH_CR_PER_Msk                    (0x1UL << FLASH_CR_PER_Pos)        /*!< 0x00000002 */
-#define FLASH_CR_PER                        FLASH_CR_PER_Msk                   /*!< Page erase                                          */
-#define FLASH_CR_MER_Pos                    (2U)
-#define FLASH_CR_MER_Msk                    (0x1UL << FLASH_CR_MER_Pos)        /*!< 0x00000004 */
-#define FLASH_CR_MER                        FLASH_CR_MER_Msk                   /*!< Mass erase                                          */
-#define FLASH_CR_PNB_Pos                    (3U)
-#define FLASH_CR_PNB_Msk                    (0x7FUL << FLASH_CR_PNB_Pos)       /*!< 0x000003F8 */
-#define FLASH_CR_PNB                        FLASH_CR_PNB_Msk                   /*!< Page number selection mask                          */
-#define FLASH_CR_STRT_Pos                   (16U)
-#define FLASH_CR_STRT_Msk                   (0x1UL << FLASH_CR_STRT_Pos)       /*!< 0x00010000 */
-#define FLASH_CR_STRT                       FLASH_CR_STRT_Msk                  /*!< Start an erase operation                            */
-#define FLASH_CR_OPTSTRT_Pos                (17U)
-#define FLASH_CR_OPTSTRT_Msk                (0x1UL << FLASH_CR_OPTSTRT_Pos)    /*!< 0x00020000 */
-#define FLASH_CR_OPTSTRT                    FLASH_CR_OPTSTRT_Msk               /*!< Options modification start                          */
-#define FLASH_CR_FSTPG_Pos                  (18U)
-#define FLASH_CR_FSTPG_Msk                  (0x1UL << FLASH_CR_FSTPG_Pos)      /*!< 0x00040000 */
-#define FLASH_CR_FSTPG                      FLASH_CR_FSTPG_Msk                 /*!< Fast programming                                    */
-#define FLASH_CR_EOPIE_Pos                  (24U)
-#define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)      /*!< 0x01000000 */
-#define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                 /*!< End of operation interrupt enable                   */
-#define FLASH_CR_ERRIE_Pos                  (25U)
-#define FLASH_CR_ERRIE_Msk                  (0x1UL << FLASH_CR_ERRIE_Pos)      /*!< 0x02000000 */
-#define FLASH_CR_ERRIE                      FLASH_CR_ERRIE_Msk                 /*!< Error interrupt enable                              */
-#define FLASH_CR_RDERRIE_Pos                (26U)
-#define FLASH_CR_RDERRIE_Msk                (0x1UL << FLASH_CR_RDERRIE_Pos)    /*!< 0x04000000 */
-#define FLASH_CR_RDERRIE                    FLASH_CR_RDERRIE_Msk               /*!< PCROP read error interrupt enable                   */
-#define FLASH_CR_OBL_LAUNCH_Pos             (27U)
-#define FLASH_CR_OBL_LAUNCH_Msk             (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
-#define FLASH_CR_OBL_LAUNCH                 FLASH_CR_OBL_LAUNCH_Msk            /*!< Force the option bute loading                       */
-#define FLASH_CR_OPTLOCK_Pos                (30U)
-#define FLASH_CR_OPTLOCK_Msk                (0x1UL << FLASH_CR_OPTLOCK_Pos)    /*!< 0x40000000 */
-#define FLASH_CR_OPTLOCK                    FLASH_CR_OPTLOCK_Msk               /*!< Options lock                                        */
-#define FLASH_CR_LOCK_Pos                   (31U)
-#define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)       /*!< 0x80000000 */
-#define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                  /*!< Flash control register lock                         */
-
-/*******************  Bits definition for FLASH_ECCR register  ****************/
-#define FLASH_ECCR_ADDR_ECC_Pos             (0U)
-#define FLASH_ECCR_ADDR_ECC_Msk             (0x1FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0001FFFF */
-#define FLASH_ECCR_ADDR_ECC                 FLASH_ECCR_ADDR_ECC_Msk            /*!< double-word address ECC fail                        */
-#define FLASH_ECCR_SYSF_ECC_Pos             (20U)
-#define FLASH_ECCR_SYSF_ECC_Msk             (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
-#define FLASH_ECCR_SYSF_ECC                 FLASH_ECCR_SYSF_ECC_Msk            /*!< System flash ECC fail                               */
-#define FLASH_ECCR_ECCCIE_Pos               (24U)
-#define FLASH_ECCR_ECCCIE_Msk               (0x1UL << FLASH_ECCR_ECCCIE_Pos)   /*!< 0x01000000 */
-#define FLASH_ECCR_ECCCIE                   FLASH_ECCR_ECCCIE_Msk              /*!< ECC correction interrupt enable                     */
-#define FLASH_ECCR_CPUID_Pos                (26U)
-#define FLASH_ECCR_CPUID_Msk                (0x7UL << FLASH_ECCR_CPUID_Pos)    /*!< 0x1C000000 */
-#define FLASH_ECCR_CPUID                    FLASH_ECCR_CPUID_Msk               /*!< CPU identification                                  */
-#define FLASH_ECCR_ECCC_Pos                 (30U)
-#define FLASH_ECCR_ECCC_Msk                 (0x1UL << FLASH_ECCR_ECCC_Pos)     /*!< 0x40000000 */
-#define FLASH_ECCR_ECCC                     FLASH_ECCR_ECCC_Msk                /*!< ECC correction                                      */
-#define FLASH_ECCR_ECCD_Pos                 (31U)
-#define FLASH_ECCR_ECCD_Msk                 (0x1UL << FLASH_ECCR_ECCD_Pos)     /*!< 0x80000000 */
-#define FLASH_ECCR_ECCD                     FLASH_ECCR_ECCD_Msk                /*!< ECC detection                                       */
-
-/*******************  Bits definition for FLASH_OPTR register  ****************/
-#define FLASH_OPTR_RDP_Pos                  (0U)
-#define FLASH_OPTR_RDP_Msk                  (0xFFUL << FLASH_OPTR_RDP_Pos)     /*!< 0x000000FF */
-#define FLASH_OPTR_RDP                      FLASH_OPTR_RDP_Msk                 /*!< Read protection level                               */
-#define FLASH_OPTR_ESE_Pos                  (8U)
-#define FLASH_OPTR_ESE_Msk                  (0x1UL << FLASH_OPTR_ESE_Pos)      /*!< 0x00000100 */
-#define FLASH_OPTR_ESE                      FLASH_OPTR_ESE_Msk                 /*!< Security enable                                     */
-#define FLASH_OPTR_BOR_LEV_Pos              (9U)
-#define FLASH_OPTR_BOR_LEV_Msk              (0x7UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000E00 */
-#define FLASH_OPTR_BOR_LEV                  FLASH_OPTR_BOR_LEV_Msk             /*!< BOR reset level mask                                */
-#define FLASH_OPTR_BOR_LEV_0                (0x1UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000200 */
-#define FLASH_OPTR_BOR_LEV_1                (0x2UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000400 */
-#define FLASH_OPTR_BOR_LEV_2                (0x4UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000800 */
-#define FLASH_OPTR_nRST_STOP_Pos            (12U)
-#define FLASH_OPTR_nRST_STOP_Msk            (0x1UL << FLASH_OPTR_nRST_STOP_Pos)/*!< 0x00001000 */
-#define FLASH_OPTR_nRST_STOP                FLASH_OPTR_nRST_STOP_Msk           /*!< Reset option in Stop mode                           */
-#define FLASH_OPTR_nRST_STDBY_Pos           (13U)
-#define FLASH_OPTR_nRST_STDBY_Msk           (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)/*!< 0x00002000 */
-#define FLASH_OPTR_nRST_STDBY               FLASH_OPTR_nRST_STDBY_Msk          /*!< Reset option in Standby mode                        */
-#define FLASH_OPTR_nRST_SHDW_Pos            (14U)
-#define FLASH_OPTR_nRST_SHDW_Msk            (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)/*!< 0x00004000 */
-#define FLASH_OPTR_nRST_SHDW                FLASH_OPTR_nRST_SHDW_Msk           /*!< Reset option in Shutdown mode                       */
-#define FLASH_OPTR_IWDG_SW_Pos              (16U)
-#define FLASH_OPTR_IWDG_SW_Msk              (0x1UL << FLASH_OPTR_IWDG_SW_Pos)  /*!< 0x00010000 */
-#define FLASH_OPTR_IWDG_SW                  FLASH_OPTR_IWDG_SW_Msk             /*!< Independent watchdog selection                      */
-#define FLASH_OPTR_IWDG_STOP_Pos            (17U)
-#define FLASH_OPTR_IWDG_STOP_Msk            (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)/*!< 0x00020000 */
-#define FLASH_OPTR_IWDG_STOP                FLASH_OPTR_IWDG_STOP_Msk           /*!< Independent watchdog counter option in Stop mode    */
-#define FLASH_OPTR_IWDG_STDBY_Pos           (18U)
-#define FLASH_OPTR_IWDG_STDBY_Msk           (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)/*!< 0x00040000 */
-#define FLASH_OPTR_IWDG_STDBY               FLASH_OPTR_IWDG_STDBY_Msk          /*!< Independent watchdog counter option in Standby mode */
-#define FLASH_OPTR_WWDG_SW_Pos              (19U)
-#define FLASH_OPTR_WWDG_SW_Msk              (0x1UL << FLASH_OPTR_WWDG_SW_Pos)  /*!< 0x00080000 */
-#define FLASH_OPTR_WWDG_SW                  FLASH_OPTR_WWDG_SW_Msk             /*!< Window watchdog selection                           */
-#define FLASH_OPTR_nBOOT1_Pos               (23U)
-#define FLASH_OPTR_nBOOT1_Msk               (0x1UL << FLASH_OPTR_nBOOT1_Pos)   /*!< 0x00800000 */
-#define FLASH_OPTR_nBOOT1                   FLASH_OPTR_nBOOT1_Msk              /*!< Boot Configuration                                  */
-#define FLASH_OPTR_SRAM2_PE_Pos             (24U)
-#define FLASH_OPTR_SRAM2_PE_Msk             (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
-#define FLASH_OPTR_SRAM2_PE                 FLASH_OPTR_SRAM2_PE_Msk            /*!< SRAM2 parity check enable                           */
-#define FLASH_OPTR_SRAM_RST_Pos             (25U)
-#define FLASH_OPTR_SRAM_RST_Msk             (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x02000000 */
-#define FLASH_OPTR_SRAM_RST                 FLASH_OPTR_SRAM_RST_Msk            /*!< SRAM1 and SRAM2 erase option when system reset      */
-#define FLASH_OPTR_nSWBOOT0_Pos             (26U)
-#define FLASH_OPTR_nSWBOOT0_Msk             (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
-#define FLASH_OPTR_nSWBOOT0                 FLASH_OPTR_nSWBOOT0_Msk            /*!< Software BOOT0                                      */
-#define FLASH_OPTR_nBOOT0_Pos               (27U)
-#define FLASH_OPTR_nBOOT0_Msk               (0x1UL << FLASH_OPTR_nBOOT0_Pos)   /*!< 0x08000000 */
-#define FLASH_OPTR_nBOOT0                   FLASH_OPTR_nBOOT0_Msk              /*!< BOOT0 option bit                                    */
-#define FLASH_OPTR_BOOT_LOCK_Pos            (30U)
-#define FLASH_OPTR_BOOT_LOCK_Msk            (0x1UL << FLASH_OPTR_BOOT_LOCK_Pos)/*!< 0x40000000 */
-#define FLASH_OPTR_BOOT_LOCK                FLASH_OPTR_BOOT_LOCK_Msk           /*!< CPU1 Boot Lock enable option bit                    */
-#define FLASH_OPTR_C2BOOT_LOCK_Pos          (31U)
-#define FLASH_OPTR_C2BOOT_LOCK_Msk          (0x1UL << FLASH_OPTR_C2BOOT_LOCK_Pos)/*!< 0x80000000 */
-#define FLASH_OPTR_C2BOOT_LOCK              FLASH_OPTR_C2BOOT_LOCK_Msk           /*!< CPU2 Boot Lock enable option bit                  */
-
-/******************  Bits definition for FLASH_PCROP1ASR register  ************/
-#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos    (0U)
-#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk    (0xFFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1ASR_PCROP1A_STRT        FLASH_PCROP1ASR_PCROP1A_STRT_Msk   /*!< PCROP area A start offset                           */
-
-/******************  Bits definition for FLASH_PCROP1AER register  ************/
-#define FLASH_PCROP1AER_PCROP1A_END_Pos     (0U)
-#define FLASH_PCROP1AER_PCROP1A_END_Msk     (0xFFUL << FLASH_PCROP1AER_PCROP1A_END_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1AER_PCROP1A_END         FLASH_PCROP1AER_PCROP1A_END_Msk    /*!< PCROP area A end offset                             */
-#define FLASH_PCROP1AER_PCROP_RDP_Pos       (31U)
-#define FLASH_PCROP1AER_PCROP_RDP_Msk       (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos)/*!< 0x80000000 */
-#define FLASH_PCROP1AER_PCROP_RDP           FLASH_PCROP1AER_PCROP_RDP_Msk      /*!< PCROP area preserved when RDP level decreased       */
-
-/******************  Bits definition for FLASH_WRP1AR register  ***************/
-#define FLASH_WRP1AR_WRP1A_STRT_Pos         (0U)
-#define FLASH_WRP1AR_WRP1A_STRT_Msk         (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
-#define FLASH_WRP1AR_WRP1A_STRT             FLASH_WRP1AR_WRP1A_STRT_Msk        /*!< WRP area A start offset                             */
-#define FLASH_WRP1AR_WRP1A_END_Pos          (16U)
-#define FLASH_WRP1AR_WRP1A_END_Msk          (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
-#define FLASH_WRP1AR_WRP1A_END              FLASH_WRP1AR_WRP1A_END_Msk         /*!< WRP area A end offset                               */
-
-/******************  Bits definition for FLASH_WRP1BR register  ***************/
-#define FLASH_WRP1BR_WRP1B_STRT_Pos         (0U)
-#define FLASH_WRP1BR_WRP1B_STRT_Msk         (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
-#define FLASH_WRP1BR_WRP1B_STRT             FLASH_WRP1BR_WRP1B_STRT_Msk        /*!< WRP area B start offset                             */
-#define FLASH_WRP1BR_WRP1B_END_Pos          (16U)
-#define FLASH_WRP1BR_WRP1B_END_Msk          (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
-#define FLASH_WRP1BR_WRP1B_END              FLASH_WRP1BR_WRP1B_END_Msk         /*!< WRP area B end offset                               */
-
-/******************  Bits definition for FLASH_PCROP1BSR register  ************/
-#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos    (0U)
-#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk    (0xFFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1BSR_PCROP1B_STRT        FLASH_PCROP1BSR_PCROP1B_STRT_Msk   /*!< PCROP area B start offset                           */
-
-/******************  Bits definition for FLASH_PCROP1BER register  ************/
-#define FLASH_PCROP1BER_PCROP1B_END_Pos     (0U)
-#define FLASH_PCROP1BER_PCROP1B_END_Msk     (0xFFUL << FLASH_PCROP1BER_PCROP1B_END_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1BER_PCROP1B_END         FLASH_PCROP1BER_PCROP1B_END_Msk    /*!< PCROP area B end offset                             */
-
-/******************  Bits definition for FLASH_IPCCBR register  ************/
-#define FLASH_IPCCBR_IPCCDBA_Pos            (0U)
-#define FLASH_IPCCBR_IPCCDBA_Msk            (0x3FFFUL << FLASH_IPCCBR_IPCCDBA_Pos)/*!< 0x00003FFF */
-#define FLASH_IPCCBR_IPCCDBA                FLASH_IPCCBR_IPCCDBA_Msk           /*!< IPCC data buffer base address                       */
-
-/******************  Bits definition for FLASH_C2ACR register  ************/
-#define FLASH_C2ACR_PRFTEN_Pos              (8U)
-#define FLASH_C2ACR_PRFTEN_Msk              (0x1UL << FLASH_C2ACR_PRFTEN_Pos) /*!< 0x00000100 */
-#define FLASH_C2ACR_PRFTEN                  FLASH_C2ACR_PRFTEN_Msk            /*!< CPU2 Prefetch enable                                 */
-#define FLASH_C2ACR_ICEN_Pos                (9U)
-#define FLASH_C2ACR_ICEN_Msk                (0x1UL << FLASH_C2ACR_ICEN_Pos)   /*!< 0x00000200 */
-#define FLASH_C2ACR_ICEN                    FLASH_C2ACR_ICEN_Msk              /*!< CPU2 Instruction cache enable                        */
-#define FLASH_C2ACR_ICRST_Pos               (11U)
-#define FLASH_C2ACR_ICRST_Msk               (0x1UL << FLASH_C2ACR_ICRST_Pos)  /*!< 0x00000800 */
-#define FLASH_C2ACR_ICRST                   FLASH_C2ACR_ICRST_Msk             /*!< CPU2 Instruction cache reset                         */
-#define FLASH_C2ACR_PES_Pos                 (15U)
-#define FLASH_C2ACR_PES_Msk                 (0x1UL << FLASH_C2ACR_PES_Pos)    /*!< 0x00008000 */
-#define FLASH_C2ACR_PES                     FLASH_C2ACR_PES_Msk               /*!< CPU2 Program/erase suspend request                   */
-
-/******************  Bits definition for FLASH_C2SR register  ************/
-#define FLASH_C2SR_EOP_Pos                  (0U)
-#define FLASH_C2SR_EOP_Msk                  (0x1UL << FLASH_C2SR_EOP_Pos)     /*!< 0x00000001 */
-#define FLASH_C2SR_EOP                      FLASH_C2SR_EOP_Msk                /*!< CPU2 End of operation                                */
-#define FLASH_C2SR_OPERR_Pos                (1U)
-#define FLASH_C2SR_OPERR_Msk                (0x1UL << FLASH_C2SR_OPERR_Pos)   /*!< 0x00000002 */
-#define FLASH_C2SR_OPERR                    FLASH_C2SR_OPERR_Msk              /*!< CPU2 Operation error                                 */
-#define FLASH_C2SR_PROGERR_Pos              (3U)
-#define FLASH_C2SR_PROGERR_Msk              (0x1UL << FLASH_C2SR_PROGERR_Pos) /*!< 0x00000008 */
-#define FLASH_C2SR_PROGERR                  FLASH_C2SR_PROGERR_Msk            /*!< CPU2 Programming error                               */
-#define FLASH_C2SR_WRPERR_Pos               (4U)
-#define FLASH_C2SR_WRPERR_Msk               (0x1UL << FLASH_C2SR_WRPERR_Pos)  /*!< 0x00000010 */
-#define FLASH_C2SR_WRPERR                   FLASH_C2SR_WRPERR_Msk             /*!< CPU2 Write protection error                          */
-#define FLASH_C2SR_PGAERR_Pos               (5U)
-#define FLASH_C2SR_PGAERR_Msk               (0x1UL << FLASH_C2SR_PGAERR_Pos)  /*!< 0x00000020 */
-#define FLASH_C2SR_PGAERR                   FLASH_C2SR_PGAERR_Msk             /*!< CPU2 Programming alignment error                     */
-#define FLASH_C2SR_SIZERR_Pos               (6U)
-#define FLASH_C2SR_SIZERR_Msk               (0x1UL << FLASH_C2SR_SIZERR_Pos)  /*!< 0x00000040 */
-#define FLASH_C2SR_SIZERR                   FLASH_C2SR_SIZERR_Msk             /*!< CPU2 Size error                                      */
-#define FLASH_C2SR_PGSERR_Pos               (7U)
-#define FLASH_C2SR_PGSERR_Msk               (0x1UL << FLASH_C2SR_PGSERR_Pos)  /*!< 0x00000080 */
-#define FLASH_C2SR_PGSERR                   FLASH_C2SR_PGSERR_Msk             /*!< CPU2 Programming sequence error                      */
-#define FLASH_C2SR_MISERR_Pos               (8U)
-#define FLASH_C2SR_MISERR_Msk               (0x1UL << FLASH_C2SR_MISERR_Pos)  /*!< 0x00000100 */
-#define FLASH_C2SR_MISERR                   FLASH_C2SR_MISERR_Msk             /*!< CPU2 Fast programming data miss error                */
-#define FLASH_C2SR_FASTERR_Pos              (9U)
-#define FLASH_C2SR_FASTERR_Msk              (0x1UL << FLASH_C2SR_FASTERR_Pos) /*!< 0x00000200 */
-#define FLASH_C2SR_FASTERR                  FLASH_C2SR_FASTERR_Msk            /*!< CPU2 Fast programming error                          */
-#define FLASH_C2SR_RDERR_Pos                (14U)
-#define FLASH_C2SR_RDERR_Msk                (0x1UL << FLASH_C2SR_RDERR_Pos)   /*!< 0x00004000 */
-#define FLASH_C2SR_RDERR                    FLASH_C2SR_RDERR_Msk              /*!< CPU2 PCROP read error                                */
-#define FLASH_C2SR_BSY_Pos                  (16U)
-#define FLASH_C2SR_BSY_Msk                  (0x1UL << FLASH_C2SR_BSY_Pos)     /*!< 0x00010000 */
-#define FLASH_C2SR_BSY                      FLASH_C2SR_BSY_Msk                /*!< CPU2 Flash busy                                      */
-#define FLASH_C2SR_CFGBSY_Pos               (18U)
-#define FLASH_C2SR_CFGBSY_Msk               (0x1UL << FLASH_C2SR_CFGBSY_Pos)  /*!< 0x00040000 */
-#define FLASH_C2SR_CFGBSY                   FLASH_C2SR_CFGBSY_Msk             /*!< CPU2 Programming or erase configuration busy         */
-#define FLASH_C2SR_PESD_Pos                 (19U)
-#define FLASH_C2SR_PESD_Msk                 (0x1UL << FLASH_C2SR_PESD_Pos)    /*!< 0x00080000 */
-#define FLASH_C2SR_PESD                     FLASH_C2SR_PESD_Msk               /*!< CPU2 Programming/erase operation suspended           */
-
-/******************  Bits definition for FLASH_C2CR register  ************/
-#define FLASH_C2CR_PG_Pos                   (0U)
-#define FLASH_C2CR_PG_Msk                   (0x1UL << FLASH_C2CR_PG_Pos)      /*!< 0x00000001 */
-#define FLASH_C2CR_PG                       FLASH_C2CR_PG_Msk                 /*!< CPU2 Flash programming                               */
-#define FLASH_C2CR_PER_Pos                  (1U)
-#define FLASH_C2CR_PER_Msk                  (0x1UL << FLASH_C2CR_PER_Pos)     /*!< 0x00000002 */
-#define FLASH_C2CR_PER                      FLASH_C2CR_PER_Msk                /*!< CPU2 Page erase                                      */
-#define FLASH_C2CR_MER_Pos                  (2U)
-#define FLASH_C2CR_MER_Msk                  (0x1UL << FLASH_C2CR_MER_Pos)     /*!< 0x00000004 */
-#define FLASH_C2CR_MER                      FLASH_C2CR_MER_Msk                /*!< CPU2 Mass erase                                      */
-#define FLASH_C2CR_PNB_Pos                  (3U)
-#define FLASH_C2CR_PNB_Msk                  (0xFFUL << FLASH_C2CR_PNB_Pos)    /*!< 0x000007F8 */
-#define FLASH_C2CR_PNB                      FLASH_C2CR_PNB_Msk                /*!< CPU2 Page number selection mask                      */
-#define FLASH_C2CR_STRT_Pos                 (16U)
-#define FLASH_C2CR_STRT_Msk                 (0x1UL << FLASH_C2CR_STRT_Pos)    /*!< 0x00010000 */
-#define FLASH_C2CR_STRT                     FLASH_C2CR_STRT_Msk               /*!< CPU2 Start an erase operation                        */
-#define FLASH_C2CR_FSTPG_Pos                (18U)
-#define FLASH_C2CR_FSTPG_Msk                (0x1UL << FLASH_C2CR_FSTPG_Pos)   /*!< 0x00040000 */
-#define FLASH_C2CR_FSTPG                    FLASH_C2CR_FSTPG_Msk              /*!< CPU2 Fast programming                                */
-#define FLASH_C2CR_EOPIE_Pos                (24U)
-#define FLASH_C2CR_EOPIE_Msk                (0x1UL << FLASH_C2CR_EOPIE_Pos)   /*!< 0x01000000 */
-#define FLASH_C2CR_EOPIE                    FLASH_C2CR_EOPIE_Msk              /*!< CPU2 End of operation interrupt enable               */
-#define FLASH_C2CR_ERRIE_Pos                (25U)
-#define FLASH_C2CR_ERRIE_Msk                (0x1UL << FLASH_C2CR_ERRIE_Pos)   /*!< 0x02000000 */
-#define FLASH_C2CR_ERRIE                    FLASH_C2CR_ERRIE_Msk              /*!< CPU2 Error interrupt enable                          */
-#define FLASH_C2CR_RDERRIE_Pos              (26U)
-#define FLASH_C2CR_RDERRIE_Msk              (0x1UL << FLASH_C2CR_RDERRIE_Pos) /*!< 0x04000000 */
-#define FLASH_C2CR_RDERRIE                  FLASH_C2CR_RDERRIE_Msk            /*!< CPU2 PCROP read error interrupt enable               */
-
-/******************  Bits definition for FLASH_SFR register  ************/
-#define FLASH_SFR_SFSA_Pos                  (0U)
-#define FLASH_SFR_SFSA_Msk                  (0x7FUL << FLASH_SFR_SFSA_Pos)     /*!< 0x0000007F */
-#define FLASH_SFR_SFSA                      FLASH_SFR_SFSA_Msk                 /* Secure flash start address                            */
-#define FLASH_SFR_FSD_Pos                   (7U)
-#define FLASH_SFR_FSD_Msk                   (0x1UL << FLASH_SFR_FSD_Pos)       /*!< 0x00000080 */
-#define FLASH_SFR_FSD                       FLASH_SFR_FSD_Msk                  /* Flash mode secure                                     */
-#define FLASH_SFR_DDS_Pos                   (12U)
-#define FLASH_SFR_DDS_Msk                   (0x1UL << FLASH_SFR_DDS_Pos)       /*!< 0x00001000 */
-#define FLASH_SFR_DDS                       FLASH_SFR_DDS_Msk                  /* Enabling and disabling CPU2 Debug access              */
-#define FLASH_SFR_HDPSA_Pos                 (16U)
-#define FLASH_SFR_HDPSA_Msk                 (0x7FUL << FLASH_SFR_HDPSA_Pos)    /*!< 0x007F0000 */
-#define FLASH_SFR_HDPSA                     FLASH_SFR_HDPSA_Msk                /*!< User Flash Hide Protection Area start address*/
-#define FLASH_SFR_HDPAD_Pos                 (23U)
-#define FLASH_SFR_HDPAD_Msk                 (0x1UL << FLASH_SFR_HDPAD_Pos)     /*!< 0x00800000 */
-#define FLASH_SFR_HDPAD                     FLASH_SFR_HDPAD_Msk                /* User Flash Hide Protection Area disabled       */
-#define FLASH_SFR_SUBGHZSPISD_Pos           (31U)
-#define FLASH_SFR_SUBGHZSPISD_Msk           (0x1UL << FLASH_SFR_SUBGHZSPISD_Pos)  /*!< 0x80000000 */
-#define FLASH_SFR_SUBGHZSPISD               FLASH_SFR_SUBGHZSPISD_Msk             /* Sub-GHz radio SPI security disable                 */
-
-/******************  Bits definition for FLASH_SRRVR register  ************/
-#define FLASH_SRRVR_SBRV_Pos                (0U)
-#define FLASH_SRRVR_SBRV_Msk                (0xFFFFUL << FLASH_SRRVR_SBRV_Pos)  /*!< 0x0000FFFF */
-#define FLASH_SRRVR_SBRV                    FLASH_SRRVR_SBRV_Msk                /* SCPU2 boot reset vector memory offset                */
-
-#define FLASH_SRRVR_SBRSA_Pos               (18U)
-#define FLASH_SRRVR_SBRSA_Msk               (0x1FUL << FLASH_SRRVR_SBRSA_Pos)   /*!< 0x007C0000 */
-#define FLASH_SRRVR_SBRSA                   FLASH_SRRVR_SBRSA_Msk               /* Secure backup SRAM2 start address                    */
-#define FLASH_SRRVR_BRSD_Pos                (23U)
-#define FLASH_SRRVR_BRSD_Msk                (0x1UL << FLASH_SRRVR_BRSD_Pos)     /*!< 0x00800000 */
-#define FLASH_SRRVR_BRSD                    FLASH_SRRVR_BRSD_Msk                /* Backup SRAM2 secure mode                             */
-
-#define FLASH_SRRVR_SNBRSA_Pos              (25U)
-#define FLASH_SRRVR_SNBRSA_Msk              (0x1FUL << FLASH_SRRVR_SNBRSA_Pos)  /*!< 0x3E000000 */
-#define FLASH_SRRVR_SNBRSA                  FLASH_SRRVR_SNBRSA_Msk              /* Secure non-backup SRAM1 start address                */
-#define FLASH_SRRVR_NBRSD_Pos               (30U)
-#define FLASH_SRRVR_NBRSD_Msk               (0x1UL << FLASH_SRRVR_NBRSD_Pos)    /*!< 0x40000000 */
-#define FLASH_SRRVR_NBRSD                   FLASH_SRRVR_NBRSD_Msk               /* Non-backup SRAM1 secure mode                         */
-#define FLASH_SRRVR_C2OPT_Pos               (31U)
-#define FLASH_SRRVR_C2OPT_Msk               (0x1UL << FLASH_SRRVR_C2OPT_Pos)    /*!< 0x80000000 */
-#define FLASH_SRRVR_C2OPT                   FLASH_SRRVR_C2OPT_Msk               /* SCPU2 boot reset vector memory selection             */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos           (0U)
-#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
-#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos           (2U)
-#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
-#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos           (4U)
-#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
-#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos           (6U)
-#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
-#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos           (8U)
-#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
-#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos           (10U)
-#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
-#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos           (12U)
-#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
-#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos           (14U)
-#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
-#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos           (16U)
-#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
-#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos           (18U)
-#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
-#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos          (20U)
-#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
-#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos          (22U)
-#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
-#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos          (24U)
-#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
-#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos          (26U)
-#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
-#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos          (28U)
-#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
-#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos          (30U)
-#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
-#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT0_Pos            (0U)
-#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
-#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
-#define GPIO_OTYPER_OT1_Pos            (1U)
-#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
-#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
-#define GPIO_OTYPER_OT2_Pos            (2U)
-#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
-#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
-#define GPIO_OTYPER_OT3_Pos            (3U)
-#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
-#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
-#define GPIO_OTYPER_OT4_Pos            (4U)
-#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
-#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
-#define GPIO_OTYPER_OT5_Pos            (5U)
-#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
-#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
-#define GPIO_OTYPER_OT6_Pos            (6U)
-#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
-#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
-#define GPIO_OTYPER_OT7_Pos            (7U)
-#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
-#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
-#define GPIO_OTYPER_OT8_Pos            (8U)
-#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
-#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
-#define GPIO_OTYPER_OT9_Pos            (9U)
-#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
-#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
-#define GPIO_OTYPER_OT10_Pos           (10U)
-#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
-#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
-#define GPIO_OTYPER_OT11_Pos           (11U)
-#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
-#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
-#define GPIO_OTYPER_OT12_Pos           (12U)
-#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
-#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
-#define GPIO_OTYPER_OT13_Pos           (13U)
-#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
-#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
-#define GPIO_OTYPER_OT14_Pos           (14U)
-#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
-#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
-#define GPIO_OTYPER_OT15_Pos           (15U)
-#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
-#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
-#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
-#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
-#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
-#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
-#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
-#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
-#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
-#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
-#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
-#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
-#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
-#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
-#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
-#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
-#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
-#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
-#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
-#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
-#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
-#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
-#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
-#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
-#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
-#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
-#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
-#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
-#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
-#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
-#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
-#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
-#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
-#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
-#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
-#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
-#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
-#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
-#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
-#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
-#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
-#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
-#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
-#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
-#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
-#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
-#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
-#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
-#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
-#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
-#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
-#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
-#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
-#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
-#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
-#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
-#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
-#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
-#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
-#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
-#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
-#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
-#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
-#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
-#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
-#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
-#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
-#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
-#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
-#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
-#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
-#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
-#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
-#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
-#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
-#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
-#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
-#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
-#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
-#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
-#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPD0_Pos           (0U)
-#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
-#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos           (2U)
-#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
-#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos           (4U)
-#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
-#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos           (6U)
-#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
-#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos           (8U)
-#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
-#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos           (10U)
-#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
-#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos           (12U)
-#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
-#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos           (14U)
-#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
-#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos           (16U)
-#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
-#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos           (18U)
-#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
-#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos          (20U)
-#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
-#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos          (22U)
-#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
-#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos          (24U)
-#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
-#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos          (26U)
-#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
-#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos          (28U)
-#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
-#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos          (30U)
-#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
-#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos               (0U)
-#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
-#define GPIO_IDR_ID1_Pos               (1U)
-#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
-#define GPIO_IDR_ID2_Pos               (2U)
-#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
-#define GPIO_IDR_ID3_Pos               (3U)
-#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
-#define GPIO_IDR_ID4_Pos               (4U)
-#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
-#define GPIO_IDR_ID5_Pos               (5U)
-#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
-#define GPIO_IDR_ID6_Pos               (6U)
-#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
-#define GPIO_IDR_ID7_Pos               (7U)
-#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
-#define GPIO_IDR_ID8_Pos               (8U)
-#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
-#define GPIO_IDR_ID9_Pos               (9U)
-#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
-#define GPIO_IDR_ID10_Pos              (10U)
-#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
-#define GPIO_IDR_ID11_Pos              (11U)
-#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
-#define GPIO_IDR_ID12_Pos              (12U)
-#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
-#define GPIO_IDR_ID13_Pos              (13U)
-#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
-#define GPIO_IDR_ID14_Pos              (14U)
-#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
-#define GPIO_IDR_ID15_Pos              (15U)
-#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_OD0_Pos               (0U)
-#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
-#define GPIO_ODR_OD1_Pos               (1U)
-#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
-#define GPIO_ODR_OD2_Pos               (2U)
-#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
-#define GPIO_ODR_OD3_Pos               (3U)
-#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
-#define GPIO_ODR_OD4_Pos               (4U)
-#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
-#define GPIO_ODR_OD5_Pos               (5U)
-#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
-#define GPIO_ODR_OD6_Pos               (6U)
-#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
-#define GPIO_ODR_OD7_Pos               (7U)
-#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
-#define GPIO_ODR_OD8_Pos               (8U)
-#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
-#define GPIO_ODR_OD9_Pos               (9U)
-#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
-#define GPIO_ODR_OD10_Pos              (10U)
-#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
-#define GPIO_ODR_OD11_Pos              (11U)
-#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
-#define GPIO_ODR_OD12_Pos              (12U)
-#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
-#define GPIO_ODR_OD13_Pos              (13U)
-#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
-#define GPIO_ODR_OD14_Pos              (14U)
-#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
-#define GPIO_ODR_OD15_Pos              (15U)
-#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS0_Pos              (0U)
-#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
-#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
-#define GPIO_BSRR_BS1_Pos              (1U)
-#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
-#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
-#define GPIO_BSRR_BS2_Pos              (2U)
-#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
-#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
-#define GPIO_BSRR_BS3_Pos              (3U)
-#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
-#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
-#define GPIO_BSRR_BS4_Pos              (4U)
-#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
-#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
-#define GPIO_BSRR_BS5_Pos              (5U)
-#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
-#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
-#define GPIO_BSRR_BS6_Pos              (6U)
-#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
-#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
-#define GPIO_BSRR_BS7_Pos              (7U)
-#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
-#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
-#define GPIO_BSRR_BS8_Pos              (8U)
-#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
-#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
-#define GPIO_BSRR_BS9_Pos              (9U)
-#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
-#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
-#define GPIO_BSRR_BS10_Pos             (10U)
-#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
-#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
-#define GPIO_BSRR_BS11_Pos             (11U)
-#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
-#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
-#define GPIO_BSRR_BS12_Pos             (12U)
-#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
-#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
-#define GPIO_BSRR_BS13_Pos             (13U)
-#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
-#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
-#define GPIO_BSRR_BS14_Pos             (14U)
-#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
-#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
-#define GPIO_BSRR_BS15_Pos             (15U)
-#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
-#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
-#define GPIO_BSRR_BR0_Pos              (16U)
-#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
-#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
-#define GPIO_BSRR_BR1_Pos              (17U)
-#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
-#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
-#define GPIO_BSRR_BR2_Pos              (18U)
-#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
-#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
-#define GPIO_BSRR_BR3_Pos              (19U)
-#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
-#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
-#define GPIO_BSRR_BR4_Pos              (20U)
-#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
-#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
-#define GPIO_BSRR_BR5_Pos              (21U)
-#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
-#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
-#define GPIO_BSRR_BR6_Pos              (22U)
-#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
-#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
-#define GPIO_BSRR_BR7_Pos              (23U)
-#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
-#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
-#define GPIO_BSRR_BR8_Pos              (24U)
-#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
-#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
-#define GPIO_BSRR_BR9_Pos              (25U)
-#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
-#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
-#define GPIO_BSRR_BR10_Pos             (26U)
-#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
-#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
-#define GPIO_BSRR_BR11_Pos             (27U)
-#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
-#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
-#define GPIO_BSRR_BR12_Pos             (28U)
-#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
-#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
-#define GPIO_BSRR_BR13_Pos             (29U)
-#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
-#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
-#define GPIO_BSRR_BR14_Pos             (30U)
-#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
-#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
-#define GPIO_BSRR_BR15_Pos             (31U)
-#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
-#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0_Pos             (0U)
-#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
-#define GPIO_LCKR_LCK1_Pos             (1U)
-#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
-#define GPIO_LCKR_LCK2_Pos             (2U)
-#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
-#define GPIO_LCKR_LCK3_Pos             (3U)
-#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
-#define GPIO_LCKR_LCK4_Pos             (4U)
-#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
-#define GPIO_LCKR_LCK5_Pos             (5U)
-#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
-#define GPIO_LCKR_LCK6_Pos             (6U)
-#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
-#define GPIO_LCKR_LCK7_Pos             (7U)
-#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
-#define GPIO_LCKR_LCK8_Pos             (8U)
-#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
-#define GPIO_LCKR_LCK9_Pos             (9U)
-#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
-#define GPIO_LCKR_LCK10_Pos            (10U)
-#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
-#define GPIO_LCKR_LCK11_Pos            (11U)
-#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
-#define GPIO_LCKR_LCK12_Pos            (12U)
-#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
-#define GPIO_LCKR_LCK13_Pos            (13U)
-#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
-#define GPIO_LCKR_LCK14_Pos            (14U)
-#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
-#define GPIO_LCKR_LCK15_Pos            (15U)
-#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
-#define GPIO_LCKR_LCKK_Pos             (16U)
-#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
-
-/****************** Bit definition for GPIO_AFRL register *********************/
-#define GPIO_AFRL_AFSEL0_Pos           (0U)
-#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
-#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
-#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
-#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
-#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
-#define GPIO_AFRL_AFSEL1_Pos           (4U)
-#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
-#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
-#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
-#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
-#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
-#define GPIO_AFRL_AFSEL2_Pos           (8U)
-#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
-#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
-#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
-#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
-#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
-#define GPIO_AFRL_AFSEL3_Pos           (12U)
-#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
-#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
-#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
-#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
-#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
-#define GPIO_AFRL_AFSEL4_Pos           (16U)
-#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
-#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
-#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
-#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
-#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
-#define GPIO_AFRL_AFSEL5_Pos           (20U)
-#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
-#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
-#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
-#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
-#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
-#define GPIO_AFRL_AFSEL6_Pos           (24U)
-#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
-#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
-#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
-#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
-#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
-#define GPIO_AFRL_AFSEL7_Pos           (28U)
-#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
-#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
-#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
-#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
-#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
-
-/****************** Bit definition for GPIO_AFRH register *********************/
-#define GPIO_AFRH_AFSEL8_Pos           (0U)
-#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
-#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
-#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
-#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
-#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
-#define GPIO_AFRH_AFSEL9_Pos           (4U)
-#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
-#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
-#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
-#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
-#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
-#define GPIO_AFRH_AFSEL10_Pos          (8U)
-#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
-#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
-#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
-#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
-#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
-#define GPIO_AFRH_AFSEL11_Pos          (12U)
-#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
-#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
-#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
-#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
-#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
-#define GPIO_AFRH_AFSEL12_Pos          (16U)
-#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
-#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
-#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
-#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
-#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
-#define GPIO_AFRH_AFSEL13_Pos          (20U)
-#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
-#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
-#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
-#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
-#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
-#define GPIO_AFRH_AFSEL14_Pos          (24U)
-#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
-#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
-#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
-#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
-#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
-#define GPIO_AFRH_AFSEL15_Pos          (28U)
-#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
-#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
-#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
-#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
-#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_BRR register  ******************/
-#define GPIO_BRR_BR0_Pos               (0U)
-#define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
-#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
-#define GPIO_BRR_BR1_Pos               (1U)
-#define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
-#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
-#define GPIO_BRR_BR2_Pos               (2U)
-#define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
-#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
-#define GPIO_BRR_BR3_Pos               (3U)
-#define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
-#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
-#define GPIO_BRR_BR4_Pos               (4U)
-#define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
-#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
-#define GPIO_BRR_BR5_Pos               (5U)
-#define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
-#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
-#define GPIO_BRR_BR6_Pos               (6U)
-#define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
-#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
-#define GPIO_BRR_BR7_Pos               (7U)
-#define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
-#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
-#define GPIO_BRR_BR8_Pos               (8U)
-#define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
-#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
-#define GPIO_BRR_BR9_Pos               (9U)
-#define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
-#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
-#define GPIO_BRR_BR10_Pos              (10U)
-#define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
-#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
-#define GPIO_BRR_BR11_Pos              (11U)
-#define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
-#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
-#define GPIO_BRR_BR12_Pos              (12U)
-#define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
-#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
-#define GPIO_BRR_BR13_Pos              (13U)
-#define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
-#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
-#define GPIO_BRR_BR14_Pos              (14U)
-#define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
-#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
-#define GPIO_BRR_BR15_Pos              (15U)
-#define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
-#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                        HSEM HW Semaphore                                   */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for HSEM_R register  ********************/
-#define HSEM_R_PROCID_Pos        (0U)
-#define HSEM_R_PROCID_Msk        (0xFFUL << HSEM_R_PROCID_Pos)                 /*!< 0x000000FF */
-#define HSEM_R_PROCID            HSEM_R_PROCID_Msk                             /*!<Semaphore ProcessID */
-#define HSEM_R_COREID_Pos        (8U)
-#define HSEM_R_COREID_Msk        (0xFUL << HSEM_R_COREID_Pos)                  /*!< 0x00000F00 */
-#define HSEM_R_COREID            HSEM_R_COREID_Msk                             /*!<Semaphore CoreID. */
-#define HSEM_R_LOCK_Pos          (31U)
-#define HSEM_R_LOCK_Msk          (0x1UL << HSEM_R_LOCK_Pos)                    /*!< 0x80000000 */
-#define HSEM_R_LOCK              HSEM_R_LOCK_Msk                               /*!<Lock indication. */
-
-/********************  Bit definition for HSEM_RLR register  ******************/
-#define HSEM_RLR_PROCID_Pos      (0U)
-#define HSEM_RLR_PROCID_Msk      (0xFFUL << HSEM_RLR_PROCID_Pos)               /*!< 0x000000FF */
-#define HSEM_RLR_PROCID          HSEM_RLR_PROCID_Msk                           /*!<Semaphore ProcessID */
-#define HSEM_RLR_COREID_Pos      (8U)
-#define HSEM_RLR_COREID_Msk      (0xFUL << HSEM_RLR_COREID_Pos)                /*!< 0x00000F00 */
-#define HSEM_RLR_COREID          HSEM_RLR_COREID_Msk                           /*!<Semaphore CoreID. */
-#define HSEM_RLR_LOCK_Pos        (31U)
-#define HSEM_RLR_LOCK_Msk        (0x1UL << HSEM_RLR_LOCK_Pos)                  /*!< 0x80000000 */
-#define HSEM_RLR_LOCK            HSEM_RLR_LOCK_Msk                             /*!<Lock indication. */
-
-/********************  Bit definition for HSEM_C1IER register  ****************/
-#define HSEM_C1IER_ISE0_Pos      (0U)
-#define HSEM_C1IER_ISE0_Msk      (0x1UL << HSEM_C1IER_ISE0_Pos)                /*!< 0x00000001 */
-#define HSEM_C1IER_ISE0          HSEM_C1IER_ISE0_Msk                           /*!<semaphore 0 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE1_Pos      (1U)
-#define HSEM_C1IER_ISE1_Msk      (0x1UL << HSEM_C1IER_ISE1_Pos)                /*!< 0x00000002 */
-#define HSEM_C1IER_ISE1          HSEM_C1IER_ISE1_Msk                           /*!<semaphore 1 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE2_Pos      (2U)
-#define HSEM_C1IER_ISE2_Msk      (0x1UL << HSEM_C1IER_ISE2_Pos)                /*!< 0x00000004 */
-#define HSEM_C1IER_ISE2          HSEM_C1IER_ISE2_Msk                           /*!<semaphore 2 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE3_Pos      (3U)
-#define HSEM_C1IER_ISE3_Msk      (0x1UL << HSEM_C1IER_ISE3_Pos)                /*!< 0x00000008 */
-#define HSEM_C1IER_ISE3          HSEM_C1IER_ISE3_Msk                           /*!<semaphore 3 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE4_Pos      (4U)
-#define HSEM_C1IER_ISE4_Msk      (0x1UL << HSEM_C1IER_ISE4_Pos)                /*!< 0x00000010 */
-#define HSEM_C1IER_ISE4          HSEM_C1IER_ISE4_Msk                           /*!<semaphore 4 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE5_Pos      (5U)
-#define HSEM_C1IER_ISE5_Msk      (0x1UL << HSEM_C1IER_ISE5_Pos)                /*!< 0x00000020 */
-#define HSEM_C1IER_ISE5          HSEM_C1IER_ISE5_Msk                           /*!<semaphore 5 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE6_Pos      (6U)
-#define HSEM_C1IER_ISE6_Msk      (0x1UL << HSEM_C1IER_ISE6_Pos)                /*!< 0x00000040 */
-#define HSEM_C1IER_ISE6          HSEM_C1IER_ISE6_Msk                           /*!<semaphore 6 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE7_Pos      (7U)
-#define HSEM_C1IER_ISE7_Msk      (0x1UL << HSEM_C1IER_ISE7_Pos)                /*!< 0x00000080 */
-#define HSEM_C1IER_ISE7          HSEM_C1IER_ISE7_Msk                           /*!<semaphore 7 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE8_Pos      (8U)
-#define HSEM_C1IER_ISE8_Msk      (0x1UL << HSEM_C1IER_ISE8_Pos)                /*!< 0x00000100 */
-#define HSEM_C1IER_ISE8          HSEM_C1IER_ISE8_Msk                           /*!<semaphore 8 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE9_Pos      (9U)
-#define HSEM_C1IER_ISE9_Msk      (0x1UL << HSEM_C1IER_ISE9_Pos)                /*!< 0x00000200 */
-#define HSEM_C1IER_ISE9          HSEM_C1IER_ISE9_Msk                           /*!<semaphore 9 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE10_Pos     (10U)
-#define HSEM_C1IER_ISE10_Msk     (0x1UL << HSEM_C1IER_ISE10_Pos)               /*!< 0x00000400 */
-#define HSEM_C1IER_ISE10         HSEM_C1IER_ISE10_Msk                          /*!<semaphore 10 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE11_Pos     (11U)
-#define HSEM_C1IER_ISE11_Msk     (0x1UL << HSEM_C1IER_ISE11_Pos)               /*!< 0x00000800 */
-#define HSEM_C1IER_ISE11         HSEM_C1IER_ISE11_Msk                          /*!<semaphore 11 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE12_Pos     (12U)
-#define HSEM_C1IER_ISE12_Msk     (0x1UL << HSEM_C1IER_ISE12_Pos)               /*!< 0x00001000 */
-#define HSEM_C1IER_ISE12         HSEM_C1IER_ISE12_Msk                          /*!<semaphore 12 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE13_Pos     (13U)
-#define HSEM_C1IER_ISE13_Msk     (0x1UL << HSEM_C1IER_ISE13_Pos)               /*!< 0x00002000 */
-#define HSEM_C1IER_ISE13         HSEM_C1IER_ISE13_Msk                          /*!<semaphore 13 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE14_Pos     (14U)
-#define HSEM_C1IER_ISE14_Msk     (0x1UL << HSEM_C1IER_ISE14_Pos)               /*!< 0x00004000 */
-#define HSEM_C1IER_ISE14         HSEM_C1IER_ISE14_Msk                          /*!<semaphore 14 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE15_Pos     (15U)
-#define HSEM_C1IER_ISE15_Msk     (0x1UL << HSEM_C1IER_ISE15_Pos)               /*!< 0x00008000 */
-#define HSEM_C1IER_ISE15         HSEM_C1IER_ISE15_Msk                          /*!<semaphore 15 CPU1 interrupt enable bit. */
-
-/********************  Bit definition for HSEM_C1ICR register  *****************/
-#define HSEM_C1ICR_ISC0_Pos      (0U)
-#define HSEM_C1ICR_ISC0_Msk      (0x1UL << HSEM_C1ICR_ISC0_Pos)                /*!< 0x00000001 */
-#define HSEM_C1ICR_ISC0          HSEM_C1ICR_ISC0_Msk                           /*!<semaphore 0 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC1_Pos      (1U)
-#define HSEM_C1ICR_ISC1_Msk      (0x1UL << HSEM_C1ICR_ISC1_Pos)                /*!< 0x00000002 */
-#define HSEM_C1ICR_ISC1          HSEM_C1ICR_ISC1_Msk                           /*!<semaphore 1 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC2_Pos      (2U)
-#define HSEM_C1ICR_ISC2_Msk      (0x1UL << HSEM_C1ICR_ISC2_Pos)                /*!< 0x00000004 */
-#define HSEM_C1ICR_ISC2          HSEM_C1ICR_ISC2_Msk                           /*!<semaphore 2 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC3_Pos      (3U)
-#define HSEM_C1ICR_ISC3_Msk      (0x1UL << HSEM_C1ICR_ISC3_Pos)                /*!< 0x00000008 */
-#define HSEM_C1ICR_ISC3          HSEM_C1ICR_ISC3_Msk                           /*!<semaphore 3 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC4_Pos      (4U)
-#define HSEM_C1ICR_ISC4_Msk      (0x1UL << HSEM_C1ICR_ISC4_Pos)                /*!< 0x00000010 */
-#define HSEM_C1ICR_ISC4          HSEM_C1ICR_ISC4_Msk                           /*!<semaphore 4 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC5_Pos      (5U)
-#define HSEM_C1ICR_ISC5_Msk      (0x1UL << HSEM_C1ICR_ISC5_Pos)                /*!< 0x00000020 */
-#define HSEM_C1ICR_ISC5          HSEM_C1ICR_ISC5_Msk                           /*!<semaphore 5 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC6_Pos      (6U)
-#define HSEM_C1ICR_ISC6_Msk      (0x1UL << HSEM_C1ICR_ISC6_Pos)                /*!< 0x00000040 */
-#define HSEM_C1ICR_ISC6          HSEM_C1ICR_ISC6_Msk                           /*!<semaphore 6 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC7_Pos      (7U)
-#define HSEM_C1ICR_ISC7_Msk      (0x1UL << HSEM_C1ICR_ISC7_Pos)                /*!< 0x00000080 */
-#define HSEM_C1ICR_ISC7          HSEM_C1ICR_ISC7_Msk                           /*!<semaphore 7 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC8_Pos      (8U)
-#define HSEM_C1ICR_ISC8_Msk      (0x1UL << HSEM_C1ICR_ISC8_Pos)                /*!< 0x00000100 */
-#define HSEM_C1ICR_ISC8          HSEM_C1ICR_ISC8_Msk                           /*!<semaphore 8 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC9_Pos      (9U)
-#define HSEM_C1ICR_ISC9_Msk      (0x1UL << HSEM_C1ICR_ISC9_Pos)                /*!< 0x00000200 */
-#define HSEM_C1ICR_ISC9          HSEM_C1ICR_ISC9_Msk                           /*!<semaphore 9 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC10_Pos     (10U)
-#define HSEM_C1ICR_ISC10_Msk     (0x1UL << HSEM_C1ICR_ISC10_Pos)               /*!< 0x00000400 */
-#define HSEM_C1ICR_ISC10         HSEM_C1ICR_ISC10_Msk                          /*!<semaphore 10 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC11_Pos     (11U)
-#define HSEM_C1ICR_ISC11_Msk     (0x1UL << HSEM_C1ICR_ISC11_Pos)               /*!< 0x00000800 */
-#define HSEM_C1ICR_ISC11         HSEM_C1ICR_ISC11_Msk                          /*!<semaphore 11 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC12_Pos     (12U)
-#define HSEM_C1ICR_ISC12_Msk     (0x1UL << HSEM_C1ICR_ISC12_Pos)               /*!< 0x00001000 */
-#define HSEM_C1ICR_ISC12         HSEM_C1ICR_ISC12_Msk                          /*!<semaphore 12 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC13_Pos     (13U)
-#define HSEM_C1ICR_ISC13_Msk     (0x1UL << HSEM_C1ICR_ISC13_Pos)               /*!< 0x00002000 */
-#define HSEM_C1ICR_ISC13         HSEM_C1ICR_ISC13_Msk                          /*!<semaphore 13 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC14_Pos     (14U)
-#define HSEM_C1ICR_ISC14_Msk     (0x1UL << HSEM_C1ICR_ISC14_Pos)               /*!< 0x00004000 */
-#define HSEM_C1ICR_ISC14         HSEM_C1ICR_ISC14_Msk                          /*!<semaphore 14 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC15_Pos     (15U)
-#define HSEM_C1ICR_ISC15_Msk     (0x1UL << HSEM_C1ICR_ISC15_Pos)               /*!< 0x00008000 */
-#define HSEM_C1ICR_ISC15         HSEM_C1ICR_ISC15_Msk                          /*!<semaphore 15 CPU1 interrupt clear bit. */
-
-/********************  Bit definition for HSEM_C1ISR register  *****************/
-#define HSEM_C1ISR_ISF0_Pos      (0U)
-#define HSEM_C1ISR_ISF0_Msk      (0x1UL << HSEM_C1ISR_ISF0_Pos)                /*!< 0x00000001 */
-#define HSEM_C1ISR_ISF0          HSEM_C1ISR_ISF0_Msk                           /*!<semaphore 0 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF1_Pos      (1U)
-#define HSEM_C1ISR_ISF1_Msk      (0x1UL << HSEM_C1ISR_ISF1_Pos)                /*!< 0x00000002 */
-#define HSEM_C1ISR_ISF1          HSEM_C1ISR_ISF1_Msk                           /*!<semaphore 1 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF2_Pos      (2U)
-#define HSEM_C1ISR_ISF2_Msk      (0x1UL << HSEM_C1ISR_ISF2_Pos)                /*!< 0x00000004 */
-#define HSEM_C1ISR_ISF2          HSEM_C1ISR_ISF2_Msk                           /*!<semaphore 2 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF3_Pos      (3U)
-#define HSEM_C1ISR_ISF3_Msk      (0x1UL << HSEM_C1ISR_ISF3_Pos)                /*!< 0x00000008 */
-#define HSEM_C1ISR_ISF3          HSEM_C1ISR_ISF3_Msk                           /*!<semaphore 3 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF4_Pos      (4U)
-#define HSEM_C1ISR_ISF4_Msk      (0x1UL << HSEM_C1ISR_ISF4_Pos)                /*!< 0x00000010 */
-#define HSEM_C1ISR_ISF4          HSEM_C1ISR_ISF4_Msk                           /*!<semaphore 4 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF5_Pos      (5U)
-#define HSEM_C1ISR_ISF5_Msk      (0x1UL << HSEM_C1ISR_ISF5_Pos)                /*!< 0x00000020 */
-#define HSEM_C1ISR_ISF5          HSEM_C1ISR_ISF5_Msk                           /*!<semaphore 5 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF6_Pos      (6U)
-#define HSEM_C1ISR_ISF6_Msk      (0x1UL << HSEM_C1ISR_ISF6_Pos)                /*!< 0x00000040 */
-#define HSEM_C1ISR_ISF6          HSEM_C1ISR_ISF6_Msk                           /*!<semaphore 6 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF7_Pos      (7U)
-#define HSEM_C1ISR_ISF7_Msk      (0x1UL << HSEM_C1ISR_ISF7_Pos)                /*!< 0x00000080 */
-#define HSEM_C1ISR_ISF7          HSEM_C1ISR_ISF7_Msk                           /*!<semaphore 7 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF8_Pos      (8U)
-#define HSEM_C1ISR_ISF8_Msk      (0x1UL << HSEM_C1ISR_ISF8_Pos)                /*!< 0x00000100 */
-#define HSEM_C1ISR_ISF8          HSEM_C1ISR_ISF8_Msk                           /*!<semaphore 8 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF9_Pos      (9U)
-#define HSEM_C1ISR_ISF9_Msk      (0x1UL << HSEM_C1ISR_ISF9_Pos)                /*!< 0x00000200 */
-#define HSEM_C1ISR_ISF9          HSEM_C1ISR_ISF9_Msk                           /*!<semaphore 9 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF10_Pos     (10U)
-#define HSEM_C1ISR_ISF10_Msk     (0x1UL << HSEM_C1ISR_ISF10_Pos)               /*!< 0x00000400 */
-#define HSEM_C1ISR_ISF10         HSEM_C1ISR_ISF10_Msk                          /*!<semaphore 10 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF11_Pos     (11U)
-#define HSEM_C1ISR_ISF11_Msk     (0x1UL << HSEM_C1ISR_ISF11_Pos)               /*!< 0x00000800 */
-#define HSEM_C1ISR_ISF11         HSEM_C1ISR_ISF11_Msk                          /*!<semaphore 11 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF12_Pos     (12U)
-#define HSEM_C1ISR_ISF12_Msk     (0x1UL << HSEM_C1ISR_ISF12_Pos)               /*!< 0x00001000 */
-#define HSEM_C1ISR_ISF12         HSEM_C1ISR_ISF12_Msk                          /*!<semaphore 12 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF13_Pos     (13U)
-#define HSEM_C1ISR_ISF13_Msk     (0x1UL << HSEM_C1ISR_ISF13_Pos)               /*!< 0x00002000 */
-#define HSEM_C1ISR_ISF13         HSEM_C1ISR_ISF13_Msk                          /*!<semaphore 13 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF14_Pos     (14U)
-#define HSEM_C1ISR_ISF14_Msk     (0x1UL << HSEM_C1ISR_ISF14_Pos)               /*!< 0x00004000 */
-#define HSEM_C1ISR_ISF14         HSEM_C1ISR_ISF14_Msk                          /*!<semaphore 14 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF15_Pos     (15U)
-#define HSEM_C1ISR_ISF15_Msk     (0x1UL << HSEM_C1ISR_ISF15_Pos)               /*!< 0x00008000 */
-#define HSEM_C1ISR_ISF15         HSEM_C1ISR_ISF15_Msk                          /*!<semaphore 15 CPU1 interrupt status bit. */
-
-/********************  Bit definition for HSEM_C1MISR register  *****************/
-#define HSEM_C1MISR_MISF0_Pos     (0U)
-#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)               /*!< 0x00000001 */
-#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                          /*!<semaphore 0 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF1_Pos     (1U)
-#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)               /*!< 0x00000002 */
-#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                          /*!<semaphore 1 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF2_Pos     (2U)
-#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)               /*!< 0x00000004 */
-#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                          /*!<semaphore 2 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF3_Pos     (3U)
-#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)               /*!< 0x00000008 */
-#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                          /*!<semaphore 3 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF4_Pos     (4U)
-#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)               /*!< 0x00000010 */
-#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                          /*!<semaphore 4 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF5_Pos     (5U)
-#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)               /*!< 0x00000020 */
-#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                          /*!<semaphore 5 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF6_Pos     (6U)
-#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)               /*!< 0x00000040 */
-#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                          /*!<semaphore 6 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF7_Pos     (7U)
-#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)               /*!< 0x00000080 */
-#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                          /*!<semaphore 7 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF8_Pos     (8U)
-#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)               /*!< 0x00000100 */
-#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                          /*!<semaphore 8 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF9_Pos     (9U)
-#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)               /*!< 0x00000200 */
-#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                          /*!<semaphore 9 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF10_Pos    (10U)
-#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)              /*!< 0x00000400 */
-#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                         /*!<semaphore 10 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF11_Pos    (11U)
-#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)              /*!< 0x00000800 */
-#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                         /*!<semaphore 11 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF12_Pos    (12U)
-#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)              /*!< 0x00001000 */
-#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                         /*!<semaphore 12 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF13_Pos    (13U)
-#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)              /*!< 0x00002000 */
-#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                         /*!<semaphore 13 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF14_Pos    (14U)
-#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)              /*!< 0x00004000 */
-#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                         /*!<semaphore 14 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF15_Pos    (15U)
-#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)              /*!< 0x00008000 */
-#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                         /*!<semaphore 15 CPU1 interrupt masked status bit. */
-
-/********************  Bit definition for HSEM_C2IER register  *****************/
-#define HSEM_C2IER_ISE0_Pos      (0U)
-#define HSEM_C2IER_ISE0_Msk      (0x1UL << HSEM_C2IER_ISE0_Pos)                /*!< 0x00000001 */
-#define HSEM_C2IER_ISE0          HSEM_C2IER_ISE0_Msk                           /*!<semaphore 0 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE1_Pos      (1U)
-#define HSEM_C2IER_ISE1_Msk      (0x1UL << HSEM_C2IER_ISE1_Pos)                /*!< 0x00000002 */
-#define HSEM_C2IER_ISE1          HSEM_C2IER_ISE1_Msk                           /*!<semaphore 1 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE2_Pos      (2U)
-#define HSEM_C2IER_ISE2_Msk      (0x1UL << HSEM_C2IER_ISE2_Pos)                /*!< 0x00000004 */
-#define HSEM_C2IER_ISE2          HSEM_C2IER_ISE2_Msk                           /*!<semaphore 2 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE3_Pos      (3U)
-#define HSEM_C2IER_ISE3_Msk      (0x1UL << HSEM_C2IER_ISE3_Pos)                /*!< 0x00000008 */
-#define HSEM_C2IER_ISE3          HSEM_C2IER_ISE3_Msk                           /*!<semaphore 3 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE4_Pos      (4U)
-#define HSEM_C2IER_ISE4_Msk      (0x1UL << HSEM_C2IER_ISE4_Pos)                /*!< 0x00000010 */
-#define HSEM_C2IER_ISE4          HSEM_C2IER_ISE4_Msk                           /*!<semaphore 4 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE5_Pos      (5U)
-#define HSEM_C2IER_ISE5_Msk      (0x1UL << HSEM_C2IER_ISE5_Pos)                /*!< 0x00000020 */
-#define HSEM_C2IER_ISE5          HSEM_C2IER_ISE5_Msk                           /*!<semaphore 5 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE6_Pos      (6U)
-#define HSEM_C2IER_ISE6_Msk      (0x1UL << HSEM_C2IER_ISE6_Pos)                /*!< 0x00000040 */
-#define HSEM_C2IER_ISE6          HSEM_C2IER_ISE6_Msk                           /*!<semaphore 6 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE7_Pos      (7U)
-#define HSEM_C2IER_ISE7_Msk      (0x1UL << HSEM_C2IER_ISE7_Pos)                /*!< 0x00000080 */
-#define HSEM_C2IER_ISE7          HSEM_C2IER_ISE7_Msk                           /*!<semaphore 7 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE8_Pos      (8U)
-#define HSEM_C2IER_ISE8_Msk      (0x1UL << HSEM_C2IER_ISE8_Pos)                /*!< 0x00000100 */
-#define HSEM_C2IER_ISE8          HSEM_C2IER_ISE8_Msk                           /*!<semaphore 8 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE9_Pos      (9U)
-#define HSEM_C2IER_ISE9_Msk      (0x1UL << HSEM_C2IER_ISE9_Pos)                /*!< 0x00000200 */
-#define HSEM_C2IER_ISE9          HSEM_C2IER_ISE9_Msk                           /*!<semaphore 9 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE10_Pos     (10U)
-#define HSEM_C2IER_ISE10_Msk     (0x1UL << HSEM_C2IER_ISE10_Pos)               /*!< 0x00000400 */
-#define HSEM_C2IER_ISE10         HSEM_C2IER_ISE10_Msk                          /*!<semaphore 10 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE11_Pos     (11U)
-#define HSEM_C2IER_ISE11_Msk     (0x1UL << HSEM_C2IER_ISE11_Pos)               /*!< 0x00000800 */
-#define HSEM_C2IER_ISE11         HSEM_C2IER_ISE11_Msk                          /*!<semaphore 11 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE12_Pos     (12U)
-#define HSEM_C2IER_ISE12_Msk     (0x1UL << HSEM_C2IER_ISE12_Pos)               /*!< 0x00001000 */
-#define HSEM_C2IER_ISE12         HSEM_C2IER_ISE12_Msk                          /*!<semaphore 12 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE13_Pos     (13U)
-#define HSEM_C2IER_ISE13_Msk     (0x1UL << HSEM_C2IER_ISE13_Pos)               /*!< 0x00002000 */
-#define HSEM_C2IER_ISE13         HSEM_C2IER_ISE13_Msk                          /*!<semaphore 13 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE14_Pos     (14U)
-#define HSEM_C2IER_ISE14_Msk     (0x1UL << HSEM_C2IER_ISE14_Pos)               /*!< 0x00004000 */
-#define HSEM_C2IER_ISE14         HSEM_C2IER_ISE14_Msk                          /*!<semaphore 14 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE15_Pos     (15U)
-#define HSEM_C2IER_ISE15_Msk     (0x1UL << HSEM_C2IER_ISE15_Pos)               /*!< 0x00008000 */
-#define HSEM_C2IER_ISE15         HSEM_C2IER_ISE15_Msk                          /*!<semaphore 15 CPU2 interrupt enable bit. */
-
-/********************  Bit definition for HSEM_C2ICR register  *****************/
-#define HSEM_C2ICR_ISC0_Pos      (0U)
-#define HSEM_C2ICR_ISC0_Msk      (0x1UL << HSEM_C2ICR_ISC0_Pos)                /*!< 0x00000001 */
-#define HSEM_C2ICR_ISC0          HSEM_C2ICR_ISC0_Msk                           /*!<semaphore 0 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC1_Pos      (1U)
-#define HSEM_C2ICR_ISC1_Msk      (0x1UL << HSEM_C2ICR_ISC1_Pos)                /*!< 0x00000002 */
-#define HSEM_C2ICR_ISC1          HSEM_C2ICR_ISC1_Msk                           /*!<semaphore 1 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC2_Pos      (2U)
-#define HSEM_C2ICR_ISC2_Msk      (0x1UL << HSEM_C2ICR_ISC2_Pos)                /*!< 0x00000004 */
-#define HSEM_C2ICR_ISC2          HSEM_C2ICR_ISC2_Msk                           /*!<semaphore 2 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC3_Pos      (3U)
-#define HSEM_C2ICR_ISC3_Msk      (0x1UL << HSEM_C2ICR_ISC3_Pos)                /*!< 0x00000008 */
-#define HSEM_C2ICR_ISC3          HSEM_C2ICR_ISC3_Msk                           /*!<semaphore 3 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC4_Pos      (4U)
-#define HSEM_C2ICR_ISC4_Msk      (0x1UL << HSEM_C2ICR_ISC4_Pos)                /*!< 0x00000010 */
-#define HSEM_C2ICR_ISC4          HSEM_C2ICR_ISC4_Msk                           /*!<semaphore 4 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC5_Pos      (5U)
-#define HSEM_C2ICR_ISC5_Msk      (0x1UL << HSEM_C2ICR_ISC5_Pos)                /*!< 0x00000020 */
-#define HSEM_C2ICR_ISC5          HSEM_C2ICR_ISC5_Msk                           /*!<semaphore 5 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC6_Pos      (6U)
-#define HSEM_C2ICR_ISC6_Msk      (0x1UL << HSEM_C2ICR_ISC6_Pos)                /*!< 0x00000040 */
-#define HSEM_C2ICR_ISC6          HSEM_C2ICR_ISC6_Msk                           /*!<semaphore 6 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC7_Pos      (7U)
-#define HSEM_C2ICR_ISC7_Msk      (0x1UL << HSEM_C2ICR_ISC7_Pos)                /*!< 0x00000080 */
-#define HSEM_C2ICR_ISC7          HSEM_C2ICR_ISC7_Msk                           /*!<semaphore 7 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC8_Pos      (8U)
-#define HSEM_C2ICR_ISC8_Msk      (0x1UL << HSEM_C2ICR_ISC8_Pos)                /*!< 0x00000100 */
-#define HSEM_C2ICR_ISC8          HSEM_C2ICR_ISC8_Msk                           /*!<semaphore 8 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC9_Pos      (9U)
-#define HSEM_C2ICR_ISC9_Msk      (0x1UL << HSEM_C2ICR_ISC9_Pos)                /*!< 0x00000200 */
-#define HSEM_C2ICR_ISC9          HSEM_C2ICR_ISC9_Msk                           /*!<semaphore 9 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC10_Pos     (10U)
-#define HSEM_C2ICR_ISC10_Msk     (0x1UL << HSEM_C2ICR_ISC10_Pos)               /*!< 0x00000400 */
-#define HSEM_C2ICR_ISC10         HSEM_C2ICR_ISC10_Msk                          /*!<semaphore 10 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC11_Pos     (11U)
-#define HSEM_C2ICR_ISC11_Msk     (0x1UL << HSEM_C2ICR_ISC11_Pos)               /*!< 0x00000800 */
-#define HSEM_C2ICR_ISC11         HSEM_C2ICR_ISC11_Msk                          /*!<semaphore 11 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC12_Pos     (12U)
-#define HSEM_C2ICR_ISC12_Msk     (0x1UL << HSEM_C2ICR_ISC12_Pos)               /*!< 0x00001000 */
-#define HSEM_C2ICR_ISC12         HSEM_C2ICR_ISC12_Msk                          /*!<semaphore 12 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC13_Pos     (13U)
-#define HSEM_C2ICR_ISC13_Msk     (0x1UL << HSEM_C2ICR_ISC13_Pos)               /*!< 0x00002000 */
-#define HSEM_C2ICR_ISC13         HSEM_C2ICR_ISC13_Msk                          /*!<semaphore 13 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC14_Pos     (14U)
-#define HSEM_C2ICR_ISC14_Msk     (0x1UL << HSEM_C2ICR_ISC14_Pos)               /*!< 0x00004000 */
-#define HSEM_C2ICR_ISC14         HSEM_C2ICR_ISC14_Msk                          /*!<semaphore 14 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC15_Pos     (15U)
-#define HSEM_C2ICR_ISC15_Msk     (0x1UL << HSEM_C2ICR_ISC15_Pos)               /*!< 0x00008000 */
-#define HSEM_C2ICR_ISC15         HSEM_C2ICR_ISC15_Msk                          /*!<semaphore 15 CPU2 interrupt clear bit. */
-
-/********************  Bit definition for HSEM_C2ISR register  *****************/
-#define HSEM_C2ISR_ISF0_Pos      (0U)
-#define HSEM_C2ISR_ISF0_Msk      (0x1UL << HSEM_C2ISR_ISF0_Pos)                /*!< 0x00000001 */
-#define HSEM_C2ISR_ISF0          HSEM_C2ISR_ISF0_Msk                           /*!<semaphore 0 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF1_Pos      (1U)
-#define HSEM_C2ISR_ISF1_Msk      (0x1UL << HSEM_C2ISR_ISF1_Pos)                /*!< 0x00000002 */
-#define HSEM_C2ISR_ISF1          HSEM_C2ISR_ISF1_Msk                           /*!<semaphore 1 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF2_Pos      (2U)
-#define HSEM_C2ISR_ISF2_Msk      (0x1UL << HSEM_C2ISR_ISF2_Pos)                /*!< 0x00000004 */
-#define HSEM_C2ISR_ISF2          HSEM_C2ISR_ISF2_Msk                           /*!<semaphore 2 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF3_Pos      (3U)
-#define HSEM_C2ISR_ISF3_Msk      (0x1UL << HSEM_C2ISR_ISF3_Pos)                /*!< 0x00000008 */
-#define HSEM_C2ISR_ISF3          HSEM_C2ISR_ISF3_Msk                           /*!<semaphore 3 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF4_Pos      (4U)
-#define HSEM_C2ISR_ISF4_Msk      (0x1UL << HSEM_C2ISR_ISF4_Pos)                /*!< 0x00000010 */
-#define HSEM_C2ISR_ISF4          HSEM_C2ISR_ISF4_Msk                           /*!<semaphore 4 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF5_Pos      (5U)
-#define HSEM_C2ISR_ISF5_Msk      (0x1UL << HSEM_C2ISR_ISF5_Pos)                /*!< 0x00000020 */
-#define HSEM_C2ISR_ISF5          HSEM_C2ISR_ISF5_Msk                           /*!<semaphore 5 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF6_Pos      (6U)
-#define HSEM_C2ISR_ISF6_Msk      (0x1UL << HSEM_C2ISR_ISF6_Pos)                /*!< 0x00000040 */
-#define HSEM_C2ISR_ISF6          HSEM_C2ISR_ISF6_Msk                           /*!<semaphore 6 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF7_Pos      (7U)
-#define HSEM_C2ISR_ISF7_Msk      (0x1UL << HSEM_C2ISR_ISF7_Pos)                /*!< 0x00000080 */
-#define HSEM_C2ISR_ISF7          HSEM_C2ISR_ISF7_Msk                           /*!<semaphore 7 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF8_Pos      (8U)
-#define HSEM_C2ISR_ISF8_Msk      (0x1UL << HSEM_C2ISR_ISF8_Pos)                /*!< 0x00000100 */
-#define HSEM_C2ISR_ISF8          HSEM_C2ISR_ISF8_Msk                           /*!<semaphore 8 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF9_Pos      (9U)
-#define HSEM_C2ISR_ISF9_Msk      (0x1UL << HSEM_C2ISR_ISF9_Pos)                /*!< 0x00000200 */
-#define HSEM_C2ISR_ISF9          HSEM_C2ISR_ISF9_Msk                           /*!<semaphore 9 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF10_Pos     (10U)
-#define HSEM_C2ISR_ISF10_Msk     (0x1UL << HSEM_C2ISR_ISF10_Pos)               /*!< 0x00000400 */
-#define HSEM_C2ISR_ISF10         HSEM_C2ISR_ISF10_Msk                          /*!<semaphore 10 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF11_Pos     (11U)
-#define HSEM_C2ISR_ISF11_Msk     (0x1UL << HSEM_C2ISR_ISF11_Pos)               /*!< 0x00000800 */
-#define HSEM_C2ISR_ISF11         HSEM_C2ISR_ISF11_Msk                          /*!<semaphore 11 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF12_Pos     (12U)
-#define HSEM_C2ISR_ISF12_Msk     (0x1UL << HSEM_C2ISR_ISF12_Pos)               /*!< 0x00001000 */
-#define HSEM_C2ISR_ISF12         HSEM_C2ISR_ISF12_Msk                          /*!<semaphore 12 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF13_Pos     (13U)
-#define HSEM_C2ISR_ISF13_Msk     (0x1UL << HSEM_C2ISR_ISF13_Pos)               /*!< 0x00002000 */
-#define HSEM_C2ISR_ISF13         HSEM_C2ISR_ISF13_Msk                          /*!<semaphore 13 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF14_Pos     (14U)
-#define HSEM_C2ISR_ISF14_Msk     (0x1UL << HSEM_C2ISR_ISF14_Pos)               /*!< 0x00004000 */
-#define HSEM_C2ISR_ISF14         HSEM_C2ISR_ISF14_Msk                          /*!<semaphore 14 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF15_Pos     (15U)
-#define HSEM_C2ISR_ISF15_Msk     (0x1UL << HSEM_C2ISR_ISF15_Pos)               /*!< 0x00008000 */
-#define HSEM_C2ISR_ISF15         HSEM_C2ISR_ISF15_Msk                          /*!<semaphore 15 CPU2 interrupt status bit. */
-
-/********************  Bit definition for HSEM_C2MISR register  *****************/
-#define HSEM_C2MISR_MISF0_Pos     (0U)
-#define HSEM_C2MISR_MISF0_Msk     (0x1UL << HSEM_C2MISR_MISF0_Pos)               /*!< 0x00000001 */
-#define HSEM_C2MISR_MISF0         HSEM_C2MISR_MISF0_Msk                          /*!<semaphore 0 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF1_Pos     (1U)
-#define HSEM_C2MISR_MISF1_Msk     (0x1UL << HSEM_C2MISR_MISF1_Pos)               /*!< 0x00000002 */
-#define HSEM_C2MISR_MISF1         HSEM_C2MISR_MISF1_Msk                          /*!<semaphore 1 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF2_Pos     (2U)
-#define HSEM_C2MISR_MISF2_Msk     (0x1UL << HSEM_C2MISR_MISF2_Pos)               /*!< 0x00000004 */
-#define HSEM_C2MISR_MISF2         HSEM_C2MISR_MISF2_Msk                          /*!<semaphore 2 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF3_Pos     (3U)
-#define HSEM_C2MISR_MISF3_Msk     (0x1UL << HSEM_C2MISR_MISF3_Pos)               /*!< 0x00000008 */
-#define HSEM_C2MISR_MISF3         HSEM_C2MISR_MISF3_Msk                          /*!<semaphore 3 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF4_Pos     (4U)
-#define HSEM_C2MISR_MISF4_Msk     (0x1UL << HSEM_C2MISR_MISF4_Pos)               /*!< 0x00000010 */
-#define HSEM_C2MISR_MISF4         HSEM_C2MISR_MISF4_Msk                          /*!<semaphore 4 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF5_Pos     (5U)
-#define HSEM_C2MISR_MISF5_Msk     (0x1UL << HSEM_C2MISR_MISF5_Pos)               /*!< 0x00000020 */
-#define HSEM_C2MISR_MISF5         HSEM_C2MISR_MISF5_Msk                          /*!<semaphore 5 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF6_Pos     (6U)
-#define HSEM_C2MISR_MISF6_Msk     (0x1UL << HSEM_C2MISR_MISF6_Pos)               /*!< 0x00000040 */
-#define HSEM_C2MISR_MISF6         HSEM_C2MISR_MISF6_Msk                          /*!<semaphore 6 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF7_Pos     (7U)
-#define HSEM_C2MISR_MISF7_Msk     (0x1UL << HSEM_C2MISR_MISF7_Pos)               /*!< 0x00000080 */
-#define HSEM_C2MISR_MISF7         HSEM_C2MISR_MISF7_Msk                          /*!<semaphore 7 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF8_Pos     (8U)
-#define HSEM_C2MISR_MISF8_Msk     (0x1UL << HSEM_C2MISR_MISF8_Pos)               /*!< 0x00000100 */
-#define HSEM_C2MISR_MISF8         HSEM_C2MISR_MISF8_Msk                          /*!<semaphore 8 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF9_Pos     (9U)
-#define HSEM_C2MISR_MISF9_Msk     (0x1UL << HSEM_C2MISR_MISF9_Pos)               /*!< 0x00000200 */
-#define HSEM_C2MISR_MISF9         HSEM_C2MISR_MISF9_Msk                          /*!<semaphore 9 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF10_Pos    (10U)
-#define HSEM_C2MISR_MISF10_Msk    (0x1UL << HSEM_C2MISR_MISF10_Pos)              /*!< 0x00000400 */
-#define HSEM_C2MISR_MISF10        HSEM_C2MISR_MISF10_Msk                         /*!<semaphore 10 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF11_Pos    (11U)
-#define HSEM_C2MISR_MISF11_Msk    (0x1UL << HSEM_C2MISR_MISF11_Pos)              /*!< 0x00000800 */
-#define HSEM_C2MISR_MISF11        HSEM_C2MISR_MISF11_Msk                         /*!<semaphore 11 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF12_Pos    (12U)
-#define HSEM_C2MISR_MISF12_Msk    (0x1UL << HSEM_C2MISR_MISF12_Pos)              /*!< 0x00001000 */
-#define HSEM_C2MISR_MISF12        HSEM_C2MISR_MISF12_Msk                         /*!<semaphore 12 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF13_Pos    (13U)
-#define HSEM_C2MISR_MISF13_Msk    (0x1UL << HSEM_C2MISR_MISF13_Pos)              /*!< 0x00002000 */
-#define HSEM_C2MISR_MISF13        HSEM_C2MISR_MISF13_Msk                         /*!<semaphore 13 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF14_Pos    (14U)
-#define HSEM_C2MISR_MISF14_Msk    (0x1UL << HSEM_C2MISR_MISF14_Pos)              /*!< 0x00004000 */
-#define HSEM_C2MISR_MISF14        HSEM_C2MISR_MISF14_Msk                         /*!<semaphore 14 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF15_Pos    (15U)
-#define HSEM_C2MISR_MISF15_Msk    (0x1UL << HSEM_C2MISR_MISF15_Pos)              /*!< 0x00008000 */
-#define HSEM_C2MISR_MISF15        HSEM_C2MISR_MISF15_Msk                         /*!<semaphore 15 CPU2 interrupt masked status bit. */
-
-/********************  Bit definition for HSEM_CR register  *****************/
-#define HSEM_CR_COREID_Pos       (8U)
-#define HSEM_CR_COREID_Msk       (0xFUL << HSEM_CR_COREID_Pos)                 /*!< 0x00000F00 */
-#define HSEM_CR_COREID           HSEM_CR_COREID_Msk                            /*!<CoreID of semaphores to be cleared. */
-#define HSEM_CR_COREID_CPU1      (0x4U << HSEM_CR_COREID_Pos)
-#define HSEM_CR_COREID_CPU2      (0x8U << HSEM_CR_COREID_Pos)
-#if defined(CORE_CM0PLUS)
-#define HSEM_CR_COREID_CURRENT   HSEM_CR_COREID_CPU2
-#else
-#define HSEM_CR_COREID_CURRENT   HSEM_CR_COREID_CPU1
-#endif
-#define HSEM_CR_KEY_Pos          (16U)
-#define HSEM_CR_KEY_Msk          (0xFFFFUL << HSEM_CR_KEY_Pos)                 /*!< 0xFFFF0000 */
-#define HSEM_CR_KEY              HSEM_CR_KEY_Msk                               /*!<semaphores clear key. */
-
-/********************  Bit definition for HSEM_KEYR register  *****************/
-#define HSEM_KEYR_KEY_Pos        (16U)
-#define HSEM_KEYR_KEY_Msk        (0xFFFFUL << HSEM_KEYR_KEY_Pos)               /*!< 0xFFFF0000 */
-#define HSEM_KEYR_KEY            HSEM_KEYR_KEY_Msk                             /*!<semaphores clear key. */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Public Key Accelerator (PKA)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bits definition for PKA_CR register  **************/
-#define PKA_CR_EN_Pos              (0U)
-#define PKA_CR_EN_Msk              (0x1UL << PKA_CR_EN_Pos)                /*!< 0x00000001 */
-#define PKA_CR_EN                  PKA_CR_EN_Msk                           /*!< PKA enable */
-#define PKA_CR_START_Pos           (1U)
-#define PKA_CR_START_Msk           (0x1UL << PKA_CR_START_Pos)             /*!< 0x00000002 */
-#define PKA_CR_START               PKA_CR_START_Msk                        /*!< Start operation */
-#define PKA_CR_MODE_Pos            (8U)
-#define PKA_CR_MODE_Msk            (0x3FUL << PKA_CR_MODE_Pos)             /*!< 0x00003F00 */
-#define PKA_CR_MODE                PKA_CR_MODE_Msk                         /*!< MODE[5:0] PKA operation code */
-#define PKA_CR_MODE_0              (0x01UL << PKA_CR_MODE_Pos)             /*!< 0x00000100 */
-#define PKA_CR_MODE_1              (0x02UL << PKA_CR_MODE_Pos)             /*!< 0x00000200 */
-#define PKA_CR_MODE_2              (0x04UL << PKA_CR_MODE_Pos)             /*!< 0x00000400 */
-#define PKA_CR_MODE_3              (0x08UL << PKA_CR_MODE_Pos)             /*!< 0x00000800 */
-#define PKA_CR_MODE_4              (0x10UL << PKA_CR_MODE_Pos)             /*!< 0x00001000 */
-#define PKA_CR_MODE_5              (0x20UL << PKA_CR_MODE_Pos)             /*!< 0x00002000 */
-#define PKA_CR_PROCENDIE_Pos       (17U)
-#define PKA_CR_PROCENDIE_Msk       (0x1UL << PKA_CR_PROCENDIE_Pos)         /*!< 0x00020000 */
-#define PKA_CR_PROCENDIE           PKA_CR_PROCENDIE_Msk                    /*!< End of operation interrupt enable */
-#define PKA_CR_RAMERRIE_Pos        (19U)
-#define PKA_CR_RAMERRIE_Msk        (0x1UL << PKA_CR_RAMERRIE_Pos)          /*!< 0x00080000 */
-#define PKA_CR_RAMERRIE            PKA_CR_RAMERRIE_Msk                     /*!< RAM error interrupt enable */
-#define PKA_CR_ADDRERRIE_Pos       (20U)
-#define PKA_CR_ADDRERRIE_Msk       (0x1UL << PKA_CR_ADDRERRIE_Pos)         /*!< 0x00100000 */
-#define PKA_CR_ADDRERRIE           PKA_CR_ADDRERRIE_Msk                    /*!< RAM error interrupt enable */
-
-/*******************  Bits definition for PKA_SR register  **************/
-#define PKA_SR_BUSY_Pos            (16U)
-#define PKA_SR_BUSY_Msk            (0x1UL << PKA_SR_BUSY_Pos)              /*!< 0x00010000 */
-#define PKA_SR_BUSY                PKA_SR_BUSY_Msk                         /*!< PKA operation is in progress */
-#define PKA_SR_PROCENDF_Pos        (17U)
-#define PKA_SR_PROCENDF_Msk        (0x1UL << PKA_SR_PROCENDF_Pos)          /*!< 0x00020000 */
-#define PKA_SR_PROCENDF            PKA_SR_PROCENDF_Msk                     /*!< PKA end of operation flag */
-#define PKA_SR_RAMERRF_Pos         (19U)
-#define PKA_SR_RAMERRF_Msk         (0x1UL << PKA_SR_RAMERRF_Pos)           /*!< 0x00080000 */
-#define PKA_SR_RAMERRF             PKA_SR_RAMERRF_Msk                      /*!< PKA RAM error flag */
-#define PKA_SR_ADDRERRF_Pos        (20U)
-#define PKA_SR_ADDRERRF_Msk        (0x1UL << PKA_SR_ADDRERRF_Pos)          /*!< 0x00100000 */
-#define PKA_SR_ADDRERRF            PKA_SR_ADDRERRF_Msk                     /*!< Address error flag */
-
-/*******************  Bits definition for PKA_CLRFR register  **************/
-#define PKA_CLRFR_PROCENDFC_Pos    (17U)
-#define PKA_CLRFR_PROCENDFC_Msk    (0x1UL << PKA_CLRFR_PROCENDFC_Pos)      /*!< 0x00020000 */
-#define PKA_CLRFR_PROCENDFC        PKA_CLRFR_PROCENDFC_Msk                 /*!< Clear PKA end of operation flag */
-#define PKA_CLRFR_RAMERRFC_Pos     (19U)
-#define PKA_CLRFR_RAMERRFC_Msk     (0x1UL << PKA_CLRFR_RAMERRFC_Pos)       /*!< 0x00080000 */
-#define PKA_CLRFR_RAMERRFC         PKA_CLRFR_RAMERRFC_Msk                  /*!< Clear PKA RAM error flag */
-#define PKA_CLRFR_ADDRERRFC_Pos    (20U)
-#define PKA_CLRFR_ADDRERRFC_Msk    (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)      /*!< 0x00100000 */
-#define PKA_CLRFR_ADDRERRFC        PKA_CLRFR_ADDRERRFC_Msk                 /*!< Clear address error flag */
-
-/*******************  Bits definition for PKA RAM  *************************/
-#define PKA_RAM_OFFSET                            0x400U                           /*!< PKA RAM address offset */
-
-/* Compute Montgomery parameter input data */
-#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS       ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_MONTGOMERY_PARAM_IN_MODULUS           ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Compute Montgomery parameter output data */
-#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER        ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Output Montgomery parameter */
-
-/* Compute modular exponentiation input data */
-#define PKA_MODULAR_EXP_IN_EXP_NB_BITS            ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent number of bits */
-#define PKA_MODULAR_EXP_IN_OP_NB_BITS             ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM       ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Input storage area for Montgomery parameter */
-#define PKA_MODULAR_EXP_IN_EXPONENT_BASE          ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input base of the exponentiation */
-#define PKA_MODULAR_EXP_IN_EXPONENT               ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent to process */
-#define PKA_MODULAR_EXP_IN_MODULUS                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Compute modular exponentiation output data */
-#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM      ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Output storage area for Montgomery parameter */
-#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1          ((0x724U - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 1 */
-#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2          ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 2 */
-#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE         ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Output base of the exponentiation */
-#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3          ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 3 */
-
-/* Compute ECC scalar multiplication input data */
-#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS         ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent number of bits */
-#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS          ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN        ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_ECC_SCALAR_MUL_IN_A_COEFF             ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_ECC_SCALAR_MUL_IN_MOD_GF              ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM    ((0x4B4U - PKA_RAM_OFFSET)>>2)   /*!< Input storage area for Montgomery parameter */
-#define PKA_ECC_SCALAR_MUL_IN_K                   ((0x508U - PKA_RAM_OFFSET)>>2)   /*!< Input 'k' of KP */
-#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X     ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y     ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-
-/* Compute ECC scalar multiplication output data */
-#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X           ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Output result X coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y           ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Output result Y coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1     ((0xDE8U - PKA_RAM_OFFSET)>>2)   /*!< Output last double X1 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1     ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Output last double Y1 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1     ((0xE90U - PKA_RAM_OFFSET)>>2)   /*!< Output last double Z1 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2     ((0xEE4U - PKA_RAM_OFFSET)>>2)   /*!< Output check point X2 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2     ((0xF38U - PKA_RAM_OFFSET)>>2)   /*!< Output check point Y2 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2     ((0xF8CU - PKA_RAM_OFFSET)>>2)   /*!< Output check point Z2 coordinate */
-
-/* Point check input data */
-#define PKA_POINT_CHECK_IN_MOD_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_POINT_CHECK_IN_A_COEFF_SIGN           ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_POINT_CHECK_IN_A_COEFF                ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_POINT_CHECK_IN_B_COEFF                ((0x7FCU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'b' coefficient */
-#define PKA_POINT_CHECK_IN_MOD_GF                 ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_POINT_CHECK_IN_INITIAL_POINT_X        ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y        ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-
-/* Point check output data */
-#define PKA_POINT_CHECK_OUT_ERROR                 ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Output error */
-
-/* ECDSA signature input data */
-#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS           ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input order number of bits */
-#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS             ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN            ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_ECDSA_SIGN_IN_A_COEFF                 ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_ECDSA_SIGN_IN_MOD_GF                  ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_ECDSA_SIGN_IN_K                       ((0x508U - PKA_RAM_OFFSET)>>2)   /*!< Input k value of the ECDSA */
-#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X         ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y         ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-#define PKA_ECDSA_SIGN_IN_HASH_E                  ((0xDE8U - PKA_RAM_OFFSET)>>2)   /*!< Input e, hash of the message */
-#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D           ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Input d, private key */
-#define PKA_ECDSA_SIGN_IN_ORDER_N                 ((0xE94U - PKA_RAM_OFFSET)>>2)   /*!< Input n, order of the curve */
-
-/* ECDSA signature output data */
-#define PKA_ECDSA_SIGN_OUT_ERROR                  ((0xEE8U - PKA_RAM_OFFSET)>>2)   /*!< Output error */
-#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R            ((0x700U - PKA_RAM_OFFSET)>>2)   /*!< Output signature r */
-#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S            ((0x754U - PKA_RAM_OFFSET)>>2)   /*!< Output signature s */
-#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X          ((0x103CU - PKA_RAM_OFFSET)>>2)   /*!< Output final point kP X coordinate */
-#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y          ((0x1090U - PKA_RAM_OFFSET)>>2)   /*!< Output final point kP Y coordinate */
-
-/* ECDSA verification input data */
-#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS          ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input order number of bits */
-#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS            ((0x4B4U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN           ((0x45CU - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_ECDSA_VERIF_IN_A_COEFF                ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_ECDSA_VERIF_IN_MOD_GF                 ((0x4B8U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X        ((0x5E8U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y        ((0x63CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X     ((0xF40U - PKA_RAM_OFFSET)>>2)   /*!< Input public key point X coordinate */
-#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y     ((0xF94U - PKA_RAM_OFFSET)>>2)   /*!< Input public key point Y coordinate */
-#define PKA_ECDSA_VERIF_IN_SIGNATURE_R            ((0x1098U - PKA_RAM_OFFSET)>>2)   /*!< Input r, part of the signature */
-#define PKA_ECDSA_VERIF_IN_SIGNATURE_S            ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input s, part of the signature */
-#define PKA_ECDSA_VERIF_IN_HASH_E                 ((0xFE8U - PKA_RAM_OFFSET)>>2)   /*!< Input e, hash of the message */
-#define PKA_ECDSA_VERIF_IN_ORDER_N                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input n, order of the curve */
-
-/* ECDSA verification output data */
-#define PKA_ECDSA_VERIF_OUT_RESULT                ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* RSA CRT exponentiation input data */
-#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operands number of bits */
-#define PKA_RSA_CRT_EXP_IN_DP_CRT                 ((0x65CU - PKA_RAM_OFFSET)>>2)   /*!< Input Dp CRT parameter */
-#define PKA_RSA_CRT_EXP_IN_DQ_CRT                 ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Input Dq CRT parameter */
-#define PKA_RSA_CRT_EXP_IN_QINV_CRT               ((0x7ECU - PKA_RAM_OFFSET)>>2)   /*!< Input qInv CRT parameter */
-#define PKA_RSA_CRT_EXP_IN_PRIME_P                ((0x97CU - PKA_RAM_OFFSET)>>2)   /*!< Input Prime p */
-#define PKA_RSA_CRT_EXP_IN_PRIME_Q                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input Prime q */
-#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE          ((0xEECU - PKA_RAM_OFFSET)>>2)   /*!< Input base of the exponentiation */
-
-/* RSA CRT exponentiation output data */
-#define PKA_RSA_CRT_EXP_OUT_RESULT                ((0x724U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular reduction input data */
-#define PKA_MODULAR_REDUC_IN_OP_LENGTH            ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input operand length */
-#define PKA_MODULAR_REDUC_IN_OPERAND              ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand */
-#define PKA_MODULAR_REDUC_IN_MOD_LENGTH           ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus length */
-#define PKA_MODULAR_REDUC_IN_MODULUS              ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Modular reduction output data */
-#define PKA_MODULAR_REDUC_OUT_RESULT              ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Arithmetic addition input data */
-#define PKA_ARITHMETIC_ADD_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_ADD_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_ADD_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Arithmetic addition output data */
-#define PKA_ARITHMETIC_ADD_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Arithmetic substraction input data */
-#define PKA_ARITHMETIC_SUB_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_SUB_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_SUB_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Arithmetic substraction output data */
-#define PKA_ARITHMETIC_SUB_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Arithmetic multiplication input data */
-#define PKA_ARITHMETIC_MUL_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_MUL_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_MUL_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Arithmetic multiplication output data */
-#define PKA_ARITHMETIC_MUL_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Comparison input data */
-#define PKA_COMPARISON_NB_BITS                    ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_COMPARISON_IN_OP1                     ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_COMPARISON_IN_OP2                     ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Comparison output data */
-#define PKA_COMPARISON_OUT_RESULT                 ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular addition input data */
-#define PKA_MODULAR_ADD_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_ADD_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MODULAR_ADD_IN_OP2                    ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_MODULAR_ADD_IN_OP3_MOD                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 (modulus) */
-
-/* Modular addition output data */
-#define PKA_MODULAR_ADD_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular inversion input data */
-#define PKA_MODULAR_INV_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_INV_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MODULAR_INV_IN_OP2_MOD                ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 (modulus) */
-
-/* Modular inversion output data */
-#define PKA_MODULAR_INV_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular substraction input data */
-#define PKA_MODULAR_SUB_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_SUB_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MODULAR_SUB_IN_OP2                    ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_MODULAR_SUB_IN_OP3_MOD                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 */
-
-/* Modular substraction output data */
-#define PKA_MODULAR_SUB_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Montgomery multiplication input data */
-#define PKA_MONTGOMERY_MUL_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MONTGOMERY_MUL_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MONTGOMERY_MUL_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_MONTGOMERY_MUL_IN_OP3_MOD             ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Montgomery multiplication output data */
-#define PKA_MONTGOMERY_MUL_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Generic Arithmetic input data */
-#define PKA_ARITHMETIC_ALL_OPS_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_ALL_OPS_IN_OP1             ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_ALL_OPS_IN_OP2             ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_ARITHMETIC_ALL_OPS_IN_OP3             ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Generic Arithmetic output data */
-#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT         ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Power Control                                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR1 register  ********************/
-#define PWR_CR1_LPMS_Pos               (0U)
-#define PWR_CR1_LPMS_Msk               (0x7UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000007 */
-#define PWR_CR1_LPMS                   PWR_CR1_LPMS_Msk                        /*!< Low Power Mode Selection for CPU1 */
-#define PWR_CR1_LPMS_0                 (0x1UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000001 */
-#define PWR_CR1_LPMS_1                 (0x2UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000002 */
-#define PWR_CR1_LPMS_2                 (0x4UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000004 */
-
-#define PWR_CR1_SUBGHZSPINSSSEL_Pos    (3U)
-#define PWR_CR1_SUBGHZSPINSSSEL_Msk    (0x1UL << PWR_CR1_SUBGHZSPINSSSEL_Pos)  /*!< 0x00000008 */
-#define PWR_CR1_SUBGHZSPINSSSEL        PWR_CR1_SUBGHZSPINSSSEL_Msk             /*!< Sub-GHz radio SPI NSS source select */
-
-#define PWR_CR1_FPDR_Pos               (4U)
-#define PWR_CR1_FPDR_Msk               (0x1UL << PWR_CR1_FPDR_Pos)             /*!< 0x00000010 */
-#define PWR_CR1_FPDR                   PWR_CR1_FPDR_Msk                        /*!< Flash power down mode during LPrun for CPU1 */
-
-#define PWR_CR1_FPDS_Pos               (5U)
-#define PWR_CR1_FPDS_Msk               (0x1UL << PWR_CR1_FPDS_Pos)             /*!< 0x00000020 */
-#define PWR_CR1_FPDS                   PWR_CR1_FPDS_Msk                        /*!< Flash power down mode during LPsleep for CPU1 */
-
-#define PWR_CR1_DBP_Pos                (8U)
-#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
-#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Backup Domain write protection */
-
-#define PWR_CR1_VOS_Pos                (9U)
-#define PWR_CR1_VOS_Msk                (0x3UL << PWR_CR1_VOS_Pos)              /*!< 0x00000600 */
-#define PWR_CR1_VOS                    PWR_CR1_VOS_Msk                         /*!< Voltage scaling range selection */
-#define PWR_CR1_VOS_0                  (0x1UL << PWR_CR1_VOS_Pos)              /*!< 0x00000200 */
-#define PWR_CR1_VOS_1                  (0x2UL << PWR_CR1_VOS_Pos)              /*!< 0x00000400 */
-
-#define PWR_CR1_LPR_Pos                (14U)
-#define PWR_CR1_LPR_Msk                (0x1UL << PWR_CR1_LPR_Pos)              /*!< 0x00004000 */
-#define PWR_CR1_LPR                    PWR_CR1_LPR_Msk                         /*!< Regulator Low-Power Run mode */
-
-/********************  Bit definition for PWR_CR2 register  ********************/
-#define PWR_CR2_PVDE_Pos               (0U)
-#define PWR_CR2_PVDE_Msk               (0x1UL << PWR_CR2_PVDE_Pos)             /*!< 0x00000001 */
-#define PWR_CR2_PVDE                   PWR_CR2_PVDE_Msk                        /*!< Power voltage detector enable */
-
-#define PWR_CR2_PLS_Pos                (1U)
-#define PWR_CR2_PLS_Msk                (0x7UL << PWR_CR2_PLS_Pos)              /*!< 0x0000000E */
-#define PWR_CR2_PLS                    PWR_CR2_PLS_Msk                         /*!< Power voltage detector level selection */
-#define PWR_CR2_PLS_0                  (0x1UL << PWR_CR2_PLS_Pos)              /*!< 0x00000002 */
-#define PWR_CR2_PLS_1                  (0x2UL << PWR_CR2_PLS_Pos)              /*!< 0x00000004 */
-#define PWR_CR2_PLS_2                  (0x4UL << PWR_CR2_PLS_Pos)              /*!< 0x00000008 */
-
-#define PWR_CR2_PVME3_Pos              (6U)
-#define PWR_CR2_PVME3_Msk              (0x1UL << PWR_CR2_PVME3_Pos)            /*!< 0x00000040 */
-#define PWR_CR2_PVME3                  PWR_CR2_PVME3_Msk                       /*!< Peripherical Voltage Monitor Vdda Enable */
-
-/********************  Bit definition for PWR_CR3 register  ********************/
-#define PWR_CR3_EWUP_Pos               (0U)
-#define PWR_CR3_EWUP_Msk               (0x07UL << PWR_CR3_EWUP_Pos)            /*!< 0x00000007 */
-#define PWR_CR3_EWUP                   PWR_CR3_EWUP_Msk                        /*!< Enable all external Wake-Up lines  */
-#define PWR_CR3_EWUP1_Pos              (0U)
-#define PWR_CR3_EWUP1_Msk              (0x1UL << PWR_CR3_EWUP1_Pos)            /*!< 0x00000001 */
-#define PWR_CR3_EWUP1                  PWR_CR3_EWUP1_Msk                       /*!< Enable external WKUP Pin 1 [line 0] */
-#define PWR_CR3_EWUP2_Pos              (1U)
-#define PWR_CR3_EWUP2_Msk              (0x1UL << PWR_CR3_EWUP2_Pos)            /*!< 0x00000002 */
-#define PWR_CR3_EWUP2                  PWR_CR3_EWUP2_Msk                       /*!< Enable external WKUP Pin 2 [line 1] */
-#define PWR_CR3_EWUP3_Pos              (2U)
-#define PWR_CR3_EWUP3_Msk              (0x1UL << PWR_CR3_EWUP3_Pos)            /*!< 0x00000004 */
-#define PWR_CR3_EWUP3                  PWR_CR3_EWUP3_Msk                       /*!< Enable external WKUP Pin 3 [line 2] */
-
-#define PWR_CR3_ULPEN_Pos              (7U)
-#define PWR_CR3_ULPEN_Msk              (0x1UL << PWR_CR3_ULPEN_Pos)            /*!< 0x00000080 */
-#define PWR_CR3_ULPEN                  PWR_CR3_ULPEN_Msk                       /*!< Enable periodical sampling of supply voltage in Stop and Standby modes for detecting condition of PDR and BOR reset */
-
-#define PWR_CR3_EWPVD_Pos              (8U)
-#define PWR_CR3_EWPVD_Msk              (0x1UL << PWR_CR3_EWPVD_Pos)            /*!< 0x00000100 */
-#define PWR_CR3_EWPVD                  PWR_CR3_EWPVD_Msk                       /*!< Enable wakeup PVD for CPU1 */
-
-#define PWR_CR3_RRS_Pos                (9U)
-#define PWR_CR3_RRS_Msk                (0x1UL << PWR_CR3_RRS_Pos)              /*!< 0x00000200 */
-#define PWR_CR3_RRS                    PWR_CR3_RRS_Msk                         /*!< SRAM2 retention in STANDBY mode */
-
-#define PWR_CR3_APC_Pos                (10U)
-#define PWR_CR3_APC_Msk                (0x1UL << PWR_CR3_APC_Pos)              /*!< 0x00000400 */
-#define PWR_CR3_APC                    PWR_CR3_APC_Msk                         /*!< Apply pull-up and pull-down configuration for CPU1 */
-
-#define PWR_CR3_EWRFBUSY_Pos           (11U)
-#define PWR_CR3_EWRFBUSY_Msk           (0x1UL << PWR_CR3_EWRFBUSY_Pos)         /*!< 0x00008000 */
-#define PWR_CR3_EWRFBUSY                PWR_CR3_EWRFBUSY_Msk                   /*!< Enable Radio busy IRQ and wake-up for CPU1 */
-#define PWR_CR3_EWRFIRQ_Pos            (13U)
-#define PWR_CR3_EWRFIRQ_Msk            (0x1UL << PWR_CR3_EWRFIRQ_Pos)          /*!< 0x00020000 */
-#define PWR_CR3_EWRFIRQ                PWR_CR3_EWRFIRQ_Msk                     /*!< Enable Radio IRQ[2:0] and wake-up for CPU1 */
-
-#define PWR_CR3_EC2H_Pos               (14U)
-#define PWR_CR3_EC2H_Msk               (0x1UL << PWR_CR3_EC2H_Pos)             /*!< 0x00040000 */
-#define PWR_CR3_EC2H                    PWR_CR3_EC2H_Msk                       /*!< CPU2 Hold interrupt for CPU1 */
-
-#define PWR_CR3_EIWUL_Pos              (15U)
-#define PWR_CR3_EIWUL_Msk              (0x1UL << PWR_CR3_EIWUL_Pos)            /*!< 0x00080000 */
-#define PWR_CR3_EIWUL                  PWR_CR3_EIWUL_Msk                       /*!< Internal Wake-Up line interrupt for CPU1 */
-
-/********************  Bit definition for PWR_CR4 register  ********************/
-#define PWR_CR4_WP1_Pos                (0U)
-#define PWR_CR4_WP1_Msk                (0x1UL << PWR_CR4_WP1_Pos)              /*!< 0x00000001 */
-#define PWR_CR4_WP1                    PWR_CR4_WP1_Msk                         /*!< Wake-Up Pin 1 [line 0] polarity */
-#define PWR_CR4_WP2_Pos                (1U)
-#define PWR_CR4_WP2_Msk                (0x1UL << PWR_CR4_WP2_Pos)              /*!< 0x00000002 */
-#define PWR_CR4_WP2                    PWR_CR4_WP2_Msk                         /*!< Wake-Up Pin 2 [line 1] polarity */
-#define PWR_CR4_WP3_Pos                (2U)
-#define PWR_CR4_WP3_Msk                (0x1UL << PWR_CR4_WP3_Pos)              /*!< 0x00000004 */
-#define PWR_CR4_WP3                    PWR_CR4_WP3_Msk                         /*!< Wake-Up Pin 3 [line 2] polarity */
-
-#define PWR_CR4_VBE_Pos                (8U)
-#define PWR_CR4_VBE_Msk                (0x1UL << PWR_CR4_VBE_Pos)              /*!< 0x00000100 */
-#define PWR_CR4_VBE                    PWR_CR4_VBE_Msk                         /*!< VBAT battery charging enable  */
-#define PWR_CR4_VBRS_Pos               (9U)
-#define PWR_CR4_VBRS_Msk               (0x1UL << PWR_CR4_VBRS_Pos)             /*!< 0x00000200 */
-#define PWR_CR4_VBRS                   PWR_CR4_VBRS_Msk                        /*!< VBAT battery charging resistor selection */
-
-#define PWR_CR4_WRFBUSYP_Pos           (11U)
-#define PWR_CR4_WRFBUSYP_Msk           (0x1UL << PWR_CR4_WRFBUSYP_Pos)         /*!< 0x00008000 */
-#define PWR_CR4_WRFBUSYP               PWR_CR4_WRFBUSYP_Msk                    /*!< Wake-up radio busy polarity */
-
-#define PWR_CR4_C2BOOT_Pos             (15U)
-#define PWR_CR4_C2BOOT_Msk             (0x1UL << PWR_CR4_C2BOOT_Pos)           /*!< 0x00008000 */
-#define PWR_CR4_C2BOOT                 PWR_CR4_C2BOOT_Msk                      /*!< Boot CPU2 after reset or wakeup from Stop or Standby modes */
-
-/********************  Bit definition for PWR_SR1 register  ********************/
-#define PWR_SR1_WUF_Pos                (0U)
-#define PWR_SR1_WUF_Msk                (0x1FUL << PWR_SR1_WUF_Pos)             /*!< 0x00000007 */
-#define PWR_SR1_WUF                    PWR_SR1_WUF_Msk                         /*!< Wakeup Flags of all pins */
-#define PWR_SR1_WUF1_Pos               (0U)
-#define PWR_SR1_WUF1_Msk               (0x1UL << PWR_SR1_WUF1_Pos)             /*!< 0x00000001 */
-#define PWR_SR1_WUF1                   PWR_SR1_WUF1_Msk                        /*!< Wakeup Pin 1 [Flag 0] */
-#define PWR_SR1_WUF2_Pos               (1U)
-#define PWR_SR1_WUF2_Msk               (0x1UL << PWR_SR1_WUF2_Pos)             /*!< 0x00000002 */
-#define PWR_SR1_WUF2                   PWR_SR1_WUF2_Msk                        /*!< Wakeup Pin 2 [Flag 1] */
-#define PWR_SR1_WUF3_Pos               (2U)
-#define PWR_SR1_WUF3_Msk               (0x1UL << PWR_SR1_WUF3_Pos)             /*!< 0x00000004 */
-#define PWR_SR1_WUF3                   PWR_SR1_WUF3_Msk                        /*!< Wakeup Pin 3 [Flag 2] */
-
-#define PWR_SR1_WPVDF_Pos              (8U)
-#define PWR_SR1_WPVDF_Msk              (0x1UL << PWR_SR1_WPVDF_Pos)            /*!< 0x00000100 */
-#define PWR_SR1_WPVDF                  PWR_SR1_WPVDF_Msk                       /*!< Wakeup PVD flag */
-
-#define PWR_SR1_WRFBUSYF_Pos           (11U)
-#define PWR_SR1_WRFBUSYF_Msk           (0x1UL << PWR_SR1_WRFBUSYF_Pos)          /*!< 0x00000800 */
-#define PWR_SR1_WRFBUSYF               PWR_SR1_WRFBUSYF_Msk                     /*!< Wakeup radio busy flag */
-
-#define PWR_SR1_C2HF_Pos               (14U)
-#define PWR_SR1_C2HF_Msk               (0x1UL << PWR_SR1_C2HF_Pos)             /*!< 0x00004000 */
-#define PWR_SR1_C2HF                   PWR_SR1_C2HF_Msk                        /*!< CPU2 Hold interrupt flag */
-
-#define PWR_SR1_WUFI_Pos               (15U)
-#define PWR_SR1_WUFI_Msk               (0x1UL << PWR_SR1_WUFI_Pos)             /*!< 0x00008000 */
-#define PWR_SR1_WUFI                   PWR_SR1_WUFI_Msk                        /*!< Internal wakeup interrupt flag */
-
-/********************  Bit definition for PWR_SR2 register  ********************/
-#define PWR_SR2_C2BOOTS_Pos            (0U)
-#define PWR_SR2_C2BOOTS_Msk            (0x1UL << PWR_SR2_C2BOOTS_Pos)          /*!< 0x00000001 */
-#define PWR_SR2_C2BOOTS                PWR_SR2_C2BOOTS_Msk                     /*!< CPU2 boot or wakeup request source information */
-
-#define PWR_SR2_RFBUSYS_Pos            (1U)
-#define PWR_SR2_RFBUSYS_Msk            (0x1UL << PWR_SR2_RFBUSYS_Pos)          /*!< 0x00000002 */
-#define PWR_SR2_RFBUSYS                PWR_SR2_RFBUSYS_Msk                     /*!< Radio busy signal status */
-
-#define PWR_SR2_RFBUSYMS_Pos           (2U)
-#define PWR_SR2_RFBUSYMS_Msk           (0x1UL << PWR_SR2_RFBUSYMS_Pos)         /*!< 0x00000004 */
-#define PWR_SR2_RFBUSYMS               PWR_SR2_RFBUSYMS_Msk                    /*!< Radio busy masked signal status */
-
-#define PWR_SR2_SMPSRDY_Pos            (3U)
-#define PWR_SR2_SMPSRDY_Msk            (0x1UL << PWR_SR2_SMPSRDY_Pos)          /*!< 0x00000008 */
-#define PWR_SR2_SMPSRDY                PWR_SR2_SMPSRDY_Msk                     /*!< SMPS ready flag */
-#define PWR_SR2_LDORDY_Pos             (4U)
-#define PWR_SR2_LDORDY_Msk             (0x1UL << PWR_SR2_LDORDY_Pos)           /*!< 0x00000010 */
-#define PWR_SR2_LDORDY                 PWR_SR2_LDORDY_Msk                      /*!< LDO ready flag */
-
-#define PWR_SR2_RFEOLF_Pos             (5U)
-#define PWR_SR2_RFEOLF_Msk             (0x1UL << PWR_SR2_RFEOLF_Pos)           /*!< 0x00000020 */
-#define PWR_SR2_RFEOLF                 PWR_SR2_RFEOLF_Msk                      /*!< Radio end of life flag */
-
-#define PWR_SR2_REGMRS_Pos             (6U)
-#define PWR_SR2_REGMRS_Msk             (0x1UL << PWR_SR2_REGMRS_Pos)           /*!< 0x00000040 */
-#define PWR_SR2_REGMRS                 PWR_SR2_REGMRS_Msk                      /*!< Main regulator status */
-
-#define PWR_SR2_FLASHRDY_Pos           (7U)
-#define PWR_SR2_FLASHRDY_Msk           (0x1UL << PWR_SR2_FLASHRDY_Pos)         /*!< 0x00000080 */
-#define PWR_SR2_FLASHRDY               PWR_SR2_FLASHRDY_Msk                    /*!< Flash ready */
-
-#define PWR_SR2_REGLPS_Pos             (8U)
-#define PWR_SR2_REGLPS_Msk             (0x1UL << PWR_SR2_REGLPS_Pos)           /*!< 0x00000100 */
-#define PWR_SR2_REGLPS                 PWR_SR2_REGLPS_Msk                      /*!< Low-power regulator ready */
-#define PWR_SR2_REGLPF_Pos             (9U)
-#define PWR_SR2_REGLPF_Msk             (0x1UL << PWR_SR2_REGLPF_Pos)           /*!< 0x00000200 */
-#define PWR_SR2_REGLPF                 PWR_SR2_REGLPF_Msk                      /*!< Low-power regulator being used */
-
-#define PWR_SR2_VOSF_Pos               (10U)
-#define PWR_SR2_VOSF_Msk               (0x1UL << PWR_SR2_VOSF_Pos)             /*!< 0x00000400 */
-#define PWR_SR2_VOSF                   PWR_SR2_VOSF_Msk                        /*!< Voltage scaling flag    */
-#define PWR_SR2_PVDO_Pos               (11U)
-#define PWR_SR2_PVDO_Msk               (0x1UL << PWR_SR2_PVDO_Pos)             /*!< 0x00000800 */
-#define PWR_SR2_PVDO                   PWR_SR2_PVDO_Msk                        /*!< Power voltage detector output */
-
-#define PWR_SR2_PVMO3_Pos              (14U)
-#define PWR_SR2_PVMO3_Msk              (0x1UL << PWR_SR2_PVMO3_Pos)            /*!< 0x00004000 */
-#define PWR_SR2_PVMO3                  PWR_SR2_PVMO3_Msk                       /*!< Peripheral voltage monitor output 3: VDDA vs. 1.62V */
-
-/********************  Bit definition for PWR_SCR register  ********************/
-#define PWR_SCR_CWUF_Pos               (0U)
-#define PWR_SCR_CWUF_Msk               (0x7UL << PWR_SCR_CWUF_Pos)             /*!< 0x00000007 */
-#define PWR_SCR_CWUF                   PWR_SCR_CWUF_Msk                        /*!< Clear Wake-up Flags for all pins */
-#define PWR_SCR_CWUF1_Pos              (0U)
-#define PWR_SCR_CWUF1_Msk              (0x1UL << PWR_SCR_CWUF1_Pos)            /*!< 0x00000001 */
-#define PWR_SCR_CWUF1                  PWR_SCR_CWUF1_Msk                       /*!< Clear Wake-up Pin 1 [Flag 0] */
-#define PWR_SCR_CWUF2_Pos              (1U)
-#define PWR_SCR_CWUF2_Msk              (0x1UL << PWR_SCR_CWUF2_Pos)            /*!< 0x00000002 */
-#define PWR_SCR_CWUF2                  PWR_SCR_CWUF2_Msk                       /*!< Clear Wake-up Pin 2 [Flag 1] */
-#define PWR_SCR_CWUF3_Pos              (2U)
-#define PWR_SCR_CWUF3_Msk              (0x1UL << PWR_SCR_CWUF3_Pos)            /*!< 0x00000004 */
-#define PWR_SCR_CWUF3                  PWR_SCR_CWUF3_Msk                       /*!< Clear Wake-up Pin 3 [Flag 2] */
-
-#define PWR_SCR_CWPVDF_Pos             (8U)
-#define PWR_SCR_CWPVDF_Msk             (0x1UL << PWR_SCR_CWPVDF_Pos)           /*!< 0x00000100 */
-#define PWR_SCR_CWPVDF                 PWR_SCR_CWPVDF_Msk                      /*!< Clear wakeup PVD interrupt flag */
-
-#define PWR_SCR_CWRFBUSYF_Pos          (11U)
-#define PWR_SCR_CWRFBUSYF_Msk          (0x1UL << PWR_SCR_CWRFBUSYF_Pos)        /*!< 0x00000800 */
-#define PWR_SCR_CWRFBUSYF              PWR_SCR_CWRFBUSYF_Msk                   /*!< Clear Radio busy interrupt flag */
-
-#define PWR_SCR_CC2HF_Pos              (14U)
-#define PWR_SCR_CC2HF_Msk              (0x1UL << PWR_SCR_CC2HF_Pos)            /*!< 0x00004000 */
-#define PWR_SCR_CC2HF                  PWR_SCR_CC2HF_Msk                       /*!< Clear CPU2 Hold interrupt flag */
-
-/********************  Bit definition for PWR_CR5 register  ********************/
-#define PWR_CR5_RFEOLEN_Pos            (14U)
-#define PWR_CR5_RFEOLEN_Msk            (0x1UL << PWR_CR5_RFEOLEN_Pos)           /*!< 0x00004000 */
-#define PWR_CR5_RFEOLEN                PWR_CR5_RFEOLEN_Msk                      /*!< Enable Radio End Of Life detector enabled */
-
-#define PWR_CR5_SMPSEN_Pos             (15U)
-#define PWR_CR5_SMPSEN_Msk             (0x1UL << PWR_CR5_SMPSEN_Pos)           /*!< 0x00008000 */
-#define PWR_CR5_SMPSEN                 PWR_CR5_SMPSEN_Msk                      /*!< Enable SMPS Step Down converter SMPS mode enable */
-
-/********************  Bit definition for PWR_PUCRA register  *****************/
-#define PWR_PUCRA_PA0_Pos              (0U)
-#define PWR_PUCRA_PA0_Msk              (0x1UL << PWR_PUCRA_PA0_Pos)            /*!< 0x00000001 */
-#define PWR_PUCRA_PA0                  PWR_PUCRA_PA0_Msk                       /*!< Pin PA0 Pull-Up set */
-#define PWR_PUCRA_PA1_Pos              (1U)
-#define PWR_PUCRA_PA1_Msk              (0x1UL << PWR_PUCRA_PA1_Pos)            /*!< 0x00000002 */
-#define PWR_PUCRA_PA1                  PWR_PUCRA_PA1_Msk                       /*!< Pin PA1 Pull-Up set */
-#define PWR_PUCRA_PA2_Pos              (2U)
-#define PWR_PUCRA_PA2_Msk              (0x1UL << PWR_PUCRA_PA2_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRA_PA2                  PWR_PUCRA_PA2_Msk                       /*!< Pin PA2 Pull-Up set */
-#define PWR_PUCRA_PA3_Pos              (3U)
-#define PWR_PUCRA_PA3_Msk              (0x1UL << PWR_PUCRA_PA3_Pos)            /*!< 0x00000008 */
-#define PWR_PUCRA_PA3                  PWR_PUCRA_PA3_Msk                       /*!< Pin PA3 Pull-Up set */
-#define PWR_PUCRA_PA4_Pos              (4U)
-#define PWR_PUCRA_PA4_Msk              (0x1UL << PWR_PUCRA_PA4_Pos)            /*!< 0x00000010 */
-#define PWR_PUCRA_PA4                  PWR_PUCRA_PA4_Msk                       /*!< Pin PA4 Pull-Up set */
-#define PWR_PUCRA_PA5_Pos              (5U)
-#define PWR_PUCRA_PA5_Msk              (0x1UL << PWR_PUCRA_PA5_Pos)            /*!< 0x00000020 */
-#define PWR_PUCRA_PA5                  PWR_PUCRA_PA5_Msk                       /*!< Pin PA5 Pull-Up set */
-#define PWR_PUCRA_PA6_Pos              (6U)
-#define PWR_PUCRA_PA6_Msk              (0x1UL << PWR_PUCRA_PA6_Pos)            /*!< 0x00000040 */
-#define PWR_PUCRA_PA6                  PWR_PUCRA_PA6_Msk                       /*!< Pin PA6 Pull-Up set */
-#define PWR_PUCRA_PA7_Pos              (7U)
-#define PWR_PUCRA_PA7_Msk              (0x1UL << PWR_PUCRA_PA7_Pos)            /*!< 0x00000080 */
-#define PWR_PUCRA_PA7                  PWR_PUCRA_PA7_Msk                       /*!< Pin PA7 Pull-Up set */
-#define PWR_PUCRA_PA8_Pos              (8U)
-#define PWR_PUCRA_PA8_Msk              (0x1UL << PWR_PUCRA_PA8_Pos)            /*!< 0x00000100 */
-#define PWR_PUCRA_PA8                  PWR_PUCRA_PA8_Msk                       /*!< Pin PA8 Pull-Up set */
-#define PWR_PUCRA_PA9_Pos              (9U)
-#define PWR_PUCRA_PA9_Msk              (0x1UL << PWR_PUCRA_PA9_Pos)            /*!< 0x00000200 */
-#define PWR_PUCRA_PA9                  PWR_PUCRA_PA9_Msk                       /*!< Pin PA9 Pull-Up set */
-#define PWR_PUCRA_PA10_Pos             (10U)
-#define PWR_PUCRA_PA10_Msk             (0x1UL << PWR_PUCRA_PA10_Pos)           /*!< 0x00000400 */
-#define PWR_PUCRA_PA10                 PWR_PUCRA_PA10_Msk                      /*!< Pin PA10 Pull-Up set */
-#define PWR_PUCRA_PA11_Pos             (11U)
-#define PWR_PUCRA_PA11_Msk             (0x1UL << PWR_PUCRA_PA11_Pos)           /*!< 0x00000800 */
-#define PWR_PUCRA_PA11                 PWR_PUCRA_PA11_Msk                      /*!< Pin PA11 Pull-Up set */
-#define PWR_PUCRA_PA12_Pos             (12U)
-#define PWR_PUCRA_PA12_Msk             (0x1UL << PWR_PUCRA_PA12_Pos)           /*!< 0x00001000 */
-#define PWR_PUCRA_PA12                 PWR_PUCRA_PA12_Msk                      /*!< Pin PA12 Pull-Up set */
-#define PWR_PUCRA_PA13_Pos             (13U)
-#define PWR_PUCRA_PA13_Msk             (0x1UL << PWR_PUCRA_PA13_Pos)           /*!< 0x00002000 */
-#define PWR_PUCRA_PA13                 PWR_PUCRA_PA13_Msk                      /*!< Pin PA13 Pull-Up set */
-#define PWR_PUCRA_PA14_Pos             (14U)
-#define PWR_PUCRA_PA14_Msk             (0x1UL << PWR_PUCRA_PA14_Pos)           /*!< 0x00004000 */
-#define PWR_PUCRA_PA14                 PWR_PUCRA_PA14_Msk                      /*!< Pin PA14 Pull-Up set */
-#define PWR_PUCRA_PA15_Pos             (15U)
-#define PWR_PUCRA_PA15_Msk             (0x1UL << PWR_PUCRA_PA15_Pos)           /*!< 0x00008000 */
-#define PWR_PUCRA_PA15                 PWR_PUCRA_PA15_Msk                      /*!< Pin PA15 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRA register  *****************/
-#define PWR_PDCRA_PA0_Pos              (0U)
-#define PWR_PDCRA_PA0_Msk              (0x1UL << PWR_PDCRA_PA0_Pos)            /*!< 0x00000001 */
-#define PWR_PDCRA_PA0                  PWR_PDCRA_PA0_Msk                       /*!< Pin PA0 Pull-Down set */
-#define PWR_PDCRA_PA1_Pos              (1U)
-#define PWR_PDCRA_PA1_Msk              (0x1UL << PWR_PDCRA_PA1_Pos)            /*!< 0x00000002 */
-#define PWR_PDCRA_PA1                  PWR_PDCRA_PA1_Msk                       /*!< Pin PA1 Pull-Down set */
-#define PWR_PDCRA_PA2_Pos              (2U)
-#define PWR_PDCRA_PA2_Msk              (0x1UL << PWR_PDCRA_PA2_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRA_PA2                  PWR_PDCRA_PA2_Msk                       /*!< Pin PA2 Pull-Down set */
-#define PWR_PDCRA_PA3_Pos              (3U)
-#define PWR_PDCRA_PA3_Msk              (0x1UL << PWR_PDCRA_PA3_Pos)            /*!< 0x00000008 */
-#define PWR_PDCRA_PA3                  PWR_PDCRA_PA3_Msk                       /*!< Pin PA3 Pull-Down set */
-#define PWR_PDCRA_PA4_Pos              (4U)
-#define PWR_PDCRA_PA4_Msk              (0x1UL << PWR_PDCRA_PA4_Pos)            /*!< 0x00000010 */
-#define PWR_PDCRA_PA4                  PWR_PDCRA_PA4_Msk                       /*!< Pin PA4 Pull-Down set */
-#define PWR_PDCRA_PA5_Pos              (5U)
-#define PWR_PDCRA_PA5_Msk              (0x1UL << PWR_PDCRA_PA5_Pos)            /*!< 0x00000020 */
-#define PWR_PDCRA_PA5                  PWR_PDCRA_PA5_Msk                       /*!< Pin PA5 Pull-Down set */
-#define PWR_PDCRA_PA6_Pos              (6U)
-#define PWR_PDCRA_PA6_Msk              (0x1UL << PWR_PDCRA_PA6_Pos)            /*!< 0x00000040 */
-#define PWR_PDCRA_PA6                  PWR_PDCRA_PA6_Msk                       /*!< Pin PA6 Pull-Down set */
-#define PWR_PDCRA_PA7_Pos              (7U)
-#define PWR_PDCRA_PA7_Msk              (0x1UL << PWR_PDCRA_PA7_Pos)            /*!< 0x00000080 */
-#define PWR_PDCRA_PA7                  PWR_PDCRA_PA7_Msk                       /*!< Pin PA7 Pull-Down set */
-#define PWR_PDCRA_PA8_Pos              (8U)
-#define PWR_PDCRA_PA8_Msk              (0x1UL << PWR_PDCRA_PA8_Pos)            /*!< 0x00000100 */
-#define PWR_PDCRA_PA8                  PWR_PDCRA_PA8_Msk                       /*!< Pin PA8 Pull-Down set */
-#define PWR_PDCRA_PA9_Pos              (9U)
-#define PWR_PDCRA_PA9_Msk              (0x1UL << PWR_PDCRA_PA9_Pos)            /*!< 0x00000200 */
-#define PWR_PDCRA_PA9                  PWR_PDCRA_PA9_Msk                       /*!< Pin PA9 Pull-Down set */
-#define PWR_PDCRA_PA10_Pos             (10U)
-#define PWR_PDCRA_PA10_Msk             (0x1UL << PWR_PDCRA_PA10_Pos)           /*!< 0x00000400 */
-#define PWR_PDCRA_PA10                 PWR_PDCRA_PA10_Msk                      /*!< Pin PA10 Pull-Down set */
-#define PWR_PDCRA_PA11_Pos             (11U)
-#define PWR_PDCRA_PA11_Msk             (0x1UL << PWR_PDCRA_PA11_Pos)           /*!< 0x00000800 */
-#define PWR_PDCRA_PA11                 PWR_PDCRA_PA11_Msk                      /*!< Pin PA11 Pull-Down set */
-#define PWR_PDCRA_PA12_Pos             (12U)
-#define PWR_PDCRA_PA12_Msk             (0x1UL << PWR_PDCRA_PA12_Pos)           /*!< 0x00001000 */
-#define PWR_PDCRA_PA12                 PWR_PDCRA_PA12_Msk                      /*!< Pin PA12 Pull-Down set */
-#define PWR_PDCRA_PA13_Pos             (13U)
-#define PWR_PDCRA_PA13_Msk             (0x1UL << PWR_PDCRA_PA13_Pos)           /*!< 0x00002000 */
-#define PWR_PDCRA_PA13                 PWR_PDCRA_PA13_Msk                      /*!< Pin PA13 Pull-Down set */
-#define PWR_PDCRA_PA14_Pos             (14U)
-#define PWR_PDCRA_PA14_Msk             (0x1UL << PWR_PDCRA_PA14_Pos)           /*!< 0x00004000 */
-#define PWR_PDCRA_PA14                 PWR_PDCRA_PA14_Msk                      /*!< Pin PA14 Pull-Down set */
-#define PWR_PDCRA_PA15_Pos             (15U)
-#define PWR_PDCRA_PA15_Msk             (0x1UL << PWR_PDCRA_PA15_Pos)           /*!< 0x00008000 */
-#define PWR_PDCRA_PA15                 PWR_PDCRA_PA15_Msk                      /*!< Pin PA15 Pull-Down set */
-
-/********************  Bit definition for PWR_PUCRB register  *****************/
-#define PWR_PUCRB_PB0_Pos              (0U)
-#define PWR_PUCRB_PB0_Msk              (0x1UL << PWR_PUCRB_PB0_Pos)            /*!< 0x00000001 */
-#define PWR_PUCRB_PB0                  PWR_PUCRB_PB0_Msk                       /*!< Pin PB0 Pull-Up set */
-#define PWR_PUCRB_PB1_Pos              (1U)
-#define PWR_PUCRB_PB1_Msk              (0x1UL << PWR_PUCRB_PB1_Pos)            /*!< 0x00000002 */
-#define PWR_PUCRB_PB1                  PWR_PUCRB_PB1_Msk                       /*!< Pin PB1 Pull-Up set */
-#define PWR_PUCRB_PB2_Pos              (2U)
-#define PWR_PUCRB_PB2_Msk              (0x1UL << PWR_PUCRB_PB2_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRB_PB2                  PWR_PUCRB_PB2_Msk                       /*!< Pin PB2 Pull-Up set */
-#define PWR_PUCRB_PB3_Pos              (3U)
-#define PWR_PUCRB_PB3_Msk              (0x1UL << PWR_PUCRB_PB3_Pos)            /*!< 0x00000008 */
-#define PWR_PUCRB_PB3                  PWR_PUCRB_PB3_Msk                       /*!< Pin PB3 Pull-Up set */
-#define PWR_PUCRB_PB4_Pos              (4U)
-#define PWR_PUCRB_PB4_Msk              (0x1UL << PWR_PUCRB_PB4_Pos)            /*!< 0x00000010 */
-#define PWR_PUCRB_PB4                  PWR_PUCRB_PB4_Msk                       /*!< Pin PB4 Pull-Up set */
-#define PWR_PUCRB_PB5_Pos              (5U)
-#define PWR_PUCRB_PB5_Msk              (0x1UL << PWR_PUCRB_PB5_Pos)            /*!< 0x00000020 */
-#define PWR_PUCRB_PB5                  PWR_PUCRB_PB5_Msk                       /*!< Pin PB5 Pull-Up set */
-#define PWR_PUCRB_PB6_Pos              (6U)
-#define PWR_PUCRB_PB6_Msk              (0x1UL << PWR_PUCRB_PB6_Pos)            /*!< 0x00000040 */
-#define PWR_PUCRB_PB6                  PWR_PUCRB_PB6_Msk                       /*!< Pin PB6 Pull-Up set */
-#define PWR_PUCRB_PB7_Pos              (7U)
-#define PWR_PUCRB_PB7_Msk              (0x1UL << PWR_PUCRB_PB7_Pos)            /*!< 0x00000080 */
-#define PWR_PUCRB_PB7                  PWR_PUCRB_PB7_Msk                       /*!< Pin PB7 Pull-Up set */
-#define PWR_PUCRB_PB8_Pos              (8U)
-#define PWR_PUCRB_PB8_Msk              (0x1UL << PWR_PUCRB_PB8_Pos)            /*!< 0x00000100 */
-#define PWR_PUCRB_PB8                  PWR_PUCRB_PB8_Msk                       /*!< Pin PB8 Pull-Up set */
-#define PWR_PUCRB_PB9_Pos              (9U)
-#define PWR_PUCRB_PB9_Msk              (0x1UL << PWR_PUCRB_PB9_Pos)            /*!< 0x00000200 */
-#define PWR_PUCRB_PB9                  PWR_PUCRB_PB9_Msk                       /*!< Pin PB9 Pull-Up set */
-#define PWR_PUCRB_PB10_Pos             (10U)
-#define PWR_PUCRB_PB10_Msk             (0x1UL << PWR_PUCRB_PB10_Pos)           /*!< 0x00000400 */
-#define PWR_PUCRB_PB10                 PWR_PUCRB_PB10_Msk                      /*!< Pin PB10 Pull-Up set */
-#define PWR_PUCRB_PB11_Pos             (11U)
-#define PWR_PUCRB_PB11_Msk             (0x1UL << PWR_PUCRB_PB11_Pos)           /*!< 0x00000800 */
-#define PWR_PUCRB_PB11                 PWR_PUCRB_PB11_Msk                      /*!< Pin PB11 Pull-Up set */
-#define PWR_PUCRB_PB12_Pos             (12U)
-#define PWR_PUCRB_PB12_Msk             (0x1UL << PWR_PUCRB_PB12_Pos)           /*!< 0x00001000 */
-#define PWR_PUCRB_PB12                 PWR_PUCRB_PB12_Msk                      /*!< Pin PB12 Pull-Up set */
-#define PWR_PUCRB_PB13_Pos             (13U)
-#define PWR_PUCRB_PB13_Msk             (0x1UL << PWR_PUCRB_PB13_Pos)           /*!< 0x00002000 */
-#define PWR_PUCRB_PB13                 PWR_PUCRB_PB13_Msk                      /*!< Pin PB13 Pull-Up set */
-#define PWR_PUCRB_PB14_Pos             (14U)
-#define PWR_PUCRB_PB14_Msk             (0x1UL << PWR_PUCRB_PB14_Pos)           /*!< 0x00004000 */
-#define PWR_PUCRB_PB14                 PWR_PUCRB_PB14_Msk                      /*!< Pin PB14 Pull-Up set */
-#define PWR_PUCRB_PB15_Pos             (15U)
-#define PWR_PUCRB_PB15_Msk             (0x1UL << PWR_PUCRB_PB15_Pos)           /*!< 0x00008000 */
-#define PWR_PUCRB_PB15                 PWR_PUCRB_PB15_Msk                      /*!< Pin PB15 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRB register  *****************/
-#define PWR_PDCRB_PB0_Pos              (0U)
-#define PWR_PDCRB_PB0_Msk              (0x1UL << PWR_PDCRB_PB0_Pos)            /*!< 0x00000001 */
-#define PWR_PDCRB_PB0                  PWR_PDCRB_PB0_Msk                       /*!< Pin PB0 Pull-Down set */
-#define PWR_PDCRB_PB1_Pos              (1U)
-#define PWR_PDCRB_PB1_Msk              (0x1UL << PWR_PDCRB_PB1_Pos)            /*!< 0x00000002 */
-#define PWR_PDCRB_PB1                  PWR_PDCRB_PB1_Msk                       /*!< Pin PB1 Pull-Down set */
-#define PWR_PDCRB_PB2_Pos              (2U)
-#define PWR_PDCRB_PB2_Msk              (0x1UL << PWR_PDCRB_PB2_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRB_PB2                  PWR_PDCRB_PB2_Msk                       /*!< Pin PB2 Pull-Down set */
-#define PWR_PDCRB_PB3_Pos              (3U)
-#define PWR_PDCRB_PB3_Msk              (0x1UL << PWR_PDCRB_PB3_Pos)            /*!< 0x00000008 */
-#define PWR_PDCRB_PB3                  PWR_PDCRB_PB3_Msk                       /*!< Pin PB3 Pull-Down set */
-#define PWR_PDCRB_PB4_Pos              (4U)
-#define PWR_PDCRB_PB4_Msk              (0x1UL << PWR_PDCRB_PB4_Pos)            /*!< 0x00000010 */
-#define PWR_PDCRB_PB4                  PWR_PDCRB_PB4_Msk                       /*!< Pin PB4 Pull-Down set */
-#define PWR_PDCRB_PB5_Pos              (5U)
-#define PWR_PDCRB_PB5_Msk              (0x1UL << PWR_PDCRB_PB5_Pos)            /*!< 0x00000020 */
-#define PWR_PDCRB_PB5                  PWR_PDCRB_PB5_Msk                       /*!< Pin PB5 Pull-Down set */
-#define PWR_PDCRB_PB6_Pos              (6U)
-#define PWR_PDCRB_PB6_Msk              (0x1UL << PWR_PDCRB_PB6_Pos)            /*!< 0x00000040 */
-#define PWR_PDCRB_PB6                  PWR_PDCRB_PB6_Msk                       /*!< Pin PB6 Pull-Down set */
-#define PWR_PDCRB_PB7_Pos              (7U)
-#define PWR_PDCRB_PB7_Msk              (0x1UL << PWR_PDCRB_PB7_Pos)            /*!< 0x00000080 */
-#define PWR_PDCRB_PB7                  PWR_PDCRB_PB7_Msk                       /*!< Pin PB7 Pull-Down set */
-#define PWR_PDCRB_PB8_Pos              (8U)
-#define PWR_PDCRB_PB8_Msk              (0x1UL << PWR_PDCRB_PB8_Pos)            /*!< 0x00000100 */
-#define PWR_PDCRB_PB8                  PWR_PDCRB_PB8_Msk                       /*!< Pin PB8 Pull-Down set */
-#define PWR_PDCRB_PB9_Pos              (9U)
-#define PWR_PDCRB_PB9_Msk              (0x1UL << PWR_PDCRB_PB9_Pos)            /*!< 0x00000200 */
-#define PWR_PDCRB_PB9                  PWR_PDCRB_PB9_Msk                       /*!< Pin PB9 Pull-Down set */
-#define PWR_PDCRB_PB10_Pos             (10U)
-#define PWR_PDCRB_PB10_Msk             (0x1UL << PWR_PDCRB_PB10_Pos)           /*!< 0x00000400 */
-#define PWR_PDCRB_PB10                 PWR_PDCRB_PB10_Msk                      /*!< Pin PB10 Pull-Down set */
-#define PWR_PDCRB_PB11_Pos             (11U)
-#define PWR_PDCRB_PB11_Msk             (0x1UL << PWR_PDCRB_PB11_Pos)           /*!< 0x00000800 */
-#define PWR_PDCRB_PB11                 PWR_PDCRB_PB11_Msk                      /*!< Pin PB11 Pull-Down set */
-#define PWR_PDCRB_PB12_Pos             (12U)
-#define PWR_PDCRB_PB12_Msk             (0x1UL << PWR_PDCRB_PB12_Pos)           /*!< 0x00001000 */
-#define PWR_PDCRB_PB12                 PWR_PDCRB_PB12_Msk                      /*!< Pin PB12 Pull-Down set */
-#define PWR_PDCRB_PB13_Pos             (13U)
-#define PWR_PDCRB_PB13_Msk             (0x1UL << PWR_PDCRB_PB13_Pos)           /*!< 0x00002000 */
-#define PWR_PDCRB_PB13                 PWR_PDCRB_PB13_Msk                      /*!< Pin PB13 Pull-Down set */
-#define PWR_PDCRB_PB14_Pos             (14U)
-#define PWR_PDCRB_PB14_Msk             (0x1UL << PWR_PDCRB_PB14_Pos)           /*!< 0x00004000 */
-#define PWR_PDCRB_PB14                 PWR_PDCRB_PB14_Msk                      /*!< Pin PB14 Pull-Down set */
-#define PWR_PDCRB_PB15_Pos             (15U)
-#define PWR_PDCRB_PB15_Msk             (0x1UL << PWR_PDCRB_PB15_Pos)           /*!< 0x00008000 */
-#define PWR_PDCRB_PB15                 PWR_PDCRB_PB15_Msk                      /*!< Pin PB15 Pull-Down set */
-
-/********************  Bit definition for PWR_PUCRC register  *****************/
-#define PWR_PUCRC_PC0_Pos              (0U)
-#define PWR_PUCRC_PC0_Msk              (0x1UL << PWR_PUCRC_PC0_Pos)            /*!< 0x00000001 */
-#define PWR_PUCRC_PC0                  PWR_PUCRC_PC0_Msk                       /*!< Pin PC0 Pull-Up set */
-#define PWR_PUCRC_PC1_Pos              (1U)
-#define PWR_PUCRC_PC1_Msk              (0x1UL << PWR_PUCRC_PC1_Pos)            /*!< 0x00000002 */
-#define PWR_PUCRC_PC1                  PWR_PUCRC_PC1_Msk                       /*!< Pin PC1 Pull-Up set */
-#define PWR_PUCRC_PC2_Pos              (2U)
-#define PWR_PUCRC_PC2_Msk              (0x1UL << PWR_PUCRC_PC2_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRC_PC2                  PWR_PUCRC_PC2_Msk                       /*!< Pin PC2 Pull-Up set */
-#define PWR_PUCRC_PC3_Pos              (3U)
-#define PWR_PUCRC_PC3_Msk              (0x1UL << PWR_PUCRC_PC3_Pos)            /*!< 0x00000008 */
-#define PWR_PUCRC_PC3                  PWR_PUCRC_PC3_Msk                       /*!< Pin PC3 Pull-Up set */
-#define PWR_PUCRC_PC4_Pos              (4U)
-#define PWR_PUCRC_PC4_Msk              (0x1UL << PWR_PUCRC_PC4_Pos)            /*!< 0x00000010 */
-#define PWR_PUCRC_PC4                  PWR_PUCRC_PC4_Msk                       /*!< Pin PC4 Pull-Up set */
-#define PWR_PUCRC_PC5_Pos              (5U)
-#define PWR_PUCRC_PC5_Msk              (0x1UL << PWR_PUCRC_PC5_Pos)            /*!< 0x00000020 */
-#define PWR_PUCRC_PC5                  PWR_PUCRC_PC5_Msk                       /*!< Pin PC5 Pull-Up set */
-#define PWR_PUCRC_PC6_Pos              (6U)
-#define PWR_PUCRC_PC6_Msk              (0x1UL << PWR_PUCRC_PC6_Pos)            /*!< 0x00000040 */
-#define PWR_PUCRC_PC6                  PWR_PUCRC_PC6_Msk                       /*!< Pin PC6 Pull-Up set */
-#define PWR_PUCRC_PC13_Pos             (13U)
-#define PWR_PUCRC_PC13_Msk             (0x1UL << PWR_PUCRC_PC13_Pos)           /*!< 0x00002000 */
-#define PWR_PUCRC_PC13                 PWR_PUCRC_PC13_Msk                      /*!< Pin PC13 Pull-Up set */
-#define PWR_PUCRC_PC14_Pos             (14U)
-#define PWR_PUCRC_PC14_Msk             (0x1UL << PWR_PUCRC_PC14_Pos)           /*!< 0x00004000 */
-#define PWR_PUCRC_PC14                 PWR_PUCRC_PC14_Msk                      /*!< Pin PC14 Pull-Up set */
-#define PWR_PUCRC_PC15_Pos             (15U)
-#define PWR_PUCRC_PC15_Msk             (0x1UL << PWR_PUCRC_PC15_Pos)           /*!< 0x00008000 */
-#define PWR_PUCRC_PC15                 PWR_PUCRC_PC15_Msk                      /*!< Pin PC15 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRC register  *****************/
-#define PWR_PDCRC_PC0_Pos              (0U)
-#define PWR_PDCRC_PC0_Msk              (0x1UL << PWR_PDCRC_PC0_Pos)            /*!< 0x00000001 */
-#define PWR_PDCRC_PC0                  PWR_PDCRC_PC0_Msk                       /*!< Pin PC0 Pull-Down set */
-#define PWR_PDCRC_PC1_Pos              (1U)
-#define PWR_PDCRC_PC1_Msk              (0x1UL << PWR_PDCRC_PC1_Pos)            /*!< 0x00000002 */
-#define PWR_PDCRC_PC1                  PWR_PDCRC_PC1_Msk                       /*!< Pin PC1 Pull-Down set */
-#define PWR_PDCRC_PC2_Pos              (2U)
-#define PWR_PDCRC_PC2_Msk              (0x1UL << PWR_PDCRC_PC2_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRC_PC2                  PWR_PDCRC_PC2_Msk                       /*!< Pin PC2 Pull-Down set */
-#define PWR_PDCRC_PC3_Pos              (3U)
-#define PWR_PDCRC_PC3_Msk              (0x1UL << PWR_PDCRC_PC3_Pos)            /*!< 0x00000008 */
-#define PWR_PDCRC_PC3                  PWR_PDCRC_PC3_Msk                       /*!< Pin PC3 Pull-Down set */
-#define PWR_PDCRC_PC4_Pos              (4U)
-#define PWR_PDCRC_PC4_Msk              (0x1UL << PWR_PDCRC_PC4_Pos)            /*!< 0x00000010 */
-#define PWR_PDCRC_PC4                  PWR_PDCRC_PC4_Msk                       /*!< Pin PC4 Pull-Down set */
-#define PWR_PDCRC_PC5_Pos              (5U)
-#define PWR_PDCRC_PC5_Msk              (0x1UL << PWR_PDCRC_PC5_Pos)            /*!< 0x00000020 */
-#define PWR_PDCRC_PC5                  PWR_PDCRC_PC5_Msk                       /*!< Pin PC5 Pull-Down set */
-#define PWR_PDCRC_PC6_Pos              (6U)
-#define PWR_PDCRC_PC6_Msk              (0x1UL << PWR_PDCRC_PC6_Pos)            /*!< 0x00000040 */
-#define PWR_PDCRC_PC6                  PWR_PDCRC_PC6_Msk                       /*!< Pin PC6 Pull-Down set */
-#define PWR_PDCRC_PC13_Pos             (13U)
-#define PWR_PDCRC_PC13_Msk             (0x1UL << PWR_PDCRC_PC13_Pos)           /*!< 0x00002000 */
-#define PWR_PDCRC_PC13                 PWR_PDCRC_PC13_Msk                      /*!< Pin PC13 Pull-Down set */
-#define PWR_PDCRC_PC14_Pos             (14U)
-#define PWR_PDCRC_PC14_Msk             (0x1UL << PWR_PDCRC_PC14_Pos)           /*!< 0x00004000 */
-#define PWR_PDCRC_PC14                 PWR_PDCRC_PC14_Msk                      /*!< Pin PC14 Pull-Down set */
-#define PWR_PDCRC_PC15_Pos             (15U)
-#define PWR_PDCRC_PC15_Msk             (0x1UL << PWR_PDCRC_PC15_Pos)           /*!< 0x00008000 */
-#define PWR_PDCRC_PC15                 PWR_PDCRC_PC15_Msk                      /*!< Pin PC15 Pull-Down set */
-
-/********************  Bit definition for PWR_PUCRH register  *****************/
-#define PWR_PUCRH_PH3_Pos              (3U)
-#define PWR_PUCRH_PH3_Msk              (0x1UL << PWR_PUCRH_PH3_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRH_PH3                  PWR_PUCRH_PH3_Msk                       /*!< Pin PH3 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRH register  *****************/
-#define PWR_PDCRH_PH3_Pos              (3U)
-#define PWR_PDCRH_PH3_Msk              (0x1UL << PWR_PDCRH_PH3_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRH_PH3                  PWR_PDCRH_PH3_Msk                       /*!< Pin PH3 Pull-Down set */
-
-/********************  Bit definition for PWR_C2CR1 register  ********************/
-#define PWR_C2CR1_LPMS_Pos             (0U)
-#define PWR_C2CR1_LPMS_Msk             (0x7UL << PWR_C2CR1_LPMS_Pos)           /*!< 0x00000007 */
-#define PWR_C2CR1_LPMS                 PWR_C2CR1_LPMS_Msk                      /*!< Low Power Mode Selection for CPU2 */
-#define PWR_C2CR1_LPMS_0               (0x1UL << PWR_C2CR1_LPMS_Pos)           /*!< 0x00000001 */
-#define PWR_C2CR1_LPMS_1               (0x2UL << PWR_C2CR1_LPMS_Pos)           /*!< 0x00000002 */
-#define PWR_C2CR1_LPMS_2               (0x4UL << PWR_C2CR1_LPMS_Pos)           /*!< 0x00000004 */
-
-#define PWR_C2CR1_FPDR_Pos             (4U)
-#define PWR_C2CR1_FPDR_Msk             (0x1UL << PWR_C2CR1_FPDR_Pos)           /*!< 0x00000010 */
-#define PWR_C2CR1_FPDR                 PWR_C2CR1_FPDR_Msk                      /*!< Flash power down mode during LPrun for CPU2 */
-
-#define PWR_C2CR1_FPDS_Pos             (5U)
-#define PWR_C2CR1_FPDS_Msk             (0x1UL << PWR_C2CR1_FPDS_Pos)           /*!< 0x00000020 */
-#define PWR_C2CR1_FPDS                 PWR_C2CR1_FPDS_Msk                      /*!< Flash power down mode during LPsleep for CPU2 */
-
-/********************  Bit definition for PWR_C2CR3 register  ********************/
-#define PWR_C2CR3_EWUP_Pos             (0U)
-#define PWR_C2CR3_EWUP_Msk             (0x07UL << PWR_C2CR3_EWUP_Pos)           /*!< 0x00000007 */
-#define PWR_C2CR3_EWUP                 PWR_C2CR3_EWUP_Msk                       /*!< Enable all external Wake-Up lines for CPU2 */
-#define PWR_C2CR3_EWUP1_Pos            (0U)
-#define PWR_C2CR3_EWUP1_Msk            (0x1UL << PWR_C2CR3_EWUP1_Pos)           /*!< 0x00000001 */
-#define PWR_C2CR3_EWUP1                PWR_C2CR3_EWUP1_Msk                      /*!< Enable external WKUP Pin 1 [line 0] for CPU2 */
-#define PWR_C2CR3_EWUP2_Pos            (1U)
-#define PWR_C2CR3_EWUP2_Msk            (0x1UL << PWR_C2CR3_EWUP2_Pos)           /*!< 0x00000002 */
-#define PWR_C2CR3_EWUP2                PWR_C2CR3_EWUP2_Msk                      /*!< Enable external WKUP Pin 2 [line 1] for CPU2 */
-#define PWR_C2CR3_EWUP3_Pos            (2U)
-#define PWR_C2CR3_EWUP3_Msk            (0x1UL << PWR_C2CR3_EWUP3_Pos)           /*!< 0x00000004 */
-#define PWR_C2CR3_EWUP3                PWR_C2CR3_EWUP3_Msk                      /*!< Enable external WKUP Pin 3 [line 2] for CPU2 */
-
-#define PWR_C2CR3_EWPVD_Pos            (8U)
-#define PWR_C2CR3_EWPVD_Msk            (0x1UL << PWR_C2CR3_EWPVD_Pos)         /*!< 0x00000100 */
-#define PWR_C2CR3_EWPVD                PWR_C2CR3_EWPVD_Msk                    /*!< Enable wakeup PVD for CPU2 */
-
-#define PWR_C2CR3_APC_Pos              (10U)
-#define PWR_C2CR3_APC_Msk              (0x1UL << PWR_C2CR3_APC_Pos)            /*!< 0x00000400 */
-#define PWR_C2CR3_APC                  PWR_C2CR3_APC_Msk                       /*!< Apply pull-up and pull-down configuration for CPU2 */
-
-#define PWR_C2CR3_EWRFBUSY_Pos         (11U)
-#define PWR_C2CR3_EWRFBUSY_Msk         (0x1UL << PWR_C2CR3_EWRFBUSY_Pos)       /*!< 0x00000800 */
-#define PWR_C2CR3_EWRFBUSY             PWR_C2CR3_EWRFBUSY_Msk                  /*!< Enable Radio busy IRQ and wake-up for CPU2 */
-#define PWR_C2CR3_EWRFIRQ_Pos          (13U)
-#define PWR_C2CR3_EWRFIRQ_Msk          (0x1UL << PWR_C2CR3_EWRFIRQ_Pos)        /*!< 0x00002000 */
-#define PWR_C2CR3_EWRFIRQ              PWR_C2CR3_EWRFIRQ_Msk                   /*!< Enable Radio IRQ[2:0] and wake-up for CPU2 */
-
-#define PWR_C2CR3_EIWUL_Pos            (15U)
-#define PWR_C2CR3_EIWUL_Msk            (0x1UL << PWR_C2CR3_EIWUL_Pos)          /*!< 0x00008000 */
-#define PWR_C2CR3_EIWUL                PWR_C2CR3_EIWUL_Msk                     /*!< Internal Wake-Up line interrupt for CPU2 */
-
-/********************  Bit definition for PWR_EXTSCR register  ********************/
-#define PWR_EXTSCR_C1CSSF_Pos          (0U)
-#define PWR_EXTSCR_C1CSSF_Msk          (0x1UL << PWR_EXTSCR_C1CSSF_Pos)        /*!< 0x00000001 */
-#define PWR_EXTSCR_C1CSSF              PWR_EXTSCR_C1CSSF_Msk                   /*!< Clear standby and stop flags for CPU1 */
-#define PWR_EXTSCR_C2CSSF_Pos          (1U)
-#define PWR_EXTSCR_C2CSSF_Msk          (0x1UL << PWR_EXTSCR_C2CSSF_Pos)        /*!< 0x00000002 */
-#define PWR_EXTSCR_C2CSSF              PWR_EXTSCR_C2CSSF_Msk                   /*!< Clear standby and stop flags for CPU2 */
-
-#define PWR_EXTSCR_C1SBF_Pos           (8U)
-#define PWR_EXTSCR_C1SBF_Msk           (0x1UL << PWR_EXTSCR_C1SBF_Pos)         /*!< 0x00000100 */
-#define PWR_EXTSCR_C1SBF               PWR_EXTSCR_C1SBF_Msk                    /*!< System standby flag for CPU1 */
-#define PWR_EXTSCR_C1STOP2F_Pos        (9U)
-#define PWR_EXTSCR_C1STOP2F_Msk        (0x1UL << PWR_EXTSCR_C1STOP2F_Pos)      /*!< 0x00000200 */
-#define PWR_EXTSCR_C1STOP2F            PWR_EXTSCR_C1STOP2F_Msk                 /*!< System stop2 flag for CPU1 */
-#define PWR_EXTSCR_C1STOPF_Pos         (10U)
-#define PWR_EXTSCR_C1STOPF_Msk         (0x1UL << PWR_EXTSCR_C1STOPF_Pos)       /*!< 0x00000400 */
-#define PWR_EXTSCR_C1STOPF             PWR_EXTSCR_C1STOPF_Msk                  /*!< System stop0 or stop1 flag for CPU1 */
-
-#define PWR_EXTSCR_C2SBF_Pos           (11U)
-#define PWR_EXTSCR_C2SBF_Msk           (0x1UL << PWR_EXTSCR_C2SBF_Pos)         /*!< 0x00000800 */
-#define PWR_EXTSCR_C2SBF               PWR_EXTSCR_C2SBF_Msk                    /*!< System standby flag for CPU2 */
-#define PWR_EXTSCR_C2STOP2F_Pos        (12U)
-#define PWR_EXTSCR_C2STOP2F_Msk        (0x1UL << PWR_EXTSCR_C2STOP2F_Pos)      /*!< 0x00001000 */
-#define PWR_EXTSCR_C2STOP2F            PWR_EXTSCR_C2STOP2F_Msk                 /*!< System stop2 flag for CPU2 */
-#define PWR_EXTSCR_C2STOPF_Pos         (13U)
-#define PWR_EXTSCR_C2STOPF_Msk         (0x1UL << PWR_EXTSCR_C2STOPF_Pos)       /*!< 0x00002000 */
-#define PWR_EXTSCR_C2STOPF             PWR_EXTSCR_C2STOPF_Msk                  /*!< System stop0 or stop1 flag for CPU2 */
-
-#define PWR_EXTSCR_C1DS_Pos            (14U)
-#define PWR_EXTSCR_C1DS_Msk            (0x1UL << PWR_EXTSCR_C1DS_Pos)          /*!< 0x00004000 */
-#define PWR_EXTSCR_C1DS                PWR_EXTSCR_C1DS_Msk                     /*!< CPU1 deepsleep mode flag */
-#define PWR_EXTSCR_C2DS_Pos            (15U)
-#define PWR_EXTSCR_C2DS_Msk            (0x1UL << PWR_EXTSCR_C2DS_Pos)          /*!< 0x00008000 */
-#define PWR_EXTSCR_C2DS                PWR_EXTSCR_C2DS_Msk                     /*!< CPU2 deepsleep mode flag */
-
-/********************  Bit definition for PWR_SECCFGR register  ********************/
-#define PWR_SECCFGR_C2EWILA_Pos        (15U)
-#define PWR_SECCFGR_C2EWILA_Msk        (0x1UL << PWR_SECCFGR_C2EWILA_Pos)      /*!< 0x00008000 */
-#define PWR_SECCFGR_C2EWILA            PWR_SECCFGR_C2EWILA_Msk                 /*!< CPU2 illegal access interrupt enable */
-
-/********************  Bit definition for PWR_SUBGHZSPICR register  ********************/
-#define PWR_SUBGHZSPICR_NSS_Pos         (15U)
-#define PWR_SUBGHZSPICR_NSS_Msk         (0x1UL << PWR_SUBGHZSPICR_NSS_Pos)       /*!< 0x00008000 */
-#define PWR_SUBGHZSPICR_NSS             PWR_SUBGHZSPICR_NSS_Msk                  /*!< Sub-GHz radio SUBGHZSPI_NSS control */
-
-/********************  Bit definition for PWR_RSSCMDR register  ********************/
-#define PWR_RSSCMDR_RSSCMD_Pos         (0U)
-#define PWR_RSSCMDR_RSSCMD_Msk         (0xFFUL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x000000FF */
-#define PWR_RSSCMDR_RSSCMD             PWR_RSSCMDR_RSSCMD_Msk                  /*!< RSS command */
-#define PWR_RSSCMDR_RSSCMD_0           (0x01UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000001 */
-#define PWR_RSSCMDR_RSSCMD_1           (0x02UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000002 */
-#define PWR_RSSCMDR_RSSCMD_2           (0x04UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000004 */
-#define PWR_RSSCMDR_RSSCMD_3           (0x08UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000008 */
-#define PWR_RSSCMDR_RSSCMD_4           (0x10UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000010 */
-#define PWR_RSSCMDR_RSSCMD_5           (0x20UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000020 */
-#define PWR_RSSCMDR_RSSCMD_6           (0x40UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000040 */
-#define PWR_RSSCMDR_RSSCMD_7           (0x80UL << PWR_RSSCMDR_RSSCMD_Pos)      /*!< 0x00000080 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RCC_CR register  *****************/
-#define RCC_CR_MSION_Pos                     (0U)
-#define RCC_CR_MSION_Msk                     (0x1UL << RCC_CR_MSION_Pos)       /*!< 0x00000001 */
-#define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
-#define RCC_CR_MSIRDY_Pos                    (1U)
-#define RCC_CR_MSIRDY_Msk                    (0x1UL << RCC_CR_MSIRDY_Pos)      /*!< 0x00000002 */
-#define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
-#define RCC_CR_MSIPLLEN_Pos                  (2U)
-#define RCC_CR_MSIPLLEN_Msk                  (0x1UL << RCC_CR_MSIPLLEN_Pos)    /*!< 0x00000004 */
-#define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
-#define RCC_CR_MSIRGSEL_Pos                  (3U)
-#define RCC_CR_MSIRGSEL_Msk                  (0x1UL << RCC_CR_MSIRGSEL_Pos)    /*!< 0x00000008 */
-#define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
-
-/*!< MSIRANGE configuration : 12 frequency ranges available */
-#define RCC_CR_MSIRANGE_Pos                  (4U)
-#define RCC_CR_MSIRANGE_Msk                  (0xFUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000F0 */
-#define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
-#define RCC_CR_MSIRANGE_0                    (0x0UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000000 */
-#define RCC_CR_MSIRANGE_1                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */
-#define RCC_CR_MSIRANGE_2                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */
-#define RCC_CR_MSIRANGE_3                    (0x3UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000030 */
-#define RCC_CR_MSIRANGE_4                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */
-#define RCC_CR_MSIRANGE_5                    (0x5UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000050 */
-#define RCC_CR_MSIRANGE_6                    (0x6UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000060 */
-#define RCC_CR_MSIRANGE_7                    (0x7UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000070 */
-#define RCC_CR_MSIRANGE_8                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */
-#define RCC_CR_MSIRANGE_9                    (0x9UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000090 */
-#define RCC_CR_MSIRANGE_10                   (0xAUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000A0 */
-#define RCC_CR_MSIRANGE_11                   (0xBUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000B0 */
-
-#define RCC_CR_HSION_Pos                     (8U)
-#define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
-#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
-#define RCC_CR_HSIKERON_Pos                  (9U)
-#define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
-#define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                    (10U)
-#define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
-#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
-#define RCC_CR_HSIASFS_Pos                   (11U)
-#define RCC_CR_HSIASFS_Msk                   (0x1UL << RCC_CR_HSIASFS_Pos)     /*!< 0x00000800 */
-#define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
-#define RCC_CR_HSIKERDY_Pos                  (12U)
-#define RCC_CR_HSIKERDY_Msk                  (0x1UL << RCC_CR_HSIKERDY_Pos)     /*!< 0x00001000 */
-#define RCC_CR_HSIKERDY                       RCC_CR_HSIKERDY_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel ready flag*/
-
-#define RCC_CR_HSEON_Pos                     (16U)
-#define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
-#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
-#define RCC_CR_HSERDY_Pos                    (17U)
-#define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
-#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
-#define RCC_CR_CSSON_Pos                     (19U)
-#define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
-#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
-#define RCC_CR_HSEPRE_Pos                    (20U)
-#define RCC_CR_HSEPRE_Msk                    (0x1UL << RCC_CR_HSEPRE_Pos)       /*!< 0x00100000 */
-#define RCC_CR_HSEPRE                        RCC_CR_HSEPRE_Msk                  /*!< HSE sysclk prescaler */
-#define RCC_CR_HSEBYPPWR_Pos                 (21U)
-#define RCC_CR_HSEBYPPWR_Msk                 (0x1UL << RCC_CR_HSEBYPPWR_Pos)    /*!< 0x00200000 */
-#define RCC_CR_HSEBYPPWR                     RCC_CR_HSEBYPPWR_Msk               /*!< Enable HSE32 VDDTCXO */
-
-#define RCC_CR_PLLON_Pos                     (24U)
-#define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
-#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
-#define RCC_CR_PLLRDY_Pos                    (25U)
-#define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
-
-/********************  Bit definition for RCC_ICSCR register  ***************/
-/*!< MSICAL configuration */
-#define RCC_ICSCR_MSICAL_Pos                 (0U)
-#define RCC_ICSCR_MSICAL_Msk                 (0xFFUL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x000000FF */
-#define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
-
-/*!< MSITRIM configuration */
-#define RCC_ICSCR_MSITRIM_Pos                (8U)
-#define RCC_ICSCR_MSITRIM_Msk                (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
-#define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
-
-/*!< HSICAL configuration */
-#define RCC_ICSCR_HSICAL_Pos                 (16U)
-#define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
-#define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
-
-/*!< HSITRIM configuration */
-#define RCC_ICSCR_HSITRIM_Pos                (24U)
-#define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
-#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
-
-/*!< STOPWUCK configuration */
-#define RCC_CFGR_STOPWUCK_Pos                (15U)
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)  /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
-
-/*!< HPREF configuration */
-#define RCC_CFGR_HPREF_Pos                   (16U)
-#define RCC_CFGR_HPREF_Msk                   (0x1UL << RCC_CFGR_HPREF_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_HPREF                       RCC_CFGR_HPREF_Msk                /*!< AHB prescaler flag */
-
-/*!< PPRE1F configuration */
-#define RCC_CFGR_PPRE1F_Pos                  (17U)
-#define RCC_CFGR_PPRE1F_Msk                  (0x1UL << RCC_CFGR_PPRE1F_Pos)    /*!< 0x00020000 */
-#define RCC_CFGR_PPRE1F                      RCC_CFGR_PPRE1F_Msk               /*!< CPU1 APB1 prescaler flag */
-
-/*!< PPRE2F configuration */
-#define RCC_CFGR_PPRE2F_Pos                  (18U)
-#define RCC_CFGR_PPRE2F_Msk                  (0x1UL << RCC_CFGR_PPRE2F_Pos)    /*!< 0x00040000 */
-#define RCC_CFGR_PPRE2F                      RCC_CFGR_PPRE2F_Msk               /*!< APB2 prescaler flag */
-
-/*!< MCOSEL configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x08000000 */
-
-/*!< MCOPRE configuration */
-#define RCC_CFGR_MCOPRE_Pos                  (28U)
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define RCC_PLLCFGR_PLLSRC_Pos               (0U)
-#define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000003 */
-#define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
-#define RCC_PLLCFGR_PLLSRC_0                 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000001 */
-#define RCC_PLLCFGR_PLLSRC_1                 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000002 */
-
-#define RCC_PLLCFGR_PLLM_Pos                 (4U)
-#define RCC_PLLCFGR_PLLM_Msk                 (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
-#define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
-#define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
-#define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
-#define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
-
-#define RCC_PLLCFGR_PLLN_Pos                 (8U)
-#define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00007F00 */
-#define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
-#define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000100 */
-#define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000200 */
-#define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000400 */
-#define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000800 */
-#define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00001000 */
-#define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00002000 */
-#define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00004000 */
-
-#define RCC_PLLCFGR_PLLPEN_Pos               (16U)
-#define RCC_PLLCFGR_PLLPEN_Msk               (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)/*!< 0x00010000 */
-#define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk
-#define RCC_PLLCFGR_PLLP_Pos                 (17U)
-#define RCC_PLLCFGR_PLLP_Msk                 (0x1FUL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x003E0000 */
-#define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk
-#define RCC_PLLCFGR_PLLP_0                   (0x01UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00020000 */
-#define RCC_PLLCFGR_PLLP_1                   (0x02UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00040000 */
-#define RCC_PLLCFGR_PLLP_2                   (0x04UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00080000 */
-#define RCC_PLLCFGR_PLLP_3                   (0x08UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00100000 */
-#define RCC_PLLCFGR_PLLP_4                   (0x10UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00200000 */
-
-#define RCC_PLLCFGR_PLLQEN_Pos               (24U)
-#define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)/*!< 0x01000000 */
-#define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
-#define RCC_PLLCFGR_PLLQ_Pos                 (25U)
-#define RCC_PLLCFGR_PLLQ_Msk                 (0x7UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x0E000000 */
-#define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
-#define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x02000000 */
-#define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x04000000 */
-#define RCC_PLLCFGR_PLLQ_2                   (0x4UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x08000000 */
-
-#define RCC_PLLCFGR_PLLREN_Pos               (28U)
-#define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos)/*!< 0x10000000 */
-#define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
-#define RCC_PLLCFGR_PLLR_Pos                 (29U)
-#define RCC_PLLCFGR_PLLR_Msk                 (0x7UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0xE0000000 */
-#define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
-#define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x20000000 */
-#define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x40000000 */
-#define RCC_PLLCFGR_PLLR_2                   (0x4UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x80000000 */
-
-
-/********************  Bit definition for RCC_CIER register  ******************/
-#define RCC_CIER_LSIRDYIE_Pos                (0U)
-#define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk
-#define RCC_CIER_LSERDYIE_Pos                (1U)
-#define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)   /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
-#define RCC_CIER_MSIRDYIE_Pos                (2U)
-#define RCC_CIER_MSIRDYIE_Msk                (0x1UL << RCC_CIER_MSIRDYIE_Pos)   /*!< 0x00000004 */
-#define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk
-#define RCC_CIER_HSIRDYIE_Pos                (3U)
-#define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)   /*!< 0x00000008 */
-#define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
-#define RCC_CIER_HSERDYIE_Pos                (4U)
-#define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)   /*!< 0x00000010 */
-#define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
-#define RCC_CIER_PLLRDYIE_Pos                (5U)
-#define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)/*!< 0x00000020 */
-#define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
-#define RCC_CIER_LSECSSIE_Pos                (9U)
-#define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)   /*!< 0x00000200 */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
-
-/********************  Bit definition for RCC_CIFR register  ******************/
-#define RCC_CIFR_LSIRDYF_Pos                 (0U)
-#define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)  /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk
-#define RCC_CIFR_LSERDYF_Pos                 (1U)
-#define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
-#define RCC_CIFR_MSIRDYF_Pos                 (2U)
-#define RCC_CIFR_MSIRDYF_Msk                 (0x1UL << RCC_CIFR_MSIRDYF_Pos)   /*!< 0x00000004 */
-#define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk
-#define RCC_CIFR_HSIRDYF_Pos                 (3U)
-#define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */
-#define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
-#define RCC_CIFR_HSERDYF_Pos                 (4U)
-#define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */
-#define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
-#define RCC_CIFR_PLLRDYF_Pos                 (5U)
-#define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)/*!< 0x00000020 */
-#define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
-#define RCC_CIFR_CSSF_Pos                    (8U)
-#define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)   /*!< 0x00000100 */
-#define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
-#define RCC_CIFR_LSECSSF_Pos                 (9U)
-#define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */
-#define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
-
-/********************  Bit definition for RCC_CICR register  ******************/
-#define RCC_CICR_LSIRDYC_Pos                (0U)
-#define RCC_CICR_LSIRDYC_Msk                (0x1UL << RCC_CICR_LSIRDYC_Pos)  /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                    RCC_CICR_LSIRDYC_Msk
-#define RCC_CICR_LSERDYC_Pos                (1U)
-#define RCC_CICR_LSERDYC_Msk                (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                    RCC_CICR_LSERDYC_Msk
-#define RCC_CICR_MSIRDYC_Pos                (2U)
-#define RCC_CICR_MSIRDYC_Msk                (0x1UL << RCC_CICR_MSIRDYC_Pos)   /*!< 0x00000004 */
-#define RCC_CICR_MSIRDYC                    RCC_CICR_MSIRDYC_Msk
-#define RCC_CICR_HSIRDYC_Pos                (3U)
-#define RCC_CICR_HSIRDYC_Msk                (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */
-#define RCC_CICR_HSIRDYC                    RCC_CICR_HSIRDYC_Msk
-#define RCC_CICR_HSERDYC_Pos                (4U)
-#define RCC_CICR_HSERDYC_Msk                (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */
-#define RCC_CICR_HSERDYC                    RCC_CICR_HSERDYC_Msk
-#define RCC_CICR_PLLRDYC_Pos                (5U)
-#define RCC_CICR_PLLRDYC_Msk                (0x1UL << RCC_CICR_PLLRDYC_Pos)/*!< 0x00000020 */
-#define RCC_CICR_PLLRDYC                    RCC_CICR_PLLRDYC_Msk
-#define RCC_CICR_CSSC_Pos                   (8U)
-#define RCC_CICR_CSSC_Msk                   (0x1UL << RCC_CICR_CSSC_Pos)   /*!< 0x00000100 */
-#define RCC_CICR_CSSC                       RCC_CICR_CSSC_Msk
-#define RCC_CICR_LSECSSC_Pos                (9U)
-#define RCC_CICR_LSECSSC_Msk                (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */
-#define RCC_CICR_LSECSSC                    RCC_CICR_LSECSSC_Msk
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
-#define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
-#define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
-#define RCC_AHB1RSTR_DMA2RST_Pos             (1U)
-#define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
-#define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk
-#define RCC_AHB1RSTR_DMAMUX1RST_Pos          (2U)
-#define RCC_AHB1RSTR_DMAMUX1RST_Msk          (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
-#define RCC_AHB1RSTR_DMAMUX1RST              RCC_AHB1RSTR_DMAMUX1RST_Msk
-#define RCC_AHB1RSTR_CRCRST_Pos              (12U)
-#define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
-#define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
-
-/********************  Bit definition for RCC_AHB2RSTR register  ***************/
-#define RCC_AHB2RSTR_GPIOARST_Pos           (0U)
-#define RCC_AHB2RSTR_GPIOARST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
-#define RCC_AHB2RSTR_GPIOARST               RCC_AHB2RSTR_GPIOARST_Msk
-#define RCC_AHB2RSTR_GPIOBRST_Pos           (1U)
-#define RCC_AHB2RSTR_GPIOBRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
-#define RCC_AHB2RSTR_GPIOBRST               RCC_AHB2RSTR_GPIOBRST_Msk
-#define RCC_AHB2RSTR_GPIOCRST_Pos           (2U)
-#define RCC_AHB2RSTR_GPIOCRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
-#define RCC_AHB2RSTR_GPIOCRST               RCC_AHB2RSTR_GPIOCRST_Msk
-#define RCC_AHB2RSTR_GPIOHRST_Pos           (7U)
-#define RCC_AHB2RSTR_GPIOHRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)/*!< 0x00000080 */
-#define RCC_AHB2RSTR_GPIOHRST               RCC_AHB2RSTR_GPIOHRST_Msk
-
-/********************  Bit definition for RCC_AHB3RSTR register  ***************/
-#define RCC_AHB3RSTR_PKARST_Pos             (16U)
-#define RCC_AHB3RSTR_PKARST_Msk             (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00010000 */
-#define RCC_AHB3RSTR_PKARST                 RCC_AHB3RSTR_PKARST_Msk
-#define RCC_AHB3RSTR_AESRST_Pos             (17U)
-#define RCC_AHB3RSTR_AESRST_Msk             (0x1UL << RCC_AHB3RSTR_AESRST_Pos)/*!< 0x00020000 */
-#define RCC_AHB3RSTR_AESRST                 RCC_AHB3RSTR_AESRST_Msk
-#define RCC_AHB3RSTR_RNGRST_Pos             (18U)
-#define RCC_AHB3RSTR_RNGRST_Msk             (0x1UL << RCC_AHB3RSTR_RNGRST_Pos)/*!< 0x00040000 */
-#define RCC_AHB3RSTR_RNGRST                 RCC_AHB3RSTR_RNGRST_Msk
-
-#define RCC_AHB3RSTR_HSEMRST_Pos            (19U)
-#define RCC_AHB3RSTR_HSEMRST_Msk            (0x1UL << RCC_AHB3RSTR_HSEMRST_Pos)/*!< 0x00080000 */
-#define RCC_AHB3RSTR_HSEMRST                RCC_AHB3RSTR_HSEMRST_Msk
-#define RCC_AHB3RSTR_IPCCRST_Pos            (20U)
-#define RCC_AHB3RSTR_IPCCRST_Msk            (0x1UL << RCC_AHB3RSTR_IPCCRST_Pos)/*!< 0x00100000 */
-#define RCC_AHB3RSTR_IPCCRST                RCC_AHB3RSTR_IPCCRST_Msk
-#define RCC_AHB3RSTR_FLASHRST_Pos           (25U)
-#define RCC_AHB3RSTR_FLASHRST_Msk           (0x1UL << RCC_AHB3RSTR_FLASHRST_Pos) /*!< 0x02000000 */
-#define RCC_AHB3RSTR_FLASHRST               RCC_AHB3RSTR_FLASHRST_Msk
-
-/********************  Bit definition for RCC_APB1RSTR1 register  **************/
-#define RCC_APB1RSTR1_TIM2RST_Pos           (0U)
-#define RCC_APB1RSTR1_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
-#define RCC_APB1RSTR1_TIM2RST               RCC_APB1RSTR1_TIM2RST_Msk
-#define RCC_APB1RSTR1_SPI2RST_Pos           (14U)
-#define RCC_APB1RSTR1_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
-#define RCC_APB1RSTR1_SPI2RST               RCC_APB1RSTR1_SPI2RST_Msk
-#define RCC_APB1RSTR1_USART2RST_Pos         (17U)
-#define RCC_APB1RSTR1_USART2RST_Msk         (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
-#define RCC_APB1RSTR1_USART2RST             RCC_APB1RSTR1_USART2RST_Msk
-#define RCC_APB1RSTR1_I2C1RST_Pos           (21U)
-#define RCC_APB1RSTR1_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
-#define RCC_APB1RSTR1_I2C1RST               RCC_APB1RSTR1_I2C1RST_Msk
-#define RCC_APB1RSTR1_I2C2RST_Pos           (22U)
-#define RCC_APB1RSTR1_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
-#define RCC_APB1RSTR1_I2C2RST               RCC_APB1RSTR1_I2C2RST_Msk
-#define RCC_APB1RSTR1_I2C3RST_Pos           (23U)
-#define RCC_APB1RSTR1_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x00800000 */
-#define RCC_APB1RSTR1_I2C3RST               RCC_APB1RSTR1_I2C3RST_Msk
-#define RCC_APB1RSTR1_DACRST_Pos            (29U)
-#define RCC_APB1RSTR1_DACRST_Msk            (0x1UL << RCC_APB1RSTR1_DACRST_Pos)/*!< 0x20000000 */
-#define RCC_APB1RSTR1_DACRST                RCC_APB1RSTR1_DACRST_Msk
-#define RCC_APB1RSTR1_LPTIM1RST_Pos         (31U)
-#define RCC_APB1RSTR1_LPTIM1RST_Msk         (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
-#define RCC_APB1RSTR1_LPTIM1RST             RCC_APB1RSTR1_LPTIM1RST_Msk
-
-/********************  Bit definition for RCC_APB1RSTR2 register  **************/
-#define RCC_APB1RSTR2_LPUART1RST_Pos        (0U)
-#define RCC_APB1RSTR2_LPUART1RST_Msk        (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
-#define RCC_APB1RSTR2_LPUART1RST            RCC_APB1RSTR2_LPUART1RST_Msk
-#define RCC_APB1RSTR2_LPTIM2RST_Pos         (5U)
-#define RCC_APB1RSTR2_LPTIM2RST_Msk         (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)/*!< 0x00000020 */
-#define RCC_APB1RSTR2_LPTIM2RST             RCC_APB1RSTR2_LPTIM2RST_Msk
-#define RCC_APB1RSTR2_LPTIM3RST_Pos         (6U)
-#define RCC_APB1RSTR2_LPTIM3RST_Msk         (0x1UL << RCC_APB1RSTR2_LPTIM3RST_Pos)/*!< 0x00000040 */
-#define RCC_APB1RSTR2_LPTIM3RST             RCC_APB1RSTR2_LPTIM3RST_Msk
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define RCC_APB2RSTR_ADCRST_Pos             (9U)
-#define RCC_APB2RSTR_ADCRST_Msk             (0x1UL << RCC_APB2RSTR_ADCRST_Pos)/*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST                 RCC_APB2RSTR_ADCRST_Msk
-#define RCC_APB2RSTR_TIM1RST_Pos            (11U)
-#define RCC_APB2RSTR_TIM1RST_Msk            (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
-#define RCC_APB2RSTR_TIM1RST                RCC_APB2RSTR_TIM1RST_Msk
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk
-#define RCC_APB2RSTR_TIM16RST_Pos           (17U)
-#define RCC_APB2RSTR_TIM16RST_Msk           (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
-#define RCC_APB2RSTR_TIM16RST               RCC_APB2RSTR_TIM16RST_Msk
-#define RCC_APB2RSTR_TIM17RST_Pos           (18U)
-#define RCC_APB2RSTR_TIM17RST_Msk           (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
-#define RCC_APB2RSTR_TIM17RST               RCC_APB2RSTR_TIM17RST_Msk
-
-/********************  Bit definition for RCC_APB3RSTR register  **************/
-#define RCC_APB3RSTR_SUBGHZSPIRST_Pos            (0U)
-#define RCC_APB3RSTR_SUBGHZSPIRST_Msk            (0x1UL << RCC_APB3RSTR_SUBGHZSPIRST_Pos) /*!< 0x00000001 */
-#define RCC_APB3RSTR_SUBGHZSPIRST                RCC_APB3RSTR_SUBGHZSPIRST_Msk
-
-/********************  Bit definition for RCC_AHB1ENR register  ****************/
-#define RCC_AHB1ENR_DMA1EN_Pos              (0U)
-#define RCC_AHB1ENR_DMA1EN_Msk              (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)  /*!< 0x00000001 */
-#define RCC_AHB1ENR_DMA1EN                  RCC_AHB1ENR_DMA1EN_Msk
-#define RCC_AHB1ENR_DMA2EN_Pos              (1U)
-#define RCC_AHB1ENR_DMA2EN_Msk              (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)  /*!< 0x00000002 */
-#define RCC_AHB1ENR_DMA2EN                  RCC_AHB1ENR_DMA2EN_Msk
-#define RCC_AHB1ENR_DMAMUX1EN_Pos           (2U)
-#define RCC_AHB1ENR_DMAMUX1EN_Msk           (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
-#define RCC_AHB1ENR_DMAMUX1EN               RCC_AHB1ENR_DMAMUX1EN_Msk
-#define RCC_AHB1ENR_CRCEN_Pos               (12U)
-#define RCC_AHB1ENR_CRCEN_Msk               (0x1UL << RCC_AHB1ENR_CRCEN_Pos)   /*!< 0x00001000 */
-#define RCC_AHB1ENR_CRCEN                   RCC_AHB1ENR_CRCEN_Msk
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define RCC_AHB2ENR_GPIOAEN_Pos             (0U)
-#define RCC_AHB2ENR_GPIOAEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
-#define RCC_AHB2ENR_GPIOAEN                 RCC_AHB2ENR_GPIOAEN_Msk
-#define RCC_AHB2ENR_GPIOBEN_Pos             (1U)
-#define RCC_AHB2ENR_GPIOBEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
-#define RCC_AHB2ENR_GPIOBEN                 RCC_AHB2ENR_GPIOBEN_Msk
-#define RCC_AHB2ENR_GPIOCEN_Pos             (2U)
-#define RCC_AHB2ENR_GPIOCEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
-#define RCC_AHB2ENR_GPIOCEN                 RCC_AHB2ENR_GPIOCEN_Msk
-#define RCC_AHB2ENR_GPIOHEN_Pos             (7U)
-#define RCC_AHB2ENR_GPIOHEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
-#define RCC_AHB2ENR_GPIOHEN                 RCC_AHB2ENR_GPIOHEN_Msk
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define RCC_AHB3ENR_PKAEN_Pos               (16U)
-#define RCC_AHB3ENR_PKAEN_Msk               (0x1UL << RCC_AHB3ENR_PKAEN_Pos)   /*!< 0x00010000 */
-#define RCC_AHB3ENR_PKAEN                   RCC_AHB3ENR_PKAEN_Msk
-#define RCC_AHB3ENR_AESEN_Pos               (17U)
-#define RCC_AHB3ENR_AESEN_Msk               (0x1UL << RCC_AHB3ENR_AESEN_Pos)/*!< 0x00020000 */
-#define RCC_AHB3ENR_AESEN                   RCC_AHB3ENR_AESEN_Msk
-#define RCC_AHB3ENR_RNGEN_Pos               (18U)
-#define RCC_AHB3ENR_RNGEN_Msk               (0x1UL << RCC_AHB3ENR_RNGEN_Pos)  /*!< 0x00040000 */
-#define RCC_AHB3ENR_RNGEN                   RCC_AHB3ENR_RNGEN_Msk
-#define RCC_AHB3ENR_HSEMEN_Pos              (19U)
-#define RCC_AHB3ENR_HSEMEN_Msk              (0x1UL << RCC_AHB3ENR_HSEMEN_Pos)  /*!< 0x00080000 */
-#define RCC_AHB3ENR_HSEMEN                  RCC_AHB3ENR_HSEMEN_Msk
-#define RCC_AHB3ENR_IPCCEN_Pos              (20U)
-#define RCC_AHB3ENR_IPCCEN_Msk              (0x1UL << RCC_AHB3ENR_IPCCEN_Pos)  /*!< 0x00100000 */
-#define RCC_AHB3ENR_IPCCEN                  RCC_AHB3ENR_IPCCEN_Msk
-#define RCC_AHB3ENR_FLASHEN_Pos             (25U)
-#define RCC_AHB3ENR_FLASHEN_Msk             (0x1UL << RCC_AHB3ENR_FLASHEN_Pos)   /*!< 0x02000000 */
-#define RCC_AHB3ENR_FLASHEN                 RCC_AHB3ENR_FLASHEN_Msk
-
-/********************  Bit definition for RCC_APB1ENR1 register  **************/
-#define RCC_APB1ENR1_TIM2EN_Pos             (0U)
-#define RCC_APB1ENR1_TIM2EN_Msk             (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
-#define RCC_APB1ENR1_TIM2EN                 RCC_APB1ENR1_TIM2EN_Msk
-#define RCC_APB1ENR1_RTCAPBEN_Pos           (10U)
-#define RCC_APB1ENR1_RTCAPBEN_Msk           (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
-#define RCC_APB1ENR1_RTCAPBEN               RCC_APB1ENR1_RTCAPBEN_Msk
-#define RCC_APB1ENR1_WWDGEN_Pos             (11U)
-#define RCC_APB1ENR1_WWDGEN_Msk             (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1ENR1_WWDGEN                 RCC_APB1ENR1_WWDGEN_Msk
-#define RCC_APB1ENR1_SPI2EN_Pos             (14U)
-#define RCC_APB1ENR1_SPI2EN_Msk             (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
-#define RCC_APB1ENR1_SPI2EN                 RCC_APB1ENR1_SPI2EN_Msk
-#define RCC_APB1ENR1_USART2EN_Pos           (17U)
-#define RCC_APB1ENR1_USART2EN_Msk           (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR1_USART2EN               RCC_APB1ENR1_USART2EN_Msk
-#define RCC_APB1ENR1_I2C1EN_Pos             (21U)
-#define RCC_APB1ENR1_I2C1EN_Msk             (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
-#define RCC_APB1ENR1_I2C1EN                 RCC_APB1ENR1_I2C1EN_Msk
-#define RCC_APB1ENR1_I2C2EN_Pos             (22U)
-#define RCC_APB1ENR1_I2C2EN_Msk             (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
-#define RCC_APB1ENR1_I2C2EN                 RCC_APB1ENR1_I2C2EN_Msk
-#define RCC_APB1ENR1_I2C3EN_Pos             (23U)
-#define RCC_APB1ENR1_I2C3EN_Msk             (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
-#define RCC_APB1ENR1_I2C3EN                 RCC_APB1ENR1_I2C3EN_Msk
-#define RCC_APB1ENR1_DACEN_Pos              (29U)
-#define RCC_APB1ENR1_DACEN_Msk              (0x1UL << RCC_APB1ENR1_DACEN_Pos)/*!< 0x20000000 */
-#define RCC_APB1ENR1_DACEN                  RCC_APB1ENR1_DACEN_Msk
-#define RCC_APB1ENR1_LPTIM1EN_Pos           (31U)
-#define RCC_APB1ENR1_LPTIM1EN_Msk           (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
-#define RCC_APB1ENR1_LPTIM1EN               RCC_APB1ENR1_LPTIM1EN_Msk
-
-/********************  Bit definition for RCC_APB1ENR2 register  **************/
-#define RCC_APB1ENR2_LPUART1EN_Pos          (0U)
-#define RCC_APB1ENR2_LPUART1EN_Msk         (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
-#define RCC_APB1ENR2_LPUART1EN              RCC_APB1ENR2_LPUART1EN_Msk
-#define RCC_APB1ENR2_LPTIM2EN_Pos           (5U)
-#define RCC_APB1ENR2_LPTIM2EN_Msk           (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)/*!< 0x00000020 */
-#define RCC_APB1ENR2_LPTIM2EN               RCC_APB1ENR2_LPTIM2EN_Msk
-#define RCC_APB1ENR2_LPTIM3EN_Pos           (6U)
-#define RCC_APB1ENR2_LPTIM3EN_Msk           (0x1UL << RCC_APB1ENR2_LPTIM3EN_Pos)/*!< 0x00000040 */
-#define RCC_APB1ENR2_LPTIM3EN               RCC_APB1ENR2_LPTIM3EN_Msk
-
-/********************  Bit definition for RCC_APB2ENR register  **************/
-#define RCC_APB2ENR_ADCEN_Pos               (9U)
-#define RCC_APB2ENR_ADCEN_Msk               (0x1UL << RCC_APB2ENR_ADCEN_Pos)  /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                   RCC_APB2ENR_ADCEN_Msk
-#define RCC_APB2ENR_TIM1EN_Pos              (11U)
-#define RCC_APB2ENR_TIM1EN_Msk              (0x1UL << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
-#define RCC_APB2ENR_TIM1EN                  RCC_APB2ENR_TIM1EN_Msk
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk
-#define RCC_APB2ENR_USART1EN_Pos            (14U)
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk
-#define RCC_APB2ENR_TIM16EN_Pos             (17U)
-#define RCC_APB2ENR_TIM16EN_Msk             (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
-#define RCC_APB2ENR_TIM16EN                 RCC_APB2ENR_TIM16EN_Msk
-#define RCC_APB2ENR_TIM17EN_Pos             (18U)
-#define RCC_APB2ENR_TIM17EN_Msk             (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
-#define RCC_APB2ENR_TIM17EN                 RCC_APB2ENR_TIM17EN_Msk
-
-/********************  Bit definition for RCC_APB3ENR register  **************/
-#define RCC_APB3ENR_SUBGHZSPIEN_Pos         (0U)
-#define RCC_APB3ENR_SUBGHZSPIEN_Msk         (0x1UL << RCC_APB3ENR_SUBGHZSPIEN_Pos)/*!< 0x00000001 */
-#define RCC_APB3ENR_SUBGHZSPIEN             RCC_APB3ENR_SUBGHZSPIEN_Msk
-
-/********************  Bit definition for RCC_AHB1SMENR register  ****************/
-#define RCC_AHB1SMENR_DMA1SMEN_Pos          (0U)
-#define RCC_AHB1SMENR_DMA1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
-#define RCC_AHB1SMENR_DMA1SMEN              RCC_AHB1SMENR_DMA1SMEN_Msk
-#define RCC_AHB1SMENR_DMA2SMEN_Pos          (1U)
-#define RCC_AHB1SMENR_DMA2SMEN_Msk          (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
-#define RCC_AHB1SMENR_DMA2SMEN              RCC_AHB1SMENR_DMA2SMEN_Msk
-#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos       (2U)
-#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk       (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
-#define RCC_AHB1SMENR_DMAMUX1SMEN           RCC_AHB1SMENR_DMAMUX1SMEN_Msk
-#define RCC_AHB1SMENR_CRCSMEN_Pos           (12U)
-#define RCC_AHB1SMENR_CRCSMEN_Msk           (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
-#define RCC_AHB1SMENR_CRCSMEN               RCC_AHB1SMENR_CRCSMEN_Msk
-
-/********************  Bit definition for RCC_AHB2SMENR register  ***************/
-#define RCC_AHB2SMENR_GPIOASMEN_Pos         (0U)
-#define RCC_AHB2SMENR_GPIOASMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
-#define RCC_AHB2SMENR_GPIOASMEN             RCC_AHB2SMENR_GPIOASMEN_Msk
-#define RCC_AHB2SMENR_GPIOBSMEN_Pos         (1U)
-#define RCC_AHB2SMENR_GPIOBSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
-#define RCC_AHB2SMENR_GPIOBSMEN             RCC_AHB2SMENR_GPIOBSMEN_Msk
-#define RCC_AHB2SMENR_GPIOCSMEN_Pos         (2U)
-#define RCC_AHB2SMENR_GPIOCSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
-#define RCC_AHB2SMENR_GPIOCSMEN             RCC_AHB2SMENR_GPIOCSMEN_Msk
-#define RCC_AHB2SMENR_GPIOHSMEN_Pos         (7U)
-#define RCC_AHB2SMENR_GPIOHSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos)/*!< 0x00000080 */
-#define RCC_AHB2SMENR_GPIOHSMEN             RCC_AHB2SMENR_GPIOHSMEN_Msk
-
-/********************  Bit definition for RCC_AHB3SMENR register  ***************/
-#define RCC_AHB3SMENR_PKASMEN_Pos           (16U)
-#define RCC_AHB3SMENR_PKASMEN_Msk           (0x1UL << RCC_AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */
-#define RCC_AHB3SMENR_PKASMEN               RCC_AHB3SMENR_PKASMEN_Msk
-#define RCC_AHB3SMENR_AESSMEN_Pos           (17U)
-#define RCC_AHB3SMENR_AESSMEN_Msk           (0x1UL << RCC_AHB3SMENR_AESSMEN_Pos) /*!< 0x00020000 */
-#define RCC_AHB3SMENR_AESSMEN               RCC_AHB3SMENR_AESSMEN_Msk
-#define RCC_AHB3SMENR_RNGSMEN_Pos           (18U)
-#define RCC_AHB3SMENR_RNGSMEN_Msk           (0x1UL << RCC_AHB3SMENR_RNGSMEN_Pos)/*!< 0x00040000 */
-#define RCC_AHB3SMENR_RNGSMEN               RCC_AHB3SMENR_RNGSMEN_Msk
-#define RCC_AHB3SMENR_SRAM1SMEN_Pos         (23U)
-#define RCC_AHB3SMENR_SRAM1SMEN_Msk         (0x1UL << RCC_AHB3SMENR_SRAM1SMEN_Pos)/*!< 0x00800000 */
-#define RCC_AHB3SMENR_SRAM1SMEN             RCC_AHB3SMENR_SRAM1SMEN_Msk
-#define RCC_AHB3SMENR_SRAM2SMEN_Pos         (24U)
-#define RCC_AHB3SMENR_SRAM2SMEN_Msk         (0x1UL << RCC_AHB3SMENR_SRAM2SMEN_Pos)/*!< 0x01000000 */
-#define RCC_AHB3SMENR_SRAM2SMEN             RCC_AHB3SMENR_SRAM2SMEN_Msk
-#define RCC_AHB3SMENR_FLASHSMEN_Pos         (25U)
-#define RCC_AHB3SMENR_FLASHSMEN_Msk         (0x1UL << RCC_AHB3SMENR_FLASHSMEN_Pos)/*!< 0x02000000 */
-#define RCC_AHB3SMENR_FLASHSMEN             RCC_AHB3SMENR_FLASHSMEN_Msk
-
-/********************  Bit definition for RCC_APB1SMENR1 register  **************/
-#define RCC_APB1SMENR1_TIM2SMEN_Pos         (0U)
-#define RCC_APB1SMENR1_TIM2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
-#define RCC_APB1SMENR1_TIM2SMEN             RCC_APB1SMENR1_TIM2SMEN_Msk
-#define RCC_APB1SMENR1_RTCAPBSMEN_Pos       (10U)
-#define RCC_APB1SMENR1_RTCAPBSMEN_Msk       (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
-#define RCC_APB1SMENR1_RTCAPBSMEN           RCC_APB1SMENR1_RTCAPBSMEN_Msk
-#define RCC_APB1SMENR1_WWDGSMEN_Pos         (11U)
-#define RCC_APB1SMENR1_WWDGSMEN_Msk         (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
-#define RCC_APB1SMENR1_WWDGSMEN             RCC_APB1SMENR1_WWDGSMEN_Msk
-#define RCC_APB1SMENR1_SPI2SMEN_Pos         (14U)
-#define RCC_APB1SMENR1_SPI2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
-#define RCC_APB1SMENR1_SPI2SMEN             RCC_APB1SMENR1_SPI2SMEN_Msk
-#define RCC_APB1SMENR1_USART2SMEN_Pos       (17U)
-#define RCC_APB1SMENR1_USART2SMEN_Msk       (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
-#define RCC_APB1SMENR1_USART2SMEN           RCC_APB1SMENR1_USART2SMEN_Msk
-#define RCC_APB1SMENR1_I2C1SMEN_Pos         (21U)
-#define RCC_APB1SMENR1_I2C1SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
-#define RCC_APB1SMENR1_I2C1SMEN             RCC_APB1SMENR1_I2C1SMEN_Msk
-#define RCC_APB1SMENR1_I2C2SMEN_Pos         (22U)
-#define RCC_APB1SMENR1_I2C2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
-#define RCC_APB1SMENR1_I2C2SMEN             RCC_APB1SMENR1_I2C2SMEN_Msk
-#define RCC_APB1SMENR1_I2C3SMEN_Pos         (23U)
-#define RCC_APB1SMENR1_I2C3SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x00800000 */
-#define RCC_APB1SMENR1_I2C3SMEN             RCC_APB1SMENR1_I2C3SMEN_Msk
-#define RCC_APB1SMENR1_DACSMEN_Pos          (29U)
-#define RCC_APB1SMENR1_DACSMEN_Msk          (0x1UL << RCC_APB1SMENR1_DACSMEN_Pos)/*!< 0x20000000 */
-#define RCC_APB1SMENR1_DACSMEN              RCC_APB1SMENR1_DACSMEN_Msk
-#define RCC_APB1SMENR1_LPTIM1SMEN_Pos       (31U)
-#define RCC_APB1SMENR1_LPTIM1SMEN_Msk       (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
-#define RCC_APB1SMENR1_LPTIM1SMEN           RCC_APB1SMENR1_LPTIM1SMEN_Msk
-
-/********************  Bit definition for RCC_APB1SMENR2 register  **************/
-#define RCC_APB1SMENR2_LPUART1SMEN_Pos      (0U)
-#define RCC_APB1SMENR2_LPUART1SMEN_Msk      (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
-#define RCC_APB1SMENR2_LPUART1SMEN          RCC_APB1SMENR2_LPUART1SMEN_Msk
-#define RCC_APB1SMENR2_LPTIM2SMEN_Pos       (5U)
-#define RCC_APB1SMENR2_LPTIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos)/*!< 0x00000020 */
-#define RCC_APB1SMENR2_LPTIM2SMEN           RCC_APB1SMENR2_LPTIM2SMEN_Msk
-#define RCC_APB1SMENR2_LPTIM3SMEN_Pos       (6U)
-#define RCC_APB1SMENR2_LPTIM3SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPTIM3SMEN_Pos)/*!< 0x00000040 */
-#define RCC_APB1SMENR2_LPTIM3SMEN           RCC_APB1SMENR2_LPTIM3SMEN_Msk
-
-/********************  Bit definition for RCC_APB2SMENR register  **************/
-#define RCC_APB2SMENR_ADCSMEN_Pos           (9U)
-#define RCC_APB2SMENR_ADCSMEN_Msk           (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)/*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN               RCC_APB2SMENR_ADCSMEN_Msk
-#define RCC_APB2SMENR_TIM1SMEN_Pos          (11U)
-#define RCC_APB2SMENR_TIM1SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
-#define RCC_APB2SMENR_TIM1SMEN              RCC_APB2SMENR_TIM1SMEN_Msk
-#define RCC_APB2SMENR_SPI1SMEN_Pos          (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk          (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN              RCC_APB2SMENR_SPI1SMEN_Msk
-#define RCC_APB2SMENR_USART1SMEN_Pos        (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk        (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN            RCC_APB2SMENR_USART1SMEN_Msk
-#define RCC_APB2SMENR_TIM16SMEN_Pos         (17U)
-#define RCC_APB2SMENR_TIM16SMEN_Msk         (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
-#define RCC_APB2SMENR_TIM16SMEN             RCC_APB2SMENR_TIM16SMEN_Msk
-#define RCC_APB2SMENR_TIM17SMEN_Pos         (18U)
-#define RCC_APB2SMENR_TIM17SMEN_Msk         (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
-#define RCC_APB2SMENR_TIM17SMEN             RCC_APB2SMENR_TIM17SMEN_Msk
-
-/********************  Bit definition for RCC_APB3SMENR register  **************/
-#define RCC_APB3SMENR_SUBGHZSPISMEN_Pos     (0U)
-#define RCC_APB3SMENR_SUBGHZSPISMEN_Msk     (0x1UL << RCC_APB3SMENR_SUBGHZSPISMEN_Pos)/*!< 0x00000001 */
-#define RCC_APB3SMENR_SUBGHZSPISMEN         RCC_APB3SMENR_SUBGHZSPISMEN_Msk
-
-/********************  Bit definition for RCC_CCIPR register  ******************/
-#define RCC_CCIPR_USART1SEL_Pos             (0U)
-#define RCC_CCIPR_USART1SEL_Msk             (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL                 RCC_CCIPR_USART1SEL_Msk
-#define RCC_CCIPR_USART1SEL_0               (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1               (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
-
-#define RCC_CCIPR_USART2SEL_Pos             (2U)
-#define RCC_CCIPR_USART2SEL_Msk             (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL                 RCC_CCIPR_USART2SEL_Msk
-#define RCC_CCIPR_USART2SEL_0               (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1               (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
-
-#define RCC_CCIPR_I2S2SEL_Pos               (8U)
-#define RCC_CCIPR_I2S2SEL_Msk               (0x3UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000300 */
-#define RCC_CCIPR_I2S2SEL                   RCC_CCIPR_I2S2SEL_Msk
-#define RCC_CCIPR_I2S2SEL_0                 (0x1UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000100 */
-#define RCC_CCIPR_I2S2SEL_1                 (0x2UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000200 */
-
-#define RCC_CCIPR_LPUART1SEL_Pos            (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk            (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL                RCC_CCIPR_LPUART1SEL_Msk
-#define RCC_CCIPR_LPUART1SEL_0              (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
-#define RCC_CCIPR_LPUART1SEL_1              (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
-
-#define RCC_CCIPR_I2C1SEL_Pos               (12U)
-#define RCC_CCIPR_I2C1SEL_Msk               (0x3UL << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                   RCC_CCIPR_I2C1SEL_Msk
-#define RCC_CCIPR_I2C1SEL_0                 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1                 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00002000 */
-
-#define RCC_CCIPR_I2C2SEL_Pos               (14U)
-#define RCC_CCIPR_I2C2SEL_Msk               (0x3UL << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x0000C000 */
-#define RCC_CCIPR_I2C2SEL                   RCC_CCIPR_I2C2SEL_Msk
-#define RCC_CCIPR_I2C2SEL_0                 (0x1UL << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00004000 */
-#define RCC_CCIPR_I2C2SEL_1                 (0x2UL << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00008000 */
-
-#define RCC_CCIPR_I2C3SEL_Pos               (16U)
-#define RCC_CCIPR_I2C3SEL_Msk               (0x3UL << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00030000 */
-#define RCC_CCIPR_I2C3SEL                   RCC_CCIPR_I2C3SEL_Msk
-#define RCC_CCIPR_I2C3SEL_0                 (0x1UL << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00010000 */
-#define RCC_CCIPR_I2C3SEL_1                 (0x2UL << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00020000 */
-
-#define RCC_CCIPR_LPTIM1SEL_Pos             (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk             (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL                 RCC_CCIPR_LPTIM1SEL_Msk
-#define RCC_CCIPR_LPTIM1SEL_0               (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1               (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
-
-#define RCC_CCIPR_LPTIM2SEL_Pos             (20U)
-#define RCC_CCIPR_LPTIM2SEL_Msk             (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
-#define RCC_CCIPR_LPTIM2SEL                 RCC_CCIPR_LPTIM2SEL_Msk
-#define RCC_CCIPR_LPTIM2SEL_0               (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
-#define RCC_CCIPR_LPTIM2SEL_1               (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
-
-#define RCC_CCIPR_LPTIM3SEL_Pos             (22U)
-#define RCC_CCIPR_LPTIM3SEL_Msk             (0x3UL << RCC_CCIPR_LPTIM3SEL_Pos)   /*!< 0x00C00000 */
-#define RCC_CCIPR_LPTIM3SEL                 RCC_CCIPR_LPTIM3SEL_Msk
-#define RCC_CCIPR_LPTIM3SEL_0               (0x1UL << RCC_CCIPR_LPTIM3SEL_Pos)   /*!< 0x00400000 */
-#define RCC_CCIPR_LPTIM3SEL_1               (0x2UL << RCC_CCIPR_LPTIM3SEL_Pos)   /*!< 0x00800000 */
-
-#define RCC_CCIPR_ADCSEL_Pos                (28U)
-#define RCC_CCIPR_ADCSEL_Msk                (0x3UL << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x30000000 */
-#define RCC_CCIPR_ADCSEL                    RCC_CCIPR_ADCSEL_Msk
-#define RCC_CCIPR_ADCSEL_0                  (0x1UL << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x10000000 */
-#define RCC_CCIPR_ADCSEL_1                  (0x2UL << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x20000000 */
-
-#define RCC_CCIPR_RNGSEL_Pos                (30U)
-#define RCC_CCIPR_RNGSEL_Msk                (0x3UL << RCC_CCIPR_RNGSEL_Pos)    /*!< 0xC0000000 */
-#define RCC_CCIPR_RNGSEL                    RCC_CCIPR_RNGSEL_Msk
-#define RCC_CCIPR_RNGSEL_0                  (0x1UL << RCC_CCIPR_RNGSEL_Pos)    /*!< 0x40000000 */
-#define RCC_CCIPR_RNGSEL_1                  (0x2UL << RCC_CCIPR_RNGSEL_Pos)    /*!< 0x80000000 */
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define RCC_BDCR_LSEON_Pos                  (0U)
-#define RCC_BDCR_LSEON_Msk                  (0x1UL << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
-#define RCC_BDCR_LSEON                      RCC_BDCR_LSEON_Msk
-#define RCC_BDCR_LSERDY_Pos                 (1U)
-#define RCC_BDCR_LSERDY_Msk                 (0x1UL << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
-#define RCC_BDCR_LSERDY                     RCC_BDCR_LSERDY_Msk
-#define RCC_BDCR_LSEBYP_Pos                 (2U)
-#define RCC_BDCR_LSEBYP_Msk                 (0x1UL << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
-#define RCC_BDCR_LSEBYP                     RCC_BDCR_LSEBYP_Msk
-
-#define RCC_BDCR_LSEDRV_Pos                 (3U)
-#define RCC_BDCR_LSEDRV_Msk                 (0x3UL << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000018 */
-#define RCC_BDCR_LSEDRV                     RCC_BDCR_LSEDRV_Msk
-#define RCC_BDCR_LSEDRV_0                   (0x1UL << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000008 */
-#define RCC_BDCR_LSEDRV_1                   (0x2UL << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000010 */
-
-#define RCC_BDCR_LSECSSON_Pos               (5U)
-#define RCC_BDCR_LSECSSON_Msk               (0x1UL << RCC_BDCR_LSECSSON_Pos)   /*!< 0x00000020 */
-#define RCC_BDCR_LSECSSON                   RCC_BDCR_LSECSSON_Msk
-#define RCC_BDCR_LSECSSD_Pos                (6U)
-#define RCC_BDCR_LSECSSD_Msk                (0x1UL << RCC_BDCR_LSECSSD_Pos)    /*!< 0x00000040 */
-#define RCC_BDCR_LSECSSD                    RCC_BDCR_LSECSSD_Msk
-#define RCC_BDCR_LSESYSEN_Pos               (7U)
-#define RCC_BDCR_LSESYSEN_Msk               (0x1UL << RCC_BDCR_LSESYSEN_Pos)   /*!< 0x00000080 */
-#define RCC_BDCR_LSESYSEN                   RCC_BDCR_LSESYSEN_Msk
-
-#define RCC_BDCR_RTCSEL_Pos                 (8U)
-#define RCC_BDCR_RTCSEL_Msk                 (0x3UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
-#define RCC_BDCR_RTCSEL                     RCC_BDCR_RTCSEL_Msk
-#define RCC_BDCR_RTCSEL_0                   (0x1UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
-#define RCC_BDCR_RTCSEL_1                   (0x2UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
-
-#define RCC_BDCR_LSESYSRDY_Pos              (11U)
-#define RCC_BDCR_LSESYSRDY_Msk              (0x1UL << RCC_BDCR_LSESYSRDY_Pos) /*!< 0x00000800 */
-#define RCC_BDCR_LSESYSRDY                  RCC_BDCR_LSESYSRDY_Msk
-
-#define RCC_BDCR_RTCEN_Pos                  (15U)
-#define RCC_BDCR_RTCEN_Msk                  (0x1UL << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
-#define RCC_BDCR_RTCEN                      RCC_BDCR_RTCEN_Msk
-
-#define RCC_BDCR_BDRST_Pos                  (16U)
-#define RCC_BDCR_BDRST_Msk                  (0x1UL << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
-#define RCC_BDCR_BDRST                      RCC_BDCR_BDRST_Msk
-
-#define RCC_BDCR_LSCOEN_Pos                 (24U)
-#define RCC_BDCR_LSCOEN_Msk                 (0x1UL << RCC_BDCR_LSCOEN_Pos)     /*!< 0x01000000 */
-#define RCC_BDCR_LSCOEN                     RCC_BDCR_LSCOEN_Msk
-#define RCC_BDCR_LSCOSEL_Pos                (25U)
-#define RCC_BDCR_LSCOSEL_Msk                (0x1UL << RCC_BDCR_LSCOSEL_Pos)    /*!< 0x02000000 */
-#define RCC_BDCR_LSCOSEL                    RCC_BDCR_LSCOSEL_Msk
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                  (0U)
-#define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */
-#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk
-#define RCC_CSR_LSIRDY_Pos                 (1U)
-#define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk
-#define RCC_CSR_LSIPRE_Pos                 (4U)
-#define RCC_CSR_LSIPRE_Msk                 (0x1UL << RCC_CSR_LSIPRE_Pos)     /*!< 0x00000010 */
-#define RCC_CSR_LSIPRE                     RCC_CSR_LSIPRE_Msk
-
-#define RCC_CSR_MSISRANGE_Pos              (8U)
-#define RCC_CSR_MSISRANGE_Msk              (0xFUL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000F00 */
-#define RCC_CSR_MSISRANGE                  RCC_CSR_MSISRANGE_Msk
-#define RCC_CSR_MSISRANGE_1                (0x4UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000400 */
-#define RCC_CSR_MSISRANGE_2                (0x5UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000500 */
-#define RCC_CSR_MSISRANGE_4                (0x6UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000600 */
-#define RCC_CSR_MSISRANGE_8                (0x7UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000700 */
-
-#define RCC_CSR_RFRSTF_Pos                  (14U)
-#define RCC_CSR_RFRSTF_Msk                  (0x1UL << RCC_CSR_RFRSTF_Pos)      /*!< 0x0004000 */
-#define RCC_CSR_RFRSTF                      RCC_CSR_RFRSTF_Msk
-#define RCC_CSR_RFRST_Pos                   (15U)
-#define RCC_CSR_RFRST_Msk                   (0x1UL << RCC_CSR_RFRST_Pos)       /*!< 0x0008000 */
-#define RCC_CSR_RFRST                       RCC_CSR_RFRST_Msk
-
-#define RCC_CSR_RMVF_Pos                    (23U)
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)        /*!< 0x00800000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk
-#define RCC_CSR_RFILARSTF_Pos               (24U)
-#define RCC_CSR_RFILARSTF_Msk               (0x1UL << RCC_CSR_RFILARSTF_Pos)   /*!< 0x01000000 */
-#define RCC_CSR_RFILARSTF                   RCC_CSR_RFILARSTF_Msk
-#define RCC_CSR_OBLRSTF_Pos                 (25U)
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)     /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk
-#define RCC_CSR_PINRSTF_Pos                 (26U)
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk
-#define RCC_CSR_BORRSTF_Pos                 (27U)
-#define RCC_CSR_BORRSTF_Msk                 (0x1UL << RCC_CSR_BORRSTF_Pos)     /*!< 0x08000000 */
-#define RCC_CSR_BORRSTF                     RCC_CSR_BORRSTF_Msk
-#define RCC_CSR_SFTRSTF_Pos                 (28U)
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk
-#define RCC_CSR_IWDGRSTF_Pos                (29U)
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk
-#define RCC_CSR_WWDGRSTF_Pos                (30U)
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk
-#define RCC_CSR_LPWRRSTF_Pos                (31U)
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk
-
-/********************  Bit definition for RCC_EXTCFGR register  *******************/
-#define RCC_EXTCFGR_SHDHPRE_Pos             (0U)
-#define RCC_EXTCFGR_SHDHPRE_Msk             (0xFUL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x0000000F */
-#define RCC_EXTCFGR_SHDHPRE                 RCC_EXTCFGR_SHDHPRE_Msk
-#define RCC_EXTCFGR_SHDHPRE_0               (0x1UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000001 */
-#define RCC_EXTCFGR_SHDHPRE_1               (0x2UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000002 */
-#define RCC_EXTCFGR_SHDHPRE_2               (0x4UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000004 */
-#define RCC_EXTCFGR_SHDHPRE_3               (0x8UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000008 */
-
-#define RCC_EXTCFGR_C2HPRE_Pos              (4U)
-#define RCC_EXTCFGR_C2HPRE_Msk              (0xFUL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x000000F0 */
-#define RCC_EXTCFGR_C2HPRE                  RCC_EXTCFGR_C2HPRE_Msk
-#define RCC_EXTCFGR_C2HPRE_0                (0x1UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000010 */
-#define RCC_EXTCFGR_C2HPRE_1                (0x2UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000020 */
-#define RCC_EXTCFGR_C2HPRE_2                (0x4UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000040 */
-#define RCC_EXTCFGR_C2HPRE_3                (0x8UL << RCC_EXTCFGR_C2HPRE_Pos)/*!< 0x00000080 */
-
-#define RCC_EXTCFGR_SHDHPREF_Pos            (16U)
-#define RCC_EXTCFGR_SHDHPREF_Msk            (0x1UL << RCC_EXTCFGR_SHDHPREF_Pos)/*!< 0x00010000 */
-#define RCC_EXTCFGR_SHDHPREF                RCC_EXTCFGR_SHDHPREF_Msk
-#define RCC_EXTCFGR_C2HPREF_Pos             (17U)
-#define RCC_EXTCFGR_C2HPREF_Msk             (0x1UL << RCC_EXTCFGR_C2HPREF_Pos)/*!< 0x00020000 */
-#define RCC_EXTCFGR_C2HPREF                 RCC_EXTCFGR_C2HPREF_Msk
-
-/********************  Bit definition for RCC_C2AHB1ENR register  ****************/
-#define RCC_C2AHB1ENR_DMA1EN_Pos            (0U)
-#define RCC_C2AHB1ENR_DMA1EN_Msk            (0x1UL << RCC_C2AHB1ENR_DMA1EN_Pos)/*!< 0x00000001 */
-#define RCC_C2AHB1ENR_DMA1EN                RCC_C2AHB1ENR_DMA1EN_Msk
-#define RCC_C2AHB1ENR_DMA2EN_Pos            (1U)
-#define RCC_C2AHB1ENR_DMA2EN_Msk            (0x1UL << RCC_C2AHB1ENR_DMA2EN_Pos)/*!< 0x00000002 */
-#define RCC_C2AHB1ENR_DMA2EN                RCC_C2AHB1ENR_DMA2EN_Msk
-#define RCC_C2AHB1ENR_DMAMUX1EN_Pos         (2U)
-#define RCC_C2AHB1ENR_DMAMUX1EN_Msk         (0x1UL << RCC_C2AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
-#define RCC_C2AHB1ENR_DMAMUX1EN             RCC_C2AHB1ENR_DMAMUX1EN_Msk
-#define RCC_C2AHB1ENR_CRCEN_Pos             (12U)
-#define RCC_C2AHB1ENR_CRCEN_Msk             (0x1UL << RCC_C2AHB1ENR_CRCEN_Pos)/*!< 0x00001000 */
-#define RCC_C2AHB1ENR_CRCEN                  RCC_C2AHB1ENR_CRCEN_Msk
-
-/********************  Bit definition for RCC_C2AHB2ENR register  ***************/
-#define RCC_C2AHB2ENR_GPIOAEN_Pos          (0U)
-#define RCC_C2AHB2ENR_GPIOAEN_Msk          (0x1UL << RCC_C2AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
-#define RCC_C2AHB2ENR_GPIOAEN              RCC_C2AHB2ENR_GPIOAEN_Msk
-#define RCC_C2AHB2ENR_GPIOBEN_Pos          (1U)
-#define RCC_C2AHB2ENR_GPIOBEN_Msk          (0x1UL << RCC_C2AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
-#define RCC_C2AHB2ENR_GPIOBEN              RCC_C2AHB2ENR_GPIOBEN_Msk
-#define RCC_C2AHB2ENR_GPIOCEN_Pos          (2U)
-#define RCC_C2AHB2ENR_GPIOCEN_Msk          (0x1UL << RCC_C2AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
-#define RCC_C2AHB2ENR_GPIOCEN              RCC_C2AHB2ENR_GPIOCEN_Msk
-#define RCC_C2AHB2ENR_GPIOHEN_Pos          (7U)
-#define RCC_C2AHB2ENR_GPIOHEN_Msk          (0x1UL << RCC_C2AHB2ENR_GPIOHEN_Pos)/*!< 0x00000080 */
-#define RCC_C2AHB2ENR_GPIOHEN              RCC_C2AHB2ENR_GPIOHEN_Msk
-
-/********************  Bit definition for RCC_C2AHB3ENR register  ***************/
-#define RCC_C2AHB3ENR_PKAEN_Pos            (16U)
-#define RCC_C2AHB3ENR_PKAEN_Msk            (0x1UL << RCC_C2AHB3ENR_PKAEN_Pos) /*!< 0x00010000 */
-#define RCC_C2AHB3ENR_PKAEN                RCC_C2AHB3ENR_PKAEN_Msk
-#define RCC_C2AHB3ENR_AESEN_Pos            (17U)
-#define RCC_C2AHB3ENR_AESEN_Msk            (0x1UL << RCC_C2AHB3ENR_AESEN_Pos)/*!< 0x00020000 */
-#define RCC_C2AHB3ENR_AESEN                RCC_C2AHB3ENR_AESEN_Msk
-#define RCC_C2AHB3ENR_RNGEN_Pos            (18U)
-#define RCC_C2AHB3ENR_RNGEN_Msk            (0x1UL << RCC_C2AHB3ENR_RNGEN_Pos)/*!< 0x00040000 */
-#define RCC_C2AHB3ENR_RNGEN                RCC_C2AHB3ENR_RNGEN_Msk
-#define RCC_C2AHB3ENR_HSEMEN_Pos           (19U)
-#define RCC_C2AHB3ENR_HSEMEN_Msk           (0x1UL << RCC_C2AHB3ENR_HSEMEN_Pos)/*!< 0x00080000 */
-#define RCC_C2AHB3ENR_HSEMEN               RCC_C2AHB3ENR_HSEMEN_Msk
-#define RCC_C2AHB3ENR_IPCCEN_Pos           (20U)
-#define RCC_C2AHB3ENR_IPCCEN_Msk           (0x1UL << RCC_C2AHB3ENR_IPCCEN_Pos)/*!< 0x00100000 */
-#define RCC_C2AHB3ENR_IPCCEN               RCC_C2AHB3ENR_IPCCEN_Msk
-#define RCC_C2AHB3ENR_FLASHEN_Pos          (25U)
-#define RCC_C2AHB3ENR_FLASHEN_Msk          (0x1UL << RCC_C2AHB3ENR_FLASHEN_Pos)/*!< 0x02000000 */
-#define RCC_C2AHB3ENR_FLASHEN              RCC_C2AHB3ENR_FLASHEN_Msk
-
-/********************  Bit definition for RCC_C2APB1ENR1 register  **************/
-#define RCC_C2APB1ENR1_TIM2EN_Pos          (0U)
-#define RCC_C2APB1ENR1_TIM2EN_Msk          (0x1UL << RCC_C2APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
-#define RCC_C2APB1ENR1_TIM2EN              RCC_C2APB1ENR1_TIM2EN_Msk
-#define RCC_C2APB1ENR1_RTCAPBEN_Pos        (10U)
-#define RCC_C2APB1ENR1_RTCAPBEN_Msk        (0x1UL << RCC_C2APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
-#define RCC_C2APB1ENR1_RTCAPBEN            RCC_C2APB1ENR1_RTCAPBEN_Msk
-#define RCC_C2APB1ENR1_SPI2EN_Pos          (14U)
-#define RCC_C2APB1ENR1_SPI2EN_Msk          (0x1UL << RCC_C2APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
-#define RCC_C2APB1ENR1_SPI2EN              RCC_C2APB1ENR1_SPI2EN_Msk
-#define RCC_C2APB1ENR1_USART2EN_Pos        (17U)
-#define RCC_C2APB1ENR1_USART2EN_Msk        (0x1UL << RCC_C2APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
-#define RCC_C2APB1ENR1_USART2EN            RCC_C2APB1ENR1_USART2EN_Msk
-#define RCC_C2APB1ENR1_I2C1EN_Pos          (21U)
-#define RCC_C2APB1ENR1_I2C1EN_Msk          (0x1UL << RCC_C2APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
-#define RCC_C2APB1ENR1_I2C1EN              RCC_C2APB1ENR1_I2C1EN_Msk
-#define RCC_C2APB1ENR1_I2C2EN_Pos          (22U)
-#define RCC_C2APB1ENR1_I2C2EN_Msk          (0x1UL << RCC_C2APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
-#define RCC_C2APB1ENR1_I2C2EN              RCC_C2APB1ENR1_I2C2EN_Msk
-#define RCC_C2APB1ENR1_I2C3EN_Pos          (23U)
-#define RCC_C2APB1ENR1_I2C3EN_Msk          (0x1UL << RCC_C2APB1ENR1_I2C3EN_Pos)/*!< 0x00800000 */
-#define RCC_C2APB1ENR1_I2C3EN              RCC_C2APB1ENR1_I2C3EN_Msk
-#define RCC_C2APB1ENR1_DACEN_Pos           (29U)
-#define RCC_C2APB1ENR1_DACEN_Msk           (0x1UL << RCC_C2APB1ENR1_DACEN_Pos)/*!< 0x20000000 */
-#define RCC_C2APB1ENR1_DACEN               RCC_C2APB1ENR1_DACEN_Msk
-#define RCC_C2APB1ENR1_LPTIM1EN_Pos        (31U)
-#define RCC_C2APB1ENR1_LPTIM1EN_Msk        (0x1UL << RCC_C2APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
-#define RCC_C2APB1ENR1_LPTIM1EN            RCC_C2APB1ENR1_LPTIM1EN_Msk
-
-/********************  Bit definition for RCC_C2APB1ENR2 register  **************/
-#define RCC_C2APB1ENR2_LPUART1EN_Pos       (0U)
-#define RCC_C2APB1ENR2_LPUART1EN_Msk       (0x1UL << RCC_C2APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
-#define RCC_C2APB1ENR2_LPUART1EN           RCC_C2APB1ENR2_LPUART1EN_Msk
-#define RCC_C2APB1ENR2_LPTIM2EN_Pos        (5U)
-#define RCC_C2APB1ENR2_LPTIM2EN_Msk        (0x1UL << RCC_C2APB1ENR2_LPTIM2EN_Pos)/*!< 0x00000020 */
-#define RCC_C2APB1ENR2_LPTIM2EN            RCC_C2APB1ENR2_LPTIM2EN_Msk
-#define RCC_C2APB1ENR2_LPTIM3EN_Pos        (6U)
-#define RCC_C2APB1ENR2_LPTIM3EN_Msk        (0x1UL << RCC_C2APB1ENR2_LPTIM3EN_Pos)/*!< 0x00000040 */
-#define RCC_C2APB1ENR2_LPTIM3EN            RCC_C2APB1ENR2_LPTIM3EN_Msk
-
-/********************  Bit definition for RCC_C2APB2ENR register  **************/
-#define RCC_C2APB2ENR_ADCEN_Pos            (9U)
-#define RCC_C2APB2ENR_ADCEN_Msk            (0x1UL << RCC_C2APB2ENR_ADCEN_Pos)/*!< 0x00000200 */
-#define RCC_C2APB2ENR_ADCEN                RCC_C2APB2ENR_ADCEN_Msk
-#define RCC_C2APB2ENR_TIM1EN_Pos           (11U)
-#define RCC_C2APB2ENR_TIM1EN_Msk           (0x1UL << RCC_C2APB2ENR_TIM1EN_Pos)/*!< 0x00000800 */
-#define RCC_C2APB2ENR_TIM1EN               RCC_C2APB2ENR_TIM1EN_Msk
-#define RCC_C2APB2ENR_SPI1EN_Pos           (12U)
-#define RCC_C2APB2ENR_SPI1EN_Msk           (0x1UL << RCC_C2APB2ENR_SPI1EN_Pos)/*!< 0x00001000 */
-#define RCC_C2APB2ENR_SPI1EN               RCC_C2APB2ENR_SPI1EN_Msk
-#define RCC_C2APB2ENR_USART1EN_Pos         (14U)
-#define RCC_C2APB2ENR_USART1EN_Msk         (0x1UL << RCC_C2APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
-#define RCC_C2APB2ENR_USART1EN             RCC_C2APB2ENR_USART1EN_Msk
-#define RCC_C2APB2ENR_TIM16EN_Pos          (17U)
-#define RCC_C2APB2ENR_TIM16EN_Msk          (0x1UL << RCC_C2APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
-#define RCC_C2APB2ENR_TIM16EN              RCC_C2APB2ENR_TIM16EN_Msk
-#define RCC_C2APB2ENR_TIM17EN_Pos          (18U)
-#define RCC_C2APB2ENR_TIM17EN_Msk          (0x1UL << RCC_C2APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
-#define RCC_C2APB2ENR_TIM17EN              RCC_C2APB2ENR_TIM17EN_Msk
-#define RCC_C2APB2ENR_SAI1EN_Pos           (21U)
-#define RCC_C2APB2ENR_SAI1EN_Msk           (0x1UL << RCC_C2APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
-#define RCC_C2APB2ENR_SAI1EN               RCC_C2APB2ENR_SAI1EN_Msk
-
-/********************  Bit definition for RCC_C2APB3ENR register  **************/
-#define RCC_C2APB3ENR_SUBGHZSPIEN_Pos      (0U)
-#define RCC_C2APB3ENR_SUBGHZSPIEN_Msk      (0x1UL << RCC_C2APB3ENR_SUBGHZSPIEN_Pos)/*!< 0x00000001 */
-#define RCC_C2APB3ENR_SUBGHZSPIEN          RCC_C2APB3ENR_SUBGHZSPIEN_Msk
-
-/********************  Bit definition for RCC_C2AHB1SMENR register  ****************/
-#define RCC_C2AHB1SMENR_DMA1SMEN_Pos       (0U)
-#define RCC_C2AHB1SMENR_DMA1SMEN_Msk       (0x1UL << RCC_C2AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
-#define RCC_C2AHB1SMENR_DMA1SMEN           RCC_C2AHB1SMENR_DMA1SMEN_Msk
-#define RCC_C2AHB1SMENR_DMA2SMEN_Pos       (1U)
-#define RCC_C2AHB1SMENR_DMA2SMEN_Msk       (0x1UL << RCC_C2AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
-#define RCC_C2AHB1SMENR_DMA2SMEN           RCC_C2AHB1SMENR_DMA2SMEN_Msk
-#define RCC_C2AHB1SMENR_DMAMUX1SMEN_Pos    (2U)
-#define RCC_C2AHB1SMENR_DMAMUX1SMEN_Msk    (0x1UL << RCC_C2AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
-#define RCC_C2AHB1SMENR_DMAMUX1SMEN        RCC_C2AHB1SMENR_DMAMUX1SMEN_Msk
-#define RCC_C2AHB1SMENR_CRCSMEN_Pos        (12U)
-#define RCC_C2AHB1SMENR_CRCSMEN_Msk        (0x1UL << RCC_C2AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
-#define RCC_C2AHB1SMENR_CRCSMEN            RCC_C2AHB1SMENR_CRCSMEN_Msk
-
-/********************  Bit definition for RCC_C2AHB2SMENR register  ***************/
-#define RCC_C2AHB2SMENR_GPIOASMEN_Pos      (0U)
-#define RCC_C2AHB2SMENR_GPIOASMEN_Msk      (0x1UL << RCC_C2AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
-#define RCC_C2AHB2SMENR_GPIOASMEN          RCC_C2AHB2SMENR_GPIOASMEN_Msk
-#define RCC_C2AHB2SMENR_GPIOBSMEN_Pos      (1U)
-#define RCC_C2AHB2SMENR_GPIOBSMEN_Msk      (0x1UL << RCC_C2AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
-#define RCC_C2AHB2SMENR_GPIOBSMEN          RCC_C2AHB2SMENR_GPIOBSMEN_Msk
-#define RCC_C2AHB2SMENR_GPIOCSMEN_Pos      (2U)
-#define RCC_C2AHB2SMENR_GPIOCSMEN_Msk      (0x1UL << RCC_C2AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
-#define RCC_C2AHB2SMENR_GPIOCSMEN          RCC_C2AHB2SMENR_GPIOCSMEN_Msk
-#define RCC_C2AHB2SMENR_GPIOHSMEN_Pos      (7U)
-#define RCC_C2AHB2SMENR_GPIOHSMEN_Msk      (0x1UL << RCC_C2AHB2SMENR_GPIOHSMEN_Pos)/*!< 0x00000080 */
-#define RCC_C2AHB2SMENR_GPIOHSMEN          RCC_C2AHB2SMENR_GPIOHSMEN_Msk
-
-/********************  Bit definition for RCC_C2AHB3SMENR register  ***************/
-#define RCC_C2AHB3SMENR_PKASMEN_Pos        (16U)
-#define RCC_C2AHB3SMENR_PKASMEN_Msk        (0x1UL << RCC_C2AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */
-#define RCC_C2AHB3SMENR_PKASMEN            RCC_C2AHB3SMENR_PKASMEN_Msk
-#define RCC_C2AHB3SMENR_AESSMEN_Pos        (17U)
-#define RCC_C2AHB3SMENR_AESSMEN_Msk        (0x1UL << RCC_C2AHB3SMENR_AESSMEN_Pos)/*!< 0x00020000 */
-#define RCC_C2AHB3SMENR_AESSMEN            RCC_C2AHB3SMENR_AESSMEN_Msk
-#define RCC_C2AHB3SMENR_RNGSMEN_Pos        (18U)
-#define RCC_C2AHB3SMENR_RNGSMEN_Msk        (0x1UL << RCC_C2AHB3SMENR_RNGSMEN_Pos)/*!< 0x00040000 */
-#define RCC_C2AHB3SMENR_RNGSMEN            RCC_C2AHB3SMENR_RNGSMEN_Msk
-#define RCC_C2AHB3SMENR_SRAM1SMEN_Pos      (23U)
-#define RCC_C2AHB3SMENR_SRAM1SMEN_Msk      (0x1UL << RCC_C2AHB3SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
-#define RCC_C2AHB3SMENR_SRAM1SMEN          RCC_C2AHB3SMENR_SRAM1SMEN_Msk
-#define RCC_C2AHB3SMENR_SRAM2SMEN_Pos      (24U)
-#define RCC_C2AHB3SMENR_SRAM2SMEN_Msk      (0x1UL << RCC_C2AHB3SMENR_SRAM2SMEN_Pos)/*!< 0x01000000 */
-#define RCC_C2AHB3SMENR_SRAM2SMEN           RCC_C2AHB3SMENR_SRAM2SMEN_Msk
-#define RCC_C2AHB3SMENR_FLASHSMEN_Pos      (25U)
-#define RCC_C2AHB3SMENR_FLASHSMEN_Msk      (0x1UL << RCC_C2AHB3SMENR_FLASHSMEN_Pos)/*!< 0x02000000 */
-#define RCC_C2AHB3SMENR_FLASHSMEN           RCC_C2AHB3SMENR_FLASHSMEN_Msk
-
-/********************  Bit definition for RCC_C2APB1SMENR1 register  **************/
-#define RCC_C2APB1SMENR1_TIM2SMEN_Pos      (0U)
-#define RCC_C2APB1SMENR1_TIM2SMEN_Msk      (0x1UL << RCC_C2APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
-#define RCC_C2APB1SMENR1_TIM2SMEN          RCC_C2APB1SMENR1_TIM2SMEN_Msk
-#define RCC_C2APB1SMENR1_RTCAPBSMEN_Pos    (10U)
-#define RCC_C2APB1SMENR1_RTCAPBSMEN_Msk    (0x1UL << RCC_C2APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
-#define RCC_C2APB1SMENR1_RTCAPBSMEN        RCC_C2APB1SMENR1_RTCAPBSMEN_Msk
-#define RCC_C2APB1SMENR1_SPI2SMEN_Pos      (14U)
-#define RCC_C2APB1SMENR1_SPI2SMEN_Msk      (0x1UL << RCC_C2APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
-#define RCC_C2APB1SMENR1_SPI2SMEN          RCC_C2APB1SMENR1_SPI2SMEN_Msk
-#define RCC_C2APB1SMENR1_USART2SMEN_Pos    (17U)
-#define RCC_C2APB1SMENR1_USART2SMEN_Msk    (0x1UL << RCC_C2APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
-#define RCC_C2APB1SMENR1_USART2SMEN        RCC_C2APB1SMENR1_USART2SMEN_Msk
-#define RCC_C2APB1SMENR1_I2C1SMEN_Pos      (21U)
-#define RCC_C2APB1SMENR1_I2C1SMEN_Msk      (0x1UL << RCC_C2APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
-#define RCC_C2APB1SMENR1_I2C1SMEN          RCC_C2APB1SMENR1_I2C1SMEN_Msk
-#define RCC_C2APB1SMENR1_I2C2SMEN_Pos      (22U)
-#define RCC_C2APB1SMENR1_I2C2SMEN_Msk      (0x1UL << RCC_C2APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
-#define RCC_C2APB1SMENR1_I2C2SMEN          RCC_C2APB1SMENR1_I2C2SMEN_Msk
-#define RCC_C2APB1SMENR1_I2C3SMEN_Pos      (23U)
-#define RCC_C2APB1SMENR1_I2C3SMEN_Msk      (0x1UL << RCC_C2APB1SMENR1_I2C3SMEN_Pos)/*!< 0x00800000 */
-#define RCC_C2APB1SMENR1_I2C3SMEN          RCC_C2APB1SMENR1_I2C3SMEN_Msk
-#define RCC_C2APB1SMENR1_DACSMEN_Pos       (29U)
-#define RCC_C2APB1SMENR1_DACSMEN_Msk       (0x1UL << RCC_C2APB1SMENR1_DACSMEN_Pos)/*!< 0x20000000 */
-#define RCC_C2APB1SMENR1_DACSMEN           RCC_C2APB1SMENR1_DACSMEN_Msk
-#define RCC_C2APB1SMENR1_LPTIM1SMEN_Pos    (31U)
-#define RCC_C2APB1SMENR1_LPTIM1SMEN_Msk    (0x1UL << RCC_C2APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
-#define RCC_C2APB1SMENR1_LPTIM1SMEN        RCC_C2APB1SMENR1_LPTIM1SMEN_Msk
-
-/********************  Bit definition for RCC_C2APB1SMENR2 register  **************/
-#define RCC_C2APB1SMENR2_LPUART1SMEN_Pos    (0U)
-#define RCC_C2APB1SMENR2_LPUART1SMEN_Msk    (0x1UL << RCC_C2APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
-#define RCC_C2APB1SMENR2_LPUART1SMEN        RCC_C2APB1SMENR2_LPUART1SMEN_Msk
-#define RCC_C2APB1SMENR2_LPTIM2SMEN_Pos     (5U)
-#define RCC_C2APB1SMENR2_LPTIM2SMEN_Msk     (0x1UL << RCC_C2APB1SMENR2_LPTIM2SMEN_Pos)/*!< 0x00000020 */
-#define RCC_C2APB1SMENR2_LPTIM2SMEN         RCC_C2APB1SMENR2_LPTIM2SMEN_Msk
-#define RCC_C2APB1SMENR2_LPTIM3SMEN_Pos     (6U)
-#define RCC_C2APB1SMENR2_LPTIM3SMEN_Msk     (0x1UL << RCC_C2APB1SMENR2_LPTIM3SMEN_Pos)/*!< 0x00000040 */
-#define RCC_C2APB1SMENR2_LPTIM3SMEN         RCC_C2APB1SMENR2_LPTIM3SMEN_Msk
-
-/********************  Bit definition for RCC_C2APB2SMENR register  **************/
-#define RCC_C2APB2SMENR_ADCSMEN_Pos        (9U)
-#define RCC_C2APB2SMENR_ADCSMEN_Msk        (0x1UL << RCC_C2APB2SMENR_ADCSMEN_Pos)/*!< 0x00000200 */
-#define RCC_C2APB2SMENR_ADCSMEN            RCC_C2APB2SMENR_ADCSMEN_Msk
-#define RCC_C2APB2SMENR_TIM1SMEN_Pos       (11U)
-#define RCC_C2APB2SMENR_TIM1SMEN_Msk       (0x1UL << RCC_C2APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
-#define RCC_C2APB2SMENR_TIM1SMEN           RCC_C2APB2SMENR_TIM1SMEN_Msk
-#define RCC_C2APB2SMENR_SPI1SMEN_Pos       (12U)
-#define RCC_C2APB2SMENR_SPI1SMEN_Msk       (0x1UL << RCC_C2APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
-#define RCC_C2APB2SMENR_SPI1SMEN           RCC_C2APB2SMENR_SPI1SMEN_Msk
-#define RCC_C2APB2SMENR_USART1SMEN_Pos     (14U)
-#define RCC_C2APB2SMENR_USART1SMEN_Msk     (0x1UL << RCC_C2APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
-#define RCC_C2APB2SMENR_USART1SMEN         RCC_C2APB2SMENR_USART1SMEN_Msk
-#define RCC_C2APB2SMENR_TIM16SMEN_Pos      (17U)
-#define RCC_C2APB2SMENR_TIM16SMEN_Msk      (0x1UL << RCC_C2APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
-#define RCC_C2APB2SMENR_TIM16SMEN          RCC_C2APB2SMENR_TIM16SMEN_Msk
-#define RCC_C2APB2SMENR_TIM17SMEN_Pos      (18U)
-#define RCC_C2APB2SMENR_TIM17SMEN_Msk      (0x1UL << RCC_C2APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
-#define RCC_C2APB2SMENR_TIM17SMEN          RCC_C2APB2SMENR_TIM17SMEN_Msk
-
-/********************  Bit definition for RCC_C2APB3SMENR register  **************/
-#define RCC_C2APB3SMENR_SUBGHZSPISMEN_Pos  (0U)
-#define RCC_C2APB3SMENR_SUBGHZSPISMEN_Msk  (0x1UL << RCC_C2APB3SMENR_SUBGHZSPISMEN_Pos)/*!< 0x00000001 */
-#define RCC_C2APB3SMENR_SUBGHZSPISMEN      RCC_C2APB3SMENR_SUBGHZSPISMEN_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions
- */
-#define RNG_VER_3_2
-
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos         (2U)
-#define RNG_CR_RNGEN_Msk         (0x1UL << RNG_CR_RNGEN_Pos)                   /*!< 0x00000004 */
-#define RNG_CR_RNGEN             RNG_CR_RNGEN_Msk
-#define RNG_CR_IE_Pos            (3U)
-#define RNG_CR_IE_Msk            (0x1UL << RNG_CR_IE_Pos)                      /*!< 0x00000008 */
-#define RNG_CR_IE                RNG_CR_IE_Msk
-#define RNG_CR_CED_Pos           (5U)
-#define RNG_CR_CED_Msk           (0x1UL << RNG_CR_CED_Pos)                     /*!< 0x00000020 */
-#define RNG_CR_CED               RNG_CR_CED_Msk
-#define RNG_CR_RNG_CONFIG3_Pos   (8U)
-#define RNG_CR_RNG_CONFIG3_Msk   (0xFUL << RNG_CR_RNG_CONFIG3_Pos)              /*!< 0x00000F00 */
-#define RNG_CR_RNG_CONFIG3       RNG_CR_RNG_CONFIG3_Msk
-#define RNG_CR_NISTC_Pos         (12U)
-#define RNG_CR_NISTC_Msk         (0x1UL << RNG_CR_NISTC_Pos)                   /*!< 0x00001000 */
-#define RNG_CR_NISTC             RNG_CR_NISTC_Msk
-#define RNG_CR_RNG_CONFIG2_Pos   (13U)
-#define RNG_CR_RNG_CONFIG2_Msk   (0x7UL << RNG_CR_RNG_CONFIG2_Pos)              /*!< 0x0000E000 */
-#define RNG_CR_RNG_CONFIG2       RNG_CR_RNG_CONFIG2_Msk
-#define RNG_CR_CLKDIV_Pos        (16U)
-#define RNG_CR_CLKDIV_Msk        (0xFUL << RNG_CR_CLKDIV_Pos)                  /*!< 0x000F0000 */
-#define RNG_CR_CLKDIV            RNG_CR_CLKDIV_Msk
-#define RNG_CR_CLKDIV_0          (0x1UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00010000 */
-#define RNG_CR_CLKDIV_1          (0x2UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00020000 */
-#define RNG_CR_CLKDIV_2          (0x4UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00040000 */
-#define RNG_CR_CLKDIV_3          (0x8UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00080000 */
-#define RNG_CR_RNG_CONFIG1_Pos   (20U)
-#define RNG_CR_RNG_CONFIG1_Msk   (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)             /*!< 0x03F00000 */
-#define RNG_CR_RNG_CONFIG1       RNG_CR_RNG_CONFIG1_Msk
-#define RNG_CR_CONDRST_Pos       (30U)
-#define RNG_CR_CONDRST_Msk       (0x1UL << RNG_CR_CONDRST_Pos)                 /*!< 0x40000000 */
-#define RNG_CR_CONDRST           RNG_CR_CONDRST_Msk
-#define RNG_CR_CONFIGLOCK_Pos    (31U)
-#define RNG_CR_CONFIGLOCK_Msk    (0x1UL << RNG_CR_CONFIGLOCK_Pos)              /*!< 0x80000000 */
-#define RNG_CR_CONFIGLOCK        RNG_CR_CONFIGLOCK_Msk
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)
-#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk
-#define RNG_SR_CECS_Pos     (1U)
-#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk
-#define RNG_SR_SECS_Pos     (2U)
-#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk
-#define RNG_SR_CEIS_Pos     (5U)
-#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk
-#define RNG_SR_SEIS_Pos     (6U)
-#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk
-
-/********************  Bits definition for RNG_DR register  *******************/
-#define RNG_DR_RNDATA_Pos        (0U)
-#define RNG_DR_RNDATA_Msk        (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos)       /*!< 0xFFFFFFFF */
-#define RNG_DR_RNDATA            RNG_DR_RNDATA_Msk
-
-/********************  Bits definition for RNG_HTCR register  *****************/
-#define RNG_HTCR_HTCFG_Pos       (0U)
-#define RNG_HTCR_HTCFG_Msk       (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)      /*!< 0xFFFFFFFF */
-#define RNG_HTCR_HTCFG           RNG_HTCR_HTCFG_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                (22U)
-#define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
-#define RTC_TR_PM                    RTC_TR_PM_Msk
-#define RTC_TR_HT_Pos                (20U)
-#define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
-#define RTC_TR_HT                    RTC_TR_HT_Msk
-#define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
-#define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                (16U)
-#define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
-#define RTC_TR_HU                    RTC_TR_HU_Msk
-#define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
-#define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
-#define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
-#define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos               (12U)
-#define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
-#define RTC_TR_MNT                   RTC_TR_MNT_Msk
-#define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
-#define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
-#define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos               (8U)
-#define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
-#define RTC_TR_MNU                   RTC_TR_MNU_Msk
-#define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
-#define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
-#define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
-#define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                (4U)
-#define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
-#define RTC_TR_ST                    RTC_TR_ST_Msk
-#define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
-#define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
-#define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                (0U)
-#define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
-#define RTC_TR_SU                    RTC_TR_SU_Msk
-#define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
-#define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
-#define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
-#define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                (20U)
-#define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
-#define RTC_DR_YT                    RTC_DR_YT_Msk
-#define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
-#define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
-#define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
-#define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                (16U)
-#define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
-#define RTC_DR_YU                    RTC_DR_YU_Msk
-#define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
-#define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
-#define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
-#define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos               (13U)
-#define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
-#define RTC_DR_WDU                   RTC_DR_WDU_Msk
-#define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
-#define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
-#define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                (12U)
-#define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
-#define RTC_DR_MT                    RTC_DR_MT_Msk
-#define RTC_DR_MU_Pos                (8U)
-#define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
-#define RTC_DR_MU                    RTC_DR_MU_Msk
-#define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
-#define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
-#define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
-#define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                (4U)
-#define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
-#define RTC_DR_DT                    RTC_DR_DT_Msk
-#define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
-#define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                (0U)
-#define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
-#define RTC_DR_DU                    RTC_DR_DU_Msk
-#define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
-#define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
-#define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
-#define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos               (0U)
-#define RTC_SSR_SS_Msk               (0xFFFFFFFFUL << RTC_SSR_SS_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_SSR_SS                   RTC_SSR_SS_Msk
-
-/********************  Bits definition for RTC_ICSR register  ******************/
-#define RTC_ICSR_RECALPF_Pos         (16U)
-#define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
-#define RTC_ICSR_BCDU_Pos            (10U)
-#define RTC_ICSR_BCDU_Msk            (0x7UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00001C00 */
-#define RTC_ICSR_BCDU                RTC_ICSR_BCDU_Msk
-#define RTC_ICSR_BCDU_0              (0x1UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00000400 */
-#define RTC_ICSR_BCDU_1              (0x2UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00000800 */
-#define RTC_ICSR_BCDU_2              (0x4UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00001000 */
-#define RTC_ICSR_BIN_Pos             (8U)
-#define RTC_ICSR_BIN_Msk             (0x3UL << RTC_ICSR_BIN_Pos)               /*!< 0x00000300 */
-#define RTC_ICSR_BIN                 RTC_ICSR_BIN_Msk
-#define RTC_ICSR_BIN_0               (0x1UL << RTC_ICSR_BIN_Pos)               /*!< 0x00000100 */
-#define RTC_ICSR_BIN_1               (0x2UL << RTC_ICSR_BIN_Pos)               /*!< 0x00000200 */
-#define RTC_ICSR_INIT_Pos            (7U)
-#define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
-#define RTC_ICSR_INITF_Pos           (6U)
-#define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
-#define RTC_ICSR_RSF_Pos             (5U)
-#define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
-#define RTC_ICSR_INITS_Pos           (4U)
-#define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
-#define RTC_ICSR_SHPF_Pos            (3U)
-#define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
-#define RTC_ICSR_WUTWF_Pos           (2U)
-#define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos        (16U)
-#define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
-#define RTC_PRER_PREDIV_S_Pos        (0U)
-#define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUTOCLR_Pos         (16U)
-#define RTC_WUTR_WUTOCLR_Msk         (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)        /*!< 0x0000FFFF */
-#define RTC_WUTR_WUTOCLR             RTC_WUTR_WUTOCLR_Msk
-#define RTC_WUTR_WUT_Pos             (0U)
-#define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_OUT2EN_Pos            (31U)
-#define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
-#define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */
-#define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
-#define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
-#define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */
-#define RTC_CR_TAMPALRM_PU_Pos       (29U)
-#define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
-#define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */
-#define RTC_CR_TAMPOE_Pos            (26U)
-#define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
-#define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */
-#define RTC_CR_TAMPTS_Pos            (25U)
-#define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
-#define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */
-#define RTC_CR_ITSE_Pos              (24U)
-#define RTC_CR_ITSE_Msk              (0x1UL << RTC_CR_ITSE_Pos)                /*!< 0x01000000 */
-#define RTC_CR_ITSE                  RTC_CR_ITSE_Msk                           /*!<Timestamp on internal event enable  */
-#define RTC_CR_COE_Pos               (23U)
-#define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
-#define RTC_CR_COE                   RTC_CR_COE_Msk
-#define RTC_CR_OSEL_Pos              (21U)
-#define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
-#define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
-#define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
-#define RTC_CR_POL_Pos               (20U)
-#define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
-#define RTC_CR_POL                   RTC_CR_POL_Msk
-#define RTC_CR_COSEL_Pos             (19U)
-#define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
-#define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
-#define RTC_CR_BKP_Pos               (18U)
-#define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                 /*!< 0x00040000 */
-#define RTC_CR_BKP                   RTC_CR_BKP_Msk
-#define RTC_CR_SUB1H_Pos             (17U)
-#define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
-#define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
-#define RTC_CR_ADD1H_Pos             (16U)
-#define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
-#define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
-#define RTC_CR_TSIE_Pos              (15U)
-#define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
-#define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
-#define RTC_CR_WUTIE_Pos             (14U)
-#define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
-#define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
-#define RTC_CR_ALRBIE_Pos            (13U)
-#define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
-#define RTC_CR_ALRAIE_Pos            (12U)
-#define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
-#define RTC_CR_TSE_Pos               (11U)
-#define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
-#define RTC_CR_TSE                   RTC_CR_TSE_Msk
-#define RTC_CR_WUTE_Pos              (10U)
-#define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
-#define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
-#define RTC_CR_ALRBE_Pos             (9U)
-#define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
-#define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
-#define RTC_CR_ALRAE_Pos             (8U)
-#define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
-#define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
-#define RTC_CR_SSRUIE_Pos            (7U)
-#define RTC_CR_SSRUIE_Msk            (0x1UL << RTC_CR_SSRUIE_Pos)              /*!< 0x00000080 */
-#define RTC_CR_SSRUIE                RTC_CR_SSRUIE_Msk
-#define RTC_CR_FMT_Pos               (6U)
-#define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
-#define RTC_CR_FMT                   RTC_CR_FMT_Msk
-#define RTC_CR_BYPSHAD_Pos           (5U)
-#define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
-#define RTC_CR_REFCKON_Pos           (4U)
-#define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
-#define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
-#define RTC_CR_TSEDGE_Pos            (3U)
-#define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
-#define RTC_CR_WUCKSEL_Pos           (0U)
-#define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
-#define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos              (0U)
-#define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
-#define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos            (15U)
-#define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
-#define RTC_CALR_CALP                RTC_CALR_CALP_Msk
-#define RTC_CALR_CALW8_Pos           (14U)
-#define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
-#define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
-#define RTC_CALR_CALW16_Pos          (13U)
-#define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
-#define RTC_CALR_LPCAL               RTC_CALR_LPCAL_Msk
-#define RTC_CALR_LPCAL_Pos           (12U)
-#define RTC_CALR_LPCAL_Msk           (0x1UL << RTC_CALR_LPCAL_Pos)             /*!< 0x00001000 */
-#define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
-#define RTC_CALR_CALM_Pos            (0U)
-#define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
-#define RTC_CALR_CALM                RTC_CALR_CALM_Msk
-#define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
-#define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
-#define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
-#define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
-#define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
-#define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
-#define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
-#define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
-#define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_ADD1S_Pos         (31U)
-#define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
-#define RTC_SHIFTR_SUBFS_Pos         (0U)
-#define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos              (22U)
-#define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
-#define RTC_TSTR_PM                  RTC_TSTR_PM_Msk                           
-#define RTC_TSTR_HT_Pos              (20U)
-#define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
-#define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
-#define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos              (16U)
-#define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
-#define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
-#define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos             (12U)
-#define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
-#define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
-#define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos             (8U)
-#define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
-#define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos              (4U)
-#define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
-#define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
-#define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos              (0U)
-#define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
-#define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
-#define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos             (13U)
-#define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk                          
-#define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos              (12U)
-#define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
-#define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
-#define RTC_TSDR_MU_Pos              (8U)
-#define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
-#define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
-#define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos              (4U)
-#define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
-#define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
-#define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos              (0U)
-#define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
-#define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
-#define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos             (0U)
-#define RTC_TSSSR_SS_Msk             (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)        /*!< 0xFFFFFFFF */
-#define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk                          
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos          (31U)
-#define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
-#define RTC_ALRMAR_WDSEL_Pos         (30U)
-#define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
-#define RTC_ALRMAR_DT_Pos            (28U)
-#define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
-#define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos            (24U)
-#define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
-#define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos          (23U)
-#define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
-#define RTC_ALRMAR_PM_Pos            (22U)
-#define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
-#define RTC_ALRMAR_HT_Pos            (20U)
-#define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
-#define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos            (16U)
-#define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
-#define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos          (15U)
-#define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
-#define RTC_ALRMAR_MNT_Pos           (12U)
-#define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
-#define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos           (8U)
-#define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
-#define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos          (7U)
-#define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
-#define RTC_ALRMAR_ST_Pos            (4U)
-#define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
-#define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos            (0U)
-#define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
-#define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_SSCLR_Pos       (31U)
-#define RTC_ALRMASSR_SSCLR_Msk       (0x1UL << RTC_ALRMASSR_SSCLR_Pos)         /*!< 0x80000000 */
-#define RTC_ALRMASSR_SSCLR           RTC_ALRMASSR_SSCLR_Msk
-#define RTC_ALRMASSR_MASKSS_Pos      (24U)
-#define RTC_ALRMASSR_MASKSS_Msk      (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
-#define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMASSR_MASKSS_4        (0x10UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMASSR_MASKSS_5        (0x20UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos          (0U)
-#define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos          (31U)
-#define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
-#define RTC_ALRMBR_WDSEL_Pos         (30U)
-#define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
-#define RTC_ALRMBR_DT_Pos            (28U)
-#define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
-#define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos            (24U)
-#define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
-#define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos          (23U)
-#define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
-#define RTC_ALRMBR_PM_Pos            (22U)
-#define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
-#define RTC_ALRMBR_HT_Pos            (20U)
-#define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
-#define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos            (16U)
-#define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
-#define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos          (15U)
-#define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
-#define RTC_ALRMBR_MNT_Pos           (12U)
-#define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
-#define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos           (8U)
-#define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
-#define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos          (7U)
-#define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
-#define RTC_ALRMBR_ST_Pos            (4U)
-#define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
-#define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos            (0U)
-#define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
-#define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_SSCLR_Pos       (31U)
-#define RTC_ALRMBSSR_SSCLR_Msk       (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)         /*!< 0x80000000 */
-#define RTC_ALRMBSSR_SSCLR           RTC_ALRMBSSR_SSCLR_Msk
-#define RTC_ALRMBSSR_MASKSS_Pos      (24U)
-#define RTC_ALRMBSSR_MASKSS_Msk      (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
-#define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMBSSR_MASKSS_4        (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBSSR_MASKSS_5        (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBSSR_SS_Pos          (0U)
-#define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
-
-/********************  Bits definition for RTC_SR register  *******************/
-#define RTC_SR_SSRUF_Pos             (6U)
-#define RTC_SR_SSRUF_Msk             (0x1UL << RTC_SR_SSRUF_Pos)               /*!< 0x00000040 */
-#define RTC_SR_SSRUF                 RTC_SR_SSRUF_Msk
-#define RTC_SR_ITSF_Pos              (5U)
-#define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                /*!< 0x00000020 */
-#define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
-#define RTC_SR_TSOVF_Pos             (4U)
-#define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */
-#define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk
-#define RTC_SR_TSF_Pos               (3U)
-#define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */
-#define RTC_SR_TSF                   RTC_SR_TSF_Msk
-#define RTC_SR_WUTF_Pos              (2U)
-#define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                /*!< 0x00000004 */
-#define RTC_SR_WUTF                  RTC_SR_WUTF_Msk
-#define RTC_SR_ALRBF_Pos             (1U)
-#define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)               /*!< 0x00000002 */
-#define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
-#define RTC_SR_ALRAF_Pos             (0U)
-#define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */
-#define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
-
-/********************  Bits definition for RTC_MISR register  *****************/
-#define RTC_MISR_SSRUMF_Pos          (6U)
-#define RTC_MISR_SSRUMF_Msk          (0x1UL << RTC_MISR_SSRUMF_Pos)            /*!< 0x00000040 */
-#define RTC_MISR_SSRUMF              RTC_MISR_SSRUMF_Msk
-#define RTC_MISR_ITSMF_Pos           (5U)
-#define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)             /*!< 0x00000020 */
-#define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
-#define RTC_MISR_TSOVMF_Pos          (4U)
-#define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */
-#define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk
-#define RTC_MISR_TSMF_Pos            (3U)
-#define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */
-#define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk
-#define RTC_MISR_WUTMF_Pos           (2U)
-#define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)             /*!< 0x00000004 */
-#define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk
-#define RTC_MISR_ALRBMF_Pos          (1U)
-#define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)            /*!< 0x00000002 */
-#define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
-#define RTC_MISR_ALRAMF_Pos          (0U)
-#define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */
-#define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
-
-/********************  Bits definition for RTC_SCR register  ******************/
-#define RTC_SCR_CSSRUF_Pos           (6U)
-#define RTC_SCR_CSSRUF_Msk           (0x1UL << RTC_SCR_CSSRUF_Pos)             /*!< 0x00000040 */
-#define RTC_SCR_CSSRUF               RTC_SCR_CSSRUF_Msk
-#define RTC_SCR_CITSF_Pos            (5U)
-#define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)              /*!< 0x00000020 */
-#define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
-#define RTC_SCR_CTSOVF_Pos           (4U)
-#define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */
-#define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk
-#define RTC_SCR_CTSF_Pos             (3U)
-#define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */
-#define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk
-#define RTC_SCR_CWUTF_Pos            (2U)
-#define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)              /*!< 0x00000004 */
-#define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk
-#define RTC_SCR_CALRBF_Pos           (1U)
-#define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)             /*!< 0x00000002 */
-#define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
-#define RTC_SCR_CALRAF_Pos           (0U)
-#define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */
-#define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
-
-/********************  Bits definition for RTC_ALRABINR register  ******************/
-#define RTC_ALRABINR_SS_Pos          (0U)
-#define RTC_ALRABINR_SS_Msk          (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)     /*!< 0xFFFFFFFF */
-#define RTC_ALRABINR_SS              RTC_ALRABINR_SS_Msk
-
-/********************  Bits definition for RTC_ALRBBINR register  ******************/
-#define RTC_ALRBBINR_SS_Pos          (0U)
-#define RTC_ALRBBINR_SS_Msk          (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)     /*!< 0xFFFFFFFF */
-#define RTC_ALRBBINR_SS              RTC_ALRBBINR_SS_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
-#define SPI_CR1_CPOL_Pos            (1U)
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
-#define SPI_CR1_MSTR_Pos            (2U)
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
-
-#define SPI_CR1_BR_Pos              (3U)
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos             (6U)
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
-#define SPI_CR1_LSBFIRST_Pos        (7U)
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
-#define SPI_CR1_SSI_Pos             (8U)
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
-#define SPI_CR1_SSM_Pos             (9U)
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
-#define SPI_CR1_RXONLY_Pos          (10U)
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
-#define SPI_CR1_CRCL_Pos            (11U)
-#define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
-#define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
-#define SPI_CR1_CRCNEXT_Pos         (12U)
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
-#define SPI_CR1_CRCEN_Pos           (13U)
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
-#define SPI_CR1_BIDIOE_Pos          (14U)
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_NSSP_Pos            (3U)
-#define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
-#define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
-#define SPI_CR2_FRF_Pos             (4U)
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-#define SPI_CR2_DS_Pos              (8U)
-#define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
-#define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
-#define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
-#define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
-#define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
-#define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
-#define SPI_CR2_FRXTH_Pos           (12U)
-#define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
-#define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
-#define SPI_CR2_LDMARX_Pos          (13U)
-#define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
-#define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
-#define SPI_CR2_LDMATX_Pos          (14U)
-#define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
-#define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
-#define SPI_SR_FRLVL_Pos            (9U)
-#define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
-#define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
-#define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
-#define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
-#define SPI_SR_FTLVL_Pos            (11U)
-#define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
-#define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
-#define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
-#define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)            /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
-#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)         /*!< 0x00001000 */
-#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)           /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)               /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)             /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Tamper and backup register (TAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for TAMP_CR1 register  *****************/
-#define TAMP_CR1_TAMP1E_Pos          (0U)
-#define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */
-#define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
-#define TAMP_CR1_TAMP2E_Pos          (1U)
-#define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */
-#define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
-#define TAMP_CR1_TAMP3E_Pos          (2U)
-#define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */
-#define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk
-#define TAMP_CR1_ITAMP3E_Pos         (18U)
-#define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */
-#define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
-#define TAMP_CR1_ITAMP5E_Pos         (20U)
-#define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */
-#define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
-#define TAMP_CR1_ITAMP6E_Pos         (21U)
-#define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x0020000 */
-#define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
-#define TAMP_CR1_ITAMP8E_Pos         (23U)
-#define TAMP_CR1_ITAMP8E_Msk         (0x1UL << TAMP_CR1_ITAMP8E_Pos)           /*!< 0x00800000 */
-#define TAMP_CR1_ITAMP8E             TAMP_CR1_ITAMP8E_Msk
-
-/********************  Bits definition for TAMP_CR2 register  *****************/
-#define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
-#define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */
-#define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
-#define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
-#define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */
-#define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
-#define TAMP_CR2_TAMP3NOERASE_Pos    (2U)
-#define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */
-#define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk
-#define TAMP_CR2_TAMP1MSK_Pos        (16U)
-#define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)          /*!< 0x00010000 */
-#define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk
-#define TAMP_CR2_TAMP2MSK_Pos        (17U)
-#define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)          /*!< 0x00020000 */
-#define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk
-#define TAMP_CR2_TAMP3MSK_Pos        (18U)
-#define TAMP_CR2_TAMP3MSK_Msk        (0x1UL << TAMP_CR2_TAMP3MSK_Pos)          /*!< 0x00040000 */
-#define TAMP_CR2_TAMP3MSK            TAMP_CR2_TAMP3MSK_Msk
-#define TAMP_CR2_BKERASE_Pos         (23U)
-#define TAMP_CR2_BKERASE_Msk         (0x1UL << TAMP_CR2_BKERASE_Pos)           /*!< 0x00800000 */
-#define TAMP_CR2_BKERASE             TAMP_CR2_BKERASE_Msk
-#define TAMP_CR2_TAMP1TRG_Pos        (24U)
-#define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */
-#define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
-#define TAMP_CR2_TAMP2TRG_Pos        (25U)
-#define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */
-#define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
-#define TAMP_CR2_TAMP3TRG_Pos        (26U)
-#define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x02000000 */
-#define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk
-
-/********************  Bits definition for TAMP_CR3 register  *****************/
-#define TAMP_CR3_ITAMP3NOER_Pos      (2U)
-#define TAMP_CR3_ITAMP3NOER_Msk      (0x1UL << TAMP_CR3_ITAMP3NOER_Pos)        /*!< 0x00000004 */
-#define TAMP_CR3_ITAMP3NOER          TAMP_CR3_ITAMP3NOER_Msk
-#define TAMP_CR3_ITAMP5NOER_Pos      (4U)
-#define TAMP_CR3_ITAMP5NOER_Msk      (0x1UL << TAMP_CR3_ITAMP5NOER_Pos)        /*!< 0x00000010 */
-#define TAMP_CR3_ITAMP5NOER          TAMP_CR3_ITAMP5NOER_Msk
-#define TAMP_CR3_ITAMP6NOER_Pos      (5U)
-#define TAMP_CR3_ITAMP6NOER_Msk      (0x1UL << TAMP_CR3_ITAMP6NOER_Pos)        /*!< 0x00000020 */
-#define TAMP_CR3_ITAMP6NOER          TAMP_CR3_ITAMP6NOER_Msk
-#define TAMP_CR3_ITAMP8NOER_Pos      (7U)
-#define TAMP_CR3_ITAMP8NOER_Msk      (0x1UL << TAMP_CR3_ITAMP8NOER_Pos)        /*!< 0x00800000 */
-#define TAMP_CR3_ITAMP8NOER          TAMP_CR3_ITAMP8NOER_Msk
-
-/********************  Bits definition for TAMP_FLTCR register  ***************/
-#define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
-#define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000007 */
-#define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
-#define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000001 */
-#define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000002 */
-#define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000004 */
-#define TAMP_FLTCR_TAMPFLT_Pos       (3U)
-#define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000018 */
-#define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
-#define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000008 */
-#define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000010 */
-#define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
-#define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000060 */
-#define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
-#define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000020 */
-#define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000040 */
-#define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
-#define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)       /*!< 0x00000080 */
-#define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
-
-/********************  Bits definition for TAMP_IER register  *****************/
-#define TAMP_IER_TAMP1IE_Pos         (0U)
-#define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */
-#define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
-#define TAMP_IER_TAMP2IE_Pos         (1U)
-#define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */
-#define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
-#define TAMP_IER_TAMP3IE_Pos         (2U)
-#define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */
-#define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk
-#define TAMP_IER_ITAMP3IE_Pos        (18U)
-#define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */
-#define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
-#define TAMP_IER_ITAMP5IE_Pos        (20U)
-#define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */
-#define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
-#define TAMP_IER_ITAMP6IE_Pos        (21U)
-#define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x0020000 */
-#define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
-#define TAMP_IER_ITAMP8IE_Pos        (23U)
-#define TAMP_IER_ITAMP8IE_Msk        (0x1UL << TAMP_IER_ITAMP8IE_Pos)          /*!< 0x00800000 */
-#define TAMP_IER_ITAMP8IE            TAMP_IER_ITAMP8IE_Msk
-
-/********************  Bits definition for TAMP_SR register  *****************/
-#define TAMP_SR_TAMP1F_Pos           (0U)
-#define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)             /*!< 0x00000001 */
-#define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
-#define TAMP_SR_TAMP2F_Pos           (1U)
-#define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)            /*!< 0x00000002 */
-#define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
-#define TAMP_SR_TAMP3F_Pos           (2U)
-#define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)             /*!< 0x00000004 */
-#define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk
-#define TAMP_SR_ITAMP3F_Pos          (18U)
-#define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)           /*!< 0x00040000 */
-#define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
-#define TAMP_SR_ITAMP5F_Pos          (20U)
-#define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)           /*!< 0x00100000 */
-#define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
-#define TAMP_SR_ITAMP6F_Pos          (21U)
-#define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)           /*!< 0x0020000 */
-#define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
-#define TAMP_SR_ITAMP8F_Pos          (23U)
-#define TAMP_SR_ITAMP8F_Msk          (0x1UL << TAMP_SR_ITAMP8F_Pos)           /*!< 0x00800000 */
-#define TAMP_SR_ITAMP8F              TAMP_SR_ITAMP8F_Msk
-
-/********************  Bits definition for TAMP_MISR register  ************ *****/
-#define TAMP_MISR_TAMP1MF_Pos        (0U)
-#define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)          /*!< 0x00000001 */
-#define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
-#define TAMP_MISR_TAMP2MF_Pos        (1U)
-#define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)          /*!< 0x00000002 */
-#define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
-#define TAMP_MISR_TAMP3MF_Pos        (2U)
-#define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)          /*!< 0x00000004 */
-#define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk
-#define TAMP_MISR_ITAMP3MF_Pos       (18U)
-#define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)           /*!< 0x00040000 */
-#define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
-#define TAMP_MISR_ITAMP5MF_Pos       (20U)
-#define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)           /*!< 0x00100000 */
-#define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
-#define TAMP_MISR_ITAMP6MF_Pos       (21U)
-#define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)           /*!< 0x0020000 */
-#define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
-#define TAMP_MISR_ITAMP8MF_Pos       (23U)
-#define TAMP_MISR_ITAMP8MF_Msk       (0x1UL << TAMP_MISR_ITAMP8MF_Pos)           /*!< 0x00800000 */
-#define TAMP_MISR_ITAMP8MF           TAMP_MISR_ITAMP8MF_Msk
-
-/********************  Bits definition for TAMP_SMISR register  ************ *****/
-#define TAMP_SMISR_TAMP1MF_Pos       (0U)
-#define TAMP_SMISR_TAMP1MF_Msk       (0x1UL << TAMP_SMISR_TAMP1MF_Pos)         /*!< 0x00000001 */
-#define TAMP_SMISR_TAMP1MF           TAMP_SMISR_TAMP1MF_Msk
-#define TAMP_SMISR_TAMP2MF_Pos       (1U)
-#define TAMP_SMISR_TAMP2MF_Msk       (0x1UL << TAMP_SMISR_TAMP2MF_Pos)         /*!< 0x00000002 */
-#define TAMP_SMISR_TAMP2MF           TAMP_SMISR_TAMP2MF_Msk
-#define TAMP_SMISR_TAMP3MF_Pos       (2U)
-#define TAMP_SMISR_TAMP3MF_Msk       (0x1UL << TAMP_SMISR_TAMP3MF_Pos)         /*!< 0x00000004 */
-#define TAMP_SMISR_TAMP3MF           TAMP_SMISR_TAMP3MF_Msk
-#define TAMP_SMISR_ITAMP3MF_Pos      (18U)
-#define TAMP_SMISR_ITAMP3MF_Msk      (0x1UL << TAMP_SMISR_ITAMP3MF_Pos)        /*!< 0x00040000 */
-#define TAMP_SMISR_ITAMP3MF          TAMP_SMISR_ITAMP3MF_Msk
-#define TAMP_SMISR_ITAMP5MF_Pos      (20U)
-#define TAMP_SMISR_ITAMP5MF_Msk      (0x1UL << TAMP_SMISR_ITAMP5MF_Pos)        /*!< 0x00100000 */
-#define TAMP_SMISR_ITAMP5MF          TAMP_SMISR_ITAMP5MF_Msk
-#define TAMP_SMISR_ITAMP6MF_Pos      (21U)
-#define TAMP_SMISR_ITAMP6MF_Msk      (0x1UL << TAMP_SMISR_ITAMP6MF_Pos)        /*!< 0x0020000 */
-#define TAMP_SMISR_ITAMP6MF          TAMP_SMISR_ITAMP6MF_Msk
-#define TAMP_SMISR_ITAMP8MF_Pos      (23U)
-#define TAMP_SMISR_ITAMP8MF_Msk      (0x1UL << TAMP_SMISR_ITAMP8MF_Pos)        /*!< 0x00800000 */
-#define TAMP_SMISR_ITAMP8MF          TAMP_SMISR_ITAMP8MF_Msk
-
-/********************  Bits definition for TAMP_SCR register  *****************/
-#define TAMP_SCR_CTAMP1F_Pos         (0U)
-#define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)           /*!< 0x00000001 */
-#define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
-#define TAMP_SCR_CTAMP2F_Pos         (1U)
-#define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)           /*!< 0x00000002 */
-#define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
-#define TAMP_SCR_CTAMP3F_Pos         (2U)
-#define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)           /*!< 0x00000004 */
-#define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk
-#define TAMP_SCR_CITAMP3F_Pos        (18U)
-#define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)          /*!< 0x00040000 */
-#define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
-#define TAMP_SCR_CITAMP5F_Pos        (20U)
-#define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)          /*!< 0x00100000 */
-#define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
-#define TAMP_SCR_CITAMP6F_Pos        (21U)
-#define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)          /*!< 0x0020000 */
-#define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
-#define TAMP_SCR_CITAMP8F_Pos        (23U)
-#define TAMP_SCR_CITAMP8F_Msk        (0x1UL << TAMP_SCR_CITAMP8F_Pos)          /*!< 0x00800000 */
-#define TAMP_SCR_CITAMP8F            TAMP_SCR_CITAMP8F_Msk
-
-/********************  Bits definition for TAMP_COUNTR register  ***************/
-#define TAMP_COUNTR_Pos               (0U)
-#define TAMP_COUNTR_Msk               (0xFFFFFFFFUL << TAMP_COUNTR_Pos)        /*!< 0xFFFFFFFF */
-#define TAMP_COUNTR                   TAMP_COUNTR_Msk
-
-/********************  Bits definition for TAMP_BKP0R register  ***************/
-#define TAMP_BKP0R_Pos               (0U)
-#define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP0R                   TAMP_BKP0R_Msk
-
-/********************  Bits definition for TAMP_BKP1R register  ****************/
-#define TAMP_BKP1R_Pos               (0U)
-#define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP1R                   TAMP_BKP1R_Msk
-
-/********************  Bits definition for TAMP_BKP2R register  ****************/
-#define TAMP_BKP2R_Pos               (0U)
-#define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP2R                   TAMP_BKP2R_Msk
-
-/********************  Bits definition for TAMP_BKP3R register  ****************/
-#define TAMP_BKP3R_Pos               (0U)
-#define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP3R                   TAMP_BKP3R_Msk
-
-/********************  Bits definition for TAMP_BKP4R register  ****************/
-#define TAMP_BKP4R_Pos               (0U)
-#define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP4R                   TAMP_BKP4R_Msk
-
-/********************  Bits definition for TAMP_BKP5R register  ****************/
-#define TAMP_BKP5R_Pos               (0U)
-#define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP5R                   TAMP_BKP5R_Msk
-
-/********************  Bits definition for TAMP_BKP6R register  ****************/
-#define TAMP_BKP6R_Pos               (0U)
-#define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP6R                   TAMP_BKP6R_Msk
-
-/********************  Bits definition for TAMP_BKP7R register  ****************/
-#define TAMP_BKP7R_Pos               (0U)
-#define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP7R                   TAMP_BKP7R_Msk
-
-/********************  Bits definition for TAMP_BKP8R register  ****************/
-#define TAMP_BKP8R_Pos               (0U)
-#define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP8R                   TAMP_BKP8R_Msk
-
-/********************  Bits definition for TAMP_BKP9R register  ****************/
-#define TAMP_BKP9R_Pos               (0U)
-#define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP9R                   TAMP_BKP9R_Msk
-
-/********************  Bits definition for TAMP_BKP10R register  ***************/
-#define TAMP_BKP10R_Pos              (0U)
-#define TAMP_BKP10R_Msk              (0xFFFFFFFFUL << TAMP_BKP10R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP10R                  TAMP_BKP10R_Msk
-
-/********************  Bits definition for TAMP_BKP11R register  ***************/
-#define TAMP_BKP11R_Pos              (0U)
-#define TAMP_BKP11R_Msk              (0xFFFFFFFFUL << TAMP_BKP11R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP11R                  TAMP_BKP11R_Msk
-
-/********************  Bits definition for TAMP_BKP12R register  ***************/
-#define TAMP_BKP12R_Pos              (0U)
-#define TAMP_BKP12R_Msk              (0xFFFFFFFFUL << TAMP_BKP12R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP12R                  TAMP_BKP12R_Msk
-
-/********************  Bits definition for TAMP_BKP13R register  ***************/
-#define TAMP_BKP13R_Pos              (0U)
-#define TAMP_BKP13R_Msk              (0xFFFFFFFFUL << TAMP_BKP13R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP13R                  TAMP_BKP13R_Msk
-
-/********************  Bits definition for TAMP_BKP14R register  ***************/
-#define TAMP_BKP14R_Pos              (0U)
-#define TAMP_BKP14R_Msk              (0xFFFFFFFFUL << TAMP_BKP14R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP14R                  TAMP_BKP14R_Msk
-
-/********************  Bits definition for TAMP_BKP15R register  ***************/
-#define TAMP_BKP15R_Pos              (0U)
-#define TAMP_BKP15R_Msk              (0xFFFFFFFFUL << TAMP_BKP15R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP15R                  TAMP_BKP15R_Msk
-
-/********************  Bits definition for TAMP_BKP16R register  ***************/
-#define TAMP_BKP16R_Pos              (0U)
-#define TAMP_BKP16R_Msk              (0xFFFFFFFFUL << TAMP_BKP16R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP16R                  TAMP_BKP16R_Msk
-
-/********************  Bits definition for TAMP_BKP17R register  ***************/
-#define TAMP_BKP17R_Pos              (0U)
-#define TAMP_BKP17R_Msk              (0xFFFFFFFFUL << TAMP_BKP17R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP17R                  TAMP_BKP17R_Msk
-
-/********************  Bits definition for TAMP_BKP18R register  ***************/
-#define TAMP_BKP18R_Pos              (0U)
-#define TAMP_BKP18R_Msk              (0xFFFFFFFFUL << TAMP_BKP18R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP18R                  TAMP_BKP18R_Msk
-
-/********************  Bits definition for TAMP_BKP19R register  ***************/
-#define TAMP_BKP19R_Pos              (0U)
-#define TAMP_BKP19R_Msk              (0xFFFFFFFFUL << TAMP_BKP19R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP19R                  TAMP_BKP19R_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  (SYSCFG memory remap register) ***********************************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos              (0U)
-#define SYSCFG_MEMRMP_MEM_MODE_Msk              (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000007 */
-#define SYSCFG_MEMRMP_MEM_MODE                  SYSCFG_MEMRMP_MEM_MODE_Msk                      /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0                (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1                (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_MEM_MODE_2                (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000004 */
-
-/*****************  Bit definition for SYSCFG_CFGR1 register  (SYSCFG configuration register 1) ****************************************************************/
-#define SYSCFG_CFGR1_BOOSTEN_Pos                (8U)
-#define SYSCFG_CFGR1_BOOSTEN_Msk                (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)             /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOSTEN                    SYSCFG_CFGR1_BOOSTEN_Msk                        /*!< I/O analog switch voltage booster enable                  */
-#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos            (16U)
-#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)         /*!< 0x00010000 */
-#define SYSCFG_CFGR1_I2C_PB6_FMP                SYSCFG_CFGR1_I2C_PB6_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB6 */
-#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos            (17U)
-#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)         /*!< 0x00020000 */
-#define SYSCFG_CFGR1_I2C_PB7_FMP                SYSCFG_CFGR1_I2C_PB7_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB7 */
-#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos            (18U)
-#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)         /*!< 0x00040000 */
-#define SYSCFG_CFGR1_I2C_PB8_FMP                SYSCFG_CFGR1_I2C_PB8_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB8 */
-#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos            (19U)
-#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)         /*!< 0x00080000 */
-#define SYSCFG_CFGR1_I2C_PB9_FMP                SYSCFG_CFGR1_I2C_PB9_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB9 */
-#define SYSCFG_CFGR1_I2C1_FMP_Pos               (20U)
-#define SYSCFG_CFGR1_I2C1_FMP_Msk               (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)            /*!< 0x00100000 */
-#define SYSCFG_CFGR1_I2C1_FMP                   SYSCFG_CFGR1_I2C1_FMP_Msk                       /*!< I2C1 Fast-mode Plus (Fm+) driving capability activation   */
-#define SYSCFG_CFGR1_I2C2_FMP_Pos               (21U)
-#define SYSCFG_CFGR1_I2C2_FMP_Msk               (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)            /*!< 0x00200000 */
-#define SYSCFG_CFGR1_I2C2_FMP                   SYSCFG_CFGR1_I2C2_FMP_Msk                       /*!< I2C2 Fast-mode Plus (Fm+) driving capability activation   */
-#define SYSCFG_CFGR1_I2C3_FMP_Pos               (22U)
-#define SYSCFG_CFGR1_I2C3_FMP_Msk               (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)            /*!< 0x00400000 */
-#define SYSCFG_CFGR1_I2C3_FMP                   SYSCFG_CFGR1_I2C3_FMP_Msk                       /*!< I2C3 Fast-mode Plus (Fm+) driving capability activation   */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  (External interrupt configuration register 1) ********************************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                (0U)
-#define SYSCFG_EXTICR1_EXTI0_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)             /*!< 0x00000007 */
-#define SYSCFG_EXTICR1_EXTI0                    SYSCFG_EXTICR1_EXTI0_Msk                        /*!< External Interrupt Line 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                (4U)
-#define SYSCFG_EXTICR1_EXTI1_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)             /*!< 0x00000070 */
-#define SYSCFG_EXTICR1_EXTI1                    SYSCFG_EXTICR1_EXTI1_Msk                        /*!< External Interrupt Line 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                (8U)
-#define SYSCFG_EXTICR1_EXTI2_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)             /*!< 0x00000700 */
-#define SYSCFG_EXTICR1_EXTI2                    SYSCFG_EXTICR1_EXTI2_Msk                        /*!< External Interrupt Line 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                (12U)
-#define SYSCFG_EXTICR1_EXTI3_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)             /*!< 0x00007000 */
-#define SYSCFG_EXTICR1_EXTI3                    SYSCFG_EXTICR1_EXTI3_Msk                        /*!< External Interrupt Line 3 configuration */
-
-/**
-  * @brief  External Interrupt Line 0 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                 (0x00000000U)   /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                 (0x00000001U)   /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                 (0x00000002U)   /*!< PC[0] pin */
-
-/**
-  * @brief  External Interrupt Line 1 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI1_PA                 (0x00000000U)   /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                 (0x00000010U)   /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                 (0x00000020U)   /*!< PC[1] pin */
-
-/**
-  * @brief  External Interrupt Line 2 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                 (0x00000000U)   /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                 (0x00000100U)   /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                 (0x00000200U)   /*!< PC[2] pin */
-
-/**
-  * @brief  External Interrupt Line 3 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                 (0x00000000U)   /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                 (0x00001000U)   /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                 (0x00002000U)   /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  (External interrupt configuration register 2) ********************************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                (0U)
-#define SYSCFG_EXTICR2_EXTI4_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)             /*!< 0x00000007 */
-#define SYSCFG_EXTICR2_EXTI4                    SYSCFG_EXTICR2_EXTI4_Msk                        /*!< External Interrupt Line 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                (4U)
-#define SYSCFG_EXTICR2_EXTI5_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)             /*!< 0x00000070 */
-#define SYSCFG_EXTICR2_EXTI5                    SYSCFG_EXTICR2_EXTI5_Msk                        /*!< External Interrupt Line 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                (8U)
-#define SYSCFG_EXTICR2_EXTI6_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)             /*!< 0x00000700 */
-#define SYSCFG_EXTICR2_EXTI6                    SYSCFG_EXTICR2_EXTI6_Msk                        /*!< External Interrupt Line 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                (12U)
-#define SYSCFG_EXTICR2_EXTI7_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)             /*!< 0x00007000 */
-#define SYSCFG_EXTICR2_EXTI7                    SYSCFG_EXTICR2_EXTI7_Msk                        /*!< External Interrupt Line 7 configuration */
-
-/**
-  * @brief  External Interrupt Line 4 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                 (0x00000000U)   /*!< PA[4] pin  */
-#define SYSCFG_EXTICR2_EXTI4_PB                 (0x00000001U)   /*!< PB[4] pin  */
-#define SYSCFG_EXTICR2_EXTI4_PC                 (0x00000002U)   /*!< PC[4] pin  */
-
-/**
-  * @brief  External Interrupt Line 5 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                 (0x00000000U)   /*!< PA[5] pin  */
-#define SYSCFG_EXTICR2_EXTI5_PB                 (0x00000010U)   /*!< PB[5] pin  */
-#define SYSCFG_EXTICR2_EXTI5_PC                 (0x00000020U)   /*!< PC[5] pin  */
-
-/**
-  * @brief  External Interrupt Line 6 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                 (0x00000000U)   /*!< PA[6] pin  */
-#define SYSCFG_EXTICR2_EXTI6_PB                 (0x00000100U)   /*!< PB[6] pin  */
-#define SYSCFG_EXTICR2_EXTI6_PC                 (0x00000200U)   /*!< PC[6] pin  */
-
-/**
-  * @brief  External Interrupt Line 7 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                 (0x00000000U)   /*!< PA[7] pin  */
-#define SYSCFG_EXTICR2_EXTI7_PB                 (0x00001000U)   /*!< PB[7] pin  */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  (External interrupt configuration register 3) ********************************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                (0U)
-#define SYSCFG_EXTICR3_EXTI8_Msk                (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)             /*!< 0x00000007 */
-#define SYSCFG_EXTICR3_EXTI8                    SYSCFG_EXTICR3_EXTI8_Msk                        /*!< External Interrupt Line 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                (4U)
-#define SYSCFG_EXTICR3_EXTI9_Msk                (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)             /*!< 0x00000070 */
-#define SYSCFG_EXTICR3_EXTI9                    SYSCFG_EXTICR3_EXTI9_Msk                        /*!< External Interrupt Line 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos               (8U)
-#define SYSCFG_EXTICR3_EXTI10_Msk               (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)            /*!< 0x00000700 */
-#define SYSCFG_EXTICR3_EXTI10                   SYSCFG_EXTICR3_EXTI10_Msk                       /*!< External Interrupt Line 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos               (12U)
-#define SYSCFG_EXTICR3_EXTI11_Msk               (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)            /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                   SYSCFG_EXTICR3_EXTI11_Msk                       /*!< External Interrupt Line 11 configuration */
-
-/**
-  * @brief  External Interrupt Line 8 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                 (0x00000000U)   /*!< PA[8] pin  */
-#define SYSCFG_EXTICR3_EXTI8_PB                 (0x00000001U)   /*!< PB[8] pin  */
-
-/**
-  * @brief  External Interrupt Line 9 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                 (0x00000000U)   /*!< PA[9] pin  */
-#define SYSCFG_EXTICR3_EXTI9_PB                 (0x00000010U)   /*!< PB[9] pin  */
-
-/**
-  * @brief  External Interrupt Line 10 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                (0x00000000U)   /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                (0x00000100U)   /*!< PB[10] pin */
-
-/**
-  * @brief  External Interrupt Line 11 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                (0x00000000U)   /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                (0x00001000U)   /*!< PB[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  (External interrupt configuration register 4) *********************************/
-#define SYSCFG_EXTICR4_EXTI12_Pos               (0U)
-#define SYSCFG_EXTICR4_EXTI12_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)            /*!< 0x00000007 */
-#define SYSCFG_EXTICR4_EXTI12                   SYSCFG_EXTICR4_EXTI12_Msk                       /*!< External Interrupt Line 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos               (4U)
-#define SYSCFG_EXTICR4_EXTI13_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)            /*!< 0x00000070 */
-#define SYSCFG_EXTICR4_EXTI13                   SYSCFG_EXTICR4_EXTI13_Msk                       /*!< External Interrupt Line 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos               (8U)
-#define SYSCFG_EXTICR4_EXTI14_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)            /*!< 0x00000700 */
-#define SYSCFG_EXTICR4_EXTI14                   SYSCFG_EXTICR4_EXTI14_Msk                       /*!< External Interrupt Line 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos               (12U)
-#define SYSCFG_EXTICR4_EXTI15_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)            /*!< 0x00007000 */
-#define SYSCFG_EXTICR4_EXTI15                   SYSCFG_EXTICR4_EXTI15_Msk                       /*!< External Interrupt Line 15 configuration */
-
-/**
-  * @brief  External Interrupt Line 12 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                (0x00000000U)   /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                (0x00000001U)   /*!< PB[12] pin */
-
-/**
-  * @brief  External Interrupt Line 13 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                (0x00000000U)   /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                (0x00000010U)   /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                (0x00000020U)   /*!< PC[13] pin */
-
-/**
-  * @brief  External Interrupt Line 14 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                (0x00000000U)   /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                (0x00000100U)   /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                (0x00000200U)   /*!< PC[14] pin */
-
-/**
-  * @brief  External Interrupt Line 15 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                (0x00000000U)   /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                (0x00001000U)   /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                (0x00002000U)   /*!< PC[15] pin */
-
-/*****************  Bit definition for SYSCFG_SCSR register  (SYSCFG SRAM control and status register) **********************************************************/
-#define SYSCFG_SCSR_SRAM2ER_Pos                 (0U)
-#define SYSCFG_SCSR_SRAM2ER_Msk                 (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)               /*!< 0x00000001 */
-#define SYSCFG_SCSR_SRAM2ER                     SYSCFG_SCSR_SRAM2ER_Msk                          /*!< SRAM2 Erase                                      */
-#define SYSCFG_SCSR_SRAMBSY_Pos                 (1U)
-#define SYSCFG_SCSR_SRAMBSY_Msk                 (0x1UL << SYSCFG_SCSR_SRAMBSY_Pos)              /*!< 0x00000002 */
-#define SYSCFG_SCSR_SRAMBSY                     SYSCFG_SCSR_SRAMBSY_Msk                         /*!< SRAM2 and SRAM1 busy by erase operation                    */
-#define SYSCFG_SCSR_PKASRAMBSY_Pos              (8U)
-#define SYSCFG_SCSR_PKASRAMBSY_Msk              (0x1UL << SYSCFG_SCSR_PKASRAMBSY_Pos)           /*!< 0x00000100 */
-#define SYSCFG_SCSR_PKASRAMBSY                  SYSCFG_SCSR_PKASRAMBSY_Msk                      /*!< PKA SRAM busy by erase operation                           */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  (SYSCFG configuration register 2) *****************************************************************/
-#define SYSCFG_CFGR2_CLL_Pos                    (0U)
-#define SYSCFG_CFGR2_CLL_Msk                    (0x1UL << SYSCFG_CFGR2_CLL_Pos)                 /*!< 0x00000001 */
-#define SYSCFG_CFGR2_CLL                        SYSCFG_CFGR2_CLL_Msk                            /*!< Cortex M4 LOCKUP (hardfault) output enable                 */
-#define SYSCFG_CFGR2_SPL_Pos                    (1U)
-#define SYSCFG_CFGR2_SPL_Msk                    (0x1UL << SYSCFG_CFGR2_SPL_Pos)                 /*!< 0x00000002 */
-#define SYSCFG_CFGR2_SPL                        SYSCFG_CFGR2_SPL_Msk                            /*!< SRAM2 Parity Lock                                          */
-#define SYSCFG_CFGR2_PVDL_Pos                   (2U)
-#define SYSCFG_CFGR2_PVDL_Msk                   (0x1UL << SYSCFG_CFGR2_PVDL_Pos)                /*!< 0x00000004 */
-#define SYSCFG_CFGR2_PVDL                       SYSCFG_CFGR2_PVDL_Msk                           /*!< PVD Lock                                                   */
-#define SYSCFG_CFGR2_ECCL_Pos                   (3U)
-#define SYSCFG_CFGR2_ECCL_Msk                   (0x1UL << SYSCFG_CFGR2_ECCL_Pos)                /*!< 0x00000008 */
-#define SYSCFG_CFGR2_ECCL                       SYSCFG_CFGR2_ECCL_Msk                           /*!< ECC Lock                                                   */
-#define SYSCFG_CFGR2_SPF_Pos                    (8U)
-#define SYSCFG_CFGR2_SPF_Msk                    (0x1UL << SYSCFG_CFGR2_SPF_Pos)                 /*!< 0x00000100 */
-#define SYSCFG_CFGR2_SPF                        SYSCFG_CFGR2_SPF_Msk                            /*!< SRAM2 Parity Lock                                          */
-
-/*****************  Bit definition for SYSCFG_SWPR register  (SYSCFG SRAM2 write protection register) ***********************************************************/
-#define SYSCFG_SWPR_PAGE0_Pos                   (0U)
-#define SYSCFG_SWPR_PAGE0_Msk                   (0x1UL << SYSCFG_SWPR_PAGE0_Pos)                /*!< 0x00000001 */
-#define SYSCFG_SWPR_PAGE0                       SYSCFG_SWPR_PAGE0_Msk                           /*!< SRAM2 Write protection page 0 (0x20008000 – 0x200083FF)    */
-#define SYSCFG_SWPR_PAGE1_Pos                   (1U)
-#define SYSCFG_SWPR_PAGE1_Msk                   (0x1UL << SYSCFG_SWPR_PAGE1_Pos)                /*!< 0x00000002 */
-#define SYSCFG_SWPR_PAGE1                       SYSCFG_SWPR_PAGE1_Msk                           /*!< SRAM2 Write protection page 1 (0x20008400 – 0x200087FF)    */
-#define SYSCFG_SWPR_PAGE2_Pos                   (2U)
-#define SYSCFG_SWPR_PAGE2_Msk                   (0x1UL << SYSCFG_SWPR_PAGE2_Pos)                /*!< 0x00000004 */
-#define SYSCFG_SWPR_PAGE2                       SYSCFG_SWPR_PAGE2_Msk                           /*!< SRAM2 Write protection page 2 (0x20008800 – 0x20008BFF)    */
-#define SYSCFG_SWPR_PAGE3_Pos                   (3U)
-#define SYSCFG_SWPR_PAGE3_Msk                   (0x1UL << SYSCFG_SWPR_PAGE3_Pos)                /*!< 0x00000008 */
-#define SYSCFG_SWPR_PAGE3                       SYSCFG_SWPR_PAGE3_Msk                           /*!< SRAM2 Write protection page 3 (0x20008C00 – 0x20008FFF)    */
-#define SYSCFG_SWPR_PAGE4_Pos                   (4U)
-#define SYSCFG_SWPR_PAGE4_Msk                   (0x1UL << SYSCFG_SWPR_PAGE4_Pos)                /*!< 0x00000010 */
-#define SYSCFG_SWPR_PAGE4                       SYSCFG_SWPR_PAGE4_Msk                           /*!< SRAM2 Write protection page 4 (0x20009000 – 0x200093FF)    */
-#define SYSCFG_SWPR_PAGE5_Pos                   (5U)
-#define SYSCFG_SWPR_PAGE5_Msk                   (0x1UL << SYSCFG_SWPR_PAGE5_Pos)                /*!< 0x00000020 */
-#define SYSCFG_SWPR_PAGE5                       SYSCFG_SWPR_PAGE5_Msk                           /*!< SRAM2 Write protection page 5 (0x20009400 – 0x200097FF)    */
-#define SYSCFG_SWPR_PAGE6_Pos                   (6U)
-#define SYSCFG_SWPR_PAGE6_Msk                   (0x1UL << SYSCFG_SWPR_PAGE6_Pos)                /*!< 0x00000040 */
-#define SYSCFG_SWPR_PAGE6                       SYSCFG_SWPR_PAGE6_Msk                           /*!< SRAM2 Write protection page 6 (0x20009800 – 0x20009BFF)    */
-#define SYSCFG_SWPR_PAGE7_Pos                   (7U)
-#define SYSCFG_SWPR_PAGE7_Msk                   (0x1UL << SYSCFG_SWPR_PAGE7_Pos)                /*!< 0x00000080 */
-#define SYSCFG_SWPR_PAGE7                       SYSCFG_SWPR_PAGE7_Msk                           /*!< SRAM2 Write protection page 7 (0x20009C00 – 0x20009FFF)    */
-#define SYSCFG_SWPR_PAGE8_Pos                   (8U)
-#define SYSCFG_SWPR_PAGE8_Msk                   (0x1UL << SYSCFG_SWPR_PAGE8_Pos)                /*!< 0x00000100 */
-#define SYSCFG_SWPR_PAGE8                       SYSCFG_SWPR_PAGE8_Msk                           /*!< SRAM2 Write protection page 8 (0x2000A000 – 0x2000A3FF)    */
-#define SYSCFG_SWPR_PAGE9_Pos                   (9U)
-#define SYSCFG_SWPR_PAGE9_Msk                   (0x1UL << SYSCFG_SWPR_PAGE9_Pos)                /*!< 0x00000200 */
-#define SYSCFG_SWPR_PAGE9                       SYSCFG_SWPR_PAGE9_Msk                           /*!< SRAM2 Write protection page 9 (0x2000A400 – 0x2000A7FF)    */
-#define SYSCFG_SWPR_PAGE10_Pos                  (10U)
-#define SYSCFG_SWPR_PAGE10_Msk                  (0x1UL << SYSCFG_SWPR_PAGE10_Pos)               /*!< 0x00000400 */
-#define SYSCFG_SWPR_PAGE10                      SYSCFG_SWPR_PAGE10_Msk                          /*!< SRAM2 Write protection page 10 (0x2000A800 – 0x2000ABFF)   */
-#define SYSCFG_SWPR_PAGE11_Pos                  (11U)
-#define SYSCFG_SWPR_PAGE11_Msk                  (0x1UL << SYSCFG_SWPR_PAGE11_Pos)               /*!< 0x00000800 */
-#define SYSCFG_SWPR_PAGE11                      SYSCFG_SWPR_PAGE11_Msk                          /*!< SRAM2 Write protection page 11 (0x2000AC00 – 0x2000AFFF)   */
-#define SYSCFG_SWPR_PAGE12_Pos                  (12U)
-#define SYSCFG_SWPR_PAGE12_Msk                  (0x1UL << SYSCFG_SWPR_PAGE12_Pos)               /*!< 0x00001000 */
-#define SYSCFG_SWPR_PAGE12                      SYSCFG_SWPR_PAGE12_Msk                          /*!< SRAM2 Write protection page 12 (0x2000B000 – 0x2000B3FF)   */
-#define SYSCFG_SWPR_PAGE13_Pos                  (13U)
-#define SYSCFG_SWPR_PAGE13_Msk                  (0x1UL << SYSCFG_SWPR_PAGE13_Pos)               /*!< 0x00002000 */
-#define SYSCFG_SWPR_PAGE13                      SYSCFG_SWPR_PAGE13_Msk                          /*!< SRAM2 Write protection page 13 (0x2000B400 – 0x2000B7FF)   */
-#define SYSCFG_SWPR_PAGE14_Pos                  (14U)
-#define SYSCFG_SWPR_PAGE14_Msk                  (0x1UL << SYSCFG_SWPR_PAGE14_Pos)               /*!< 0x00004000 */
-#define SYSCFG_SWPR_PAGE14                      SYSCFG_SWPR_PAGE14_Msk                          /*!< SRAM2 Write protection page 14 (0x2000B800 – 0x2000BBFF)   */
-#define SYSCFG_SWPR_PAGE15_Pos                  (15U)
-#define SYSCFG_SWPR_PAGE15_Msk                  (0x1UL << SYSCFG_SWPR_PAGE15_Pos)               /*!< 0x00008000 */
-#define SYSCFG_SWPR_PAGE15                      SYSCFG_SWPR_PAGE15_Msk                          /*!< SRAM2 Write protection page 15 (0x2000BC00 – 0x2000BFFF)   */
-#define SYSCFG_SWPR_PAGE16_Pos                  (16U)
-#define SYSCFG_SWPR_PAGE16_Msk                  (0x1UL << SYSCFG_SWPR_PAGE16_Pos)               /*!< 0x00010000 */
-#define SYSCFG_SWPR_PAGE16                      SYSCFG_SWPR_PAGE16_Msk                          /*!< SRAM2 Write protection page 16 (0x2000C000 – 0x2000C3FF)   */
-#define SYSCFG_SWPR_PAGE17_Pos                  (17U)
-#define SYSCFG_SWPR_PAGE17_Msk                  (0x1UL << SYSCFG_SWPR_PAGE17_Pos)               /*!< 0x00020000 */
-#define SYSCFG_SWPR_PAGE17                      SYSCFG_SWPR_PAGE17_Msk                          /*!< SRAM2 Write protection page 17 (0x2000C400 – 0x2000C7FF)   */
-#define SYSCFG_SWPR_PAGE18_Pos                  (18U)
-#define SYSCFG_SWPR_PAGE18_Msk                  (0x1UL << SYSCFG_SWPR_PAGE18_Pos)               /*!< 0x00040000 */
-#define SYSCFG_SWPR_PAGE18                      SYSCFG_SWPR_PAGE18_Msk                          /*!< SRAM2 Write protection page 18 (0x2000C800 – 0x2000CBFF)   */
-#define SYSCFG_SWPR_PAGE19_Pos                  (19U)
-#define SYSCFG_SWPR_PAGE19_Msk                  (0x1UL << SYSCFG_SWPR_PAGE19_Pos)               /*!< 0x00080000 */
-#define SYSCFG_SWPR_PAGE19                      SYSCFG_SWPR_PAGE19_Msk                          /*!< SRAM2 Write protection page 19 (0x2000CC00 – 0x2000CFFF)   */
-#define SYSCFG_SWPR_PAGE20_Pos                  (20U)
-#define SYSCFG_SWPR_PAGE20_Msk                  (0x1UL << SYSCFG_SWPR_PAGE20_Pos)               /*!< 0x00100000 */
-#define SYSCFG_SWPR_PAGE20                      SYSCFG_SWPR_PAGE20_Msk                          /*!< SRAM2 Write protection page 20 (0x2000D000 – 0x2000D3FF)   */
-#define SYSCFG_SWPR_PAGE21_Pos                  (21U)
-#define SYSCFG_SWPR_PAGE21_Msk                  (0x1UL << SYSCFG_SWPR_PAGE21_Pos)               /*!< 0x00200000 */
-#define SYSCFG_SWPR_PAGE21                      SYSCFG_SWPR_PAGE21_Msk                          /*!< SRAM2 Write protection page 21 (0x2000D400 – 0x2000D7FF)   */
-#define SYSCFG_SWPR_PAGE22_Pos                  (22U)
-#define SYSCFG_SWPR_PAGE22_Msk                  (0x1UL << SYSCFG_SWPR_PAGE22_Pos)               /*!< 0x00400000 */
-#define SYSCFG_SWPR_PAGE22                      SYSCFG_SWPR_PAGE22_Msk                          /*!< SRAM2 Write protection page 22 (0x2000D800 – 0x2000DBFF)   */
-#define SYSCFG_SWPR_PAGE23_Pos                  (23U)
-#define SYSCFG_SWPR_PAGE23_Msk                  (0x1UL << SYSCFG_SWPR_PAGE23_Pos)               /*!< 0x00800000 */
-#define SYSCFG_SWPR_PAGE23                      SYSCFG_SWPR_PAGE23_Msk                          /*!< SRAM2 Write protection page 23 (0x2000DC00 – 0x2000DFFF)   */
-#define SYSCFG_SWPR_PAGE24_Pos                  (24U)
-#define SYSCFG_SWPR_PAGE24_Msk                  (0x1UL << SYSCFG_SWPR_PAGE24_Pos)               /*!< 0x01000000 */
-#define SYSCFG_SWPR_PAGE24                      SYSCFG_SWPR_PAGE24_Msk                          /*!< SRAM2 Write protection page 24 (0x2000E000 – 0x2000E3FF)   */
-#define SYSCFG_SWPR_PAGE25_Pos                  (25U)
-#define SYSCFG_SWPR_PAGE25_Msk                  (0x1UL << SYSCFG_SWPR_PAGE25_Pos)               /*!< 0x02000000 */
-#define SYSCFG_SWPR_PAGE25                      SYSCFG_SWPR_PAGE25_Msk                          /*!< SRAM2 Write protection page 25 (0x2000E400 – 0x2000E7FF)   */
-#define SYSCFG_SWPR_PAGE26_Pos                  (26U)
-#define SYSCFG_SWPR_PAGE26_Msk                  (0x1UL << SYSCFG_SWPR_PAGE26_Pos)               /*!< 0x04000000 */
-#define SYSCFG_SWPR_PAGE26                      SYSCFG_SWPR_PAGE26_Msk                          /*!< SRAM2 Write protection page 26 (0x2000E800 – 0x2000EBFF)   */
-#define SYSCFG_SWPR_PAGE27_Pos                  (27U)
-#define SYSCFG_SWPR_PAGE27_Msk                  (0x1UL << SYSCFG_SWPR_PAGE27_Pos)               /*!< 0x08000000 */
-#define SYSCFG_SWPR_PAGE27                      SYSCFG_SWPR_PAGE27_Msk                          /*!< SRAM2 Write protection page 27 (0x2000EC00 – 0x2000EFFF)   */
-#define SYSCFG_SWPR_PAGE28_Pos                  (28U)
-#define SYSCFG_SWPR_PAGE28_Msk                  (0x1UL << SYSCFG_SWPR_PAGE28_Pos)               /*!< 0x10000000 */
-#define SYSCFG_SWPR_PAGE28                      SYSCFG_SWPR_PAGE28_Msk                          /*!< SRAM2 Write protection page 28 (0x2000F000 – 0x2000F3FF)   */
-#define SYSCFG_SWPR_PAGE29_Pos                  (29U)
-#define SYSCFG_SWPR_PAGE29_Msk                  (0x1UL << SYSCFG_SWPR_PAGE29_Pos)               /*!< 0x20000000 */
-#define SYSCFG_SWPR_PAGE29                      SYSCFG_SWPR_PAGE29_Msk                          /*!< SRAM2 Write protection page 29 (0x2000F400 – 0x2000F7FF)   */
-#define SYSCFG_SWPR_PAGE30_Pos                  (30U)
-#define SYSCFG_SWPR_PAGE30_Msk                  (0x1UL << SYSCFG_SWPR_PAGE30_Pos)               /*!< 0x40000000 */
-#define SYSCFG_SWPR_PAGE30                      SYSCFG_SWPR_PAGE30_Msk                          /*!< SRAM2 Write protection page 30 (0x2000F800 – 0x2000FBFF)   */
-#define SYSCFG_SWPR_PAGE31_Pos                  (31U)
-#define SYSCFG_SWPR_PAGE31_Msk                  (0x1UL << SYSCFG_SWPR_PAGE31_Pos)               /*!< 0x80000000 */
-#define SYSCFG_SWPR_PAGE31                      SYSCFG_SWPR_PAGE31_Msk                          /*!< SRAM2 Write protection page 31 (0x2000FC00 – 0x2000FFFF)   */
-
-/*****************  Bit definition for SYSCFG_SKR register  (SYSCFG SRAM2 key register) *************************************************************************/
-#define SYSCFG_SKR_KEY_Pos                      (0U)
-#define SYSCFG_SKR_KEY_Msk                      (0xFFUL << SYSCFG_SKR_KEY_Pos)                  /*!< 0x000000FF */
-#define SYSCFG_SKR_KEY                          SYSCFG_SKR_KEY_Msk                              /*!< SRAM2 write protection key for software erase              */
-
-/*****************  Bit definition for SYSCFG_IMR1 register (Interrupt masks control and status register on CPU1 - part 1) *******************************************/
-#define SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM_Pos    (0U)
-#define SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM_Msk    (0x1UL << SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM_Pos) /*!< 0x00000001 */
-#define SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM        SYSCFG_IMR1_RTCSTAMPTAMPLSECSSIM_Msk            /*!< Enabling of interrupt from RTCSTAMPTAMPLSECSS to CPU1             */
-#define SYSCFG_IMR1_RTCSSRUIM_Pos               (2U)
-#define SYSCFG_IMR1_RTCSSRUIM_Msk               (0x1UL << SYSCFG_IMR1_RTCSSRUIM_Pos)            /*!< 0x00000004 */
-#define SYSCFG_IMR1_RTCSSRUIM                   SYSCFG_IMR1_RTCSSRUIM_Msk                       /*!< Enabling of interrupt from RTC SSRU to CPU1                       */
-#define SYSCFG_IMR1_EXTI5IM_Pos                 (21U)
-#define SYSCFG_IMR1_EXTI5IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI5IM_Pos)            /*!< 0x00200000 */
-#define SYSCFG_IMR1_EXTI5IM                     SYSCFG_IMR1_EXTI5IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1      */
-#define SYSCFG_IMR1_EXTI6IM_Pos                 (22U)
-#define SYSCFG_IMR1_EXTI6IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI6IM_Pos)            /*!< 0x00400000 */
-#define SYSCFG_IMR1_EXTI6IM                     SYSCFG_IMR1_EXTI6IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1      */
-#define SYSCFG_IMR1_EXTI7IM_Pos                 (23U)
-#define SYSCFG_IMR1_EXTI7IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI7IM_Pos)            /*!< 0x00800000 */
-#define SYSCFG_IMR1_EXTI7IM                     SYSCFG_IMR1_EXTI7IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 7 to CPU1      */
-#define SYSCFG_IMR1_EXTI8IM_Pos                 (24U)
-#define SYSCFG_IMR1_EXTI8IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI8IM_Pos)            /*!< 0x01000000 */
-#define SYSCFG_IMR1_EXTI8IM                     SYSCFG_IMR1_EXTI8IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 8 to CPU1      */
-#define SYSCFG_IMR1_EXTI9IM_Pos                 (25U)
-#define SYSCFG_IMR1_EXTI9IM_Msk                 (0x1UL << SYSCFG_IMR1_EXTI9IM_Pos)            /*!< 0x02000000 */
-#define SYSCFG_IMR1_EXTI9IM                     SYSCFG_IMR1_EXTI9IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 9 to CPU1      */
-#define SYSCFG_IMR1_EXTI10IM_Pos                (26U)
-#define SYSCFG_IMR1_EXTI10IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI10IM_Pos)           /*!< 0x04000000 */
-#define SYSCFG_IMR1_EXTI10IM                    SYSCFG_IMR1_EXTI10IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 10 to CPU1     */
-#define SYSCFG_IMR1_EXTI11IM_Pos                (27U)
-#define SYSCFG_IMR1_EXTI11IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI11IM_Pos)           /*!< 0x08000000 */
-#define SYSCFG_IMR1_EXTI11IM                    SYSCFG_IMR1_EXTI11IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 11 to CPU1     */
-#define SYSCFG_IMR1_EXTI12IM_Pos                (28U)
-#define SYSCFG_IMR1_EXTI12IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI12IM_Pos)           /*!< 0x10000000 */
-#define SYSCFG_IMR1_EXTI12IM                    SYSCFG_IMR1_EXTI12IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 12 to CPU1     */
-#define SYSCFG_IMR1_EXTI13IM_Pos                (29U)
-#define SYSCFG_IMR1_EXTI13IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI13IM_Pos)           /*!< 0x20000000 */
-#define SYSCFG_IMR1_EXTI13IM                    SYSCFG_IMR1_EXTI13IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 13 to CPU1     */
-#define SYSCFG_IMR1_EXTI14IM_Pos                (30U)
-#define SYSCFG_IMR1_EXTI14IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI14IM_Pos)           /*!< 0x40000000 */
-#define SYSCFG_IMR1_EXTI14IM                    SYSCFG_IMR1_EXTI14IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 14 to CPU1     */
-#define SYSCFG_IMR1_EXTI15IM_Pos                (31U)
-#define SYSCFG_IMR1_EXTI15IM_Msk                (0x1UL << SYSCFG_IMR1_EXTI15IM_Pos)           /*!< 0x80000000 */
-#define SYSCFG_IMR1_EXTI15IM                    SYSCFG_IMR1_EXTI15IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 15 to CPU1     */
-
-/*****************  Bit definition for SYSCFG_IMR2 register (Interrupt masks control and status register on CPU1 - part 2) *******************************************/
-#define SYSCFG_IMR2_PVM3IM_Pos                  (18U)
-#define SYSCFG_IMR2_PVM3IM_Msk                  (0x1UL << SYSCFG_IMR2_PVM3IM_Pos)             /*!< 0x00040000 */
-#define SYSCFG_IMR2_PVM3IM                      SYSCFG_IMR2_PVM3IM_Msk                        /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1     */
-#define SYSCFG_IMR2_PVDIM_Pos                   (20U)
-#define SYSCFG_IMR2_PVDIM_Msk                   (0x1UL << SYSCFG_IMR2_PVDIM_Pos)              /*!< 0x00100000 */
-#define SYSCFG_IMR2_PVDIM                       SYSCFG_IMR2_PVDIM_Msk                         /*!< Enabling of interrupt from Power Voltage Detector to CPU1         */
-
-/*****************  Bit definition for SYSCFG_C2IMR1 register (Interrupt masks control and status register on CPU2 - part 1) *******************************************/
-#define SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Pos  (0U)
-#define SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Msk  (0x1U << SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Pos)/*!< 0x00000001 */
-#define SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM      SYSCFG_C2IMR1_RTCSTAMPTAMPLSECSSIM_Msk          /* !< Enabling of interrupt from RTC TimeStamp, RTC Tampers                                                                                                      and LSE Clock Security System to CPU2                            */
-#define SYSCFG_C2IMR1_RTCALARMIM_Pos            (1U)
-#define SYSCFG_C2IMR1_RTCALARMIM_Msk            (0x1UL << SYSCFG_C2IMR1_RTCALARMIM_Pos)         /*!< 0x00000002 */
-#define SYSCFG_C2IMR1_RTCALARMIM                SYSCFG_C2IMR1_RTCALARMIM_Msk                    /*!< Enabling of interrupt from RTC Alarms to CPU2                    */
-#define SYSCFG_C2IMR1_RTCSSRUIM_Pos             (2U)
-#define SYSCFG_C2IMR1_RTCSSRUIM_Msk             (0x1UL << SYSCFG_C2IMR1_RTCSSRUIM_Pos)          /*!< 0x00000004 */
-#define SYSCFG_C2IMR1_RTCSSRUIM                 SYSCFG_C2IMR1_RTCSSRUIM_Msk                     /*!< Enabling of interrupt from RTC SSRU to CPU2                      */
-#define SYSCFG_C2IMR1_RTCWKUPIM_Pos             (3U)
-#define SYSCFG_C2IMR1_RTCWKUPIM_Msk             (0x1UL << SYSCFG_C2IMR1_RTCWKUPIM_Pos)          /*!< 0x00000008 */
-#define SYSCFG_C2IMR1_RTCWKUPIM                 SYSCFG_C2IMR1_RTCWKUPIM_Msk                     /*!< Enabling of interrupt from RTC Wakeup to CPU2                    */
-#define SYSCFG_C2IMR1_RCCIM_Pos                 (5U)
-#define SYSCFG_C2IMR1_RCCIM_Msk                 (0x1UL << SYSCFG_C2IMR1_RCCIM_Pos)              /*!< 0x00000020 */
-#define SYSCFG_C2IMR1_RCCIM                     SYSCFG_C2IMR1_RCCIM_Msk                         /*!< Enabling of interrupt from RCC to CPU2                           */
-#define SYSCFG_C2IMR1_FLASHIM_Pos               (6U)
-#define SYSCFG_C2IMR1_FLASHIM_Msk               (0x1UL << SYSCFG_C2IMR1_FLASHIM_Pos)            /*!< 0x00000040 */
-#define SYSCFG_C2IMR1_FLASHIM                   SYSCFG_C2IMR1_FLASHIM_Msk                       /*!< Enabling of interrupt from FLASH to CPU2                         */
-#define SYSCFG_C2IMR1_PKAIM_Pos                 (8U)
-#define SYSCFG_C2IMR1_PKAIM_Msk                 (0x1UL << SYSCFG_C2IMR1_PKAIM_Pos)              /*!< 0x00000040 */
-#define SYSCFG_C2IMR1_PKAIM                     SYSCFG_C2IMR1_PKAIM_Msk                         /*!< Enabling of interrupt from PKA to CPU2                           */
-#define SYSCFG_C2IMR1_AESIM_Pos                 (10U)
-#define SYSCFG_C2IMR1_AESIM_Msk                 (0x1UL << SYSCFG_C2IMR1_AESIM_Pos)              /*!< 0x00000800 */
-#define SYSCFG_C2IMR1_AESIM                     SYSCFG_C2IMR1_AESIM_Msk                         /*!< Enabling of interrupt from AES to CPU2                          */
-#define SYSCFG_C2IMR1_COMPIM_Pos                (11U)
-#define SYSCFG_C2IMR1_COMPIM_Msk                (0x1UL << SYSCFG_C2IMR1_COMPIM_Pos)             /*!< 0x00000800 */
-#define SYSCFG_C2IMR1_COMPIM                    SYSCFG_C2IMR1_COMPIM_Msk                        /*!< Enabling of interrupt from Comparator to CPU2                    */
-#define SYSCFG_C2IMR1_ADCIM_Pos                 (12U)
-#define SYSCFG_C2IMR1_ADCIM_Msk                 (0x1UL << SYSCFG_C2IMR1_ADCIM_Pos)              /*!< 0x00001000 */
-#define SYSCFG_C2IMR1_ADCIM                     SYSCFG_C2IMR1_ADCIM_Msk                         /*!< Enabling of interrupt from Analog Digital Converter to CPU2      */
-#define SYSCFG_C2IMR1_DACIM_Pos                 (13U)
-#define SYSCFG_C2IMR1_DACIM_Msk                 (0x1UL << SYSCFG_C2IMR1_DACIM_Pos)               /*!< 0x00002000 */
-#define SYSCFG_C2IMR1_DACIM                     SYSCFG_C2IMR1_DACIM_Msk                          /*!< Enabling of interrupt from Digital Analog Converter to CPU2     */
-#define SYSCFG_C2IMR1_EXTI0IM_Pos               (16U)
-#define SYSCFG_C2IMR1_EXTI0IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI0IM_Pos)            /*!< 0x00010000 */
-#define SYSCFG_C2IMR1_EXTI0IM                   SYSCFG_C2IMR1_EXTI0IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2     */
-#define SYSCFG_C2IMR1_EXTI1IM_Pos               (17U)
-#define SYSCFG_C2IMR1_EXTI1IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI1IM_Pos)            /*!< 0x00020000 */
-#define SYSCFG_C2IMR1_EXTI1IM                   SYSCFG_C2IMR1_EXTI1IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 1 to CPU2     */
-#define SYSCFG_C2IMR1_EXTI2IM_Pos               (18U)
-#define SYSCFG_C2IMR1_EXTI2IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI2IM_Pos)            /*!< 0x00040000 */
-#define SYSCFG_C2IMR1_EXTI2IM                   SYSCFG_C2IMR1_EXTI2IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 2 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI3IM_Pos               (19U)
-#define SYSCFG_C2IMR1_EXTI3IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI3IM_Pos)            /*!< 0x00080000 */
-#define SYSCFG_C2IMR1_EXTI3IM                   SYSCFG_C2IMR1_EXTI3IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 3 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI4IM_Pos               (20U)
-#define SYSCFG_C2IMR1_EXTI4IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI4IM_Pos)            /*!< 0x00100000 */
-#define SYSCFG_C2IMR1_EXTI4IM                   SYSCFG_C2IMR1_EXTI4IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 4 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI5IM_Pos               (21U)
-#define SYSCFG_C2IMR1_EXTI5IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI5IM_Pos)            /*!< 0x00200000 */
-#define SYSCFG_C2IMR1_EXTI5IM                   SYSCFG_C2IMR1_EXTI5IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 5 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI6IM_Pos               (22U)
-#define SYSCFG_C2IMR1_EXTI6IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI6IM_Pos)            /*!< 0x00400000 */
-#define SYSCFG_C2IMR1_EXTI6IM                   SYSCFG_C2IMR1_EXTI6IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 6 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI7IM_Pos               (23U)
-#define SYSCFG_C2IMR1_EXTI7IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI7IM_Pos)            /*!< 0x00800000 */
-#define SYSCFG_C2IMR1_EXTI7IM                   SYSCFG_C2IMR1_EXTI7IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 7 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI8IM_Pos               (24U)
-#define SYSCFG_C2IMR1_EXTI8IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI8IM_Pos)            /*!< 0x01000000 */
-#define SYSCFG_C2IMR1_EXTI8IM                   SYSCFG_C2IMR1_EXTI8IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 8 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI9IM_Pos               (25U)
-#define SYSCFG_C2IMR1_EXTI9IM_Msk               (0x1UL << SYSCFG_C2IMR1_EXTI9IM_Pos)            /*!< 0x02000000 */
-#define SYSCFG_C2IMR1_EXTI9IM                   SYSCFG_C2IMR1_EXTI9IM_Msk                       /*!< Enabling of interrupt from External Interrupt Line 9 to CPU2      */
-#define SYSCFG_C2IMR1_EXTI10IM_Pos              (26U)
-#define SYSCFG_C2IMR1_EXTI10IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI10IM_Pos)           /*!< 0x04000000 */
-#define SYSCFG_C2IMR1_EXTI10IM                  SYSCFG_C2IMR1_EXTI10IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 10 to CPU2     */
-#define SYSCFG_C2IMR1_EXTI11IM_Pos              (27U)
-#define SYSCFG_C2IMR1_EXTI11IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI11IM_Pos)           /*!< 0x08000000 */
-#define SYSCFG_C2IMR1_EXTI11IM                  SYSCFG_C2IMR1_EXTI11IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 11 to CPU2     */
-#define SYSCFG_C2IMR1_EXTI12IM_Pos              (28U)
-#define SYSCFG_C2IMR1_EXTI12IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI12IM_Pos)           /*!< 0x10000000 */
-#define SYSCFG_C2IMR1_EXTI12IM                  SYSCFG_C2IMR1_EXTI12IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 12 to CPU2     */
-#define SYSCFG_C2IMR1_EXTI13IM_Pos              (29U)
-#define SYSCFG_C2IMR1_EXTI13IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI13IM_Pos)           /*!< 0x20000000 */
-#define SYSCFG_C2IMR1_EXTI13IM                  SYSCFG_C2IMR1_EXTI13IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 13 to CPU2     */
-#define SYSCFG_C2IMR1_EXTI14IM_Pos              (30U)
-#define SYSCFG_C2IMR1_EXTI14IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI14IM_Pos)           /*!< 0x40000000 */
-#define SYSCFG_C2IMR1_EXTI14IM                  SYSCFG_C2IMR1_EXTI14IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 14 to CPU2     */
-#define SYSCFG_C2IMR1_EXTI15IM_Pos              (31U)
-#define SYSCFG_C2IMR1_EXTI15IM_Msk              (0x1UL << SYSCFG_C2IMR1_EXTI15IM_Pos)           /*!< 0x80000000 */
-#define SYSCFG_C2IMR1_EXTI15IM                  SYSCFG_C2IMR1_EXTI15IM_Msk                      /*!< Enabling of interrupt from External Interrupt Line 15 to CPU2     */
-
-/*****************  Bit definition for SYSCFG_C2IMR2 register (Interrupt masks control and status register on CPU2 - part 2) *******************************************/
-#define SYSCFG_C2IMR2_DMA1CH1IM_Pos             (0U)
-#define SYSCFG_C2IMR2_DMA1CH1IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH1IM_Pos)          /*!< 0x00000001 */
-#define SYSCFG_C2IMR2_DMA1CH1IM                 SYSCFG_C2IMR2_DMA1CH1IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 1 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA1CH2IM_Pos             (1U)
-#define SYSCFG_C2IMR2_DMA1CH2IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH2IM_Pos)          /*!< 0x00000002 */
-#define SYSCFG_C2IMR2_DMA1CH2IM                 SYSCFG_C2IMR2_DMA1CH2IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 2 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA1CH3IM_Pos             (2U)
-#define SYSCFG_C2IMR2_DMA1CH3IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH3IM_Pos)          /*!< 0x00000004 */
-#define SYSCFG_C2IMR2_DMA1CH3IM                 SYSCFG_C2IMR2_DMA1CH3IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 3 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA1CH4IM_Pos             (3U)
-#define SYSCFG_C2IMR2_DMA1CH4IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH4IM_Pos)          /*!< 0x00000008 */
-#define SYSCFG_C2IMR2_DMA1CH4IM                 SYSCFG_C2IMR2_DMA1CH4IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 4 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA1CH5IM_Pos             (4U)
-#define SYSCFG_C2IMR2_DMA1CH5IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH5IM_Pos)          /*!< 0x00000010 */
-#define SYSCFG_C2IMR2_DMA1CH5IM                 SYSCFG_C2IMR2_DMA1CH5IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 5 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA1CH6IM_Pos             (5U)
-#define SYSCFG_C2IMR2_DMA1CH6IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH6IM_Pos)          /*!< 0x00000020 */
-#define SYSCFG_C2IMR2_DMA1CH6IM                 SYSCFG_C2IMR2_DMA1CH6IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 6 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA1CH7IM_Pos             (6U)
-#define SYSCFG_C2IMR2_DMA1CH7IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA1CH7IM_Pos)          /*!< 0x00000040 */
-#define SYSCFG_C2IMR2_DMA1CH7IM                 SYSCFG_C2IMR2_DMA1CH7IM_Msk                     /*!< Enabling of interrupt from DMA1 Channel 7 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA2CH1IM_Pos             (8U)
-#define SYSCFG_C2IMR2_DMA2CH1IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA2CH1IM_Pos)          /*!< 0x00000100 */
-#define SYSCFG_C2IMR2_DMA2CH1IM                 SYSCFG_C2IMR2_DMA2CH1IM_Msk                     /*!< Enabling of interrupt from DMA2 Channel 1 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA2CH2IM_Pos             (9U)
-#define SYSCFG_C2IMR2_DMA2CH2IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA2CH2IM_Pos)          /*!< 0x00000200 */
-#define SYSCFG_C2IMR2_DMA2CH2IM                 SYSCFG_C2IMR2_DMA2CH2IM_Msk                     /*!< Enabling of interrupt from DMA2 Channel 2 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA2CH3IM_Pos             (10U)
-#define SYSCFG_C2IMR2_DMA2CH3IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA2CH3IM_Pos)          /*!< 0x00000400 */
-#define SYSCFG_C2IMR2_DMA2CH3IM                 SYSCFG_C2IMR2_DMA2CH3IM_Msk                     /*!< Enabling of interrupt from DMA2 Channel 3 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA2CH4IM_Pos             (11U)
-#define SYSCFG_C2IMR2_DMA2CH4IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA2CH4IM_Pos)          /*!< 0x00000800 */
-#define SYSCFG_C2IMR2_DMA2CH4IM                 SYSCFG_C2IMR2_DMA2CH4IM_Msk                     /*!< Enabling of interrupt from DMA2 Channel 4 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA2CH5IM_Pos             (12U)
-#define SYSCFG_C2IMR2_DMA2CH5IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA2CH5IM_Pos)          /*!< 0x00001000 */
-#define SYSCFG_C2IMR2_DMA2CH5IM                 SYSCFG_C2IMR2_DMA2CH5IM_Msk                     /*!< Enabling of interrupt from DMA2 Channel 5 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA2CH6IM_Pos             (13U)
-#define SYSCFG_C2IMR2_DMA2CH6IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA2CH6IM_Pos)          /*!< 0x00002000 */
-#define SYSCFG_C2IMR2_DMA2CH6IM                 SYSCFG_C2IMR2_DMA2CH6IM_Msk                     /*!< Enabling of interrupt from DMA2 Channel 6 to CPU2                 */
-#define SYSCFG_C2IMR2_DMA2CH7IM_Pos             (14U)
-#define SYSCFG_C2IMR2_DMA2CH7IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMA2CH7IM_Pos)          /*!< 0x00004000 */
-#define SYSCFG_C2IMR2_DMA2CH7IM                 SYSCFG_C2IMR2_DMA2CH7IM_Msk                     /*!< Enabling of interrupt from DMA2 Channel 7 to CPU2                 */
-#define SYSCFG_C2IMR2_DMAMUX1IM_Pos             (15U)
-#define SYSCFG_C2IMR2_DMAMUX1IM_Msk             (0x1UL << SYSCFG_C2IMR2_DMAMUX1IM_Pos)          /*!< 0x00008000 */
-#define SYSCFG_C2IMR2_DMAMUX1IM                 SYSCFG_C2IMR2_DMAMUX1IM_Msk                     /*!< Enabling of interrupt from DMAMUX1 to CPU2                        */
-#define SYSCFG_C2IMR2_PVM3IM_Pos                (18U)
-#define SYSCFG_C2IMR2_PVM3IM_Msk                (0x1UL << SYSCFG_C2IMR2_PVM3IM_Pos)             /*!< 0x00040000 */
-#define SYSCFG_C2IMR2_PVM3IM                    SYSCFG_C2IMR2_PVM3IM_Msk                        /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2     */
-#define SYSCFG_C2IMR2_PVDIM_Pos                 (20U)
-#define SYSCFG_C2IMR2_PVDIM_Msk                 (0x1UL << SYSCFG_C2IMR2_PVDIM_Pos)              /*!< 0x00100000 */
-#define SYSCFG_C2IMR2_PVDIM                     SYSCFG_C2IMR2_PVDIM_Msk                         /*!< Enabling of interrupt from Power Voltage Detector to CPU2         */
-
-/**************************************  Bit definition for SYSCFG_RFDCR register (SYSCFG radio debug control register) ************************************************/
-#define SYSCFG_RFDCR_RFTBSEL_Pos                (0U)
-#define SYSCFG_RFDCR_RFTBSEL_Msk                (0x1UL << SYSCFG_RFDCR_RFTBSEL_Pos)             /*!< 0x00000001 */
-#define SYSCFG_RFDCR_RFTBSEL                    SYSCFG_RFDCR_RFTBSEL_Msk                        /*!< Radio debug test bus selection                                    */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface (I2C)              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK_Pos          (8U)
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
-#define I2C_OAR2_OA2NOMASK           (0x00000000UL)                            /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*         Inter-Processor Communication Controller (IPCC)                    */
-/*                                                                            */
-/******************************************************************************/
-
-/**********************  Bit definition for IPCC_C1CR register  ***************/
-#define IPCC_C1CR_RXOIE_Pos      (0U)
-#define IPCC_C1CR_RXOIE_Msk      (0x1UL << IPCC_C1CR_RXOIE_Pos)                /*!< 0x00000001 */
-#define IPCC_C1CR_RXOIE          IPCC_C1CR_RXOIE_Msk                           /*!< Processor M4 Receive channel occupied interrupt enable */
-#define IPCC_C1CR_TXFIE_Pos      (16U)
-#define IPCC_C1CR_TXFIE_Msk      (0x1UL << IPCC_C1CR_TXFIE_Pos)                /*!< 0x00010000 */
-#define IPCC_C1CR_TXFIE          IPCC_C1CR_TXFIE_Msk                           /*!< Processor M4 Transmit channel free interrupt enable */
-
-/**********************  Bit definition for IPCC_C1MR register  **************/
-#define IPCC_C1MR_CH1OM_Pos      (0U)
-#define IPCC_C1MR_CH1OM_Msk      (0x1UL << IPCC_C1MR_CH1OM_Pos)                /*!< 0x00000001 */
-#define IPCC_C1MR_CH1OM          IPCC_C1MR_CH1OM_Msk                           /*!< M4 Channel1 occupied interrupt mask */
-#define IPCC_C1MR_CH2OM_Pos      (1U)
-#define IPCC_C1MR_CH2OM_Msk      (0x1UL << IPCC_C1MR_CH2OM_Pos)                /*!< 0x00000002 */
-#define IPCC_C1MR_CH2OM          IPCC_C1MR_CH2OM_Msk                           /*!< M4 Channel2 occupied interrupt mask */
-#define IPCC_C1MR_CH3OM_Pos      (2U)
-#define IPCC_C1MR_CH3OM_Msk      (0x1UL << IPCC_C1MR_CH3OM_Pos)                /*!< 0x00000004 */
-#define IPCC_C1MR_CH3OM          IPCC_C1MR_CH3OM_Msk                           /*!< M4 Channel3 occupied interrupt mask */
-#define IPCC_C1MR_CH4OM_Pos      (3U)
-#define IPCC_C1MR_CH4OM_Msk      (0x1UL << IPCC_C1MR_CH4OM_Pos)                /*!< 0x00000008 */
-#define IPCC_C1MR_CH4OM          IPCC_C1MR_CH4OM_Msk                           /*!< M4 Channel4 occupied interrupt mask */
-#define IPCC_C1MR_CH5OM_Pos      (4U)
-#define IPCC_C1MR_CH5OM_Msk      (0x1UL << IPCC_C1MR_CH5OM_Pos)                /*!< 0x00000010 */
-#define IPCC_C1MR_CH5OM          IPCC_C1MR_CH5OM_Msk                           /*!< M4 Channel5 occupied interrupt mask */
-#define IPCC_C1MR_CH6OM_Pos      (5U)
-#define IPCC_C1MR_CH6OM_Msk      (0x1UL << IPCC_C1MR_CH6OM_Pos)                /*!< 0x00000020 */
-#define IPCC_C1MR_CH6OM          IPCC_C1MR_CH6OM_Msk                           /*!< M4 Channel6 occupied interrupt mask */
-
-#define IPCC_C1MR_CH1FM_Pos      (16U)
-#define IPCC_C1MR_CH1FM_Msk      (0x1UL << IPCC_C1MR_CH1FM_Pos)                /*!< 0x00010000 */
-#define IPCC_C1MR_CH1FM          IPCC_C1MR_CH1FM_Msk                           /*!< M4 Transmit Channel1 free interrupt mask */
-#define IPCC_C1MR_CH2FM_Pos      (17U)
-#define IPCC_C1MR_CH2FM_Msk      (0x1UL << IPCC_C1MR_CH2FM_Pos)                /*!< 0x00020000 */
-#define IPCC_C1MR_CH2FM          IPCC_C1MR_CH2FM_Msk                           /*!< M4 Transmit Channel2 free interrupt mask */
-#define IPCC_C1MR_CH3FM_Pos      (18U)
-#define IPCC_C1MR_CH3FM_Msk      (0x1UL << IPCC_C1MR_CH3FM_Pos)                /*!< 0x00040000 */
-#define IPCC_C1MR_CH3FM          IPCC_C1MR_CH3FM_Msk                           /*!< M4 Transmit Channel3 free interrupt mask */
-#define IPCC_C1MR_CH4FM_Pos      (19U)
-#define IPCC_C1MR_CH4FM_Msk      (0x1UL << IPCC_C1MR_CH4FM_Pos)                /*!< 0x00080000 */
-#define IPCC_C1MR_CH4FM          IPCC_C1MR_CH4FM_Msk                           /*!< M4 Transmit Channel4 free interrupt mask */
-#define IPCC_C1MR_CH5FM_Pos      (20U)
-#define IPCC_C1MR_CH5FM_Msk      (0x1UL << IPCC_C1MR_CH5FM_Pos)                /*!< 0x00100000 */
-#define IPCC_C1MR_CH5FM          IPCC_C1MR_CH5FM_Msk                           /*!< M4 Transmit Channel5 free interrupt mask */
-#define IPCC_C1MR_CH6FM_Pos      (21U)
-#define IPCC_C1MR_CH6FM_Msk      (0x1UL << IPCC_C1MR_CH6FM_Pos)                /*!< 0x00200000 */
-#define IPCC_C1MR_CH6FM          IPCC_C1MR_CH6FM_Msk                           /*!< M4 Transmit Channel6 free interrupt mask */
-
-/**********************  Bit definition for IPCC_C1SCR register  ***************/
-#define IPCC_C1SCR_CH1C_Pos      (0U)
-#define IPCC_C1SCR_CH1C_Msk      (0x1UL << IPCC_C1SCR_CH1C_Pos)                /*!< 0x00000001 */
-#define IPCC_C1SCR_CH1C          IPCC_C1SCR_CH1C_Msk                           /*!< M4 receive Channel1 status clear */
-#define IPCC_C1SCR_CH2C_Pos      (1U)
-#define IPCC_C1SCR_CH2C_Msk      (0x1UL << IPCC_C1SCR_CH2C_Pos)                /*!< 0x00000002 */
-#define IPCC_C1SCR_CH2C          IPCC_C1SCR_CH2C_Msk                           /*!< M4 receive Channel2 status clear */
-#define IPCC_C1SCR_CH3C_Pos      (2U)
-#define IPCC_C1SCR_CH3C_Msk      (0x1UL << IPCC_C1SCR_CH3C_Pos)                /*!< 0x00000004 */
-#define IPCC_C1SCR_CH3C          IPCC_C1SCR_CH3C_Msk                           /*!< M4 receive Channel3 status clear */
-#define IPCC_C1SCR_CH4C_Pos      (3U)
-#define IPCC_C1SCR_CH4C_Msk      (0x1UL << IPCC_C1SCR_CH4C_Pos)                /*!< 0x00000008 */
-#define IPCC_C1SCR_CH4C          IPCC_C1SCR_CH4C_Msk                           /*!< M4 receive Channel4 status clear */
-#define IPCC_C1SCR_CH5C_Pos      (4U)
-#define IPCC_C1SCR_CH5C_Msk      (0x1UL << IPCC_C1SCR_CH5C_Pos)                /*!< 0x00000010 */
-#define IPCC_C1SCR_CH5C          IPCC_C1SCR_CH5C_Msk                           /*!< M4 receive Channel5 status clear */
-#define IPCC_C1SCR_CH6C_Pos      (5U)
-#define IPCC_C1SCR_CH6C_Msk      (0x1UL << IPCC_C1SCR_CH6C_Pos)                /*!< 0x00000020 */
-#define IPCC_C1SCR_CH6C          IPCC_C1SCR_CH6C_Msk                           /*!< M4 receive Channel6 status clear */
-
-#define IPCC_C1SCR_CH1S_Pos      (16U)
-#define IPCC_C1SCR_CH1S_Msk      (0x1UL << IPCC_C1SCR_CH1S_Pos)                /*!< 0x00010000 */
-#define IPCC_C1SCR_CH1S          IPCC_C1SCR_CH1S_Msk                           /*!< M4 transmit Channel1 status set */
-#define IPCC_C1SCR_CH2S_Pos      (17U)
-#define IPCC_C1SCR_CH2S_Msk      (0x1UL << IPCC_C1SCR_CH2S_Pos)                /*!< 0x00020000 */
-#define IPCC_C1SCR_CH2S          IPCC_C1SCR_CH2S_Msk                           /*!< M4 transmit Channel2 status set  */
-#define IPCC_C1SCR_CH3S_Pos      (18U)
-#define IPCC_C1SCR_CH3S_Msk      (0x1UL << IPCC_C1SCR_CH3S_Pos)                /*!< 0x00040000 */
-#define IPCC_C1SCR_CH3S          IPCC_C1SCR_CH3S_Msk                           /*!< M4 transmit Channel3 status set  */
-#define IPCC_C1SCR_CH4S_Pos      (19U)
-#define IPCC_C1SCR_CH4S_Msk      (0x1UL << IPCC_C1SCR_CH4S_Pos)                /*!< 0x00080000 */
-#define IPCC_C1SCR_CH4S          IPCC_C1SCR_CH4S_Msk                           /*!< M4 transmit Channel4 status set  */
-#define IPCC_C1SCR_CH5S_Pos      (20U)
-#define IPCC_C1SCR_CH5S_Msk      (0x1UL << IPCC_C1SCR_CH5S_Pos)                /*!< 0x00100000 */
-#define IPCC_C1SCR_CH5S          IPCC_C1SCR_CH5S_Msk                           /*!< M4 transmit Channel5 status set  */
-#define IPCC_C1SCR_CH6S_Pos      (21U)
-#define IPCC_C1SCR_CH6S_Msk      (0x1UL << IPCC_C1SCR_CH6S_Pos)                /*!< 0x00200000 */
-#define IPCC_C1SCR_CH6S          IPCC_C1SCR_CH6S_Msk                           /*!< M4 transmit Channel6 status set  */
-
-/**********************  Bit definition for IPCC_C1TOC2SR register  ***************/
-#define IPCC_C1TOC2SR_CH1F_Pos    (0U)
-#define IPCC_C1TOC2SR_CH1F_Msk    (0x1UL << IPCC_C1TOC2SR_CH1F_Pos)            /*!< 0x00000001 */
-#define IPCC_C1TOC2SR_CH1F        IPCC_C1TOC2SR_CH1F_Msk                       /*!< M4 transmit to M4 receive Channel1 status flag before masking */
-#define IPCC_C1TOC2SR_CH2F_Pos    (1U)
-#define IPCC_C1TOC2SR_CH2F_Msk    (0x1UL << IPCC_C1TOC2SR_CH2F_Pos)            /*!< 0x00000002 */
-#define IPCC_C1TOC2SR_CH2F        IPCC_C1TOC2SR_CH2F_Msk                       /*!< M4 transmit to M4 receive Channel2 status flag before masking */
-#define IPCC_C1TOC2SR_CH3F_Pos    (2U)
-#define IPCC_C1TOC2SR_CH3F_Msk    (0x1UL << IPCC_C1TOC2SR_CH3F_Pos)            /*!< 0x00000004 */
-#define IPCC_C1TOC2SR_CH3F        IPCC_C1TOC2SR_CH3F_Msk                       /*!< M4 transmit to M4 receive Channel3 status flag before masking */
-#define IPCC_C1TOC2SR_CH4F_Pos    (3U)
-#define IPCC_C1TOC2SR_CH4F_Msk    (0x1UL << IPCC_C1TOC2SR_CH4F_Pos)            /*!< 0x00000008 */
-#define IPCC_C1TOC2SR_CH4F        IPCC_C1TOC2SR_CH4F_Msk                       /*!< M4 transmit to M4 receive Channel4 status flag before masking */
-#define IPCC_C1TOC2SR_CH5F_Pos    (4U)
-#define IPCC_C1TOC2SR_CH5F_Msk    (0x1UL << IPCC_C1TOC2SR_CH5F_Pos)            /*!< 0x00000010 */
-#define IPCC_C1TOC2SR_CH5F        IPCC_C1TOC2SR_CH5F_Msk                       /*!< M4 transmit to M4 receive Channel5 status flag before masking */
-#define IPCC_C1TOC2SR_CH6F_Pos    (5U)
-#define IPCC_C1TOC2SR_CH6F_Msk    (0x1UL << IPCC_C1TOC2SR_CH6F_Pos)            /*!< 0x00000020 */
-#define IPCC_C1TOC2SR_CH6F        IPCC_C1TOC2SR_CH6F_Msk                       /*!< M4 transmit to M4 receive Channel6 status flag before masking */
-
-/**********************  Bit definition for IPCC_C2CR register  ***************/
-#define IPCC_C2CR_RXOIE_Pos      (0U)
-#define IPCC_C2CR_RXOIE_Msk      (0x1UL << IPCC_C2CR_RXOIE_Pos)                /*!< 0x00000001 */
-#define IPCC_C2CR_RXOIE          IPCC_C2CR_RXOIE_Msk                           /*!< Processor M0+ Receive channel occupied interrupt enable */
-#define IPCC_C2CR_TXFIE_Pos      (16U)
-#define IPCC_C2CR_TXFIE_Msk      (0x1UL << IPCC_C2CR_TXFIE_Pos)                /*!< 0x00010000 */
-#define IPCC_C2CR_TXFIE          IPCC_C2CR_TXFIE_Msk                           /*!< Processor M0+ Transmit channel free interrupt enable */
-
-/**********************  Bit definition for IPCC_C2MR register  ***************/
-#define IPCC_C2MR_CH1OM_Pos      (0U)
-#define IPCC_C2MR_CH1OM_Msk      (0x1UL << IPCC_C2MR_CH1OM_Pos)                /*!< 0x00000001 */
-#define IPCC_C2MR_CH1OM          IPCC_C2MR_CH1OM_Msk                           /*!< M0+ Channel1 occupied interrupt mask */
-#define IPCC_C2MR_CH2OM_Pos      (1U)
-#define IPCC_C2MR_CH2OM_Msk      (0x1UL << IPCC_C2MR_CH2OM_Pos)                /*!< 0x00000002 */
-#define IPCC_C2MR_CH2OM          IPCC_C2MR_CH2OM_Msk                           /*!< M0+ Channel2 occupied interrupt mask */
-#define IPCC_C2MR_CH3OM_Pos      (2U)
-#define IPCC_C2MR_CH3OM_Msk      (0x1UL << IPCC_C2MR_CH3OM_Pos)                /*!< 0x00000004 */
-#define IPCC_C2MR_CH3OM          IPCC_C2MR_CH3OM_Msk                           /*!< M0+ Channel3 occupied interrupt mask */
-#define IPCC_C2MR_CH4OM_Pos      (3U)
-#define IPCC_C2MR_CH4OM_Msk      (0x1UL << IPCC_C2MR_CH4OM_Pos)                /*!< 0x00000008 */
-#define IPCC_C2MR_CH4OM          IPCC_C2MR_CH4OM_Msk                           /*!< M0+ Channel4 occupied interrupt mask */
-#define IPCC_C2MR_CH5OM_Pos      (4U)
-#define IPCC_C2MR_CH5OM_Msk      (0x1UL << IPCC_C2MR_CH5OM_Pos)                /*!< 0x00000010 */
-#define IPCC_C2MR_CH5OM          IPCC_C2MR_CH5OM_Msk                           /*!< M0+ Channel5 occupied interrupt mask */
-#define IPCC_C2MR_CH6OM_Pos      (5U)
-#define IPCC_C2MR_CH6OM_Msk      (0x1UL << IPCC_C2MR_CH6OM_Pos)                /*!< 0x00000020 */
-#define IPCC_C2MR_CH6OM          IPCC_C2MR_CH6OM_Msk                           /*!< M0+ Channel6 occupied interrupt mask */
-
-#define IPCC_C2MR_CH1FM_Pos      (16U)
-#define IPCC_C2MR_CH1FM_Msk      (0x1UL << IPCC_C2MR_CH1FM_Pos)                /*!< 0x00010000 */
-#define IPCC_C2MR_CH1FM          IPCC_C2MR_CH1FM_Msk                           /*!< M0+ Transmit Channel1 free interrupt mask */
-#define IPCC_C2MR_CH2FM_Pos      (17U)
-#define IPCC_C2MR_CH2FM_Msk      (0x1UL << IPCC_C2MR_CH2FM_Pos)                /*!< 0x00020000 */
-#define IPCC_C2MR_CH2FM          IPCC_C2MR_CH2FM_Msk                           /*!< M0+ Transmit Channel2 free interrupt mask */
-#define IPCC_C2MR_CH3FM_Pos      (18U)
-#define IPCC_C2MR_CH3FM_Msk      (0x1UL << IPCC_C2MR_CH3FM_Pos)                /*!< 0x00040000 */
-#define IPCC_C2MR_CH3FM          IPCC_C2MR_CH3FM_Msk                           /*!< M0+ Transmit Channel3 free interrupt mask */
-#define IPCC_C2MR_CH4FM_Pos      (19U)
-#define IPCC_C2MR_CH4FM_Msk      (0x1UL << IPCC_C2MR_CH4FM_Pos)                /*!< 0x00080000 */
-#define IPCC_C2MR_CH4FM          IPCC_C2MR_CH4FM_Msk                           /*!< M0+ Transmit Channel4 free interrupt mask */
-#define IPCC_C2MR_CH5FM_Pos      (20U)
-#define IPCC_C2MR_CH5FM_Msk      (0x1UL << IPCC_C2MR_CH5FM_Pos)                /*!< 0x00100000 */
-#define IPCC_C2MR_CH5FM          IPCC_C2MR_CH5FM_Msk                           /*!< M0+ Transmit Channel5 free interrupt mask */
-#define IPCC_C2MR_CH6FM_Pos      (21U)
-#define IPCC_C2MR_CH6FM_Msk      (0x1UL << IPCC_C2MR_CH6FM_Pos)                /*!< 0x00200000 */
-#define IPCC_C2MR_CH6FM          IPCC_C2MR_CH6FM_Msk                           /*!< M0+ Transmit Channel6 free interrupt mask */
-
-/**********************  Bit definition for IPCC_C2SCR register  ***************/
-#define IPCC_C2SCR_CH1C_Pos      (0U)
-#define IPCC_C2SCR_CH1C_Msk      (0x1UL << IPCC_C2SCR_CH1C_Pos)                /*!< 0x00000001 */
-#define IPCC_C2SCR_CH1C          IPCC_C2SCR_CH1C_Msk                           /*!< M0+ receive Channel1 status clear */
-#define IPCC_C2SCR_CH2C_Pos      (1U)
-#define IPCC_C2SCR_CH2C_Msk      (0x1UL << IPCC_C2SCR_CH2C_Pos)                /*!< 0x00000002 */
-#define IPCC_C2SCR_CH2C          IPCC_C2SCR_CH2C_Msk                           /*!< M0+ receive Channel2 status clear */
-#define IPCC_C2SCR_CH3C_Pos      (2U)
-#define IPCC_C2SCR_CH3C_Msk      (0x1UL << IPCC_C2SCR_CH3C_Pos)                /*!< 0x00000004 */
-#define IPCC_C2SCR_CH3C          IPCC_C2SCR_CH3C_Msk                           /*!< M0+ receive Channel3 status clear */
-#define IPCC_C2SCR_CH4C_Pos      (3U)
-#define IPCC_C2SCR_CH4C_Msk      (0x1UL << IPCC_C2SCR_CH4C_Pos)                /*!< 0x00000008 */
-#define IPCC_C2SCR_CH4C          IPCC_C2SCR_CH4C_Msk                           /*!< M0+ receive Channel4 status clear */
-#define IPCC_C2SCR_CH5C_Pos      (4U)
-#define IPCC_C2SCR_CH5C_Msk      (0x1UL << IPCC_C2SCR_CH5C_Pos)                /*!< 0x00000010 */
-#define IPCC_C2SCR_CH5C          IPCC_C2SCR_CH5C_Msk                           /*!< M0+ receive Channel5 status clear */
-#define IPCC_C2SCR_CH6C_Pos      (5U)
-#define IPCC_C2SCR_CH6C_Msk      (0x1UL << IPCC_C2SCR_CH6C_Pos)                /*!< 0x00000020 */
-#define IPCC_C2SCR_CH6C          IPCC_C2SCR_CH6C_Msk                           /*!< M0+ receive Channel6 status clear */
-
-#define IPCC_C2SCR_CH1S_Pos      (16U)
-#define IPCC_C2SCR_CH1S_Msk      (0x1UL << IPCC_C2SCR_CH1S_Pos)                /*!< 0x00010000 */
-#define IPCC_C2SCR_CH1S          IPCC_C2SCR_CH1S_Msk                           /*!< M0+ transmit Channel1 status set  */
-#define IPCC_C2SCR_CH2S_Pos      (17U)
-#define IPCC_C2SCR_CH2S_Msk      (0x1UL << IPCC_C2SCR_CH2S_Pos)                /*!< 0x00020000 */
-#define IPCC_C2SCR_CH2S          IPCC_C2SCR_CH2S_Msk                           /*!< M0+ transmit Channel2 status set  */
-#define IPCC_C2SCR_CH3S_Pos      (18U)
-#define IPCC_C2SCR_CH3S_Msk      (0x1UL << IPCC_C2SCR_CH3S_Pos)                /*!< 0x00040000 */
-#define IPCC_C2SCR_CH3S          IPCC_C2SCR_CH3S_Msk                           /*!< M0+ transmit Channel3 status set  */
-#define IPCC_C2SCR_CH4S_Pos      (19U)
-#define IPCC_C2SCR_CH4S_Msk      (0x1UL << IPCC_C2SCR_CH4S_Pos)                /*!< 0x00080000 */
-#define IPCC_C2SCR_CH4S          IPCC_C2SCR_CH4S_Msk                           /*!< M0+ transmit Channel4 status set  */
-#define IPCC_C2SCR_CH5S_Pos      (20U)
-#define IPCC_C2SCR_CH5S_Msk      (0x1UL << IPCC_C2SCR_CH5S_Pos)                /*!< 0x00100000 */
-#define IPCC_C2SCR_CH5S          IPCC_C2SCR_CH5S_Msk                           /*!< M0+ transmit Channel5 status set  */
-#define IPCC_C2SCR_CH6S_Pos      (21U)
-#define IPCC_C2SCR_CH6S_Msk      (0x1UL << IPCC_C2SCR_CH6S_Pos)                /*!< 0x00200000 */
-#define IPCC_C2SCR_CH6S          IPCC_C2SCR_CH6S_Msk                           /*!< M0+ transmit Channel6 status set  */
-
-/**********************  Bit definition for IPCC_C2TOC1SR register  ***************/
-#define IPCC_C2TOC1SR_CH1F_Pos    (0U)
-#define IPCC_C2TOC1SR_CH1F_Msk    (0x1UL << IPCC_C2TOC1SR_CH1F_Pos)            /*!< 0x00000001 */
-#define IPCC_C2TOC1SR_CH1F        IPCC_C2TOC1SR_CH1F_Msk                       /*!< M0+ transmit to M0 receive Channel1 status flag before masking */
-#define IPCC_C2TOC1SR_CH2F_Pos    (1U)
-#define IPCC_C2TOC1SR_CH2F_Msk    (0x1UL << IPCC_C2TOC1SR_CH2F_Pos)            /*!< 0x00000002 */
-#define IPCC_C2TOC1SR_CH2F        IPCC_C2TOC1SR_CH2F_Msk                       /*!< M0+ transmit to M0 receive Channel2 status flag before masking */
-#define IPCC_C2TOC1SR_CH3F_Pos    (2U)
-#define IPCC_C2TOC1SR_CH3F_Msk    (0x1UL << IPCC_C2TOC1SR_CH3F_Pos)            /*!< 0x00000004 */
-#define IPCC_C2TOC1SR_CH3F        IPCC_C2TOC1SR_CH3F_Msk                       /*!< M0+ transmit to M0 receive Channel3 status flag before masking */
-#define IPCC_C2TOC1SR_CH4F_Pos    (3U)
-#define IPCC_C2TOC1SR_CH4F_Msk    (0x1UL << IPCC_C2TOC1SR_CH4F_Pos)            /*!< 0x00000008 */
-#define IPCC_C2TOC1SR_CH4F        IPCC_C2TOC1SR_CH4F_Msk                       /*!< M0+ transmit to M0 receive Channel4 status flag before masking */
-#define IPCC_C2TOC1SR_CH5F_Pos    (4U)
-#define IPCC_C2TOC1SR_CH5F_Msk    (0x1UL << IPCC_C2TOC1SR_CH5F_Pos)            /*!< 0x00000010 */
-#define IPCC_C2TOC1SR_CH5F        IPCC_C2TOC1SR_CH5F_Msk                       /*!< M0+ transmit to M0 receive Channel5 status flag before masking */
-#define IPCC_C2TOC1SR_CH6F_Pos    (5U)
-#define IPCC_C2TOC1SR_CH6F_Msk    (0x1UL << IPCC_C2TOC1SR_CH6F_Pos)            /*!< 0x00000020 */
-#define IPCC_C2TOC1SR_CH6F        IPCC_C2TOC1SR_CH6F_Msk                       /*!< M0+ transmit to M0 receive Channel6 status flag before masking */
-
-/**********************  Bit definition for IPCC_C1CR register  ***************/
-#define IPCC_CR_RXOIE_Pos         IPCC_C1CR_RXOIE_Pos
-#define IPCC_CR_RXOIE_Msk         IPCC_C1CR_RXOIE_Msk
-#define IPCC_CR_RXOIE             IPCC_C1CR_RXOIE
-#define IPCC_CR_TXFIE_Pos         IPCC_C1CR_TXFIE_Pos
-#define IPCC_CR_TXFIE_Msk         IPCC_C1CR_TXFIE_Msk
-#define IPCC_CR_TXFIE             IPCC_C1CR_TXFIE
-
-/**********************  Bit definition for IPCC_C1MR register  **************/
-#define IPCC_MR_CH1OM_Pos         IPCC_C1MR_CH1OM_Pos
-#define IPCC_MR_CH1OM_Msk         IPCC_C1MR_CH1OM_Msk
-#define IPCC_MR_CH1OM             IPCC_C1MR_CH1OM
-#define IPCC_MR_CH2OM_Pos         IPCC_C1MR_CH2OM_Pos
-#define IPCC_MR_CH2OM_Msk         IPCC_C1MR_CH2OM_Msk
-#define IPCC_MR_CH2OM             IPCC_C1MR_CH2OM
-#define IPCC_MR_CH3OM_Pos         IPCC_C1MR_CH3OM_Pos
-#define IPCC_MR_CH3OM_Msk         IPCC_C1MR_CH3OM_Msk
-#define IPCC_MR_CH3OM             IPCC_C1MR_CH3OM
-#define IPCC_MR_CH4OM_Pos         IPCC_C1MR_CH4OM_Pos
-#define IPCC_MR_CH4OM_Msk         IPCC_C1MR_CH4OM_Msk
-#define IPCC_MR_CH4OM             IPCC_C1MR_CH4OM
-#define IPCC_MR_CH5OM_Pos         IPCC_C1MR_CH5OM_Pos
-#define IPCC_MR_CH5OM_Msk         IPCC_C1MR_CH5OM_Msk
-#define IPCC_MR_CH5OM             IPCC_C1MR_CH5OM
-#define IPCC_MR_CH6OM_Pos         IPCC_C1MR_CH6OM_Pos
-#define IPCC_MR_CH6OM_Msk         IPCC_C1MR_CH6OM_Msk
-#define IPCC_MR_CH6OM             IPCC_C1MR_CH6OM
-
-#define IPCC_MR_CH1FM_Pos         IPCC_C1MR_CH1FM_Pos
-#define IPCC_MR_CH1FM_Msk         IPCC_C1MR_CH1FM_Msk
-#define IPCC_MR_CH1FM             IPCC_C1MR_CH1FM
-#define IPCC_MR_CH2FM_Pos         IPCC_C1MR_CH2FM_Pos
-#define IPCC_MR_CH2FM_Msk         IPCC_C1MR_CH2FM_Msk
-#define IPCC_MR_CH2FM             IPCC_C1MR_CH2FM
-#define IPCC_MR_CH3FM_Pos         IPCC_C1MR_CH3FM_Pos
-#define IPCC_MR_CH3FM_Msk         IPCC_C1MR_CH3FM_Msk
-#define IPCC_MR_CH3FM             IPCC_C1MR_CH3FM
-#define IPCC_MR_CH4FM_Pos         IPCC_C1MR_CH4FM_Pos
-#define IPCC_MR_CH4FM_Msk         IPCC_C1MR_CH4FM_Msk
-#define IPCC_MR_CH4FM             IPCC_C1MR_CH4FM
-#define IPCC_MR_CH5FM_Pos         IPCC_C1MR_CH5FM_Pos
-#define IPCC_MR_CH5FM_Msk         IPCC_C1MR_CH5FM_Msk
-#define IPCC_MR_CH5FM             IPCC_C1MR_CH5FM
-#define IPCC_MR_CH6FM_Pos         IPCC_C1MR_CH6FM_Pos
-#define IPCC_MR_CH6FM_Msk         IPCC_C1MR_CH6FM_Msk
-#define IPCC_MR_CH6FM             IPCC_C1MR_CH6FM
-
-/**********************  Bit definition for IPCC_C1SCR register  ***************/
-#define IPCC_SCR_CH1C_Pos         IPCC_C1SCR_CH1C_Pos
-#define IPCC_SCR_CH1C_Msk         IPCC_C1SCR_CH1C_Msk
-#define IPCC_SCR_CH1C             IPCC_C1SCR_CH1C
-#define IPCC_SCR_CH2C_Pos         IPCC_C1SCR_CH2C_Pos
-#define IPCC_SCR_CH2C_Msk         IPCC_C1SCR_CH2C_Msk
-#define IPCC_SCR_CH2C             IPCC_C1SCR_CH2C
-#define IPCC_SCR_CH3C_Pos         IPCC_C1SCR_CH3C_Pos
-#define IPCC_SCR_CH3C_Msk         IPCC_C1SCR_CH3C_Msk
-#define IPCC_SCR_CH3C             IPCC_C1SCR_CH3C
-#define IPCC_SCR_CH4C_Pos         IPCC_C1SCR_CH4C_Pos
-#define IPCC_SCR_CH4C_Msk         IPCC_C1SCR_CH4C_Msk
-#define IPCC_SCR_CH4C             IPCC_C1SCR_CH4C
-#define IPCC_SCR_CH5C_Pos         IPCC_C1SCR_CH5C_Pos
-#define IPCC_SCR_CH5C_Msk         IPCC_C1SCR_CH5C_Msk
-#define IPCC_SCR_CH5C             IPCC_C1SCR_CH5C
-#define IPCC_SCR_CH6C_Pos         IPCC_C1SCR_CH6C_Pos
-#define IPCC_SCR_CH6C_Msk         IPCC_C1SCR_CH6C_Msk
-#define IPCC_SCR_CH6C             IPCC_C1SCR_CH6C
-
-#define IPCC_SCR_CH1S_Pos         IPCC_C1SCR_CH1S_Pos
-#define IPCC_SCR_CH1S_Msk         IPCC_C1SCR_CH1S_Msk
-#define IPCC_SCR_CH1S             IPCC_C1SCR_CH1S
-#define IPCC_SCR_CH2S_Pos         IPCC_C1SCR_CH2S_Pos
-#define IPCC_SCR_CH2S_Msk         IPCC_C1SCR_CH2S_Msk
-#define IPCC_SCR_CH2S             IPCC_C1SCR_CH2S
-#define IPCC_SCR_CH3S_Pos         IPCC_C1SCR_CH3S_Pos
-#define IPCC_SCR_CH3S_Msk         IPCC_C1SCR_CH3S_Msk
-#define IPCC_SCR_CH3S             IPCC_C1SCR_CH3S
-#define IPCC_SCR_CH4S_Pos         IPCC_C1SCR_CH4S_Pos
-#define IPCC_SCR_CH4S_Msk         IPCC_C1SCR_CH4S_Msk
-#define IPCC_SCR_CH4S             IPCC_C1SCR_CH4S
-#define IPCC_SCR_CH5S_Pos         IPCC_C1SCR_CH5S_Pos
-#define IPCC_SCR_CH5S_Msk         IPCC_C1SCR_CH5S_Msk
-#define IPCC_SCR_CH5S             IPCC_C1SCR_CH5S
-#define IPCC_SCR_CH6S_Pos         IPCC_C1SCR_CH6S_Pos
-#define IPCC_SCR_CH6S_Msk         IPCC_C1SCR_CH6S_Msk
-#define IPCC_SCR_CH6S             IPCC_C1SCR_CH6S
-
-/**********************  Bit definition for IPCC_C1TOC2SR register  ***************/
-#define IPCC_SR_CH1F_Pos          IPCC_C1TOC2SR_CH1F_Pos
-#define IPCC_SR_CH1F_Msk          IPCC_C1TOC2SR_CH1F_Msk
-#define IPCC_SR_CH1F              IPCC_C1TOC2SR_CH1F
-#define IPCC_SR_CH2F_Pos          IPCC_C1TOC2SR_CH2F_Pos
-#define IPCC_SR_CH2F_Msk          IPCC_C1TOC2SR_CH2F_Msk
-#define IPCC_SR_CH2F              IPCC_C1TOC2SR_CH2F
-#define IPCC_SR_CH3F_Pos          IPCC_C1TOC2SR_CH3F_Pos
-#define IPCC_SR_CH3F_Msk          IPCC_C1TOC2SR_CH3F_Msk
-#define IPCC_SR_CH3F              IPCC_C1TOC2SR_CH3F
-#define IPCC_SR_CH4F_Pos          IPCC_C1TOC2SR_CH4F_Pos
-#define IPCC_SR_CH4F_Msk          IPCC_C1TOC2SR_CH4F_Msk
-#define IPCC_SR_CH4F              IPCC_C1TOC2SR_CH4F
-#define IPCC_SR_CH5F_Pos          IPCC_C1TOC2SR_CH5F_Pos
-#define IPCC_SR_CH5F_Msk          IPCC_C1TOC2SR_CH5F_Msk
-#define IPCC_SR_CH5F              IPCC_C1TOC2SR_CH5F
-#define IPCC_SR_CH6F_Pos          IPCC_C1TOC2SR_CH6F_Pos
-#define IPCC_SR_CH6F_Msk          IPCC_C1TOC2SR_CH6F_Msk
-#define IPCC_SR_CH6F              IPCC_C1TOC2SR_CH6F
-
-/******************** Number of IPCC channels ******************************/
-#define IPCC_CHANNEL_NUMBER       6U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 VREFBUF                                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for VREFBUF_CSR register  ****************/
-#define VREFBUF_CSR_ENVR_Pos    (0U)
-#define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                /*!< 0x00000001 */
-#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
-#define VREFBUF_CSR_HIZ_Pos     (1U)
-#define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                 /*!< 0x00000002 */
-#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
-#define VREFBUF_CSR_VRS_Pos     (2U)
-#define VREFBUF_CSR_VRS_Msk     (0x1UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000004 */
-#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference buffer ready  */
-#define VREFBUF_CSR_VRR_Pos     (3U)
-#define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                 /*!< 0x00000008 */
-#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference scale         */
-
-/*******************  Bit definition for VREFBUF_CCR register  ******************/
-#define VREFBUF_CCR_TRIM_Pos    (0U)
-#define VREFBUF_CCR_TRIM_Msk    (0x3FUL << VREFBUF_CCR_TRIM_Pos)               /*!< 0x0000003F */
-#define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
-
-#define WWDG_CR_WDGA_Pos        (7U)
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
-
-#define WWDG_CFR_EWI_Pos        (9U)
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
-
-#define WWDG_CFR_WDGTB_Pos      (11U)
-#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000800 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00001000 */
-#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00002000 */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
-
-
-#if defined(CORE_CM0PLUS)
-#else
-/******************************************************************************/
-/*                                                                            */
-/*                                Debug MCU                                   */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                          (0U)
-#define DBGMCU_IDCODE_DEV_ID_Msk                          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                              DBGMCU_IDCODE_DEV_ID_Msk
-#define DBGMCU_IDCODE_REV_ID_Pos                          (16U)
-#define DBGMCU_IDCODE_REV_ID_Msk                          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                              DBGMCU_IDCODE_REV_ID_Msk
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                           (0U)
-#define DBGMCU_CR_DBG_SLEEP_Msk                           (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)  /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                               DBGMCU_CR_DBG_SLEEP_Msk
-#define DBGMCU_CR_DBG_STOP_Pos                            (1U)
-#define DBGMCU_CR_DBG_STOP_Msk                            (0x1UL << DBGMCU_CR_DBG_STOP_Pos)   /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                                DBGMCU_CR_DBG_STOP_Msk
-#define DBGMCU_CR_DBG_STANDBY_Pos                         (2U)
-#define DBGMCU_CR_DBG_STANDBY_Msk                         (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                             DBGMCU_CR_DBG_STANDBY_Msk
-
-/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos                 (0U)
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)  /*!< 0x00000001 */
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP                     DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos                  (10U)
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk                  (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)   /*!< 0x00000400 */
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP                      DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos                 (11U)
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)  /*!< 0x00000800 */
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP                     DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos                 (12U)
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)  /*!< 0x00001000 */
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP                     DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos                 (21U)
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)  /*!< 0x00200000 */
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP                     DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos                 (22U)
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)  /*!< 0x00400000 */
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP                     DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos                 (23U)
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)  /*!< 0x00800000 */
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP                     DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos               (31U)
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk               (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP                   DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
-
-/********************  Bit definition for DBGMCU_C2APB1FZR1 register  ***********/
-#define DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Pos               (0U)
-#define DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Msk               (0x1UL << DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Pos)  /*!< 0x00000001 */
-#define DBGMCU_C2APB1FZR1_DBG_TIM2_STOP                   DBGMCU_C2APB1FZR1_DBG_TIM2_STOP_Msk
-#define DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Pos                (10U)
-#define DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Msk                (0x1UL << DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Pos)   /*!< 0x00000400 */
-#define DBGMCU_C2APB1FZR1_DBG_RTC_STOP                    DBGMCU_C2APB1FZR1_DBG_RTC_STOP_Msk
-#define DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Pos               (12U)
-#define DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Msk               (0x1UL << DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Pos)  /*!< 0x00001000 */
-#define DBGMCU_C2APB1FZR1_DBG_IWDG_STOP                   DBGMCU_C2APB1FZR1_DBG_IWDG_STOP_Msk
-#define DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Pos               (21U)
-#define DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Msk               (0x1UL << DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Pos)  /*!< 0x00200000 */
-#define DBGMCU_C2APB1FZR1_DBG_I2C1_STOP                   DBGMCU_C2APB1FZR1_DBG_I2C1_STOP_Msk
-#define DBGMCU_C2APB1FZR1_DBG_I2C2_STOP_Pos               (22U)
-#define DBGMCU_C2APB1FZR1_DBG_I2C2_STOP_Msk               (0x1UL << DBGMCU_C2APB1FZR1_DBG_I2C2_STOP_Pos)  /*!< 0x00400000 */
-#define DBGMCU_C2APB1FZR1_DBG_I2C2_STOP                   DBGMCU_C2APB1FZR1_DBG_I2C2_STOP_Msk
-#define DBGMCU_C2APB1FZR1_DBG_I2C3_STOP_Pos               (23U)
-#define DBGMCU_C2APB1FZR1_DBG_I2C3_STOP_Msk               (0x1UL << DBGMCU_C2APB1FZR1_DBG_I2C3_STOP_Pos)  /*!< 0x00800000 */
-#define DBGMCU_C2APB1FZR1_DBG_I2C3_STOP                   DBGMCU_C2APB1FZR1_DBG_I2C3_STOP_Msk
-#define DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Pos             (31U)
-#define DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Msk             (0x1UL << DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
-#define DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP                 DBGMCU_C2APB1FZR1_DBG_LPTIM1_STOP_Msk
-
-/********************  Bit definition for DBGMCU_APB1FZR2 register  ***********/
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos               (5U)
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk               (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)/*!< 0x00000020 */
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP                   DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
-#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Pos               (6U)
-#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk               (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Pos)/*!< 0x00000040 */
-#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP                   DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk
-
-/********************  Bit definition for DBGMCU_C2APB1FZR2 register  ***********/
-#define DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Pos             (5U)
-#define DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Msk             (0x1UL << DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Pos)/*!< 0x00000020 */
-#define DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP                 DBGMCU_C2APB1FZR2_DBG_LPTIM2_STOP_Msk
-#define DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP_Pos             (6U)
-#define DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP_Msk             (0x1UL << DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP_Pos)/*!< 0x00000040 */
-#define DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP                 DBGMCU_C2APB1FZR2_DBG_LPTIM3_STOP_Msk
-
-/********************  Bit definition for DBGMCU_APB2FZR register  ************/
-#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos                  (11U)
-#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk                  (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)/*!< 0x000000800 */
-#define DBGMCU_APB2FZR_DBG_TIM1_STOP                      DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk
-#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos                 (17U)
-#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk                 (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
-#define DBGMCU_APB2FZR_DBG_TIM16_STOP                     DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk
-#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos                 (18U)
-#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk                 (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
-#define DBGMCU_APB2FZR_DBG_TIM17_STOP                     DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk
-
-/********************  Bit definition for DBGMCU_C2APB2FZR register  ************/
-#define DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Pos                (11U)
-#define DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Msk                (0x1UL << DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Pos)/*!< 0x000000800 */
-#define DBGMCU_C2APB2FZR_DBG_TIM1_STOP                    DBGMCU_C2APB2FZR_DBG_TIM1_STOP_Msk
-#define DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Pos               (17U)
-#define DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Msk               (0x1UL << DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
-#define DBGMCU_C2APB2FZR_DBG_TIM16_STOP                   DBGMCU_C2APB2FZR_DBG_TIM16_STOP_Msk
-#define DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Pos               (18U)
-#define DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Msk               (0x1UL << DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
-#define DBGMCU_C2APB2FZR_DBG_TIM17_STOP                   DBGMCU_C2APB2FZR_DBG_TIM17_STOP_Msk
-
-#endif
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
-
-#define TIM_CR1_UIFREMAP_Pos      (11U)
-#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
-#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCPC_Pos          (0U)
-#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
-#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS_Pos          (2U)
-#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
-#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS_Pos          (3U)
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-#define TIM_CR2_OIS1_Pos          (8U)
-#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
-#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N_Pos         (9U)
-#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
-#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2_Pos          (10U)
-#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
-#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N_Pos         (11U)
-#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
-#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3_Pos          (12U)
-#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
-#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N_Pos         (13U)
-#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
-#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4_Pos          (14U)
-#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
-#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS5_Pos          (16U)
-#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
-#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
-#define TIM_CR2_OIS6_Pos          (18U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
-#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
-
-#define TIM_CR2_MMS2_Pos          (20U)
-#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
-#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
-#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
-#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
-#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)
-#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
-#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
-
-#define TIM_SMCR_OCCS_Pos         (3U)
-#define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
-#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos           (4U)
-#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
-#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
-#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
-
-#define TIM_SMCR_MSM_Pos          (7U)
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE_Pos        (5U)
-#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
-#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_BIE_Pos          (7U)
-#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
-#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE_Pos        (13U)
-#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
-#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF_Pos          (5U)
-#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
-#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF_Pos            (7U)
-#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
-#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
-#define TIM_SR_B2IF_Pos           (8U)
-#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
-#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-#define TIM_SR_SBIF_Pos           (13U)
-#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
-#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
-#define TIM_SR_CC5IF_Pos          (16U)
-#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
-#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
-#define TIM_SR_CC6IF_Pos          (17U)
-#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
-#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
-
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG_Pos          (5U)
-#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
-#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG_Pos            (6U)
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-#define TIM_EGR_BG_Pos            (7U)
-#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
-#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
-#define TIM_EGR_B2G_Pos           (8U)
-#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
-#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)
-#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
-#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)
-#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
-#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-#define TIM_CCMR1_IC1PSC_Pos      (2U)
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
-#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-#define TIM_CCMR2_IC3PSC_Pos      (2U)
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR3 register  *******************/
-#define TIM_CCMR3_OC5FE_Pos       (2U)
-#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
-#define TIM_CCMR3_OC5PE_Pos       (3U)
-#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
-#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
-
-#define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
-#define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
-#define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
-#define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
-#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
-
-#define TIM_CCMR3_OC5CE_Pos       (7U)
-#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
-#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
-
-#define TIM_CCMR3_OC6FE_Pos       (10U)
-#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
-#define TIM_CCMR3_OC6PE_Pos       (11U)
-#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
-#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
-
-#define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
-#define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
-#define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
-#define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
-
-#define TIM_CCMR3_OC6CE_Pos       (15U)
-#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
-#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE_Pos        (2U)
-#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
-#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP_Pos        (3U)
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE_Pos        (6U)
-#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
-#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP_Pos        (7U)
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE_Pos        (10U)
-#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
-#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP_Pos        (11U)
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-#define TIM_CCER_CC5E_Pos         (16U)
-#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
-#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
-#define TIM_CCER_CC5P_Pos         (17U)
-#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
-#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
-#define TIM_CCER_CC6E_Pos         (20U)
-#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
-#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
-#define TIM_CCER_CC6P_Pos         (21U)
-#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
-#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)
-#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-#define TIM_CNT_UIFCPY_Pos        (31U)
-#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
-#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)
-#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define TIM_RCR_REP_Pos           (0U)
-#define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
-#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)
-#define TIM_CCR1_CCR1_Msk         (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)
-#define TIM_CCR2_CCR2_Msk         (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)
-#define TIM_CCR3_CCR3_Msk         (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)
-#define TIM_CCR4_CCR4_Msk         (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_CCR5 register  *******************/
-#define TIM_CCR5_CCR5_Pos         (0U)
-#define TIM_CCR5_CCR5_Msk         (0xFFFFUL << TIM_CCR5_CCR5_Pos)              /*!< 0x0000FFFF */
-#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
-#define TIM_CCR5_GC5C1_Pos        (29U)
-#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
-#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
-#define TIM_CCR5_GC5C2_Pos        (30U)
-#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
-#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
-#define TIM_CCR5_GC5C3_Pos        (31U)
-#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
-#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
-
-/*******************  Bit definition for TIM_CCR6 register  *******************/
-#define TIM_CCR6_CCR6_Pos         (0U)
-#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
-#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define TIM_BDTR_DTG_Pos          (0U)
-#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
-#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
-#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
-#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
-#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
-#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
-#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
-#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
-#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
-
-#define TIM_BDTR_LOCK_Pos         (8U)
-#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
-#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
-#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
-
-#define TIM_BDTR_OSSI_Pos         (10U)
-#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
-#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR_Pos         (11U)
-#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
-#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE_Pos          (12U)
-#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
-#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
-#define TIM_BDTR_BKP_Pos          (13U)
-#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
-#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
-#define TIM_BDTR_AOE_Pos          (14U)
-#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
-#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
-#define TIM_BDTR_MOE_Pos          (15U)
-#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
-#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
-
-#define TIM_BDTR_BKF_Pos          (16U)
-#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
-#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
-#define TIM_BDTR_BK2F_Pos         (20U)
-#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
-#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
-
-#define TIM_BDTR_BK2E_Pos         (24U)
-#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
-#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
-#define TIM_BDTR_BK2P_Pos         (25U)
-#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
-#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
-
-
-#define TIM_BDTR_BKDSRM_Pos       (26U)
-#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
-#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
-#define TIM_BDTR_BK2DSRM_Pos      (27U)
-#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
-#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
-
-#define TIM_BDTR_BKBID_Pos        (28U)
-#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
-#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
-#define TIM_BDTR_BK2BID_Pos       (29U)
-#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
-#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM1_OR1 register  ******************/
-#define TIM1_OR1_ETR_ADC_RMP_Pos   (0U)
-#define TIM1_OR1_ETR_ADC_RMP_Msk   (0x3UL << TIM1_OR1_ETR_ADC_RMP_Pos)         /*!< 0x00000003 */
-#define TIM1_OR1_ETR_ADC_RMP       TIM1_OR1_ETR_ADC_RMP_Msk                    /*!< TIM1_ETR_ADC remapping capability */
-#define TIM1_OR1_ETR_ADC_RMP_0     (0x1UL << TIM1_OR1_ETR_ADC_RMP_Pos)         /*!< 0x00000001 */
-#define TIM1_OR1_ETR_ADC_RMP_1     (0x2UL << TIM1_OR1_ETR_ADC_RMP_Pos)         /*!< 0x00000002 */
-#define TIM1_OR1_TI1_RMP_Pos       (4U)
-#define TIM1_OR1_TI1_RMP_Msk       (0x1UL << TIM1_OR1_TI1_RMP_Pos)             /*!< 0x00000010 */
-#define TIM1_OR1_TI1_RMP           TIM1_OR1_TI1_RMP_Msk                        /*!< Input Capture 1 remap*/
-
-/*******************  Bit definition for TIM2_OR1 register  ******************/
-#define TIM2_OR1_TI4_RMP_Pos       (2U)
-#define TIM2_OR1_TI4_RMP_Msk       (0x3UL << TIM2_OR1_TI4_RMP_Pos)             /*!< 0x0000000C */
-#define TIM2_OR1_TI4_RMP           TIM2_OR1_TI4_RMP_Msk                        /*!< TI4 RMA[1:0]Input capture 4 remap*/
-#define TIM2_OR1_TI4_RMP_0         (0x1UL << TIM2_OR1_TI4_RMP_Pos)             /*!< 0x00000004 */
-#define TIM2_OR1_TI4_RMP_1         (0x2UL << TIM2_OR1_TI4_RMP_Pos)             /*!< 0x00000008 */
-#define TIM2_OR1_ETR_RMP_Pos       (1U)
-#define TIM2_OR1_ETR_RMP_Msk       (0x1UL << TIM2_OR1_ETR_RMP_Pos)             /*!< 0x00000002 */
-#define TIM2_OR1_ETR_RMP           TIM2_OR1_ETR_RMP_Msk                        /*!< External trigger remap*/
-
-/*******************  Bit definition for TIM16_OR1 register  *****************/
-#define TIM16_OR1_TI1_RMP_Pos      (0U)
-#define TIM16_OR1_TI1_RMP_Msk      (0x3UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000003 */
-#define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<Timer 16 input 1 connection. */
-#define TIM16_OR1_TI1_RMP_0        (0x1UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */
-#define TIM16_OR1_TI1_RMP_1        (0x2UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */
-
-/*******************  Bit definition for TIM17_OR1 register  *****************/
-#define TIM17_OR1_TI1_RMP_Pos      (0U)
-#define TIM17_OR1_TI1_RMP_Msk      (0x3UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000003 */
-#define TIM17_OR1_TI1_RMP          TIM17_OR1_TI1_RMP_Msk                       /*!<Timer 17 input 1 connection. */
-#define TIM17_OR1_TI1_RMP_0        (0x1UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */
-#define TIM17_OR1_TI1_RMP_1        (0x2UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */
-
-/*******************  Bit definition for TIM1_AF1 register  *******************/
-#define TIM1_AF1_BKINE_Pos        (0U)
-#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
-#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
-#define TIM1_AF1_BKCMP1E_Pos      (1U)                                         
-#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
-#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
-#define TIM1_AF1_BKCMP2E_Pos      (2U)                                         
-#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
-#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
-#define TIM1_AF1_BKINP_Pos        (9U)                                         
-#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
-#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
-#define TIM1_AF1_BKCMP1P_Pos      (10U)                                        
-#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
-#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
-#define TIM1_AF1_BKCMP2P_Pos      (11U)                                        
-#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
-#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
-#define TIM1_AF1_ETRSEL_Pos       (14U)                                        
-#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
-#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
-#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
-#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
-#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
-#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
-
-/*******************  Bit definition for TIM2_AF1 register  *******************/
-#define TIM2_AF1_ETRSEL_Pos       (14U)
-#define TIM2_AF1_ETRSEL_Msk       (0xFUL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
-#define TIM2_AF1_ETRSEL           (0x00003C000)                                /*!< External trigger source selection */
-#define TIM2_AF1_ETRSEL_0         (0x000004000)                                /*!< Bit_0 */
-#define TIM2_AF1_ETRSEL_1         (0x000008000)                                /*!< Bit_1 */
-#define TIM2_AF1_ETRSEL_2         (0x000010000)                                /*!< Bit_2 */
-#define TIM2_AF1_ETRSEL_3         (0x000020000)                                /*!< Bit_3 */
-
-/*******************  Bit definition for TIM16_AF1 register  *******************/
-#define TIM16_AF1_BKINE_Pos       (0U)
-#define TIM16_AF1_BKINE_Msk       (0x1UL << TIM16_AF1_BKINE_Pos)               /*!< 0x00000001 */
-#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BRK BKIN input enable */
-#define TIM16_AF1_BKCMP1E_Pos     (1U)
-#define TIM16_AF1_BKCMP1E_Msk     (0x1UL << TIM16_AF1_BKCMP1E_Pos)             /*!< 0x00000002 */
-#define TIM16_AF1_BKCMP1E         TIM16_AF1_BKCMP1E_Msk                        /*!<BRK COMP1 enable */
-#define TIM16_AF1_BKCMP2E_Pos     (2U)                                         
-#define TIM16_AF1_BKCMP2E_Msk     (0x1UL << TIM16_AF1_BKCMP2E_Pos)             /*!< 0x00000004 */
-#define TIM16_AF1_BKCMP2E         TIM16_AF1_BKCMP2E_Msk                        /*!<BRK COMP2 enable */
-#define TIM16_AF1_BKINP_Pos       (9U)                                         
-#define TIM16_AF1_BKINP_Msk       (0x1UL << TIM16_AF1_BKINP_Pos)               /*!< 0x00000200 */
-#define TIM16_AF1_BKINP           TIM16_AF1_BKINP_Msk                          /*!<BRK BKIN2 input polarity */
-#define TIM16_AF1_BKCMP1P_Pos     (10U)                                        
-#define TIM16_AF1_BKCMP1P_Msk     (0x1UL << TIM16_AF1_BKCMP1P_Pos)             /*!< 0x00000400 */
-#define TIM16_AF1_BKCMP1P         TIM16_AF1_BKCMP1P_Msk                        /*!<BRK COMP1 input polarity */
-#define TIM16_AF1_BKCMP2P_Pos     (11U)                                        
-#define TIM16_AF1_BKCMP2P_Msk     (0x1UL << TIM16_AF1_BKCMP2P_Pos)             /*!< 0x00000800 */
-#define TIM16_AF1_BKCMP2P         TIM16_AF1_BKCMP2P_Msk                        /*!<BRK COMP2 input polarity */
-
-/*******************  Bit definition for TIM17_AF1 register  *******************/
-#define TIM17_AF1_BKINE_Pos       (0U)
-#define TIM17_AF1_BKINE_Msk       (0x1UL << TIM17_AF1_BKINE_Pos)               /*!< 0x00000001 */
-#define TIM17_AF1_BKINE           TIM17_AF1_BKINE_Msk                          /*!<BRK BKIN input enable */
-#define TIM17_AF1_BKCMP1E_Pos     (1U)
-#define TIM17_AF1_BKCMP1E_Msk     (0x1UL << TIM17_AF1_BKCMP1E_Pos)             /*!< 0x00000002 */
-#define TIM17_AF1_BKCMP1E         TIM17_AF1_BKCMP1E_Msk                        /*!<BRK COMP1 enable */
-#define TIM17_AF1_BKCMP2E_Pos     (2U)                                         
-#define TIM17_AF1_BKCMP2E_Msk     (0x1UL << TIM17_AF1_BKCMP2E_Pos)             /*!< 0x00000004 */
-#define TIM17_AF1_BKCMP2E         TIM17_AF1_BKCMP2E_Msk                        /*!<BRK COMP2 enable */
-#define TIM17_AF1_BKINP_Pos       (9U)                                         
-#define TIM17_AF1_BKINP_Msk       (0x1UL << TIM17_AF1_BKINP_Pos)               /*!< 0x00000200 */
-#define TIM17_AF1_BKINP           TIM17_AF1_BKINP_Msk                          /*!<BRK BKIN2 input polarity */
-#define TIM17_AF1_BKCMP1P_Pos     (10U)                                        
-#define TIM17_AF1_BKCMP1P_Msk     (0x1UL << TIM17_AF1_BKCMP1P_Pos)             /*!< 0x00000400 */
-#define TIM17_AF1_BKCMP1P         TIM17_AF1_BKCMP1P_Msk                        /*!<BRK COMP1 input polarity */
-#define TIM17_AF1_BKCMP2P_Pos     (11U)                                        
-#define TIM17_AF1_BKCMP2P_Msk     (0x1UL << TIM17_AF1_BKCMP2P_Pos)             /*!< 0x00000800 */
-#define TIM17_AF1_BKCMP2P         TIM17_AF1_BKCMP2P_Msk                        /*!<BRK COMP2 input polarity */
-
-/*******************  Bit definition for TIM1_AF2 register  *******************/
-#define TIM1_AF2_BK2INE_Pos       (0U)
-#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */
-#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BRK2 BKIN2 input enable */
-#define TIM1_AF2_BK2CMP1E_Pos     (1U)                                         
-#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
-#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BRK2 COMP1 enable */
-#define TIM1_AF2_BK2CMP2E_Pos     (2U)                                         
-#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
-#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BRK2 COMP2 enable */
-#define TIM1_AF2_BK2INP_Pos       (9U)                                         
-#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */
-#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRK2 BKIN2 input polarity */
-#define TIM1_AF2_BK2CMP1P_Pos     (10U)                                        
-#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
-#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BRK2 COMP1 input polarity */
-#define TIM1_AF2_BK2CMP2P_Pos     (11U)                                        
-#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
-#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BRK2 COMP2 input polarity */
-
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/*!< Root Secure Service Library */
-/*!< HDP Area constant definition */
-#define RSSLIB_HDP_AREA_Pos       (0U)
-#define RSSLIB_HDP_AREA_Msk       (0x3UL << RSSLIB_HDP_AREA_Pos)
-#define RSSLIB_HDP_AREA1_Msk      (0x1UL << RSSLIB_HDP_AREA_Pos)
-#define RSSLIB_HDP_AREA1          RSSLIB_HDP_AREA1_Msk
-
-/**
-  * @brief  Prototype of RSSLIB Close and exit HDP Function
-  * @detail This function close the requested hdp area passed in input
-  *         parameter and jump to the reset handler present within the
-  *         Vector table. The function does not return on successful execution.
-  * @param  HdpArea notifies which hdp area to close.
-  * @param  pointer on the vector table containing the reset handler the function
-  *         jumps to.
-  * @retval No return value.
-  */
-typedef void (*RSSLIB_S_CloseExitHDP_t)(uint32_t hdp_area, uint32_t jump_addr);
-
-/**
-  * @brief RSSLib function pointer structure
-  */
-typedef struct
-{
-  RSSLIB_S_CloseExitHDP_t CloseExitHDP;
-}RSSLIB_pFunc_TypeDef;
-
-#define RSSLIB_PFUNC                  ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE)
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC_COMMON)
-
-/******************************* AES Instances ********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5) || \
-                                       ((INSTANCE) == DMA2_Channel6) || \
-                                       ((INSTANCE) == DMA2_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************* GPIO AF Instances ****************************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************* SMBUS Instances ******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************* IPCC Instances ********************************/
-#define IS_IPCC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IPCC)
-
-/******************************** HSEM Instances *******************************/
-#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
-
-#define HSEM_CPU1_COREID   (0x00000004U) /* Semaphore Core ID */
-#define HSEM_CPU2_COREID   (0x00000008U) /* Semaphore Core ID */
-
-#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/
-#define HSEM_SEMID_MAX     (15U)      /* HSEM ID Max */
-
-#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */
-#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */
-
-#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */
-#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */
-
-/******************************** PKA Instances *******************************/
-#define IS_PKA_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == PKA)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
-
-/****************************** RTC Instances *********************************/
-#define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SUBGHZSPI))
-
-/******************************** SUBGHZSPI Instances *************************/
-#define IS_SUBGHZ_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SUBGHZSPI)
-#define IS_SUBGHZ_MODULATION_SUPPORTED(COMMAND,PACKET_TYPE)  (1U == 1U)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
-                                         ((INSTANCE) == LPTIM2) || \
-                                         ((INSTANCE) == LPTIM3))
-
-/****************** LPTIM Instances : Encoder mode ****************************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM16)  || \
-                                         ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting 32 bits counter ****************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : supporting the break function *************/
-#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
-                                            ((INSTANCE) == TIM16)   || \
-                                            ((INSTANCE) == TIM17))
-
-/************** TIM Instances : supporting Break source selection *************/
-#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                               ((INSTANCE) == TIM16)  || \
-                                               ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting 2 break inputs *****************/
-#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM16)  || \
-                                         ((INSTANCE) == TIM17))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : at least 5 capture/compare channels *******/
-#define IS_TIM_CC5_INSTANCE(INSTANCE)      ((INSTANCE) == TIM1)
-
-/****************** TIM Instances : at least 6 capture/compare channels *******/
-#define IS_TIM_CC6_INSTANCE(INSTANCE)      ((INSTANCE) == TIM1)
-
-/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/******************* TIM Instances : Timer input selection ********************/
-#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM16)   || \
-                                         ((INSTANCE) == TIM17))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-        ((((INSTANCE) == TIM1) &&                  \
-           (((CHANNEL) == TIM_CHANNEL_1) ||          \
-            ((CHANNEL) == TIM_CHANNEL_2) ||          \
-            ((CHANNEL) == TIM_CHANNEL_3) ||          \
-            ((CHANNEL) == TIM_CHANNEL_4) ||          \
-            ((CHANNEL) == TIM_CHANNEL_5) ||          \
-            ((CHANNEL) == TIM_CHANNEL_6)))           \
-           ||                                        \
-           (((INSTANCE) == TIM2) &&                  \
-           (((CHANNEL) == TIM_CHANNEL_1) ||          \
-            ((CHANNEL) == TIM_CHANNEL_2) ||          \
-            ((CHANNEL) == TIM_CHANNEL_3) ||          \
-            ((CHANNEL) == TIM_CHANNEL_4)))           \
-           ||                                        \
-           (((INSTANCE) == TIM16) &&                 \
-           (((CHANNEL) == TIM_CHANNEL_1)))           \
-           ||                                        \
-           (((INSTANCE) == TIM17) &&                 \
-            (((CHANNEL) == TIM_CHANNEL_1))))
-
-/****************** TIM Instances : supporting complementary output(s) ********/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM17) &&                   \
-     ((CHANNEL) == TIM_CHANNEL_1))              \
-    ||                                          \
-    (((INSTANCE) == TIM16) &&                   \
-     ((CHANNEL) == TIM_CHANNEL_1)))
-
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
-                                                    ((INSTANCE) == TIM2)    || \
-                                                    ((INSTANCE) == TIM16)   || \
-                                                    ((INSTANCE) == TIM17))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
-#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/****************** TIM Instances : supporting commutation event generation ***/
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
-                                                     ((INSTANCE) == TIM16)   || \
-                                                     ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting counting mode selection ********/
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
-                                                      ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting Hall sensor interface **********/
-#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/**************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2))
-
-/************* TIM Instances : supporting ETR source selection ***************/
-#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                             ((INSTANCE) == TIM2))
-
-/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting OCxREF clear *******************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
-                                                       ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM16) || \
-                                            ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting repetition counter *************/
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
-                                                       ((INSTANCE) == TIM16) || \
-                                                       ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
-#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2))
-
-/************ TIM Instances : Advanced timers  ********************************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* USART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/****************** UART Instances : Auto Baud Rate detection ****************/
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : SPI Slave selection mode ***************/
-#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                              ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_FIFO_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
-                                             ((INSTANCE) == USART2) || \
-                                             ((INSTANCE) == LPUART1))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32WL55xx_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Include/stm32wle4xx.h

@@ -1,9758 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wle4xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex Device Peripheral Access Layer Header File.
-  *          This file contains all the peripheral register's definitions, bits
-  *          definitions and memory mapping for stm32wle4xx devices.
-  *
-  *          This file contains:selected
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2020(-2021) STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32wle4xx
-  * @{
-  */
-
-#ifndef __STM32WLE4xx_H
-#define __STM32WLE4xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-
-
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief stm32wle4xx Interrupt Number Definition, according to the selected device
- *        in @ref Library_configuration_section
- */
-/*!< Interrupt Number Definition for M4 */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn                 = -14,    /*!< Non Maskable Interrupt                                            */
-  HardFault_IRQn                      = -13,    /*!< Cortex-M4 Hard Fault Interrupt                                    */
-  MemoryManagement_IRQn               = -12,    /*!< Cortex-M4 Memory Management Interrupt                             */
-  BusFault_IRQn                       = -11,    /*!< Cortex-M4 Bus Fault Interrupt                                     */
-  UsageFault_IRQn                     = -10,    /*!< Cortex-M4 Usage Fault Interrupt                                   */
-  SVCall_IRQn                         = -5,     /*!< Cortex-M4 SV Call Interrupt                                       */
-  DebugMonitor_IRQn                   = -4,     /*!< Cortex-M4 Debug Monitor Interrupt                                 */
-  PendSV_IRQn                         = -2,     /*!< Cortex-M4 Pend SV Interrupt                                       */
-  SysTick_IRQn                        = -1,     /*!< Cortex-M4 System Tick Interrupt                                   */
-
-/*************  STM32WLxx specific Interrupt Numbers on M4 core ************************************************/
-  WWDG_IRQn                           = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_PVM_IRQn                        = 1,      /*!< PVD and PVM detector                                              */
-  TAMP_STAMP_LSECSS_SSRU_IRQn         = 2,      /*!< RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts         */
-  RTC_WKUP_IRQn                       = 3,      /*!< RTC Wakeup Interrupt                                              */
-  FLASH_IRQn                          = 4,      /*!< FLASH (CFI)  global Interrupt                                     */
-  RCC_IRQn                            = 5,      /*!< RCC Interrupt                                                     */
-  EXTI0_IRQn                          = 6,      /*!< EXTI Line 0 Interrupt                                             */
-  EXTI1_IRQn                          = 7,      /*!< EXTI Line 1 Interrupt                                             */
-  EXTI2_IRQn                          = 8,      /*!< EXTI Line 2 Interrupt                                             */
-  EXTI3_IRQn                          = 9,      /*!< EXTI Line 3 Interrupt                                             */
-  EXTI4_IRQn                          = 10,     /*!< EXTI Line 4 Interrupt                                             */
-  DMA1_Channel1_IRQn                  = 11,     /*!< DMA1 Channel 1 Interrupt                                          */
-  DMA1_Channel2_IRQn                  = 12,     /*!< DMA1 Channel 2 Interrupt                                          */
-  DMA1_Channel3_IRQn                  = 13,     /*!< DMA1 Channel 3 Interrupt                                          */
-  DMA1_Channel4_IRQn                  = 14,     /*!< DMA1 Channel 4 Interrupt                                          */
-  DMA1_Channel5_IRQn                  = 15,     /*!< DMA1 Channel 5 Interrupt                                          */
-  DMA1_Channel6_IRQn                  = 16,     /*!< DMA1 Channel 6 Interrupt                                          */
-  DMA1_Channel7_IRQn                  = 17,     /*!< DMA1 Channel 7 Interrupt                                          */
-  ADC_IRQn                            = 18,     /*!< ADC Interrupt                                                     */
-  DAC_IRQn                            = 19,     /*!< DAC Interrupt                                                     */
-  COMP_IRQn                           = 21,     /*!< COMP1 and COMP2 Interrupts                                        */
-  EXTI9_5_IRQn                        = 22,     /*!< EXTI Lines [9:5] Interrupt                                        */
-  TIM1_BRK_IRQn                       = 23,     /*!< TIM1 Break Interrupt                                              */
-  TIM1_UP_IRQn                        = 24,     /*!< TIM1 Update Interrupt                                             */
-  TIM1_TRG_COM_IRQn                   = 25,     /*!< TIM1 Trigger and Communication Interrupts                         */
-  TIM1_CC_IRQn                        = 26,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                           = 27,     /*!< TIM2 Global Interrupt                                             */
-  TIM16_IRQn                          = 28,     /*!< TIM16 Global Interrupt                                            */
-  TIM17_IRQn                          = 29,     /*!< TIM17 Global Interrupt                                            */
-  I2C1_EV_IRQn                        = 30,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                        = 31,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                        = 32,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                        = 33,     /*!< I2C2 Error Interrupt                                              */
-  SPI1_IRQn                           = 34,     /*!< SPI1 Interrupt                                                    */
-  SPI2_IRQn                           = 35,     /*!< SPI2 Interrupt                                                    */
-  USART1_IRQn                         = 36,     /*!< USART1 Interrupt                                                  */
-  USART2_IRQn                         = 37,     /*!< USART2 Interrupt                                                  */
-  LPUART1_IRQn                        = 38,     /*!< LPUART1 Interrupt                                                 */
-  LPTIM1_IRQn                         = 39,     /*!< LPTIM1 Global Interrupt                                           */
-  LPTIM2_IRQn                         = 40,     /*!< LPTIM2 Global Interrupt                                           */
-  EXTI15_10_IRQn                      = 41,     /*!< EXTI Lines [15:10] Interrupt                                      */
-  RTC_Alarm_IRQn                      = 42,     /*!< RTC Alarms (A and B) Interrupt                                    */
-  LPTIM3_IRQn                         = 43,     /*!< LPTIM3 Global Interrupt                                           */
-  SUBGHZSPI_IRQn                      = 44,     /*!< SUBGHZSPI Interrupt                                               */
-  HSEM_IRQn                           = 47,     /*!< HSEM Interrupt                                                    */
-  I2C3_EV_IRQn                        = 48,     /*!< I2C3 Event Interrupt                                              */
-  I2C3_ER_IRQn                        = 49,     /*!< I2C3 Error Interrupt                                              */
-  SUBGHZ_Radio_IRQn                   = 50,     /*!< SUBGHZ Radio Interrupt                                            */
-  AES_IRQn                            = 51,     /*!< AES Interrupt                                                     */
-  RNG_IRQn                            = 52,     /*!< RNG Interrupt                                                     */
-  PKA_IRQn                            = 53,     /*!< PKA Interrupt                                                     */
-  DMA2_Channel1_IRQn                  = 54,     /*!< DMA2 Channel 1 Interrupt                                          */
-  DMA2_Channel2_IRQn                  = 55,     /*!< DMA2 Channel 2 Interrupt                                          */
-  DMA2_Channel3_IRQn                  = 56,     /*!< DMA2 Channel 3 Interrupt                                          */
-  DMA2_Channel4_IRQn                  = 57,     /*!< DMA2 Channel 4 Interrupt                                          */
-  DMA2_Channel5_IRQn                  = 58,     /*!< DMA2 Channel 5 Interrupt                                          */
-  DMA2_Channel6_IRQn                  = 59,     /*!< DMA2 Channel 6 Interrupt                                          */
-  DMA2_Channel7_IRQn                  = 60,     /*!< DMA2 Channel 7 Interrupt                                          */
-  DMAMUX1_OVR_IRQn                    = 61      /*!< DMAMUX1 overrun Interrupt                                         */
-} IRQn_Type;
-/**
-  * @}
-  */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
-  */
-#define __CM4_REV                 1U /*!< Core Revision r0p1                            */
-#define __MPU_PRESENT             1U /*!< M4 provides an MPU                            */
-#define __VTOR_PRESENT            1U /*!< Vector Table Register supported               */
-#define __NVIC_PRIO_BITS          4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             0U /*!< FPU not present                                   */
-
-#include "core_cm4.h"                /* Cortex-M4 processor and core peripherals */
-
-
-#include "system_stm32wlxx.h"
-#include <stdint.h>
-
-/**
-  * @}
-  */
-
-
-
-
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */
-
-/**
-  * @brief Analog to Digital Converter
-  */
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
-  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
-  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC configuration register 1,                  Address offset: 0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR;         /*!< ADC sampling time register,                    Address offset: 0x14 */
-       uint32_t RESERVED1;    /*!< Reserved,                                                      0x18 */
-       uint32_t RESERVED2;    /*!< Reserved,                                                      0x1C */
-  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
-  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC group regular sequencer register,          Address offset: 0x28 */
-  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x2C */
-       uint32_t RESERVED3[4]; /*!< Reserved,                                               0x30 - 0x3C */
-  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
-       uint32_t RESERVED4[23];/*!< Reserved,                                               0x44 - 0x9C */
-  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
-  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 configuration register,  Address offset: 0xA4 */
-       uint32_t RESERVED5[3]; /*!< Reserved,                                               0xA8 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC Calibration factor register,               Address offset: 0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/**
-  * @brief AES hardware accelerator
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;          /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;        /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;       /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;       /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;       /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;       /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;       /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;        /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;        /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;        /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;        /*!< AES initialization vector register 3,        Address offset: 0x2C */
-  __IO uint32_t KEYR4;       /*!< AES key register 4,                          Address offset: 0x30 */
-  __IO uint32_t KEYR5;       /*!< AES key register 5,                          Address offset: 0x34 */
-  __IO uint32_t KEYR6;       /*!< AES key register 6,                          Address offset: 0x38 */
-  __IO uint32_t KEYR7;       /*!< AES key register 7,                          Address offset: 0x3C */
-  __IO uint32_t SUSP0R;      /*!< AES Suspend register 0,                      Address offset: 0x40 */
-  __IO uint32_t SUSP1R;      /*!< AES Suspend register 1,                      Address offset: 0x44 */
-  __IO uint32_t SUSP2R;      /*!< AES Suspend register 2,                      Address offset: 0x48 */
-  __IO uint32_t SUSP3R;      /*!< AES Suspend register 3,                      Address offset: 0x4C */
-  __IO uint32_t SUSP4R;      /*!< AES Suspend register 4,                      Address offset: 0x50 */
-  __IO uint32_t SUSP5R;      /*!< AES Suspend register 5,                      Address offset: 0x54 */
-  __IO uint32_t SUSP6R;      /*!< AES Suspend register 6,                      Address offset: 0x58 */
-  __IO uint32_t SUSP7R;      /*!< AES Suspend register 7,                      Address offset: 0x6C */
-} AES_TypeDef;
-
-/**
-  * @brief Comparator
-  */
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register,               Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/**
-  * @brief CRC calculation unit
-  */
-typedef struct
-{
-  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
-  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
-       uint32_t RESERVED2;   /*!< Reserved,                                                    0x0C */
-  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
-  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Digital to Analog Converter
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-       uint32_t RESERVED1;   /*!< Reserved                                                 Address offset: 0x14 */
-       uint32_t RESERVED2;   /*!< Reserved                                                 Address offset: 0x18 */
-       uint32_t RESERVED3;   /*!< Reserved                                                 Address offset: 0x1C */
-  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-       uint32_t RESERVED4;   /*!< Reserved                                                 Address offset: 0x30 */
-  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
-  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
-  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
-  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
-       uint32_t RESERVED5;   /*!< Reserved                                                 Address offset: 0x44 */
-  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
-  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
-} DAC_TypeDef;
-
-/**
-  * @brief Debug MCU
-  */
-typedef struct
-{
-  __IO uint32_t IDCODE;      /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;          /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  uint32_t RESERVED1[13];    /*!< Reserved,                                               0x08-0x38 */
-  __IO uint32_t APB1FZR1;    /*!< Debug MCU CPU1 APB1 freeze register,         Address offset: 0x3C */
-  uint32_t RESERVED2;        /*!< Reserved,                                    Address offset: 0x40 */
-  __IO uint32_t APB1FZR2;    /*!< Debug MCU CPU1 APB1 freeze register,         Address offset: 0x44 */
-  uint32_t RESERVED3;        /*!< Reserved,                                    Address offset: 0x48 */
-  __IO uint32_t APB2FZR;     /*!< Debug MCU CPU1 APB2 freeze register,         Address offset: 0x4C */
-} DBGMCU_TypeDef;
-
-/**
-  * @brief DMA Controller
-  */
-typedef struct
-{
-  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
-  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
-} DMA_TypeDef;
-
-/**
-  * @brief DMA Multiplexer
-  */
-typedef struct
-{
-  __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
-}DMAMUX_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t   CSR;       /*!< DMA Channel Status Register                    Address offset: 0x0080   */
-  __IO uint32_t   CFR;       /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
-}DMAMUX_ChannelStatus_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
-}DMAMUX_RequestGen_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
-  __IO uint32_t   RGCFR;       /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
-}DMAMUX_RequestGenStatus_TypeDef;
-
-/**
-  * @brief Async Interrupts and Events Controller
-  */
-typedef struct
-{
-  __IO uint32_t RTSR1;          /*!< EXTI rising trigger selection register [31:0],            Address offset: 0x00 */
-  __IO uint32_t FTSR1;          /*!< EXTI falling trigger selection register [31:0],           Address offset: 0x04 */
-  __IO uint32_t SWIER1;         /*!< EXTI software interrupt event register [31:0],            Address offset: 0x08 */
-  __IO uint32_t PR1;            /*!< EXTI pending register [31:0],                             Address offset: 0x0C */
-  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                                 Address offset: 0x10 - 0x1C */
-  __IO uint32_t RTSR2;          /*!< EXTI rising trigger selection register [31:0],            Address offset: 0x20 */
-  __IO uint32_t FTSR2;          /*!< EXTI falling trigger selection register [31:0],           Address offset: 0x24 */
-  __IO uint32_t SWIER2;         /*!< EXTI software interrupt event register [31:0],            Address offset: 0x28 */
-  __IO uint32_t PR2;            /*!< EXTI pending register [31:0],                             Address offset: 0x2C */
-  __IO uint32_t RESERVED2[4];   /*!< Reserved,                                                 Address offset: 0x30 - 0x3C */
-  __IO uint32_t RESERVED3[8];   /*!< Reserved,                                                 Address offset: 0x40 - 0x5C */
-  __IO uint32_t RESERVED4[8];   /*!< Reserved,                                                 Address offset: 0x60 - 0x7C */
-  __IO uint32_t IMR1;           /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
-  __IO uint32_t EMR1;           /*!< EXTI wakeup with event mask register for cpu1 [31:0],     Address offset: 0x84 */
-  __IO uint32_t RESERVED5[2];   /*!< Reserved,                                                 Address offset: 0x88 - 0x8C */
-  __IO uint32_t IMR2;           /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
-  __IO uint32_t EMR2;           /*!< EXTI wakeup with event mask register for cpu1 [31:0],     Address offset: 0x94 */
-}EXTI_TypeDef;
-
-/**
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< FLASH Access control register,                      Address offset: 0x00      */
-  uint32_t RESERVED0;          /*!< Reserved,                                           Address offset: 0x04      */
-  __IO uint32_t KEYR;          /*!< FLASH Key register,                                 Address offset: 0x08      */
-  __IO uint32_t OPTKEYR;       /*!< FLASH Option Key register,                          Address offset: 0x0C      */
-  __IO uint32_t SR;            /*!< FLASH Status register,                              Address offset: 0x10      */
-  __IO uint32_t CR;            /*!< FLASH Control register,                             Address offset: 0x14      */
-  __IO uint32_t ECCR;          /*!< FLASH ECC register,                                 Address offset: 0x18      */
-  uint32_t RESERVED1;          /*!< Reserved,                                           Address offset: 0x1C      */
-  __IO uint32_t OPTR;          /*!< FLASH Option register,                              Address offset: 0x20      */
-  __IO uint32_t PCROP1ASR;     /*!< FLASH Bank 1 PCROP area A Start address register,   Address offset: 0x24      */
-  __IO uint32_t PCROP1AER;     /*!< FLASH Bank 1 PCROP area A End address register,     Address offset: 0x28      */
-  __IO uint32_t WRP1AR;        /*!< FLASH Bank 1 WRP area A address register,           Address offset: 0x2C      */
-  __IO uint32_t WRP1BR;        /*!< FLASH Bank 1 WRP area B address register,           Address offset: 0x30      */
-  __IO uint32_t PCROP1BSR;     /*!< FLASH Bank 1 PCROP area B Start address register,   Address offset: 0x34      */
-  __IO uint32_t PCROP1BER;     /*!< FLASH Bank 1 PCROP area B End address register,     Address offset: 0x38      */
-} FLASH_TypeDef;
-
-/**
-  * @brief General Purpose I/O
-  */
-typedef struct
-{
-  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
-  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/**
-  * @brief HW Semaphore HSEM
-  */
-typedef struct
-{
-  __IO uint32_t R[16];      /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-3Ch  */
-   uint32_t  Reserved1[16]; /*!< Reserved                                        Address offset: 40h-7Ch  */
-  __IO uint32_t RLR[16];    /*!< HSEM 1-step read lock registers,                Address offset: 80h-BCh  */
-   uint32_t  Reserved2[16]; /*!< Reserved                                        Address offset: C0h-FCh  */
-  __IO uint32_t C1IER;      /*!< HSEM CPU1 interrupt enable register ,           Address offset: 100h     */
-  __IO uint32_t C1ICR;      /*!< HSEM CPU1 interrupt clear register ,            Address offset: 104h     */
-  __IO uint32_t C1ISR;      /*!< HSEM CPU1 interrupt status register ,           Address offset: 108h     */
-  __IO uint32_t C1MISR;     /*!< HSEM CPU1 masked interrupt status register ,    Address offset: 10Ch     */
-   uint32_t  Reserved[12];  /*!< Reserved                                        Address offset: 110h-13Ch*/
-  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                 Address offset: 140h     */
-  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,             Address offset: 144h     */
-} HSEM_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */
-  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */
-  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */
-  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */
-} HSEM_Common_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
-} I2C_TypeDef;
-
-/**
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/**
-  * @brief LPTIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
-  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
-  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
-  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
-  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
-  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
-  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
-  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
-  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
-  __IO uint32_t RESERVED;    /*!< Reserved,                                           Address offset: 0x24 */
-  __IO uint32_t RCR;         /*!< LPTIM repetition register,                          Address offset: 0x28 */
-} LPTIM_TypeDef;
-
-/**
-  * @brief Public Key Accelerator (PKA)
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< PKA control register,                 Address offset: 0x00 */
-  __IO uint32_t SR;          /*!< PKA status register,                  Address offset: 0x04 */
-  __IO uint32_t CLRFR;       /*!< PKA clear flag register,              Address offset: 0x08 */
-  uint32_t  Reserved1[253];  /*!< Reserved                              Address offset: 0x000C-0x03FC*/
-  __IO uint32_t RAM[894];    /*!< PKA RAM,                              Address offset: 0x0400-0x11F4 */
-} PKA_TypeDef;
-
-/**
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< PWR Power Control Register 1,                     Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< PWR Power Control Register 2,                     Address offset: 0x04 */
-  __IO uint32_t CR3;          /*!< PWR Power Control Register 3,                     Address offset: 0x08 */
-  __IO uint32_t CR4;          /*!< PWR Power Control Register 4,                     Address offset: 0x0C */
-  __IO uint32_t SR1;          /*!< PWR Power Status Register 1,                      Address offset: 0x10 */
-  __IO uint32_t SR2;          /*!< PWR Power Status Register 2,                      Address offset: 0x14 */
-  __IO uint32_t SCR;          /*!< PWR Power Status Reset Register,                  Address offset: 0x18 */
-  __IO uint32_t CR5;          /*!< PWR Power Control Register 5,                     Address offset: 0x1C */
-  __IO uint32_t PUCRA;        /*!< PWR Pull-Up Control Register of port A,           Address offset: 0x20 */
-  __IO uint32_t PDCRA;        /*!< PWR Pull-Down Control Register of port A,         Address offset: 0x24 */
-  __IO uint32_t PUCRB;        /*!< PWR Pull-Up Control Register of port B,           Address offset: 0x28 */
-  __IO uint32_t PDCRB;        /*!< PWR Pull-Down Control Register of port B,         Address offset: 0x2C */
-  __IO uint32_t PUCRC;        /*!< PWR Pull-Up Control Register of port C,           Address offset: 0x30 */
-  __IO uint32_t PDCRC;        /*!< PWR Pull-Down Control Register of port C,         Address offset: 0x34 */
-       uint32_t RESERVED0[8]; /*!< Reserved,                                         Address offset: 0x38-0x54 */
-  __IO uint32_t PUCRH;        /*!< PWR Pull-Up Control Register of port H,           Address offset: 0x58 */
-  __IO uint32_t PDCRH;        /*!< PWR Pull-Down Control Register of port H,         Address offset: 0x5C */
-       uint32_t RESERVED1[10];/*!< Reserved,                                         Address offset: 0x60-0x84 */
-  __IO uint32_t EXTSCR;       /*!< PWR Power Status Reset Register for CPU2,         Address offset: 0x88 */
-       uint32_t RESERVED2;    /*!< Reserved,                                         Address offset: 0x8C */
-  __IO uint32_t SUBGHZSPICR;  /*!< PWR SUBGHZSPI Control Register,                   Address offset: 0x90 */
-} PWR_TypeDef;
-
-/**
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;           /*!< RCC clock  Control Register,                                                    Address offset: 0x00 */
-  __IO uint32_t ICSCR;        /*!< RCC Internal Clock Sources Calibration Register,                                Address offset: 0x04 */
-  __IO uint32_t CFGR;         /*!< RCC Clocks Configuration Register,                                              Address offset: 0x08 */
-  __IO uint32_t PLLCFGR;      /*!< RCC System PLL configuration Register,                                          Address offset: 0x0C */
-uint32_t RESERVED0;           /*!< Reserved,                                                                       Address offset: 0x10 */
-uint32_t RESERVED1;           /*!< Reserved,                                                                       Address offset: 0x14 */
-  __IO uint32_t CIER;         /*!< RCC Clock Interrupt Enable Register,                                            Address offset: 0x18 */
-  __IO uint32_t CIFR;         /*!< RCC Clock Interrupt Flag Register,                                              Address offset: 0x1C */
-  __IO uint32_t CICR;         /*!< RCC Clock Interrupt Clear Register,                                             Address offset: 0x20 */
-uint32_t RESERVED2;           /*!< Reserved,                                                                       Address offset: 0x24 */
-  __IO uint32_t AHB1RSTR;     /*!< RCC AHB1 peripheral reset register,                                             Address offset: 0x28 */
-  __IO uint32_t AHB2RSTR;     /*!< RCC AHB2 peripheral reset register,                                             Address offset: 0x2C */
-  __IO uint32_t AHB3RSTR;     /*!< RCC AHB3 peripheral reset register,                                             Address offset: 0x30 */
-uint32_t RESERVED3;           /*!< Reserved,                                                                       Address offset: 0x34 */
-  __IO uint32_t APB1RSTR1;    /*!< RCC APB1 peripheral reset register 1,                                           Address offset: 0x38 */
-  __IO uint32_t APB1RSTR2;    /*!< RCC APB1 peripheral reset register 2,                                           Address offset: 0x3C */
-  __IO uint32_t APB2RSTR;     /*!< RCC APB2 peripheral reset register,                                             Address offset: 0x40 */
-  __IO uint32_t APB3RSTR;     /*!< RCC APB3 peripheral reset register,                                             Address offset: 0x44 */
-  __IO uint32_t AHB1ENR;      /*!< RCC AHB1 peripheral clocks enable register,                                     Address offset: 0x48 */
-  __IO uint32_t AHB2ENR;      /*!< RCC AHB2 peripheral clocks enable register,                                     Address offset: 0x4C */
-  __IO uint32_t AHB3ENR;      /*!< RCC AHB3 peripheral clocks enable register,                                     Address offset: 0x50 */
-uint32_t RESERVED4;           /*!< Reserved,                                                                       Address offset: 0x54 */
-  __IO uint32_t APB1ENR1;     /*!< RCC APB1 peripheral clocks enable register 1,                                   Address offset: 0x58 */
-  __IO uint32_t APB1ENR2;     /*!< RCC APB1 peripheral clocks enable register 2,                                   Address offset: 0x5C */
-  __IO uint32_t APB2ENR;      /*!< RCC APB2 peripheral clocks enable register,                                     Address offset: 0x60 */
-  __IO uint32_t APB3ENR;      /*!< RCC APB3 peripheral clocks enable register,                                     Address offset: 0x64 */
-  __IO uint32_t AHB1SMENR;    /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,             Address offset: 0x68 */
-  __IO uint32_t AHB2SMENR;    /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,             Address offset: 0x6C */
-  __IO uint32_t AHB3SMENR;    /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
-uint32_t RESERVED5;           /*!< Reserved,                                                                       Address offset: 0x74 */
-  __IO uint32_t APB1SMENR1;   /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1,      Address offset: 0x78 */
-  __IO uint32_t APB1SMENR2;   /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2,      Address offset: 0x7C */
-  __IO uint32_t APB2SMENR;    /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register,        Address offset: 0x80 */
-  __IO uint32_t APB3SMENR;    /*!< RCC APB3 peripheral clocks enable in sleep mode and stop modes register,        Address offset: 0x84 */
-  __IO uint32_t CCIPR;        /*!< RCC Peripherals Clock Configuration Independent Register,                       Address offset: 0x88 */
-uint32_t RESERVED6;           /*!< Reserved,                                                                       Address offset: 0x8C */
-  __IO uint32_t BDCR;         /*!< RCC Backup Domain Control Register,                                             Address offset: 0x90 */
-  __IO uint32_t CSR;          /*!< RCC Control and Status Register,                                                Address offset: 0x94 */
-uint32_t RESERVED7[28];       /*!< Reserved,                                                                       Address offset: 0x98-0x104 */
-  __IO uint32_t EXTCFGR;      /*!< RCC Extended Clock Recovery Register,                                           Address offset: 0x108 */
-} RCC_TypeDef;
-
-/**
-  * @brief RNG
-  */
-typedef struct
-{
-  __IO uint32_t CR;        /*!< RNG control register,             Address offset: 0x00 */
-  __IO uint32_t SR;        /*!< RNG status register,              Address offset: 0x04 */
-  __IO uint32_t DR;        /*!< RNG data register,                Address offset: 0x08 */
-  uint32_t      RESERVED0; /*!< Reserved,                         Address offset: 0x0C */
-  __IO uint32_t HTCR;      /*!< RNG health test control register, Address offset: 0x10 */
-} RNG_TypeDef;
-
-/**
-  * @brief RTC Specific device feature definitions
-  */
-#define RTC_BACKUP_NB       20u
-#define RTC_TAMP_NB         3u
-
-/**
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
-  __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
-  __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
-  __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
-  __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
-  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
-  __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
-       uint32_t RESERVED0;   /*!< Reserved,                                       Address offset: 0x1C */
-       uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x20 */
-  __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
-  __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
-  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
-  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
-  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
-  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
-       uint32_t RESERVED2;   /*!< Reserved,                                       Address offset: 0x3C */
-  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
-  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
-  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
-  __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
-  __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
-       uint32_t RESERVED3;   /*!< Reserved,                                       Address offset: 0x58 */
-  __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
-       uint32_t RESERVED4[4];/*!< Reserved,                                       Address offset: 0x58 */
-  __IO uint32_t ALRABINR;/*!< RTC alarm A binary mode register,                   Address offset: 0x70 */
-  __IO uint32_t ALRBBINR;/*!< RTC alarm B binary mode register,                   Address offset: 0x74 */
-} RTC_TypeDef;
-
-/**
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/**
-  * @brief System configuration controller
-  */
-typedef struct
-{
-  __IO uint32_t MEMRMP;            /*!< SYSCFG memory remap register                                            Address offset: 0x00       */
-  __IO uint32_t CFGR1;             /*!< SYSCFG configuration register 1,                                        Address offset: 0x04       */
-  __IO uint32_t EXTICR[4];         /*!< SYSCFG external interrupt configuration registers,                      Address offset: 0x08-0x14  */
-  __IO uint32_t SCSR;              /*!< SYSCFG SRAM2 control and status register,                               Address offset: 0x18       */
-  __IO uint32_t CFGR2;             /*!< SYSCFG configuration register 2,                                        Address offset: 0x1C       */
-  __IO uint32_t SWPR;              /*!< SYSCFG SRAM2 write protection register part,                            Address offset: 0x20       */
-  __IO uint32_t SKR;               /*!< SYSCFG SRAM2 key register,                                              Address offset: 0x24       */
-       uint32_t RESERVED1[120];    /*!< Reserved,                                                               Address offset: 0x28-0x204 */
-  __IO uint32_t RFDCR;             /*!< SYSCFG CPU2 radio debug control register,                               Address offset: 0x208      */
-} SYSCFG_TypeDef;
-
-/**
-  * @brief Tamper and backup registers
-  */
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TAMP configuration register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TAMP configuration register 2,            Address offset: 0x04 */
-  __IO uint32_t CR3;         /*!< TAMP configuration register 3,            Address offset: 0x08 */
-  __IO uint32_t FLTCR;       /*!< TAMP filter control register,             Address offset: 0x0C */
-       uint32_t RESERVED0[7];/*!< Reserved,                                 Address offset: 0x10 */
-  __IO uint32_t IER;         /*!< TAMP interrupt enable register,           Address offset: 0x2C */
-  __IO uint32_t SR;          /*!< TAMP status register,                     Address offset: 0x30 */
-  __IO uint32_t MISR;        /*!< TAMP masked interrupt status register,    Address offset: 0x34 */
-       uint32_t RESERVED1;   /*!< Reserved,                                 Address offset: 0x38 */
-  __IO uint32_t SCR;         /*!< TAMP status clear register,               Address offset: 0x3C */
-  __IO uint32_t COUNTR;      /*!< TAMP monotonic counter register,          Address offset: 0x40 */
-       uint32_t RESERVED2[47];/*!< Reserved,                                Address offset: 0x54 -- 0xFC */
-  __IO uint32_t BKP0R;       /*!< TAMP backup register 0,                   Address offset: 0x100 */
-  __IO uint32_t BKP1R;       /*!< TAMP backup register 1,                   Address offset: 0x104 */
-  __IO uint32_t BKP2R;       /*!< TAMP backup register 2,                   Address offset: 0x108 */
-  __IO uint32_t BKP3R;       /*!< TAMP backup register 3,                   Address offset: 0x10C */
-  __IO uint32_t BKP4R;       /*!< TAMP backup register 4,                   Address offset: 0x110 */
-  __IO uint32_t BKP5R;       /*!< TAMP backup register 5,                   Address offset: 0x114 */
-  __IO uint32_t BKP6R;       /*!< TAMP backup register 6,                   Address offset: 0x118 */
-  __IO uint32_t BKP7R;       /*!< TAMP backup register 7,                   Address offset: 0x11C */
-  __IO uint32_t BKP8R;       /*!< TAMP backup register 8,                   Address offset: 0x120 */
-  __IO uint32_t BKP9R;       /*!< TAMP backup register 9,                   Address offset: 0x124 */
-  __IO uint32_t BKP10R;      /*!< TAMP backup register 10,                  Address offset: 0x128 */
-  __IO uint32_t BKP11R;      /*!< TAMP backup register 11,                  Address offset: 0x12C */
-  __IO uint32_t BKP12R;      /*!< TAMP backup register 12,                  Address offset: 0x130 */
-  __IO uint32_t BKP13R;      /*!< TAMP backup register 13,                  Address offset: 0x134 */
-  __IO uint32_t BKP14R;      /*!< TAMP backup register 14,                  Address offset: 0x138 */
-  __IO uint32_t BKP15R;      /*!< TAMP backup register 15,                  Address offset: 0x13C */
-  __IO uint32_t BKP16R;      /*!< TAMP backup register 16,                  Address offset: 0x140 */
-  __IO uint32_t BKP17R;      /*!< TAMP backup register 17,                  Address offset: 0x144 */
-  __IO uint32_t BKP18R;      /*!< TAMP backup register 18,                  Address offset: 0x148 */
-  __IO uint32_t BKP19R;      /*!< TAMP backup register 19,                  Address offset: 0x14C */
-} TAMP_TypeDef;
-
-/**
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler register,                   Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
-  __IO uint32_t OR1;         /*!< TIM option register                       Address offset: 0x50 */
-  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
-  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
-  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
-  __IO uint32_t AF1;         /*!< TIM Alternate function option register 1, Address offset: 0x60 */
-  __IO uint32_t AF2;         /*!< TIM Alternate function option register 2, Address offset: 0x64 */
-} TIM_TypeDef;
-
-/**
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;               /*!< USART Control register 1,                 Address offset: 0x00  */
-  __IO uint32_t CR2;               /*!< USART Control register 2,                 Address offset: 0x04  */
-  __IO uint32_t CR3;               /*!< USART Control register 3,                 Address offset: 0x08  */
-  __IO uint32_t BRR;               /*!< USART Baud rate register,                 Address offset: 0x0C  */
-  __IO uint32_t GTPR;              /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
-  __IO uint32_t RTOR;              /*!< USART Receiver Time Out register,         Address offset: 0x14  */
-  __IO uint32_t RQR;               /*!< USART Request register,                   Address offset: 0x18  */
-  __IO uint32_t ISR;               /*!< USART Interrupt and status register,      Address offset: 0x1C  */
-  __IO uint32_t ICR;               /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
-  __IO uint32_t RDR;               /*!< USART Receive Data register,              Address offset: 0x24  */
-  __IO uint32_t TDR;               /*!< USART Transmit Data register,             Address offset: 0x28  */
-  __IO uint32_t PRESC;             /*!< USART Prescaler register,                 Address offset: 0x2C  */
-} USART_TypeDef;
-
-/**
-  * @brief VREFBUF
-  */
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
-  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
-} VREFBUF_TypeDef;
-
-/**
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-/*!< Boundary memory map */
-#define FLASH_BASE              0x08000000UL   /*!< FLASH(up to 256 KB) base address */
-#define SYSTEM_FLASH_BASE       0x1FFF0000UL   /*!< System FLASH(28Kb) base address */
-#define SRAM1_BASE              0x20000000UL   /*!< SRAM1(up to 32 KB) base address */
-#define SRAM2_BASE              0x20008000UL   /*!< SRAM2(up to 32 KB) base address */
-#define PERIPH_BASE             0x40000000UL   /*!< Peripheral base address */
-
-#define FLASH_SIZE              (((*((uint32_t *)FLASHSIZE_BASE)) & 0xFFFFU) << 10U)
-#define SRAM1_SIZE              0x00008000UL   /*!< SRAM1 default size : 32 kB */
-#define SRAM2_SIZE              0x00008000UL   /*!< SRAM2 default size : 32 kB  */
-
-/*!< Memory, OTP and Option bytes */
-#define OTP_AREA_BASE           (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 – 0x1FFF73FF)      */
-#define ENGI_BYTES_BASE         (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 – 0x1FFF77FF)    */
-#define OPTION_BYTES_BASE       (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 – 0x1FFF7FFF)  */
-
-/*!< Device Electronic Signature */
-#define PACKAGE_BASE            (ENGI_BYTES_BASE + 0x00000100UL) /*!< Package data register base address     */
-#define UID64_BASE              (ENGI_BYTES_BASE + 0x00000180UL) /*!< 64-bit Unique device Identification    */
-#define UID_BASE                (ENGI_BYTES_BASE + 0x00000190UL) /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE          (ENGI_BYTES_BASE + 0x000001E0UL) /*!< Flash size data register base address  */
-
-#define SYSTEM_MEMORY_END_ADDR  (0x1FFF6FFFUL)   /*!< System Memory : 28KB (0x1FFF0000 – 0x1FFF6FFF)  */
-#define OTP_AREA_END_ADDR       (0x1FFF73FFUL)   /*!< OTP area : 1KB (0x1FFF7000 – 0x1FFF73FF)        */
-#define ENGI_BYTE_END_ADDR      (0x1FFF77FFUL)   /*!< Engi Bytes : 1kB (0x1FFF7400 – 0x1FFF77FF)      */
-#define OPTION_BYTE_END_ADDR    (0x1FFF7FFFUL)   /*!< Option Bytes : 2KB (0x1FFF7800 – 0x1FFF7FFF)    */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE         PERIPH_BASE
-#define APB2PERIPH_BASE         (PERIPH_BASE + 0x00010000UL)
-#define AHB1PERIPH_BASE         (PERIPH_BASE + 0x00020000UL)
-#define AHB2PERIPH_BASE         (PERIPH_BASE + 0x08000000UL)
-#define AHB3PERIPH_BASE         (PERIPH_BASE + 0x18000000UL)
-#define APB3PERIPH_BASE         (PERIPH_BASE + 0x18010000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE               (APB1PERIPH_BASE + 0x00000000UL)
-#define RTC_BASE                (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE               (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE               (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE               (APB1PERIPH_BASE + 0x00003800UL)
-#define USART2_BASE             (APB1PERIPH_BASE + 0x00004400UL)
-#define I2C1_BASE               (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE               (APB1PERIPH_BASE + 0x00005800UL)
-#define I2C3_BASE               (APB1PERIPH_BASE + 0x00005C00UL)
-#define DAC_BASE                (APB1PERIPH_BASE + 0x00007400UL)
-#define LPTIM1_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define LPUART1_BASE            (APB1PERIPH_BASE + 0x00008000UL)
-#define LPTIM2_BASE             (APB1PERIPH_BASE + 0x00009400UL)
-#define LPTIM3_BASE             (APB1PERIPH_BASE + 0x00009800UL)
-#define TAMP_BASE               (APB1PERIPH_BASE + 0x0000B000UL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE             (APB2PERIPH_BASE + 0x00000000UL)
-#define VREFBUF_BASE            (APB2PERIPH_BASE + 0x00000030UL)
-#define COMP1_BASE              (APB2PERIPH_BASE + 0x00000200UL)
-#define COMP2_BASE              (APB2PERIPH_BASE + 0x00000204UL)
-#define ADC_BASE                (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_COMMON_BASE         (APB2PERIPH_BASE + 0x00002708UL)
-#define TIM1_BASE               (APB2PERIPH_BASE + 0x00002C00UL)
-#define SPI1_BASE               (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE             (APB2PERIPH_BASE + 0x00003800UL)
-#define TIM16_BASE              (APB2PERIPH_BASE + 0x00004400UL)
-#define TIM17_BASE              (APB2PERIPH_BASE + 0x00004800UL)
-
-/*!< AHB1 peripherals */
-#define DMA1_BASE               (AHB1PERIPH_BASE + 0x00000000UL)
-#define DMA2_BASE               (AHB1PERIPH_BASE + 0x00000400UL)
-#define DMAMUX1_BASE            (AHB1PERIPH_BASE + 0x00000800UL)
-#define CRC_BASE                (AHB1PERIPH_BASE + 0x00003000UL)
-
-#define DMA1_Channel1_BASE       (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE       (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE       (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE       (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE       (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE       (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE       (DMA1_BASE + 0x00000080UL)
-
-#define DMA2_Channel1_BASE       (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE       (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE       (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE       (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE       (DMA2_BASE + 0x00000058UL)
-#define DMA2_Channel6_BASE       (DMA2_BASE + 0x0000006CUL)
-#define DMA2_Channel7_BASE       (DMA2_BASE + 0x00000080UL)
-
-#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
-#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x00000004UL)
-#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x00000008UL)
-#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x0000000CUL)
-#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x00000010UL)
-#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x00000014UL)
-#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x00000018UL)
-#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x0000001CUL)
-#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x00000020UL)
-#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x00000024UL)
-#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x00000028UL)
-#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x0000002CUL)
-#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x00000030UL)
-#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x00000034UL)
-
-#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x00000100UL)
-#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x00000104UL)
-#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x00000108UL)
-#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x0000010CUL)
-
-#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x00000080UL)
-#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x00000140UL)
-
-/*!< AHB2 peripherals */
-#define IOPORT_BASE             (AHB2PERIPH_BASE + 0x00000000UL)
-#define GPIOA_BASE              (IOPORT_BASE + 0x00000000UL)
-#define GPIOB_BASE              (IOPORT_BASE + 0x00000400UL)
-#define GPIOC_BASE              (IOPORT_BASE + 0x00000800UL)
-#define GPIOH_BASE              (IOPORT_BASE + 0x00001C00UL)
-
-/*!< AHB3 peripherals */
-#define PWR_BASE                (AHB3PERIPH_BASE + 0x00000400UL)
-#define EXTI_BASE               (AHB3PERIPH_BASE + 0x00000800UL)
-#define RCC_BASE                (AHB3PERIPH_BASE + 0x00000000UL)
-#define RNG_BASE                (AHB3PERIPH_BASE + 0x00001000UL)
-#define HSEM_BASE               (AHB3PERIPH_BASE + 0x00001400UL)
-#define AES_BASE                (AHB3PERIPH_BASE + 0x00001800UL)
-#define PKA_BASE                (AHB3PERIPH_BASE + 0x00002000UL)
-#define FLASH_REG_BASE          (AHB3PERIPH_BASE + 0x00004000UL)
-
-/*!< APB3 peripherals */
-#define SUBGHZSPI_BASE          (APB3PERIPH_BASE + 0x00000000UL)
-
-/*!< Peripherals available on CPU1 external PPB bus */
-#define DBGMCU_BASE             (0xE0042000UL)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_declaration
-  * @{
-  */
-
-/* Peripherals available on APB1 bus */
-#define TIM2                    ((TIM_TypeDef *) TIM2_BASE)
-#define IWDG                    ((IWDG_TypeDef *) IWDG_BASE)
-#define WWDG                    ((WWDG_TypeDef *) WWDG_BASE)
-#define DAC                     ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1                  ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define LPTIM2                  ((LPTIM_TypeDef *) LPTIM2_BASE)
-#define LPTIM3                  ((LPTIM_TypeDef *) LPTIM3_BASE)
-#define RTC                     ((RTC_TypeDef *) RTC_BASE)
-#define SPI2                    ((SPI_TypeDef *) SPI2_BASE)
-#define I2C1                    ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                    ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                    ((I2C_TypeDef *) I2C3_BASE)
-#define TAMP                    ((TAMP_TypeDef *) TAMP_BASE)
-#define USART2                  ((USART_TypeDef *) USART2_BASE)
-#define LPUART1                 ((USART_TypeDef *) LPUART1_BASE)
-
-/* Peripherals available on APB2 bus */
-#define SYSCFG                  ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define VREFBUF                 ((VREFBUF_TypeDef *) VREFBUF_BASE)
-#define COMP1                   ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2                   ((COMP_TypeDef *) COMP2_BASE)
-#define COMP12_COMMON           ((COMP_Common_TypeDef *) COMP2_BASE)
-#define TIM1                    ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1                    ((SPI_TypeDef *) SPI1_BASE)
-#define ADC                     ((ADC_TypeDef *) ADC_BASE)
-#define ADC_COMMON              ((ADC_Common_TypeDef *) ADC_COMMON_BASE)
-#define TIM16                   ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17                   ((TIM_TypeDef *) TIM17_BASE)
-#define USART1                  ((USART_TypeDef *) USART1_BASE)
-
-/* Peripherals available on AHB1 bus */
-#define DMA1                    ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1           ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2           ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3           ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4           ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5           ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6           ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7           ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-
-#define DMA2                    ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1           ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2           ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3           ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4           ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5           ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DMA2_Channel6           ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
-#define DMA2_Channel7           ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
-
-#define DMAMUX1                 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
-#define DMAMUX1_Channel0        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
-#define DMAMUX1_Channel1        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
-#define DMAMUX1_Channel2        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
-#define DMAMUX1_Channel3        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
-#define DMAMUX1_Channel4        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
-#define DMAMUX1_Channel5        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
-#define DMAMUX1_Channel6        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
-#define DMAMUX1_Channel7        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
-#define DMAMUX1_Channel8        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
-#define DMAMUX1_Channel9        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
-#define DMAMUX1_Channel10       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
-#define DMAMUX1_Channel11       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
-#define DMAMUX1_Channel12       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
-#define DMAMUX1_Channel13       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
-
-#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
-#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
-#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
-#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
-
-#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
-#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
-
-#define CRC                     ((CRC_TypeDef *) CRC_BASE)
-
-/* Peripherals available on AHB2 bus */
-#define GPIOA                   ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB                   ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC                   ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOH                   ((GPIO_TypeDef *) GPIOH_BASE)
-
-/* Peripherals available on AH3 bus */
-#define AES                     ((AES_TypeDef *) AES_BASE)
-
-#define EXTI                    ((EXTI_TypeDef *) EXTI_BASE)
-#define RCC                     ((RCC_TypeDef *) RCC_BASE)
-#define PWR                     ((PWR_TypeDef *) PWR_BASE)
-#define RNG                     ((RNG_TypeDef *) RNG_BASE)
-#define HSEM                    ((HSEM_TypeDef *) HSEM_BASE)
-#define HSEM_COMMON             ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U))
-#define PKA                     ((PKA_TypeDef *) PKA_BASE)
-#define FLASH                   ((FLASH_TypeDef *) FLASH_REG_BASE)
-
-/* Peripherals available on APB3 bus */
-#define SUBGHZSPI               ((SPI_TypeDef *) SUBGHZSPI_BASE)
-
-/* Peripherals available on CPU1 external PPB bus */
-#define DBGMCU                  ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-/** @addtogroup Hardware_Constant_Definition
-  * @{
-  */
-#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_ISR register  *******************/
-#define ADC_ISR_ADRDY_Pos              (0U)
-#define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
-#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
-#define ADC_ISR_EOSMP_Pos              (1U)
-#define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
-#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
-#define ADC_ISR_EOC_Pos                (2U)
-#define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
-#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
-#define ADC_ISR_EOS_Pos                (3U)
-#define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
-#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
-#define ADC_ISR_OVR_Pos                (4U)
-#define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
-#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
-#define ADC_ISR_AWD1_Pos               (7U)
-#define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
-#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
-#define ADC_ISR_AWD2_Pos               (8U)
-#define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
-#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
-#define ADC_ISR_AWD3_Pos               (9U)
-#define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
-#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
-#define ADC_ISR_EOCAL_Pos              (11U)
-#define ADC_ISR_EOCAL_Msk              (0x1UL << ADC_ISR_EOCAL_Pos)            /*!< 0x00000800 */
-#define ADC_ISR_EOCAL                  ADC_ISR_EOCAL_Msk                       /*!< ADC end of calibration flag */
-#define ADC_ISR_CCRDY_Pos              (13U)
-#define ADC_ISR_CCRDY_Msk              (0x1UL << ADC_ISR_CCRDY_Pos)            /*!< 0x00002000 */
-#define ADC_ISR_CCRDY                  ADC_ISR_CCRDY_Msk                       /*!< ADC channel configuration ready flag */
-
-/********************  Bit definition for ADC_IER register  *******************/
-#define ADC_IER_ADRDYIE_Pos            (0U)
-#define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
-#define ADC_IER_EOSMPIE_Pos            (1U)
-#define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
-#define ADC_IER_EOCIE_Pos              (2U)
-#define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
-#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
-#define ADC_IER_EOSIE_Pos              (3U)
-#define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
-#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
-#define ADC_IER_OVRIE_Pos              (4U)
-#define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
-#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
-#define ADC_IER_AWD1IE_Pos             (7U)
-#define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
-#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
-#define ADC_IER_AWD2IE_Pos             (8U)
-#define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
-#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
-#define ADC_IER_AWD3IE_Pos             (9U)
-#define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
-#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
-#define ADC_IER_EOCALIE_Pos            (11U)
-#define ADC_IER_EOCALIE_Msk            (0x1UL << ADC_IER_EOCALIE_Pos)          /*!< 0x00000800 */
-#define ADC_IER_EOCALIE                ADC_IER_EOCALIE_Msk                     /*!< ADC end of calibration interrupt */
-#define ADC_IER_CCRDYIE_Pos            (13U)
-#define ADC_IER_CCRDYIE_Msk            (0x1UL << ADC_IER_CCRDYIE_Pos)          /*!< 0x00002000 */
-#define ADC_IER_CCRDYIE                ADC_IER_CCRDYIE_Msk                     /*!< ADC channel configuration ready interrupt */
-
-/********************  Bit definition for ADC_CR register  ********************/
-#define ADC_CR_ADEN_Pos                (0U)
-#define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
-#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
-#define ADC_CR_ADDIS_Pos               (1U)
-#define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
-#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
-#define ADC_CR_ADSTART_Pos             (2U)
-#define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
-#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
-#define ADC_CR_ADSTP_Pos               (4U)
-#define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
-#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
-#define ADC_CR_ADVREGEN_Pos            (28U)
-#define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
-#define ADC_CR_ADCAL_Pos               (31U)
-#define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
-#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
-
-/********************  Bit definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_DMAEN_Pos            (0U)
-#define ADC_CFGR1_DMAEN_Msk            (0x1UL << ADC_CFGR1_DMAEN_Pos)          /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN                ADC_CFGR1_DMAEN_Msk                     /*!< ADC DMA transfer enable */
-#define ADC_CFGR1_DMACFG_Pos           (1U)
-#define ADC_CFGR1_DMACFG_Msk           (0x1UL << ADC_CFGR1_DMACFG_Pos)         /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG               ADC_CFGR1_DMACFG_Msk                    /*!< ADC DMA transfer configuration */
-
-#define ADC_CFGR1_SCANDIR_Pos          (2U)
-#define ADC_CFGR1_SCANDIR_Msk          (0x1UL << ADC_CFGR1_SCANDIR_Pos)        /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR              ADC_CFGR1_SCANDIR_Msk                   /*!< ADC group regular sequencer scan direction */
-
-#define ADC_CFGR1_RES_Pos              (3U)
-#define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000018 */
-#define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
-#define ADC_CFGR1_RES_0                (0x1UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1                (0x2UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000010 */
-
-#define ADC_CFGR1_ALIGN_Pos            (5U)
-#define ADC_CFGR1_ALIGN_Msk            (0x1UL << ADC_CFGR1_ALIGN_Pos)          /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN                ADC_CFGR1_ALIGN_Msk                     /*!< ADC data alignement */
-
-#define ADC_CFGR1_EXTSEL_Pos           (6U)
-#define ADC_CFGR1_EXTSEL_Msk           (0x7UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
-#define ADC_CFGR1_EXTSEL_0             (0x1UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1             (0x2UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2             (0x4UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000100 */
-
-#define ADC_CFGR1_EXTEN_Pos            (10U)
-#define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
-#define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */
-
-#define ADC_CFGR1_OVRMOD_Pos           (12U)
-#define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
-#define ADC_CFGR1_CONT_Pos             (13U)
-#define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
-#define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
-#define ADC_CFGR1_WAIT_Pos             (14U)
-#define ADC_CFGR1_WAIT_Msk             (0x1UL << ADC_CFGR1_WAIT_Pos)           /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT                 ADC_CFGR1_WAIT_Msk                      /*!< ADC low power auto wait */
-#define ADC_CFGR1_AUTOFF_Pos           (15U)
-#define ADC_CFGR1_AUTOFF_Msk           (0x1UL << ADC_CFGR1_AUTOFF_Pos)         /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF               ADC_CFGR1_AUTOFF_Msk                    /*!< ADC low power auto power off */
-#define ADC_CFGR1_DISCEN_Pos           (16U)
-#define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CFGR1_CHSELRMOD_Pos        (21U)
-#define ADC_CFGR1_CHSELRMOD_Msk        (0x1UL << ADC_CFGR1_CHSELRMOD_Pos)      /*!< 0x00200000 */
-#define ADC_CFGR1_CHSELRMOD            ADC_CFGR1_CHSELRMOD_Msk                 /*!< ADC group regular sequencer mode */
-
-#define ADC_CFGR1_AWD1SGL_Pos          (22U)
-#define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
-#define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CFGR1_AWD1EN_Pos           (23U)
-#define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
-#define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CFGR1_AWD1CH_Pos           (26U)
-#define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
-#define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
-#define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
-#define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
-#define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
-#define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */
-
-/********************  Bit definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_OVSE_Pos             (0U)
-#define ADC_CFGR2_OVSE_Msk             (0x1UL << ADC_CFGR2_OVSE_Pos)           /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE                 ADC_CFGR2_OVSE_Msk                      /*!< ADC oversampler enable on scope ADC group regular */
-
-#define ADC_CFGR2_OVSR_Pos             (2U)
-#define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
-#define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
-
-#define ADC_CFGR2_OVSS_Pos             (5U)
-#define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
-#define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
-
-#define ADC_CFGR2_TOVS_Pos             (9U)
-#define ADC_CFGR2_TOVS_Msk             (0x1UL << ADC_CFGR2_TOVS_Pos)           /*!< 0x00000200 */
-#define ADC_CFGR2_TOVS                 ADC_CFGR2_TOVS_Msk                      /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
-
-#define ADC_CFGR2_LFTRIG_Pos           (29U)
-#define ADC_CFGR2_LFTRIG_Msk           (0x1UL << ADC_CFGR2_LFTRIG_Pos)         /*!< 0x20000000 */
-#define ADC_CFGR2_LFTRIG               ADC_CFGR2_LFTRIG_Msk                    /*!< ADC low frequency trigger mode */
-
-#define ADC_CFGR2_CKMODE_Pos           (30U)
-#define ADC_CFGR2_CKMODE_Msk           (0x3UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE               ADC_CFGR2_CKMODE_Msk                    /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
-#define ADC_CFGR2_CKMODE_1             (0x2UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x80000000 */
-#define ADC_CFGR2_CKMODE_0             (0x1UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x40000000 */
-
-/********************  Bit definition for ADC_SMPR register  ******************/
-#define ADC_SMPR_SMP1_Pos              (0U)
-#define ADC_SMPR_SMP1_Msk              (0x7UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000007 */
-#define ADC_SMPR_SMP1                  ADC_SMPR_SMP1_Msk                       /*!< ADC group of channels sampling time 1 */
-#define ADC_SMPR_SMP1_0                (0x1UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000001 */
-#define ADC_SMPR_SMP1_1                (0x2UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000002 */
-#define ADC_SMPR_SMP1_2                (0x4UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000004 */
-
-#define ADC_SMPR_SMP2_Pos              (4U)
-#define ADC_SMPR_SMP2_Msk              (0x7UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000070 */
-#define ADC_SMPR_SMP2                  ADC_SMPR_SMP2_Msk                       /*!< ADC group of channels sampling time 2 */
-#define ADC_SMPR_SMP2_0                (0x1UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000010 */
-#define ADC_SMPR_SMP2_1                (0x2UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000020 */
-#define ADC_SMPR_SMP2_2                (0x4UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000040 */
-
-#define ADC_SMPR_SMPSEL_Pos            (8U)
-#define ADC_SMPR_SMPSEL_Msk            (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos)      /*!< 0x03FFFF00 */
-#define ADC_SMPR_SMPSEL                ADC_SMPR_SMPSEL_Msk                     /*!< ADC all channels sampling time selection */
-#define ADC_SMPR_SMPSEL0_Pos           (8U)
-#define ADC_SMPR_SMPSEL0_Msk           (0x1UL << ADC_SMPR_SMPSEL0_Pos)         /*!< 0x00000100 */
-#define ADC_SMPR_SMPSEL0               ADC_SMPR_SMPSEL0_Msk                    /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR_SMPSEL1_Pos           (9U)
-#define ADC_SMPR_SMPSEL1_Msk           (0x1UL << ADC_SMPR_SMPSEL1_Pos)         /*!< 0x00000200 */
-#define ADC_SMPR_SMPSEL1               ADC_SMPR_SMPSEL1_Msk                    /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR_SMPSEL2_Pos           (10U)
-#define ADC_SMPR_SMPSEL2_Msk           (0x1UL << ADC_SMPR_SMPSEL2_Pos)         /*!< 0x00000400 */
-#define ADC_SMPR_SMPSEL2               ADC_SMPR_SMPSEL2_Msk                    /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR_SMPSEL3_Pos           (11U)
-#define ADC_SMPR_SMPSEL3_Msk           (0x1UL << ADC_SMPR_SMPSEL3_Pos)         /*!< 0x00000800 */
-#define ADC_SMPR_SMPSEL3               ADC_SMPR_SMPSEL3_Msk                    /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR_SMPSEL4_Pos           (12U)
-#define ADC_SMPR_SMPSEL4_Msk           (0x1UL << ADC_SMPR_SMPSEL4_Pos)         /*!< 0x00001000 */
-#define ADC_SMPR_SMPSEL4               ADC_SMPR_SMPSEL4_Msk                    /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR_SMPSEL5_Pos           (13U)
-#define ADC_SMPR_SMPSEL5_Msk           (0x1UL << ADC_SMPR_SMPSEL5_Pos)         /*!< 0x00002000 */
-#define ADC_SMPR_SMPSEL5               ADC_SMPR_SMPSEL5_Msk                    /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR_SMPSEL6_Pos           (14U)
-#define ADC_SMPR_SMPSEL6_Msk           (0x1UL << ADC_SMPR_SMPSEL6_Pos)         /*!< 0x00004000 */
-#define ADC_SMPR_SMPSEL6               ADC_SMPR_SMPSEL6_Msk                    /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR_SMPSEL7_Pos           (15U)
-#define ADC_SMPR_SMPSEL7_Msk           (0x1UL << ADC_SMPR_SMPSEL7_Pos)         /*!< 0x00008000 */
-#define ADC_SMPR_SMPSEL7               ADC_SMPR_SMPSEL7_Msk                    /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR_SMPSEL8_Pos           (16U)
-#define ADC_SMPR_SMPSEL8_Msk           (0x1UL << ADC_SMPR_SMPSEL8_Pos)         /*!< 0x00010000 */
-#define ADC_SMPR_SMPSEL8               ADC_SMPR_SMPSEL8_Msk                    /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR_SMPSEL9_Pos           (17U)
-#define ADC_SMPR_SMPSEL9_Msk           (0x1UL << ADC_SMPR_SMPSEL9_Pos)         /*!< 0x00020000 */
-#define ADC_SMPR_SMPSEL9               ADC_SMPR_SMPSEL9_Msk                    /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR_SMPSEL10_Pos          (18U)
-#define ADC_SMPR_SMPSEL10_Msk          (0x1UL << ADC_SMPR_SMPSEL10_Pos)        /*!< 0x00040000 */
-#define ADC_SMPR_SMPSEL10              ADC_SMPR_SMPSEL10_Msk                   /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR_SMPSEL11_Pos          (19U)
-#define ADC_SMPR_SMPSEL11_Msk          (0x1UL << ADC_SMPR_SMPSEL11_Pos)        /*!< 0x00080000 */
-#define ADC_SMPR_SMPSEL11              ADC_SMPR_SMPSEL11_Msk                   /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR_SMPSEL12_Pos          (20U)
-#define ADC_SMPR_SMPSEL12_Msk          (0x1UL << ADC_SMPR_SMPSEL12_Pos)        /*!< 0x00100000 */
-#define ADC_SMPR_SMPSEL12              ADC_SMPR_SMPSEL12_Msk                   /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR_SMPSEL13_Pos          (21U)
-#define ADC_SMPR_SMPSEL13_Msk          (0x1UL << ADC_SMPR_SMPSEL13_Pos)        /*!< 0x00200000 */
-#define ADC_SMPR_SMPSEL13              ADC_SMPR_SMPSEL13_Msk                   /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR_SMPSEL14_Pos          (22U)
-#define ADC_SMPR_SMPSEL14_Msk          (0x1UL << ADC_SMPR_SMPSEL14_Pos)        /*!< 0x00400000 */
-#define ADC_SMPR_SMPSEL14              ADC_SMPR_SMPSEL14_Msk                   /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR_SMPSEL15_Pos          (23U)
-#define ADC_SMPR_SMPSEL15_Msk          (0x1UL << ADC_SMPR_SMPSEL15_Pos)        /*!< 0x00800000 */
-#define ADC_SMPR_SMPSEL15              ADC_SMPR_SMPSEL15_Msk                   /*!< ADC channel 15 sampling time selection */
-#define ADC_SMPR_SMPSEL16_Pos          (24U)
-#define ADC_SMPR_SMPSEL16_Msk          (0x1UL << ADC_SMPR_SMPSEL16_Pos)        /*!< 0x01000000 */
-#define ADC_SMPR_SMPSEL16              ADC_SMPR_SMPSEL16_Msk                   /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR_SMPSEL17_Pos          (25U)
-#define ADC_SMPR_SMPSEL17_Msk          (0x1UL << ADC_SMPR_SMPSEL17_Pos)        /*!< 0x02000000 */
-#define ADC_SMPR_SMPSEL17              ADC_SMPR_SMPSEL17_Msk                   /*!< ADC channel 17 sampling time selection */
-
-/********************  Bit definition for ADC_TR1 register  *******************/
-#define ADC_TR1_LT1_Pos                (0U)
-#define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
-#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
-#define ADC_TR1_LT1_0                  (0x001UL << ADC_TR1_LT1_Pos)            /*!< 0x00000001 */
-#define ADC_TR1_LT1_1                  (0x002UL << ADC_TR1_LT1_Pos)            /*!< 0x00000002 */
-#define ADC_TR1_LT1_2                  (0x004UL << ADC_TR1_LT1_Pos)            /*!< 0x00000004 */
-#define ADC_TR1_LT1_3                  (0x008UL << ADC_TR1_LT1_Pos)            /*!< 0x00000008 */
-#define ADC_TR1_LT1_4                  (0x010UL << ADC_TR1_LT1_Pos)            /*!< 0x00000010 */
-#define ADC_TR1_LT1_5                  (0x020UL << ADC_TR1_LT1_Pos)            /*!< 0x00000020 */
-#define ADC_TR1_LT1_6                  (0x040UL << ADC_TR1_LT1_Pos)            /*!< 0x00000040 */
-#define ADC_TR1_LT1_7                  (0x080UL << ADC_TR1_LT1_Pos)            /*!< 0x00000080 */
-#define ADC_TR1_LT1_8                  (0x100UL << ADC_TR1_LT1_Pos)            /*!< 0x00000100 */
-#define ADC_TR1_LT1_9                  (0x200UL << ADC_TR1_LT1_Pos)            /*!< 0x00000200 */
-#define ADC_TR1_LT1_10                 (0x400UL << ADC_TR1_LT1_Pos)            /*!< 0x00000400 */
-#define ADC_TR1_LT1_11                 (0x800UL << ADC_TR1_LT1_Pos)            /*!< 0x00000800 */
-
-#define ADC_TR1_HT1_Pos                (16U)
-#define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
-#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
-#define ADC_TR1_HT1_0                  (0x001UL << ADC_TR1_HT1_Pos)            /*!< 0x00010000 */
-#define ADC_TR1_HT1_1                  (0x002UL << ADC_TR1_HT1_Pos)            /*!< 0x00020000 */
-#define ADC_TR1_HT1_2                  (0x004UL << ADC_TR1_HT1_Pos)            /*!< 0x00040000 */
-#define ADC_TR1_HT1_3                  (0x008UL << ADC_TR1_HT1_Pos)            /*!< 0x00080000 */
-#define ADC_TR1_HT1_4                  (0x010UL << ADC_TR1_HT1_Pos)            /*!< 0x00100000 */
-#define ADC_TR1_HT1_5                  (0x020UL << ADC_TR1_HT1_Pos)            /*!< 0x00200000 */
-#define ADC_TR1_HT1_6                  (0x040UL << ADC_TR1_HT1_Pos)            /*!< 0x00400000 */
-#define ADC_TR1_HT1_7                  (0x080UL << ADC_TR1_HT1_Pos)            /*!< 0x00800000 */
-#define ADC_TR1_HT1_8                  (0x100UL << ADC_TR1_HT1_Pos)            /*!< 0x01000000 */
-#define ADC_TR1_HT1_9                  (0x200UL << ADC_TR1_HT1_Pos)            /*!< 0x02000000 */
-#define ADC_TR1_HT1_10                 (0x400UL << ADC_TR1_HT1_Pos)            /*!< 0x04000000 */
-#define ADC_TR1_HT1_11                 (0x800UL << ADC_TR1_HT1_Pos)            /*!< 0x08000000 */
-
-/********************  Bit definition for ADC_TR2 register  *******************/
-#define ADC_TR2_LT2_Pos                (0U)
-#define ADC_TR2_LT2_Msk                (0xFFFUL << ADC_TR2_LT2_Pos)            /*!< 0x00000FFF */
-#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
-#define ADC_TR2_LT2_0                  (0x001UL << ADC_TR2_LT2_Pos)            /*!< 0x00000001 */
-#define ADC_TR2_LT2_1                  (0x002UL << ADC_TR2_LT2_Pos)            /*!< 0x00000002 */
-#define ADC_TR2_LT2_2                  (0x004UL << ADC_TR2_LT2_Pos)            /*!< 0x00000004 */
-#define ADC_TR2_LT2_3                  (0x008UL << ADC_TR2_LT2_Pos)            /*!< 0x00000008 */
-#define ADC_TR2_LT2_4                  (0x010UL << ADC_TR2_LT2_Pos)            /*!< 0x00000010 */
-#define ADC_TR2_LT2_5                  (0x020UL << ADC_TR2_LT2_Pos)            /*!< 0x00000020 */
-#define ADC_TR2_LT2_6                  (0x040UL << ADC_TR2_LT2_Pos)            /*!< 0x00000040 */
-#define ADC_TR2_LT2_7                  (0x080UL << ADC_TR2_LT2_Pos)            /*!< 0x00000080 */
-#define ADC_TR2_LT2_8                  (0x100UL << ADC_TR2_LT2_Pos)            /*!< 0x00000100 */
-#define ADC_TR2_LT2_9                  (0x200UL << ADC_TR2_LT2_Pos)            /*!< 0x00000200 */
-#define ADC_TR2_LT2_10                 (0x400UL << ADC_TR2_LT2_Pos)            /*!< 0x00000400 */
-#define ADC_TR2_LT2_11                 (0x800UL << ADC_TR2_LT2_Pos)            /*!< 0x00000800 */
-
-#define ADC_TR2_HT2_Pos                (16U)
-#define ADC_TR2_HT2_Msk                (0xFFFUL << ADC_TR2_HT2_Pos)            /*!< 0x0FFF0000 */
-#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
-#define ADC_TR2_HT2_0                  (0x001UL << ADC_TR2_HT2_Pos)            /*!< 0x00010000 */
-#define ADC_TR2_HT2_1                  (0x002UL << ADC_TR2_HT2_Pos)            /*!< 0x00020000 */
-#define ADC_TR2_HT2_2                  (0x004UL << ADC_TR2_HT2_Pos)            /*!< 0x00040000 */
-#define ADC_TR2_HT2_3                  (0x008UL << ADC_TR2_HT2_Pos)            /*!< 0x00080000 */
-#define ADC_TR2_HT2_4                  (0x010UL << ADC_TR2_HT2_Pos)            /*!< 0x00100000 */
-#define ADC_TR2_HT2_5                  (0x020UL << ADC_TR2_HT2_Pos)            /*!< 0x00200000 */
-#define ADC_TR2_HT2_6                  (0x040UL << ADC_TR2_HT2_Pos)            /*!< 0x00400000 */
-#define ADC_TR2_HT2_7                  (0x080UL << ADC_TR2_HT2_Pos)            /*!< 0x00800000 */
-#define ADC_TR2_HT2_8                  (0x100UL << ADC_TR2_HT2_Pos)            /*!< 0x01000000 */
-#define ADC_TR2_HT2_9                  (0x200UL << ADC_TR2_HT2_Pos)            /*!< 0x02000000 */
-#define ADC_TR2_HT2_10                 (0x400UL << ADC_TR2_HT2_Pos)            /*!< 0x04000000 */
-#define ADC_TR2_HT2_11                 (0x800UL << ADC_TR2_HT2_Pos)            /*!< 0x08000000 */
-
-/********************  Bit definition for ADC_CHSELR register  ****************/
-#define ADC_CHSELR_CHSEL_Pos           (0U)
-#define ADC_CHSELR_CHSEL_Msk           (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos)     /*!< 0x0003FFFF */
-#define ADC_CHSELR_CHSEL               ADC_CHSELR_CHSEL_Msk                    /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL17_Pos         (17U)
-#define ADC_CHSELR_CHSEL17_Msk         (0x1UL << ADC_CHSELR_CHSEL17_Pos)       /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17             ADC_CHSELR_CHSEL17_Msk                  /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL16_Pos         (16U)
-#define ADC_CHSELR_CHSEL16_Msk         (0x1UL << ADC_CHSELR_CHSEL16_Pos)       /*!< 0x00010000 */
-#define ADC_CHSELR_CHSEL16             ADC_CHSELR_CHSEL16_Msk                  /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL15_Pos         (15U)
-#define ADC_CHSELR_CHSEL15_Msk         (0x1UL << ADC_CHSELR_CHSEL15_Pos)       /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15             ADC_CHSELR_CHSEL15_Msk                  /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL14_Pos         (14U)
-#define ADC_CHSELR_CHSEL14_Msk         (0x1UL << ADC_CHSELR_CHSEL14_Pos)       /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14             ADC_CHSELR_CHSEL14_Msk                  /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL13_Pos         (13U)
-#define ADC_CHSELR_CHSEL13_Msk         (0x1UL << ADC_CHSELR_CHSEL13_Pos)       /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13             ADC_CHSELR_CHSEL13_Msk                  /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL12_Pos         (12U)
-#define ADC_CHSELR_CHSEL12_Msk         (0x1UL << ADC_CHSELR_CHSEL12_Pos)       /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12             ADC_CHSELR_CHSEL12_Msk                  /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL11_Pos         (11U)
-#define ADC_CHSELR_CHSEL11_Msk         (0x1UL << ADC_CHSELR_CHSEL11_Pos)       /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11             ADC_CHSELR_CHSEL11_Msk                  /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL10_Pos         (10U)
-#define ADC_CHSELR_CHSEL10_Msk         (0x1UL << ADC_CHSELR_CHSEL10_Pos)       /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10             ADC_CHSELR_CHSEL10_Msk                  /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL9_Pos          (9U)
-#define ADC_CHSELR_CHSEL9_Msk          (0x1UL << ADC_CHSELR_CHSEL9_Pos)        /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9              ADC_CHSELR_CHSEL9_Msk                   /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL8_Pos          (8U)
-#define ADC_CHSELR_CHSEL8_Msk          (0x1UL << ADC_CHSELR_CHSEL8_Pos)        /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8              ADC_CHSELR_CHSEL8_Msk                   /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL7_Pos          (7U)
-#define ADC_CHSELR_CHSEL7_Msk          (0x1UL << ADC_CHSELR_CHSEL7_Pos)        /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7              ADC_CHSELR_CHSEL7_Msk                   /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL6_Pos          (6U)
-#define ADC_CHSELR_CHSEL6_Msk          (0x1UL << ADC_CHSELR_CHSEL6_Pos)        /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6              ADC_CHSELR_CHSEL6_Msk                   /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL5_Pos          (5U)
-#define ADC_CHSELR_CHSEL5_Msk          (0x1UL << ADC_CHSELR_CHSEL5_Pos)        /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5              ADC_CHSELR_CHSEL5_Msk                   /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL4_Pos          (4U)
-#define ADC_CHSELR_CHSEL4_Msk          (0x1UL << ADC_CHSELR_CHSEL4_Pos)        /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4              ADC_CHSELR_CHSEL4_Msk                   /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL3_Pos          (3U)
-#define ADC_CHSELR_CHSEL3_Msk          (0x1UL << ADC_CHSELR_CHSEL3_Pos)        /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3              ADC_CHSELR_CHSEL3_Msk                   /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL2_Pos          (2U)
-#define ADC_CHSELR_CHSEL2_Msk          (0x1UL << ADC_CHSELR_CHSEL2_Pos)        /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2              ADC_CHSELR_CHSEL2_Msk                   /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL1_Pos          (1U)
-#define ADC_CHSELR_CHSEL1_Msk          (0x1UL << ADC_CHSELR_CHSEL1_Pos)        /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1              ADC_CHSELR_CHSEL1_Msk                   /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL0_Pos          (0U)
-#define ADC_CHSELR_CHSEL0_Msk          (0x1UL << ADC_CHSELR_CHSEL0_Pos)        /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0              ADC_CHSELR_CHSEL0_Msk                   /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
-
-#define ADC_CHSELR_SQ_ALL_Pos          (0U)
-#define ADC_CHSELR_SQ_ALL_Msk          (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
-#define ADC_CHSELR_SQ_ALL              ADC_CHSELR_SQ_ALL_Msk                   /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
-
-#define ADC_CHSELR_SQ8_Pos             (28U)
-#define ADC_CHSELR_SQ8_Msk             (0xFUL << ADC_CHSELR_SQ8_Pos)           /*!< 0xF0000000 */
-#define ADC_CHSELR_SQ8                 ADC_CHSELR_SQ8_Msk                      /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ8_0               (0x1UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x10000000 */
-#define ADC_CHSELR_SQ8_1               (0x2UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x20000000 */
-#define ADC_CHSELR_SQ8_2               (0x4UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x40000000 */
-#define ADC_CHSELR_SQ8_3               (0x8UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x80000000 */
-
-#define ADC_CHSELR_SQ7_Pos             (24U)
-#define ADC_CHSELR_SQ7_Msk             (0xFUL << ADC_CHSELR_SQ7_Pos)           /*!< 0x0F000000 */
-#define ADC_CHSELR_SQ7                 ADC_CHSELR_SQ7_Msk                      /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ7_0               (0x1UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x01000000 */
-#define ADC_CHSELR_SQ7_1               (0x2UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x02000000 */
-#define ADC_CHSELR_SQ7_2               (0x4UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x04000000 */
-#define ADC_CHSELR_SQ7_3               (0x8UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x08000000 */
-
-#define ADC_CHSELR_SQ6_Pos             (20U)
-#define ADC_CHSELR_SQ6_Msk             (0xFUL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00F00000 */
-#define ADC_CHSELR_SQ6                 ADC_CHSELR_SQ6_Msk                      /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ6_0               (0x1UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00100000 */
-#define ADC_CHSELR_SQ6_1               (0x2UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00200000 */
-#define ADC_CHSELR_SQ6_2               (0x4UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00400000 */
-#define ADC_CHSELR_SQ6_3               (0x8UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00800000 */
-
-#define ADC_CHSELR_SQ5_Pos             (16U)
-#define ADC_CHSELR_SQ5_Msk             (0xFUL << ADC_CHSELR_SQ5_Pos)           /*!< 0x000F0000 */
-#define ADC_CHSELR_SQ5                 ADC_CHSELR_SQ5_Msk                      /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ5_0               (0x1UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00010000 */
-#define ADC_CHSELR_SQ5_1               (0x2UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00020000 */
-#define ADC_CHSELR_SQ5_2               (0x4UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00040000 */
-#define ADC_CHSELR_SQ5_3               (0x8UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00080000 */
-
-#define ADC_CHSELR_SQ4_Pos             (12U)
-#define ADC_CHSELR_SQ4_Msk             (0xFUL << ADC_CHSELR_SQ4_Pos)           /*!< 0x0000F000 */
-#define ADC_CHSELR_SQ4                 ADC_CHSELR_SQ4_Msk                      /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ4_0               (0x1UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00001000 */
-#define ADC_CHSELR_SQ4_1               (0x2UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00002000 */
-#define ADC_CHSELR_SQ4_2               (0x4UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00004000 */
-#define ADC_CHSELR_SQ4_3               (0x8UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00008000 */
-
-#define ADC_CHSELR_SQ3_Pos             (8U)
-#define ADC_CHSELR_SQ3_Msk             (0xFUL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000F00 */
-#define ADC_CHSELR_SQ3                 ADC_CHSELR_SQ3_Msk                      /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ3_0               (0x1UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000100 */
-#define ADC_CHSELR_SQ3_1               (0x2UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000200 */
-#define ADC_CHSELR_SQ3_2               (0x4UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000400 */
-#define ADC_CHSELR_SQ3_3               (0x8UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000800 */
-
-#define ADC_CHSELR_SQ2_Pos             (4U)
-#define ADC_CHSELR_SQ2_Msk             (0xFUL << ADC_CHSELR_SQ2_Pos)           /*!< 0x000000F0 */
-#define ADC_CHSELR_SQ2                 ADC_CHSELR_SQ2_Msk                      /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ2_0               (0x1UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000010 */
-#define ADC_CHSELR_SQ2_1               (0x2UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000020 */
-#define ADC_CHSELR_SQ2_2               (0x4UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000040 */
-#define ADC_CHSELR_SQ2_3               (0x8UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000080 */
-
-#define ADC_CHSELR_SQ1_Pos             (0U)
-#define ADC_CHSELR_SQ1_Msk             (0xFUL << ADC_CHSELR_SQ1_Pos)           /*!< 0x0000000F */
-#define ADC_CHSELR_SQ1                 ADC_CHSELR_SQ1_Msk                      /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ1_0               (0x1UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000001 */
-#define ADC_CHSELR_SQ1_1               (0x2UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000002 */
-#define ADC_CHSELR_SQ1_2               (0x4UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000004 */
-#define ADC_CHSELR_SQ1_3               (0x8UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000008 */
-
-/********************  Bit definition for ADC_TR3 register  *******************/
-#define ADC_TR3_LT3_Pos                (0U)
-#define ADC_TR3_LT3_Msk                (0xFFFUL << ADC_TR3_LT3_Pos)            /*!< 0x00000FFF */
-#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
-#define ADC_TR3_LT3_0                  (0x001UL << ADC_TR3_LT3_Pos)            /*!< 0x00000001 */
-#define ADC_TR3_LT3_1                  (0x002UL << ADC_TR3_LT3_Pos)            /*!< 0x00000002 */
-#define ADC_TR3_LT3_2                  (0x004UL << ADC_TR3_LT3_Pos)            /*!< 0x00000004 */
-#define ADC_TR3_LT3_3                  (0x008UL << ADC_TR3_LT3_Pos)            /*!< 0x00000008 */
-#define ADC_TR3_LT3_4                  (0x010UL << ADC_TR3_LT3_Pos)            /*!< 0x00000010 */
-#define ADC_TR3_LT3_5                  (0x020UL << ADC_TR3_LT3_Pos)            /*!< 0x00000020 */
-#define ADC_TR3_LT3_6                  (0x040UL << ADC_TR3_LT3_Pos)            /*!< 0x00000040 */
-#define ADC_TR3_LT3_7                  (0x080UL << ADC_TR3_LT3_Pos)            /*!< 0x00000080 */
-#define ADC_TR3_LT3_8                  (0x100UL << ADC_TR3_LT3_Pos)            /*!< 0x00000100 */
-#define ADC_TR3_LT3_9                  (0x200UL << ADC_TR3_LT3_Pos)            /*!< 0x00000200 */
-#define ADC_TR3_LT3_10                 (0x400UL << ADC_TR3_LT3_Pos)            /*!< 0x00000400 */
-#define ADC_TR3_LT3_11                 (0x800UL << ADC_TR3_LT3_Pos)            /*!< 0x00000800 */
-
-#define ADC_TR3_HT3_Pos                (16U)
-#define ADC_TR3_HT3_Msk                (0xFFFUL << ADC_TR3_HT3_Pos)            /*!< 0x0FFF0000 */
-#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
-#define ADC_TR3_HT3_0                  (0x001UL << ADC_TR3_HT3_Pos)            /*!< 0x00010000 */
-#define ADC_TR3_HT3_1                  (0x002UL << ADC_TR3_HT3_Pos)            /*!< 0x00020000 */
-#define ADC_TR3_HT3_2                  (0x004UL << ADC_TR3_HT3_Pos)            /*!< 0x00040000 */
-#define ADC_TR3_HT3_3                  (0x008UL << ADC_TR3_HT3_Pos)            /*!< 0x00080000 */
-#define ADC_TR3_HT3_4                  (0x010UL << ADC_TR3_HT3_Pos)            /*!< 0x00100000 */
-#define ADC_TR3_HT3_5                  (0x020UL << ADC_TR3_HT3_Pos)            /*!< 0x00200000 */
-#define ADC_TR3_HT3_6                  (0x040UL << ADC_TR3_HT3_Pos)            /*!< 0x00400000 */
-#define ADC_TR3_HT3_7                  (0x080UL << ADC_TR3_HT3_Pos)            /*!< 0x00800000 */
-#define ADC_TR3_HT3_8                  (0x100UL << ADC_TR3_HT3_Pos)            /*!< 0x01000000 */
-#define ADC_TR3_HT3_9                  (0x200UL << ADC_TR3_HT3_Pos)            /*!< 0x02000000 */
-#define ADC_TR3_HT3_10                 (0x400UL << ADC_TR3_HT3_Pos)            /*!< 0x04000000 */
-#define ADC_TR3_HT3_11                 (0x800UL << ADC_TR3_HT3_Pos)            /*!< 0x08000000 */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                (0U)
-#define ADC_DR_DATA_Msk                (0xFFFFUL << ADC_DR_DATA_Pos)           /*!< 0x0000FFFF */
-#define ADC_DR_DATA                    ADC_DR_DATA_Msk                         /*!< ADC group regular conversion data */
-#define ADC_DR_DATA_0                  (0x0001UL << ADC_DR_DATA_Pos)           /*!< 0x00000001 */
-#define ADC_DR_DATA_1                  (0x0002UL << ADC_DR_DATA_Pos)           /*!< 0x00000002 */
-#define ADC_DR_DATA_2                  (0x0004UL << ADC_DR_DATA_Pos)           /*!< 0x00000004 */
-#define ADC_DR_DATA_3                  (0x0008UL << ADC_DR_DATA_Pos)           /*!< 0x00000008 */
-#define ADC_DR_DATA_4                  (0x0010UL << ADC_DR_DATA_Pos)           /*!< 0x00000010 */
-#define ADC_DR_DATA_5                  (0x0020UL << ADC_DR_DATA_Pos)           /*!< 0x00000020 */
-#define ADC_DR_DATA_6                  (0x0040UL << ADC_DR_DATA_Pos)           /*!< 0x00000040 */
-#define ADC_DR_DATA_7                  (0x0080UL << ADC_DR_DATA_Pos)           /*!< 0x00000080 */
-#define ADC_DR_DATA_8                  (0x0100UL << ADC_DR_DATA_Pos)           /*!< 0x00000100 */
-#define ADC_DR_DATA_9                  (0x0200UL << ADC_DR_DATA_Pos)           /*!< 0x00000200 */
-#define ADC_DR_DATA_10                 (0x0400UL << ADC_DR_DATA_Pos)           /*!< 0x00000400 */
-#define ADC_DR_DATA_11                 (0x0800UL << ADC_DR_DATA_Pos)           /*!< 0x00000800 */
-#define ADC_DR_DATA_12                 (0x1000UL << ADC_DR_DATA_Pos)           /*!< 0x00001000 */
-#define ADC_DR_DATA_13                 (0x2000UL << ADC_DR_DATA_Pos)           /*!< 0x00002000 */
-#define ADC_DR_DATA_14                 (0x4000UL << ADC_DR_DATA_Pos)           /*!< 0x00004000 */
-#define ADC_DR_DATA_15                 (0x8000UL << ADC_DR_DATA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for ADC_AWD2CR register  ****************/
-#define ADC_AWD2CR_AWD2CH_Pos          (0U)
-#define ADC_AWD2CR_AWD2CH_Msk          (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0003FFFF */
-#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
-#define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
-#define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
-#define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
-#define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
-#define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
-#define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
-#define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
-#define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
-#define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
-#define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
-#define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
-#define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
-#define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
-#define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
-#define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
-#define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
-#define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
-#define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
-
-/********************  Bit definition for ADC_AWD3CR register  ****************/
-#define ADC_AWD3CR_AWD3CH_Pos          (0U)
-#define ADC_AWD3CR_AWD3CH_Msk          (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0003FFFF */
-#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
-#define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
-#define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
-#define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
-#define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
-#define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
-#define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
-#define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
-#define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
-#define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
-#define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
-#define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
-#define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
-#define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
-#define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
-#define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
-#define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
-#define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
-#define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
-
-/********************  Bit definition for ADC_CALFACT register  ***************/
-#define ADC_CALFACT_CALFACT_Pos        (0U)
-#define ADC_CALFACT_CALFACT_Msk        (0x7FUL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT            ADC_CALFACT_CALFACT_Msk                 /*!< ADC calibration factor in single-ended mode */
-#define ADC_CALFACT_CALFACT_0          (0x01UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000001 */
-#define ADC_CALFACT_CALFACT_1          (0x02UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000002 */
-#define ADC_CALFACT_CALFACT_2          (0x04UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000004 */
-#define ADC_CALFACT_CALFACT_3          (0x08UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000008 */
-#define ADC_CALFACT_CALFACT_4          (0x10UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000010 */
-#define ADC_CALFACT_CALFACT_5          (0x20UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000020 */
-#define ADC_CALFACT_CALFACT_6          (0x40UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000040 */
-
-/*************************  ADC Common registers  *****************************/
-/********************  Bit definition for ADC_CCR register  *******************/
-#define ADC_CCR_PRESC_Pos              (18U)
-#define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
-#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
-#define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
-
-#define ADC_CCR_VREFEN_Pos             (22U)
-#define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
-#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
-#define ADC_CCR_TSEN_Pos               (23U)
-#define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
-#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
-#define ADC_CCR_VBATEN_Pos             (24U)
-#define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
-#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/**********************  Bit definition for COMP_CSR register  ****************/
-#define COMP_CSR_EN_Pos            (0U)
-#define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
-#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
-
-#define COMP_CSR_PWRMODE_Pos       (2U)
-#define COMP_CSR_PWRMODE_Msk       (0x3UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x0000000C */
-#define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
-#define COMP_CSR_PWRMODE_0         (0x1UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000004 */
-#define COMP_CSR_PWRMODE_1         (0x2UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000008 */
-
-#define COMP_CSR_INMSEL_Pos        (4U)
-#define COMP_CSR_INMSEL_Msk        (0x7UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */
-#define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
-#define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
-#define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
-#define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
-
-#define COMP_CSR_INPSEL_Pos        (7U)
-#define COMP_CSR_INPSEL_Msk        (0x3UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000180 */
-#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
-#define COMP_CSR_INPSEL_0          (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000080 */
-#define COMP_CSR_INPSEL_1          (0x2UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
-
-#define COMP_CSR_WINMODE_Pos       (9U)
-#define COMP_CSR_WINMODE_Msk       (0x1UL << COMP_CSR_WINMODE_Pos)             /*!< 0x00000200 */
-#define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_POLARITY_Pos      (15U)
-#define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
-#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
-
-#define COMP_CSR_HYST_Pos          (16U)
-#define COMP_CSR_HYST_Msk          (0x3UL << COMP_CSR_HYST_Pos)                /*!< 0x00030000 */
-#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
-#define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
-#define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
-
-#define COMP_CSR_BLANKING_Pos      (18U)
-#define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x001C0000 */
-#define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
-#define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00040000 */
-#define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */
-#define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */
-
-#define COMP_CSR_BRGEN_Pos         (22U)
-#define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */
-#define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
-#define COMP_CSR_SCALEN_Pos        (23U)
-#define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */
-#define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
-
-#define COMP_CSR_INMESEL_Pos       (25U)
-#define COMP_CSR_INMESEL_Msk       (0x3UL << COMP_CSR_INMESEL_Pos)             /*!< 0x06000000 */
-#define COMP_CSR_INMESEL           COMP_CSR_INMESEL_Msk                        /*!< Comparator input minus extended selection */
-#define COMP_CSR_INMESEL_0         (0x1UL << COMP_CSR_INMESEL_Pos)             /*!< 0x02000000 */
-#define COMP_CSR_INMESEL_1         (0x2UL << COMP_CSR_INMESEL_Pos)             /*!< 0x04000000 */
-
-#define COMP_CSR_VALUE_Pos         (30U)
-#define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
-#define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
-
-#define COMP_CSR_LOCK_Pos          (31U)
-#define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
-#define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)
-#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
-#define DAC_CR_TEN1_Pos             (1U)
-#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (2U)
-#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000004 */
-#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */
-#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */
-#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)
-#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)
-#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)
-#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)
-#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
-#define DAC_CR_CEN1_Pos             (14U)
-#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
-#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos    (0U)
-#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos    (4U)
-#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos     (0U)
-#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos       (0U)
-#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)
-#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_CAL_FLAG1_Pos        (14U)
-#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
-#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
-#define DAC_SR_BWST1_Pos            (15U)
-#define DAC_SR_BWST1_Msk            (0x1UL << DAC_SR_BWST1_Pos)                /*!< 0x00008000 */
-#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
-
-/*******************  Bit definition for DAC_CCR register  ********************/
-#define DAC_CCR_OTRIM1_Pos          (0U)
-#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
-#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
-
-/*******************  Bit definition for DAC_MCR register  *******************/
-#define DAC_MCR_MODE1_Pos           (0U)
-#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
-#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
-#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */
-#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */
-#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */
-
-/******************  Bit definition for DAC_SHSR1 register  ******************/
-#define DAC_SHSR1_TSAMPLE1_Pos      (0U)
-#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
-#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
-
-/******************  Bit definition for DAC_SHHR register  ******************/
-#define DAC_SHHR_THOLD1_Pos         (0U)
-#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
-#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
-
-/******************  Bit definition for DAC_SHRR register  ******************/
-#define DAC_SHRR_TREFRESH1_Pos      (0U)
-#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
-#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-#define LPTIM_ISR_UE_Pos            (7U)
-#define LPTIM_ISR_UE_Msk            (0x1UL << LPTIM_ISR_UE_Pos)                /*!< 0x00000080 */
-#define LPTIM_ISR_UE                LPTIM_ISR_UE_Msk                           /*!< Update event occurrence */
-#define LPTIM_ISR_REPOK_Pos         (8U)
-#define LPTIM_ISR_REPOK_Msk         (0x1UL << LPTIM_ISR_REPOK_Pos)              /*!< 0x00000100 */
-#define LPTIM_ISR_REPOK             LPTIM_ISR_REPOK_Msk                         /*!< Repetition register update OK */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-#define LPTIM_ICR_UECF_Pos          (7U)
-#define LPTIM_ICR_UECF_Msk          (0x1UL << LPTIM_ICR_UECF_Pos)              /*!< 0x00000080 */
-#define LPTIM_ICR_UECF              LPTIM_ICR_UECF_Msk                         /*!< Update event Clear Flag */
-#define LPTIM_ICR_REPOKCF_Pos       (8U)
-#define LPTIM_ICR_REPOKCF_Msk       (0x1UL << LPTIM_ICR_REPOKCF_Pos)           /*!< 0x00000100 */
-#define LPTIM_ICR_REPOKCF           LPTIM_ICR_REPOKCF_Msk                      /*!< Repetition register update OK Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-#define LPTIM_IER_UEIE_Pos          (7U)
-#define LPTIM_IER_UEIE_Msk          (0x1UL << LPTIM_IER_UEIE_Pos)              /*!< 0x00000080 */
-#define LPTIM_IER_UEIE              LPTIM_IER_UEIE_Msk                         /*!< Update event Interrupt Enable */
-#define LPTIM_IER_REPOKIE_Pos       (8U)
-#define LPTIM_IER_REPOKIE_Msk       (0x1UL << LPTIM_IER_REPOKIE_Pos)           /*!< 0x00000100 */
-#define LPTIM_IER_REPOKIE           LPTIM_IER_REPOKIE_Msk                      /*!< Repetition register update OK Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-#define LPTIM_CR_COUNTRST_Pos       (3U)
-#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
-#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
-#define LPTIM_CR_RSTARE_Pos         (4U)
-#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
-#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************  Bit definition for LPTIM_OR register  ********************/
-#define LPTIM_OR_OR_Pos             (0U)
-#define LPTIM_OR_OR_Msk             (0x3UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000003 */
-#define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
-#define LPTIM_OR_OR_0               (0x1UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000001 */
-#define LPTIM_OR_OR_1               (0x2UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000002 */
-
-/******************  Bit definition for LPTIM_RCR register  *******************/
-#define LPTIM_RCR_REP_Pos           (0U)
-#define LPTIM_RCR_REP_Msk           (0xFFUL << LPTIM_RCR_REP_Pos)              /*!< 0x000000FF */
-#define LPTIM_RCR_REP               LPTIM_RCR_REP_Msk                          /*!<Repetition Counter Value */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos             (0U)
-#define USART_CR1_UE_Msk             (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                 USART_CR1_UE_Msk                          /*!< USART Enable */
-#define USART_CR1_UESM_Pos           (1U)
-#define USART_CR1_UESM_Msk           (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM               USART_CR1_UESM_Msk                        /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos             (2U)
-#define USART_CR1_RE_Msk             (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                 USART_CR1_RE_Msk                          /*!< Receiver Enable */
-#define USART_CR1_TE_Pos             (3U)
-#define USART_CR1_TE_Msk             (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                 USART_CR1_TE_Msk                          /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos         (4U)
-#define USART_CR1_IDLEIE_Msk         (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE             USART_CR1_IDLEIE_Msk                      /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_RXFNEIE_Pos   (5U)
-#define USART_CR1_RXNEIE_RXFNEIE_Msk   (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
-#define USART_CR1_RXNEIE_RXFNEIE       USART_CR1_RXNEIE_RXFNEIE_Msk            /*!< RXNE/RXFIFO not empty Interrupt Enable */
-#define USART_CR1_TCIE_Pos           (6U)
-#define USART_CR1_TCIE_Msk           (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE               USART_CR1_TCIE_Msk                        /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_TXFNFIE_Pos  (7U)
-#define USART_CR1_TXEIE_TXFNFIE_Msk   (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)   /*!< 0x00000080 */
-#define USART_CR1_TXEIE_TXFNFIE       USART_CR1_TXEIE_TXFNFIE_Msk              /*!< TXE/TXFIFO not full Interrupt Enable */
-#define USART_CR1_PEIE_Pos           (8U)
-#define USART_CR1_PEIE_Msk           (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE               USART_CR1_PEIE_Msk                        /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos             (9U)
-#define USART_CR1_PS_Msk             (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                 USART_CR1_PS_Msk                          /*!< Parity Selection */
-#define USART_CR1_PCE_Pos            (10U)
-#define USART_CR1_PCE_Msk            (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                USART_CR1_PCE_Msk                         /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos           (11U)
-#define USART_CR1_WAKE_Msk           (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE               USART_CR1_WAKE_Msk                        /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos              (12U)
-#define USART_CR1_M_Msk              (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                  USART_CR1_M_Msk                           /*!< Word length */
-#define USART_CR1_M0_Pos             (12U)
-#define USART_CR1_M0_Msk             (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                 USART_CR1_M0_Msk                          /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos            (13U)
-#define USART_CR1_MME_Msk            (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                USART_CR1_MME_Msk                         /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos           (14U)
-#define USART_CR1_CMIE_Msk           (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE               USART_CR1_CMIE_Msk                        /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos          (15U)
-#define USART_CR1_OVER8_Msk          (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8              USART_CR1_OVER8_Msk                       /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos           (16U)
-#define USART_CR1_DEDT_Msk           (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT               USART_CR1_DEDT_Msk                        /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0             (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1             (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2             (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3             (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4             (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos           (21U)
-#define USART_CR1_DEAT_Msk           (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT               USART_CR1_DEAT_Msk                        /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0             (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1             (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2             (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3             (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4             (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos          (26U)
-#define USART_CR1_RTOIE_Msk          (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE              USART_CR1_RTOIE_Msk                       /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos          (27U)
-#define USART_CR1_EOBIE_Msk          (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE              USART_CR1_EOBIE_Msk                       /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos             (28U)
-#define USART_CR1_M1_Msk             (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                 USART_CR1_M1_Msk                          /*!< Word length - Bit 1 */
-#define USART_CR1_FIFOEN_Pos         (29U)
-#define USART_CR1_FIFOEN_Msk         (0x1UL << USART_CR1_FIFOEN_Pos)           /*!< 0x20000000 */
-#define USART_CR1_FIFOEN             USART_CR1_FIFOEN_Msk                      /*!< FIFO mode enable */
-#define USART_CR1_TXFEIE_Pos         (30U)
-#define USART_CR1_TXFEIE_Msk         (0x1UL << USART_CR1_TXFEIE_Pos)           /*!< 0x40000000 */
-#define USART_CR1_TXFEIE             USART_CR1_TXFEIE_Msk                      /*!< TXFIFO empty interrupt enable */
-#define USART_CR1_RXFFIE_Pos         (31U)
-#define USART_CR1_RXFFIE_Msk         (0x1UL << USART_CR1_RXFFIE_Pos)           /*!< 0x80000000 */
-#define USART_CR1_RXFFIE             USART_CR1_RXFFIE_Msk                      /*!< RXFIFO Full interrupt enable */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_SLVEN_Pos          (0U)
-#define USART_CR2_SLVEN_Msk          (0x1UL << USART_CR2_SLVEN_Pos)            /*!< 0x00000001 */
-#define USART_CR2_SLVEN              USART_CR2_SLVEN_Msk                       /*!< Synchronous Slave mode enable */
-#define USART_CR2_DIS_NSS_Pos        (3U)
-#define USART_CR2_DIS_NSS_Msk        (0x1UL << USART_CR2_DIS_NSS_Pos)          /*!< 0x00000008 */
-#define USART_CR2_DIS_NSS            USART_CR2_DIS_NSS_Msk                     /*!< NSS input pin disable for SPI slave selection */
-#define USART_CR2_ADDM7_Pos          (4U)
-#define USART_CR2_ADDM7_Msk          (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7              USART_CR2_ADDM7_Msk                       /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos           (5U)
-#define USART_CR2_LBDL_Msk           (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL               USART_CR2_LBDL_Msk                        /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos          (6U)
-#define USART_CR2_LBDIE_Msk          (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE              USART_CR2_LBDIE_Msk                       /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos           (8U)
-#define USART_CR2_LBCL_Msk           (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL               USART_CR2_LBCL_Msk                        /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos           (9U)
-#define USART_CR2_CPHA_Msk           (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA               USART_CR2_CPHA_Msk                        /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos           (10U)
-#define USART_CR2_CPOL_Msk           (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL               USART_CR2_CPOL_Msk                        /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos          (11U)
-#define USART_CR2_CLKEN_Msk          (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN              USART_CR2_CLKEN_Msk                       /*!< Clock Enable */
-#define USART_CR2_STOP_Pos           (12U)
-#define USART_CR2_STOP_Msk           (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP               USART_CR2_STOP_Msk                        /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0             (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1             (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos          (14U)
-#define USART_CR2_LINEN_Msk          (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN              USART_CR2_LINEN_Msk                       /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos           (15U)
-#define USART_CR2_SWAP_Msk           (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP               USART_CR2_SWAP_Msk                        /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos          (16U)
-#define USART_CR2_RXINV_Msk          (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV              USART_CR2_RXINV_Msk                       /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos          (17U)
-#define USART_CR2_TXINV_Msk          (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV              USART_CR2_TXINV_Msk                       /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos        (18U)
-#define USART_CR2_DATAINV_Msk        (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV            USART_CR2_DATAINV_Msk                     /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos       (19U)
-#define USART_CR2_MSBFIRST_Msk       (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST           USART_CR2_MSBFIRST_Msk                    /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos          (20U)
-#define USART_CR2_ABREN_Msk          (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN              USART_CR2_ABREN_Msk                       /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos        (21U)
-#define USART_CR2_ABRMODE_Msk        (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE            USART_CR2_ABRMODE_Msk                     /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0          (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1          (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos          (23U)
-#define USART_CR2_RTOEN_Msk          (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN              USART_CR2_RTOEN_Msk                       /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos            (24U)
-#define USART_CR2_ADD_Msk            (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                USART_CR2_ADD_Msk                         /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos            (0U)
-#define USART_CR3_EIE_Msk            (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                USART_CR3_EIE_Msk                         /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos           (1U)
-#define USART_CR3_IREN_Msk           (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN               USART_CR3_IREN_Msk                        /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos           (2U)
-#define USART_CR3_IRLP_Msk           (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP               USART_CR3_IRLP_Msk                        /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos          (3U)
-#define USART_CR3_HDSEL_Msk          (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL              USART_CR3_HDSEL_Msk                       /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos           (4U)
-#define USART_CR3_NACK_Msk           (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK               USART_CR3_NACK_Msk                        /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos           (5U)
-#define USART_CR3_SCEN_Msk           (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN               USART_CR3_SCEN_Msk                        /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos           (6U)
-#define USART_CR3_DMAR_Msk           (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR               USART_CR3_DMAR_Msk                        /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos           (7U)
-#define USART_CR3_DMAT_Msk           (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT               USART_CR3_DMAT_Msk                        /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos           (8U)
-#define USART_CR3_RTSE_Msk           (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE               USART_CR3_RTSE_Msk                        /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos           (9U)
-#define USART_CR3_CTSE_Msk           (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE               USART_CR3_CTSE_Msk                        /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos          (10U)
-#define USART_CR3_CTSIE_Msk          (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE              USART_CR3_CTSIE_Msk                       /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos         (11U)
-#define USART_CR3_ONEBIT_Msk         (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT             USART_CR3_ONEBIT_Msk                      /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos         (12U)
-#define USART_CR3_OVRDIS_Msk         (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS             USART_CR3_OVRDIS_Msk                      /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos           (13U)
-#define USART_CR3_DDRE_Msk           (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE               USART_CR3_DDRE_Msk                        /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos            (14U)
-#define USART_CR3_DEM_Msk            (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                USART_CR3_DEM_Msk                         /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos            (15U)
-#define USART_CR3_DEP_Msk            (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                USART_CR3_DEP_Msk                         /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos        (17U)
-#define USART_CR3_SCARCNT_Msk        (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT            USART_CR3_SCARCNT_Msk                     /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0          (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1          (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2          (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos            (20U)
-#define USART_CR3_WUS_Msk            (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                USART_CR3_WUS_Msk                         /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0              (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1              (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos          (22U)
-#define USART_CR3_WUFIE_Msk          (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE              USART_CR3_WUFIE_Msk                       /*!< Wake Up Interrupt Enable */
-#define USART_CR3_TXFTIE_Pos         (23U)
-#define USART_CR3_TXFTIE_Msk         (0x1UL << USART_CR3_TXFTIE_Pos)           /*!< 0x00800000 */
-#define USART_CR3_TXFTIE             USART_CR3_TXFTIE_Msk                      /*!< TXFIFO threshold interrupt enable */
-#define USART_CR3_TCBGTIE_Pos        (24U)
-#define USART_CR3_TCBGTIE_Msk        (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
-#define USART_CR3_TCBGTIE            USART_CR3_TCBGTIE_Msk                     /*!< Transmission Complete Before Guard Time Interrupt Enable */
-#define USART_CR3_RXFTCFG_Pos        (25U)
-#define USART_CR3_RXFTCFG_Msk        (0x7UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x0E000000 */
-#define USART_CR3_RXFTCFG            USART_CR3_RXFTCFG_Msk                     /*!< RXFIFO FIFO threshold configuration */
-#define USART_CR3_RXFTCFG_0          (0x1UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x02000000 */
-#define USART_CR3_RXFTCFG_1          (0x2UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x04000000 */
-#define USART_CR3_RXFTCFG_2          (0x4UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x08000000 */
-#define USART_CR3_RXFTIE_Pos         (28U)
-#define USART_CR3_RXFTIE_Msk         (0x1UL << USART_CR3_RXFTIE_Pos)           /*!< 0x10000000 */
-#define USART_CR3_RXFTIE             USART_CR3_RXFTIE_Msk                      /*!< RXFIFO threshold interrupt enable */
-#define USART_CR3_TXFTCFG_Pos        (29U)
-#define USART_CR3_TXFTCFG_Msk        (0x7UL << USART_CR3_TXFTCFG_Pos)          /*!< 0xE0000000 */
-#define USART_CR3_TXFTCFG            USART_CR3_TXFTCFG_Msk                     /*!< TXFIFO threshold configuration */
-#define USART_CR3_TXFTCFG_0          (0x1UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x20000000 */
-#define USART_CR3_TXFTCFG_1          (0x2UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x40000000 */
-#define USART_CR3_TXFTCFG_2          (0x4UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x80000000 */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_BRR                ((uint16_t)0xFFFF)                        /*!< USART  Baud rate register [15:0] */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos           (0U)
-#define USART_GTPR_PSC_Msk           (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC               USART_GTPR_PSC_Msk                        /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos            (8U)
-#define USART_GTPR_GT_Msk            (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                USART_GTPR_GT_Msk                         /*!< GT[7:0] bits (Guard time value) */
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos           (0U)
-#define USART_RTOR_RTO_Msk           (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO               USART_RTOR_RTO_Msk                        /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos          (24U)
-#define USART_RTOR_BLEN_Msk          (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN              USART_RTOR_BLEN_Msk                       /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ        ((uint16_t)0x0001)                              /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ        ((uint16_t)0x0002)                              /*!< Send Break Request */
-#define USART_RQR_MMRQ         ((uint16_t)0x0004)                              /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ        ((uint16_t)0x0008)                              /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ        ((uint16_t)0x0010)                              /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos             (0U)
-#define USART_ISR_PE_Msk             (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                 USART_ISR_PE_Msk                          /*!< Parity Error */
-#define USART_ISR_FE_Pos             (1U)
-#define USART_ISR_FE_Msk             (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                 USART_ISR_FE_Msk                          /*!< Framing Error */
-#define USART_ISR_NE_Pos             (2U)
-#define USART_ISR_NE_Msk             (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                 USART_ISR_NE_Msk                          /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos            (3U)
-#define USART_ISR_ORE_Msk            (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                USART_ISR_ORE_Msk                         /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos           (4U)
-#define USART_ISR_IDLE_Msk           (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE               USART_ISR_IDLE_Msk                        /*!< IDLE line detected */
-#define USART_ISR_RXNE_RXFNE_Pos     (5U)
-#define USART_ISR_RXNE_RXFNE_Msk     (0x1UL << USART_ISR_RXNE_RXFNE_Pos)      /*!< 0x00000020 */
-#define USART_ISR_RXNE_RXFNE         USART_ISR_RXNE_RXFNE_Msk                /*!< Read Data Register Not Empty/RXFIFO Not Empty */
-#define USART_ISR_TC_Pos             (6U)
-#define USART_ISR_TC_Msk             (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                 USART_ISR_TC_Msk                          /*!< Transmission Complete */
-#define USART_ISR_TXE_TXFNF_Pos      (7U)
-#define USART_ISR_TXE_TXFNF_Msk      (0x1UL << USART_ISR_TXE_TXFNF_Pos)       /*!< 0x00000080 */
-#define USART_ISR_TXE_TXFNF          USART_ISR_TXE_TXFNF_Msk                  /*!< Transmit Data Register Empty/TXFIFO Not Full */
-#define USART_ISR_LBDF_Pos           (8U)
-#define USART_ISR_LBDF_Msk           (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF               USART_ISR_LBDF_Msk                        /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos          (9U)
-#define USART_ISR_CTSIF_Msk          (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF              USART_ISR_CTSIF_Msk                       /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos            (10U)
-#define USART_ISR_CTS_Msk            (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                USART_ISR_CTS_Msk                         /*!< CTS flag */
-#define USART_ISR_RTOF_Pos           (11U)
-#define USART_ISR_RTOF_Msk           (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF               USART_ISR_RTOF_Msk                        /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos           (12U)
-#define USART_ISR_EOBF_Msk           (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF               USART_ISR_EOBF_Msk                        /*!< End Of Block Flag */
-#define USART_ISR_UDR_Pos            (13U)
-#define USART_ISR_UDR_Msk            (0x1UL << USART_ISR_UDR_Pos)              /*!< 0x00002000 */
-#define USART_ISR_UDR                 USART_ISR_UDR_Msk                        /*!< SPI Slave Underrun Error Flag */
-#define USART_ISR_ABRE_Pos           (14U)
-#define USART_ISR_ABRE_Msk           (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE               USART_ISR_ABRE_Msk                        /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos           (15U)
-#define USART_ISR_ABRF_Msk           (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF               USART_ISR_ABRF_Msk                        /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos           (16U)
-#define USART_ISR_BUSY_Msk           (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY               USART_ISR_BUSY_Msk                        /*!< Busy Flag */
-#define USART_ISR_CMF_Pos            (17U)
-#define USART_ISR_CMF_Msk            (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                USART_ISR_CMF_Msk                         /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos           (18U)
-#define USART_ISR_SBKF_Msk           (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF               USART_ISR_SBKF_Msk                        /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos            (19U)
-#define USART_ISR_RWU_Msk            (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                USART_ISR_RWU_Msk                         /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos            (20U)
-#define USART_ISR_WUF_Msk            (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                USART_ISR_WUF_Msk                         /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos          (21U)
-#define USART_ISR_TEACK_Msk          (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK              USART_ISR_TEACK_Msk                       /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos          (22U)
-#define USART_ISR_REACK_Msk          (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK              USART_ISR_REACK_Msk                       /*!< Receive Enable Acknowledge Flag */
-#define USART_ISR_TXFE_Pos           (23U)
-#define USART_ISR_TXFE_Msk           (0x1UL << USART_ISR_TXFE_Pos)             /*!< 0x00800000 */
-#define USART_ISR_TXFE               USART_ISR_TXFE_Msk                        /*!< TXFIFO Empty Flag */
-#define USART_ISR_RXFF_Pos           (24U)
-#define USART_ISR_RXFF_Msk           (0x1UL << USART_ISR_RXFF_Pos)             /*!< 0x01000000 */
-#define USART_ISR_RXFF               USART_ISR_RXFF_Msk                        /*!< RXFIFO Full Flag */
-#define USART_ISR_TCBGT_Pos          (25U)
-#define USART_ISR_TCBGT_Msk          (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
-#define USART_ISR_TCBGT              USART_ISR_TCBGT_Msk                       /*!< Transmission Complete Before Guard Time Completion Flag */
-#define USART_ISR_RXFT_Pos           (26U)
-#define USART_ISR_RXFT_Msk           (0x1UL << USART_ISR_RXFT_Pos)             /*!< 0x04000000 */
-#define USART_ISR_RXFT               USART_ISR_RXFT_Msk                        /*!< RXFIFO Threshold Flag */
-#define USART_ISR_TXFT_Pos           (27U)
-#define USART_ISR_TXFT_Msk           (0x1UL << USART_ISR_TXFT_Pos)             /*!< 0x08000000 */
-#define USART_ISR_TXFT               USART_ISR_TXFT_Msk                        /*!< TXFIFO Threshold Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos           (0U)
-#define USART_ICR_PECF_Msk           (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF               USART_ICR_PECF_Msk                        /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos           (1U)
-#define USART_ICR_FECF_Msk           (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF               USART_ICR_FECF_Msk                        /*!< Framing Error Clear Flag */
-#define USART_ICR_NECF_Pos           (2U)
-#define USART_ICR_NECF_Msk           (0x1UL << USART_ICR_NECF_Pos)             /*!< 0x00000004 */
-#define USART_ICR_NECF               USART_ICR_NECF_Msk                        /*!< Noise Error detected Clear Flag */
-#define USART_ICR_ORECF_Pos          (3U)
-#define USART_ICR_ORECF_Msk          (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF              USART_ICR_ORECF_Msk                       /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos         (4U)
-#define USART_ICR_IDLECF_Msk         (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF             USART_ICR_IDLECF_Msk                      /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TXFECF_Pos         (5U)
-#define USART_ICR_TXFECF_Msk         (0x1UL << USART_ICR_TXFECF_Pos)           /*!< 0x00000020 */
-#define USART_ICR_TXFECF             USART_ICR_TXFECF_Msk                      /*!< TXFIFO Empty Clear Flag */
-#define USART_ICR_TCCF_Pos           (6U)
-#define USART_ICR_TCCF_Msk           (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF               USART_ICR_TCCF_Msk                        /*!< Transmission Complete Clear Flag */
-#define USART_ICR_TCBGTCF_Pos        (7U)
-#define USART_ICR_TCBGTCF_Msk        (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
-#define USART_ICR_TCBGTCF            USART_ICR_TCBGTCF_Msk                     /*!< Transmission Complete Before Guard Time Clear Flag */
-#define USART_ICR_LBDCF_Pos          (8U)
-#define USART_ICR_LBDCF_Msk          (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF              USART_ICR_LBDCF_Msk                       /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos          (9U)
-#define USART_ICR_CTSCF_Msk          (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF              USART_ICR_CTSCF_Msk                       /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos          (11U)
-#define USART_ICR_RTOCF_Msk          (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF              USART_ICR_RTOCF_Msk                       /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos          (12U)
-#define USART_ICR_EOBCF_Msk          (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF              USART_ICR_EOBCF_Msk                       /*!< End Of Block Clear Flag */
-#define USART_ICR_UDRCF_Pos          (13U)
-#define USART_ICR_UDRCF_Msk          (0x1UL << USART_ICR_UDRCF_Pos)            /*!< 0x00002000 */
-#define USART_ICR_UDRCF              USART_ICR_UDRCF_Msk                       /*!< SPI Slave Underrun Clear Flag */
-#define USART_ICR_CMCF_Pos           (17U)
-#define USART_ICR_CMCF_Msk           (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF               USART_ICR_CMCF_Msk                        /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos           (20U)
-#define USART_ICR_WUCF_Msk           (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF               USART_ICR_WUCF_Msk                        /*!< Wake Up from stop mode Clear Flag */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)           /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)           /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/*******************  Bit definition for USART_PRESC register  ****************/
-#define USART_PRESC_PRESCALER_Pos    (0U)
-#define USART_PRESC_PRESCALER_Msk    (0xFUL << USART_PRESC_PRESCALER_Pos)      /*!< 0x0000000F */
-#define USART_PRESC_PRESCALER        USART_PRESC_PRESCALER_Msk                 /*!< PRESCALER[3:0] bits (Clock prescaler) */
-#define USART_PRESC_PRESCALER_0      (0x1UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000001 */
-#define USART_PRESC_PRESCALER_1      (0x2UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000002 */
-#define USART_PRESC_PRESCALER_2      (0x4UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000004 */
-#define USART_PRESC_PRESCALER_3      (0x8UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000008 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos          (0U)
-#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)                   /*!< 0x000000FF */
-#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bits data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos            (0U)
-#define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                      /*!< 0x00000001 */
-#define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos      (1U)
-#define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000006 */
-#define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
-#define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos          (3U)
-#define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                    /*!< 0x00000018 */
-#define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                    /*!< 0x00000008 */
-#define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                    /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos         (5U)
-#define AES_CR_CHMOD_Msk         (0x803UL << AES_CR_CHMOD_Pos)                 /*!< 0x00010060 */
-#define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0           (0x001UL << AES_CR_CHMOD_Pos)                 /*!< 0x00000020 */
-#define AES_CR_CHMOD_1           (0x002UL << AES_CR_CHMOD_Pos)                 /*!< 0x00000040 */
-#define AES_CR_CHMOD_2           (0x800UL << AES_CR_CHMOD_Pos)                 /*!< 0x00010000 */
-
-#define AES_CR_CCFC_Pos          (7U)
-#define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                    /*!< 0x00000080 */
-#define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos          (8U)
-#define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                    /*!< 0x00000100 */
-#define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
-#define AES_CR_CCFIE_Pos         (9U)
-#define AES_CR_CCFIE_Msk         (0x1UL << AES_CR_CCFIE_Pos)                   /*!< 0x00000200 */
-#define AES_CR_CCFIE             AES_CR_CCFIE_Msk                              /*!< Computation Complete Flag Interrupt Enable */
-#define AES_CR_ERRIE_Pos         (10U)
-#define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                   /*!< 0x00000400 */
-#define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos       (11U)
-#define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                 /*!< 0x00000800 */
-#define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< Enable data input phase DMA management  */
-#define AES_CR_DMAOUTEN_Pos      (12U)
-#define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< Enable data output phase DMA management */
-
-#define AES_CR_GCMPH_Pos         (13U)
-#define AES_CR_GCMPH_Msk         (0x3UL << AES_CR_GCMPH_Pos)                   /*!< 0x00006000 */
-#define AES_CR_GCMPH             AES_CR_GCMPH_Msk                              /*!< GCM Phase */
-#define AES_CR_GCMPH_0           (0x1UL << AES_CR_GCMPH_Pos)                   /*!< 0x00002000 */
-#define AES_CR_GCMPH_1           (0x2UL << AES_CR_GCMPH_Pos)                   /*!< 0x00004000 */
-
-#define AES_CR_KEYSIZE_Pos       (18U)
-#define AES_CR_KEYSIZE_Msk       (0x1UL << AES_CR_KEYSIZE_Pos)                 /*!< 0x00040000 */
-#define AES_CR_KEYSIZE           AES_CR_KEYSIZE_Msk                            /*!< Key size selection */
-
-#define AES_CR_NPBLB_Pos         (20U)
-#define AES_CR_NPBLB_Msk         (0xFUL << AES_CR_NPBLB_Pos)                   /*!< 0x00F00000 */
-#define AES_CR_NPBLB             AES_CR_NPBLB_Msk                              /*!< Number of padding bytes in last payload block */
-#define AES_CR_NPBLB_0           (0x1UL << AES_CR_NPBLB_Pos)                   /*!< 0x00100000 */
-#define AES_CR_NPBLB_1           (0x2UL << AES_CR_NPBLB_Pos)                   /*!< 0x00200000 */
-#define AES_CR_NPBLB_2           (0x4UL << AES_CR_NPBLB_Pos)                   /*!< 0x00400000 */
-#define AES_CR_NPBLB_3           (0x8UL << AES_CR_NPBLB_Pos)                   /*!< 0x00800000 */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos           (0U)
-#define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                     /*!< 0x00000001 */
-#define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos         (1U)
-#define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                   /*!< 0x00000002 */
-#define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos         (2U)
-#define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                   /*!< 0x00000004 */
-#define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
-#define AES_SR_BUSY_Pos          (3U)
-#define AES_SR_BUSY_Msk          (0x1UL << AES_SR_BUSY_Pos)                    /*!< 0x00000008 */
-#define AES_SR_BUSY              AES_SR_BUSY_Msk                               /*!< Busy Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos             (0U)
-#define AES_DINR_Msk             (0xFFFFFFFFUL << AES_DINR_Pos)                /*!< 0xFFFFFFFF */
-#define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos            (0U)
-#define AES_DOUTR_Msk            (0xFFFFFFFFUL << AES_DOUTR_Pos)               /*!< 0xFFFFFFFF */
-#define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos            (0U)
-#define AES_KEYR0_Msk            (0xFFFFFFFFUL << AES_KEYR0_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos            (0U)
-#define AES_KEYR1_Msk            (0xFFFFFFFFUL << AES_KEYR1_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos            (0U)
-#define AES_KEYR2_Msk            (0xFFFFFFFFUL << AES_KEYR2_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos            (0U)
-#define AES_KEYR3_Msk            (0xFFFFFFFFUL << AES_KEYR3_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_KEYR4 register  ******************/
-#define AES_KEYR4_Pos            (0U)
-#define AES_KEYR4_Msk            (0xFFFFFFFFUL << AES_KEYR4_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR4                AES_KEYR4_Msk                                 /*!< AES Key Register 4 */
-
-/*******************  Bit definition for AES_KEYR5 register  ******************/
-#define AES_KEYR5_Pos            (0U)
-#define AES_KEYR5_Msk            (0xFFFFFFFFUL << AES_KEYR5_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR5                AES_KEYR5_Msk                                 /*!< AES Key Register 5 */
-
-/*******************  Bit definition for AES_KEYR6 register  ******************/
-#define AES_KEYR6_Pos            (0U)
-#define AES_KEYR6_Msk            (0xFFFFFFFFUL << AES_KEYR6_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR6                AES_KEYR6_Msk                                 /*!< AES Key Register 6 */
-
-/*******************  Bit definition for AES_KEYR7 register  ******************/
-#define AES_KEYR7_Pos            (0U)
-#define AES_KEYR7_Msk            (0xFFFFFFFFUL << AES_KEYR7_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR7                AES_KEYR7_Msk                                 /*!< AES Key Register 7 */
-
-/*******************  Bit definition for AES_IVR0 register   ******************/
-#define AES_IVR0_Pos             (0U)
-#define AES_IVR0_Msk             (0xFFFFFFFFUL << AES_IVR0_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register   ******************/
-#define AES_IVR1_Pos             (0U)
-#define AES_IVR1_Msk             (0xFFFFFFFFUL << AES_IVR1_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register   ******************/
-#define AES_IVR2_Pos             (0U)
-#define AES_IVR2_Msk             (0xFFFFFFFFUL << AES_IVR2_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register   ******************/
-#define AES_IVR3_Pos             (0U)
-#define AES_IVR3_Msk             (0xFFFFFFFFUL << AES_IVR3_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
-
-/*******************  Bit definition for AES_SUSP0R register  ******************/
-#define AES_SUSP0R_Pos           (0U)
-#define AES_SUSP0R_Msk           (0xFFFFFFFFUL << AES_SUSP0R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP0R               AES_SUSP0R_Msk                                /*!< AES Suspend registers 0 */
-
-/*******************  Bit definition for AES_SUSP1R register  ******************/
-#define AES_SUSP1R_Pos           (0U)
-#define AES_SUSP1R_Msk           (0xFFFFFFFFUL << AES_SUSP1R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP1R               AES_SUSP1R_Msk                                /*!< AES Suspend registers 1 */
-
-/*******************  Bit definition for AES_SUSP2R register  ******************/
-#define AES_SUSP2R_Pos           (0U)
-#define AES_SUSP2R_Msk           (0xFFFFFFFFUL << AES_SUSP2R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP2R               AES_SUSP2R_Msk                                /*!< AES Suspend registers 2 */
-
-/*******************  Bit definition for AES_SUSP3R register  ******************/
-#define AES_SUSP3R_Pos           (0U)
-#define AES_SUSP3R_Msk           (0xFFFFFFFFUL << AES_SUSP3R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP3R               AES_SUSP3R_Msk                                /*!< AES Suspend registers 3 */
-
-/*******************  Bit definition for AES_SUSP4R register  ******************/
-#define AES_SUSP4R_Pos           (0U)
-#define AES_SUSP4R_Msk           (0xFFFFFFFFUL << AES_SUSP4R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP4R               AES_SUSP4R_Msk                                /*!< AES Suspend registers 4 */
-
-/*******************  Bit definition for AES_SUSP5R register  ******************/
-#define AES_SUSP5R_Pos           (0U)
-#define AES_SUSP5R_Msk           (0xFFFFFFFFUL << AES_SUSP5R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP5R               AES_SUSP5R_Msk                                /*!< AES Suspend registers 5 */
-
-/*******************  Bit definition for AES_SUSP6R register  ******************/
-#define AES_SUSP6R_Pos           (0U)
-#define AES_SUSP6R_Msk           (0xFFFFFFFFUL << AES_SUSP6R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP6R               AES_SUSP6R_Msk                                /*!< AES Suspend registers 6 */
-
-/*******************  Bit definition for AES_SUSP7R register  ******************/
-#define AES_SUSP7R_Pos           (0U)
-#define AES_SUSP7R_Msk           (0xFFFFFFFFUL << AES_SUSP7R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP7R               AES_SUSP7R_Msk                                /*!< AES Suspend registers 7 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos      (1U)
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos      (2U)
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos      (3U)
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos       (4U)
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos      (5U)
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos      (6U)
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos      (7U)
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos       (8U)
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos      (9U)
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos      (10U)
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos      (11U)
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos       (12U)
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos      (13U)
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos      (14U)
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos      (15U)
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos       (16U)
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos      (17U)
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos      (18U)
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos      (19U)
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos       (20U)
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos    (1U)
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos    (2U)
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos    (3U)
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos     (4U)
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos    (5U)
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos    (6U)
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos    (7U)
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos     (8U)
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos    (9U)
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos    (10U)
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos    (11U)
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos     (12U)
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos    (13U)
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos    (14U)
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos    (15U)
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos     (16U)
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos    (17U)
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos    (18U)
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos    (19U)
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos     (20U)
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)
-#define DMA_CNDTR_NDT_Msk      (0x3FFFFUL << DMA_CNDTR_NDT_Pos)                /*!< 0x0003FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMAMUX Controller                              */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMAMUX_CxCR register  **************/
-#define DMAMUX_CxCR_DMAREQ_ID_Pos              (0U)
-#define DMAMUX_CxCR_DMAREQ_ID_Msk              (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x0000007F */
-#define DMAMUX_CxCR_DMAREQ_ID                  DMAMUX_CxCR_DMAREQ_ID_Msk       /*!< DMA Request ID                       */
-#define DMAMUX_CxCR_DMAREQ_ID_0                (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
-#define DMAMUX_CxCR_DMAREQ_ID_1                (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
-#define DMAMUX_CxCR_DMAREQ_ID_2                (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
-#define DMAMUX_CxCR_DMAREQ_ID_3                (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
-#define DMAMUX_CxCR_DMAREQ_ID_4                (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
-#define DMAMUX_CxCR_DMAREQ_ID_5                (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
-#define DMAMUX_CxCR_DMAREQ_ID_6                (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
-#define DMAMUX_CxCR_SOIE_Pos                   (8U)
-#define DMAMUX_CxCR_SOIE_Msk                   (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
-#define DMAMUX_CxCR_SOIE                       DMAMUX_CxCR_SOIE_Msk            /*!< Synchro overrun interrupt enable     */
-#define DMAMUX_CxCR_EGE_Pos                    (9U)
-#define DMAMUX_CxCR_EGE_Msk                    (0x1UL << DMAMUX_CxCR_EGE_Pos)  /*!< 0x00000200 */
-#define DMAMUX_CxCR_EGE                        DMAMUX_CxCR_EGE_Msk             /*!< Event generation interrupt enable    */
-#define DMAMUX_CxCR_SE_Pos                     (16U)
-#define DMAMUX_CxCR_SE_Msk                     (0x1UL << DMAMUX_CxCR_SE_Pos)   /*!< 0x00010000 */
-#define DMAMUX_CxCR_SE                         DMAMUX_CxCR_SE_Msk              /*!< Synchronization enable               */
-#define DMAMUX_CxCR_SPOL_Pos                   (17U)
-#define DMAMUX_CxCR_SPOL_Msk                   (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
-#define DMAMUX_CxCR_SPOL                       DMAMUX_CxCR_SPOL_Msk            /*!< Synchronization polarity             */
-#define DMAMUX_CxCR_SPOL_0                     (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
-#define DMAMUX_CxCR_SPOL_1                     (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
-#define DMAMUX_CxCR_NBREQ_Pos                  (19U)
-#define DMAMUX_CxCR_NBREQ_Msk                  (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
-#define DMAMUX_CxCR_NBREQ                      DMAMUX_CxCR_NBREQ_Msk           /*!< Number of request                    */
-#define DMAMUX_CxCR_NBREQ_0                    (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
-#define DMAMUX_CxCR_NBREQ_1                    (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
-#define DMAMUX_CxCR_NBREQ_2                    (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
-#define DMAMUX_CxCR_NBREQ_3                    (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
-#define DMAMUX_CxCR_NBREQ_4                    (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
-#define DMAMUX_CxCR_SYNC_ID_Pos                (24U)
-#define DMAMUX_CxCR_SYNC_ID_Msk                (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
-#define DMAMUX_CxCR_SYNC_ID                    DMAMUX_CxCR_SYNC_ID_Msk         /*!< Synchronization ID                   */
-#define DMAMUX_CxCR_SYNC_ID_0                  (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
-#define DMAMUX_CxCR_SYNC_ID_1                  (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
-#define DMAMUX_CxCR_SYNC_ID_2                  (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
-#define DMAMUX_CxCR_SYNC_ID_3                  (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
-#define DMAMUX_CxCR_SYNC_ID_4                  (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
-
-/*******************  Bits definition for DMAMUX_CSR register  **************/
-#define DMAMUX_CSR_SOF0_Pos                    (0U)
-#define DMAMUX_CSR_SOF0_Msk                    (0x1UL << DMAMUX_CSR_SOF0_Pos)  /*!< 0x00000001 */
-#define DMAMUX_CSR_SOF0                        DMAMUX_CSR_SOF0_Msk             /*!< Synchronization Overrun Flag 0       */
-#define DMAMUX_CSR_SOF1_Pos                    (1U)
-#define DMAMUX_CSR_SOF1_Msk                    (0x1UL << DMAMUX_CSR_SOF1_Pos)  /*!< 0x00000002 */
-#define DMAMUX_CSR_SOF1                        DMAMUX_CSR_SOF1_Msk             /*!< Synchronization Overrun Flag 1       */
-#define DMAMUX_CSR_SOF2_Pos                    (2U)
-#define DMAMUX_CSR_SOF2_Msk                    (0x1UL << DMAMUX_CSR_SOF2_Pos)  /*!< 0x00000004 */
-#define DMAMUX_CSR_SOF2                        DMAMUX_CSR_SOF2_Msk             /*!< Synchronization Overrun Flag 2       */
-#define DMAMUX_CSR_SOF3_Pos                    (3U)
-#define DMAMUX_CSR_SOF3_Msk                    (0x1UL << DMAMUX_CSR_SOF3_Pos)  /*!< 0x00000008 */
-#define DMAMUX_CSR_SOF3                        DMAMUX_CSR_SOF3_Msk             /*!< Synchronization Overrun Flag 3       */
-#define DMAMUX_CSR_SOF4_Pos                    (4U)
-#define DMAMUX_CSR_SOF4_Msk                    (0x1UL << DMAMUX_CSR_SOF4_Pos)  /*!< 0x00000010 */
-#define DMAMUX_CSR_SOF4                        DMAMUX_CSR_SOF4_Msk             /*!< Synchronization Overrun Flag 4       */
-#define DMAMUX_CSR_SOF5_Pos                    (5U)
-#define DMAMUX_CSR_SOF5_Msk                    (0x1UL << DMAMUX_CSR_SOF5_Pos)  /*!< 0x00000020 */
-#define DMAMUX_CSR_SOF5                        DMAMUX_CSR_SOF5_Msk             /*!< Synchronization Overrun Flag 5       */
-#define DMAMUX_CSR_SOF6_Pos                    (6U)
-#define DMAMUX_CSR_SOF6_Msk                    (0x1UL << DMAMUX_CSR_SOF6_Pos)  /*!< 0x00000040 */
-#define DMAMUX_CSR_SOF6                        DMAMUX_CSR_SOF6_Msk             /*!< Synchronization Overrun Flag 6       */
-#define DMAMUX_CSR_SOF7_Pos                    (7U)
-#define DMAMUX_CSR_SOF7_Msk                    (0x1UL << DMAMUX_CSR_SOF7_Pos)  /*!< 0x00000080 */
-#define DMAMUX_CSR_SOF7                        DMAMUX_CSR_SOF7_Msk             /*!< Synchronization Overrun Flag 7       */
-#define DMAMUX_CSR_SOF8_Pos                    (8U)
-#define DMAMUX_CSR_SOF8_Msk                    (0x1UL << DMAMUX_CSR_SOF8_Pos)  /*!< 0x00000100 */
-#define DMAMUX_CSR_SOF8                        DMAMUX_CSR_SOF8_Msk             /*!< Synchronization Overrun Flag 8       */
-#define DMAMUX_CSR_SOF9_Pos                    (9U)
-#define DMAMUX_CSR_SOF9_Msk                    (0x1UL << DMAMUX_CSR_SOF9_Pos)  /*!< 0x00000200 */
-#define DMAMUX_CSR_SOF9                        DMAMUX_CSR_SOF9_Msk             /*!< Synchronization Overrun Flag 9       */
-#define DMAMUX_CSR_SOF10_Pos                   (10U)
-#define DMAMUX_CSR_SOF10_Msk                   (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
-#define DMAMUX_CSR_SOF10                       DMAMUX_CSR_SOF10_Msk            /*!< Synchronization Overrun Flag 10      */
-#define DMAMUX_CSR_SOF11_Pos                   (11U)
-#define DMAMUX_CSR_SOF11_Msk                   (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
-#define DMAMUX_CSR_SOF11                       DMAMUX_CSR_SOF11_Msk            /*!< Synchronization Overrun Flag 11      */
-#define DMAMUX_CSR_SOF12_Pos                   (12U)
-#define DMAMUX_CSR_SOF12_Msk                   (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
-#define DMAMUX_CSR_SOF12                       DMAMUX_CSR_SOF12_Msk            /*!< Synchronization Overrun Flag 12      */
-#define DMAMUX_CSR_SOF13_Pos                   (13U)
-#define DMAMUX_CSR_SOF13_Msk                   (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
-#define DMAMUX_CSR_SOF13                       DMAMUX_CSR_SOF13_Msk            /*!< Synchronization Overrun Flag 13      */
-
-/********************  Bits definition for DMAMUX_CFR register  **************/
-#define DMAMUX_CFR_CSOF0_Pos                   (0U)
-#define DMAMUX_CFR_CSOF0_Msk                   (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
-#define DMAMUX_CFR_CSOF0                       DMAMUX_CFR_CSOF0_Msk            /*!< Clear Overrun Flag 0                 */
-#define DMAMUX_CFR_CSOF1_Pos                   (1U)
-#define DMAMUX_CFR_CSOF1_Msk                   (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
-#define DMAMUX_CFR_CSOF1                       DMAMUX_CFR_CSOF1_Msk            /*!< Clear Overrun Flag 1                 */
-#define DMAMUX_CFR_CSOF2_Pos                   (2U)
-#define DMAMUX_CFR_CSOF2_Msk                   (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
-#define DMAMUX_CFR_CSOF2                       DMAMUX_CFR_CSOF2_Msk            /*!< Clear Overrun Flag 2                 */
-#define DMAMUX_CFR_CSOF3_Pos                   (3U)
-#define DMAMUX_CFR_CSOF3_Msk                   (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
-#define DMAMUX_CFR_CSOF3                       DMAMUX_CFR_CSOF3_Msk            /*!< Clear Overrun Flag 3                 */
-#define DMAMUX_CFR_CSOF4_Pos                   (4U)
-#define DMAMUX_CFR_CSOF4_Msk                   (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
-#define DMAMUX_CFR_CSOF4                       DMAMUX_CFR_CSOF4_Msk            /*!< Clear Overrun Flag 4                 */
-#define DMAMUX_CFR_CSOF5_Pos                   (5U)
-#define DMAMUX_CFR_CSOF5_Msk                   (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
-#define DMAMUX_CFR_CSOF5                       DMAMUX_CFR_CSOF5_Msk            /*!< Clear Overrun Flag 5                 */
-#define DMAMUX_CFR_CSOF6_Pos                   (6U)
-#define DMAMUX_CFR_CSOF6_Msk                   (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
-#define DMAMUX_CFR_CSOF6                       DMAMUX_CFR_CSOF6_Msk            /*!< Clear Overrun Flag 6                 */
-#define DMAMUX_CFR_CSOF7_Pos                   (7U)
-#define DMAMUX_CFR_CSOF7_Msk                   (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
-#define DMAMUX_CFR_CSOF7                       DMAMUX_CFR_CSOF7_Msk            /*!< Clear Overrun Flag 7                 */
-#define DMAMUX_CFR_CSOF8_Pos                   (8U)
-#define DMAMUX_CFR_CSOF8_Msk                   (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
-#define DMAMUX_CFR_CSOF8                       DMAMUX_CFR_CSOF8_Msk            /*!< Clear Overrun Flag 8                 */
-#define DMAMUX_CFR_CSOF9_Pos                   (9U)
-#define DMAMUX_CFR_CSOF9_Msk                   (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
-#define DMAMUX_CFR_CSOF9                       DMAMUX_CFR_CSOF9_Msk            /*!< Clear Overrun Flag 9                 */
-#define DMAMUX_CFR_CSOF10_Pos                  (10U)
-#define DMAMUX_CFR_CSOF10_Msk                  (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
-#define DMAMUX_CFR_CSOF10                      DMAMUX_CFR_CSOF10_Msk           /*!< Clear Overrun Flag 10                */
-#define DMAMUX_CFR_CSOF11_Pos                  (11U)
-#define DMAMUX_CFR_CSOF11_Msk                  (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
-#define DMAMUX_CFR_CSOF11                      DMAMUX_CFR_CSOF11_Msk           /*!< Clear Overrun Flag 11                */
-#define DMAMUX_CFR_CSOF12_Pos                  (12U)
-#define DMAMUX_CFR_CSOF12_Msk                  (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
-#define DMAMUX_CFR_CSOF12                      DMAMUX_CFR_CSOF12_Msk           /*!< Clear Overrun Flag 12                */
-#define DMAMUX_CFR_CSOF13_Pos                  (13U)
-#define DMAMUX_CFR_CSOF13_Msk                  (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
-#define DMAMUX_CFR_CSOF13                      DMAMUX_CFR_CSOF13_Msk           /*!< Clear Overrun Flag 13                */
-
-/********************  Bits definition for DMAMUX_RGxCR register  ************/
-#define DMAMUX_RGxCR_SIG_ID_Pos                (0U)
-#define DMAMUX_RGxCR_SIG_ID_Msk                (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
-#define DMAMUX_RGxCR_SIG_ID                    DMAMUX_RGxCR_SIG_ID_Msk         /*!< Signal ID                            */
-#define DMAMUX_RGxCR_SIG_ID_0                  (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
-#define DMAMUX_RGxCR_SIG_ID_1                  (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
-#define DMAMUX_RGxCR_SIG_ID_2                  (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
-#define DMAMUX_RGxCR_SIG_ID_3                  (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
-#define DMAMUX_RGxCR_SIG_ID_4                  (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
-#define DMAMUX_RGxCR_OIE_Pos                   (8U)
-#define DMAMUX_RGxCR_OIE_Msk                   (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
-#define DMAMUX_RGxCR_OIE                       DMAMUX_RGxCR_OIE_Msk            /*!< Overrun interrupt enable             */
-#define DMAMUX_RGxCR_GE_Pos                    (16U)
-#define DMAMUX_RGxCR_GE_Msk                    (0x1UL << DMAMUX_RGxCR_GE_Pos)  /*!< 0x00010000 */
-#define DMAMUX_RGxCR_GE                        DMAMUX_RGxCR_GE_Msk             /*!< Generation enable                    */
-#define DMAMUX_RGxCR_GPOL_Pos                  (17U)
-#define DMAMUX_RGxCR_GPOL_Msk                  (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
-#define DMAMUX_RGxCR_GPOL                      DMAMUX_RGxCR_GPOL_Msk           /*!< Generation polarity                  */
-#define DMAMUX_RGxCR_GPOL_0                    (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
-#define DMAMUX_RGxCR_GPOL_1                    (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
-#define DMAMUX_RGxCR_GNBREQ_Pos                (19U)
-#define DMAMUX_RGxCR_GNBREQ_Msk                (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
-#define DMAMUX_RGxCR_GNBREQ                    DMAMUX_RGxCR_GNBREQ_Msk          /*!< Number of request                    */
-#define DMAMUX_RGxCR_GNBREQ_0                  (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
-#define DMAMUX_RGxCR_GNBREQ_1                  (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
-#define DMAMUX_RGxCR_GNBREQ_2                  (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
-#define DMAMUX_RGxCR_GNBREQ_3                  (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
-#define DMAMUX_RGxCR_GNBREQ_4                  (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
-
-/********************  Bits definition for DMAMUX_RGSR register  **************/
-#define DMAMUX_RGSR_OF0_Pos                    (0U)
-#define DMAMUX_RGSR_OF0_Msk                    (0x1UL << DMAMUX_RGSR_OF0_Pos)  /*!< 0x00000001 */
-#define DMAMUX_RGSR_OF0                        DMAMUX_RGSR_OF0_Msk             /*!< Overrun flag 0                       */
-#define DMAMUX_RGSR_OF1_Pos                    (1U)
-#define DMAMUX_RGSR_OF1_Msk                    (0x1UL << DMAMUX_RGSR_OF1_Pos)  /*!< 0x00000002 */
-#define DMAMUX_RGSR_OF1                        DMAMUX_RGSR_OF1_Msk             /*!< Overrun flag 1                       */
-#define DMAMUX_RGSR_OF2_Pos                    (2U)
-#define DMAMUX_RGSR_OF2_Msk                    (0x1UL << DMAMUX_RGSR_OF2_Pos)  /*!< 0x00000004 */
-#define DMAMUX_RGSR_OF2                        DMAMUX_RGSR_OF2_Msk             /*!< Overrun flag 2                       */
-#define DMAMUX_RGSR_OF3_Pos                    (3U)
-#define DMAMUX_RGSR_OF3_Msk                    (0x1UL << DMAMUX_RGSR_OF3_Pos)  /*!< 0x00000008 */
-#define DMAMUX_RGSR_OF3                        DMAMUX_RGSR_OF3_Msk             /*!< Overrun flag 3                       */
-
-/********************  Bits definition for DMAMUX_RGCFR register  **************/
-#define DMAMUX_RGCFR_COF0_Pos                  (0U)
-#define DMAMUX_RGCFR_COF0_Msk                  (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
-#define DMAMUX_RGCFR_COF0                      DMAMUX_RGCFR_COF0_Msk           /*!< Clear Overrun flag 0                 */
-#define DMAMUX_RGCFR_COF1_Pos                  (1U)
-#define DMAMUX_RGCFR_COF1_Msk                  (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
-#define DMAMUX_RGCFR_COF1                      DMAMUX_RGCFR_COF1_Msk           /*!< Clear Overrun flag 1                 */
-#define DMAMUX_RGCFR_COF2_Pos                  (2U)
-#define DMAMUX_RGCFR_COF2_Msk                  (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
-#define DMAMUX_RGCFR_COF2                      DMAMUX_RGCFR_COF2_Msk           /*!< Clear Overrun flag 2                 */
-#define DMAMUX_RGCFR_COF3_Pos                  (3U)
-#define DMAMUX_RGCFR_COF3_Msk                  (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
-#define DMAMUX_RGCFR_COF3                      DMAMUX_RGCFR_COF3_Msk           /*!< Clear Overrun flag 3                 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Asynchronous Interrupt/Event Controller                 */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for EXTI_RTSR1 register  ******************/
-#define EXTI_RTSR1_RT0_Pos       (0U)
-#define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */
-#define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR1_RT1_Pos       (1U)
-#define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */
-#define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR1_RT2_Pos       (2U)
-#define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */
-#define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR1_RT3_Pos       (3U)
-#define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */
-#define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR1_RT4_Pos       (4U)
-#define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */
-#define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR1_RT5_Pos       (5U)
-#define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */
-#define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR1_RT6_Pos       (6U)
-#define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */
-#define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR1_RT7_Pos       (7U)
-#define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */
-#define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR1_RT8_Pos       (8U)
-#define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */
-#define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR1_RT9_Pos       (9U)
-#define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */
-#define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR1_RT10_Pos      (10U)
-#define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */
-#define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR1_RT11_Pos      (11U)
-#define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */
-#define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR1_RT12_Pos      (12U)
-#define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */
-#define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR1_RT13_Pos      (13U)
-#define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */
-#define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR1_RT14_Pos      (14U)
-#define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */
-#define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR1_RT15_Pos      (15U)
-#define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */
-#define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR1_RT16_Pos      (16U)
-#define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */
-#define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR1_RT21_Pos      (21U)
-#define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */
-#define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR1_RT22_Pos      (22U)
-#define EXTI_RTSR1_RT22_Msk      (0x1UL << EXTI_RTSR1_RT22_Pos)                /*!< 0x00400000 */
-#define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR1 register  ******************/
-#define EXTI_FTSR1_FT0_Pos       (0U)
-#define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */
-#define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR1_FT1_Pos       (1U)
-#define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */
-#define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR1_FT2_Pos       (2U)
-#define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */
-#define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR1_FT3_Pos       (3U)
-#define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */
-#define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR1_FT4_Pos       (4U)
-#define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */
-#define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR1_FT5_Pos       (5U)
-#define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */
-#define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR1_FT6_Pos       (6U)
-#define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */
-#define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR1_FT7_Pos       (7U)
-#define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */
-#define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR1_FT8_Pos       (8U)
-#define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */
-#define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR1_FT9_Pos       (9U)
-#define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */
-#define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR1_FT10_Pos      (10U)
-#define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */
-#define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR1_FT11_Pos      (11U)
-#define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */
-#define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR1_FT12_Pos      (12U)
-#define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */
-#define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR1_FT13_Pos      (13U)
-#define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */
-#define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR1_FT14_Pos      (14U)
-#define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */
-#define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR1_FT15_Pos      (15U)
-#define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */
-#define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR1_FT16_Pos      (16U)
-#define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */
-#define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR1_FT21_Pos      (21U)
-#define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */
-#define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR1_FT22_Pos      (22U)
-#define EXTI_FTSR1_FT22_Msk      (0x1UL << EXTI_FTSR1_FT22_Pos)                /*!< 0x00400000 */
-#define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER1 register  *****************/
-#define EXTI_SWIER1_SWI0_Pos     (0U)
-#define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */
-#define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER1_SWI1_Pos     (1U)
-#define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */
-#define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER1_SWI2_Pos     (2U)
-#define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */
-#define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER1_SWI3_Pos     (3U)
-#define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */
-#define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER1_SWI4_Pos     (4U)
-#define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */
-#define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER1_SWI5_Pos     (5U)
-#define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */
-#define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER1_SWI6_Pos     (6U)
-#define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */
-#define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER1_SWI7_Pos     (7U)
-#define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */
-#define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER1_SWI8_Pos     (8U)
-#define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */
-#define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER1_SWI9_Pos     (9U)
-#define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */
-#define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER1_SWI10_Pos    (10U)
-#define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */
-#define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER1_SWI11_Pos    (11U)
-#define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */
-#define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER1_SWI12_Pos    (12U)
-#define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */
-#define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER1_SWI13_Pos    (13U)
-#define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */
-#define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER1_SWI14_Pos    (14U)
-#define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */
-#define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER1_SWI15_Pos    (15U)
-#define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */
-#define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER1_SWI16_Pos    (16U)
-#define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */
-#define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER1_SWI21_Pos    (21U)
-#define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */
-#define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER1_SWI22_Pos    (22U)
-#define EXTI_SWIER1_SWI22_Msk    (0x1UL << EXTI_SWIER1_SWI22_Pos)              /*!< 0x00400000 */
-#define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR1 register  *******************/
-#define EXTI_PR1_PIF0_Pos        (0U)
-#define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */
-#define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
-#define EXTI_PR1_PIF1_Pos        (1U)
-#define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */
-#define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
-#define EXTI_PR1_PIF2_Pos        (2U)
-#define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */
-#define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
-#define EXTI_PR1_PIF3_Pos        (3U)
-#define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */
-#define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
-#define EXTI_PR1_PIF4_Pos        (4U)
-#define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */
-#define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
-#define EXTI_PR1_PIF5_Pos        (5U)
-#define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */
-#define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
-#define EXTI_PR1_PIF6_Pos        (6U)
-#define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */
-#define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
-#define EXTI_PR1_PIF7_Pos        (7U)
-#define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */
-#define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
-#define EXTI_PR1_PIF8_Pos        (8U)
-#define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */
-#define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
-#define EXTI_PR1_PIF9_Pos        (9U)
-#define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */
-#define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
-#define EXTI_PR1_PIF10_Pos       (10U)
-#define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */
-#define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
-#define EXTI_PR1_PIF11_Pos       (11U)
-#define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */
-#define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
-#define EXTI_PR1_PIF12_Pos       (12U)
-#define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */
-#define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
-#define EXTI_PR1_PIF13_Pos       (13U)
-#define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */
-#define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
-#define EXTI_PR1_PIF14_Pos       (14U)
-#define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */
-#define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
-#define EXTI_PR1_PIF15_Pos       (15U)
-#define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */
-#define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
-#define EXTI_PR1_PIF16_Pos       (16U)
-#define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */
-#define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
-#define EXTI_PR1_PIF21_Pos       (21U)
-#define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */
-#define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
-#define EXTI_PR1_PIF22_Pos       (22U)
-#define EXTI_PR1_PIF22_Msk       (0x1UL << EXTI_PR1_PIF22_Pos)                 /*!< 0x00400000 */
-#define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
-
-/******************  Bit definition for EXTI_RTSR2 register  ******************/
-#define EXTI_RTSR2_RT34_Pos      (2U)
-#define EXTI_RTSR2_RT34_Msk      (0x1UL << EXTI_RTSR2_RT34_Pos)                /*!< 0x00000004 */
-#define EXTI_RTSR2_RT34          EXTI_RTSR2_RT34_Msk                           /*!< Rising trigger event configuration bit of line 34 */
-#define EXTI_RTSR2_RT45_Pos      (13U)
-#define EXTI_RTSR2_RT45_Msk      (0x1UL << EXTI_RTSR2_RT45_Pos)                /*!< 0x00002000 */
-#define EXTI_RTSR2_RT45          EXTI_RTSR2_RT45_Msk                           /*!< Rising trigger event configuration bit of line 45 */
-
-/******************  Bit definition for EXTI_FTSR2 register  ******************/
-#define EXTI_FTSR2_FT34_Pos      (2U)
-#define EXTI_FTSR2_FT34_Msk      (0x1UL << EXTI_FTSR2_FT34_Pos)                /*!< 0x00000004 */
-#define EXTI_FTSR2_FT34          EXTI_FTSR2_FT34_Msk                           /*!< Falling trigger event configuration bit of line 34 */
-#define EXTI_FTSR2_FT45_Pos      (13U)
-#define EXTI_FTSR2_FT45_Msk      (0x1UL << EXTI_FTSR2_FT45_Pos)                /*!< 0x00002000 */
-#define EXTI_FTSR2_FT45          EXTI_FTSR2_FT45_Msk                           /*!< Falling trigger event configuration bit of line 45 */
-
-/******************  Bit definition for EXTI_SWIER2 register  *****************/
-#define EXTI_SWIER2_SWI34_Pos    (2U)
-#define EXTI_SWIER2_SWI34_Msk    (0x1UL << EXTI_SWIER2_SWI34_Pos)              /*!< 0x00000004 */
-#define EXTI_SWIER2_SWI34        EXTI_SWIER2_SWI34_Msk                         /*!< Software Interrupt on line 34 */
-#define EXTI_SWIER2_SWI45_Pos    (13U)
-#define EXTI_SWIER2_SWI45_Msk    (0x1UL << EXTI_SWIER2_SWI45_Pos)              /*!< 0x00002000 */
-#define EXTI_SWIER2_SWI45        EXTI_SWIER2_SWI45_Msk                         /*!< Software Interrupt on line 45 */
-
-/*******************  Bit definition for EXTI_PR2 register  *******************/
-#define EXTI_PR2_PIF34_Pos       (2U)
-#define EXTI_PR2_PIF34_Msk       (0x1UL << EXTI_PR2_PIF34_Pos)                 /*!< 0x00000004 */
-#define EXTI_PR2_PIF34           EXTI_PR2_PIF34_Msk                            /*!< Pending bit for line 34 */
-#define EXTI_PR2_PIF45_Pos       (13U)
-#define EXTI_PR2_PIF45_Msk       (0x1UL << EXTI_PR2_PIF45_Pos)                 /*!< 0x00002000 */
-#define EXTI_PR2_PIF45           EXTI_PR2_PIF45_Msk                            /*!< Pending bit for line 45 */
-
-/********************  Bits definition for EXTI_IMR1 register  **************/
-#define EXTI_IMR1_IM0_Pos        (0U)
-#define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */
-#define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< CPU1 Interrupt Mask on line 0 */
-#define EXTI_IMR1_IM1_Pos        (1U)
-#define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */
-#define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< CPU1 Interrupt Mask on line 1 */
-#define EXTI_IMR1_IM2_Pos        (2U)
-#define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */
-#define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< CPU1 Interrupt Mask on line 2 */
-#define EXTI_IMR1_IM3_Pos        (3U)
-#define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */
-#define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< CPU1 Interrupt Mask on line 3 */
-#define EXTI_IMR1_IM4_Pos        (4U)
-#define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */
-#define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< CPU1 Interrupt Mask on line 4 */
-#define EXTI_IMR1_IM5_Pos        (5U)
-#define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */
-#define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< CPU1 Interrupt Mask on line 5 */
-#define EXTI_IMR1_IM6_Pos        (6U)
-#define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */
-#define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< CPU1 Interrupt Mask on line 6 */
-#define EXTI_IMR1_IM7_Pos        (7U)
-#define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */
-#define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< CPU1 Interrupt Mask on line 7 */
-#define EXTI_IMR1_IM8_Pos        (8U)
-#define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */
-#define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< CPU1 Interrupt Mask on line 8 */
-#define EXTI_IMR1_IM9_Pos        (9U)
-#define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */
-#define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< CPU1 Interrupt Mask on line 9 */
-#define EXTI_IMR1_IM10_Pos       (10U)
-#define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */
-#define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< CPU1 Interrupt Mask on line 10 */
-#define EXTI_IMR1_IM11_Pos       (11U)
-#define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */
-#define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< CPU1 Interrupt Mask on line 11 */
-#define EXTI_IMR1_IM12_Pos       (12U)
-#define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */
-#define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< CPU1 Interrupt Mask on line 12 */
-#define EXTI_IMR1_IM13_Pos       (13U)
-#define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */
-#define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< CPU1 Interrupt Mask on line 13 */
-#define EXTI_IMR1_IM14_Pos       (14U)
-#define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */
-#define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< CPU1 Interrupt Mask on line 14 */
-#define EXTI_IMR1_IM15_Pos       (15U)
-#define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */
-#define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< CPU1 Interrupt Mask on line 15 */
-#define EXTI_IMR1_IM16_Pos       (16U)
-#define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */
-#define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< CPU1 Interrupt Mask on line 16 */
-#define EXTI_IMR1_IM17_Pos       (17U)
-#define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */
-#define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< CPU1 Interrupt Mask on line 17 */
-#define EXTI_IMR1_IM18_Pos       (18U)
-#define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */
-#define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< CPU1 Interrupt Mask on line 18 */
-#define EXTI_IMR1_IM19_Pos       (19U)
-#define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */
-#define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< CPU1 Interrupt Mask on line 19 */
-#define EXTI_IMR1_IM20_Pos       (20U)
-#define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */
-#define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< CPU1 Interrupt Mask on line 20 */
-#define EXTI_IMR1_IM21_Pos       (21U)
-#define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */
-#define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< CPU1 Interrupt Mask on line 21 */
-#define EXTI_IMR1_IM22_Pos       (22U)
-#define EXTI_IMR1_IM22_Msk       (0x1UL << EXTI_IMR1_IM22_Pos)                 /*!< 0x00400000 */
-#define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< CPU1 Interrupt Mask on line 22 */
-#define EXTI_IMR1_IM23_Pos       (23U)
-#define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */
-#define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< CPU1 Interrupt Mask on line 23 */
-#define EXTI_IMR1_IM24_Pos       (24U)
-#define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */
-#define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< CPU1 Interrupt Mask on line 24 */
-#define EXTI_IMR1_IM25_Pos       (25U)
-#define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */
-#define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< CPU1 Interrupt Mask on line 25 */
-#define EXTI_IMR1_IM26_Pos       (26U)
-#define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */
-#define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< CPU1 Interrupt Mask on line 26 */
-#define EXTI_IMR1_IM27_Pos       (27U)
-#define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */
-#define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< CPU1 Interrupt Mask on line 27 */
-#define EXTI_IMR1_IM28_Pos       (28U)
-#define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */
-#define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< CPU1 Interrupt Mask on line 28 */
-#define EXTI_IMR1_IM29_Pos       (29U)
-#define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */
-#define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< CPU1 Interrupt Mask on line 29 */
-#define EXTI_IMR1_IM30_Pos       (30U)
-#define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */
-#define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< CPU1 Interrupt Mask on line 30 */
-#define EXTI_IMR1_IM31_Pos       (31U)
-#define EXTI_IMR1_IM31_Msk       (0x1UL << EXTI_IMR1_IM31_Pos)                 /*!< 0x80000000 */
-#define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< CPU1 Interrupt Mask on line 31 */
-
-/********************  Bits definition for EXTI_EMR1 register  **************/
-#define EXTI_EMR1_EM0_Pos        (0U)
-#define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */
-#define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< CPU1 Event Mask on line 0 */
-#define EXTI_EMR1_EM1_Pos        (1U)
-#define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */
-#define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< CPU1 Event Mask on line 1 */
-#define EXTI_EMR1_EM2_Pos        (2U)
-#define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */
-#define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< CPU1 Event Mask on line 2 */
-#define EXTI_EMR1_EM3_Pos        (3U)
-#define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */
-#define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< CPU1 Event Mask on line 3 */
-#define EXTI_EMR1_EM4_Pos        (4U)
-#define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */
-#define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< CPU1 Event Mask on line 4 */
-#define EXTI_EMR1_EM5_Pos        (5U)
-#define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */
-#define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< CPU1 Event Mask on line 5 */
-#define EXTI_EMR1_EM6_Pos        (6U)
-#define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */
-#define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< CPU1 Event Mask on line 6 */
-#define EXTI_EMR1_EM7_Pos        (7U)
-#define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */
-#define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< CPU1 Event Mask on line 7 */
-#define EXTI_EMR1_EM8_Pos        (8U)
-#define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */
-#define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< CPU1 Event Mask on line 8 */
-#define EXTI_EMR1_EM9_Pos        (9U)
-#define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */
-#define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< CPU1 Event Mask on line 9 */
-#define EXTI_EMR1_EM10_Pos       (10U)
-#define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */
-#define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< CPU1 Event Mask on line 10 */
-#define EXTI_EMR1_EM11_Pos       (11U)
-#define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */
-#define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< CPU1 Event Mask on line 11 */
-#define EXTI_EMR1_EM12_Pos       (12U)
-#define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */
-#define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< CPU1 Event Mask on line 12 */
-#define EXTI_EMR1_EM13_Pos       (13U)
-#define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */
-#define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< CPU1 Event Mask on line 13 */
-#define EXTI_EMR1_EM14_Pos       (14U)
-#define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */
-#define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< CPU1 Event Mask on line 14 */
-#define EXTI_EMR1_EM15_Pos       (15U)
-#define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */
-#define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< CPU1 Event Mask on line 15 */
-#define EXTI_EMR1_EM17_Pos       (17U)
-#define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */
-#define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< CPU1 Event Mask on line 17 */
-#define EXTI_EMR1_EM19_Pos       (19U)
-#define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */
-#define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< CPU1 Event Mask on line 19 */
-#define EXTI_EMR1_EM20_Pos       (20U)
-#define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */
-#define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< CPU1 Event Mask on line 20 */
-#define EXTI_EMR1_EM21_Pos       (21U)
-#define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */
-#define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< CPU1 Event Mask on line 21 */
-#define EXTI_EMR1_EM22_Pos       (22U)
-#define EXTI_EMR1_EM22_Msk       (0x1UL << EXTI_EMR1_EM22_Pos)                 /*!< 0x00400000 */
-#define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< CPU1 Event Mask on line 22 */
-
-/********************  Bits definition for EXTI_IMR2 register  **************/
-#define EXTI_IMR2_IM34_Pos       (2U)
-#define EXTI_IMR2_IM34_Msk       (0x1UL << EXTI_IMR2_IM34_Pos)                 /*!< 0x00000004 */
-#define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< CPU1 Interrupt Mask on line 34 */
-#define EXTI_IMR2_IM38_Pos       (6U)
-#define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */
-#define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< CPU1 Interrupt Mask on line 38 */
-#define EXTI_IMR2_IM42_Pos       (10U)
-#define EXTI_IMR2_IM42_Msk       (0x1UL << EXTI_IMR2_IM42_Pos)                 /*!< 0x00000400 */
-#define EXTI_IMR2_IM42           EXTI_IMR2_IM42_Msk                            /*!< CPU1 Interrupt Mask on line 42 */
-#define EXTI_IMR2_IM43_Pos       (11U)
-#define EXTI_IMR2_IM43_Msk       (0x1UL << EXTI_IMR2_IM43_Pos)                 /*!< 0x00000800 */
-#define EXTI_IMR2_IM43           EXTI_IMR2_IM43_Msk                            /*!< CPU1 Interrupt Mask on line 43 */
-#define EXTI_IMR2_IM44_Pos       (12U)
-#define EXTI_IMR2_IM44_Msk       (0x1UL << EXTI_IMR2_IM44_Pos)                 /*!< 0x00001000 */
-#define EXTI_IMR2_IM44           EXTI_IMR2_IM44_Msk                            /*!< CPU1 Interrupt Mask on line 44 */
-#define EXTI_IMR2_IM45_Pos       (13U)
-#define EXTI_IMR2_IM45_Msk       (0x1UL << EXTI_IMR2_IM45_Pos)                 /*!< 0x00002000 */
-#define EXTI_IMR2_IM45           EXTI_IMR2_IM45_Msk                            /*!< CPU1 Interrupt Mask on line 45 */
-#define EXTI_IMR2_IM46_Pos       (14U)
-#define EXTI_IMR2_IM46_Msk       (0x1UL << EXTI_IMR2_IM46_Pos)                 /*!< 0x00004000 */
-#define EXTI_IMR2_IM46           EXTI_IMR2_IM46_Msk                            /*!< CPU1 Interrupt Mask on line 46 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY_Pos               (0U)
-#define FLASH_ACR_LATENCY_Msk               (0x7UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000007 */
-#define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk              /*!< Latency                                             */
-#define FLASH_ACR_LATENCY_0                 (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY_1                 (0x2UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN_Pos                (8U)
-#define FLASH_ACR_PRFTEN_Msk                (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000100 */
-#define FLASH_ACR_PRFTEN                    FLASH_ACR_PRFTEN_Msk               /*!< Prefetch enable                                     */
-#define FLASH_ACR_ICEN_Pos                  (9U)
-#define FLASH_ACR_ICEN_Msk                  (0x1UL << FLASH_ACR_ICEN_Pos)      /*!< 0x00000200 */
-#define FLASH_ACR_ICEN                      FLASH_ACR_ICEN_Msk                 /*!< Instruction cache enable                            */
-#define FLASH_ACR_DCEN_Pos                  (10U)
-#define FLASH_ACR_DCEN_Msk                  (0x1UL << FLASH_ACR_DCEN_Pos)      /*!< 0x00000400 */
-#define FLASH_ACR_DCEN                      FLASH_ACR_DCEN_Msk                 /*!< Data cache enable                                   */
-#define FLASH_ACR_ICRST_Pos                 (11U)
-#define FLASH_ACR_ICRST_Msk                 (0x1UL << FLASH_ACR_ICRST_Pos)     /*!< 0x00000800 */
-#define FLASH_ACR_ICRST                     FLASH_ACR_ICRST_Msk                /*!< Instruction cache reset                             */
-#define FLASH_ACR_DCRST_Pos                 (12U)
-#define FLASH_ACR_DCRST_Msk                 (0x1UL << FLASH_ACR_DCRST_Pos)     /*!< 0x00001000 */
-#define FLASH_ACR_DCRST                     FLASH_ACR_DCRST_Msk                /*!< Data cache reset                                    */
-#define FLASH_ACR_PES_Pos                   (15U)
-#define FLASH_ACR_PES_Msk                   (0x1UL << FLASH_ACR_PES_Pos)       /*!< 0x00008000 */
-#define FLASH_ACR_PES                       FLASH_ACR_PES_Msk                  /*!< Program/erase suspend request                       */
-#define FLASH_ACR_EMPTY_Pos                 (16U)
-#define FLASH_ACR_EMPTY_Msk                 (0x1UL << FLASH_ACR_EMPTY_Pos)     /*!< 0x00010000 */
-#define FLASH_ACR_EMPTY                     FLASH_ACR_EMPTY_Msk                /*!< Flash use area empty                                */
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP_Pos                    (0U)
-#define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                   /*!< End of Operation                                    */
-#define FLASH_SR_OPERR_Pos                  (1U)
-#define FLASH_SR_OPERR_Msk                  (0x1UL << FLASH_SR_OPERR_Pos)      /*!< 0x00000002 */
-#define FLASH_SR_OPERR                      FLASH_SR_OPERR_Msk                 /*!< Operation error                                     */
-#define FLASH_SR_PROGERR_Pos                (3U)
-#define FLASH_SR_PROGERR_Msk                (0x1UL << FLASH_SR_PROGERR_Pos)    /*!< 0x00000008 */
-#define FLASH_SR_PROGERR                    FLASH_SR_PROGERR_Msk               /*!< Programming error                                   */
-#define FLASH_SR_WRPERR_Pos                 (4U)
-#define FLASH_SR_WRPERR_Msk                 (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000010 */
-#define FLASH_SR_WRPERR                     FLASH_SR_WRPERR_Msk                /*!< Write protection error                              */
-#define FLASH_SR_PGAERR_Pos                 (5U)
-#define FLASH_SR_PGAERR_Msk                 (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000020 */
-#define FLASH_SR_PGAERR                     FLASH_SR_PGAERR_Msk                /*!< Programming alignment error                         */
-#define FLASH_SR_SIZERR_Pos                 (6U)
-#define FLASH_SR_SIZERR_Msk                 (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000040 */
-#define FLASH_SR_SIZERR                     FLASH_SR_SIZERR_Msk                /*!< Size error                                          */
-#define FLASH_SR_PGSERR_Pos                 (7U)
-#define FLASH_SR_PGSERR_Msk                 (0x1UL << FLASH_SR_PGSERR_Pos)     /*!< 0x00000080 */
-#define FLASH_SR_PGSERR                     FLASH_SR_PGSERR_Msk                /*!< Programming sequence error                          */
-#define FLASH_SR_MISERR_Pos                 (8U)
-#define FLASH_SR_MISERR_Msk                 (0x1UL << FLASH_SR_MISERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_MISERR                     FLASH_SR_MISERR_Msk                /*!< Fast programming data miss error                    */
-#define FLASH_SR_FASTERR_Pos                (9U)
-#define FLASH_SR_FASTERR_Msk                (0x1UL << FLASH_SR_FASTERR_Pos)    /*!< 0x00000200 */
-#define FLASH_SR_FASTERR                    FLASH_SR_FASTERR_Msk               /*!< Fast programming error                              */
-#define FLASH_SR_OPTNV_Pos                  (13U)
-#define FLASH_SR_OPTNV_Msk                  (0x1UL << FLASH_SR_OPTNV_Pos)     /*!< 0x00002000 */
-#define FLASH_SR_OPTNV                      FLASH_SR_OPTNV_Msk                /*!< User option OPTVAL indication                       */
-#define FLASH_SR_RDERR_Pos                  (14U)
-#define FLASH_SR_RDERR_Msk                  (0x1UL << FLASH_SR_RDERR_Pos)      /*!< 0x00004000 */
-#define FLASH_SR_RDERR                      FLASH_SR_RDERR_Msk                 /*!< PCROP read error                                    */
-#define FLASH_SR_OPTVERR_Pos                (15U)
-#define FLASH_SR_OPTVERR_Msk                (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00008000 */
-#define FLASH_SR_OPTVERR                    FLASH_SR_OPTVERR_Msk               /*!< Option validity error                               */
-#define FLASH_SR_BSY_Pos                    (16U)
-#define FLASH_SR_BSY_Msk                    (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00010000 */
-#define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                   /*!< Flash Busy                                          */
-#define FLASH_SR_CFGBSY_Pos                 (18U)
-#define FLASH_SR_CFGBSY_Msk                 (0x1UL << FLASH_SR_CFGBSY_Pos)     /*!< 0x00040000 */
-#define FLASH_SR_CFGBSY                     FLASH_SR_CFGBSY_Msk                /*!< Programming or erase configuration busy             */
-#define FLASH_SR_PESD_Pos                   (19U)
-#define FLASH_SR_PESD_Msk                   (0x1UL << FLASH_SR_PESD_Pos)       /*!< 0x00080000 */
-#define FLASH_SR_PESD                       FLASH_SR_PESD_Msk                  /*!< Programming/erase operation suspended               */
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG_Pos                     (0U)
-#define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)         /*!< 0x00000001 */
-#define FLASH_CR_PG                         FLASH_CR_PG_Msk                    /*!< Flash programming                                   */
-#define FLASH_CR_PER_Pos                    (1U)
-#define FLASH_CR_PER_Msk                    (0x1UL << FLASH_CR_PER_Pos)        /*!< 0x00000002 */
-#define FLASH_CR_PER                        FLASH_CR_PER_Msk                   /*!< Page erase                                          */
-#define FLASH_CR_MER_Pos                    (2U)
-#define FLASH_CR_MER_Msk                    (0x1UL << FLASH_CR_MER_Pos)        /*!< 0x00000004 */
-#define FLASH_CR_MER                        FLASH_CR_MER_Msk                   /*!< Mass erase                                          */
-#define FLASH_CR_PNB_Pos                    (3U)
-#define FLASH_CR_PNB_Msk                    (0x7FUL << FLASH_CR_PNB_Pos)       /*!< 0x000003F8 */
-#define FLASH_CR_PNB                        FLASH_CR_PNB_Msk                   /*!< Page number selection mask                          */
-#define FLASH_CR_STRT_Pos                   (16U)
-#define FLASH_CR_STRT_Msk                   (0x1UL << FLASH_CR_STRT_Pos)       /*!< 0x00010000 */
-#define FLASH_CR_STRT                       FLASH_CR_STRT_Msk                  /*!< Start an erase operation                            */
-#define FLASH_CR_OPTSTRT_Pos                (17U)
-#define FLASH_CR_OPTSTRT_Msk                (0x1UL << FLASH_CR_OPTSTRT_Pos)    /*!< 0x00020000 */
-#define FLASH_CR_OPTSTRT                    FLASH_CR_OPTSTRT_Msk               /*!< Options modification start                          */
-#define FLASH_CR_FSTPG_Pos                  (18U)
-#define FLASH_CR_FSTPG_Msk                  (0x1UL << FLASH_CR_FSTPG_Pos)      /*!< 0x00040000 */
-#define FLASH_CR_FSTPG                      FLASH_CR_FSTPG_Msk                 /*!< Fast programming                                    */
-#define FLASH_CR_EOPIE_Pos                  (24U)
-#define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)      /*!< 0x01000000 */
-#define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                 /*!< End of operation interrupt enable                   */
-#define FLASH_CR_ERRIE_Pos                  (25U)
-#define FLASH_CR_ERRIE_Msk                  (0x1UL << FLASH_CR_ERRIE_Pos)      /*!< 0x02000000 */
-#define FLASH_CR_ERRIE                      FLASH_CR_ERRIE_Msk                 /*!< Error interrupt enable                              */
-#define FLASH_CR_RDERRIE_Pos                (26U)
-#define FLASH_CR_RDERRIE_Msk                (0x1UL << FLASH_CR_RDERRIE_Pos)    /*!< 0x04000000 */
-#define FLASH_CR_RDERRIE                    FLASH_CR_RDERRIE_Msk               /*!< PCROP read error interrupt enable                   */
-#define FLASH_CR_OBL_LAUNCH_Pos             (27U)
-#define FLASH_CR_OBL_LAUNCH_Msk             (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
-#define FLASH_CR_OBL_LAUNCH                 FLASH_CR_OBL_LAUNCH_Msk            /*!< Force the option bute loading                       */
-#define FLASH_CR_OPTLOCK_Pos                (30U)
-#define FLASH_CR_OPTLOCK_Msk                (0x1UL << FLASH_CR_OPTLOCK_Pos)    /*!< 0x40000000 */
-#define FLASH_CR_OPTLOCK                    FLASH_CR_OPTLOCK_Msk               /*!< Options lock                                        */
-#define FLASH_CR_LOCK_Pos                   (31U)
-#define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)       /*!< 0x80000000 */
-#define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                  /*!< Flash control register lock                         */
-
-/*******************  Bits definition for FLASH_ECCR register  ****************/
-#define FLASH_ECCR_ADDR_ECC_Pos             (0U)
-#define FLASH_ECCR_ADDR_ECC_Msk             (0x1FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0001FFFF */
-#define FLASH_ECCR_ADDR_ECC                 FLASH_ECCR_ADDR_ECC_Msk            /*!< double-word address ECC fail                        */
-#define FLASH_ECCR_SYSF_ECC_Pos             (20U)
-#define FLASH_ECCR_SYSF_ECC_Msk             (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
-#define FLASH_ECCR_SYSF_ECC                 FLASH_ECCR_SYSF_ECC_Msk            /*!< System flash ECC fail                               */
-#define FLASH_ECCR_ECCCIE_Pos               (24U)
-#define FLASH_ECCR_ECCCIE_Msk               (0x1UL << FLASH_ECCR_ECCCIE_Pos)   /*!< 0x01000000 */
-#define FLASH_ECCR_ECCCIE                   FLASH_ECCR_ECCCIE_Msk              /*!< ECC correction interrupt enable                     */
-#define FLASH_ECCR_CPUID_Pos                (26U)
-#define FLASH_ECCR_CPUID_Msk                (0x7UL << FLASH_ECCR_CPUID_Pos)    /*!< 0x1C000000 */
-#define FLASH_ECCR_CPUID                    FLASH_ECCR_CPUID_Msk               /*!< CPU identification                                  */
-#define FLASH_ECCR_ECCC_Pos                 (30U)
-#define FLASH_ECCR_ECCC_Msk                 (0x1UL << FLASH_ECCR_ECCC_Pos)     /*!< 0x40000000 */
-#define FLASH_ECCR_ECCC                     FLASH_ECCR_ECCC_Msk                /*!< ECC correction                                      */
-#define FLASH_ECCR_ECCD_Pos                 (31U)
-#define FLASH_ECCR_ECCD_Msk                 (0x1UL << FLASH_ECCR_ECCD_Pos)     /*!< 0x80000000 */
-#define FLASH_ECCR_ECCD                     FLASH_ECCR_ECCD_Msk                /*!< ECC detection                                       */
-
-/*******************  Bits definition for FLASH_OPTR register  ****************/
-#define FLASH_OPTR_RDP_Pos                  (0U)
-#define FLASH_OPTR_RDP_Msk                  (0xFFUL << FLASH_OPTR_RDP_Pos)     /*!< 0x000000FF */
-#define FLASH_OPTR_RDP                      FLASH_OPTR_RDP_Msk                 /*!< Read protection level                               */
-#define FLASH_OPTR_ESE_Pos                  (8U)
-#define FLASH_OPTR_ESE_Msk                  (0x1UL << FLASH_OPTR_ESE_Pos)      /*!< 0x00000100 */
-#define FLASH_OPTR_ESE                      FLASH_OPTR_ESE_Msk                 /*!< Security enable                                     */
-#define FLASH_OPTR_BOR_LEV_Pos              (9U)
-#define FLASH_OPTR_BOR_LEV_Msk              (0x7UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000E00 */
-#define FLASH_OPTR_BOR_LEV                  FLASH_OPTR_BOR_LEV_Msk             /*!< BOR reset level mask                                */
-#define FLASH_OPTR_BOR_LEV_0                (0x1UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000200 */
-#define FLASH_OPTR_BOR_LEV_1                (0x2UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000400 */
-#define FLASH_OPTR_BOR_LEV_2                (0x4UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000800 */
-#define FLASH_OPTR_nRST_STOP_Pos            (12U)
-#define FLASH_OPTR_nRST_STOP_Msk            (0x1UL << FLASH_OPTR_nRST_STOP_Pos)/*!< 0x00001000 */
-#define FLASH_OPTR_nRST_STOP                FLASH_OPTR_nRST_STOP_Msk           /*!< Reset option in Stop mode                           */
-#define FLASH_OPTR_nRST_STDBY_Pos           (13U)
-#define FLASH_OPTR_nRST_STDBY_Msk           (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)/*!< 0x00002000 */
-#define FLASH_OPTR_nRST_STDBY               FLASH_OPTR_nRST_STDBY_Msk          /*!< Reset option in Standby mode                        */
-#define FLASH_OPTR_nRST_SHDW_Pos            (14U)
-#define FLASH_OPTR_nRST_SHDW_Msk            (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)/*!< 0x00004000 */
-#define FLASH_OPTR_nRST_SHDW                FLASH_OPTR_nRST_SHDW_Msk           /*!< Reset option in Shutdown mode                       */
-#define FLASH_OPTR_IWDG_SW_Pos              (16U)
-#define FLASH_OPTR_IWDG_SW_Msk              (0x1UL << FLASH_OPTR_IWDG_SW_Pos)  /*!< 0x00010000 */
-#define FLASH_OPTR_IWDG_SW                  FLASH_OPTR_IWDG_SW_Msk             /*!< Independent watchdog selection                      */
-#define FLASH_OPTR_IWDG_STOP_Pos            (17U)
-#define FLASH_OPTR_IWDG_STOP_Msk            (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)/*!< 0x00020000 */
-#define FLASH_OPTR_IWDG_STOP                FLASH_OPTR_IWDG_STOP_Msk           /*!< Independent watchdog counter option in Stop mode    */
-#define FLASH_OPTR_IWDG_STDBY_Pos           (18U)
-#define FLASH_OPTR_IWDG_STDBY_Msk           (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)/*!< 0x00040000 */
-#define FLASH_OPTR_IWDG_STDBY               FLASH_OPTR_IWDG_STDBY_Msk          /*!< Independent watchdog counter option in Standby mode */
-#define FLASH_OPTR_WWDG_SW_Pos              (19U)
-#define FLASH_OPTR_WWDG_SW_Msk              (0x1UL << FLASH_OPTR_WWDG_SW_Pos)  /*!< 0x00080000 */
-#define FLASH_OPTR_WWDG_SW                  FLASH_OPTR_WWDG_SW_Msk             /*!< Window watchdog selection                           */
-#define FLASH_OPTR_nBOOT1_Pos               (23U)
-#define FLASH_OPTR_nBOOT1_Msk               (0x1UL << FLASH_OPTR_nBOOT1_Pos)   /*!< 0x00800000 */
-#define FLASH_OPTR_nBOOT1                   FLASH_OPTR_nBOOT1_Msk              /*!< Boot Configuration                                  */
-#define FLASH_OPTR_SRAM2_PE_Pos             (24U)
-#define FLASH_OPTR_SRAM2_PE_Msk             (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
-#define FLASH_OPTR_SRAM2_PE                 FLASH_OPTR_SRAM2_PE_Msk            /*!< SRAM2 parity check enable                           */
-#define FLASH_OPTR_SRAM_RST_Pos             (25U)
-#define FLASH_OPTR_SRAM_RST_Msk             (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x02000000 */
-#define FLASH_OPTR_SRAM_RST                 FLASH_OPTR_SRAM_RST_Msk            /*!< SRAM1 and SRAM2 erase option when system reset      */
-#define FLASH_OPTR_nSWBOOT0_Pos             (26U)
-#define FLASH_OPTR_nSWBOOT0_Msk             (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
-#define FLASH_OPTR_nSWBOOT0                 FLASH_OPTR_nSWBOOT0_Msk            /*!< Software BOOT0                                      */
-#define FLASH_OPTR_nBOOT0_Pos               (27U)
-#define FLASH_OPTR_nBOOT0_Msk               (0x1UL << FLASH_OPTR_nBOOT0_Pos)   /*!< 0x08000000 */
-#define FLASH_OPTR_nBOOT0                   FLASH_OPTR_nBOOT0_Msk              /*!< BOOT0 option bit                                    */
-#define FLASH_OPTR_BOOT_LOCK_Pos            (30U)
-#define FLASH_OPTR_BOOT_LOCK_Msk            (0x1UL << FLASH_OPTR_BOOT_LOCK_Pos)/*!< 0x40000000 */
-#define FLASH_OPTR_BOOT_LOCK                FLASH_OPTR_BOOT_LOCK_Msk           /*!< CPU1 Boot Lock enable option bit                    */
-
-/******************  Bits definition for FLASH_PCROP1ASR register  ************/
-#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos    (0U)
-#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk    (0xFFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1ASR_PCROP1A_STRT        FLASH_PCROP1ASR_PCROP1A_STRT_Msk   /*!< PCROP area A start offset                           */
-
-/******************  Bits definition for FLASH_PCROP1AER register  ************/
-#define FLASH_PCROP1AER_PCROP1A_END_Pos     (0U)
-#define FLASH_PCROP1AER_PCROP1A_END_Msk     (0xFFUL << FLASH_PCROP1AER_PCROP1A_END_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1AER_PCROP1A_END         FLASH_PCROP1AER_PCROP1A_END_Msk    /*!< PCROP area A end offset                             */
-#define FLASH_PCROP1AER_PCROP_RDP_Pos       (31U)
-#define FLASH_PCROP1AER_PCROP_RDP_Msk       (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos)/*!< 0x80000000 */
-#define FLASH_PCROP1AER_PCROP_RDP           FLASH_PCROP1AER_PCROP_RDP_Msk      /*!< PCROP area preserved when RDP level decreased       */
-
-/******************  Bits definition for FLASH_WRP1AR register  ***************/
-#define FLASH_WRP1AR_WRP1A_STRT_Pos         (0U)
-#define FLASH_WRP1AR_WRP1A_STRT_Msk         (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
-#define FLASH_WRP1AR_WRP1A_STRT             FLASH_WRP1AR_WRP1A_STRT_Msk        /*!< WRP area A start offset                             */
-#define FLASH_WRP1AR_WRP1A_END_Pos          (16U)
-#define FLASH_WRP1AR_WRP1A_END_Msk          (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
-#define FLASH_WRP1AR_WRP1A_END              FLASH_WRP1AR_WRP1A_END_Msk         /*!< WRP area A end offset                               */
-
-/******************  Bits definition for FLASH_WRP1BR register  ***************/
-#define FLASH_WRP1BR_WRP1B_STRT_Pos         (0U)
-#define FLASH_WRP1BR_WRP1B_STRT_Msk         (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
-#define FLASH_WRP1BR_WRP1B_STRT             FLASH_WRP1BR_WRP1B_STRT_Msk        /*!< WRP area B start offset                             */
-#define FLASH_WRP1BR_WRP1B_END_Pos          (16U)
-#define FLASH_WRP1BR_WRP1B_END_Msk          (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
-#define FLASH_WRP1BR_WRP1B_END              FLASH_WRP1BR_WRP1B_END_Msk         /*!< WRP area B end offset                               */
-
-/******************  Bits definition for FLASH_PCROP1BSR register  ************/
-#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos    (0U)
-#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk    (0xFFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1BSR_PCROP1B_STRT        FLASH_PCROP1BSR_PCROP1B_STRT_Msk   /*!< PCROP area B start offset                           */
-
-/******************  Bits definition for FLASH_PCROP1BER register  ************/
-#define FLASH_PCROP1BER_PCROP1B_END_Pos     (0U)
-#define FLASH_PCROP1BER_PCROP1B_END_Msk     (0xFFUL << FLASH_PCROP1BER_PCROP1B_END_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1BER_PCROP1B_END         FLASH_PCROP1BER_PCROP1B_END_Msk    /*!< PCROP area B end offset                             */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos           (0U)
-#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
-#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos           (2U)
-#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
-#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos           (4U)
-#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
-#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos           (6U)
-#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
-#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos           (8U)
-#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
-#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos           (10U)
-#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
-#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos           (12U)
-#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
-#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos           (14U)
-#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
-#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos           (16U)
-#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
-#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos           (18U)
-#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
-#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos          (20U)
-#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
-#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos          (22U)
-#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
-#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos          (24U)
-#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
-#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos          (26U)
-#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
-#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos          (28U)
-#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
-#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos          (30U)
-#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
-#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT0_Pos            (0U)
-#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
-#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
-#define GPIO_OTYPER_OT1_Pos            (1U)
-#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
-#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
-#define GPIO_OTYPER_OT2_Pos            (2U)
-#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
-#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
-#define GPIO_OTYPER_OT3_Pos            (3U)
-#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
-#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
-#define GPIO_OTYPER_OT4_Pos            (4U)
-#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
-#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
-#define GPIO_OTYPER_OT5_Pos            (5U)
-#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
-#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
-#define GPIO_OTYPER_OT6_Pos            (6U)
-#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
-#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
-#define GPIO_OTYPER_OT7_Pos            (7U)
-#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
-#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
-#define GPIO_OTYPER_OT8_Pos            (8U)
-#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
-#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
-#define GPIO_OTYPER_OT9_Pos            (9U)
-#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
-#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
-#define GPIO_OTYPER_OT10_Pos           (10U)
-#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
-#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
-#define GPIO_OTYPER_OT11_Pos           (11U)
-#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
-#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
-#define GPIO_OTYPER_OT12_Pos           (12U)
-#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
-#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
-#define GPIO_OTYPER_OT13_Pos           (13U)
-#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
-#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
-#define GPIO_OTYPER_OT14_Pos           (14U)
-#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
-#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
-#define GPIO_OTYPER_OT15_Pos           (15U)
-#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
-#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
-#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
-#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
-#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
-#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
-#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
-#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
-#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
-#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
-#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
-#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
-#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
-#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
-#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
-#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
-#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
-#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
-#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
-#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
-#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
-#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
-#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
-#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
-#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
-#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
-#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
-#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
-#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
-#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
-#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
-#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
-#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
-#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
-#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
-#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
-#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
-#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
-#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
-#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
-#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
-#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
-#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
-#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
-#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
-#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
-#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
-#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
-#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
-#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
-#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
-#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
-#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
-#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
-#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
-#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
-#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
-#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
-#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
-#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
-#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
-#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
-#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
-#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
-#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
-#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
-#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
-#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
-#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
-#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
-#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
-#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
-#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
-#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
-#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
-#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
-#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
-#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
-#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
-#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
-#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPD0_Pos           (0U)
-#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
-#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos           (2U)
-#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
-#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos           (4U)
-#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
-#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos           (6U)
-#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
-#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos           (8U)
-#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
-#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos           (10U)
-#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
-#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos           (12U)
-#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
-#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos           (14U)
-#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
-#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos           (16U)
-#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
-#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos           (18U)
-#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
-#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos          (20U)
-#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
-#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos          (22U)
-#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
-#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos          (24U)
-#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
-#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos          (26U)
-#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
-#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos          (28U)
-#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
-#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos          (30U)
-#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
-#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos               (0U)
-#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
-#define GPIO_IDR_ID1_Pos               (1U)
-#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
-#define GPIO_IDR_ID2_Pos               (2U)
-#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
-#define GPIO_IDR_ID3_Pos               (3U)
-#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
-#define GPIO_IDR_ID4_Pos               (4U)
-#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
-#define GPIO_IDR_ID5_Pos               (5U)
-#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
-#define GPIO_IDR_ID6_Pos               (6U)
-#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
-#define GPIO_IDR_ID7_Pos               (7U)
-#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
-#define GPIO_IDR_ID8_Pos               (8U)
-#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
-#define GPIO_IDR_ID9_Pos               (9U)
-#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
-#define GPIO_IDR_ID10_Pos              (10U)
-#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
-#define GPIO_IDR_ID11_Pos              (11U)
-#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
-#define GPIO_IDR_ID12_Pos              (12U)
-#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
-#define GPIO_IDR_ID13_Pos              (13U)
-#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
-#define GPIO_IDR_ID14_Pos              (14U)
-#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
-#define GPIO_IDR_ID15_Pos              (15U)
-#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_OD0_Pos               (0U)
-#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
-#define GPIO_ODR_OD1_Pos               (1U)
-#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
-#define GPIO_ODR_OD2_Pos               (2U)
-#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
-#define GPIO_ODR_OD3_Pos               (3U)
-#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
-#define GPIO_ODR_OD4_Pos               (4U)
-#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
-#define GPIO_ODR_OD5_Pos               (5U)
-#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
-#define GPIO_ODR_OD6_Pos               (6U)
-#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
-#define GPIO_ODR_OD7_Pos               (7U)
-#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
-#define GPIO_ODR_OD8_Pos               (8U)
-#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
-#define GPIO_ODR_OD9_Pos               (9U)
-#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
-#define GPIO_ODR_OD10_Pos              (10U)
-#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
-#define GPIO_ODR_OD11_Pos              (11U)
-#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
-#define GPIO_ODR_OD12_Pos              (12U)
-#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
-#define GPIO_ODR_OD13_Pos              (13U)
-#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
-#define GPIO_ODR_OD14_Pos              (14U)
-#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
-#define GPIO_ODR_OD15_Pos              (15U)
-#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS0_Pos              (0U)
-#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
-#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
-#define GPIO_BSRR_BS1_Pos              (1U)
-#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
-#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
-#define GPIO_BSRR_BS2_Pos              (2U)
-#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
-#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
-#define GPIO_BSRR_BS3_Pos              (3U)
-#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
-#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
-#define GPIO_BSRR_BS4_Pos              (4U)
-#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
-#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
-#define GPIO_BSRR_BS5_Pos              (5U)
-#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
-#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
-#define GPIO_BSRR_BS6_Pos              (6U)
-#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
-#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
-#define GPIO_BSRR_BS7_Pos              (7U)
-#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
-#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
-#define GPIO_BSRR_BS8_Pos              (8U)
-#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
-#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
-#define GPIO_BSRR_BS9_Pos              (9U)
-#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
-#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
-#define GPIO_BSRR_BS10_Pos             (10U)
-#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
-#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
-#define GPIO_BSRR_BS11_Pos             (11U)
-#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
-#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
-#define GPIO_BSRR_BS12_Pos             (12U)
-#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
-#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
-#define GPIO_BSRR_BS13_Pos             (13U)
-#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
-#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
-#define GPIO_BSRR_BS14_Pos             (14U)
-#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
-#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
-#define GPIO_BSRR_BS15_Pos             (15U)
-#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
-#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
-#define GPIO_BSRR_BR0_Pos              (16U)
-#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
-#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
-#define GPIO_BSRR_BR1_Pos              (17U)
-#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
-#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
-#define GPIO_BSRR_BR2_Pos              (18U)
-#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
-#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
-#define GPIO_BSRR_BR3_Pos              (19U)
-#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
-#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
-#define GPIO_BSRR_BR4_Pos              (20U)
-#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
-#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
-#define GPIO_BSRR_BR5_Pos              (21U)
-#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
-#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
-#define GPIO_BSRR_BR6_Pos              (22U)
-#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
-#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
-#define GPIO_BSRR_BR7_Pos              (23U)
-#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
-#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
-#define GPIO_BSRR_BR8_Pos              (24U)
-#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
-#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
-#define GPIO_BSRR_BR9_Pos              (25U)
-#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
-#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
-#define GPIO_BSRR_BR10_Pos             (26U)
-#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
-#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
-#define GPIO_BSRR_BR11_Pos             (27U)
-#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
-#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
-#define GPIO_BSRR_BR12_Pos             (28U)
-#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
-#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
-#define GPIO_BSRR_BR13_Pos             (29U)
-#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
-#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
-#define GPIO_BSRR_BR14_Pos             (30U)
-#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
-#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
-#define GPIO_BSRR_BR15_Pos             (31U)
-#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
-#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0_Pos             (0U)
-#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
-#define GPIO_LCKR_LCK1_Pos             (1U)
-#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
-#define GPIO_LCKR_LCK2_Pos             (2U)
-#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
-#define GPIO_LCKR_LCK3_Pos             (3U)
-#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
-#define GPIO_LCKR_LCK4_Pos             (4U)
-#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
-#define GPIO_LCKR_LCK5_Pos             (5U)
-#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
-#define GPIO_LCKR_LCK6_Pos             (6U)
-#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
-#define GPIO_LCKR_LCK7_Pos             (7U)
-#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
-#define GPIO_LCKR_LCK8_Pos             (8U)
-#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
-#define GPIO_LCKR_LCK9_Pos             (9U)
-#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
-#define GPIO_LCKR_LCK10_Pos            (10U)
-#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
-#define GPIO_LCKR_LCK11_Pos            (11U)
-#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
-#define GPIO_LCKR_LCK12_Pos            (12U)
-#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
-#define GPIO_LCKR_LCK13_Pos            (13U)
-#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
-#define GPIO_LCKR_LCK14_Pos            (14U)
-#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
-#define GPIO_LCKR_LCK15_Pos            (15U)
-#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
-#define GPIO_LCKR_LCKK_Pos             (16U)
-#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
-
-/****************** Bit definition for GPIO_AFRL register *********************/
-#define GPIO_AFRL_AFSEL0_Pos           (0U)
-#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
-#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
-#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
-#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
-#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
-#define GPIO_AFRL_AFSEL1_Pos           (4U)
-#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
-#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
-#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
-#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
-#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
-#define GPIO_AFRL_AFSEL2_Pos           (8U)
-#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
-#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
-#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
-#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
-#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
-#define GPIO_AFRL_AFSEL3_Pos           (12U)
-#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
-#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
-#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
-#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
-#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
-#define GPIO_AFRL_AFSEL4_Pos           (16U)
-#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
-#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
-#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
-#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
-#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
-#define GPIO_AFRL_AFSEL5_Pos           (20U)
-#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
-#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
-#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
-#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
-#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
-#define GPIO_AFRL_AFSEL6_Pos           (24U)
-#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
-#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
-#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
-#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
-#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
-#define GPIO_AFRL_AFSEL7_Pos           (28U)
-#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
-#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
-#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
-#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
-#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
-
-/****************** Bit definition for GPIO_AFRH register *********************/
-#define GPIO_AFRH_AFSEL8_Pos           (0U)
-#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
-#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
-#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
-#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
-#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
-#define GPIO_AFRH_AFSEL9_Pos           (4U)
-#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
-#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
-#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
-#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
-#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
-#define GPIO_AFRH_AFSEL10_Pos          (8U)
-#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
-#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
-#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
-#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
-#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
-#define GPIO_AFRH_AFSEL11_Pos          (12U)
-#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
-#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
-#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
-#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
-#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
-#define GPIO_AFRH_AFSEL12_Pos          (16U)
-#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
-#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
-#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
-#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
-#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
-#define GPIO_AFRH_AFSEL13_Pos          (20U)
-#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
-#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
-#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
-#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
-#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
-#define GPIO_AFRH_AFSEL14_Pos          (24U)
-#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
-#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
-#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
-#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
-#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
-#define GPIO_AFRH_AFSEL15_Pos          (28U)
-#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
-#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
-#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
-#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
-#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_BRR register  ******************/
-#define GPIO_BRR_BR0_Pos               (0U)
-#define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
-#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
-#define GPIO_BRR_BR1_Pos               (1U)
-#define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
-#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
-#define GPIO_BRR_BR2_Pos               (2U)
-#define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
-#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
-#define GPIO_BRR_BR3_Pos               (3U)
-#define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
-#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
-#define GPIO_BRR_BR4_Pos               (4U)
-#define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
-#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
-#define GPIO_BRR_BR5_Pos               (5U)
-#define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
-#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
-#define GPIO_BRR_BR6_Pos               (6U)
-#define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
-#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
-#define GPIO_BRR_BR7_Pos               (7U)
-#define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
-#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
-#define GPIO_BRR_BR8_Pos               (8U)
-#define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
-#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
-#define GPIO_BRR_BR9_Pos               (9U)
-#define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
-#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
-#define GPIO_BRR_BR10_Pos              (10U)
-#define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
-#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
-#define GPIO_BRR_BR11_Pos              (11U)
-#define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
-#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
-#define GPIO_BRR_BR12_Pos              (12U)
-#define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
-#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
-#define GPIO_BRR_BR13_Pos              (13U)
-#define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
-#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
-#define GPIO_BRR_BR14_Pos              (14U)
-#define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
-#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
-#define GPIO_BRR_BR15_Pos              (15U)
-#define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
-#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                        HSEM HW Semaphore                                   */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for HSEM_R register  ********************/
-#define HSEM_R_PROCID_Pos        (0U)
-#define HSEM_R_PROCID_Msk        (0xFFUL << HSEM_R_PROCID_Pos)                 /*!< 0x000000FF */
-#define HSEM_R_PROCID            HSEM_R_PROCID_Msk                             /*!<Semaphore ProcessID */
-#define HSEM_R_COREID_Pos        (8U)
-#define HSEM_R_COREID_Msk        (0xFUL << HSEM_R_COREID_Pos)                  /*!< 0x00000F00 */
-#define HSEM_R_COREID            HSEM_R_COREID_Msk                             /*!<Semaphore CoreID. */
-#define HSEM_R_LOCK_Pos          (31U)
-#define HSEM_R_LOCK_Msk          (0x1UL << HSEM_R_LOCK_Pos)                    /*!< 0x80000000 */
-#define HSEM_R_LOCK              HSEM_R_LOCK_Msk                               /*!<Lock indication. */
-
-/********************  Bit definition for HSEM_RLR register  ******************/
-#define HSEM_RLR_PROCID_Pos      (0U)
-#define HSEM_RLR_PROCID_Msk      (0xFFUL << HSEM_RLR_PROCID_Pos)               /*!< 0x000000FF */
-#define HSEM_RLR_PROCID          HSEM_RLR_PROCID_Msk                           /*!<Semaphore ProcessID */
-#define HSEM_RLR_COREID_Pos      (8U)
-#define HSEM_RLR_COREID_Msk      (0xFUL << HSEM_RLR_COREID_Pos)                /*!< 0x00000F00 */
-#define HSEM_RLR_COREID          HSEM_RLR_COREID_Msk                           /*!<Semaphore CoreID. */
-#define HSEM_RLR_LOCK_Pos        (31U)
-#define HSEM_RLR_LOCK_Msk        (0x1UL << HSEM_RLR_LOCK_Pos)                  /*!< 0x80000000 */
-#define HSEM_RLR_LOCK            HSEM_RLR_LOCK_Msk                             /*!<Lock indication. */
-
-/********************  Bit definition for HSEM_C1IER register  ****************/
-#define HSEM_C1IER_ISE0_Pos      (0U)
-#define HSEM_C1IER_ISE0_Msk      (0x1UL << HSEM_C1IER_ISE0_Pos)                /*!< 0x00000001 */
-#define HSEM_C1IER_ISE0          HSEM_C1IER_ISE0_Msk                           /*!<semaphore 0 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE1_Pos      (1U)
-#define HSEM_C1IER_ISE1_Msk      (0x1UL << HSEM_C1IER_ISE1_Pos)                /*!< 0x00000002 */
-#define HSEM_C1IER_ISE1          HSEM_C1IER_ISE1_Msk                           /*!<semaphore 1 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE2_Pos      (2U)
-#define HSEM_C1IER_ISE2_Msk      (0x1UL << HSEM_C1IER_ISE2_Pos)                /*!< 0x00000004 */
-#define HSEM_C1IER_ISE2          HSEM_C1IER_ISE2_Msk                           /*!<semaphore 2 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE3_Pos      (3U)
-#define HSEM_C1IER_ISE3_Msk      (0x1UL << HSEM_C1IER_ISE3_Pos)                /*!< 0x00000008 */
-#define HSEM_C1IER_ISE3          HSEM_C1IER_ISE3_Msk                           /*!<semaphore 3 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE4_Pos      (4U)
-#define HSEM_C1IER_ISE4_Msk      (0x1UL << HSEM_C1IER_ISE4_Pos)                /*!< 0x00000010 */
-#define HSEM_C1IER_ISE4          HSEM_C1IER_ISE4_Msk                           /*!<semaphore 4 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE5_Pos      (5U)
-#define HSEM_C1IER_ISE5_Msk      (0x1UL << HSEM_C1IER_ISE5_Pos)                /*!< 0x00000020 */
-#define HSEM_C1IER_ISE5          HSEM_C1IER_ISE5_Msk                           /*!<semaphore 5 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE6_Pos      (6U)
-#define HSEM_C1IER_ISE6_Msk      (0x1UL << HSEM_C1IER_ISE6_Pos)                /*!< 0x00000040 */
-#define HSEM_C1IER_ISE6          HSEM_C1IER_ISE6_Msk                           /*!<semaphore 6 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE7_Pos      (7U)
-#define HSEM_C1IER_ISE7_Msk      (0x1UL << HSEM_C1IER_ISE7_Pos)                /*!< 0x00000080 */
-#define HSEM_C1IER_ISE7          HSEM_C1IER_ISE7_Msk                           /*!<semaphore 7 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE8_Pos      (8U)
-#define HSEM_C1IER_ISE8_Msk      (0x1UL << HSEM_C1IER_ISE8_Pos)                /*!< 0x00000100 */
-#define HSEM_C1IER_ISE8          HSEM_C1IER_ISE8_Msk                           /*!<semaphore 8 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE9_Pos      (9U)
-#define HSEM_C1IER_ISE9_Msk      (0x1UL << HSEM_C1IER_ISE9_Pos)                /*!< 0x00000200 */
-#define HSEM_C1IER_ISE9          HSEM_C1IER_ISE9_Msk                           /*!<semaphore 9 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE10_Pos     (10U)
-#define HSEM_C1IER_ISE10_Msk     (0x1UL << HSEM_C1IER_ISE10_Pos)               /*!< 0x00000400 */
-#define HSEM_C1IER_ISE10         HSEM_C1IER_ISE10_Msk                          /*!<semaphore 10 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE11_Pos     (11U)
-#define HSEM_C1IER_ISE11_Msk     (0x1UL << HSEM_C1IER_ISE11_Pos)               /*!< 0x00000800 */
-#define HSEM_C1IER_ISE11         HSEM_C1IER_ISE11_Msk                          /*!<semaphore 11 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE12_Pos     (12U)
-#define HSEM_C1IER_ISE12_Msk     (0x1UL << HSEM_C1IER_ISE12_Pos)               /*!< 0x00001000 */
-#define HSEM_C1IER_ISE12         HSEM_C1IER_ISE12_Msk                          /*!<semaphore 12 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE13_Pos     (13U)
-#define HSEM_C1IER_ISE13_Msk     (0x1UL << HSEM_C1IER_ISE13_Pos)               /*!< 0x00002000 */
-#define HSEM_C1IER_ISE13         HSEM_C1IER_ISE13_Msk                          /*!<semaphore 13 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE14_Pos     (14U)
-#define HSEM_C1IER_ISE14_Msk     (0x1UL << HSEM_C1IER_ISE14_Pos)               /*!< 0x00004000 */
-#define HSEM_C1IER_ISE14         HSEM_C1IER_ISE14_Msk                          /*!<semaphore 14 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE15_Pos     (15U)
-#define HSEM_C1IER_ISE15_Msk     (0x1UL << HSEM_C1IER_ISE15_Pos)               /*!< 0x00008000 */
-#define HSEM_C1IER_ISE15         HSEM_C1IER_ISE15_Msk                          /*!<semaphore 15 CPU1 interrupt enable bit. */
-
-/********************  Bit definition for HSEM_C1ICR register  *****************/
-#define HSEM_C1ICR_ISC0_Pos      (0U)
-#define HSEM_C1ICR_ISC0_Msk      (0x1UL << HSEM_C1ICR_ISC0_Pos)                /*!< 0x00000001 */
-#define HSEM_C1ICR_ISC0          HSEM_C1ICR_ISC0_Msk                           /*!<semaphore 0 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC1_Pos      (1U)
-#define HSEM_C1ICR_ISC1_Msk      (0x1UL << HSEM_C1ICR_ISC1_Pos)                /*!< 0x00000002 */
-#define HSEM_C1ICR_ISC1          HSEM_C1ICR_ISC1_Msk                           /*!<semaphore 1 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC2_Pos      (2U)
-#define HSEM_C1ICR_ISC2_Msk      (0x1UL << HSEM_C1ICR_ISC2_Pos)                /*!< 0x00000004 */
-#define HSEM_C1ICR_ISC2          HSEM_C1ICR_ISC2_Msk                           /*!<semaphore 2 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC3_Pos      (3U)
-#define HSEM_C1ICR_ISC3_Msk      (0x1UL << HSEM_C1ICR_ISC3_Pos)                /*!< 0x00000008 */
-#define HSEM_C1ICR_ISC3          HSEM_C1ICR_ISC3_Msk                           /*!<semaphore 3 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC4_Pos      (4U)
-#define HSEM_C1ICR_ISC4_Msk      (0x1UL << HSEM_C1ICR_ISC4_Pos)                /*!< 0x00000010 */
-#define HSEM_C1ICR_ISC4          HSEM_C1ICR_ISC4_Msk                           /*!<semaphore 4 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC5_Pos      (5U)
-#define HSEM_C1ICR_ISC5_Msk      (0x1UL << HSEM_C1ICR_ISC5_Pos)                /*!< 0x00000020 */
-#define HSEM_C1ICR_ISC5          HSEM_C1ICR_ISC5_Msk                           /*!<semaphore 5 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC6_Pos      (6U)
-#define HSEM_C1ICR_ISC6_Msk      (0x1UL << HSEM_C1ICR_ISC6_Pos)                /*!< 0x00000040 */
-#define HSEM_C1ICR_ISC6          HSEM_C1ICR_ISC6_Msk                           /*!<semaphore 6 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC7_Pos      (7U)
-#define HSEM_C1ICR_ISC7_Msk      (0x1UL << HSEM_C1ICR_ISC7_Pos)                /*!< 0x00000080 */
-#define HSEM_C1ICR_ISC7          HSEM_C1ICR_ISC7_Msk                           /*!<semaphore 7 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC8_Pos      (8U)
-#define HSEM_C1ICR_ISC8_Msk      (0x1UL << HSEM_C1ICR_ISC8_Pos)                /*!< 0x00000100 */
-#define HSEM_C1ICR_ISC8          HSEM_C1ICR_ISC8_Msk                           /*!<semaphore 8 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC9_Pos      (9U)
-#define HSEM_C1ICR_ISC9_Msk      (0x1UL << HSEM_C1ICR_ISC9_Pos)                /*!< 0x00000200 */
-#define HSEM_C1ICR_ISC9          HSEM_C1ICR_ISC9_Msk                           /*!<semaphore 9 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC10_Pos     (10U)
-#define HSEM_C1ICR_ISC10_Msk     (0x1UL << HSEM_C1ICR_ISC10_Pos)               /*!< 0x00000400 */
-#define HSEM_C1ICR_ISC10         HSEM_C1ICR_ISC10_Msk                          /*!<semaphore 10 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC11_Pos     (11U)
-#define HSEM_C1ICR_ISC11_Msk     (0x1UL << HSEM_C1ICR_ISC11_Pos)               /*!< 0x00000800 */
-#define HSEM_C1ICR_ISC11         HSEM_C1ICR_ISC11_Msk                          /*!<semaphore 11 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC12_Pos     (12U)
-#define HSEM_C1ICR_ISC12_Msk     (0x1UL << HSEM_C1ICR_ISC12_Pos)               /*!< 0x00001000 */
-#define HSEM_C1ICR_ISC12         HSEM_C1ICR_ISC12_Msk                          /*!<semaphore 12 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC13_Pos     (13U)
-#define HSEM_C1ICR_ISC13_Msk     (0x1UL << HSEM_C1ICR_ISC13_Pos)               /*!< 0x00002000 */
-#define HSEM_C1ICR_ISC13         HSEM_C1ICR_ISC13_Msk                          /*!<semaphore 13 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC14_Pos     (14U)
-#define HSEM_C1ICR_ISC14_Msk     (0x1UL << HSEM_C1ICR_ISC14_Pos)               /*!< 0x00004000 */
-#define HSEM_C1ICR_ISC14         HSEM_C1ICR_ISC14_Msk                          /*!<semaphore 14 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC15_Pos     (15U)
-#define HSEM_C1ICR_ISC15_Msk     (0x1UL << HSEM_C1ICR_ISC15_Pos)               /*!< 0x00008000 */
-#define HSEM_C1ICR_ISC15         HSEM_C1ICR_ISC15_Msk                          /*!<semaphore 15 CPU1 interrupt clear bit. */
-
-/********************  Bit definition for HSEM_C1ISR register  *****************/
-#define HSEM_C1ISR_ISF0_Pos      (0U)
-#define HSEM_C1ISR_ISF0_Msk      (0x1UL << HSEM_C1ISR_ISF0_Pos)                /*!< 0x00000001 */
-#define HSEM_C1ISR_ISF0          HSEM_C1ISR_ISF0_Msk                           /*!<semaphore 0 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF1_Pos      (1U)
-#define HSEM_C1ISR_ISF1_Msk      (0x1UL << HSEM_C1ISR_ISF1_Pos)                /*!< 0x00000002 */
-#define HSEM_C1ISR_ISF1          HSEM_C1ISR_ISF1_Msk                           /*!<semaphore 1 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF2_Pos      (2U)
-#define HSEM_C1ISR_ISF2_Msk      (0x1UL << HSEM_C1ISR_ISF2_Pos)                /*!< 0x00000004 */
-#define HSEM_C1ISR_ISF2          HSEM_C1ISR_ISF2_Msk                           /*!<semaphore 2 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF3_Pos      (3U)
-#define HSEM_C1ISR_ISF3_Msk      (0x1UL << HSEM_C1ISR_ISF3_Pos)                /*!< 0x00000008 */
-#define HSEM_C1ISR_ISF3          HSEM_C1ISR_ISF3_Msk                           /*!<semaphore 3 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF4_Pos      (4U)
-#define HSEM_C1ISR_ISF4_Msk      (0x1UL << HSEM_C1ISR_ISF4_Pos)                /*!< 0x00000010 */
-#define HSEM_C1ISR_ISF4          HSEM_C1ISR_ISF4_Msk                           /*!<semaphore 4 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF5_Pos      (5U)
-#define HSEM_C1ISR_ISF5_Msk      (0x1UL << HSEM_C1ISR_ISF5_Pos)                /*!< 0x00000020 */
-#define HSEM_C1ISR_ISF5          HSEM_C1ISR_ISF5_Msk                           /*!<semaphore 5 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF6_Pos      (6U)
-#define HSEM_C1ISR_ISF6_Msk      (0x1UL << HSEM_C1ISR_ISF6_Pos)                /*!< 0x00000040 */
-#define HSEM_C1ISR_ISF6          HSEM_C1ISR_ISF6_Msk                           /*!<semaphore 6 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF7_Pos      (7U)
-#define HSEM_C1ISR_ISF7_Msk      (0x1UL << HSEM_C1ISR_ISF7_Pos)                /*!< 0x00000080 */
-#define HSEM_C1ISR_ISF7          HSEM_C1ISR_ISF7_Msk                           /*!<semaphore 7 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF8_Pos      (8U)
-#define HSEM_C1ISR_ISF8_Msk      (0x1UL << HSEM_C1ISR_ISF8_Pos)                /*!< 0x00000100 */
-#define HSEM_C1ISR_ISF8          HSEM_C1ISR_ISF8_Msk                           /*!<semaphore 8 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF9_Pos      (9U)
-#define HSEM_C1ISR_ISF9_Msk      (0x1UL << HSEM_C1ISR_ISF9_Pos)                /*!< 0x00000200 */
-#define HSEM_C1ISR_ISF9          HSEM_C1ISR_ISF9_Msk                           /*!<semaphore 9 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF10_Pos     (10U)
-#define HSEM_C1ISR_ISF10_Msk     (0x1UL << HSEM_C1ISR_ISF10_Pos)               /*!< 0x00000400 */
-#define HSEM_C1ISR_ISF10         HSEM_C1ISR_ISF10_Msk                          /*!<semaphore 10 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF11_Pos     (11U)
-#define HSEM_C1ISR_ISF11_Msk     (0x1UL << HSEM_C1ISR_ISF11_Pos)               /*!< 0x00000800 */
-#define HSEM_C1ISR_ISF11         HSEM_C1ISR_ISF11_Msk                          /*!<semaphore 11 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF12_Pos     (12U)
-#define HSEM_C1ISR_ISF12_Msk     (0x1UL << HSEM_C1ISR_ISF12_Pos)               /*!< 0x00001000 */
-#define HSEM_C1ISR_ISF12         HSEM_C1ISR_ISF12_Msk                          /*!<semaphore 12 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF13_Pos     (13U)
-#define HSEM_C1ISR_ISF13_Msk     (0x1UL << HSEM_C1ISR_ISF13_Pos)               /*!< 0x00002000 */
-#define HSEM_C1ISR_ISF13         HSEM_C1ISR_ISF13_Msk                          /*!<semaphore 13 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF14_Pos     (14U)
-#define HSEM_C1ISR_ISF14_Msk     (0x1UL << HSEM_C1ISR_ISF14_Pos)               /*!< 0x00004000 */
-#define HSEM_C1ISR_ISF14         HSEM_C1ISR_ISF14_Msk                          /*!<semaphore 14 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF15_Pos     (15U)
-#define HSEM_C1ISR_ISF15_Msk     (0x1UL << HSEM_C1ISR_ISF15_Pos)               /*!< 0x00008000 */
-#define HSEM_C1ISR_ISF15         HSEM_C1ISR_ISF15_Msk                          /*!<semaphore 15 CPU1 interrupt status bit. */
-
-/********************  Bit definition for HSEM_C1MISR register  *****************/
-#define HSEM_C1MISR_MISF0_Pos     (0U)
-#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)               /*!< 0x00000001 */
-#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                          /*!<semaphore 0 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF1_Pos     (1U)
-#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)               /*!< 0x00000002 */
-#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                          /*!<semaphore 1 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF2_Pos     (2U)
-#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)               /*!< 0x00000004 */
-#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                          /*!<semaphore 2 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF3_Pos     (3U)
-#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)               /*!< 0x00000008 */
-#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                          /*!<semaphore 3 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF4_Pos     (4U)
-#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)               /*!< 0x00000010 */
-#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                          /*!<semaphore 4 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF5_Pos     (5U)
-#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)               /*!< 0x00000020 */
-#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                          /*!<semaphore 5 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF6_Pos     (6U)
-#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)               /*!< 0x00000040 */
-#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                          /*!<semaphore 6 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF7_Pos     (7U)
-#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)               /*!< 0x00000080 */
-#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                          /*!<semaphore 7 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF8_Pos     (8U)
-#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)               /*!< 0x00000100 */
-#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                          /*!<semaphore 8 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF9_Pos     (9U)
-#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)               /*!< 0x00000200 */
-#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                          /*!<semaphore 9 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF10_Pos    (10U)
-#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)              /*!< 0x00000400 */
-#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                         /*!<semaphore 10 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF11_Pos    (11U)
-#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)              /*!< 0x00000800 */
-#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                         /*!<semaphore 11 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF12_Pos    (12U)
-#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)              /*!< 0x00001000 */
-#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                         /*!<semaphore 12 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF13_Pos    (13U)
-#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)              /*!< 0x00002000 */
-#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                         /*!<semaphore 13 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF14_Pos    (14U)
-#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)              /*!< 0x00004000 */
-#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                         /*!<semaphore 14 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF15_Pos    (15U)
-#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)              /*!< 0x00008000 */
-#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                         /*!<semaphore 15 CPU1 interrupt masked status bit. */
-
-/********************  Bit definition for HSEM_C2IER register  *****************/
-#define HSEM_C2IER_ISE0_Pos      (0U)
-#define HSEM_C2IER_ISE0_Msk      (0x1UL << HSEM_C2IER_ISE0_Pos)                /*!< 0x00000001 */
-#define HSEM_C2IER_ISE0          HSEM_C2IER_ISE0_Msk                           /*!<semaphore 0 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE1_Pos      (1U)
-#define HSEM_C2IER_ISE1_Msk      (0x1UL << HSEM_C2IER_ISE1_Pos)                /*!< 0x00000002 */
-#define HSEM_C2IER_ISE1          HSEM_C2IER_ISE1_Msk                           /*!<semaphore 1 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE2_Pos      (2U)
-#define HSEM_C2IER_ISE2_Msk      (0x1UL << HSEM_C2IER_ISE2_Pos)                /*!< 0x00000004 */
-#define HSEM_C2IER_ISE2          HSEM_C2IER_ISE2_Msk                           /*!<semaphore 2 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE3_Pos      (3U)
-#define HSEM_C2IER_ISE3_Msk      (0x1UL << HSEM_C2IER_ISE3_Pos)                /*!< 0x00000008 */
-#define HSEM_C2IER_ISE3          HSEM_C2IER_ISE3_Msk                           /*!<semaphore 3 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE4_Pos      (4U)
-#define HSEM_C2IER_ISE4_Msk      (0x1UL << HSEM_C2IER_ISE4_Pos)                /*!< 0x00000010 */
-#define HSEM_C2IER_ISE4          HSEM_C2IER_ISE4_Msk                           /*!<semaphore 4 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE5_Pos      (5U)
-#define HSEM_C2IER_ISE5_Msk      (0x1UL << HSEM_C2IER_ISE5_Pos)                /*!< 0x00000020 */
-#define HSEM_C2IER_ISE5          HSEM_C2IER_ISE5_Msk                           /*!<semaphore 5 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE6_Pos      (6U)
-#define HSEM_C2IER_ISE6_Msk      (0x1UL << HSEM_C2IER_ISE6_Pos)                /*!< 0x00000040 */
-#define HSEM_C2IER_ISE6          HSEM_C2IER_ISE6_Msk                           /*!<semaphore 6 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE7_Pos      (7U)
-#define HSEM_C2IER_ISE7_Msk      (0x1UL << HSEM_C2IER_ISE7_Pos)                /*!< 0x00000080 */
-#define HSEM_C2IER_ISE7          HSEM_C2IER_ISE7_Msk                           /*!<semaphore 7 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE8_Pos      (8U)
-#define HSEM_C2IER_ISE8_Msk      (0x1UL << HSEM_C2IER_ISE8_Pos)                /*!< 0x00000100 */
-#define HSEM_C2IER_ISE8          HSEM_C2IER_ISE8_Msk                           /*!<semaphore 8 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE9_Pos      (9U)
-#define HSEM_C2IER_ISE9_Msk      (0x1UL << HSEM_C2IER_ISE9_Pos)                /*!< 0x00000200 */
-#define HSEM_C2IER_ISE9          HSEM_C2IER_ISE9_Msk                           /*!<semaphore 9 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE10_Pos     (10U)
-#define HSEM_C2IER_ISE10_Msk     (0x1UL << HSEM_C2IER_ISE10_Pos)               /*!< 0x00000400 */
-#define HSEM_C2IER_ISE10         HSEM_C2IER_ISE10_Msk                          /*!<semaphore 10 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE11_Pos     (11U)
-#define HSEM_C2IER_ISE11_Msk     (0x1UL << HSEM_C2IER_ISE11_Pos)               /*!< 0x00000800 */
-#define HSEM_C2IER_ISE11         HSEM_C2IER_ISE11_Msk                          /*!<semaphore 11 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE12_Pos     (12U)
-#define HSEM_C2IER_ISE12_Msk     (0x1UL << HSEM_C2IER_ISE12_Pos)               /*!< 0x00001000 */
-#define HSEM_C2IER_ISE12         HSEM_C2IER_ISE12_Msk                          /*!<semaphore 12 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE13_Pos     (13U)
-#define HSEM_C2IER_ISE13_Msk     (0x1UL << HSEM_C2IER_ISE13_Pos)               /*!< 0x00002000 */
-#define HSEM_C2IER_ISE13         HSEM_C2IER_ISE13_Msk                          /*!<semaphore 13 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE14_Pos     (14U)
-#define HSEM_C2IER_ISE14_Msk     (0x1UL << HSEM_C2IER_ISE14_Pos)               /*!< 0x00004000 */
-#define HSEM_C2IER_ISE14         HSEM_C2IER_ISE14_Msk                          /*!<semaphore 14 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE15_Pos     (15U)
-#define HSEM_C2IER_ISE15_Msk     (0x1UL << HSEM_C2IER_ISE15_Pos)               /*!< 0x00008000 */
-#define HSEM_C2IER_ISE15         HSEM_C2IER_ISE15_Msk                          /*!<semaphore 15 CPU2 interrupt enable bit. */
-
-/********************  Bit definition for HSEM_C2ICR register  *****************/
-#define HSEM_C2ICR_ISC0_Pos      (0U)
-#define HSEM_C2ICR_ISC0_Msk      (0x1UL << HSEM_C2ICR_ISC0_Pos)                /*!< 0x00000001 */
-#define HSEM_C2ICR_ISC0          HSEM_C2ICR_ISC0_Msk                           /*!<semaphore 0 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC1_Pos      (1U)
-#define HSEM_C2ICR_ISC1_Msk      (0x1UL << HSEM_C2ICR_ISC1_Pos)                /*!< 0x00000002 */
-#define HSEM_C2ICR_ISC1          HSEM_C2ICR_ISC1_Msk                           /*!<semaphore 1 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC2_Pos      (2U)
-#define HSEM_C2ICR_ISC2_Msk      (0x1UL << HSEM_C2ICR_ISC2_Pos)                /*!< 0x00000004 */
-#define HSEM_C2ICR_ISC2          HSEM_C2ICR_ISC2_Msk                           /*!<semaphore 2 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC3_Pos      (3U)
-#define HSEM_C2ICR_ISC3_Msk      (0x1UL << HSEM_C2ICR_ISC3_Pos)                /*!< 0x00000008 */
-#define HSEM_C2ICR_ISC3          HSEM_C2ICR_ISC3_Msk                           /*!<semaphore 3 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC4_Pos      (4U)
-#define HSEM_C2ICR_ISC4_Msk      (0x1UL << HSEM_C2ICR_ISC4_Pos)                /*!< 0x00000010 */
-#define HSEM_C2ICR_ISC4          HSEM_C2ICR_ISC4_Msk                           /*!<semaphore 4 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC5_Pos      (5U)
-#define HSEM_C2ICR_ISC5_Msk      (0x1UL << HSEM_C2ICR_ISC5_Pos)                /*!< 0x00000020 */
-#define HSEM_C2ICR_ISC5          HSEM_C2ICR_ISC5_Msk                           /*!<semaphore 5 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC6_Pos      (6U)
-#define HSEM_C2ICR_ISC6_Msk      (0x1UL << HSEM_C2ICR_ISC6_Pos)                /*!< 0x00000040 */
-#define HSEM_C2ICR_ISC6          HSEM_C2ICR_ISC6_Msk                           /*!<semaphore 6 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC7_Pos      (7U)
-#define HSEM_C2ICR_ISC7_Msk      (0x1UL << HSEM_C2ICR_ISC7_Pos)                /*!< 0x00000080 */
-#define HSEM_C2ICR_ISC7          HSEM_C2ICR_ISC7_Msk                           /*!<semaphore 7 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC8_Pos      (8U)
-#define HSEM_C2ICR_ISC8_Msk      (0x1UL << HSEM_C2ICR_ISC8_Pos)                /*!< 0x00000100 */
-#define HSEM_C2ICR_ISC8          HSEM_C2ICR_ISC8_Msk                           /*!<semaphore 8 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC9_Pos      (9U)
-#define HSEM_C2ICR_ISC9_Msk      (0x1UL << HSEM_C2ICR_ISC9_Pos)                /*!< 0x00000200 */
-#define HSEM_C2ICR_ISC9          HSEM_C2ICR_ISC9_Msk                           /*!<semaphore 9 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC10_Pos     (10U)
-#define HSEM_C2ICR_ISC10_Msk     (0x1UL << HSEM_C2ICR_ISC10_Pos)               /*!< 0x00000400 */
-#define HSEM_C2ICR_ISC10         HSEM_C2ICR_ISC10_Msk                          /*!<semaphore 10 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC11_Pos     (11U)
-#define HSEM_C2ICR_ISC11_Msk     (0x1UL << HSEM_C2ICR_ISC11_Pos)               /*!< 0x00000800 */
-#define HSEM_C2ICR_ISC11         HSEM_C2ICR_ISC11_Msk                          /*!<semaphore 11 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC12_Pos     (12U)
-#define HSEM_C2ICR_ISC12_Msk     (0x1UL << HSEM_C2ICR_ISC12_Pos)               /*!< 0x00001000 */
-#define HSEM_C2ICR_ISC12         HSEM_C2ICR_ISC12_Msk                          /*!<semaphore 12 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC13_Pos     (13U)
-#define HSEM_C2ICR_ISC13_Msk     (0x1UL << HSEM_C2ICR_ISC13_Pos)               /*!< 0x00002000 */
-#define HSEM_C2ICR_ISC13         HSEM_C2ICR_ISC13_Msk                          /*!<semaphore 13 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC14_Pos     (14U)
-#define HSEM_C2ICR_ISC14_Msk     (0x1UL << HSEM_C2ICR_ISC14_Pos)               /*!< 0x00004000 */
-#define HSEM_C2ICR_ISC14         HSEM_C2ICR_ISC14_Msk                          /*!<semaphore 14 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC15_Pos     (15U)
-#define HSEM_C2ICR_ISC15_Msk     (0x1UL << HSEM_C2ICR_ISC15_Pos)               /*!< 0x00008000 */
-#define HSEM_C2ICR_ISC15         HSEM_C2ICR_ISC15_Msk                          /*!<semaphore 15 CPU2 interrupt clear bit. */
-
-/********************  Bit definition for HSEM_C2ISR register  *****************/
-#define HSEM_C2ISR_ISF0_Pos      (0U)
-#define HSEM_C2ISR_ISF0_Msk      (0x1UL << HSEM_C2ISR_ISF0_Pos)                /*!< 0x00000001 */
-#define HSEM_C2ISR_ISF0          HSEM_C2ISR_ISF0_Msk                           /*!<semaphore 0 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF1_Pos      (1U)
-#define HSEM_C2ISR_ISF1_Msk      (0x1UL << HSEM_C2ISR_ISF1_Pos)                /*!< 0x00000002 */
-#define HSEM_C2ISR_ISF1          HSEM_C2ISR_ISF1_Msk                           /*!<semaphore 1 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF2_Pos      (2U)
-#define HSEM_C2ISR_ISF2_Msk      (0x1UL << HSEM_C2ISR_ISF2_Pos)                /*!< 0x00000004 */
-#define HSEM_C2ISR_ISF2          HSEM_C2ISR_ISF2_Msk                           /*!<semaphore 2 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF3_Pos      (3U)
-#define HSEM_C2ISR_ISF3_Msk      (0x1UL << HSEM_C2ISR_ISF3_Pos)                /*!< 0x00000008 */
-#define HSEM_C2ISR_ISF3          HSEM_C2ISR_ISF3_Msk                           /*!<semaphore 3 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF4_Pos      (4U)
-#define HSEM_C2ISR_ISF4_Msk      (0x1UL << HSEM_C2ISR_ISF4_Pos)                /*!< 0x00000010 */
-#define HSEM_C2ISR_ISF4          HSEM_C2ISR_ISF4_Msk                           /*!<semaphore 4 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF5_Pos      (5U)
-#define HSEM_C2ISR_ISF5_Msk      (0x1UL << HSEM_C2ISR_ISF5_Pos)                /*!< 0x00000020 */
-#define HSEM_C2ISR_ISF5          HSEM_C2ISR_ISF5_Msk                           /*!<semaphore 5 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF6_Pos      (6U)
-#define HSEM_C2ISR_ISF6_Msk      (0x1UL << HSEM_C2ISR_ISF6_Pos)                /*!< 0x00000040 */
-#define HSEM_C2ISR_ISF6          HSEM_C2ISR_ISF6_Msk                           /*!<semaphore 6 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF7_Pos      (7U)
-#define HSEM_C2ISR_ISF7_Msk      (0x1UL << HSEM_C2ISR_ISF7_Pos)                /*!< 0x00000080 */
-#define HSEM_C2ISR_ISF7          HSEM_C2ISR_ISF7_Msk                           /*!<semaphore 7 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF8_Pos      (8U)
-#define HSEM_C2ISR_ISF8_Msk      (0x1UL << HSEM_C2ISR_ISF8_Pos)                /*!< 0x00000100 */
-#define HSEM_C2ISR_ISF8          HSEM_C2ISR_ISF8_Msk                           /*!<semaphore 8 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF9_Pos      (9U)
-#define HSEM_C2ISR_ISF9_Msk      (0x1UL << HSEM_C2ISR_ISF9_Pos)                /*!< 0x00000200 */
-#define HSEM_C2ISR_ISF9          HSEM_C2ISR_ISF9_Msk                           /*!<semaphore 9 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF10_Pos     (10U)
-#define HSEM_C2ISR_ISF10_Msk     (0x1UL << HSEM_C2ISR_ISF10_Pos)               /*!< 0x00000400 */
-#define HSEM_C2ISR_ISF10         HSEM_C2ISR_ISF10_Msk                          /*!<semaphore 10 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF11_Pos     (11U)
-#define HSEM_C2ISR_ISF11_Msk     (0x1UL << HSEM_C2ISR_ISF11_Pos)               /*!< 0x00000800 */
-#define HSEM_C2ISR_ISF11         HSEM_C2ISR_ISF11_Msk                          /*!<semaphore 11 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF12_Pos     (12U)
-#define HSEM_C2ISR_ISF12_Msk     (0x1UL << HSEM_C2ISR_ISF12_Pos)               /*!< 0x00001000 */
-#define HSEM_C2ISR_ISF12         HSEM_C2ISR_ISF12_Msk                          /*!<semaphore 12 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF13_Pos     (13U)
-#define HSEM_C2ISR_ISF13_Msk     (0x1UL << HSEM_C2ISR_ISF13_Pos)               /*!< 0x00002000 */
-#define HSEM_C2ISR_ISF13         HSEM_C2ISR_ISF13_Msk                          /*!<semaphore 13 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF14_Pos     (14U)
-#define HSEM_C2ISR_ISF14_Msk     (0x1UL << HSEM_C2ISR_ISF14_Pos)               /*!< 0x00004000 */
-#define HSEM_C2ISR_ISF14         HSEM_C2ISR_ISF14_Msk                          /*!<semaphore 14 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF15_Pos     (15U)
-#define HSEM_C2ISR_ISF15_Msk     (0x1UL << HSEM_C2ISR_ISF15_Pos)               /*!< 0x00008000 */
-#define HSEM_C2ISR_ISF15         HSEM_C2ISR_ISF15_Msk                          /*!<semaphore 15 CPU2 interrupt status bit. */
-
-/********************  Bit definition for HSEM_C2MISR register  *****************/
-#define HSEM_C2MISR_MISF0_Pos     (0U)
-#define HSEM_C2MISR_MISF0_Msk     (0x1UL << HSEM_C2MISR_MISF0_Pos)               /*!< 0x00000001 */
-#define HSEM_C2MISR_MISF0         HSEM_C2MISR_MISF0_Msk                          /*!<semaphore 0 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF1_Pos     (1U)
-#define HSEM_C2MISR_MISF1_Msk     (0x1UL << HSEM_C2MISR_MISF1_Pos)               /*!< 0x00000002 */
-#define HSEM_C2MISR_MISF1         HSEM_C2MISR_MISF1_Msk                          /*!<semaphore 1 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF2_Pos     (2U)
-#define HSEM_C2MISR_MISF2_Msk     (0x1UL << HSEM_C2MISR_MISF2_Pos)               /*!< 0x00000004 */
-#define HSEM_C2MISR_MISF2         HSEM_C2MISR_MISF2_Msk                          /*!<semaphore 2 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF3_Pos     (3U)
-#define HSEM_C2MISR_MISF3_Msk     (0x1UL << HSEM_C2MISR_MISF3_Pos)               /*!< 0x00000008 */
-#define HSEM_C2MISR_MISF3         HSEM_C2MISR_MISF3_Msk                          /*!<semaphore 3 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF4_Pos     (4U)
-#define HSEM_C2MISR_MISF4_Msk     (0x1UL << HSEM_C2MISR_MISF4_Pos)               /*!< 0x00000010 */
-#define HSEM_C2MISR_MISF4         HSEM_C2MISR_MISF4_Msk                          /*!<semaphore 4 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF5_Pos     (5U)
-#define HSEM_C2MISR_MISF5_Msk     (0x1UL << HSEM_C2MISR_MISF5_Pos)               /*!< 0x00000020 */
-#define HSEM_C2MISR_MISF5         HSEM_C2MISR_MISF5_Msk                          /*!<semaphore 5 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF6_Pos     (6U)
-#define HSEM_C2MISR_MISF6_Msk     (0x1UL << HSEM_C2MISR_MISF6_Pos)               /*!< 0x00000040 */
-#define HSEM_C2MISR_MISF6         HSEM_C2MISR_MISF6_Msk                          /*!<semaphore 6 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF7_Pos     (7U)
-#define HSEM_C2MISR_MISF7_Msk     (0x1UL << HSEM_C2MISR_MISF7_Pos)               /*!< 0x00000080 */
-#define HSEM_C2MISR_MISF7         HSEM_C2MISR_MISF7_Msk                          /*!<semaphore 7 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF8_Pos     (8U)
-#define HSEM_C2MISR_MISF8_Msk     (0x1UL << HSEM_C2MISR_MISF8_Pos)               /*!< 0x00000100 */
-#define HSEM_C2MISR_MISF8         HSEM_C2MISR_MISF8_Msk                          /*!<semaphore 8 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF9_Pos     (9U)
-#define HSEM_C2MISR_MISF9_Msk     (0x1UL << HSEM_C2MISR_MISF9_Pos)               /*!< 0x00000200 */
-#define HSEM_C2MISR_MISF9         HSEM_C2MISR_MISF9_Msk                          /*!<semaphore 9 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF10_Pos    (10U)
-#define HSEM_C2MISR_MISF10_Msk    (0x1UL << HSEM_C2MISR_MISF10_Pos)              /*!< 0x00000400 */
-#define HSEM_C2MISR_MISF10        HSEM_C2MISR_MISF10_Msk                         /*!<semaphore 10 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF11_Pos    (11U)
-#define HSEM_C2MISR_MISF11_Msk    (0x1UL << HSEM_C2MISR_MISF11_Pos)              /*!< 0x00000800 */
-#define HSEM_C2MISR_MISF11        HSEM_C2MISR_MISF11_Msk                         /*!<semaphore 11 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF12_Pos    (12U)
-#define HSEM_C2MISR_MISF12_Msk    (0x1UL << HSEM_C2MISR_MISF12_Pos)              /*!< 0x00001000 */
-#define HSEM_C2MISR_MISF12        HSEM_C2MISR_MISF12_Msk                         /*!<semaphore 12 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF13_Pos    (13U)
-#define HSEM_C2MISR_MISF13_Msk    (0x1UL << HSEM_C2MISR_MISF13_Pos)              /*!< 0x00002000 */
-#define HSEM_C2MISR_MISF13        HSEM_C2MISR_MISF13_Msk                         /*!<semaphore 13 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF14_Pos    (14U)
-#define HSEM_C2MISR_MISF14_Msk    (0x1UL << HSEM_C2MISR_MISF14_Pos)              /*!< 0x00004000 */
-#define HSEM_C2MISR_MISF14        HSEM_C2MISR_MISF14_Msk                         /*!<semaphore 14 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF15_Pos    (15U)
-#define HSEM_C2MISR_MISF15_Msk    (0x1UL << HSEM_C2MISR_MISF15_Pos)              /*!< 0x00008000 */
-#define HSEM_C2MISR_MISF15        HSEM_C2MISR_MISF15_Msk                         /*!<semaphore 15 CPU2 interrupt masked status bit. */
-
-/********************  Bit definition for HSEM_CR register  *****************/
-#define HSEM_CR_COREID_Pos       (8U)
-#define HSEM_CR_COREID_Msk       (0xFUL << HSEM_CR_COREID_Pos)                 /*!< 0x00000F00 */
-#define HSEM_CR_COREID           HSEM_CR_COREID_Msk                            /*!<CoreID of semaphores to be cleared. */
-#define HSEM_CR_COREID_CPU1      (0x4U << HSEM_CR_COREID_Pos)
-#define HSEM_CR_COREID_CPU2      (0x8U << HSEM_CR_COREID_Pos)
-#define HSEM_CR_COREID_CURRENT   HSEM_CR_COREID_CPU1
-#define HSEM_CR_KEY_Pos          (16U)
-#define HSEM_CR_KEY_Msk          (0xFFFFUL << HSEM_CR_KEY_Pos)                 /*!< 0xFFFF0000 */
-#define HSEM_CR_KEY              HSEM_CR_KEY_Msk                               /*!<semaphores clear key. */
-
-/********************  Bit definition for HSEM_KEYR register  *****************/
-#define HSEM_KEYR_KEY_Pos        (16U)
-#define HSEM_KEYR_KEY_Msk        (0xFFFFUL << HSEM_KEYR_KEY_Pos)               /*!< 0xFFFF0000 */
-#define HSEM_KEYR_KEY            HSEM_KEYR_KEY_Msk                             /*!<semaphores clear key. */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Public Key Accelerator (PKA)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bits definition for PKA_CR register  **************/
-#define PKA_CR_EN_Pos              (0U)
-#define PKA_CR_EN_Msk              (0x1UL << PKA_CR_EN_Pos)                /*!< 0x00000001 */
-#define PKA_CR_EN                  PKA_CR_EN_Msk                           /*!< PKA enable */
-#define PKA_CR_START_Pos           (1U)
-#define PKA_CR_START_Msk           (0x1UL << PKA_CR_START_Pos)             /*!< 0x00000002 */
-#define PKA_CR_START               PKA_CR_START_Msk                        /*!< Start operation */
-#define PKA_CR_MODE_Pos            (8U)
-#define PKA_CR_MODE_Msk            (0x3FUL << PKA_CR_MODE_Pos)             /*!< 0x00003F00 */
-#define PKA_CR_MODE                PKA_CR_MODE_Msk                         /*!< MODE[5:0] PKA operation code */
-#define PKA_CR_MODE_0              (0x01UL << PKA_CR_MODE_Pos)             /*!< 0x00000100 */
-#define PKA_CR_MODE_1              (0x02UL << PKA_CR_MODE_Pos)             /*!< 0x00000200 */
-#define PKA_CR_MODE_2              (0x04UL << PKA_CR_MODE_Pos)             /*!< 0x00000400 */
-#define PKA_CR_MODE_3              (0x08UL << PKA_CR_MODE_Pos)             /*!< 0x00000800 */
-#define PKA_CR_MODE_4              (0x10UL << PKA_CR_MODE_Pos)             /*!< 0x00001000 */
-#define PKA_CR_MODE_5              (0x20UL << PKA_CR_MODE_Pos)             /*!< 0x00002000 */
-#define PKA_CR_PROCENDIE_Pos       (17U)
-#define PKA_CR_PROCENDIE_Msk       (0x1UL << PKA_CR_PROCENDIE_Pos)         /*!< 0x00020000 */
-#define PKA_CR_PROCENDIE           PKA_CR_PROCENDIE_Msk                    /*!< End of operation interrupt enable */
-#define PKA_CR_RAMERRIE_Pos        (19U)
-#define PKA_CR_RAMERRIE_Msk        (0x1UL << PKA_CR_RAMERRIE_Pos)          /*!< 0x00080000 */
-#define PKA_CR_RAMERRIE            PKA_CR_RAMERRIE_Msk                     /*!< RAM error interrupt enable */
-#define PKA_CR_ADDRERRIE_Pos       (20U)
-#define PKA_CR_ADDRERRIE_Msk       (0x1UL << PKA_CR_ADDRERRIE_Pos)         /*!< 0x00100000 */
-#define PKA_CR_ADDRERRIE           PKA_CR_ADDRERRIE_Msk                    /*!< RAM error interrupt enable */
-
-/*******************  Bits definition for PKA_SR register  **************/
-#define PKA_SR_BUSY_Pos            (16U)
-#define PKA_SR_BUSY_Msk            (0x1UL << PKA_SR_BUSY_Pos)              /*!< 0x00010000 */
-#define PKA_SR_BUSY                PKA_SR_BUSY_Msk                         /*!< PKA operation is in progress */
-#define PKA_SR_PROCENDF_Pos        (17U)
-#define PKA_SR_PROCENDF_Msk        (0x1UL << PKA_SR_PROCENDF_Pos)          /*!< 0x00020000 */
-#define PKA_SR_PROCENDF            PKA_SR_PROCENDF_Msk                     /*!< PKA end of operation flag */
-#define PKA_SR_RAMERRF_Pos         (19U)
-#define PKA_SR_RAMERRF_Msk         (0x1UL << PKA_SR_RAMERRF_Pos)           /*!< 0x00080000 */
-#define PKA_SR_RAMERRF             PKA_SR_RAMERRF_Msk                      /*!< PKA RAM error flag */
-#define PKA_SR_ADDRERRF_Pos        (20U)
-#define PKA_SR_ADDRERRF_Msk        (0x1UL << PKA_SR_ADDRERRF_Pos)          /*!< 0x00100000 */
-#define PKA_SR_ADDRERRF            PKA_SR_ADDRERRF_Msk                     /*!< Address error flag */
-
-/*******************  Bits definition for PKA_CLRFR register  **************/
-#define PKA_CLRFR_PROCENDFC_Pos    (17U)
-#define PKA_CLRFR_PROCENDFC_Msk    (0x1UL << PKA_CLRFR_PROCENDFC_Pos)      /*!< 0x00020000 */
-#define PKA_CLRFR_PROCENDFC        PKA_CLRFR_PROCENDFC_Msk                 /*!< Clear PKA end of operation flag */
-#define PKA_CLRFR_RAMERRFC_Pos     (19U)
-#define PKA_CLRFR_RAMERRFC_Msk     (0x1UL << PKA_CLRFR_RAMERRFC_Pos)       /*!< 0x00080000 */
-#define PKA_CLRFR_RAMERRFC         PKA_CLRFR_RAMERRFC_Msk                  /*!< Clear PKA RAM error flag */
-#define PKA_CLRFR_ADDRERRFC_Pos    (20U)
-#define PKA_CLRFR_ADDRERRFC_Msk    (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)      /*!< 0x00100000 */
-#define PKA_CLRFR_ADDRERRFC        PKA_CLRFR_ADDRERRFC_Msk                 /*!< Clear address error flag */
-
-/*******************  Bits definition for PKA RAM  *************************/
-#define PKA_RAM_OFFSET                            0x400U                           /*!< PKA RAM address offset */
-
-/* Compute Montgomery parameter input data */
-#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS       ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_MONTGOMERY_PARAM_IN_MODULUS           ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Compute Montgomery parameter output data */
-#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER        ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Output Montgomery parameter */
-
-/* Compute modular exponentiation input data */
-#define PKA_MODULAR_EXP_IN_EXP_NB_BITS            ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent number of bits */
-#define PKA_MODULAR_EXP_IN_OP_NB_BITS             ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM       ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Input storage area for Montgomery parameter */
-#define PKA_MODULAR_EXP_IN_EXPONENT_BASE          ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input base of the exponentiation */
-#define PKA_MODULAR_EXP_IN_EXPONENT               ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent to process */
-#define PKA_MODULAR_EXP_IN_MODULUS                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Compute modular exponentiation output data */
-#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM      ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Output storage area for Montgomery parameter */
-#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1          ((0x724U - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 1 */
-#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2          ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 2 */
-#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE         ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Output base of the exponentiation */
-#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3          ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 3 */
-
-/* Compute ECC scalar multiplication input data */
-#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS         ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent number of bits */
-#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS          ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN        ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_ECC_SCALAR_MUL_IN_A_COEFF             ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_ECC_SCALAR_MUL_IN_MOD_GF              ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM    ((0x4B4U - PKA_RAM_OFFSET)>>2)   /*!< Input storage area for Montgomery parameter */
-#define PKA_ECC_SCALAR_MUL_IN_K                   ((0x508U - PKA_RAM_OFFSET)>>2)   /*!< Input 'k' of KP */
-#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X     ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y     ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-
-/* Compute ECC scalar multiplication output data */
-#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X           ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Output result X coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y           ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Output result Y coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1     ((0xDE8U - PKA_RAM_OFFSET)>>2)   /*!< Output last double X1 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1     ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Output last double Y1 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1     ((0xE90U - PKA_RAM_OFFSET)>>2)   /*!< Output last double Z1 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2     ((0xEE4U - PKA_RAM_OFFSET)>>2)   /*!< Output check point X2 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2     ((0xF38U - PKA_RAM_OFFSET)>>2)   /*!< Output check point Y2 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2     ((0xF8CU - PKA_RAM_OFFSET)>>2)   /*!< Output check point Z2 coordinate */
-
-/* Point check input data */
-#define PKA_POINT_CHECK_IN_MOD_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_POINT_CHECK_IN_A_COEFF_SIGN           ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_POINT_CHECK_IN_A_COEFF                ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_POINT_CHECK_IN_B_COEFF                ((0x7FCU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'b' coefficient */
-#define PKA_POINT_CHECK_IN_MOD_GF                 ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_POINT_CHECK_IN_INITIAL_POINT_X        ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y        ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-
-/* Point check output data */
-#define PKA_POINT_CHECK_OUT_ERROR                 ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Output error */
-
-/* ECDSA signature input data */
-#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS           ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input order number of bits */
-#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS             ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN            ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_ECDSA_SIGN_IN_A_COEFF                 ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_ECDSA_SIGN_IN_MOD_GF                  ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_ECDSA_SIGN_IN_K                       ((0x508U - PKA_RAM_OFFSET)>>2)   /*!< Input k value of the ECDSA */
-#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X         ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y         ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-#define PKA_ECDSA_SIGN_IN_HASH_E                  ((0xDE8U - PKA_RAM_OFFSET)>>2)   /*!< Input e, hash of the message */
-#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D           ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Input d, private key */
-#define PKA_ECDSA_SIGN_IN_ORDER_N                 ((0xE94U - PKA_RAM_OFFSET)>>2)   /*!< Input n, order of the curve */
-
-/* ECDSA signature output data */
-#define PKA_ECDSA_SIGN_OUT_ERROR                  ((0xEE8U - PKA_RAM_OFFSET)>>2)   /*!< Output error */
-#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R            ((0x700U - PKA_RAM_OFFSET)>>2)   /*!< Output signature r */
-#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S            ((0x754U - PKA_RAM_OFFSET)>>2)   /*!< Output signature s */
-#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X          ((0x103CU - PKA_RAM_OFFSET)>>2)   /*!< Output final point kP X coordinate */
-#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y          ((0x1090U - PKA_RAM_OFFSET)>>2)   /*!< Output final point kP Y coordinate */
-
-/* ECDSA verification input data */
-#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS          ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input order number of bits */
-#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS            ((0x4B4U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN           ((0x45CU - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_ECDSA_VERIF_IN_A_COEFF                ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_ECDSA_VERIF_IN_MOD_GF                 ((0x4B8U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X        ((0x5E8U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y        ((0x63CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X     ((0xF40U - PKA_RAM_OFFSET)>>2)   /*!< Input public key point X coordinate */
-#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y     ((0xF94U - PKA_RAM_OFFSET)>>2)   /*!< Input public key point Y coordinate */
-#define PKA_ECDSA_VERIF_IN_SIGNATURE_R            ((0x1098U - PKA_RAM_OFFSET)>>2)   /*!< Input r, part of the signature */
-#define PKA_ECDSA_VERIF_IN_SIGNATURE_S            ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input s, part of the signature */
-#define PKA_ECDSA_VERIF_IN_HASH_E                 ((0xFE8U - PKA_RAM_OFFSET)>>2)   /*!< Input e, hash of the message */
-#define PKA_ECDSA_VERIF_IN_ORDER_N                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input n, order of the curve */
-
-/* ECDSA verification output data */
-#define PKA_ECDSA_VERIF_OUT_RESULT                ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* RSA CRT exponentiation input data */
-#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operands number of bits */
-#define PKA_RSA_CRT_EXP_IN_DP_CRT                 ((0x65CU - PKA_RAM_OFFSET)>>2)   /*!< Input Dp CRT parameter */
-#define PKA_RSA_CRT_EXP_IN_DQ_CRT                 ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Input Dq CRT parameter */
-#define PKA_RSA_CRT_EXP_IN_QINV_CRT               ((0x7ECU - PKA_RAM_OFFSET)>>2)   /*!< Input qInv CRT parameter */
-#define PKA_RSA_CRT_EXP_IN_PRIME_P                ((0x97CU - PKA_RAM_OFFSET)>>2)   /*!< Input Prime p */
-#define PKA_RSA_CRT_EXP_IN_PRIME_Q                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input Prime q */
-#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE          ((0xEECU - PKA_RAM_OFFSET)>>2)   /*!< Input base of the exponentiation */
-
-/* RSA CRT exponentiation output data */
-#define PKA_RSA_CRT_EXP_OUT_RESULT                ((0x724U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular reduction input data */
-#define PKA_MODULAR_REDUC_IN_OP_LENGTH            ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input operand length */
-#define PKA_MODULAR_REDUC_IN_OPERAND              ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand */
-#define PKA_MODULAR_REDUC_IN_MOD_LENGTH           ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus length */
-#define PKA_MODULAR_REDUC_IN_MODULUS              ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Modular reduction output data */
-#define PKA_MODULAR_REDUC_OUT_RESULT              ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Arithmetic addition input data */
-#define PKA_ARITHMETIC_ADD_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_ADD_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_ADD_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Arithmetic addition output data */
-#define PKA_ARITHMETIC_ADD_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Arithmetic substraction input data */
-#define PKA_ARITHMETIC_SUB_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_SUB_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_SUB_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Arithmetic substraction output data */
-#define PKA_ARITHMETIC_SUB_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Arithmetic multiplication input data */
-#define PKA_ARITHMETIC_MUL_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_MUL_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_MUL_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Arithmetic multiplication output data */
-#define PKA_ARITHMETIC_MUL_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Comparison input data */
-#define PKA_COMPARISON_NB_BITS                    ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_COMPARISON_IN_OP1                     ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_COMPARISON_IN_OP2                     ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Comparison output data */
-#define PKA_COMPARISON_OUT_RESULT                 ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular addition input data */
-#define PKA_MODULAR_ADD_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_ADD_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MODULAR_ADD_IN_OP2                    ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_MODULAR_ADD_IN_OP3_MOD                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 (modulus) */
-
-/* Modular addition output data */
-#define PKA_MODULAR_ADD_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular inversion input data */
-#define PKA_MODULAR_INV_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_INV_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MODULAR_INV_IN_OP2_MOD                ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 (modulus) */
-
-/* Modular inversion output data */
-#define PKA_MODULAR_INV_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular substraction input data */
-#define PKA_MODULAR_SUB_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_SUB_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MODULAR_SUB_IN_OP2                    ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_MODULAR_SUB_IN_OP3_MOD                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 */
-
-/* Modular substraction output data */
-#define PKA_MODULAR_SUB_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Montgomery multiplication input data */
-#define PKA_MONTGOMERY_MUL_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MONTGOMERY_MUL_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MONTGOMERY_MUL_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_MONTGOMERY_MUL_IN_OP3_MOD             ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Montgomery multiplication output data */
-#define PKA_MONTGOMERY_MUL_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Generic Arithmetic input data */
-#define PKA_ARITHMETIC_ALL_OPS_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_ALL_OPS_IN_OP1             ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_ALL_OPS_IN_OP2             ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_ARITHMETIC_ALL_OPS_IN_OP3             ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Generic Arithmetic output data */
-#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT         ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Power Control                                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR1 register  ********************/
-#define PWR_CR1_LPMS_Pos               (0U)
-#define PWR_CR1_LPMS_Msk               (0x7UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000007 */
-#define PWR_CR1_LPMS                   PWR_CR1_LPMS_Msk                        /*!< Low Power Mode Selection for CPU1 */
-#define PWR_CR1_LPMS_0                 (0x1UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000001 */
-#define PWR_CR1_LPMS_1                 (0x2UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000002 */
-#define PWR_CR1_LPMS_2                 (0x4UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000004 */
-
-#define PWR_CR1_SUBGHZSPINSSSEL_Pos    (3U)
-#define PWR_CR1_SUBGHZSPINSSSEL_Msk    (0x1UL << PWR_CR1_SUBGHZSPINSSSEL_Pos)  /*!< 0x00000008 */
-#define PWR_CR1_SUBGHZSPINSSSEL        PWR_CR1_SUBGHZSPINSSSEL_Msk             /*!< Sub-GHz radio SPI NSS source select */
-
-#define PWR_CR1_FPDR_Pos               (4U)
-#define PWR_CR1_FPDR_Msk               (0x1UL << PWR_CR1_FPDR_Pos)             /*!< 0x00000010 */
-#define PWR_CR1_FPDR                   PWR_CR1_FPDR_Msk                        /*!< Flash power down mode during LPrun for CPU1 */
-
-#define PWR_CR1_FPDS_Pos               (5U)
-#define PWR_CR1_FPDS_Msk               (0x1UL << PWR_CR1_FPDS_Pos)             /*!< 0x00000020 */
-#define PWR_CR1_FPDS                   PWR_CR1_FPDS_Msk                        /*!< Flash power down mode during LPsleep for CPU1 */
-
-#define PWR_CR1_DBP_Pos                (8U)
-#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
-#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Backup Domain write protection */
-
-#define PWR_CR1_VOS_Pos                (9U)
-#define PWR_CR1_VOS_Msk                (0x3UL << PWR_CR1_VOS_Pos)              /*!< 0x00000600 */
-#define PWR_CR1_VOS                    PWR_CR1_VOS_Msk                         /*!< Voltage scaling range selection */
-#define PWR_CR1_VOS_0                  (0x1UL << PWR_CR1_VOS_Pos)              /*!< 0x00000200 */
-#define PWR_CR1_VOS_1                  (0x2UL << PWR_CR1_VOS_Pos)              /*!< 0x00000400 */
-
-#define PWR_CR1_LPR_Pos                (14U)
-#define PWR_CR1_LPR_Msk                (0x1UL << PWR_CR1_LPR_Pos)              /*!< 0x00004000 */
-#define PWR_CR1_LPR                    PWR_CR1_LPR_Msk                         /*!< Regulator Low-Power Run mode */
-
-/********************  Bit definition for PWR_CR2 register  ********************/
-#define PWR_CR2_PVDE_Pos               (0U)
-#define PWR_CR2_PVDE_Msk               (0x1UL << PWR_CR2_PVDE_Pos)             /*!< 0x00000001 */
-#define PWR_CR2_PVDE                   PWR_CR2_PVDE_Msk                        /*!< Power voltage detector enable */
-
-#define PWR_CR2_PLS_Pos                (1U)
-#define PWR_CR2_PLS_Msk                (0x7UL << PWR_CR2_PLS_Pos)              /*!< 0x0000000E */
-#define PWR_CR2_PLS                    PWR_CR2_PLS_Msk                         /*!< Power voltage detector level selection */
-#define PWR_CR2_PLS_0                  (0x1UL << PWR_CR2_PLS_Pos)              /*!< 0x00000002 */
-#define PWR_CR2_PLS_1                  (0x2UL << PWR_CR2_PLS_Pos)              /*!< 0x00000004 */
-#define PWR_CR2_PLS_2                  (0x4UL << PWR_CR2_PLS_Pos)              /*!< 0x00000008 */
-
-#define PWR_CR2_PVME3_Pos              (6U)
-#define PWR_CR2_PVME3_Msk              (0x1UL << PWR_CR2_PVME3_Pos)            /*!< 0x00000040 */
-#define PWR_CR2_PVME3                  PWR_CR2_PVME3_Msk                       /*!< Peripherical Voltage Monitor Vdda Enable */
-
-/********************  Bit definition for PWR_CR3 register  ********************/
-#define PWR_CR3_EWUP_Pos               (0U)
-#define PWR_CR3_EWUP_Msk               (0x07UL << PWR_CR3_EWUP_Pos)            /*!< 0x00000007 */
-#define PWR_CR3_EWUP                   PWR_CR3_EWUP_Msk                        /*!< Enable all external Wake-Up lines  */
-#define PWR_CR3_EWUP1_Pos              (0U)
-#define PWR_CR3_EWUP1_Msk              (0x1UL << PWR_CR3_EWUP1_Pos)            /*!< 0x00000001 */
-#define PWR_CR3_EWUP1                  PWR_CR3_EWUP1_Msk                       /*!< Enable external WKUP Pin 1 [line 0] */
-#define PWR_CR3_EWUP2_Pos              (1U)
-#define PWR_CR3_EWUP2_Msk              (0x1UL << PWR_CR3_EWUP2_Pos)            /*!< 0x00000002 */
-#define PWR_CR3_EWUP2                  PWR_CR3_EWUP2_Msk                       /*!< Enable external WKUP Pin 2 [line 1] */
-#define PWR_CR3_EWUP3_Pos              (2U)
-#define PWR_CR3_EWUP3_Msk              (0x1UL << PWR_CR3_EWUP3_Pos)            /*!< 0x00000004 */
-#define PWR_CR3_EWUP3                  PWR_CR3_EWUP3_Msk                       /*!< Enable external WKUP Pin 3 [line 2] */
-
-#define PWR_CR3_ULPEN_Pos              (7U)
-#define PWR_CR3_ULPEN_Msk              (0x1UL << PWR_CR3_ULPEN_Pos)            /*!< 0x00000080 */
-#define PWR_CR3_ULPEN                  PWR_CR3_ULPEN_Msk                       /*!< Enable periodical sampling of supply voltage in Stop and Standby modes for detecting condition of PDR and BOR reset */
-
-#define PWR_CR3_EWPVD_Pos              (8U)
-#define PWR_CR3_EWPVD_Msk              (0x1UL << PWR_CR3_EWPVD_Pos)            /*!< 0x00000100 */
-#define PWR_CR3_EWPVD                  PWR_CR3_EWPVD_Msk                       /*!< Enable wakeup PVD for CPU1 */
-
-#define PWR_CR3_RRS_Pos                (9U)
-#define PWR_CR3_RRS_Msk                (0x1UL << PWR_CR3_RRS_Pos)              /*!< 0x00000200 */
-#define PWR_CR3_RRS                    PWR_CR3_RRS_Msk                         /*!< SRAM2 retention in STANDBY mode */
-
-#define PWR_CR3_APC_Pos                (10U)
-#define PWR_CR3_APC_Msk                (0x1UL << PWR_CR3_APC_Pos)              /*!< 0x00000400 */
-#define PWR_CR3_APC                    PWR_CR3_APC_Msk                         /*!< Apply pull-up and pull-down configuration for CPU1 */
-
-#define PWR_CR3_EWRFBUSY_Pos           (11U)
-#define PWR_CR3_EWRFBUSY_Msk           (0x1UL << PWR_CR3_EWRFBUSY_Pos)         /*!< 0x00008000 */
-#define PWR_CR3_EWRFBUSY                PWR_CR3_EWRFBUSY_Msk                   /*!< Enable Radio busy IRQ and wake-up for CPU1 */
-#define PWR_CR3_EWRFIRQ_Pos            (13U)
-#define PWR_CR3_EWRFIRQ_Msk            (0x1UL << PWR_CR3_EWRFIRQ_Pos)          /*!< 0x00020000 */
-#define PWR_CR3_EWRFIRQ                PWR_CR3_EWRFIRQ_Msk                     /*!< Enable Radio IRQ[2:0] and wake-up for CPU1 */
-
-#define PWR_CR3_EIWUL_Pos              (15U)
-#define PWR_CR3_EIWUL_Msk              (0x1UL << PWR_CR3_EIWUL_Pos)            /*!< 0x00080000 */
-#define PWR_CR3_EIWUL                  PWR_CR3_EIWUL_Msk                       /*!< Internal Wake-Up line interrupt for CPU1 */
-
-/********************  Bit definition for PWR_CR4 register  ********************/
-#define PWR_CR4_WP1_Pos                (0U)
-#define PWR_CR4_WP1_Msk                (0x1UL << PWR_CR4_WP1_Pos)              /*!< 0x00000001 */
-#define PWR_CR4_WP1                    PWR_CR4_WP1_Msk                         /*!< Wake-Up Pin 1 [line 0] polarity */
-#define PWR_CR4_WP2_Pos                (1U)
-#define PWR_CR4_WP2_Msk                (0x1UL << PWR_CR4_WP2_Pos)              /*!< 0x00000002 */
-#define PWR_CR4_WP2                    PWR_CR4_WP2_Msk                         /*!< Wake-Up Pin 2 [line 1] polarity */
-#define PWR_CR4_WP3_Pos                (2U)
-#define PWR_CR4_WP3_Msk                (0x1UL << PWR_CR4_WP3_Pos)              /*!< 0x00000004 */
-#define PWR_CR4_WP3                    PWR_CR4_WP3_Msk                         /*!< Wake-Up Pin 3 [line 2] polarity */
-
-#define PWR_CR4_VBE_Pos                (8U)
-#define PWR_CR4_VBE_Msk                (0x1UL << PWR_CR4_VBE_Pos)              /*!< 0x00000100 */
-#define PWR_CR4_VBE                    PWR_CR4_VBE_Msk                         /*!< VBAT battery charging enable  */
-#define PWR_CR4_VBRS_Pos               (9U)
-#define PWR_CR4_VBRS_Msk               (0x1UL << PWR_CR4_VBRS_Pos)             /*!< 0x00000200 */
-#define PWR_CR4_VBRS                   PWR_CR4_VBRS_Msk                        /*!< VBAT battery charging resistor selection */
-
-#define PWR_CR4_WRFBUSYP_Pos           (11U)
-#define PWR_CR4_WRFBUSYP_Msk           (0x1UL << PWR_CR4_WRFBUSYP_Pos)         /*!< 0x00008000 */
-#define PWR_CR4_WRFBUSYP               PWR_CR4_WRFBUSYP_Msk                    /*!< Wake-up radio busy polarity */
-
-/********************  Bit definition for PWR_SR1 register  ********************/
-#define PWR_SR1_WUF_Pos                (0U)
-#define PWR_SR1_WUF_Msk                (0x1FUL << PWR_SR1_WUF_Pos)             /*!< 0x00000007 */
-#define PWR_SR1_WUF                    PWR_SR1_WUF_Msk                         /*!< Wakeup Flags of all pins */
-#define PWR_SR1_WUF1_Pos               (0U)
-#define PWR_SR1_WUF1_Msk               (0x1UL << PWR_SR1_WUF1_Pos)             /*!< 0x00000001 */
-#define PWR_SR1_WUF1                   PWR_SR1_WUF1_Msk                        /*!< Wakeup Pin 1 [Flag 0] */
-#define PWR_SR1_WUF2_Pos               (1U)
-#define PWR_SR1_WUF2_Msk               (0x1UL << PWR_SR1_WUF2_Pos)             /*!< 0x00000002 */
-#define PWR_SR1_WUF2                   PWR_SR1_WUF2_Msk                        /*!< Wakeup Pin 2 [Flag 1] */
-#define PWR_SR1_WUF3_Pos               (2U)
-#define PWR_SR1_WUF3_Msk               (0x1UL << PWR_SR1_WUF3_Pos)             /*!< 0x00000004 */
-#define PWR_SR1_WUF3                   PWR_SR1_WUF3_Msk                        /*!< Wakeup Pin 3 [Flag 2] */
-
-#define PWR_SR1_WPVDF_Pos              (8U)
-#define PWR_SR1_WPVDF_Msk              (0x1UL << PWR_SR1_WPVDF_Pos)            /*!< 0x00000100 */
-#define PWR_SR1_WPVDF                  PWR_SR1_WPVDF_Msk                       /*!< Wakeup PVD flag */
-
-#define PWR_SR1_WRFBUSYF_Pos           (11U)
-#define PWR_SR1_WRFBUSYF_Msk           (0x1UL << PWR_SR1_WRFBUSYF_Pos)          /*!< 0x00000800 */
-#define PWR_SR1_WRFBUSYF               PWR_SR1_WRFBUSYF_Msk                     /*!< Wakeup radio busy flag */
-
-#define PWR_SR1_WUFI_Pos               (15U)
-#define PWR_SR1_WUFI_Msk               (0x1UL << PWR_SR1_WUFI_Pos)             /*!< 0x00008000 */
-#define PWR_SR1_WUFI                   PWR_SR1_WUFI_Msk                        /*!< Internal wakeup interrupt flag */
-
-/********************  Bit definition for PWR_SR2 register  ********************/
-#define PWR_SR2_RFBUSYS_Pos            (1U)
-#define PWR_SR2_RFBUSYS_Msk            (0x1UL << PWR_SR2_RFBUSYS_Pos)          /*!< 0x00000002 */
-#define PWR_SR2_RFBUSYS                PWR_SR2_RFBUSYS_Msk                     /*!< Radio busy signal status */
-
-#define PWR_SR2_RFBUSYMS_Pos           (2U)
-#define PWR_SR2_RFBUSYMS_Msk           (0x1UL << PWR_SR2_RFBUSYMS_Pos)         /*!< 0x00000004 */
-#define PWR_SR2_RFBUSYMS               PWR_SR2_RFBUSYMS_Msk                    /*!< Radio busy masked signal status */
-
-#define PWR_SR2_SMPSRDY_Pos            (3U)
-#define PWR_SR2_SMPSRDY_Msk            (0x1UL << PWR_SR2_SMPSRDY_Pos)          /*!< 0x00000008 */
-#define PWR_SR2_SMPSRDY                PWR_SR2_SMPSRDY_Msk                     /*!< SMPS ready flag */
-#define PWR_SR2_LDORDY_Pos             (4U)
-#define PWR_SR2_LDORDY_Msk             (0x1UL << PWR_SR2_LDORDY_Pos)           /*!< 0x00000010 */
-#define PWR_SR2_LDORDY                 PWR_SR2_LDORDY_Msk                      /*!< LDO ready flag */
-
-#define PWR_SR2_RFEOLF_Pos             (5U)
-#define PWR_SR2_RFEOLF_Msk             (0x1UL << PWR_SR2_RFEOLF_Pos)           /*!< 0x00000020 */
-#define PWR_SR2_RFEOLF                 PWR_SR2_RFEOLF_Msk                      /*!< Radio end of life flag */
-
-#define PWR_SR2_REGMRS_Pos             (6U)
-#define PWR_SR2_REGMRS_Msk             (0x1UL << PWR_SR2_REGMRS_Pos)           /*!< 0x00000040 */
-#define PWR_SR2_REGMRS                 PWR_SR2_REGMRS_Msk                      /*!< Main regulator status */
-
-#define PWR_SR2_FLASHRDY_Pos           (7U)
-#define PWR_SR2_FLASHRDY_Msk           (0x1UL << PWR_SR2_FLASHRDY_Pos)         /*!< 0x00000080 */
-#define PWR_SR2_FLASHRDY               PWR_SR2_FLASHRDY_Msk                    /*!< Flash ready */
-
-#define PWR_SR2_REGLPS_Pos             (8U)
-#define PWR_SR2_REGLPS_Msk             (0x1UL << PWR_SR2_REGLPS_Pos)           /*!< 0x00000100 */
-#define PWR_SR2_REGLPS                 PWR_SR2_REGLPS_Msk                      /*!< Low-power regulator ready */
-#define PWR_SR2_REGLPF_Pos             (9U)
-#define PWR_SR2_REGLPF_Msk             (0x1UL << PWR_SR2_REGLPF_Pos)           /*!< 0x00000200 */
-#define PWR_SR2_REGLPF                 PWR_SR2_REGLPF_Msk                      /*!< Low-power regulator being used */
-
-#define PWR_SR2_VOSF_Pos               (10U)
-#define PWR_SR2_VOSF_Msk               (0x1UL << PWR_SR2_VOSF_Pos)             /*!< 0x00000400 */
-#define PWR_SR2_VOSF                   PWR_SR2_VOSF_Msk                        /*!< Voltage scaling flag    */
-#define PWR_SR2_PVDO_Pos               (11U)
-#define PWR_SR2_PVDO_Msk               (0x1UL << PWR_SR2_PVDO_Pos)             /*!< 0x00000800 */
-#define PWR_SR2_PVDO                   PWR_SR2_PVDO_Msk                        /*!< Power voltage detector output */
-
-#define PWR_SR2_PVMO3_Pos              (14U)
-#define PWR_SR2_PVMO3_Msk              (0x1UL << PWR_SR2_PVMO3_Pos)            /*!< 0x00004000 */
-#define PWR_SR2_PVMO3                  PWR_SR2_PVMO3_Msk                       /*!< Peripheral voltage monitor output 3: VDDA vs. 1.62V */
-
-/********************  Bit definition for PWR_SCR register  ********************/
-#define PWR_SCR_CWUF_Pos               (0U)
-#define PWR_SCR_CWUF_Msk               (0x7UL << PWR_SCR_CWUF_Pos)             /*!< 0x00000007 */
-#define PWR_SCR_CWUF                   PWR_SCR_CWUF_Msk                        /*!< Clear Wake-up Flags for all pins */
-#define PWR_SCR_CWUF1_Pos              (0U)
-#define PWR_SCR_CWUF1_Msk              (0x1UL << PWR_SCR_CWUF1_Pos)            /*!< 0x00000001 */
-#define PWR_SCR_CWUF1                  PWR_SCR_CWUF1_Msk                       /*!< Clear Wake-up Pin 1 [Flag 0] */
-#define PWR_SCR_CWUF2_Pos              (1U)
-#define PWR_SCR_CWUF2_Msk              (0x1UL << PWR_SCR_CWUF2_Pos)            /*!< 0x00000002 */
-#define PWR_SCR_CWUF2                  PWR_SCR_CWUF2_Msk                       /*!< Clear Wake-up Pin 2 [Flag 1] */
-#define PWR_SCR_CWUF3_Pos              (2U)
-#define PWR_SCR_CWUF3_Msk              (0x1UL << PWR_SCR_CWUF3_Pos)            /*!< 0x00000004 */
-#define PWR_SCR_CWUF3                  PWR_SCR_CWUF3_Msk                       /*!< Clear Wake-up Pin 3 [Flag 2] */
-
-#define PWR_SCR_CWPVDF_Pos             (8U)
-#define PWR_SCR_CWPVDF_Msk             (0x1UL << PWR_SCR_CWPVDF_Pos)           /*!< 0x00000100 */
-#define PWR_SCR_CWPVDF                 PWR_SCR_CWPVDF_Msk                      /*!< Clear wakeup PVD interrupt flag */
-
-#define PWR_SCR_CWRFBUSYF_Pos          (11U)
-#define PWR_SCR_CWRFBUSYF_Msk          (0x1UL << PWR_SCR_CWRFBUSYF_Pos)        /*!< 0x00000800 */
-#define PWR_SCR_CWRFBUSYF              PWR_SCR_CWRFBUSYF_Msk                   /*!< Clear Radio busy interrupt flag */
-
-/********************  Bit definition for PWR_CR5 register  ********************/
-#define PWR_CR5_RFEOLEN_Pos            (14U)
-#define PWR_CR5_RFEOLEN_Msk            (0x1UL << PWR_CR5_RFEOLEN_Pos)           /*!< 0x00004000 */
-#define PWR_CR5_RFEOLEN                PWR_CR5_RFEOLEN_Msk                      /*!< Enable Radio End Of Life detector enabled */
-
-#define PWR_CR5_SMPSEN_Pos             (15U)
-#define PWR_CR5_SMPSEN_Msk             (0x1UL << PWR_CR5_SMPSEN_Pos)           /*!< 0x00008000 */
-#define PWR_CR5_SMPSEN                 PWR_CR5_SMPSEN_Msk                      /*!< Enable SMPS Step Down converter SMPS mode enable */
-
-/********************  Bit definition for PWR_PUCRA register  *****************/
-#define PWR_PUCRA_PA0_Pos              (0U)
-#define PWR_PUCRA_PA0_Msk              (0x1UL << PWR_PUCRA_PA0_Pos)            /*!< 0x00000001 */
-#define PWR_PUCRA_PA0                  PWR_PUCRA_PA0_Msk                       /*!< Pin PA0 Pull-Up set */
-#define PWR_PUCRA_PA1_Pos              (1U)
-#define PWR_PUCRA_PA1_Msk              (0x1UL << PWR_PUCRA_PA1_Pos)            /*!< 0x00000002 */
-#define PWR_PUCRA_PA1                  PWR_PUCRA_PA1_Msk                       /*!< Pin PA1 Pull-Up set */
-#define PWR_PUCRA_PA2_Pos              (2U)
-#define PWR_PUCRA_PA2_Msk              (0x1UL << PWR_PUCRA_PA2_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRA_PA2                  PWR_PUCRA_PA2_Msk                       /*!< Pin PA2 Pull-Up set */
-#define PWR_PUCRA_PA3_Pos              (3U)
-#define PWR_PUCRA_PA3_Msk              (0x1UL << PWR_PUCRA_PA3_Pos)            /*!< 0x00000008 */
-#define PWR_PUCRA_PA3                  PWR_PUCRA_PA3_Msk                       /*!< Pin PA3 Pull-Up set */
-#define PWR_PUCRA_PA4_Pos              (4U)
-#define PWR_PUCRA_PA4_Msk              (0x1UL << PWR_PUCRA_PA4_Pos)            /*!< 0x00000010 */
-#define PWR_PUCRA_PA4                  PWR_PUCRA_PA4_Msk                       /*!< Pin PA4 Pull-Up set */
-#define PWR_PUCRA_PA5_Pos              (5U)
-#define PWR_PUCRA_PA5_Msk              (0x1UL << PWR_PUCRA_PA5_Pos)            /*!< 0x00000020 */
-#define PWR_PUCRA_PA5                  PWR_PUCRA_PA5_Msk                       /*!< Pin PA5 Pull-Up set */
-#define PWR_PUCRA_PA6_Pos              (6U)
-#define PWR_PUCRA_PA6_Msk              (0x1UL << PWR_PUCRA_PA6_Pos)            /*!< 0x00000040 */
-#define PWR_PUCRA_PA6                  PWR_PUCRA_PA6_Msk                       /*!< Pin PA6 Pull-Up set */
-#define PWR_PUCRA_PA7_Pos              (7U)
-#define PWR_PUCRA_PA7_Msk              (0x1UL << PWR_PUCRA_PA7_Pos)            /*!< 0x00000080 */
-#define PWR_PUCRA_PA7                  PWR_PUCRA_PA7_Msk                       /*!< Pin PA7 Pull-Up set */
-#define PWR_PUCRA_PA8_Pos              (8U)
-#define PWR_PUCRA_PA8_Msk              (0x1UL << PWR_PUCRA_PA8_Pos)            /*!< 0x00000100 */
-#define PWR_PUCRA_PA8                  PWR_PUCRA_PA8_Msk                       /*!< Pin PA8 Pull-Up set */
-#define PWR_PUCRA_PA9_Pos              (9U)
-#define PWR_PUCRA_PA9_Msk              (0x1UL << PWR_PUCRA_PA9_Pos)            /*!< 0x00000200 */
-#define PWR_PUCRA_PA9                  PWR_PUCRA_PA9_Msk                       /*!< Pin PA9 Pull-Up set */
-#define PWR_PUCRA_PA10_Pos             (10U)
-#define PWR_PUCRA_PA10_Msk             (0x1UL << PWR_PUCRA_PA10_Pos)           /*!< 0x00000400 */
-#define PWR_PUCRA_PA10                 PWR_PUCRA_PA10_Msk                      /*!< Pin PA10 Pull-Up set */
-#define PWR_PUCRA_PA11_Pos             (11U)
-#define PWR_PUCRA_PA11_Msk             (0x1UL << PWR_PUCRA_PA11_Pos)           /*!< 0x00000800 */
-#define PWR_PUCRA_PA11                 PWR_PUCRA_PA11_Msk                      /*!< Pin PA11 Pull-Up set */
-#define PWR_PUCRA_PA12_Pos             (12U)
-#define PWR_PUCRA_PA12_Msk             (0x1UL << PWR_PUCRA_PA12_Pos)           /*!< 0x00001000 */
-#define PWR_PUCRA_PA12                 PWR_PUCRA_PA12_Msk                      /*!< Pin PA12 Pull-Up set */
-#define PWR_PUCRA_PA13_Pos             (13U)
-#define PWR_PUCRA_PA13_Msk             (0x1UL << PWR_PUCRA_PA13_Pos)           /*!< 0x00002000 */
-#define PWR_PUCRA_PA13                 PWR_PUCRA_PA13_Msk                      /*!< Pin PA13 Pull-Up set */
-#define PWR_PUCRA_PA14_Pos             (14U)
-#define PWR_PUCRA_PA14_Msk             (0x1UL << PWR_PUCRA_PA14_Pos)           /*!< 0x00004000 */
-#define PWR_PUCRA_PA14                 PWR_PUCRA_PA14_Msk                      /*!< Pin PA14 Pull-Up set */
-#define PWR_PUCRA_PA15_Pos             (15U)
-#define PWR_PUCRA_PA15_Msk             (0x1UL << PWR_PUCRA_PA15_Pos)           /*!< 0x00008000 */
-#define PWR_PUCRA_PA15                 PWR_PUCRA_PA15_Msk                      /*!< Pin PA15 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRA register  *****************/
-#define PWR_PDCRA_PA0_Pos              (0U)
-#define PWR_PDCRA_PA0_Msk              (0x1UL << PWR_PDCRA_PA0_Pos)            /*!< 0x00000001 */
-#define PWR_PDCRA_PA0                  PWR_PDCRA_PA0_Msk                       /*!< Pin PA0 Pull-Down set */
-#define PWR_PDCRA_PA1_Pos              (1U)
-#define PWR_PDCRA_PA1_Msk              (0x1UL << PWR_PDCRA_PA1_Pos)            /*!< 0x00000002 */
-#define PWR_PDCRA_PA1                  PWR_PDCRA_PA1_Msk                       /*!< Pin PA1 Pull-Down set */
-#define PWR_PDCRA_PA2_Pos              (2U)
-#define PWR_PDCRA_PA2_Msk              (0x1UL << PWR_PDCRA_PA2_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRA_PA2                  PWR_PDCRA_PA2_Msk                       /*!< Pin PA2 Pull-Down set */
-#define PWR_PDCRA_PA3_Pos              (3U)
-#define PWR_PDCRA_PA3_Msk              (0x1UL << PWR_PDCRA_PA3_Pos)            /*!< 0x00000008 */
-#define PWR_PDCRA_PA3                  PWR_PDCRA_PA3_Msk                       /*!< Pin PA3 Pull-Down set */
-#define PWR_PDCRA_PA4_Pos              (4U)
-#define PWR_PDCRA_PA4_Msk              (0x1UL << PWR_PDCRA_PA4_Pos)            /*!< 0x00000010 */
-#define PWR_PDCRA_PA4                  PWR_PDCRA_PA4_Msk                       /*!< Pin PA4 Pull-Down set */
-#define PWR_PDCRA_PA5_Pos              (5U)
-#define PWR_PDCRA_PA5_Msk              (0x1UL << PWR_PDCRA_PA5_Pos)            /*!< 0x00000020 */
-#define PWR_PDCRA_PA5                  PWR_PDCRA_PA5_Msk                       /*!< Pin PA5 Pull-Down set */
-#define PWR_PDCRA_PA6_Pos              (6U)
-#define PWR_PDCRA_PA6_Msk              (0x1UL << PWR_PDCRA_PA6_Pos)            /*!< 0x00000040 */
-#define PWR_PDCRA_PA6                  PWR_PDCRA_PA6_Msk                       /*!< Pin PA6 Pull-Down set */
-#define PWR_PDCRA_PA7_Pos              (7U)
-#define PWR_PDCRA_PA7_Msk              (0x1UL << PWR_PDCRA_PA7_Pos)            /*!< 0x00000080 */
-#define PWR_PDCRA_PA7                  PWR_PDCRA_PA7_Msk                       /*!< Pin PA7 Pull-Down set */
-#define PWR_PDCRA_PA8_Pos              (8U)
-#define PWR_PDCRA_PA8_Msk              (0x1UL << PWR_PDCRA_PA8_Pos)            /*!< 0x00000100 */
-#define PWR_PDCRA_PA8                  PWR_PDCRA_PA8_Msk                       /*!< Pin PA8 Pull-Down set */
-#define PWR_PDCRA_PA9_Pos              (9U)
-#define PWR_PDCRA_PA9_Msk              (0x1UL << PWR_PDCRA_PA9_Pos)            /*!< 0x00000200 */
-#define PWR_PDCRA_PA9                  PWR_PDCRA_PA9_Msk                       /*!< Pin PA9 Pull-Down set */
-#define PWR_PDCRA_PA10_Pos             (10U)
-#define PWR_PDCRA_PA10_Msk             (0x1UL << PWR_PDCRA_PA10_Pos)           /*!< 0x00000400 */
-#define PWR_PDCRA_PA10                 PWR_PDCRA_PA10_Msk                      /*!< Pin PA10 Pull-Down set */
-#define PWR_PDCRA_PA11_Pos             (11U)
-#define PWR_PDCRA_PA11_Msk             (0x1UL << PWR_PDCRA_PA11_Pos)           /*!< 0x00000800 */
-#define PWR_PDCRA_PA11                 PWR_PDCRA_PA11_Msk                      /*!< Pin PA11 Pull-Down set */
-#define PWR_PDCRA_PA12_Pos             (12U)
-#define PWR_PDCRA_PA12_Msk             (0x1UL << PWR_PDCRA_PA12_Pos)           /*!< 0x00001000 */
-#define PWR_PDCRA_PA12                 PWR_PDCRA_PA12_Msk                      /*!< Pin PA12 Pull-Down set */
-#define PWR_PDCRA_PA13_Pos             (13U)
-#define PWR_PDCRA_PA13_Msk             (0x1UL << PWR_PDCRA_PA13_Pos)           /*!< 0x00002000 */
-#define PWR_PDCRA_PA13                 PWR_PDCRA_PA13_Msk                      /*!< Pin PA13 Pull-Down set */
-#define PWR_PDCRA_PA14_Pos             (14U)
-#define PWR_PDCRA_PA14_Msk             (0x1UL << PWR_PDCRA_PA14_Pos)           /*!< 0x00004000 */
-#define PWR_PDCRA_PA14                 PWR_PDCRA_PA14_Msk                      /*!< Pin PA14 Pull-Down set */
-#define PWR_PDCRA_PA15_Pos             (15U)
-#define PWR_PDCRA_PA15_Msk             (0x1UL << PWR_PDCRA_PA15_Pos)           /*!< 0x00008000 */
-#define PWR_PDCRA_PA15                 PWR_PDCRA_PA15_Msk                      /*!< Pin PA15 Pull-Down set */
-
-/********************  Bit definition for PWR_PUCRB register  *****************/
-#define PWR_PUCRB_PB0_Pos              (0U)
-#define PWR_PUCRB_PB0_Msk              (0x1UL << PWR_PUCRB_PB0_Pos)            /*!< 0x00000001 */
-#define PWR_PUCRB_PB0                  PWR_PUCRB_PB0_Msk                       /*!< Pin PB0 Pull-Up set */
-#define PWR_PUCRB_PB1_Pos              (1U)
-#define PWR_PUCRB_PB1_Msk              (0x1UL << PWR_PUCRB_PB1_Pos)            /*!< 0x00000002 */
-#define PWR_PUCRB_PB1                  PWR_PUCRB_PB1_Msk                       /*!< Pin PB1 Pull-Up set */
-#define PWR_PUCRB_PB2_Pos              (2U)
-#define PWR_PUCRB_PB2_Msk              (0x1UL << PWR_PUCRB_PB2_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRB_PB2                  PWR_PUCRB_PB2_Msk                       /*!< Pin PB2 Pull-Up set */
-#define PWR_PUCRB_PB3_Pos              (3U)
-#define PWR_PUCRB_PB3_Msk              (0x1UL << PWR_PUCRB_PB3_Pos)            /*!< 0x00000008 */
-#define PWR_PUCRB_PB3                  PWR_PUCRB_PB3_Msk                       /*!< Pin PB3 Pull-Up set */
-#define PWR_PUCRB_PB4_Pos              (4U)
-#define PWR_PUCRB_PB4_Msk              (0x1UL << PWR_PUCRB_PB4_Pos)            /*!< 0x00000010 */
-#define PWR_PUCRB_PB4                  PWR_PUCRB_PB4_Msk                       /*!< Pin PB4 Pull-Up set */
-#define PWR_PUCRB_PB5_Pos              (5U)
-#define PWR_PUCRB_PB5_Msk              (0x1UL << PWR_PUCRB_PB5_Pos)            /*!< 0x00000020 */
-#define PWR_PUCRB_PB5                  PWR_PUCRB_PB5_Msk                       /*!< Pin PB5 Pull-Up set */
-#define PWR_PUCRB_PB6_Pos              (6U)
-#define PWR_PUCRB_PB6_Msk              (0x1UL << PWR_PUCRB_PB6_Pos)            /*!< 0x00000040 */
-#define PWR_PUCRB_PB6                  PWR_PUCRB_PB6_Msk                       /*!< Pin PB6 Pull-Up set */
-#define PWR_PUCRB_PB7_Pos              (7U)
-#define PWR_PUCRB_PB7_Msk              (0x1UL << PWR_PUCRB_PB7_Pos)            /*!< 0x00000080 */
-#define PWR_PUCRB_PB7                  PWR_PUCRB_PB7_Msk                       /*!< Pin PB7 Pull-Up set */
-#define PWR_PUCRB_PB8_Pos              (8U)
-#define PWR_PUCRB_PB8_Msk              (0x1UL << PWR_PUCRB_PB8_Pos)            /*!< 0x00000100 */
-#define PWR_PUCRB_PB8                  PWR_PUCRB_PB8_Msk                       /*!< Pin PB8 Pull-Up set */
-#define PWR_PUCRB_PB9_Pos              (9U)
-#define PWR_PUCRB_PB9_Msk              (0x1UL << PWR_PUCRB_PB9_Pos)            /*!< 0x00000200 */
-#define PWR_PUCRB_PB9                  PWR_PUCRB_PB9_Msk                       /*!< Pin PB9 Pull-Up set */
-#define PWR_PUCRB_PB10_Pos             (10U)
-#define PWR_PUCRB_PB10_Msk             (0x1UL << PWR_PUCRB_PB10_Pos)           /*!< 0x00000400 */
-#define PWR_PUCRB_PB10                 PWR_PUCRB_PB10_Msk                      /*!< Pin PB10 Pull-Up set */
-#define PWR_PUCRB_PB11_Pos             (11U)
-#define PWR_PUCRB_PB11_Msk             (0x1UL << PWR_PUCRB_PB11_Pos)           /*!< 0x00000800 */
-#define PWR_PUCRB_PB11                 PWR_PUCRB_PB11_Msk                      /*!< Pin PB11 Pull-Up set */
-#define PWR_PUCRB_PB12_Pos             (12U)
-#define PWR_PUCRB_PB12_Msk             (0x1UL << PWR_PUCRB_PB12_Pos)           /*!< 0x00001000 */
-#define PWR_PUCRB_PB12                 PWR_PUCRB_PB12_Msk                      /*!< Pin PB12 Pull-Up set */
-#define PWR_PUCRB_PB13_Pos             (13U)
-#define PWR_PUCRB_PB13_Msk             (0x1UL << PWR_PUCRB_PB13_Pos)           /*!< 0x00002000 */
-#define PWR_PUCRB_PB13                 PWR_PUCRB_PB13_Msk                      /*!< Pin PB13 Pull-Up set */
-#define PWR_PUCRB_PB14_Pos             (14U)
-#define PWR_PUCRB_PB14_Msk             (0x1UL << PWR_PUCRB_PB14_Pos)           /*!< 0x00004000 */
-#define PWR_PUCRB_PB14                 PWR_PUCRB_PB14_Msk                      /*!< Pin PB14 Pull-Up set */
-#define PWR_PUCRB_PB15_Pos             (15U)
-#define PWR_PUCRB_PB15_Msk             (0x1UL << PWR_PUCRB_PB15_Pos)           /*!< 0x00008000 */
-#define PWR_PUCRB_PB15                 PWR_PUCRB_PB15_Msk                      /*!< Pin PB15 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRB register  *****************/
-#define PWR_PDCRB_PB0_Pos              (0U)
-#define PWR_PDCRB_PB0_Msk              (0x1UL << PWR_PDCRB_PB0_Pos)            /*!< 0x00000001 */
-#define PWR_PDCRB_PB0                  PWR_PDCRB_PB0_Msk                       /*!< Pin PB0 Pull-Down set */
-#define PWR_PDCRB_PB1_Pos              (1U)
-#define PWR_PDCRB_PB1_Msk              (0x1UL << PWR_PDCRB_PB1_Pos)            /*!< 0x00000002 */
-#define PWR_PDCRB_PB1                  PWR_PDCRB_PB1_Msk                       /*!< Pin PB1 Pull-Down set */
-#define PWR_PDCRB_PB2_Pos              (2U)
-#define PWR_PDCRB_PB2_Msk              (0x1UL << PWR_PDCRB_PB2_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRB_PB2                  PWR_PDCRB_PB2_Msk                       /*!< Pin PB2 Pull-Down set */
-#define PWR_PDCRB_PB3_Pos              (3U)
-#define PWR_PDCRB_PB3_Msk              (0x1UL << PWR_PDCRB_PB3_Pos)            /*!< 0x00000008 */
-#define PWR_PDCRB_PB3                  PWR_PDCRB_PB3_Msk                       /*!< Pin PB3 Pull-Down set */
-#define PWR_PDCRB_PB4_Pos              (4U)
-#define PWR_PDCRB_PB4_Msk              (0x1UL << PWR_PDCRB_PB4_Pos)            /*!< 0x00000010 */
-#define PWR_PDCRB_PB4                  PWR_PDCRB_PB4_Msk                       /*!< Pin PB4 Pull-Down set */
-#define PWR_PDCRB_PB5_Pos              (5U)
-#define PWR_PDCRB_PB5_Msk              (0x1UL << PWR_PDCRB_PB5_Pos)            /*!< 0x00000020 */
-#define PWR_PDCRB_PB5                  PWR_PDCRB_PB5_Msk                       /*!< Pin PB5 Pull-Down set */
-#define PWR_PDCRB_PB6_Pos              (6U)
-#define PWR_PDCRB_PB6_Msk              (0x1UL << PWR_PDCRB_PB6_Pos)            /*!< 0x00000040 */
-#define PWR_PDCRB_PB6                  PWR_PDCRB_PB6_Msk                       /*!< Pin PB6 Pull-Down set */
-#define PWR_PDCRB_PB7_Pos              (7U)
-#define PWR_PDCRB_PB7_Msk              (0x1UL << PWR_PDCRB_PB7_Pos)            /*!< 0x00000080 */
-#define PWR_PDCRB_PB7                  PWR_PDCRB_PB7_Msk                       /*!< Pin PB7 Pull-Down set */
-#define PWR_PDCRB_PB8_Pos              (8U)
-#define PWR_PDCRB_PB8_Msk              (0x1UL << PWR_PDCRB_PB8_Pos)            /*!< 0x00000100 */
-#define PWR_PDCRB_PB8                  PWR_PDCRB_PB8_Msk                       /*!< Pin PB8 Pull-Down set */
-#define PWR_PDCRB_PB9_Pos              (9U)
-#define PWR_PDCRB_PB9_Msk              (0x1UL << PWR_PDCRB_PB9_Pos)            /*!< 0x00000200 */
-#define PWR_PDCRB_PB9                  PWR_PDCRB_PB9_Msk                       /*!< Pin PB9 Pull-Down set */
-#define PWR_PDCRB_PB10_Pos             (10U)
-#define PWR_PDCRB_PB10_Msk             (0x1UL << PWR_PDCRB_PB10_Pos)           /*!< 0x00000400 */
-#define PWR_PDCRB_PB10                 PWR_PDCRB_PB10_Msk                      /*!< Pin PB10 Pull-Down set */
-#define PWR_PDCRB_PB11_Pos             (11U)
-#define PWR_PDCRB_PB11_Msk             (0x1UL << PWR_PDCRB_PB11_Pos)           /*!< 0x00000800 */
-#define PWR_PDCRB_PB11                 PWR_PDCRB_PB11_Msk                      /*!< Pin PB11 Pull-Down set */
-#define PWR_PDCRB_PB12_Pos             (12U)
-#define PWR_PDCRB_PB12_Msk             (0x1UL << PWR_PDCRB_PB12_Pos)           /*!< 0x00001000 */
-#define PWR_PDCRB_PB12                 PWR_PDCRB_PB12_Msk                      /*!< Pin PB12 Pull-Down set */
-#define PWR_PDCRB_PB13_Pos             (13U)
-#define PWR_PDCRB_PB13_Msk             (0x1UL << PWR_PDCRB_PB13_Pos)           /*!< 0x00002000 */
-#define PWR_PDCRB_PB13                 PWR_PDCRB_PB13_Msk                      /*!< Pin PB13 Pull-Down set */
-#define PWR_PDCRB_PB14_Pos             (14U)
-#define PWR_PDCRB_PB14_Msk             (0x1UL << PWR_PDCRB_PB14_Pos)           /*!< 0x00004000 */
-#define PWR_PDCRB_PB14                 PWR_PDCRB_PB14_Msk                      /*!< Pin PB14 Pull-Down set */
-#define PWR_PDCRB_PB15_Pos             (15U)
-#define PWR_PDCRB_PB15_Msk             (0x1UL << PWR_PDCRB_PB15_Pos)           /*!< 0x00008000 */
-#define PWR_PDCRB_PB15                 PWR_PDCRB_PB15_Msk                      /*!< Pin PB15 Pull-Down set */
-
-/********************  Bit definition for PWR_PUCRC register  *****************/
-#define PWR_PUCRC_PC0_Pos              (0U)
-#define PWR_PUCRC_PC0_Msk              (0x1UL << PWR_PUCRC_PC0_Pos)            /*!< 0x00000001 */
-#define PWR_PUCRC_PC0                  PWR_PUCRC_PC0_Msk                       /*!< Pin PC0 Pull-Up set */
-#define PWR_PUCRC_PC1_Pos              (1U)
-#define PWR_PUCRC_PC1_Msk              (0x1UL << PWR_PUCRC_PC1_Pos)            /*!< 0x00000002 */
-#define PWR_PUCRC_PC1                  PWR_PUCRC_PC1_Msk                       /*!< Pin PC1 Pull-Up set */
-#define PWR_PUCRC_PC2_Pos              (2U)
-#define PWR_PUCRC_PC2_Msk              (0x1UL << PWR_PUCRC_PC2_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRC_PC2                  PWR_PUCRC_PC2_Msk                       /*!< Pin PC2 Pull-Up set */
-#define PWR_PUCRC_PC3_Pos              (3U)
-#define PWR_PUCRC_PC3_Msk              (0x1UL << PWR_PUCRC_PC3_Pos)            /*!< 0x00000008 */
-#define PWR_PUCRC_PC3                  PWR_PUCRC_PC3_Msk                       /*!< Pin PC3 Pull-Up set */
-#define PWR_PUCRC_PC4_Pos              (4U)
-#define PWR_PUCRC_PC4_Msk              (0x1UL << PWR_PUCRC_PC4_Pos)            /*!< 0x00000010 */
-#define PWR_PUCRC_PC4                  PWR_PUCRC_PC4_Msk                       /*!< Pin PC4 Pull-Up set */
-#define PWR_PUCRC_PC5_Pos              (5U)
-#define PWR_PUCRC_PC5_Msk              (0x1UL << PWR_PUCRC_PC5_Pos)            /*!< 0x00000020 */
-#define PWR_PUCRC_PC5                  PWR_PUCRC_PC5_Msk                       /*!< Pin PC5 Pull-Up set */
-#define PWR_PUCRC_PC6_Pos              (6U)
-#define PWR_PUCRC_PC6_Msk              (0x1UL << PWR_PUCRC_PC6_Pos)            /*!< 0x00000040 */
-#define PWR_PUCRC_PC6                  PWR_PUCRC_PC6_Msk                       /*!< Pin PC6 Pull-Up set */
-#define PWR_PUCRC_PC13_Pos             (13U)
-#define PWR_PUCRC_PC13_Msk             (0x1UL << PWR_PUCRC_PC13_Pos)           /*!< 0x00002000 */
-#define PWR_PUCRC_PC13                 PWR_PUCRC_PC13_Msk                      /*!< Pin PC13 Pull-Up set */
-#define PWR_PUCRC_PC14_Pos             (14U)
-#define PWR_PUCRC_PC14_Msk             (0x1UL << PWR_PUCRC_PC14_Pos)           /*!< 0x00004000 */
-#define PWR_PUCRC_PC14                 PWR_PUCRC_PC14_Msk                      /*!< Pin PC14 Pull-Up set */
-#define PWR_PUCRC_PC15_Pos             (15U)
-#define PWR_PUCRC_PC15_Msk             (0x1UL << PWR_PUCRC_PC15_Pos)           /*!< 0x00008000 */
-#define PWR_PUCRC_PC15                 PWR_PUCRC_PC15_Msk                      /*!< Pin PC15 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRC register  *****************/
-#define PWR_PDCRC_PC0_Pos              (0U)
-#define PWR_PDCRC_PC0_Msk              (0x1UL << PWR_PDCRC_PC0_Pos)            /*!< 0x00000001 */
-#define PWR_PDCRC_PC0                  PWR_PDCRC_PC0_Msk                       /*!< Pin PC0 Pull-Down set */
-#define PWR_PDCRC_PC1_Pos              (1U)
-#define PWR_PDCRC_PC1_Msk              (0x1UL << PWR_PDCRC_PC1_Pos)            /*!< 0x00000002 */
-#define PWR_PDCRC_PC1                  PWR_PDCRC_PC1_Msk                       /*!< Pin PC1 Pull-Down set */
-#define PWR_PDCRC_PC2_Pos              (2U)
-#define PWR_PDCRC_PC2_Msk              (0x1UL << PWR_PDCRC_PC2_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRC_PC2                  PWR_PDCRC_PC2_Msk                       /*!< Pin PC2 Pull-Down set */
-#define PWR_PDCRC_PC3_Pos              (3U)
-#define PWR_PDCRC_PC3_Msk              (0x1UL << PWR_PDCRC_PC3_Pos)            /*!< 0x00000008 */
-#define PWR_PDCRC_PC3                  PWR_PDCRC_PC3_Msk                       /*!< Pin PC3 Pull-Down set */
-#define PWR_PDCRC_PC4_Pos              (4U)
-#define PWR_PDCRC_PC4_Msk              (0x1UL << PWR_PDCRC_PC4_Pos)            /*!< 0x00000010 */
-#define PWR_PDCRC_PC4                  PWR_PDCRC_PC4_Msk                       /*!< Pin PC4 Pull-Down set */
-#define PWR_PDCRC_PC5_Pos              (5U)
-#define PWR_PDCRC_PC5_Msk              (0x1UL << PWR_PDCRC_PC5_Pos)            /*!< 0x00000020 */
-#define PWR_PDCRC_PC5                  PWR_PDCRC_PC5_Msk                       /*!< Pin PC5 Pull-Down set */
-#define PWR_PDCRC_PC6_Pos              (6U)
-#define PWR_PDCRC_PC6_Msk              (0x1UL << PWR_PDCRC_PC6_Pos)            /*!< 0x00000040 */
-#define PWR_PDCRC_PC6                  PWR_PDCRC_PC6_Msk                       /*!< Pin PC6 Pull-Down set */
-#define PWR_PDCRC_PC13_Pos             (13U)
-#define PWR_PDCRC_PC13_Msk             (0x1UL << PWR_PDCRC_PC13_Pos)           /*!< 0x00002000 */
-#define PWR_PDCRC_PC13                 PWR_PDCRC_PC13_Msk                      /*!< Pin PC13 Pull-Down set */
-#define PWR_PDCRC_PC14_Pos             (14U)
-#define PWR_PDCRC_PC14_Msk             (0x1UL << PWR_PDCRC_PC14_Pos)           /*!< 0x00004000 */
-#define PWR_PDCRC_PC14                 PWR_PDCRC_PC14_Msk                      /*!< Pin PC14 Pull-Down set */
-#define PWR_PDCRC_PC15_Pos             (15U)
-#define PWR_PDCRC_PC15_Msk             (0x1UL << PWR_PDCRC_PC15_Pos)           /*!< 0x00008000 */
-#define PWR_PDCRC_PC15                 PWR_PDCRC_PC15_Msk                      /*!< Pin PC15 Pull-Down set */
-
-/********************  Bit definition for PWR_PUCRH register  *****************/
-#define PWR_PUCRH_PH3_Pos              (3U)
-#define PWR_PUCRH_PH3_Msk              (0x1UL << PWR_PUCRH_PH3_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRH_PH3                  PWR_PUCRH_PH3_Msk                       /*!< Pin PH3 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRH register  *****************/
-#define PWR_PDCRH_PH3_Pos              (3U)
-#define PWR_PDCRH_PH3_Msk              (0x1UL << PWR_PDCRH_PH3_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRH_PH3                  PWR_PDCRH_PH3_Msk                       /*!< Pin PH3 Pull-Down set */
-
-/********************  Bit definition for PWR_EXTSCR register  ********************/
-#define PWR_EXTSCR_C1CSSF_Pos          (0U)
-#define PWR_EXTSCR_C1CSSF_Msk          (0x1UL << PWR_EXTSCR_C1CSSF_Pos)        /*!< 0x00000001 */
-#define PWR_EXTSCR_C1CSSF              PWR_EXTSCR_C1CSSF_Msk                   /*!< Clear standby and stop flags for CPU1 */
-
-#define PWR_EXTSCR_C1SBF_Pos           (8U)
-#define PWR_EXTSCR_C1SBF_Msk           (0x1UL << PWR_EXTSCR_C1SBF_Pos)         /*!< 0x00000100 */
-#define PWR_EXTSCR_C1SBF               PWR_EXTSCR_C1SBF_Msk                    /*!< System standby flag for CPU1 */
-#define PWR_EXTSCR_C1STOP2F_Pos        (9U)
-#define PWR_EXTSCR_C1STOP2F_Msk        (0x1UL << PWR_EXTSCR_C1STOP2F_Pos)      /*!< 0x00000200 */
-#define PWR_EXTSCR_C1STOP2F            PWR_EXTSCR_C1STOP2F_Msk                 /*!< System stop2 flag for CPU1 */
-#define PWR_EXTSCR_C1STOPF_Pos         (10U)
-#define PWR_EXTSCR_C1STOPF_Msk         (0x1UL << PWR_EXTSCR_C1STOPF_Pos)       /*!< 0x00000400 */
-#define PWR_EXTSCR_C1STOPF             PWR_EXTSCR_C1STOPF_Msk                  /*!< System stop0 or stop1 flag for CPU1 */
-
-#define PWR_EXTSCR_C1DS_Pos            (14U)
-#define PWR_EXTSCR_C1DS_Msk            (0x1UL << PWR_EXTSCR_C1DS_Pos)          /*!< 0x00004000 */
-#define PWR_EXTSCR_C1DS                PWR_EXTSCR_C1DS_Msk                     /*!< CPU1 deepsleep mode flag */
-
-/********************  Bit definition for PWR_SUBGHZSPICR register  ********************/
-#define PWR_SUBGHZSPICR_NSS_Pos         (15U)
-#define PWR_SUBGHZSPICR_NSS_Msk         (0x1UL << PWR_SUBGHZSPICR_NSS_Pos)       /*!< 0x00008000 */
-#define PWR_SUBGHZSPICR_NSS             PWR_SUBGHZSPICR_NSS_Msk                  /*!< Sub-GHz radio SUBGHZSPI_NSS control */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RCC_CR register  *****************/
-#define RCC_CR_MSION_Pos                     (0U)
-#define RCC_CR_MSION_Msk                     (0x1UL << RCC_CR_MSION_Pos)       /*!< 0x00000001 */
-#define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
-#define RCC_CR_MSIRDY_Pos                    (1U)
-#define RCC_CR_MSIRDY_Msk                    (0x1UL << RCC_CR_MSIRDY_Pos)      /*!< 0x00000002 */
-#define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
-#define RCC_CR_MSIPLLEN_Pos                  (2U)
-#define RCC_CR_MSIPLLEN_Msk                  (0x1UL << RCC_CR_MSIPLLEN_Pos)    /*!< 0x00000004 */
-#define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
-#define RCC_CR_MSIRGSEL_Pos                  (3U)
-#define RCC_CR_MSIRGSEL_Msk                  (0x1UL << RCC_CR_MSIRGSEL_Pos)    /*!< 0x00000008 */
-#define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
-
-/*!< MSIRANGE configuration : 12 frequency ranges available */
-#define RCC_CR_MSIRANGE_Pos                  (4U)
-#define RCC_CR_MSIRANGE_Msk                  (0xFUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000F0 */
-#define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
-#define RCC_CR_MSIRANGE_0                    (0x0UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000000 */
-#define RCC_CR_MSIRANGE_1                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */
-#define RCC_CR_MSIRANGE_2                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */
-#define RCC_CR_MSIRANGE_3                    (0x3UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000030 */
-#define RCC_CR_MSIRANGE_4                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */
-#define RCC_CR_MSIRANGE_5                    (0x5UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000050 */
-#define RCC_CR_MSIRANGE_6                    (0x6UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000060 */
-#define RCC_CR_MSIRANGE_7                    (0x7UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000070 */
-#define RCC_CR_MSIRANGE_8                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */
-#define RCC_CR_MSIRANGE_9                    (0x9UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000090 */
-#define RCC_CR_MSIRANGE_10                   (0xAUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000A0 */
-#define RCC_CR_MSIRANGE_11                   (0xBUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000B0 */
-
-#define RCC_CR_HSION_Pos                     (8U)
-#define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
-#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
-#define RCC_CR_HSIKERON_Pos                  (9U)
-#define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
-#define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                    (10U)
-#define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
-#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
-#define RCC_CR_HSIASFS_Pos                   (11U)
-#define RCC_CR_HSIASFS_Msk                   (0x1UL << RCC_CR_HSIASFS_Pos)     /*!< 0x00000800 */
-#define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
-#define RCC_CR_HSIKERDY_Pos                  (12U)
-#define RCC_CR_HSIKERDY_Msk                  (0x1UL << RCC_CR_HSIKERDY_Pos)     /*!< 0x00001000 */
-#define RCC_CR_HSIKERDY                       RCC_CR_HSIKERDY_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel ready flag*/
-
-#define RCC_CR_HSEON_Pos                     (16U)
-#define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
-#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
-#define RCC_CR_HSERDY_Pos                    (17U)
-#define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
-#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
-#define RCC_CR_CSSON_Pos                     (19U)
-#define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
-#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
-#define RCC_CR_HSEPRE_Pos                    (20U)
-#define RCC_CR_HSEPRE_Msk                    (0x1UL << RCC_CR_HSEPRE_Pos)       /*!< 0x00100000 */
-#define RCC_CR_HSEPRE                        RCC_CR_HSEPRE_Msk                  /*!< HSE sysclk prescaler */
-#define RCC_CR_HSEBYPPWR_Pos                 (21U)
-#define RCC_CR_HSEBYPPWR_Msk                 (0x1UL << RCC_CR_HSEBYPPWR_Pos)    /*!< 0x00200000 */
-#define RCC_CR_HSEBYPPWR                     RCC_CR_HSEBYPPWR_Msk               /*!< Enable HSE32 VDDTCXO */
-
-#define RCC_CR_PLLON_Pos                     (24U)
-#define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
-#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
-#define RCC_CR_PLLRDY_Pos                    (25U)
-#define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
-
-/********************  Bit definition for RCC_ICSCR register  ***************/
-/*!< MSICAL configuration */
-#define RCC_ICSCR_MSICAL_Pos                 (0U)
-#define RCC_ICSCR_MSICAL_Msk                 (0xFFUL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x000000FF */
-#define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
-
-/*!< MSITRIM configuration */
-#define RCC_ICSCR_MSITRIM_Pos                (8U)
-#define RCC_ICSCR_MSITRIM_Msk                (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
-#define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
-
-/*!< HSICAL configuration */
-#define RCC_ICSCR_HSICAL_Pos                 (16U)
-#define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
-#define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
-
-/*!< HSITRIM configuration */
-#define RCC_ICSCR_HSITRIM_Pos                (24U)
-#define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
-#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
-
-/*!< STOPWUCK configuration */
-#define RCC_CFGR_STOPWUCK_Pos                (15U)
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)  /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
-
-/*!< HPREF configuration */
-#define RCC_CFGR_HPREF_Pos                   (16U)
-#define RCC_CFGR_HPREF_Msk                   (0x1UL << RCC_CFGR_HPREF_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_HPREF                       RCC_CFGR_HPREF_Msk                /*!< AHB prescaler flag */
-
-/*!< PPRE1F configuration */
-#define RCC_CFGR_PPRE1F_Pos                  (17U)
-#define RCC_CFGR_PPRE1F_Msk                  (0x1UL << RCC_CFGR_PPRE1F_Pos)    /*!< 0x00020000 */
-#define RCC_CFGR_PPRE1F                      RCC_CFGR_PPRE1F_Msk               /*!< CPU1 APB1 prescaler flag */
-
-/*!< PPRE2F configuration */
-#define RCC_CFGR_PPRE2F_Pos                  (18U)
-#define RCC_CFGR_PPRE2F_Msk                  (0x1UL << RCC_CFGR_PPRE2F_Pos)    /*!< 0x00040000 */
-#define RCC_CFGR_PPRE2F                      RCC_CFGR_PPRE2F_Msk               /*!< APB2 prescaler flag */
-
-/*!< MCOSEL configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x08000000 */
-
-/*!< MCOPRE configuration */
-#define RCC_CFGR_MCOPRE_Pos                  (28U)
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define RCC_PLLCFGR_PLLSRC_Pos               (0U)
-#define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000003 */
-#define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
-#define RCC_PLLCFGR_PLLSRC_0                 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000001 */
-#define RCC_PLLCFGR_PLLSRC_1                 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000002 */
-
-#define RCC_PLLCFGR_PLLM_Pos                 (4U)
-#define RCC_PLLCFGR_PLLM_Msk                 (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
-#define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
-#define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
-#define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
-#define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
-
-#define RCC_PLLCFGR_PLLN_Pos                 (8U)
-#define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00007F00 */
-#define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
-#define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000100 */
-#define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000200 */
-#define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000400 */
-#define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000800 */
-#define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00001000 */
-#define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00002000 */
-#define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00004000 */
-
-#define RCC_PLLCFGR_PLLPEN_Pos               (16U)
-#define RCC_PLLCFGR_PLLPEN_Msk               (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)/*!< 0x00010000 */
-#define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk
-#define RCC_PLLCFGR_PLLP_Pos                 (17U)
-#define RCC_PLLCFGR_PLLP_Msk                 (0x1FUL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x003E0000 */
-#define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk
-#define RCC_PLLCFGR_PLLP_0                   (0x01UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00020000 */
-#define RCC_PLLCFGR_PLLP_1                   (0x02UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00040000 */
-#define RCC_PLLCFGR_PLLP_2                   (0x04UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00080000 */
-#define RCC_PLLCFGR_PLLP_3                   (0x08UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00100000 */
-#define RCC_PLLCFGR_PLLP_4                   (0x10UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00200000 */
-
-#define RCC_PLLCFGR_PLLQEN_Pos               (24U)
-#define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)/*!< 0x01000000 */
-#define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
-#define RCC_PLLCFGR_PLLQ_Pos                 (25U)
-#define RCC_PLLCFGR_PLLQ_Msk                 (0x7UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x0E000000 */
-#define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
-#define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x02000000 */
-#define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x04000000 */
-#define RCC_PLLCFGR_PLLQ_2                   (0x4UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x08000000 */
-
-#define RCC_PLLCFGR_PLLREN_Pos               (28U)
-#define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos)/*!< 0x10000000 */
-#define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
-#define RCC_PLLCFGR_PLLR_Pos                 (29U)
-#define RCC_PLLCFGR_PLLR_Msk                 (0x7UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0xE0000000 */
-#define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
-#define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x20000000 */
-#define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x40000000 */
-#define RCC_PLLCFGR_PLLR_2                   (0x4UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x80000000 */
-
-
-/********************  Bit definition for RCC_CIER register  ******************/
-#define RCC_CIER_LSIRDYIE_Pos                (0U)
-#define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk
-#define RCC_CIER_LSERDYIE_Pos                (1U)
-#define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)   /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
-#define RCC_CIER_MSIRDYIE_Pos                (2U)
-#define RCC_CIER_MSIRDYIE_Msk                (0x1UL << RCC_CIER_MSIRDYIE_Pos)   /*!< 0x00000004 */
-#define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk
-#define RCC_CIER_HSIRDYIE_Pos                (3U)
-#define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)   /*!< 0x00000008 */
-#define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
-#define RCC_CIER_HSERDYIE_Pos                (4U)
-#define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)   /*!< 0x00000010 */
-#define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
-#define RCC_CIER_PLLRDYIE_Pos                (5U)
-#define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)/*!< 0x00000020 */
-#define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
-#define RCC_CIER_LSECSSIE_Pos                (9U)
-#define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)   /*!< 0x00000200 */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
-
-/********************  Bit definition for RCC_CIFR register  ******************/
-#define RCC_CIFR_LSIRDYF_Pos                 (0U)
-#define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)  /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk
-#define RCC_CIFR_LSERDYF_Pos                 (1U)
-#define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
-#define RCC_CIFR_MSIRDYF_Pos                 (2U)
-#define RCC_CIFR_MSIRDYF_Msk                 (0x1UL << RCC_CIFR_MSIRDYF_Pos)   /*!< 0x00000004 */
-#define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk
-#define RCC_CIFR_HSIRDYF_Pos                 (3U)
-#define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */
-#define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
-#define RCC_CIFR_HSERDYF_Pos                 (4U)
-#define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */
-#define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
-#define RCC_CIFR_PLLRDYF_Pos                 (5U)
-#define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)/*!< 0x00000020 */
-#define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
-#define RCC_CIFR_CSSF_Pos                    (8U)
-#define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)   /*!< 0x00000100 */
-#define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
-#define RCC_CIFR_LSECSSF_Pos                 (9U)
-#define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */
-#define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
-
-/********************  Bit definition for RCC_CICR register  ******************/
-#define RCC_CICR_LSIRDYC_Pos                (0U)
-#define RCC_CICR_LSIRDYC_Msk                (0x1UL << RCC_CICR_LSIRDYC_Pos)  /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                    RCC_CICR_LSIRDYC_Msk
-#define RCC_CICR_LSERDYC_Pos                (1U)
-#define RCC_CICR_LSERDYC_Msk                (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                    RCC_CICR_LSERDYC_Msk
-#define RCC_CICR_MSIRDYC_Pos                (2U)
-#define RCC_CICR_MSIRDYC_Msk                (0x1UL << RCC_CICR_MSIRDYC_Pos)   /*!< 0x00000004 */
-#define RCC_CICR_MSIRDYC                    RCC_CICR_MSIRDYC_Msk
-#define RCC_CICR_HSIRDYC_Pos                (3U)
-#define RCC_CICR_HSIRDYC_Msk                (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */
-#define RCC_CICR_HSIRDYC                    RCC_CICR_HSIRDYC_Msk
-#define RCC_CICR_HSERDYC_Pos                (4U)
-#define RCC_CICR_HSERDYC_Msk                (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */
-#define RCC_CICR_HSERDYC                    RCC_CICR_HSERDYC_Msk
-#define RCC_CICR_PLLRDYC_Pos                (5U)
-#define RCC_CICR_PLLRDYC_Msk                (0x1UL << RCC_CICR_PLLRDYC_Pos)/*!< 0x00000020 */
-#define RCC_CICR_PLLRDYC                    RCC_CICR_PLLRDYC_Msk
-#define RCC_CICR_CSSC_Pos                   (8U)
-#define RCC_CICR_CSSC_Msk                   (0x1UL << RCC_CICR_CSSC_Pos)   /*!< 0x00000100 */
-#define RCC_CICR_CSSC                       RCC_CICR_CSSC_Msk
-#define RCC_CICR_LSECSSC_Pos                (9U)
-#define RCC_CICR_LSECSSC_Msk                (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */
-#define RCC_CICR_LSECSSC                    RCC_CICR_LSECSSC_Msk
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
-#define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
-#define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
-#define RCC_AHB1RSTR_DMA2RST_Pos             (1U)
-#define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
-#define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk
-#define RCC_AHB1RSTR_DMAMUX1RST_Pos          (2U)
-#define RCC_AHB1RSTR_DMAMUX1RST_Msk          (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
-#define RCC_AHB1RSTR_DMAMUX1RST              RCC_AHB1RSTR_DMAMUX1RST_Msk
-#define RCC_AHB1RSTR_CRCRST_Pos              (12U)
-#define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
-#define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
-
-/********************  Bit definition for RCC_AHB2RSTR register  ***************/
-#define RCC_AHB2RSTR_GPIOARST_Pos           (0U)
-#define RCC_AHB2RSTR_GPIOARST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
-#define RCC_AHB2RSTR_GPIOARST               RCC_AHB2RSTR_GPIOARST_Msk
-#define RCC_AHB2RSTR_GPIOBRST_Pos           (1U)
-#define RCC_AHB2RSTR_GPIOBRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
-#define RCC_AHB2RSTR_GPIOBRST               RCC_AHB2RSTR_GPIOBRST_Msk
-#define RCC_AHB2RSTR_GPIOCRST_Pos           (2U)
-#define RCC_AHB2RSTR_GPIOCRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
-#define RCC_AHB2RSTR_GPIOCRST               RCC_AHB2RSTR_GPIOCRST_Msk
-#define RCC_AHB2RSTR_GPIOHRST_Pos           (7U)
-#define RCC_AHB2RSTR_GPIOHRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)/*!< 0x00000080 */
-#define RCC_AHB2RSTR_GPIOHRST               RCC_AHB2RSTR_GPIOHRST_Msk
-
-/********************  Bit definition for RCC_AHB3RSTR register  ***************/
-#define RCC_AHB3RSTR_PKARST_Pos             (16U)
-#define RCC_AHB3RSTR_PKARST_Msk             (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00010000 */
-#define RCC_AHB3RSTR_PKARST                 RCC_AHB3RSTR_PKARST_Msk
-#define RCC_AHB3RSTR_AESRST_Pos             (17U)
-#define RCC_AHB3RSTR_AESRST_Msk             (0x1UL << RCC_AHB3RSTR_AESRST_Pos)/*!< 0x00020000 */
-#define RCC_AHB3RSTR_AESRST                 RCC_AHB3RSTR_AESRST_Msk
-#define RCC_AHB3RSTR_RNGRST_Pos             (18U)
-#define RCC_AHB3RSTR_RNGRST_Msk             (0x1UL << RCC_AHB3RSTR_RNGRST_Pos)/*!< 0x00040000 */
-#define RCC_AHB3RSTR_RNGRST                 RCC_AHB3RSTR_RNGRST_Msk
-
-#define RCC_AHB3RSTR_HSEMRST_Pos            (19U)
-#define RCC_AHB3RSTR_HSEMRST_Msk            (0x1UL << RCC_AHB3RSTR_HSEMRST_Pos)/*!< 0x00080000 */
-#define RCC_AHB3RSTR_HSEMRST                RCC_AHB3RSTR_HSEMRST_Msk
-#define RCC_AHB3RSTR_FLASHRST_Pos           (25U)
-#define RCC_AHB3RSTR_FLASHRST_Msk           (0x1UL << RCC_AHB3RSTR_FLASHRST_Pos) /*!< 0x02000000 */
-#define RCC_AHB3RSTR_FLASHRST               RCC_AHB3RSTR_FLASHRST_Msk
-
-/********************  Bit definition for RCC_APB1RSTR1 register  **************/
-#define RCC_APB1RSTR1_TIM2RST_Pos           (0U)
-#define RCC_APB1RSTR1_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
-#define RCC_APB1RSTR1_TIM2RST               RCC_APB1RSTR1_TIM2RST_Msk
-#define RCC_APB1RSTR1_SPI2RST_Pos           (14U)
-#define RCC_APB1RSTR1_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
-#define RCC_APB1RSTR1_SPI2RST               RCC_APB1RSTR1_SPI2RST_Msk
-#define RCC_APB1RSTR1_USART2RST_Pos         (17U)
-#define RCC_APB1RSTR1_USART2RST_Msk         (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
-#define RCC_APB1RSTR1_USART2RST             RCC_APB1RSTR1_USART2RST_Msk
-#define RCC_APB1RSTR1_I2C1RST_Pos           (21U)
-#define RCC_APB1RSTR1_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
-#define RCC_APB1RSTR1_I2C1RST               RCC_APB1RSTR1_I2C1RST_Msk
-#define RCC_APB1RSTR1_I2C2RST_Pos           (22U)
-#define RCC_APB1RSTR1_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
-#define RCC_APB1RSTR1_I2C2RST               RCC_APB1RSTR1_I2C2RST_Msk
-#define RCC_APB1RSTR1_I2C3RST_Pos           (23U)
-#define RCC_APB1RSTR1_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x00800000 */
-#define RCC_APB1RSTR1_I2C3RST               RCC_APB1RSTR1_I2C3RST_Msk
-#define RCC_APB1RSTR1_DACRST_Pos            (29U)
-#define RCC_APB1RSTR1_DACRST_Msk            (0x1UL << RCC_APB1RSTR1_DACRST_Pos)/*!< 0x20000000 */
-#define RCC_APB1RSTR1_DACRST                RCC_APB1RSTR1_DACRST_Msk
-#define RCC_APB1RSTR1_LPTIM1RST_Pos         (31U)
-#define RCC_APB1RSTR1_LPTIM1RST_Msk         (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
-#define RCC_APB1RSTR1_LPTIM1RST             RCC_APB1RSTR1_LPTIM1RST_Msk
-
-/********************  Bit definition for RCC_APB1RSTR2 register  **************/
-#define RCC_APB1RSTR2_LPUART1RST_Pos        (0U)
-#define RCC_APB1RSTR2_LPUART1RST_Msk        (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
-#define RCC_APB1RSTR2_LPUART1RST            RCC_APB1RSTR2_LPUART1RST_Msk
-#define RCC_APB1RSTR2_LPTIM2RST_Pos         (5U)
-#define RCC_APB1RSTR2_LPTIM2RST_Msk         (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)/*!< 0x00000020 */
-#define RCC_APB1RSTR2_LPTIM2RST             RCC_APB1RSTR2_LPTIM2RST_Msk
-#define RCC_APB1RSTR2_LPTIM3RST_Pos         (6U)
-#define RCC_APB1RSTR2_LPTIM3RST_Msk         (0x1UL << RCC_APB1RSTR2_LPTIM3RST_Pos)/*!< 0x00000040 */
-#define RCC_APB1RSTR2_LPTIM3RST             RCC_APB1RSTR2_LPTIM3RST_Msk
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define RCC_APB2RSTR_ADCRST_Pos             (9U)
-#define RCC_APB2RSTR_ADCRST_Msk             (0x1UL << RCC_APB2RSTR_ADCRST_Pos)/*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST                 RCC_APB2RSTR_ADCRST_Msk
-#define RCC_APB2RSTR_TIM1RST_Pos            (11U)
-#define RCC_APB2RSTR_TIM1RST_Msk            (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
-#define RCC_APB2RSTR_TIM1RST                RCC_APB2RSTR_TIM1RST_Msk
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk
-#define RCC_APB2RSTR_TIM16RST_Pos           (17U)
-#define RCC_APB2RSTR_TIM16RST_Msk           (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
-#define RCC_APB2RSTR_TIM16RST               RCC_APB2RSTR_TIM16RST_Msk
-#define RCC_APB2RSTR_TIM17RST_Pos           (18U)
-#define RCC_APB2RSTR_TIM17RST_Msk           (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
-#define RCC_APB2RSTR_TIM17RST               RCC_APB2RSTR_TIM17RST_Msk
-
-/********************  Bit definition for RCC_APB3RSTR register  **************/
-#define RCC_APB3RSTR_SUBGHZSPIRST_Pos            (0U)
-#define RCC_APB3RSTR_SUBGHZSPIRST_Msk            (0x1UL << RCC_APB3RSTR_SUBGHZSPIRST_Pos) /*!< 0x00000001 */
-#define RCC_APB3RSTR_SUBGHZSPIRST                RCC_APB3RSTR_SUBGHZSPIRST_Msk
-
-/********************  Bit definition for RCC_AHB1ENR register  ****************/
-#define RCC_AHB1ENR_DMA1EN_Pos              (0U)
-#define RCC_AHB1ENR_DMA1EN_Msk              (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)  /*!< 0x00000001 */
-#define RCC_AHB1ENR_DMA1EN                  RCC_AHB1ENR_DMA1EN_Msk
-#define RCC_AHB1ENR_DMA2EN_Pos              (1U)
-#define RCC_AHB1ENR_DMA2EN_Msk              (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)  /*!< 0x00000002 */
-#define RCC_AHB1ENR_DMA2EN                  RCC_AHB1ENR_DMA2EN_Msk
-#define RCC_AHB1ENR_DMAMUX1EN_Pos           (2U)
-#define RCC_AHB1ENR_DMAMUX1EN_Msk           (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
-#define RCC_AHB1ENR_DMAMUX1EN               RCC_AHB1ENR_DMAMUX1EN_Msk
-#define RCC_AHB1ENR_CRCEN_Pos               (12U)
-#define RCC_AHB1ENR_CRCEN_Msk               (0x1UL << RCC_AHB1ENR_CRCEN_Pos)   /*!< 0x00001000 */
-#define RCC_AHB1ENR_CRCEN                   RCC_AHB1ENR_CRCEN_Msk
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define RCC_AHB2ENR_GPIOAEN_Pos             (0U)
-#define RCC_AHB2ENR_GPIOAEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
-#define RCC_AHB2ENR_GPIOAEN                 RCC_AHB2ENR_GPIOAEN_Msk
-#define RCC_AHB2ENR_GPIOBEN_Pos             (1U)
-#define RCC_AHB2ENR_GPIOBEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
-#define RCC_AHB2ENR_GPIOBEN                 RCC_AHB2ENR_GPIOBEN_Msk
-#define RCC_AHB2ENR_GPIOCEN_Pos             (2U)
-#define RCC_AHB2ENR_GPIOCEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
-#define RCC_AHB2ENR_GPIOCEN                 RCC_AHB2ENR_GPIOCEN_Msk
-#define RCC_AHB2ENR_GPIOHEN_Pos             (7U)
-#define RCC_AHB2ENR_GPIOHEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
-#define RCC_AHB2ENR_GPIOHEN                 RCC_AHB2ENR_GPIOHEN_Msk
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define RCC_AHB3ENR_PKAEN_Pos               (16U)
-#define RCC_AHB3ENR_PKAEN_Msk               (0x1UL << RCC_AHB3ENR_PKAEN_Pos)   /*!< 0x00010000 */
-#define RCC_AHB3ENR_PKAEN                   RCC_AHB3ENR_PKAEN_Msk
-#define RCC_AHB3ENR_AESEN_Pos               (17U)
-#define RCC_AHB3ENR_AESEN_Msk               (0x1UL << RCC_AHB3ENR_AESEN_Pos)/*!< 0x00020000 */
-#define RCC_AHB3ENR_AESEN                   RCC_AHB3ENR_AESEN_Msk
-#define RCC_AHB3ENR_RNGEN_Pos               (18U)
-#define RCC_AHB3ENR_RNGEN_Msk               (0x1UL << RCC_AHB3ENR_RNGEN_Pos)  /*!< 0x00040000 */
-#define RCC_AHB3ENR_RNGEN                   RCC_AHB3ENR_RNGEN_Msk
-#define RCC_AHB3ENR_HSEMEN_Pos              (19U)
-#define RCC_AHB3ENR_HSEMEN_Msk              (0x1UL << RCC_AHB3ENR_HSEMEN_Pos)  /*!< 0x00080000 */
-#define RCC_AHB3ENR_HSEMEN                  RCC_AHB3ENR_HSEMEN_Msk
-#define RCC_AHB3ENR_FLASHEN_Pos             (25U)
-#define RCC_AHB3ENR_FLASHEN_Msk             (0x1UL << RCC_AHB3ENR_FLASHEN_Pos)   /*!< 0x02000000 */
-#define RCC_AHB3ENR_FLASHEN                 RCC_AHB3ENR_FLASHEN_Msk
-
-/********************  Bit definition for RCC_APB1ENR1 register  **************/
-#define RCC_APB1ENR1_TIM2EN_Pos             (0U)
-#define RCC_APB1ENR1_TIM2EN_Msk             (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
-#define RCC_APB1ENR1_TIM2EN                 RCC_APB1ENR1_TIM2EN_Msk
-#define RCC_APB1ENR1_RTCAPBEN_Pos           (10U)
-#define RCC_APB1ENR1_RTCAPBEN_Msk           (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
-#define RCC_APB1ENR1_RTCAPBEN               RCC_APB1ENR1_RTCAPBEN_Msk
-#define RCC_APB1ENR1_WWDGEN_Pos             (11U)
-#define RCC_APB1ENR1_WWDGEN_Msk             (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1ENR1_WWDGEN                 RCC_APB1ENR1_WWDGEN_Msk
-#define RCC_APB1ENR1_SPI2EN_Pos             (14U)
-#define RCC_APB1ENR1_SPI2EN_Msk             (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
-#define RCC_APB1ENR1_SPI2EN                 RCC_APB1ENR1_SPI2EN_Msk
-#define RCC_APB1ENR1_USART2EN_Pos           (17U)
-#define RCC_APB1ENR1_USART2EN_Msk           (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR1_USART2EN               RCC_APB1ENR1_USART2EN_Msk
-#define RCC_APB1ENR1_I2C1EN_Pos             (21U)
-#define RCC_APB1ENR1_I2C1EN_Msk             (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
-#define RCC_APB1ENR1_I2C1EN                 RCC_APB1ENR1_I2C1EN_Msk
-#define RCC_APB1ENR1_I2C2EN_Pos             (22U)
-#define RCC_APB1ENR1_I2C2EN_Msk             (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
-#define RCC_APB1ENR1_I2C2EN                 RCC_APB1ENR1_I2C2EN_Msk
-#define RCC_APB1ENR1_I2C3EN_Pos             (23U)
-#define RCC_APB1ENR1_I2C3EN_Msk             (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
-#define RCC_APB1ENR1_I2C3EN                 RCC_APB1ENR1_I2C3EN_Msk
-#define RCC_APB1ENR1_DACEN_Pos              (29U)
-#define RCC_APB1ENR1_DACEN_Msk              (0x1UL << RCC_APB1ENR1_DACEN_Pos)/*!< 0x20000000 */
-#define RCC_APB1ENR1_DACEN                  RCC_APB1ENR1_DACEN_Msk
-#define RCC_APB1ENR1_LPTIM1EN_Pos           (31U)
-#define RCC_APB1ENR1_LPTIM1EN_Msk           (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
-#define RCC_APB1ENR1_LPTIM1EN               RCC_APB1ENR1_LPTIM1EN_Msk
-
-/********************  Bit definition for RCC_APB1ENR2 register  **************/
-#define RCC_APB1ENR2_LPUART1EN_Pos          (0U)
-#define RCC_APB1ENR2_LPUART1EN_Msk         (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
-#define RCC_APB1ENR2_LPUART1EN              RCC_APB1ENR2_LPUART1EN_Msk
-#define RCC_APB1ENR2_LPTIM2EN_Pos           (5U)
-#define RCC_APB1ENR2_LPTIM2EN_Msk           (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)/*!< 0x00000020 */
-#define RCC_APB1ENR2_LPTIM2EN               RCC_APB1ENR2_LPTIM2EN_Msk
-#define RCC_APB1ENR2_LPTIM3EN_Pos           (6U)
-#define RCC_APB1ENR2_LPTIM3EN_Msk           (0x1UL << RCC_APB1ENR2_LPTIM3EN_Pos)/*!< 0x00000040 */
-#define RCC_APB1ENR2_LPTIM3EN               RCC_APB1ENR2_LPTIM3EN_Msk
-
-/********************  Bit definition for RCC_APB2ENR register  **************/
-#define RCC_APB2ENR_ADCEN_Pos               (9U)
-#define RCC_APB2ENR_ADCEN_Msk               (0x1UL << RCC_APB2ENR_ADCEN_Pos)  /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                   RCC_APB2ENR_ADCEN_Msk
-#define RCC_APB2ENR_TIM1EN_Pos              (11U)
-#define RCC_APB2ENR_TIM1EN_Msk              (0x1UL << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
-#define RCC_APB2ENR_TIM1EN                  RCC_APB2ENR_TIM1EN_Msk
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk
-#define RCC_APB2ENR_USART1EN_Pos            (14U)
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk
-#define RCC_APB2ENR_TIM16EN_Pos             (17U)
-#define RCC_APB2ENR_TIM16EN_Msk             (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
-#define RCC_APB2ENR_TIM16EN                 RCC_APB2ENR_TIM16EN_Msk
-#define RCC_APB2ENR_TIM17EN_Pos             (18U)
-#define RCC_APB2ENR_TIM17EN_Msk             (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
-#define RCC_APB2ENR_TIM17EN                 RCC_APB2ENR_TIM17EN_Msk
-
-/********************  Bit definition for RCC_APB3ENR register  **************/
-#define RCC_APB3ENR_SUBGHZSPIEN_Pos         (0U)
-#define RCC_APB3ENR_SUBGHZSPIEN_Msk         (0x1UL << RCC_APB3ENR_SUBGHZSPIEN_Pos)/*!< 0x00000001 */
-#define RCC_APB3ENR_SUBGHZSPIEN             RCC_APB3ENR_SUBGHZSPIEN_Msk
-
-/********************  Bit definition for RCC_AHB1SMENR register  ****************/
-#define RCC_AHB1SMENR_DMA1SMEN_Pos          (0U)
-#define RCC_AHB1SMENR_DMA1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
-#define RCC_AHB1SMENR_DMA1SMEN              RCC_AHB1SMENR_DMA1SMEN_Msk
-#define RCC_AHB1SMENR_DMA2SMEN_Pos          (1U)
-#define RCC_AHB1SMENR_DMA2SMEN_Msk          (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
-#define RCC_AHB1SMENR_DMA2SMEN              RCC_AHB1SMENR_DMA2SMEN_Msk
-#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos       (2U)
-#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk       (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
-#define RCC_AHB1SMENR_DMAMUX1SMEN           RCC_AHB1SMENR_DMAMUX1SMEN_Msk
-#define RCC_AHB1SMENR_CRCSMEN_Pos           (12U)
-#define RCC_AHB1SMENR_CRCSMEN_Msk           (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
-#define RCC_AHB1SMENR_CRCSMEN               RCC_AHB1SMENR_CRCSMEN_Msk
-
-/********************  Bit definition for RCC_AHB2SMENR register  ***************/
-#define RCC_AHB2SMENR_GPIOASMEN_Pos         (0U)
-#define RCC_AHB2SMENR_GPIOASMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
-#define RCC_AHB2SMENR_GPIOASMEN             RCC_AHB2SMENR_GPIOASMEN_Msk
-#define RCC_AHB2SMENR_GPIOBSMEN_Pos         (1U)
-#define RCC_AHB2SMENR_GPIOBSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
-#define RCC_AHB2SMENR_GPIOBSMEN             RCC_AHB2SMENR_GPIOBSMEN_Msk
-#define RCC_AHB2SMENR_GPIOCSMEN_Pos         (2U)
-#define RCC_AHB2SMENR_GPIOCSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
-#define RCC_AHB2SMENR_GPIOCSMEN             RCC_AHB2SMENR_GPIOCSMEN_Msk
-#define RCC_AHB2SMENR_GPIOHSMEN_Pos         (7U)
-#define RCC_AHB2SMENR_GPIOHSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos)/*!< 0x00000080 */
-#define RCC_AHB2SMENR_GPIOHSMEN             RCC_AHB2SMENR_GPIOHSMEN_Msk
-
-/********************  Bit definition for RCC_AHB3SMENR register  ***************/
-#define RCC_AHB3SMENR_PKASMEN_Pos           (16U)
-#define RCC_AHB3SMENR_PKASMEN_Msk           (0x1UL << RCC_AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */
-#define RCC_AHB3SMENR_PKASMEN               RCC_AHB3SMENR_PKASMEN_Msk
-#define RCC_AHB3SMENR_AESSMEN_Pos           (17U)
-#define RCC_AHB3SMENR_AESSMEN_Msk           (0x1UL << RCC_AHB3SMENR_AESSMEN_Pos) /*!< 0x00020000 */
-#define RCC_AHB3SMENR_AESSMEN               RCC_AHB3SMENR_AESSMEN_Msk
-#define RCC_AHB3SMENR_RNGSMEN_Pos           (18U)
-#define RCC_AHB3SMENR_RNGSMEN_Msk           (0x1UL << RCC_AHB3SMENR_RNGSMEN_Pos)/*!< 0x00040000 */
-#define RCC_AHB3SMENR_RNGSMEN               RCC_AHB3SMENR_RNGSMEN_Msk
-#define RCC_AHB3SMENR_SRAM1SMEN_Pos         (23U)
-#define RCC_AHB3SMENR_SRAM1SMEN_Msk         (0x1UL << RCC_AHB3SMENR_SRAM1SMEN_Pos)/*!< 0x00800000 */
-#define RCC_AHB3SMENR_SRAM1SMEN             RCC_AHB3SMENR_SRAM1SMEN_Msk
-#define RCC_AHB3SMENR_SRAM2SMEN_Pos         (24U)
-#define RCC_AHB3SMENR_SRAM2SMEN_Msk         (0x1UL << RCC_AHB3SMENR_SRAM2SMEN_Pos)/*!< 0x01000000 */
-#define RCC_AHB3SMENR_SRAM2SMEN             RCC_AHB3SMENR_SRAM2SMEN_Msk
-#define RCC_AHB3SMENR_FLASHSMEN_Pos         (25U)
-#define RCC_AHB3SMENR_FLASHSMEN_Msk         (0x1UL << RCC_AHB3SMENR_FLASHSMEN_Pos)/*!< 0x02000000 */
-#define RCC_AHB3SMENR_FLASHSMEN             RCC_AHB3SMENR_FLASHSMEN_Msk
-
-/********************  Bit definition for RCC_APB1SMENR1 register  **************/
-#define RCC_APB1SMENR1_TIM2SMEN_Pos         (0U)
-#define RCC_APB1SMENR1_TIM2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
-#define RCC_APB1SMENR1_TIM2SMEN             RCC_APB1SMENR1_TIM2SMEN_Msk
-#define RCC_APB1SMENR1_RTCAPBSMEN_Pos       (10U)
-#define RCC_APB1SMENR1_RTCAPBSMEN_Msk       (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
-#define RCC_APB1SMENR1_RTCAPBSMEN           RCC_APB1SMENR1_RTCAPBSMEN_Msk
-#define RCC_APB1SMENR1_WWDGSMEN_Pos         (11U)
-#define RCC_APB1SMENR1_WWDGSMEN_Msk         (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
-#define RCC_APB1SMENR1_WWDGSMEN             RCC_APB1SMENR1_WWDGSMEN_Msk
-#define RCC_APB1SMENR1_SPI2SMEN_Pos         (14U)
-#define RCC_APB1SMENR1_SPI2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
-#define RCC_APB1SMENR1_SPI2SMEN             RCC_APB1SMENR1_SPI2SMEN_Msk
-#define RCC_APB1SMENR1_USART2SMEN_Pos       (17U)
-#define RCC_APB1SMENR1_USART2SMEN_Msk       (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
-#define RCC_APB1SMENR1_USART2SMEN           RCC_APB1SMENR1_USART2SMEN_Msk
-#define RCC_APB1SMENR1_I2C1SMEN_Pos         (21U)
-#define RCC_APB1SMENR1_I2C1SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
-#define RCC_APB1SMENR1_I2C1SMEN             RCC_APB1SMENR1_I2C1SMEN_Msk
-#define RCC_APB1SMENR1_I2C2SMEN_Pos         (22U)
-#define RCC_APB1SMENR1_I2C2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
-#define RCC_APB1SMENR1_I2C2SMEN             RCC_APB1SMENR1_I2C2SMEN_Msk
-#define RCC_APB1SMENR1_I2C3SMEN_Pos         (23U)
-#define RCC_APB1SMENR1_I2C3SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x00800000 */
-#define RCC_APB1SMENR1_I2C3SMEN             RCC_APB1SMENR1_I2C3SMEN_Msk
-#define RCC_APB1SMENR1_DACSMEN_Pos          (29U)
-#define RCC_APB1SMENR1_DACSMEN_Msk          (0x1UL << RCC_APB1SMENR1_DACSMEN_Pos)/*!< 0x20000000 */
-#define RCC_APB1SMENR1_DACSMEN              RCC_APB1SMENR1_DACSMEN_Msk
-#define RCC_APB1SMENR1_LPTIM1SMEN_Pos       (31U)
-#define RCC_APB1SMENR1_LPTIM1SMEN_Msk       (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
-#define RCC_APB1SMENR1_LPTIM1SMEN           RCC_APB1SMENR1_LPTIM1SMEN_Msk
-
-/********************  Bit definition for RCC_APB1SMENR2 register  **************/
-#define RCC_APB1SMENR2_LPUART1SMEN_Pos      (0U)
-#define RCC_APB1SMENR2_LPUART1SMEN_Msk      (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
-#define RCC_APB1SMENR2_LPUART1SMEN          RCC_APB1SMENR2_LPUART1SMEN_Msk
-#define RCC_APB1SMENR2_LPTIM2SMEN_Pos       (5U)
-#define RCC_APB1SMENR2_LPTIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos)/*!< 0x00000020 */
-#define RCC_APB1SMENR2_LPTIM2SMEN           RCC_APB1SMENR2_LPTIM2SMEN_Msk
-#define RCC_APB1SMENR2_LPTIM3SMEN_Pos       (6U)
-#define RCC_APB1SMENR2_LPTIM3SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPTIM3SMEN_Pos)/*!< 0x00000040 */
-#define RCC_APB1SMENR2_LPTIM3SMEN           RCC_APB1SMENR2_LPTIM3SMEN_Msk
-
-/********************  Bit definition for RCC_APB2SMENR register  **************/
-#define RCC_APB2SMENR_ADCSMEN_Pos           (9U)
-#define RCC_APB2SMENR_ADCSMEN_Msk           (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)/*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN               RCC_APB2SMENR_ADCSMEN_Msk
-#define RCC_APB2SMENR_TIM1SMEN_Pos          (11U)
-#define RCC_APB2SMENR_TIM1SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
-#define RCC_APB2SMENR_TIM1SMEN              RCC_APB2SMENR_TIM1SMEN_Msk
-#define RCC_APB2SMENR_SPI1SMEN_Pos          (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk          (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN              RCC_APB2SMENR_SPI1SMEN_Msk
-#define RCC_APB2SMENR_USART1SMEN_Pos        (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk        (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN            RCC_APB2SMENR_USART1SMEN_Msk
-#define RCC_APB2SMENR_TIM16SMEN_Pos         (17U)
-#define RCC_APB2SMENR_TIM16SMEN_Msk         (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
-#define RCC_APB2SMENR_TIM16SMEN             RCC_APB2SMENR_TIM16SMEN_Msk
-#define RCC_APB2SMENR_TIM17SMEN_Pos         (18U)
-#define RCC_APB2SMENR_TIM17SMEN_Msk         (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
-#define RCC_APB2SMENR_TIM17SMEN             RCC_APB2SMENR_TIM17SMEN_Msk
-
-/********************  Bit definition for RCC_APB3SMENR register  **************/
-#define RCC_APB3SMENR_SUBGHZSPISMEN_Pos     (0U)
-#define RCC_APB3SMENR_SUBGHZSPISMEN_Msk     (0x1UL << RCC_APB3SMENR_SUBGHZSPISMEN_Pos)/*!< 0x00000001 */
-#define RCC_APB3SMENR_SUBGHZSPISMEN         RCC_APB3SMENR_SUBGHZSPISMEN_Msk
-
-/********************  Bit definition for RCC_CCIPR register  ******************/
-#define RCC_CCIPR_USART1SEL_Pos             (0U)
-#define RCC_CCIPR_USART1SEL_Msk             (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL                 RCC_CCIPR_USART1SEL_Msk
-#define RCC_CCIPR_USART1SEL_0               (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1               (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
-
-#define RCC_CCIPR_USART2SEL_Pos             (2U)
-#define RCC_CCIPR_USART2SEL_Msk             (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL                 RCC_CCIPR_USART2SEL_Msk
-#define RCC_CCIPR_USART2SEL_0               (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1               (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
-
-#define RCC_CCIPR_I2S2SEL_Pos               (8U)
-#define RCC_CCIPR_I2S2SEL_Msk               (0x3UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000300 */
-#define RCC_CCIPR_I2S2SEL                   RCC_CCIPR_I2S2SEL_Msk
-#define RCC_CCIPR_I2S2SEL_0                 (0x1UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000100 */
-#define RCC_CCIPR_I2S2SEL_1                 (0x2UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000200 */
-
-#define RCC_CCIPR_LPUART1SEL_Pos            (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk            (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL                RCC_CCIPR_LPUART1SEL_Msk
-#define RCC_CCIPR_LPUART1SEL_0              (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
-#define RCC_CCIPR_LPUART1SEL_1              (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
-
-#define RCC_CCIPR_I2C1SEL_Pos               (12U)
-#define RCC_CCIPR_I2C1SEL_Msk               (0x3UL << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                   RCC_CCIPR_I2C1SEL_Msk
-#define RCC_CCIPR_I2C1SEL_0                 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1                 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00002000 */
-
-#define RCC_CCIPR_I2C2SEL_Pos               (14U)
-#define RCC_CCIPR_I2C2SEL_Msk               (0x3UL << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x0000C000 */
-#define RCC_CCIPR_I2C2SEL                   RCC_CCIPR_I2C2SEL_Msk
-#define RCC_CCIPR_I2C2SEL_0                 (0x1UL << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00004000 */
-#define RCC_CCIPR_I2C2SEL_1                 (0x2UL << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00008000 */
-
-#define RCC_CCIPR_I2C3SEL_Pos               (16U)
-#define RCC_CCIPR_I2C3SEL_Msk               (0x3UL << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00030000 */
-#define RCC_CCIPR_I2C3SEL                   RCC_CCIPR_I2C3SEL_Msk
-#define RCC_CCIPR_I2C3SEL_0                 (0x1UL << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00010000 */
-#define RCC_CCIPR_I2C3SEL_1                 (0x2UL << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00020000 */
-
-#define RCC_CCIPR_LPTIM1SEL_Pos             (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk             (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL                 RCC_CCIPR_LPTIM1SEL_Msk
-#define RCC_CCIPR_LPTIM1SEL_0               (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1               (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
-
-#define RCC_CCIPR_LPTIM2SEL_Pos             (20U)
-#define RCC_CCIPR_LPTIM2SEL_Msk             (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
-#define RCC_CCIPR_LPTIM2SEL                 RCC_CCIPR_LPTIM2SEL_Msk
-#define RCC_CCIPR_LPTIM2SEL_0               (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
-#define RCC_CCIPR_LPTIM2SEL_1               (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
-
-#define RCC_CCIPR_LPTIM3SEL_Pos             (22U)
-#define RCC_CCIPR_LPTIM3SEL_Msk             (0x3UL << RCC_CCIPR_LPTIM3SEL_Pos)   /*!< 0x00C00000 */
-#define RCC_CCIPR_LPTIM3SEL                 RCC_CCIPR_LPTIM3SEL_Msk
-#define RCC_CCIPR_LPTIM3SEL_0               (0x1UL << RCC_CCIPR_LPTIM3SEL_Pos)   /*!< 0x00400000 */
-#define RCC_CCIPR_LPTIM3SEL_1               (0x2UL << RCC_CCIPR_LPTIM3SEL_Pos)   /*!< 0x00800000 */
-
-#define RCC_CCIPR_ADCSEL_Pos                (28U)
-#define RCC_CCIPR_ADCSEL_Msk                (0x3UL << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x30000000 */
-#define RCC_CCIPR_ADCSEL                    RCC_CCIPR_ADCSEL_Msk
-#define RCC_CCIPR_ADCSEL_0                  (0x1UL << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x10000000 */
-#define RCC_CCIPR_ADCSEL_1                  (0x2UL << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x20000000 */
-
-#define RCC_CCIPR_RNGSEL_Pos                (30U)
-#define RCC_CCIPR_RNGSEL_Msk                (0x3UL << RCC_CCIPR_RNGSEL_Pos)    /*!< 0xC0000000 */
-#define RCC_CCIPR_RNGSEL                    RCC_CCIPR_RNGSEL_Msk
-#define RCC_CCIPR_RNGSEL_0                  (0x1UL << RCC_CCIPR_RNGSEL_Pos)    /*!< 0x40000000 */
-#define RCC_CCIPR_RNGSEL_1                  (0x2UL << RCC_CCIPR_RNGSEL_Pos)    /*!< 0x80000000 */
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define RCC_BDCR_LSEON_Pos                  (0U)
-#define RCC_BDCR_LSEON_Msk                  (0x1UL << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
-#define RCC_BDCR_LSEON                      RCC_BDCR_LSEON_Msk
-#define RCC_BDCR_LSERDY_Pos                 (1U)
-#define RCC_BDCR_LSERDY_Msk                 (0x1UL << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
-#define RCC_BDCR_LSERDY                     RCC_BDCR_LSERDY_Msk
-#define RCC_BDCR_LSEBYP_Pos                 (2U)
-#define RCC_BDCR_LSEBYP_Msk                 (0x1UL << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
-#define RCC_BDCR_LSEBYP                     RCC_BDCR_LSEBYP_Msk
-
-#define RCC_BDCR_LSEDRV_Pos                 (3U)
-#define RCC_BDCR_LSEDRV_Msk                 (0x3UL << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000018 */
-#define RCC_BDCR_LSEDRV                     RCC_BDCR_LSEDRV_Msk
-#define RCC_BDCR_LSEDRV_0                   (0x1UL << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000008 */
-#define RCC_BDCR_LSEDRV_1                   (0x2UL << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000010 */
-
-#define RCC_BDCR_LSECSSON_Pos               (5U)
-#define RCC_BDCR_LSECSSON_Msk               (0x1UL << RCC_BDCR_LSECSSON_Pos)   /*!< 0x00000020 */
-#define RCC_BDCR_LSECSSON                   RCC_BDCR_LSECSSON_Msk
-#define RCC_BDCR_LSECSSD_Pos                (6U)
-#define RCC_BDCR_LSECSSD_Msk                (0x1UL << RCC_BDCR_LSECSSD_Pos)    /*!< 0x00000040 */
-#define RCC_BDCR_LSECSSD                    RCC_BDCR_LSECSSD_Msk
-#define RCC_BDCR_LSESYSEN_Pos               (7U)
-#define RCC_BDCR_LSESYSEN_Msk               (0x1UL << RCC_BDCR_LSESYSEN_Pos)   /*!< 0x00000080 */
-#define RCC_BDCR_LSESYSEN                   RCC_BDCR_LSESYSEN_Msk
-
-#define RCC_BDCR_RTCSEL_Pos                 (8U)
-#define RCC_BDCR_RTCSEL_Msk                 (0x3UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
-#define RCC_BDCR_RTCSEL                     RCC_BDCR_RTCSEL_Msk
-#define RCC_BDCR_RTCSEL_0                   (0x1UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
-#define RCC_BDCR_RTCSEL_1                   (0x2UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
-
-#define RCC_BDCR_LSESYSRDY_Pos              (11U)
-#define RCC_BDCR_LSESYSRDY_Msk              (0x1UL << RCC_BDCR_LSESYSRDY_Pos) /*!< 0x00000800 */
-#define RCC_BDCR_LSESYSRDY                  RCC_BDCR_LSESYSRDY_Msk
-
-#define RCC_BDCR_RTCEN_Pos                  (15U)
-#define RCC_BDCR_RTCEN_Msk                  (0x1UL << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
-#define RCC_BDCR_RTCEN                      RCC_BDCR_RTCEN_Msk
-
-#define RCC_BDCR_BDRST_Pos                  (16U)
-#define RCC_BDCR_BDRST_Msk                  (0x1UL << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
-#define RCC_BDCR_BDRST                      RCC_BDCR_BDRST_Msk
-
-#define RCC_BDCR_LSCOEN_Pos                 (24U)
-#define RCC_BDCR_LSCOEN_Msk                 (0x1UL << RCC_BDCR_LSCOEN_Pos)     /*!< 0x01000000 */
-#define RCC_BDCR_LSCOEN                     RCC_BDCR_LSCOEN_Msk
-#define RCC_BDCR_LSCOSEL_Pos                (25U)
-#define RCC_BDCR_LSCOSEL_Msk                (0x1UL << RCC_BDCR_LSCOSEL_Pos)    /*!< 0x02000000 */
-#define RCC_BDCR_LSCOSEL                    RCC_BDCR_LSCOSEL_Msk
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                  (0U)
-#define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */
-#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk
-#define RCC_CSR_LSIRDY_Pos                 (1U)
-#define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk
-#define RCC_CSR_LSIPRE_Pos                 (4U)
-#define RCC_CSR_LSIPRE_Msk                 (0x1UL << RCC_CSR_LSIPRE_Pos)     /*!< 0x00000010 */
-#define RCC_CSR_LSIPRE                     RCC_CSR_LSIPRE_Msk
-
-#define RCC_CSR_MSISRANGE_Pos              (8U)
-#define RCC_CSR_MSISRANGE_Msk              (0xFUL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000F00 */
-#define RCC_CSR_MSISRANGE                  RCC_CSR_MSISRANGE_Msk
-#define RCC_CSR_MSISRANGE_1                (0x4UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000400 */
-#define RCC_CSR_MSISRANGE_2                (0x5UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000500 */
-#define RCC_CSR_MSISRANGE_4                (0x6UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000600 */
-#define RCC_CSR_MSISRANGE_8                (0x7UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000700 */
-
-#define RCC_CSR_RFRSTF_Pos                  (14U)
-#define RCC_CSR_RFRSTF_Msk                  (0x1UL << RCC_CSR_RFRSTF_Pos)      /*!< 0x0004000 */
-#define RCC_CSR_RFRSTF                      RCC_CSR_RFRSTF_Msk
-#define RCC_CSR_RFRST_Pos                   (15U)
-#define RCC_CSR_RFRST_Msk                   (0x1UL << RCC_CSR_RFRST_Pos)       /*!< 0x0008000 */
-#define RCC_CSR_RFRST                       RCC_CSR_RFRST_Msk
-
-#define RCC_CSR_RMVF_Pos                    (23U)
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)        /*!< 0x00800000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk
-#define RCC_CSR_RFILARSTF_Pos               (24U)
-#define RCC_CSR_RFILARSTF_Msk               (0x1UL << RCC_CSR_RFILARSTF_Pos)   /*!< 0x01000000 */
-#define RCC_CSR_RFILARSTF                   RCC_CSR_RFILARSTF_Msk
-#define RCC_CSR_OBLRSTF_Pos                 (25U)
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)     /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk
-#define RCC_CSR_PINRSTF_Pos                 (26U)
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk
-#define RCC_CSR_BORRSTF_Pos                 (27U)
-#define RCC_CSR_BORRSTF_Msk                 (0x1UL << RCC_CSR_BORRSTF_Pos)     /*!< 0x08000000 */
-#define RCC_CSR_BORRSTF                     RCC_CSR_BORRSTF_Msk
-#define RCC_CSR_SFTRSTF_Pos                 (28U)
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk
-#define RCC_CSR_IWDGRSTF_Pos                (29U)
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk
-#define RCC_CSR_WWDGRSTF_Pos                (30U)
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk
-#define RCC_CSR_LPWRRSTF_Pos                (31U)
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk
-
-/********************  Bit definition for RCC_EXTCFGR register  *******************/
-#define RCC_EXTCFGR_SHDHPRE_Pos             (0U)
-#define RCC_EXTCFGR_SHDHPRE_Msk             (0xFUL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x0000000F */
-#define RCC_EXTCFGR_SHDHPRE                 RCC_EXTCFGR_SHDHPRE_Msk
-#define RCC_EXTCFGR_SHDHPRE_0               (0x1UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000001 */
-#define RCC_EXTCFGR_SHDHPRE_1               (0x2UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000002 */
-#define RCC_EXTCFGR_SHDHPRE_2               (0x4UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000004 */
-#define RCC_EXTCFGR_SHDHPRE_3               (0x8UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000008 */
-
-#define RCC_EXTCFGR_SHDHPREF_Pos            (16U)
-#define RCC_EXTCFGR_SHDHPREF_Msk            (0x1UL << RCC_EXTCFGR_SHDHPREF_Pos)/*!< 0x00010000 */
-#define RCC_EXTCFGR_SHDHPREF                RCC_EXTCFGR_SHDHPREF_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions
- */
-#define RNG_VER_3_2
-
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos         (2U)
-#define RNG_CR_RNGEN_Msk         (0x1UL << RNG_CR_RNGEN_Pos)                   /*!< 0x00000004 */
-#define RNG_CR_RNGEN             RNG_CR_RNGEN_Msk
-#define RNG_CR_IE_Pos            (3U)
-#define RNG_CR_IE_Msk            (0x1UL << RNG_CR_IE_Pos)                      /*!< 0x00000008 */
-#define RNG_CR_IE                RNG_CR_IE_Msk
-#define RNG_CR_CED_Pos           (5U)
-#define RNG_CR_CED_Msk           (0x1UL << RNG_CR_CED_Pos)                     /*!< 0x00000020 */
-#define RNG_CR_CED               RNG_CR_CED_Msk
-#define RNG_CR_RNG_CONFIG3_Pos   (8U)
-#define RNG_CR_RNG_CONFIG3_Msk   (0xFUL << RNG_CR_RNG_CONFIG3_Pos)              /*!< 0x00000F00 */
-#define RNG_CR_RNG_CONFIG3       RNG_CR_RNG_CONFIG3_Msk
-#define RNG_CR_NISTC_Pos         (12U)
-#define RNG_CR_NISTC_Msk         (0x1UL << RNG_CR_NISTC_Pos)                   /*!< 0x00001000 */
-#define RNG_CR_NISTC             RNG_CR_NISTC_Msk
-#define RNG_CR_RNG_CONFIG2_Pos   (13U)
-#define RNG_CR_RNG_CONFIG2_Msk   (0x7UL << RNG_CR_RNG_CONFIG2_Pos)              /*!< 0x0000E000 */
-#define RNG_CR_RNG_CONFIG2       RNG_CR_RNG_CONFIG2_Msk
-#define RNG_CR_CLKDIV_Pos        (16U)
-#define RNG_CR_CLKDIV_Msk        (0xFUL << RNG_CR_CLKDIV_Pos)                  /*!< 0x000F0000 */
-#define RNG_CR_CLKDIV            RNG_CR_CLKDIV_Msk
-#define RNG_CR_CLKDIV_0          (0x1UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00010000 */
-#define RNG_CR_CLKDIV_1          (0x2UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00020000 */
-#define RNG_CR_CLKDIV_2          (0x4UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00040000 */
-#define RNG_CR_CLKDIV_3          (0x8UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00080000 */
-#define RNG_CR_RNG_CONFIG1_Pos   (20U)
-#define RNG_CR_RNG_CONFIG1_Msk   (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)             /*!< 0x03F00000 */
-#define RNG_CR_RNG_CONFIG1       RNG_CR_RNG_CONFIG1_Msk
-#define RNG_CR_CONDRST_Pos       (30U)
-#define RNG_CR_CONDRST_Msk       (0x1UL << RNG_CR_CONDRST_Pos)                 /*!< 0x40000000 */
-#define RNG_CR_CONDRST           RNG_CR_CONDRST_Msk
-#define RNG_CR_CONFIGLOCK_Pos    (31U)
-#define RNG_CR_CONFIGLOCK_Msk    (0x1UL << RNG_CR_CONFIGLOCK_Pos)              /*!< 0x80000000 */
-#define RNG_CR_CONFIGLOCK        RNG_CR_CONFIGLOCK_Msk
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)
-#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk
-#define RNG_SR_CECS_Pos     (1U)
-#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk
-#define RNG_SR_SECS_Pos     (2U)
-#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk
-#define RNG_SR_CEIS_Pos     (5U)
-#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk
-#define RNG_SR_SEIS_Pos     (6U)
-#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk
-
-/********************  Bits definition for RNG_DR register  *******************/
-#define RNG_DR_RNDATA_Pos        (0U)
-#define RNG_DR_RNDATA_Msk        (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos)       /*!< 0xFFFFFFFF */
-#define RNG_DR_RNDATA            RNG_DR_RNDATA_Msk
-
-/********************  Bits definition for RNG_HTCR register  *****************/
-#define RNG_HTCR_HTCFG_Pos       (0U)
-#define RNG_HTCR_HTCFG_Msk       (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)      /*!< 0xFFFFFFFF */
-#define RNG_HTCR_HTCFG           RNG_HTCR_HTCFG_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                (22U)
-#define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
-#define RTC_TR_PM                    RTC_TR_PM_Msk
-#define RTC_TR_HT_Pos                (20U)
-#define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
-#define RTC_TR_HT                    RTC_TR_HT_Msk
-#define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
-#define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                (16U)
-#define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
-#define RTC_TR_HU                    RTC_TR_HU_Msk
-#define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
-#define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
-#define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
-#define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos               (12U)
-#define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
-#define RTC_TR_MNT                   RTC_TR_MNT_Msk
-#define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
-#define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
-#define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos               (8U)
-#define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
-#define RTC_TR_MNU                   RTC_TR_MNU_Msk
-#define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
-#define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
-#define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
-#define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                (4U)
-#define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
-#define RTC_TR_ST                    RTC_TR_ST_Msk
-#define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
-#define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
-#define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                (0U)
-#define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
-#define RTC_TR_SU                    RTC_TR_SU_Msk
-#define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
-#define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
-#define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
-#define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                (20U)
-#define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
-#define RTC_DR_YT                    RTC_DR_YT_Msk
-#define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
-#define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
-#define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
-#define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                (16U)
-#define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
-#define RTC_DR_YU                    RTC_DR_YU_Msk
-#define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
-#define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
-#define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
-#define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos               (13U)
-#define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
-#define RTC_DR_WDU                   RTC_DR_WDU_Msk
-#define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
-#define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
-#define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                (12U)
-#define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
-#define RTC_DR_MT                    RTC_DR_MT_Msk
-#define RTC_DR_MU_Pos                (8U)
-#define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
-#define RTC_DR_MU                    RTC_DR_MU_Msk
-#define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
-#define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
-#define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
-#define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                (4U)
-#define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
-#define RTC_DR_DT                    RTC_DR_DT_Msk
-#define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
-#define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                (0U)
-#define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
-#define RTC_DR_DU                    RTC_DR_DU_Msk
-#define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
-#define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
-#define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
-#define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos               (0U)
-#define RTC_SSR_SS_Msk               (0xFFFFFFFFUL << RTC_SSR_SS_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_SSR_SS                   RTC_SSR_SS_Msk
-
-/********************  Bits definition for RTC_ICSR register  ******************/
-#define RTC_ICSR_RECALPF_Pos         (16U)
-#define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
-#define RTC_ICSR_BCDU_Pos            (10U)
-#define RTC_ICSR_BCDU_Msk            (0x7UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00001C00 */
-#define RTC_ICSR_BCDU                RTC_ICSR_BCDU_Msk
-#define RTC_ICSR_BCDU_0              (0x1UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00000400 */
-#define RTC_ICSR_BCDU_1              (0x2UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00000800 */
-#define RTC_ICSR_BCDU_2              (0x4UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00001000 */
-#define RTC_ICSR_BIN_Pos             (8U)
-#define RTC_ICSR_BIN_Msk             (0x3UL << RTC_ICSR_BIN_Pos)               /*!< 0x00000300 */
-#define RTC_ICSR_BIN                 RTC_ICSR_BIN_Msk
-#define RTC_ICSR_BIN_0               (0x1UL << RTC_ICSR_BIN_Pos)               /*!< 0x00000100 */
-#define RTC_ICSR_BIN_1               (0x2UL << RTC_ICSR_BIN_Pos)               /*!< 0x00000200 */
-#define RTC_ICSR_INIT_Pos            (7U)
-#define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
-#define RTC_ICSR_INITF_Pos           (6U)
-#define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
-#define RTC_ICSR_RSF_Pos             (5U)
-#define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
-#define RTC_ICSR_INITS_Pos           (4U)
-#define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
-#define RTC_ICSR_SHPF_Pos            (3U)
-#define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
-#define RTC_ICSR_WUTWF_Pos           (2U)
-#define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos        (16U)
-#define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
-#define RTC_PRER_PREDIV_S_Pos        (0U)
-#define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUTOCLR_Pos         (16U)
-#define RTC_WUTR_WUTOCLR_Msk         (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)        /*!< 0x0000FFFF */
-#define RTC_WUTR_WUTOCLR             RTC_WUTR_WUTOCLR_Msk
-#define RTC_WUTR_WUT_Pos             (0U)
-#define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_OUT2EN_Pos            (31U)
-#define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
-#define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */
-#define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
-#define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
-#define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */
-#define RTC_CR_TAMPALRM_PU_Pos       (29U)
-#define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
-#define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */
-#define RTC_CR_TAMPOE_Pos            (26U)
-#define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
-#define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */
-#define RTC_CR_TAMPTS_Pos            (25U)
-#define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
-#define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */
-#define RTC_CR_ITSE_Pos              (24U)
-#define RTC_CR_ITSE_Msk              (0x1UL << RTC_CR_ITSE_Pos)                /*!< 0x01000000 */
-#define RTC_CR_ITSE                  RTC_CR_ITSE_Msk                           /*!<Timestamp on internal event enable  */
-#define RTC_CR_COE_Pos               (23U)
-#define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
-#define RTC_CR_COE                   RTC_CR_COE_Msk
-#define RTC_CR_OSEL_Pos              (21U)
-#define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
-#define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
-#define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
-#define RTC_CR_POL_Pos               (20U)
-#define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
-#define RTC_CR_POL                   RTC_CR_POL_Msk
-#define RTC_CR_COSEL_Pos             (19U)
-#define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
-#define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
-#define RTC_CR_BKP_Pos               (18U)
-#define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                 /*!< 0x00040000 */
-#define RTC_CR_BKP                   RTC_CR_BKP_Msk
-#define RTC_CR_SUB1H_Pos             (17U)
-#define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
-#define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
-#define RTC_CR_ADD1H_Pos             (16U)
-#define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
-#define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
-#define RTC_CR_TSIE_Pos              (15U)
-#define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
-#define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
-#define RTC_CR_WUTIE_Pos             (14U)
-#define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
-#define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
-#define RTC_CR_ALRBIE_Pos            (13U)
-#define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
-#define RTC_CR_ALRAIE_Pos            (12U)
-#define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
-#define RTC_CR_TSE_Pos               (11U)
-#define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
-#define RTC_CR_TSE                   RTC_CR_TSE_Msk
-#define RTC_CR_WUTE_Pos              (10U)
-#define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
-#define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
-#define RTC_CR_ALRBE_Pos             (9U)
-#define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
-#define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
-#define RTC_CR_ALRAE_Pos             (8U)
-#define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
-#define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
-#define RTC_CR_SSRUIE_Pos            (7U)
-#define RTC_CR_SSRUIE_Msk            (0x1UL << RTC_CR_SSRUIE_Pos)              /*!< 0x00000080 */
-#define RTC_CR_SSRUIE                RTC_CR_SSRUIE_Msk
-#define RTC_CR_FMT_Pos               (6U)
-#define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
-#define RTC_CR_FMT                   RTC_CR_FMT_Msk
-#define RTC_CR_BYPSHAD_Pos           (5U)
-#define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
-#define RTC_CR_REFCKON_Pos           (4U)
-#define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
-#define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
-#define RTC_CR_TSEDGE_Pos            (3U)
-#define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
-#define RTC_CR_WUCKSEL_Pos           (0U)
-#define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
-#define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos              (0U)
-#define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
-#define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos            (15U)
-#define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
-#define RTC_CALR_CALP                RTC_CALR_CALP_Msk
-#define RTC_CALR_CALW8_Pos           (14U)
-#define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
-#define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
-#define RTC_CALR_CALW16_Pos          (13U)
-#define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
-#define RTC_CALR_LPCAL               RTC_CALR_LPCAL_Msk
-#define RTC_CALR_LPCAL_Pos           (12U)
-#define RTC_CALR_LPCAL_Msk           (0x1UL << RTC_CALR_LPCAL_Pos)             /*!< 0x00001000 */
-#define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
-#define RTC_CALR_CALM_Pos            (0U)
-#define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
-#define RTC_CALR_CALM                RTC_CALR_CALM_Msk
-#define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
-#define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
-#define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
-#define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
-#define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
-#define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
-#define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
-#define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
-#define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_ADD1S_Pos         (31U)
-#define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
-#define RTC_SHIFTR_SUBFS_Pos         (0U)
-#define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos              (22U)
-#define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
-#define RTC_TSTR_PM                  RTC_TSTR_PM_Msk                           
-#define RTC_TSTR_HT_Pos              (20U)
-#define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
-#define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
-#define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos              (16U)
-#define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
-#define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
-#define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos             (12U)
-#define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
-#define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
-#define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos             (8U)
-#define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
-#define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos              (4U)
-#define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
-#define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
-#define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos              (0U)
-#define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
-#define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
-#define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos             (13U)
-#define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk                          
-#define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos              (12U)
-#define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
-#define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
-#define RTC_TSDR_MU_Pos              (8U)
-#define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
-#define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
-#define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos              (4U)
-#define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
-#define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
-#define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos              (0U)
-#define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
-#define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
-#define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos             (0U)
-#define RTC_TSSSR_SS_Msk             (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)        /*!< 0xFFFFFFFF */
-#define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk                          
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos          (31U)
-#define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
-#define RTC_ALRMAR_WDSEL_Pos         (30U)
-#define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
-#define RTC_ALRMAR_DT_Pos            (28U)
-#define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
-#define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos            (24U)
-#define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
-#define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos          (23U)
-#define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
-#define RTC_ALRMAR_PM_Pos            (22U)
-#define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
-#define RTC_ALRMAR_HT_Pos            (20U)
-#define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
-#define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos            (16U)
-#define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
-#define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos          (15U)
-#define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
-#define RTC_ALRMAR_MNT_Pos           (12U)
-#define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
-#define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos           (8U)
-#define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
-#define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos          (7U)
-#define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
-#define RTC_ALRMAR_ST_Pos            (4U)
-#define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
-#define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos            (0U)
-#define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
-#define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_SSCLR_Pos       (31U)
-#define RTC_ALRMASSR_SSCLR_Msk       (0x1UL << RTC_ALRMASSR_SSCLR_Pos)         /*!< 0x80000000 */
-#define RTC_ALRMASSR_SSCLR           RTC_ALRMASSR_SSCLR_Msk
-#define RTC_ALRMASSR_MASKSS_Pos      (24U)
-#define RTC_ALRMASSR_MASKSS_Msk      (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
-#define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMASSR_MASKSS_4        (0x10UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMASSR_MASKSS_5        (0x20UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos          (0U)
-#define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos          (31U)
-#define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
-#define RTC_ALRMBR_WDSEL_Pos         (30U)
-#define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
-#define RTC_ALRMBR_DT_Pos            (28U)
-#define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
-#define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos            (24U)
-#define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
-#define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos          (23U)
-#define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
-#define RTC_ALRMBR_PM_Pos            (22U)
-#define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
-#define RTC_ALRMBR_HT_Pos            (20U)
-#define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
-#define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos            (16U)
-#define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
-#define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos          (15U)
-#define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
-#define RTC_ALRMBR_MNT_Pos           (12U)
-#define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
-#define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos           (8U)
-#define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
-#define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos          (7U)
-#define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
-#define RTC_ALRMBR_ST_Pos            (4U)
-#define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
-#define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos            (0U)
-#define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
-#define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_SSCLR_Pos       (31U)
-#define RTC_ALRMBSSR_SSCLR_Msk       (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)         /*!< 0x80000000 */
-#define RTC_ALRMBSSR_SSCLR           RTC_ALRMBSSR_SSCLR_Msk
-#define RTC_ALRMBSSR_MASKSS_Pos      (24U)
-#define RTC_ALRMBSSR_MASKSS_Msk      (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
-#define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMBSSR_MASKSS_4        (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBSSR_MASKSS_5        (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBSSR_SS_Pos          (0U)
-#define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
-
-/********************  Bits definition for RTC_SR register  *******************/
-#define RTC_SR_SSRUF_Pos             (6U)
-#define RTC_SR_SSRUF_Msk             (0x1UL << RTC_SR_SSRUF_Pos)               /*!< 0x00000040 */
-#define RTC_SR_SSRUF                 RTC_SR_SSRUF_Msk
-#define RTC_SR_ITSF_Pos              (5U)
-#define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                /*!< 0x00000020 */
-#define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
-#define RTC_SR_TSOVF_Pos             (4U)
-#define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */
-#define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk
-#define RTC_SR_TSF_Pos               (3U)
-#define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */
-#define RTC_SR_TSF                   RTC_SR_TSF_Msk
-#define RTC_SR_WUTF_Pos              (2U)
-#define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                /*!< 0x00000004 */
-#define RTC_SR_WUTF                  RTC_SR_WUTF_Msk
-#define RTC_SR_ALRBF_Pos             (1U)
-#define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)               /*!< 0x00000002 */
-#define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
-#define RTC_SR_ALRAF_Pos             (0U)
-#define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */
-#define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
-
-/********************  Bits definition for RTC_MISR register  *****************/
-#define RTC_MISR_SSRUMF_Pos          (6U)
-#define RTC_MISR_SSRUMF_Msk          (0x1UL << RTC_MISR_SSRUMF_Pos)            /*!< 0x00000040 */
-#define RTC_MISR_SSRUMF              RTC_MISR_SSRUMF_Msk
-#define RTC_MISR_ITSMF_Pos           (5U)
-#define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)             /*!< 0x00000020 */
-#define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
-#define RTC_MISR_TSOVMF_Pos          (4U)
-#define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */
-#define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk
-#define RTC_MISR_TSMF_Pos            (3U)
-#define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */
-#define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk
-#define RTC_MISR_WUTMF_Pos           (2U)
-#define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)             /*!< 0x00000004 */
-#define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk
-#define RTC_MISR_ALRBMF_Pos          (1U)
-#define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)            /*!< 0x00000002 */
-#define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
-#define RTC_MISR_ALRAMF_Pos          (0U)
-#define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */
-#define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
-
-/********************  Bits definition for RTC_SCR register  ******************/
-#define RTC_SCR_CSSRUF_Pos           (6U)
-#define RTC_SCR_CSSRUF_Msk           (0x1UL << RTC_SCR_CSSRUF_Pos)             /*!< 0x00000040 */
-#define RTC_SCR_CSSRUF               RTC_SCR_CSSRUF_Msk
-#define RTC_SCR_CITSF_Pos            (5U)
-#define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)              /*!< 0x00000020 */
-#define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
-#define RTC_SCR_CTSOVF_Pos           (4U)
-#define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */
-#define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk
-#define RTC_SCR_CTSF_Pos             (3U)
-#define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */
-#define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk
-#define RTC_SCR_CWUTF_Pos            (2U)
-#define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)              /*!< 0x00000004 */
-#define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk
-#define RTC_SCR_CALRBF_Pos           (1U)
-#define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)             /*!< 0x00000002 */
-#define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
-#define RTC_SCR_CALRAF_Pos           (0U)
-#define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */
-#define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
-
-/********************  Bits definition for RTC_ALRABINR register  ******************/
-#define RTC_ALRABINR_SS_Pos          (0U)
-#define RTC_ALRABINR_SS_Msk          (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)     /*!< 0xFFFFFFFF */
-#define RTC_ALRABINR_SS              RTC_ALRABINR_SS_Msk
-
-/********************  Bits definition for RTC_ALRBBINR register  ******************/
-#define RTC_ALRBBINR_SS_Pos          (0U)
-#define RTC_ALRBBINR_SS_Msk          (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)     /*!< 0xFFFFFFFF */
-#define RTC_ALRBBINR_SS              RTC_ALRBBINR_SS_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
-#define SPI_CR1_CPOL_Pos            (1U)
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
-#define SPI_CR1_MSTR_Pos            (2U)
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
-
-#define SPI_CR1_BR_Pos              (3U)
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos             (6U)
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
-#define SPI_CR1_LSBFIRST_Pos        (7U)
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
-#define SPI_CR1_SSI_Pos             (8U)
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
-#define SPI_CR1_SSM_Pos             (9U)
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
-#define SPI_CR1_RXONLY_Pos          (10U)
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
-#define SPI_CR1_CRCL_Pos            (11U)
-#define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
-#define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
-#define SPI_CR1_CRCNEXT_Pos         (12U)
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
-#define SPI_CR1_CRCEN_Pos           (13U)
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
-#define SPI_CR1_BIDIOE_Pos          (14U)
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_NSSP_Pos            (3U)
-#define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
-#define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
-#define SPI_CR2_FRF_Pos             (4U)
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-#define SPI_CR2_DS_Pos              (8U)
-#define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
-#define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
-#define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
-#define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
-#define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
-#define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
-#define SPI_CR2_FRXTH_Pos           (12U)
-#define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
-#define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
-#define SPI_CR2_LDMARX_Pos          (13U)
-#define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
-#define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
-#define SPI_CR2_LDMATX_Pos          (14U)
-#define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
-#define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
-#define SPI_SR_FRLVL_Pos            (9U)
-#define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
-#define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
-#define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
-#define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
-#define SPI_SR_FTLVL_Pos            (11U)
-#define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
-#define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
-#define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
-#define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)            /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
-#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)         /*!< 0x00001000 */
-#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)           /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)               /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)             /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Tamper and backup register (TAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for TAMP_CR1 register  *****************/
-#define TAMP_CR1_TAMP1E_Pos          (0U)
-#define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */
-#define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
-#define TAMP_CR1_TAMP2E_Pos          (1U)
-#define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */
-#define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
-#define TAMP_CR1_TAMP3E_Pos          (2U)
-#define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */
-#define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk
-#define TAMP_CR1_ITAMP3E_Pos         (18U)
-#define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */
-#define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
-#define TAMP_CR1_ITAMP5E_Pos         (20U)
-#define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */
-#define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
-#define TAMP_CR1_ITAMP6E_Pos         (21U)
-#define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x0020000 */
-#define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
-#define TAMP_CR1_ITAMP8E_Pos         (23U)
-#define TAMP_CR1_ITAMP8E_Msk         (0x1UL << TAMP_CR1_ITAMP8E_Pos)           /*!< 0x00800000 */
-#define TAMP_CR1_ITAMP8E             TAMP_CR1_ITAMP8E_Msk
-
-/********************  Bits definition for TAMP_CR2 register  *****************/
-#define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
-#define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */
-#define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
-#define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
-#define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */
-#define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
-#define TAMP_CR2_TAMP3NOERASE_Pos    (2U)
-#define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */
-#define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk
-#define TAMP_CR2_TAMP1MSK_Pos        (16U)
-#define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)          /*!< 0x00010000 */
-#define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk
-#define TAMP_CR2_TAMP2MSK_Pos        (17U)
-#define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)          /*!< 0x00020000 */
-#define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk
-#define TAMP_CR2_TAMP3MSK_Pos        (18U)
-#define TAMP_CR2_TAMP3MSK_Msk        (0x1UL << TAMP_CR2_TAMP3MSK_Pos)          /*!< 0x00040000 */
-#define TAMP_CR2_TAMP3MSK            TAMP_CR2_TAMP3MSK_Msk
-#define TAMP_CR2_BKERASE_Pos         (23U)
-#define TAMP_CR2_BKERASE_Msk         (0x1UL << TAMP_CR2_BKERASE_Pos)           /*!< 0x00800000 */
-#define TAMP_CR2_BKERASE             TAMP_CR2_BKERASE_Msk
-#define TAMP_CR2_TAMP1TRG_Pos        (24U)
-#define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */
-#define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
-#define TAMP_CR2_TAMP2TRG_Pos        (25U)
-#define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */
-#define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
-#define TAMP_CR2_TAMP3TRG_Pos        (26U)
-#define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x02000000 */
-#define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk
-
-/********************  Bits definition for TAMP_CR3 register  *****************/
-#define TAMP_CR3_ITAMP3NOER_Pos      (2U)
-#define TAMP_CR3_ITAMP3NOER_Msk      (0x1UL << TAMP_CR3_ITAMP3NOER_Pos)        /*!< 0x00000004 */
-#define TAMP_CR3_ITAMP3NOER          TAMP_CR3_ITAMP3NOER_Msk
-#define TAMP_CR3_ITAMP5NOER_Pos      (4U)
-#define TAMP_CR3_ITAMP5NOER_Msk      (0x1UL << TAMP_CR3_ITAMP5NOER_Pos)        /*!< 0x00000010 */
-#define TAMP_CR3_ITAMP5NOER          TAMP_CR3_ITAMP5NOER_Msk
-#define TAMP_CR3_ITAMP6NOER_Pos      (5U)
-#define TAMP_CR3_ITAMP6NOER_Msk      (0x1UL << TAMP_CR3_ITAMP6NOER_Pos)        /*!< 0x00000020 */
-#define TAMP_CR3_ITAMP6NOER          TAMP_CR3_ITAMP6NOER_Msk
-#define TAMP_CR3_ITAMP8NOER_Pos      (7U)
-#define TAMP_CR3_ITAMP8NOER_Msk      (0x1UL << TAMP_CR3_ITAMP8NOER_Pos)        /*!< 0x00800000 */
-#define TAMP_CR3_ITAMP8NOER          TAMP_CR3_ITAMP8NOER_Msk
-
-/********************  Bits definition for TAMP_FLTCR register  ***************/
-#define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
-#define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000007 */
-#define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
-#define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000001 */
-#define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000002 */
-#define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000004 */
-#define TAMP_FLTCR_TAMPFLT_Pos       (3U)
-#define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000018 */
-#define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
-#define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000008 */
-#define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000010 */
-#define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
-#define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000060 */
-#define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
-#define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000020 */
-#define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000040 */
-#define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
-#define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)       /*!< 0x00000080 */
-#define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
-
-/********************  Bits definition for TAMP_IER register  *****************/
-#define TAMP_IER_TAMP1IE_Pos         (0U)
-#define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */
-#define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
-#define TAMP_IER_TAMP2IE_Pos         (1U)
-#define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */
-#define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
-#define TAMP_IER_TAMP3IE_Pos         (2U)
-#define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */
-#define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk
-#define TAMP_IER_ITAMP3IE_Pos        (18U)
-#define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */
-#define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
-#define TAMP_IER_ITAMP5IE_Pos        (20U)
-#define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */
-#define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
-#define TAMP_IER_ITAMP6IE_Pos        (21U)
-#define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x0020000 */
-#define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
-#define TAMP_IER_ITAMP8IE_Pos        (23U)
-#define TAMP_IER_ITAMP8IE_Msk        (0x1UL << TAMP_IER_ITAMP8IE_Pos)          /*!< 0x00800000 */
-#define TAMP_IER_ITAMP8IE            TAMP_IER_ITAMP8IE_Msk
-
-/********************  Bits definition for TAMP_SR register  *****************/
-#define TAMP_SR_TAMP1F_Pos           (0U)
-#define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)             /*!< 0x00000001 */
-#define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
-#define TAMP_SR_TAMP2F_Pos           (1U)
-#define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)            /*!< 0x00000002 */
-#define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
-#define TAMP_SR_TAMP3F_Pos           (2U)
-#define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)             /*!< 0x00000004 */
-#define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk
-#define TAMP_SR_ITAMP3F_Pos          (18U)
-#define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)           /*!< 0x00040000 */
-#define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
-#define TAMP_SR_ITAMP5F_Pos          (20U)
-#define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)           /*!< 0x00100000 */
-#define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
-#define TAMP_SR_ITAMP6F_Pos          (21U)
-#define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)           /*!< 0x0020000 */
-#define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
-#define TAMP_SR_ITAMP8F_Pos          (23U)
-#define TAMP_SR_ITAMP8F_Msk          (0x1UL << TAMP_SR_ITAMP8F_Pos)           /*!< 0x00800000 */
-#define TAMP_SR_ITAMP8F              TAMP_SR_ITAMP8F_Msk
-
-/********************  Bits definition for TAMP_MISR register  ************ *****/
-#define TAMP_MISR_TAMP1MF_Pos        (0U)
-#define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)          /*!< 0x00000001 */
-#define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
-#define TAMP_MISR_TAMP2MF_Pos        (1U)
-#define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)          /*!< 0x00000002 */
-#define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
-#define TAMP_MISR_TAMP3MF_Pos        (2U)
-#define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)          /*!< 0x00000004 */
-#define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk
-#define TAMP_MISR_ITAMP3MF_Pos       (18U)
-#define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)           /*!< 0x00040000 */
-#define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
-#define TAMP_MISR_ITAMP5MF_Pos       (20U)
-#define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)           /*!< 0x00100000 */
-#define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
-#define TAMP_MISR_ITAMP6MF_Pos       (21U)
-#define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)           /*!< 0x0020000 */
-#define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
-#define TAMP_MISR_ITAMP8MF_Pos       (23U)
-#define TAMP_MISR_ITAMP8MF_Msk       (0x1UL << TAMP_MISR_ITAMP8MF_Pos)           /*!< 0x00800000 */
-#define TAMP_MISR_ITAMP8MF           TAMP_MISR_ITAMP8MF_Msk
-
-/********************  Bits definition for TAMP_SMISR register  ************ *****/
-#define TAMP_SMISR_TAMP1MF_Pos       (0U)
-#define TAMP_SMISR_TAMP1MF_Msk       (0x1UL << TAMP_SMISR_TAMP1MF_Pos)         /*!< 0x00000001 */
-#define TAMP_SMISR_TAMP1MF           TAMP_SMISR_TAMP1MF_Msk
-#define TAMP_SMISR_TAMP2MF_Pos       (1U)
-#define TAMP_SMISR_TAMP2MF_Msk       (0x1UL << TAMP_SMISR_TAMP2MF_Pos)         /*!< 0x00000002 */
-#define TAMP_SMISR_TAMP2MF           TAMP_SMISR_TAMP2MF_Msk
-#define TAMP_SMISR_TAMP3MF_Pos       (2U)
-#define TAMP_SMISR_TAMP3MF_Msk       (0x1UL << TAMP_SMISR_TAMP3MF_Pos)         /*!< 0x00000004 */
-#define TAMP_SMISR_TAMP3MF           TAMP_SMISR_TAMP3MF_Msk
-#define TAMP_SMISR_ITAMP3MF_Pos      (18U)
-#define TAMP_SMISR_ITAMP3MF_Msk      (0x1UL << TAMP_SMISR_ITAMP3MF_Pos)        /*!< 0x00040000 */
-#define TAMP_SMISR_ITAMP3MF          TAMP_SMISR_ITAMP3MF_Msk
-#define TAMP_SMISR_ITAMP5MF_Pos      (20U)
-#define TAMP_SMISR_ITAMP5MF_Msk      (0x1UL << TAMP_SMISR_ITAMP5MF_Pos)        /*!< 0x00100000 */
-#define TAMP_SMISR_ITAMP5MF          TAMP_SMISR_ITAMP5MF_Msk
-#define TAMP_SMISR_ITAMP6MF_Pos      (21U)
-#define TAMP_SMISR_ITAMP6MF_Msk      (0x1UL << TAMP_SMISR_ITAMP6MF_Pos)        /*!< 0x0020000 */
-#define TAMP_SMISR_ITAMP6MF          TAMP_SMISR_ITAMP6MF_Msk
-#define TAMP_SMISR_ITAMP8MF_Pos      (23U)
-#define TAMP_SMISR_ITAMP8MF_Msk      (0x1UL << TAMP_SMISR_ITAMP8MF_Pos)        /*!< 0x00800000 */
-#define TAMP_SMISR_ITAMP8MF          TAMP_SMISR_ITAMP8MF_Msk
-
-/********************  Bits definition for TAMP_SCR register  *****************/
-#define TAMP_SCR_CTAMP1F_Pos         (0U)
-#define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)           /*!< 0x00000001 */
-#define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
-#define TAMP_SCR_CTAMP2F_Pos         (1U)
-#define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)           /*!< 0x00000002 */
-#define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
-#define TAMP_SCR_CTAMP3F_Pos         (2U)
-#define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)           /*!< 0x00000004 */
-#define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk
-#define TAMP_SCR_CITAMP3F_Pos        (18U)
-#define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)          /*!< 0x00040000 */
-#define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
-#define TAMP_SCR_CITAMP5F_Pos        (20U)
-#define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)          /*!< 0x00100000 */
-#define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
-#define TAMP_SCR_CITAMP6F_Pos        (21U)
-#define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)          /*!< 0x0020000 */
-#define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
-#define TAMP_SCR_CITAMP8F_Pos        (23U)
-#define TAMP_SCR_CITAMP8F_Msk        (0x1UL << TAMP_SCR_CITAMP8F_Pos)          /*!< 0x00800000 */
-#define TAMP_SCR_CITAMP8F            TAMP_SCR_CITAMP8F_Msk
-
-/********************  Bits definition for TAMP_COUNTR register  ***************/
-#define TAMP_COUNTR_Pos               (0U)
-#define TAMP_COUNTR_Msk               (0xFFFFFFFFUL << TAMP_COUNTR_Pos)        /*!< 0xFFFFFFFF */
-#define TAMP_COUNTR                   TAMP_COUNTR_Msk
-
-/********************  Bits definition for TAMP_BKP0R register  ***************/
-#define TAMP_BKP0R_Pos               (0U)
-#define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP0R                   TAMP_BKP0R_Msk
-
-/********************  Bits definition for TAMP_BKP1R register  ****************/
-#define TAMP_BKP1R_Pos               (0U)
-#define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP1R                   TAMP_BKP1R_Msk
-
-/********************  Bits definition for TAMP_BKP2R register  ****************/
-#define TAMP_BKP2R_Pos               (0U)
-#define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP2R                   TAMP_BKP2R_Msk
-
-/********************  Bits definition for TAMP_BKP3R register  ****************/
-#define TAMP_BKP3R_Pos               (0U)
-#define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP3R                   TAMP_BKP3R_Msk
-
-/********************  Bits definition for TAMP_BKP4R register  ****************/
-#define TAMP_BKP4R_Pos               (0U)
-#define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP4R                   TAMP_BKP4R_Msk
-
-/********************  Bits definition for TAMP_BKP5R register  ****************/
-#define TAMP_BKP5R_Pos               (0U)
-#define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP5R                   TAMP_BKP5R_Msk
-
-/********************  Bits definition for TAMP_BKP6R register  ****************/
-#define TAMP_BKP6R_Pos               (0U)
-#define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP6R                   TAMP_BKP6R_Msk
-
-/********************  Bits definition for TAMP_BKP7R register  ****************/
-#define TAMP_BKP7R_Pos               (0U)
-#define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP7R                   TAMP_BKP7R_Msk
-
-/********************  Bits definition for TAMP_BKP8R register  ****************/
-#define TAMP_BKP8R_Pos               (0U)
-#define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP8R                   TAMP_BKP8R_Msk
-
-/********************  Bits definition for TAMP_BKP9R register  ****************/
-#define TAMP_BKP9R_Pos               (0U)
-#define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP9R                   TAMP_BKP9R_Msk
-
-/********************  Bits definition for TAMP_BKP10R register  ***************/
-#define TAMP_BKP10R_Pos              (0U)
-#define TAMP_BKP10R_Msk              (0xFFFFFFFFUL << TAMP_BKP10R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP10R                  TAMP_BKP10R_Msk
-
-/********************  Bits definition for TAMP_BKP11R register  ***************/
-#define TAMP_BKP11R_Pos              (0U)
-#define TAMP_BKP11R_Msk              (0xFFFFFFFFUL << TAMP_BKP11R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP11R                  TAMP_BKP11R_Msk
-
-/********************  Bits definition for TAMP_BKP12R register  ***************/
-#define TAMP_BKP12R_Pos              (0U)
-#define TAMP_BKP12R_Msk              (0xFFFFFFFFUL << TAMP_BKP12R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP12R                  TAMP_BKP12R_Msk
-
-/********************  Bits definition for TAMP_BKP13R register  ***************/
-#define TAMP_BKP13R_Pos              (0U)
-#define TAMP_BKP13R_Msk              (0xFFFFFFFFUL << TAMP_BKP13R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP13R                  TAMP_BKP13R_Msk
-
-/********************  Bits definition for TAMP_BKP14R register  ***************/
-#define TAMP_BKP14R_Pos              (0U)
-#define TAMP_BKP14R_Msk              (0xFFFFFFFFUL << TAMP_BKP14R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP14R                  TAMP_BKP14R_Msk
-
-/********************  Bits definition for TAMP_BKP15R register  ***************/
-#define TAMP_BKP15R_Pos              (0U)
-#define TAMP_BKP15R_Msk              (0xFFFFFFFFUL << TAMP_BKP15R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP15R                  TAMP_BKP15R_Msk
-
-/********************  Bits definition for TAMP_BKP16R register  ***************/
-#define TAMP_BKP16R_Pos              (0U)
-#define TAMP_BKP16R_Msk              (0xFFFFFFFFUL << TAMP_BKP16R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP16R                  TAMP_BKP16R_Msk
-
-/********************  Bits definition for TAMP_BKP17R register  ***************/
-#define TAMP_BKP17R_Pos              (0U)
-#define TAMP_BKP17R_Msk              (0xFFFFFFFFUL << TAMP_BKP17R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP17R                  TAMP_BKP17R_Msk
-
-/********************  Bits definition for TAMP_BKP18R register  ***************/
-#define TAMP_BKP18R_Pos              (0U)
-#define TAMP_BKP18R_Msk              (0xFFFFFFFFUL << TAMP_BKP18R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP18R                  TAMP_BKP18R_Msk
-
-/********************  Bits definition for TAMP_BKP19R register  ***************/
-#define TAMP_BKP19R_Pos              (0U)
-#define TAMP_BKP19R_Msk              (0xFFFFFFFFUL << TAMP_BKP19R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP19R                  TAMP_BKP19R_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  (SYSCFG memory remap register) ***********************************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos              (0U)
-#define SYSCFG_MEMRMP_MEM_MODE_Msk              (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000007 */
-#define SYSCFG_MEMRMP_MEM_MODE                  SYSCFG_MEMRMP_MEM_MODE_Msk                      /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0                (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1                (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_MEM_MODE_2                (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000004 */
-
-/*****************  Bit definition for SYSCFG_CFGR1 register  (SYSCFG configuration register 1) ****************************************************************/
-#define SYSCFG_CFGR1_BOOSTEN_Pos                (8U)
-#define SYSCFG_CFGR1_BOOSTEN_Msk                (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)             /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOSTEN                    SYSCFG_CFGR1_BOOSTEN_Msk                        /*!< I/O analog switch voltage booster enable                  */
-#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos            (16U)
-#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)         /*!< 0x00010000 */
-#define SYSCFG_CFGR1_I2C_PB6_FMP                SYSCFG_CFGR1_I2C_PB6_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB6 */
-#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos            (17U)
-#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)         /*!< 0x00020000 */
-#define SYSCFG_CFGR1_I2C_PB7_FMP                SYSCFG_CFGR1_I2C_PB7_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB7 */
-#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos            (18U)
-#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)         /*!< 0x00040000 */
-#define SYSCFG_CFGR1_I2C_PB8_FMP                SYSCFG_CFGR1_I2C_PB8_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB8 */
-#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos            (19U)
-#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)         /*!< 0x00080000 */
-#define SYSCFG_CFGR1_I2C_PB9_FMP                SYSCFG_CFGR1_I2C_PB9_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB9 */
-#define SYSCFG_CFGR1_I2C1_FMP_Pos               (20U)
-#define SYSCFG_CFGR1_I2C1_FMP_Msk               (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)            /*!< 0x00100000 */
-#define SYSCFG_CFGR1_I2C1_FMP                   SYSCFG_CFGR1_I2C1_FMP_Msk                       /*!< I2C1 Fast-mode Plus (Fm+) driving capability activation   */
-#define SYSCFG_CFGR1_I2C2_FMP_Pos               (21U)
-#define SYSCFG_CFGR1_I2C2_FMP_Msk               (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)            /*!< 0x00200000 */
-#define SYSCFG_CFGR1_I2C2_FMP                   SYSCFG_CFGR1_I2C2_FMP_Msk                       /*!< I2C2 Fast-mode Plus (Fm+) driving capability activation   */
-#define SYSCFG_CFGR1_I2C3_FMP_Pos               (22U)
-#define SYSCFG_CFGR1_I2C3_FMP_Msk               (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)            /*!< 0x00400000 */
-#define SYSCFG_CFGR1_I2C3_FMP                   SYSCFG_CFGR1_I2C3_FMP_Msk                       /*!< I2C3 Fast-mode Plus (Fm+) driving capability activation   */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  (External interrupt configuration register 1) ********************************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                (0U)
-#define SYSCFG_EXTICR1_EXTI0_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)             /*!< 0x00000007 */
-#define SYSCFG_EXTICR1_EXTI0                    SYSCFG_EXTICR1_EXTI0_Msk                        /*!< External Interrupt Line 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                (4U)
-#define SYSCFG_EXTICR1_EXTI1_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)             /*!< 0x00000070 */
-#define SYSCFG_EXTICR1_EXTI1                    SYSCFG_EXTICR1_EXTI1_Msk                        /*!< External Interrupt Line 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                (8U)
-#define SYSCFG_EXTICR1_EXTI2_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)             /*!< 0x00000700 */
-#define SYSCFG_EXTICR1_EXTI2                    SYSCFG_EXTICR1_EXTI2_Msk                        /*!< External Interrupt Line 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                (12U)
-#define SYSCFG_EXTICR1_EXTI3_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)             /*!< 0x00007000 */
-#define SYSCFG_EXTICR1_EXTI3                    SYSCFG_EXTICR1_EXTI3_Msk                        /*!< External Interrupt Line 3 configuration */
-
-/**
-  * @brief  External Interrupt Line 0 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                 (0x00000000U)   /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                 (0x00000001U)   /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                 (0x00000002U)   /*!< PC[0] pin */
-
-/**
-  * @brief  External Interrupt Line 1 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI1_PA                 (0x00000000U)   /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                 (0x00000010U)   /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                 (0x00000020U)   /*!< PC[1] pin */
-
-/**
-  * @brief  External Interrupt Line 2 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                 (0x00000000U)   /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                 (0x00000100U)   /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                 (0x00000200U)   /*!< PC[2] pin */
-
-/**
-  * @brief  External Interrupt Line 3 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                 (0x00000000U)   /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                 (0x00001000U)   /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                 (0x00002000U)   /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  (External interrupt configuration register 2) ********************************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                (0U)
-#define SYSCFG_EXTICR2_EXTI4_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)             /*!< 0x00000007 */
-#define SYSCFG_EXTICR2_EXTI4                    SYSCFG_EXTICR2_EXTI4_Msk                        /*!< External Interrupt Line 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                (4U)
-#define SYSCFG_EXTICR2_EXTI5_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)             /*!< 0x00000070 */
-#define SYSCFG_EXTICR2_EXTI5                    SYSCFG_EXTICR2_EXTI5_Msk                        /*!< External Interrupt Line 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                (8U)
-#define SYSCFG_EXTICR2_EXTI6_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)             /*!< 0x00000700 */
-#define SYSCFG_EXTICR2_EXTI6                    SYSCFG_EXTICR2_EXTI6_Msk                        /*!< External Interrupt Line 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                (12U)
-#define SYSCFG_EXTICR2_EXTI7_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)             /*!< 0x00007000 */
-#define SYSCFG_EXTICR2_EXTI7                    SYSCFG_EXTICR2_EXTI7_Msk                        /*!< External Interrupt Line 7 configuration */
-
-/**
-  * @brief  External Interrupt Line 4 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                 (0x00000000U)   /*!< PA[4] pin  */
-#define SYSCFG_EXTICR2_EXTI4_PB                 (0x00000001U)   /*!< PB[4] pin  */
-#define SYSCFG_EXTICR2_EXTI4_PC                 (0x00000002U)   /*!< PC[4] pin  */
-
-/**
-  * @brief  External Interrupt Line 5 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                 (0x00000000U)   /*!< PA[5] pin  */
-#define SYSCFG_EXTICR2_EXTI5_PB                 (0x00000010U)   /*!< PB[5] pin  */
-#define SYSCFG_EXTICR2_EXTI5_PC                 (0x00000020U)   /*!< PC[5] pin  */
-
-/**
-  * @brief  External Interrupt Line 6 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                 (0x00000000U)   /*!< PA[6] pin  */
-#define SYSCFG_EXTICR2_EXTI6_PB                 (0x00000100U)   /*!< PB[6] pin  */
-#define SYSCFG_EXTICR2_EXTI6_PC                 (0x00000200U)   /*!< PC[6] pin  */
-
-/**
-  * @brief  External Interrupt Line 7 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                 (0x00000000U)   /*!< PA[7] pin  */
-#define SYSCFG_EXTICR2_EXTI7_PB                 (0x00001000U)   /*!< PB[7] pin  */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  (External interrupt configuration register 3) ********************************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                (0U)
-#define SYSCFG_EXTICR3_EXTI8_Msk                (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)             /*!< 0x00000007 */
-#define SYSCFG_EXTICR3_EXTI8                    SYSCFG_EXTICR3_EXTI8_Msk                        /*!< External Interrupt Line 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                (4U)
-#define SYSCFG_EXTICR3_EXTI9_Msk                (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)             /*!< 0x00000070 */
-#define SYSCFG_EXTICR3_EXTI9                    SYSCFG_EXTICR3_EXTI9_Msk                        /*!< External Interrupt Line 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos               (8U)
-#define SYSCFG_EXTICR3_EXTI10_Msk               (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)            /*!< 0x00000700 */
-#define SYSCFG_EXTICR3_EXTI10                   SYSCFG_EXTICR3_EXTI10_Msk                       /*!< External Interrupt Line 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos               (12U)
-#define SYSCFG_EXTICR3_EXTI11_Msk               (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)            /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                   SYSCFG_EXTICR3_EXTI11_Msk                       /*!< External Interrupt Line 11 configuration */
-
-/**
-  * @brief  External Interrupt Line 8 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                 (0x00000000U)   /*!< PA[8] pin  */
-#define SYSCFG_EXTICR3_EXTI8_PB                 (0x00000001U)   /*!< PB[8] pin  */
-
-/**
-  * @brief  External Interrupt Line 9 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                 (0x00000000U)   /*!< PA[9] pin  */
-#define SYSCFG_EXTICR3_EXTI9_PB                 (0x00000010U)   /*!< PB[9] pin  */
-
-/**
-  * @brief  External Interrupt Line 10 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                (0x00000000U)   /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                (0x00000100U)   /*!< PB[10] pin */
-
-/**
-  * @brief  External Interrupt Line 11 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                (0x00000000U)   /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                (0x00001000U)   /*!< PB[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  (External interrupt configuration register 4) *********************************/
-#define SYSCFG_EXTICR4_EXTI12_Pos               (0U)
-#define SYSCFG_EXTICR4_EXTI12_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)            /*!< 0x00000007 */
-#define SYSCFG_EXTICR4_EXTI12                   SYSCFG_EXTICR4_EXTI12_Msk                       /*!< External Interrupt Line 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos               (4U)
-#define SYSCFG_EXTICR4_EXTI13_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)            /*!< 0x00000070 */
-#define SYSCFG_EXTICR4_EXTI13                   SYSCFG_EXTICR4_EXTI13_Msk                       /*!< External Interrupt Line 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos               (8U)
-#define SYSCFG_EXTICR4_EXTI14_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)            /*!< 0x00000700 */
-#define SYSCFG_EXTICR4_EXTI14                   SYSCFG_EXTICR4_EXTI14_Msk                       /*!< External Interrupt Line 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos               (12U)
-#define SYSCFG_EXTICR4_EXTI15_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)            /*!< 0x00007000 */
-#define SYSCFG_EXTICR4_EXTI15                   SYSCFG_EXTICR4_EXTI15_Msk                       /*!< External Interrupt Line 15 configuration */
-
-/**
-  * @brief  External Interrupt Line 12 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                (0x00000000U)   /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                (0x00000001U)   /*!< PB[12] pin */
-
-/**
-  * @brief  External Interrupt Line 13 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                (0x00000000U)   /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                (0x00000010U)   /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                (0x00000020U)   /*!< PC[13] pin */
-
-/**
-  * @brief  External Interrupt Line 14 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                (0x00000000U)   /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                (0x00000100U)   /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                (0x00000200U)   /*!< PC[14] pin */
-
-/**
-  * @brief  External Interrupt Line 15 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                (0x00000000U)   /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                (0x00001000U)   /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                (0x00002000U)   /*!< PC[15] pin */
-
-/*****************  Bit definition for SYSCFG_SCSR register  (SYSCFG SRAM control and status register) **********************************************************/
-#define SYSCFG_SCSR_SRAM2ER_Pos                 (0U)
-#define SYSCFG_SCSR_SRAM2ER_Msk                 (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)               /*!< 0x00000001 */
-#define SYSCFG_SCSR_SRAM2ER                     SYSCFG_SCSR_SRAM2ER_Msk                          /*!< SRAM2 Erase                                      */
-#define SYSCFG_SCSR_SRAMBSY_Pos                 (1U)
-#define SYSCFG_SCSR_SRAMBSY_Msk                 (0x1UL << SYSCFG_SCSR_SRAMBSY_Pos)              /*!< 0x00000002 */
-#define SYSCFG_SCSR_SRAMBSY                     SYSCFG_SCSR_SRAMBSY_Msk                         /*!< SRAM2 and SRAM1 busy by erase operation                    */
-#define SYSCFG_SCSR_PKASRAMBSY_Pos              (8U)
-#define SYSCFG_SCSR_PKASRAMBSY_Msk              (0x1UL << SYSCFG_SCSR_PKASRAMBSY_Pos)           /*!< 0x00000100 */
-#define SYSCFG_SCSR_PKASRAMBSY                  SYSCFG_SCSR_PKASRAMBSY_Msk                      /*!< PKA SRAM busy by erase operation                           */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  (SYSCFG configuration register 2) *****************************************************************/
-#define SYSCFG_CFGR2_CLL_Pos                    (0U)
-#define SYSCFG_CFGR2_CLL_Msk                    (0x1UL << SYSCFG_CFGR2_CLL_Pos)                 /*!< 0x00000001 */
-#define SYSCFG_CFGR2_CLL                        SYSCFG_CFGR2_CLL_Msk                            /*!< Cortex M4 LOCKUP (hardfault) output enable                 */
-#define SYSCFG_CFGR2_SPL_Pos                    (1U)
-#define SYSCFG_CFGR2_SPL_Msk                    (0x1UL << SYSCFG_CFGR2_SPL_Pos)                 /*!< 0x00000002 */
-#define SYSCFG_CFGR2_SPL                        SYSCFG_CFGR2_SPL_Msk                            /*!< SRAM2 Parity Lock                                          */
-#define SYSCFG_CFGR2_PVDL_Pos                   (2U)
-#define SYSCFG_CFGR2_PVDL_Msk                   (0x1UL << SYSCFG_CFGR2_PVDL_Pos)                /*!< 0x00000004 */
-#define SYSCFG_CFGR2_PVDL                       SYSCFG_CFGR2_PVDL_Msk                           /*!< PVD Lock                                                   */
-#define SYSCFG_CFGR2_ECCL_Pos                   (3U)
-#define SYSCFG_CFGR2_ECCL_Msk                   (0x1UL << SYSCFG_CFGR2_ECCL_Pos)                /*!< 0x00000008 */
-#define SYSCFG_CFGR2_ECCL                       SYSCFG_CFGR2_ECCL_Msk                           /*!< ECC Lock                                                   */
-#define SYSCFG_CFGR2_SPF_Pos                    (8U)
-#define SYSCFG_CFGR2_SPF_Msk                    (0x1UL << SYSCFG_CFGR2_SPF_Pos)                 /*!< 0x00000100 */
-#define SYSCFG_CFGR2_SPF                        SYSCFG_CFGR2_SPF_Msk                            /*!< SRAM2 Parity Lock                                          */
-
-/*****************  Bit definition for SYSCFG_SWPR register  (SYSCFG SRAM2 write protection register) ***********************************************************/
-#define SYSCFG_SWPR_PAGE0_Pos                   (0U)
-#define SYSCFG_SWPR_PAGE0_Msk                   (0x1UL << SYSCFG_SWPR_PAGE0_Pos)                /*!< 0x00000001 */
-#define SYSCFG_SWPR_PAGE0                       SYSCFG_SWPR_PAGE0_Msk                           /*!< SRAM2 Write protection page 0 (0x20008000 – 0x200083FF)    */
-#define SYSCFG_SWPR_PAGE1_Pos                   (1U)
-#define SYSCFG_SWPR_PAGE1_Msk                   (0x1UL << SYSCFG_SWPR_PAGE1_Pos)                /*!< 0x00000002 */
-#define SYSCFG_SWPR_PAGE1                       SYSCFG_SWPR_PAGE1_Msk                           /*!< SRAM2 Write protection page 1 (0x20008400 – 0x200087FF)    */
-#define SYSCFG_SWPR_PAGE2_Pos                   (2U)
-#define SYSCFG_SWPR_PAGE2_Msk                   (0x1UL << SYSCFG_SWPR_PAGE2_Pos)                /*!< 0x00000004 */
-#define SYSCFG_SWPR_PAGE2                       SYSCFG_SWPR_PAGE2_Msk                           /*!< SRAM2 Write protection page 2 (0x20008800 – 0x20008BFF)    */
-#define SYSCFG_SWPR_PAGE3_Pos                   (3U)
-#define SYSCFG_SWPR_PAGE3_Msk                   (0x1UL << SYSCFG_SWPR_PAGE3_Pos)                /*!< 0x00000008 */
-#define SYSCFG_SWPR_PAGE3                       SYSCFG_SWPR_PAGE3_Msk                           /*!< SRAM2 Write protection page 3 (0x20008C00 – 0x20008FFF)    */
-#define SYSCFG_SWPR_PAGE4_Pos                   (4U)
-#define SYSCFG_SWPR_PAGE4_Msk                   (0x1UL << SYSCFG_SWPR_PAGE4_Pos)                /*!< 0x00000010 */
-#define SYSCFG_SWPR_PAGE4                       SYSCFG_SWPR_PAGE4_Msk                           /*!< SRAM2 Write protection page 4 (0x20009000 – 0x200093FF)    */
-#define SYSCFG_SWPR_PAGE5_Pos                   (5U)
-#define SYSCFG_SWPR_PAGE5_Msk                   (0x1UL << SYSCFG_SWPR_PAGE5_Pos)                /*!< 0x00000020 */
-#define SYSCFG_SWPR_PAGE5                       SYSCFG_SWPR_PAGE5_Msk                           /*!< SRAM2 Write protection page 5 (0x20009400 – 0x200097FF)    */
-#define SYSCFG_SWPR_PAGE6_Pos                   (6U)
-#define SYSCFG_SWPR_PAGE6_Msk                   (0x1UL << SYSCFG_SWPR_PAGE6_Pos)                /*!< 0x00000040 */
-#define SYSCFG_SWPR_PAGE6                       SYSCFG_SWPR_PAGE6_Msk                           /*!< SRAM2 Write protection page 6 (0x20009800 – 0x20009BFF)    */
-#define SYSCFG_SWPR_PAGE7_Pos                   (7U)
-#define SYSCFG_SWPR_PAGE7_Msk                   (0x1UL << SYSCFG_SWPR_PAGE7_Pos)                /*!< 0x00000080 */
-#define SYSCFG_SWPR_PAGE7                       SYSCFG_SWPR_PAGE7_Msk                           /*!< SRAM2 Write protection page 7 (0x20009C00 – 0x20009FFF)    */
-#define SYSCFG_SWPR_PAGE8_Pos                   (8U)
-#define SYSCFG_SWPR_PAGE8_Msk                   (0x1UL << SYSCFG_SWPR_PAGE8_Pos)                /*!< 0x00000100 */
-#define SYSCFG_SWPR_PAGE8                       SYSCFG_SWPR_PAGE8_Msk                           /*!< SRAM2 Write protection page 8 (0x2000A000 – 0x2000A3FF)    */
-#define SYSCFG_SWPR_PAGE9_Pos                   (9U)
-#define SYSCFG_SWPR_PAGE9_Msk                   (0x1UL << SYSCFG_SWPR_PAGE9_Pos)                /*!< 0x00000200 */
-#define SYSCFG_SWPR_PAGE9                       SYSCFG_SWPR_PAGE9_Msk                           /*!< SRAM2 Write protection page 9 (0x2000A400 – 0x2000A7FF)    */
-#define SYSCFG_SWPR_PAGE10_Pos                  (10U)
-#define SYSCFG_SWPR_PAGE10_Msk                  (0x1UL << SYSCFG_SWPR_PAGE10_Pos)               /*!< 0x00000400 */
-#define SYSCFG_SWPR_PAGE10                      SYSCFG_SWPR_PAGE10_Msk                          /*!< SRAM2 Write protection page 10 (0x2000A800 – 0x2000ABFF)   */
-#define SYSCFG_SWPR_PAGE11_Pos                  (11U)
-#define SYSCFG_SWPR_PAGE11_Msk                  (0x1UL << SYSCFG_SWPR_PAGE11_Pos)               /*!< 0x00000800 */
-#define SYSCFG_SWPR_PAGE11                      SYSCFG_SWPR_PAGE11_Msk                          /*!< SRAM2 Write protection page 11 (0x2000AC00 – 0x2000AFFF)   */
-#define SYSCFG_SWPR_PAGE12_Pos                  (12U)
-#define SYSCFG_SWPR_PAGE12_Msk                  (0x1UL << SYSCFG_SWPR_PAGE12_Pos)               /*!< 0x00001000 */
-#define SYSCFG_SWPR_PAGE12                      SYSCFG_SWPR_PAGE12_Msk                          /*!< SRAM2 Write protection page 12 (0x2000B000 – 0x2000B3FF)   */
-#define SYSCFG_SWPR_PAGE13_Pos                  (13U)
-#define SYSCFG_SWPR_PAGE13_Msk                  (0x1UL << SYSCFG_SWPR_PAGE13_Pos)               /*!< 0x00002000 */
-#define SYSCFG_SWPR_PAGE13                      SYSCFG_SWPR_PAGE13_Msk                          /*!< SRAM2 Write protection page 13 (0x2000B400 – 0x2000B7FF)   */
-#define SYSCFG_SWPR_PAGE14_Pos                  (14U)
-#define SYSCFG_SWPR_PAGE14_Msk                  (0x1UL << SYSCFG_SWPR_PAGE14_Pos)               /*!< 0x00004000 */
-#define SYSCFG_SWPR_PAGE14                      SYSCFG_SWPR_PAGE14_Msk                          /*!< SRAM2 Write protection page 14 (0x2000B800 – 0x2000BBFF)   */
-#define SYSCFG_SWPR_PAGE15_Pos                  (15U)
-#define SYSCFG_SWPR_PAGE15_Msk                  (0x1UL << SYSCFG_SWPR_PAGE15_Pos)               /*!< 0x00008000 */
-#define SYSCFG_SWPR_PAGE15                      SYSCFG_SWPR_PAGE15_Msk                          /*!< SRAM2 Write protection page 15 (0x2000BC00 – 0x2000BFFF)   */
-#define SYSCFG_SWPR_PAGE16_Pos                  (16U)
-#define SYSCFG_SWPR_PAGE16_Msk                  (0x1UL << SYSCFG_SWPR_PAGE16_Pos)               /*!< 0x00010000 */
-#define SYSCFG_SWPR_PAGE16                      SYSCFG_SWPR_PAGE16_Msk                          /*!< SRAM2 Write protection page 16 (0x2000C000 – 0x2000C3FF)   */
-#define SYSCFG_SWPR_PAGE17_Pos                  (17U)
-#define SYSCFG_SWPR_PAGE17_Msk                  (0x1UL << SYSCFG_SWPR_PAGE17_Pos)               /*!< 0x00020000 */
-#define SYSCFG_SWPR_PAGE17                      SYSCFG_SWPR_PAGE17_Msk                          /*!< SRAM2 Write protection page 17 (0x2000C400 – 0x2000C7FF)   */
-#define SYSCFG_SWPR_PAGE18_Pos                  (18U)
-#define SYSCFG_SWPR_PAGE18_Msk                  (0x1UL << SYSCFG_SWPR_PAGE18_Pos)               /*!< 0x00040000 */
-#define SYSCFG_SWPR_PAGE18                      SYSCFG_SWPR_PAGE18_Msk                          /*!< SRAM2 Write protection page 18 (0x2000C800 – 0x2000CBFF)   */
-#define SYSCFG_SWPR_PAGE19_Pos                  (19U)
-#define SYSCFG_SWPR_PAGE19_Msk                  (0x1UL << SYSCFG_SWPR_PAGE19_Pos)               /*!< 0x00080000 */
-#define SYSCFG_SWPR_PAGE19                      SYSCFG_SWPR_PAGE19_Msk                          /*!< SRAM2 Write protection page 19 (0x2000CC00 – 0x2000CFFF)   */
-#define SYSCFG_SWPR_PAGE20_Pos                  (20U)
-#define SYSCFG_SWPR_PAGE20_Msk                  (0x1UL << SYSCFG_SWPR_PAGE20_Pos)               /*!< 0x00100000 */
-#define SYSCFG_SWPR_PAGE20                      SYSCFG_SWPR_PAGE20_Msk                          /*!< SRAM2 Write protection page 20 (0x2000D000 – 0x2000D3FF)   */
-#define SYSCFG_SWPR_PAGE21_Pos                  (21U)
-#define SYSCFG_SWPR_PAGE21_Msk                  (0x1UL << SYSCFG_SWPR_PAGE21_Pos)               /*!< 0x00200000 */
-#define SYSCFG_SWPR_PAGE21                      SYSCFG_SWPR_PAGE21_Msk                          /*!< SRAM2 Write protection page 21 (0x2000D400 – 0x2000D7FF)   */
-#define SYSCFG_SWPR_PAGE22_Pos                  (22U)
-#define SYSCFG_SWPR_PAGE22_Msk                  (0x1UL << SYSCFG_SWPR_PAGE22_Pos)               /*!< 0x00400000 */
-#define SYSCFG_SWPR_PAGE22                      SYSCFG_SWPR_PAGE22_Msk                          /*!< SRAM2 Write protection page 22 (0x2000D800 – 0x2000DBFF)   */
-#define SYSCFG_SWPR_PAGE23_Pos                  (23U)
-#define SYSCFG_SWPR_PAGE23_Msk                  (0x1UL << SYSCFG_SWPR_PAGE23_Pos)               /*!< 0x00800000 */
-#define SYSCFG_SWPR_PAGE23                      SYSCFG_SWPR_PAGE23_Msk                          /*!< SRAM2 Write protection page 23 (0x2000DC00 – 0x2000DFFF)   */
-#define SYSCFG_SWPR_PAGE24_Pos                  (24U)
-#define SYSCFG_SWPR_PAGE24_Msk                  (0x1UL << SYSCFG_SWPR_PAGE24_Pos)               /*!< 0x01000000 */
-#define SYSCFG_SWPR_PAGE24                      SYSCFG_SWPR_PAGE24_Msk                          /*!< SRAM2 Write protection page 24 (0x2000E000 – 0x2000E3FF)   */
-#define SYSCFG_SWPR_PAGE25_Pos                  (25U)
-#define SYSCFG_SWPR_PAGE25_Msk                  (0x1UL << SYSCFG_SWPR_PAGE25_Pos)               /*!< 0x02000000 */
-#define SYSCFG_SWPR_PAGE25                      SYSCFG_SWPR_PAGE25_Msk                          /*!< SRAM2 Write protection page 25 (0x2000E400 – 0x2000E7FF)   */
-#define SYSCFG_SWPR_PAGE26_Pos                  (26U)
-#define SYSCFG_SWPR_PAGE26_Msk                  (0x1UL << SYSCFG_SWPR_PAGE26_Pos)               /*!< 0x04000000 */
-#define SYSCFG_SWPR_PAGE26                      SYSCFG_SWPR_PAGE26_Msk                          /*!< SRAM2 Write protection page 26 (0x2000E800 – 0x2000EBFF)   */
-#define SYSCFG_SWPR_PAGE27_Pos                  (27U)
-#define SYSCFG_SWPR_PAGE27_Msk                  (0x1UL << SYSCFG_SWPR_PAGE27_Pos)               /*!< 0x08000000 */
-#define SYSCFG_SWPR_PAGE27                      SYSCFG_SWPR_PAGE27_Msk                          /*!< SRAM2 Write protection page 27 (0x2000EC00 – 0x2000EFFF)   */
-#define SYSCFG_SWPR_PAGE28_Pos                  (28U)
-#define SYSCFG_SWPR_PAGE28_Msk                  (0x1UL << SYSCFG_SWPR_PAGE28_Pos)               /*!< 0x10000000 */
-#define SYSCFG_SWPR_PAGE28                      SYSCFG_SWPR_PAGE28_Msk                          /*!< SRAM2 Write protection page 28 (0x2000F000 – 0x2000F3FF)   */
-#define SYSCFG_SWPR_PAGE29_Pos                  (29U)
-#define SYSCFG_SWPR_PAGE29_Msk                  (0x1UL << SYSCFG_SWPR_PAGE29_Pos)               /*!< 0x20000000 */
-#define SYSCFG_SWPR_PAGE29                      SYSCFG_SWPR_PAGE29_Msk                          /*!< SRAM2 Write protection page 29 (0x2000F400 – 0x2000F7FF)   */
-#define SYSCFG_SWPR_PAGE30_Pos                  (30U)
-#define SYSCFG_SWPR_PAGE30_Msk                  (0x1UL << SYSCFG_SWPR_PAGE30_Pos)               /*!< 0x40000000 */
-#define SYSCFG_SWPR_PAGE30                      SYSCFG_SWPR_PAGE30_Msk                          /*!< SRAM2 Write protection page 30 (0x2000F800 – 0x2000FBFF)   */
-#define SYSCFG_SWPR_PAGE31_Pos                  (31U)
-#define SYSCFG_SWPR_PAGE31_Msk                  (0x1UL << SYSCFG_SWPR_PAGE31_Pos)               /*!< 0x80000000 */
-#define SYSCFG_SWPR_PAGE31                      SYSCFG_SWPR_PAGE31_Msk                          /*!< SRAM2 Write protection page 31 (0x2000FC00 – 0x2000FFFF)   */
-
-/*****************  Bit definition for SYSCFG_SKR register  (SYSCFG SRAM2 key register) *************************************************************************/
-#define SYSCFG_SKR_KEY_Pos                      (0U)
-#define SYSCFG_SKR_KEY_Msk                      (0xFFUL << SYSCFG_SKR_KEY_Pos)                  /*!< 0x000000FF */
-#define SYSCFG_SKR_KEY                          SYSCFG_SKR_KEY_Msk                              /*!< SRAM2 write protection key for software erase              */
-
-/**************************************  Bit definition for SYSCFG_RFDCR register (SYSCFG radio debug control register) ************************************************/
-#define SYSCFG_RFDCR_RFTBSEL_Pos                (0U)
-#define SYSCFG_RFDCR_RFTBSEL_Msk                (0x1UL << SYSCFG_RFDCR_RFTBSEL_Pos)             /*!< 0x00000001 */
-#define SYSCFG_RFDCR_RFTBSEL                    SYSCFG_RFDCR_RFTBSEL_Msk                        /*!< Radio debug test bus selection                                    */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface (I2C)              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK_Pos          (8U)
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
-#define I2C_OAR2_OA2NOMASK           (0x00000000UL)                            /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 VREFBUF                                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for VREFBUF_CSR register  ****************/
-#define VREFBUF_CSR_ENVR_Pos    (0U)
-#define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                /*!< 0x00000001 */
-#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
-#define VREFBUF_CSR_HIZ_Pos     (1U)
-#define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                 /*!< 0x00000002 */
-#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
-#define VREFBUF_CSR_VRS_Pos     (2U)
-#define VREFBUF_CSR_VRS_Msk     (0x1UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000004 */
-#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference buffer ready  */
-#define VREFBUF_CSR_VRR_Pos     (3U)
-#define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                 /*!< 0x00000008 */
-#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference scale         */
-
-/*******************  Bit definition for VREFBUF_CCR register  ******************/
-#define VREFBUF_CCR_TRIM_Pos    (0U)
-#define VREFBUF_CCR_TRIM_Msk    (0x3FUL << VREFBUF_CCR_TRIM_Pos)               /*!< 0x0000003F */
-#define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
-
-#define WWDG_CR_WDGA_Pos        (7U)
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
-
-#define WWDG_CFR_EWI_Pos        (9U)
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
-
-#define WWDG_CFR_WDGTB_Pos      (11U)
-#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000800 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00001000 */
-#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00002000 */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                Debug MCU                                   */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                          (0U)
-#define DBGMCU_IDCODE_DEV_ID_Msk                          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                              DBGMCU_IDCODE_DEV_ID_Msk
-#define DBGMCU_IDCODE_REV_ID_Pos                          (16U)
-#define DBGMCU_IDCODE_REV_ID_Msk                          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                              DBGMCU_IDCODE_REV_ID_Msk
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                           (0U)
-#define DBGMCU_CR_DBG_SLEEP_Msk                           (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)  /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                               DBGMCU_CR_DBG_SLEEP_Msk
-#define DBGMCU_CR_DBG_STOP_Pos                            (1U)
-#define DBGMCU_CR_DBG_STOP_Msk                            (0x1UL << DBGMCU_CR_DBG_STOP_Pos)   /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                                DBGMCU_CR_DBG_STOP_Msk
-#define DBGMCU_CR_DBG_STANDBY_Pos                         (2U)
-#define DBGMCU_CR_DBG_STANDBY_Msk                         (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                             DBGMCU_CR_DBG_STANDBY_Msk
-
-/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos                 (0U)
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)  /*!< 0x00000001 */
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP                     DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos                  (10U)
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk                  (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)   /*!< 0x00000400 */
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP                      DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos                 (11U)
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)  /*!< 0x00000800 */
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP                     DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos                 (12U)
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)  /*!< 0x00001000 */
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP                     DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos                 (21U)
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)  /*!< 0x00200000 */
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP                     DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos                 (22U)
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)  /*!< 0x00400000 */
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP                     DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos                 (23U)
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)  /*!< 0x00800000 */
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP                     DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos               (31U)
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk               (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP                   DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
-
-/********************  Bit definition for DBGMCU_APB1FZR2 register  ***********/
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos               (5U)
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk               (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)/*!< 0x00000020 */
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP                   DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
-#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Pos               (6U)
-#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk               (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Pos)/*!< 0x00000040 */
-#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP                   DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk
-
-/********************  Bit definition for DBGMCU_APB2FZR register  ************/
-#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos                  (11U)
-#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk                  (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)/*!< 0x000000800 */
-#define DBGMCU_APB2FZR_DBG_TIM1_STOP                      DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk
-#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos                 (17U)
-#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk                 (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
-#define DBGMCU_APB2FZR_DBG_TIM16_STOP                     DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk
-#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos                 (18U)
-#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk                 (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
-#define DBGMCU_APB2FZR_DBG_TIM17_STOP                     DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
-
-#define TIM_CR1_UIFREMAP_Pos      (11U)
-#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
-#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCPC_Pos          (0U)
-#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
-#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS_Pos          (2U)
-#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
-#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS_Pos          (3U)
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-#define TIM_CR2_OIS1_Pos          (8U)
-#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
-#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N_Pos         (9U)
-#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
-#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2_Pos          (10U)
-#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
-#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N_Pos         (11U)
-#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
-#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3_Pos          (12U)
-#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
-#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N_Pos         (13U)
-#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
-#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4_Pos          (14U)
-#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
-#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS5_Pos          (16U)
-#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
-#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
-#define TIM_CR2_OIS6_Pos          (18U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
-#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
-
-#define TIM_CR2_MMS2_Pos          (20U)
-#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
-#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
-#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
-#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
-#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)
-#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
-#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
-
-#define TIM_SMCR_OCCS_Pos         (3U)
-#define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
-#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos           (4U)
-#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
-#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
-#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
-
-#define TIM_SMCR_MSM_Pos          (7U)
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE_Pos        (5U)
-#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
-#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_BIE_Pos          (7U)
-#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
-#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE_Pos        (13U)
-#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
-#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF_Pos          (5U)
-#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
-#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF_Pos            (7U)
-#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
-#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
-#define TIM_SR_B2IF_Pos           (8U)
-#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
-#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-#define TIM_SR_SBIF_Pos           (13U)
-#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
-#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
-#define TIM_SR_CC5IF_Pos          (16U)
-#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
-#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
-#define TIM_SR_CC6IF_Pos          (17U)
-#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
-#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
-
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG_Pos          (5U)
-#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
-#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG_Pos            (6U)
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-#define TIM_EGR_BG_Pos            (7U)
-#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
-#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
-#define TIM_EGR_B2G_Pos           (8U)
-#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
-#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)
-#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
-#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)
-#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
-#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-#define TIM_CCMR1_IC1PSC_Pos      (2U)
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
-#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-#define TIM_CCMR2_IC3PSC_Pos      (2U)
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR3 register  *******************/
-#define TIM_CCMR3_OC5FE_Pos       (2U)
-#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
-#define TIM_CCMR3_OC5PE_Pos       (3U)
-#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
-#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
-
-#define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
-#define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
-#define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
-#define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
-#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
-
-#define TIM_CCMR3_OC5CE_Pos       (7U)
-#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
-#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
-
-#define TIM_CCMR3_OC6FE_Pos       (10U)
-#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
-#define TIM_CCMR3_OC6PE_Pos       (11U)
-#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
-#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
-
-#define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
-#define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
-#define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
-#define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
-
-#define TIM_CCMR3_OC6CE_Pos       (15U)
-#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
-#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE_Pos        (2U)
-#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
-#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP_Pos        (3U)
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE_Pos        (6U)
-#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
-#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP_Pos        (7U)
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE_Pos        (10U)
-#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
-#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP_Pos        (11U)
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-#define TIM_CCER_CC5E_Pos         (16U)
-#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
-#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
-#define TIM_CCER_CC5P_Pos         (17U)
-#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
-#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
-#define TIM_CCER_CC6E_Pos         (20U)
-#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
-#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
-#define TIM_CCER_CC6P_Pos         (21U)
-#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
-#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)
-#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-#define TIM_CNT_UIFCPY_Pos        (31U)
-#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
-#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)
-#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define TIM_RCR_REP_Pos           (0U)
-#define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
-#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)
-#define TIM_CCR1_CCR1_Msk         (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)
-#define TIM_CCR2_CCR2_Msk         (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)
-#define TIM_CCR3_CCR3_Msk         (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)
-#define TIM_CCR4_CCR4_Msk         (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_CCR5 register  *******************/
-#define TIM_CCR5_CCR5_Pos         (0U)
-#define TIM_CCR5_CCR5_Msk         (0xFFFFUL << TIM_CCR5_CCR5_Pos)              /*!< 0x0000FFFF */
-#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
-#define TIM_CCR5_GC5C1_Pos        (29U)
-#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
-#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
-#define TIM_CCR5_GC5C2_Pos        (30U)
-#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
-#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
-#define TIM_CCR5_GC5C3_Pos        (31U)
-#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
-#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
-
-/*******************  Bit definition for TIM_CCR6 register  *******************/
-#define TIM_CCR6_CCR6_Pos         (0U)
-#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
-#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define TIM_BDTR_DTG_Pos          (0U)
-#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
-#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
-#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
-#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
-#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
-#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
-#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
-#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
-#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
-
-#define TIM_BDTR_LOCK_Pos         (8U)
-#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
-#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
-#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
-
-#define TIM_BDTR_OSSI_Pos         (10U)
-#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
-#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR_Pos         (11U)
-#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
-#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE_Pos          (12U)
-#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
-#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
-#define TIM_BDTR_BKP_Pos          (13U)
-#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
-#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
-#define TIM_BDTR_AOE_Pos          (14U)
-#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
-#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
-#define TIM_BDTR_MOE_Pos          (15U)
-#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
-#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
-
-#define TIM_BDTR_BKF_Pos          (16U)
-#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
-#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
-#define TIM_BDTR_BK2F_Pos         (20U)
-#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
-#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
-
-#define TIM_BDTR_BK2E_Pos         (24U)
-#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
-#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
-#define TIM_BDTR_BK2P_Pos         (25U)
-#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
-#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
-
-
-#define TIM_BDTR_BKDSRM_Pos       (26U)
-#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
-#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
-#define TIM_BDTR_BK2DSRM_Pos      (27U)
-#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
-#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
-
-#define TIM_BDTR_BKBID_Pos        (28U)
-#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
-#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
-#define TIM_BDTR_BK2BID_Pos       (29U)
-#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
-#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM1_OR1 register  ******************/
-#define TIM1_OR1_ETR_ADC_RMP_Pos   (0U)
-#define TIM1_OR1_ETR_ADC_RMP_Msk   (0x3UL << TIM1_OR1_ETR_ADC_RMP_Pos)         /*!< 0x00000003 */
-#define TIM1_OR1_ETR_ADC_RMP       TIM1_OR1_ETR_ADC_RMP_Msk                    /*!< TIM1_ETR_ADC remapping capability */
-#define TIM1_OR1_ETR_ADC_RMP_0     (0x1UL << TIM1_OR1_ETR_ADC_RMP_Pos)         /*!< 0x00000001 */
-#define TIM1_OR1_ETR_ADC_RMP_1     (0x2UL << TIM1_OR1_ETR_ADC_RMP_Pos)         /*!< 0x00000002 */
-#define TIM1_OR1_TI1_RMP_Pos       (4U)
-#define TIM1_OR1_TI1_RMP_Msk       (0x1UL << TIM1_OR1_TI1_RMP_Pos)             /*!< 0x00000010 */
-#define TIM1_OR1_TI1_RMP           TIM1_OR1_TI1_RMP_Msk                        /*!< Input Capture 1 remap*/
-
-/*******************  Bit definition for TIM2_OR1 register  ******************/
-#define TIM2_OR1_TI4_RMP_Pos       (2U)
-#define TIM2_OR1_TI4_RMP_Msk       (0x3UL << TIM2_OR1_TI4_RMP_Pos)             /*!< 0x0000000C */
-#define TIM2_OR1_TI4_RMP           TIM2_OR1_TI4_RMP_Msk                        /*!< TI4 RMA[1:0]Input capture 4 remap*/
-#define TIM2_OR1_TI4_RMP_0         (0x1UL << TIM2_OR1_TI4_RMP_Pos)             /*!< 0x00000004 */
-#define TIM2_OR1_TI4_RMP_1         (0x2UL << TIM2_OR1_TI4_RMP_Pos)             /*!< 0x00000008 */
-#define TIM2_OR1_ETR_RMP_Pos       (1U)
-#define TIM2_OR1_ETR_RMP_Msk       (0x1UL << TIM2_OR1_ETR_RMP_Pos)             /*!< 0x00000002 */
-#define TIM2_OR1_ETR_RMP           TIM2_OR1_ETR_RMP_Msk                        /*!< External trigger remap*/
-
-/*******************  Bit definition for TIM16_OR1 register  *****************/
-#define TIM16_OR1_TI1_RMP_Pos      (0U)
-#define TIM16_OR1_TI1_RMP_Msk      (0x3UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000003 */
-#define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<Timer 16 input 1 connection. */
-#define TIM16_OR1_TI1_RMP_0        (0x1UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */
-#define TIM16_OR1_TI1_RMP_1        (0x2UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */
-
-/*******************  Bit definition for TIM17_OR1 register  *****************/
-#define TIM17_OR1_TI1_RMP_Pos      (0U)
-#define TIM17_OR1_TI1_RMP_Msk      (0x3UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000003 */
-#define TIM17_OR1_TI1_RMP          TIM17_OR1_TI1_RMP_Msk                       /*!<Timer 17 input 1 connection. */
-#define TIM17_OR1_TI1_RMP_0        (0x1UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */
-#define TIM17_OR1_TI1_RMP_1        (0x2UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */
-
-/*******************  Bit definition for TIM1_AF1 register  *******************/
-#define TIM1_AF1_BKINE_Pos        (0U)
-#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
-#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
-#define TIM1_AF1_BKCMP1E_Pos      (1U)                                         
-#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
-#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
-#define TIM1_AF1_BKCMP2E_Pos      (2U)                                         
-#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
-#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
-#define TIM1_AF1_BKINP_Pos        (9U)                                         
-#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
-#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
-#define TIM1_AF1_BKCMP1P_Pos      (10U)                                        
-#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
-#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
-#define TIM1_AF1_BKCMP2P_Pos      (11U)                                        
-#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
-#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
-#define TIM1_AF1_ETRSEL_Pos       (14U)                                        
-#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
-#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
-#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
-#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
-#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
-#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
-
-/*******************  Bit definition for TIM2_AF1 register  *******************/
-#define TIM2_AF1_ETRSEL_Pos       (14U)
-#define TIM2_AF1_ETRSEL_Msk       (0xFUL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
-#define TIM2_AF1_ETRSEL           (0x00003C000)                                /*!< External trigger source selection */
-#define TIM2_AF1_ETRSEL_0         (0x000004000)                                /*!< Bit_0 */
-#define TIM2_AF1_ETRSEL_1         (0x000008000)                                /*!< Bit_1 */
-#define TIM2_AF1_ETRSEL_2         (0x000010000)                                /*!< Bit_2 */
-#define TIM2_AF1_ETRSEL_3         (0x000020000)                                /*!< Bit_3 */
-
-/*******************  Bit definition for TIM16_AF1 register  *******************/
-#define TIM16_AF1_BKINE_Pos       (0U)
-#define TIM16_AF1_BKINE_Msk       (0x1UL << TIM16_AF1_BKINE_Pos)               /*!< 0x00000001 */
-#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BRK BKIN input enable */
-#define TIM16_AF1_BKCMP1E_Pos     (1U)
-#define TIM16_AF1_BKCMP1E_Msk     (0x1UL << TIM16_AF1_BKCMP1E_Pos)             /*!< 0x00000002 */
-#define TIM16_AF1_BKCMP1E         TIM16_AF1_BKCMP1E_Msk                        /*!<BRK COMP1 enable */
-#define TIM16_AF1_BKCMP2E_Pos     (2U)                                         
-#define TIM16_AF1_BKCMP2E_Msk     (0x1UL << TIM16_AF1_BKCMP2E_Pos)             /*!< 0x00000004 */
-#define TIM16_AF1_BKCMP2E         TIM16_AF1_BKCMP2E_Msk                        /*!<BRK COMP2 enable */
-#define TIM16_AF1_BKINP_Pos       (9U)                                         
-#define TIM16_AF1_BKINP_Msk       (0x1UL << TIM16_AF1_BKINP_Pos)               /*!< 0x00000200 */
-#define TIM16_AF1_BKINP           TIM16_AF1_BKINP_Msk                          /*!<BRK BKIN2 input polarity */
-#define TIM16_AF1_BKCMP1P_Pos     (10U)                                        
-#define TIM16_AF1_BKCMP1P_Msk     (0x1UL << TIM16_AF1_BKCMP1P_Pos)             /*!< 0x00000400 */
-#define TIM16_AF1_BKCMP1P         TIM16_AF1_BKCMP1P_Msk                        /*!<BRK COMP1 input polarity */
-#define TIM16_AF1_BKCMP2P_Pos     (11U)                                        
-#define TIM16_AF1_BKCMP2P_Msk     (0x1UL << TIM16_AF1_BKCMP2P_Pos)             /*!< 0x00000800 */
-#define TIM16_AF1_BKCMP2P         TIM16_AF1_BKCMP2P_Msk                        /*!<BRK COMP2 input polarity */
-
-/*******************  Bit definition for TIM17_AF1 register  *******************/
-#define TIM17_AF1_BKINE_Pos       (0U)
-#define TIM17_AF1_BKINE_Msk       (0x1UL << TIM17_AF1_BKINE_Pos)               /*!< 0x00000001 */
-#define TIM17_AF1_BKINE           TIM17_AF1_BKINE_Msk                          /*!<BRK BKIN input enable */
-#define TIM17_AF1_BKCMP1E_Pos     (1U)
-#define TIM17_AF1_BKCMP1E_Msk     (0x1UL << TIM17_AF1_BKCMP1E_Pos)             /*!< 0x00000002 */
-#define TIM17_AF1_BKCMP1E         TIM17_AF1_BKCMP1E_Msk                        /*!<BRK COMP1 enable */
-#define TIM17_AF1_BKCMP2E_Pos     (2U)                                         
-#define TIM17_AF1_BKCMP2E_Msk     (0x1UL << TIM17_AF1_BKCMP2E_Pos)             /*!< 0x00000004 */
-#define TIM17_AF1_BKCMP2E         TIM17_AF1_BKCMP2E_Msk                        /*!<BRK COMP2 enable */
-#define TIM17_AF1_BKINP_Pos       (9U)                                         
-#define TIM17_AF1_BKINP_Msk       (0x1UL << TIM17_AF1_BKINP_Pos)               /*!< 0x00000200 */
-#define TIM17_AF1_BKINP           TIM17_AF1_BKINP_Msk                          /*!<BRK BKIN2 input polarity */
-#define TIM17_AF1_BKCMP1P_Pos     (10U)                                        
-#define TIM17_AF1_BKCMP1P_Msk     (0x1UL << TIM17_AF1_BKCMP1P_Pos)             /*!< 0x00000400 */
-#define TIM17_AF1_BKCMP1P         TIM17_AF1_BKCMP1P_Msk                        /*!<BRK COMP1 input polarity */
-#define TIM17_AF1_BKCMP2P_Pos     (11U)                                        
-#define TIM17_AF1_BKCMP2P_Msk     (0x1UL << TIM17_AF1_BKCMP2P_Pos)             /*!< 0x00000800 */
-#define TIM17_AF1_BKCMP2P         TIM17_AF1_BKCMP2P_Msk                        /*!<BRK COMP2 input polarity */
-
-/*******************  Bit definition for TIM1_AF2 register  *******************/
-#define TIM1_AF2_BK2INE_Pos       (0U)
-#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */
-#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BRK2 BKIN2 input enable */
-#define TIM1_AF2_BK2CMP1E_Pos     (1U)                                         
-#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
-#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BRK2 COMP1 enable */
-#define TIM1_AF2_BK2CMP2E_Pos     (2U)                                         
-#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
-#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BRK2 COMP2 enable */
-#define TIM1_AF2_BK2INP_Pos       (9U)                                         
-#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */
-#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRK2 BKIN2 input polarity */
-#define TIM1_AF2_BK2CMP1P_Pos     (10U)                                        
-#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
-#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BRK2 COMP1 input polarity */
-#define TIM1_AF2_BK2CMP2P_Pos     (11U)                                        
-#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
-#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BRK2 COMP2 input polarity */
-
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC_COMMON)
-
-/******************************* AES Instances ********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5) || \
-                                       ((INSTANCE) == DMA2_Channel6) || \
-                                       ((INSTANCE) == DMA2_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************* GPIO AF Instances ****************************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************* SMBUS Instances ******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************** HSEM Instances *******************************/
-#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
-
-#define HSEM_CPU1_COREID   (0x00000004U) /* Semaphore Core ID */
-#define HSEM_CPU2_COREID   (0x00000008U) /* Semaphore Core ID */
-
-#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/
-#define HSEM_SEMID_MAX     (15U)      /* HSEM ID Max */
-
-#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */
-#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */
-
-#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */
-#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */
-
-/******************************** PKA Instances *******************************/
-#define IS_PKA_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == PKA)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
-
-/****************************** RTC Instances *********************************/
-#define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SUBGHZSPI))
-
-/******************************** SUBGHZSPI Instances *************************/
-#define IS_SUBGHZ_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SUBGHZSPI)
-#define IS_SUBGHZ_MODULATION_SUPPORTED(COMMAND,PACKET_TYPE)  \
-                                   ((((COMMAND) != RADIO_SET_PACKETTYPE)) || \
-                                    (((COMMAND) == RADIO_SET_PACKETTYPE)  && \
-                                    (((PACKET_TYPE) == 0x00)              || \
-                                     ((PACKET_TYPE) > 0x01 ))))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
-                                         ((INSTANCE) == LPTIM2) || \
-                                         ((INSTANCE) == LPTIM3))
-
-/****************** LPTIM Instances : Encoder mode ****************************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM16)  || \
-                                         ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting 32 bits counter ****************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : supporting the break function *************/
-#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
-                                            ((INSTANCE) == TIM16)   || \
-                                            ((INSTANCE) == TIM17))
-
-/************** TIM Instances : supporting Break source selection *************/
-#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                               ((INSTANCE) == TIM16)  || \
-                                               ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting 2 break inputs *****************/
-#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM16)  || \
-                                         ((INSTANCE) == TIM17))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : at least 5 capture/compare channels *******/
-#define IS_TIM_CC5_INSTANCE(INSTANCE)      ((INSTANCE) == TIM1)
-
-/****************** TIM Instances : at least 6 capture/compare channels *******/
-#define IS_TIM_CC6_INSTANCE(INSTANCE)      ((INSTANCE) == TIM1)
-
-/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/******************* TIM Instances : Timer input selection ********************/
-#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM16)   || \
-                                         ((INSTANCE) == TIM17))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-        ((((INSTANCE) == TIM1) &&                  \
-           (((CHANNEL) == TIM_CHANNEL_1) ||          \
-            ((CHANNEL) == TIM_CHANNEL_2) ||          \
-            ((CHANNEL) == TIM_CHANNEL_3) ||          \
-            ((CHANNEL) == TIM_CHANNEL_4) ||          \
-            ((CHANNEL) == TIM_CHANNEL_5) ||          \
-            ((CHANNEL) == TIM_CHANNEL_6)))           \
-           ||                                        \
-           (((INSTANCE) == TIM2) &&                  \
-           (((CHANNEL) == TIM_CHANNEL_1) ||          \
-            ((CHANNEL) == TIM_CHANNEL_2) ||          \
-            ((CHANNEL) == TIM_CHANNEL_3) ||          \
-            ((CHANNEL) == TIM_CHANNEL_4)))           \
-           ||                                        \
-           (((INSTANCE) == TIM16) &&                 \
-           (((CHANNEL) == TIM_CHANNEL_1)))           \
-           ||                                        \
-           (((INSTANCE) == TIM17) &&                 \
-            (((CHANNEL) == TIM_CHANNEL_1))))
-
-/****************** TIM Instances : supporting complementary output(s) ********/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM17) &&                   \
-     ((CHANNEL) == TIM_CHANNEL_1))              \
-    ||                                          \
-    (((INSTANCE) == TIM16) &&                   \
-     ((CHANNEL) == TIM_CHANNEL_1)))
-
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
-                                                    ((INSTANCE) == TIM2)    || \
-                                                    ((INSTANCE) == TIM16)   || \
-                                                    ((INSTANCE) == TIM17))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
-#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/****************** TIM Instances : supporting commutation event generation ***/
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
-                                                     ((INSTANCE) == TIM16)   || \
-                                                     ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting counting mode selection ********/
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
-                                                      ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting Hall sensor interface **********/
-#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/**************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2))
-
-/************* TIM Instances : supporting ETR source selection ***************/
-#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                             ((INSTANCE) == TIM2))
-
-/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting OCxREF clear *******************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
-                                                       ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM16) || \
-                                            ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting repetition counter *************/
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
-                                                       ((INSTANCE) == TIM16) || \
-                                                       ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
-#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2))
-
-/************ TIM Instances : Advanced timers  ********************************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* USART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/****************** UART Instances : Auto Baud Rate detection ****************/
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : SPI Slave selection mode ***************/
-#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                              ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_FIFO_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
-                                             ((INSTANCE) == USART2) || \
-                                             ((INSTANCE) == LPUART1))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32WLE4xx_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h

@@ -1,9754 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wle5xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex Device Peripheral Access Layer Header File.
-  *          This file contains all the peripheral register's definitions, bits
-  *          definitions and memory mapping for stm32wle5xx devices.
-  *
-  *          This file contains:selected
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2020(-2021) STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32wle5xx
-  * @{
-  */
-
-#ifndef __STM32WLE5xx_H
-#define __STM32WLE5xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-
-
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief stm32wle5xx Interrupt Number Definition, according to the selected device
- *        in @ref Library_configuration_section
- */
-/*!< Interrupt Number Definition for M4 */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn                 = -14,    /*!< Non Maskable Interrupt                                            */
-  HardFault_IRQn                      = -13,    /*!< Cortex-M4 Hard Fault Interrupt                                    */
-  MemoryManagement_IRQn               = -12,    /*!< Cortex-M4 Memory Management Interrupt                             */
-  BusFault_IRQn                       = -11,    /*!< Cortex-M4 Bus Fault Interrupt                                     */
-  UsageFault_IRQn                     = -10,    /*!< Cortex-M4 Usage Fault Interrupt                                   */
-  SVCall_IRQn                         = -5,     /*!< Cortex-M4 SV Call Interrupt                                       */
-  DebugMonitor_IRQn                   = -4,     /*!< Cortex-M4 Debug Monitor Interrupt                                 */
-  PendSV_IRQn                         = -2,     /*!< Cortex-M4 Pend SV Interrupt                                       */
-  SysTick_IRQn                        = -1,     /*!< Cortex-M4 System Tick Interrupt                                   */
-
-/*************  STM32WLxx specific Interrupt Numbers on M4 core ************************************************/
-  WWDG_IRQn                           = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_PVM_IRQn                        = 1,      /*!< PVD and PVM detector                                              */
-  TAMP_STAMP_LSECSS_SSRU_IRQn         = 2,      /*!< RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts         */
-  RTC_WKUP_IRQn                       = 3,      /*!< RTC Wakeup Interrupt                                              */
-  FLASH_IRQn                          = 4,      /*!< FLASH (CFI)  global Interrupt                                     */
-  RCC_IRQn                            = 5,      /*!< RCC Interrupt                                                     */
-  EXTI0_IRQn                          = 6,      /*!< EXTI Line 0 Interrupt                                             */
-  EXTI1_IRQn                          = 7,      /*!< EXTI Line 1 Interrupt                                             */
-  EXTI2_IRQn                          = 8,      /*!< EXTI Line 2 Interrupt                                             */
-  EXTI3_IRQn                          = 9,      /*!< EXTI Line 3 Interrupt                                             */
-  EXTI4_IRQn                          = 10,     /*!< EXTI Line 4 Interrupt                                             */
-  DMA1_Channel1_IRQn                  = 11,     /*!< DMA1 Channel 1 Interrupt                                          */
-  DMA1_Channel2_IRQn                  = 12,     /*!< DMA1 Channel 2 Interrupt                                          */
-  DMA1_Channel3_IRQn                  = 13,     /*!< DMA1 Channel 3 Interrupt                                          */
-  DMA1_Channel4_IRQn                  = 14,     /*!< DMA1 Channel 4 Interrupt                                          */
-  DMA1_Channel5_IRQn                  = 15,     /*!< DMA1 Channel 5 Interrupt                                          */
-  DMA1_Channel6_IRQn                  = 16,     /*!< DMA1 Channel 6 Interrupt                                          */
-  DMA1_Channel7_IRQn                  = 17,     /*!< DMA1 Channel 7 Interrupt                                          */
-  ADC_IRQn                            = 18,     /*!< ADC Interrupt                                                     */
-  DAC_IRQn                            = 19,     /*!< DAC Interrupt                                                     */
-  COMP_IRQn                           = 21,     /*!< COMP1 and COMP2 Interrupts                                        */
-  EXTI9_5_IRQn                        = 22,     /*!< EXTI Lines [9:5] Interrupt                                        */
-  TIM1_BRK_IRQn                       = 23,     /*!< TIM1 Break Interrupt                                              */
-  TIM1_UP_IRQn                        = 24,     /*!< TIM1 Update Interrupt                                             */
-  TIM1_TRG_COM_IRQn                   = 25,     /*!< TIM1 Trigger and Communication Interrupts                         */
-  TIM1_CC_IRQn                        = 26,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                           = 27,     /*!< TIM2 Global Interrupt                                             */
-  TIM16_IRQn                          = 28,     /*!< TIM16 Global Interrupt                                            */
-  TIM17_IRQn                          = 29,     /*!< TIM17 Global Interrupt                                            */
-  I2C1_EV_IRQn                        = 30,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                        = 31,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                        = 32,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                        = 33,     /*!< I2C2 Error Interrupt                                              */
-  SPI1_IRQn                           = 34,     /*!< SPI1 Interrupt                                                    */
-  SPI2_IRQn                           = 35,     /*!< SPI2 Interrupt                                                    */
-  USART1_IRQn                         = 36,     /*!< USART1 Interrupt                                                  */
-  USART2_IRQn                         = 37,     /*!< USART2 Interrupt                                                  */
-  LPUART1_IRQn                        = 38,     /*!< LPUART1 Interrupt                                                 */
-  LPTIM1_IRQn                         = 39,     /*!< LPTIM1 Global Interrupt                                           */
-  LPTIM2_IRQn                         = 40,     /*!< LPTIM2 Global Interrupt                                           */
-  EXTI15_10_IRQn                      = 41,     /*!< EXTI Lines [15:10] Interrupt                                      */
-  RTC_Alarm_IRQn                      = 42,     /*!< RTC Alarms (A and B) Interrupt                                    */
-  LPTIM3_IRQn                         = 43,     /*!< LPTIM3 Global Interrupt                                           */
-  SUBGHZSPI_IRQn                      = 44,     /*!< SUBGHZSPI Interrupt                                               */
-  HSEM_IRQn                           = 47,     /*!< HSEM Interrupt                                                    */
-  I2C3_EV_IRQn                        = 48,     /*!< I2C3 Event Interrupt                                              */
-  I2C3_ER_IRQn                        = 49,     /*!< I2C3 Error Interrupt                                              */
-  SUBGHZ_Radio_IRQn                   = 50,     /*!< SUBGHZ Radio Interrupt                                            */
-  AES_IRQn                            = 51,     /*!< AES Interrupt                                                     */
-  RNG_IRQn                            = 52,     /*!< RNG Interrupt                                                     */
-  PKA_IRQn                            = 53,     /*!< PKA Interrupt                                                     */
-  DMA2_Channel1_IRQn                  = 54,     /*!< DMA2 Channel 1 Interrupt                                          */
-  DMA2_Channel2_IRQn                  = 55,     /*!< DMA2 Channel 2 Interrupt                                          */
-  DMA2_Channel3_IRQn                  = 56,     /*!< DMA2 Channel 3 Interrupt                                          */
-  DMA2_Channel4_IRQn                  = 57,     /*!< DMA2 Channel 4 Interrupt                                          */
-  DMA2_Channel5_IRQn                  = 58,     /*!< DMA2 Channel 5 Interrupt                                          */
-  DMA2_Channel6_IRQn                  = 59,     /*!< DMA2 Channel 6 Interrupt                                          */
-  DMA2_Channel7_IRQn                  = 60,     /*!< DMA2 Channel 7 Interrupt                                          */
-  DMAMUX1_OVR_IRQn                    = 61      /*!< DMAMUX1 overrun Interrupt                                         */
-} IRQn_Type;
-/**
-  * @}
-  */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
-  */
-#define __CM4_REV                 1U /*!< Core Revision r0p1                            */
-#define __MPU_PRESENT             1U /*!< M4 provides an MPU                            */
-#define __VTOR_PRESENT            1U /*!< Vector Table Register supported               */
-#define __NVIC_PRIO_BITS          4U /*!< STM32WLxx uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             0U /*!< FPU not present                                   */
-
-#include "core_cm4.h"                /* Cortex-M4 processor and core peripherals */
-
-
-#include "system_stm32wlxx.h"
-#include <stdint.h>
-
-/**
-  * @}
-  */
-
-
-
-
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */
-
-/**
-  * @brief Analog to Digital Converter
-  */
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC interrupt and status register,             Address offset: 0x00 */
-  __IO uint32_t IER;          /*!< ADC interrupt enable register,                 Address offset: 0x04 */
-  __IO uint32_t CR;           /*!< ADC control register,                          Address offset: 0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC configuration register 1,                  Address offset: 0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC configuration register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR;         /*!< ADC sampling time register,                    Address offset: 0x14 */
-       uint32_t RESERVED1;    /*!< Reserved,                                                      0x18 */
-       uint32_t RESERVED2;    /*!< Reserved,                                                      0x1C */
-  __IO uint32_t TR1;          /*!< ADC analog watchdog 1 threshold register,      Address offset: 0x20 */
-  __IO uint32_t TR2;          /*!< ADC analog watchdog 2 threshold register,      Address offset: 0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC group regular sequencer register,          Address offset: 0x28 */
-  __IO uint32_t TR3;          /*!< ADC analog watchdog 3 threshold register,      Address offset: 0x2C */
-       uint32_t RESERVED3[4]; /*!< Reserved,                                               0x30 - 0x3C */
-  __IO uint32_t DR;           /*!< ADC group regular data register,               Address offset: 0x40 */
-       uint32_t RESERVED4[23];/*!< Reserved,                                               0x44 - 0x9C */
-  __IO uint32_t AWD2CR;       /*!< ADC analog watchdog 2 configuration register,  Address offset: 0xA0 */
-  __IO uint32_t AWD3CR;       /*!< ADC analog watchdog 3 configuration register,  Address offset: 0xA4 */
-       uint32_t RESERVED5[3]; /*!< Reserved,                                               0xA8 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC Calibration factor register,               Address offset: 0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< ADC common configuration register,             Address offset: ADC base address + 0x308 */
-} ADC_Common_TypeDef;
-
-/**
-  * @brief AES hardware accelerator
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< AES control register,                        Address offset: 0x00 */
-  __IO uint32_t SR;          /*!< AES status register,                         Address offset: 0x04 */
-  __IO uint32_t DINR;        /*!< AES data input register,                     Address offset: 0x08 */
-  __IO uint32_t DOUTR;       /*!< AES data output register,                    Address offset: 0x0C */
-  __IO uint32_t KEYR0;       /*!< AES key register 0,                          Address offset: 0x10 */
-  __IO uint32_t KEYR1;       /*!< AES key register 1,                          Address offset: 0x14 */
-  __IO uint32_t KEYR2;       /*!< AES key register 2,                          Address offset: 0x18 */
-  __IO uint32_t KEYR3;       /*!< AES key register 3,                          Address offset: 0x1C */
-  __IO uint32_t IVR0;        /*!< AES initialization vector register 0,        Address offset: 0x20 */
-  __IO uint32_t IVR1;        /*!< AES initialization vector register 1,        Address offset: 0x24 */
-  __IO uint32_t IVR2;        /*!< AES initialization vector register 2,        Address offset: 0x28 */
-  __IO uint32_t IVR3;        /*!< AES initialization vector register 3,        Address offset: 0x2C */
-  __IO uint32_t KEYR4;       /*!< AES key register 4,                          Address offset: 0x30 */
-  __IO uint32_t KEYR5;       /*!< AES key register 5,                          Address offset: 0x34 */
-  __IO uint32_t KEYR6;       /*!< AES key register 6,                          Address offset: 0x38 */
-  __IO uint32_t KEYR7;       /*!< AES key register 7,                          Address offset: 0x3C */
-  __IO uint32_t SUSP0R;      /*!< AES Suspend register 0,                      Address offset: 0x40 */
-  __IO uint32_t SUSP1R;      /*!< AES Suspend register 1,                      Address offset: 0x44 */
-  __IO uint32_t SUSP2R;      /*!< AES Suspend register 2,                      Address offset: 0x48 */
-  __IO uint32_t SUSP3R;      /*!< AES Suspend register 3,                      Address offset: 0x4C */
-  __IO uint32_t SUSP4R;      /*!< AES Suspend register 4,                      Address offset: 0x50 */
-  __IO uint32_t SUSP5R;      /*!< AES Suspend register 5,                      Address offset: 0x54 */
-  __IO uint32_t SUSP6R;      /*!< AES Suspend register 6,                      Address offset: 0x58 */
-  __IO uint32_t SUSP7R;      /*!< AES Suspend register 7,                      Address offset: 0x6C */
-} AES_TypeDef;
-
-/**
-  * @brief Comparator
-  */
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register,               Address offset: 0x00 */
-} COMP_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
-} COMP_Common_TypeDef;
-
-/**
-  * @brief CRC calculation unit
-  */
-typedef struct
-{
-  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */
-  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
-       uint32_t RESERVED2;   /*!< Reserved,                                                    0x0C */
-  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
-  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Digital to Analog Converter
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;     /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-       uint32_t RESERVED1;   /*!< Reserved                                                 Address offset: 0x14 */
-       uint32_t RESERVED2;   /*!< Reserved                                                 Address offset: 0x18 */
-       uint32_t RESERVED3;   /*!< Reserved                                                 Address offset: 0x1C */
-  __IO uint32_t DHR12RD;     /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;     /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;      /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;        /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-       uint32_t RESERVED4;   /*!< Reserved                                                 Address offset: 0x30 */
-  __IO uint32_t SR;          /*!< DAC status register,                                     Address offset: 0x34 */
-  __IO uint32_t CCR;         /*!< DAC calibration control register,                        Address offset: 0x38 */
-  __IO uint32_t MCR;         /*!< DAC mode control register,                               Address offset: 0x3C */
-  __IO uint32_t SHSR1;       /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */
-       uint32_t RESERVED5;   /*!< Reserved                                                 Address offset: 0x44 */
-  __IO uint32_t SHHR;        /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */
-  __IO uint32_t SHRR;        /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */
-} DAC_TypeDef;
-
-/**
-  * @brief Debug MCU
-  */
-typedef struct
-{
-  __IO uint32_t IDCODE;      /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;          /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  uint32_t RESERVED1[13];    /*!< Reserved,                                               0x08-0x38 */
-  __IO uint32_t APB1FZR1;    /*!< Debug MCU CPU1 APB1 freeze register,         Address offset: 0x3C */
-  uint32_t RESERVED2;        /*!< Reserved,                                    Address offset: 0x40 */
-  __IO uint32_t APB1FZR2;    /*!< Debug MCU CPU1 APB1 freeze register,         Address offset: 0x44 */
-  uint32_t RESERVED3;        /*!< Reserved,                                    Address offset: 0x48 */
-  __IO uint32_t APB2FZR;     /*!< Debug MCU CPU1 APB2 freeze register,         Address offset: 0x4C */
-} DBGMCU_TypeDef;
-
-/**
-  * @brief DMA Controller
-  */
-typedef struct
-{
-  __IO uint32_t CCR;         /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;       /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;        /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;        /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;         /*!< DMA interrupt status register,                 Address offset: 0x00 */
-  __IO uint32_t IFCR;        /*!< DMA interrupt flag clear register,             Address offset: 0x04 */
-} DMA_TypeDef;
-
-/**
-  * @brief DMA Multiplexer
-  */
-typedef struct
-{
-  __IO uint32_t   CCR;       /*!< DMA Multiplexer Channel x Control Register    Address offset: 0x0004 * (channel x) */
-}DMAMUX_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t   CSR;       /*!< DMA Channel Status Register                    Address offset: 0x0080   */
-  __IO uint32_t   CFR;       /*!< DMA Channel Clear Flag Register                Address offset: 0x0084   */
-}DMAMUX_ChannelStatus_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t   RGCR;        /*!< DMA Request Generator x Control Register     Address offset: 0x0100 + 0x0004 * (Req Gen x) */
-}DMAMUX_RequestGen_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t   RGSR;        /*!< DMA Request Generator Status Register        Address offset: 0x0140   */
-  __IO uint32_t   RGCFR;       /*!< DMA Request Generator Clear Flag Register    Address offset: 0x0144   */
-}DMAMUX_RequestGenStatus_TypeDef;
-
-/**
-  * @brief Async Interrupts and Events Controller
-  */
-typedef struct
-{
-  __IO uint32_t RTSR1;          /*!< EXTI rising trigger selection register [31:0],            Address offset: 0x00 */
-  __IO uint32_t FTSR1;          /*!< EXTI falling trigger selection register [31:0],           Address offset: 0x04 */
-  __IO uint32_t SWIER1;         /*!< EXTI software interrupt event register [31:0],            Address offset: 0x08 */
-  __IO uint32_t PR1;            /*!< EXTI pending register [31:0],                             Address offset: 0x0C */
-  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                                 Address offset: 0x10 - 0x1C */
-  __IO uint32_t RTSR2;          /*!< EXTI rising trigger selection register [31:0],            Address offset: 0x20 */
-  __IO uint32_t FTSR2;          /*!< EXTI falling trigger selection register [31:0],           Address offset: 0x24 */
-  __IO uint32_t SWIER2;         /*!< EXTI software interrupt event register [31:0],            Address offset: 0x28 */
-  __IO uint32_t PR2;            /*!< EXTI pending register [31:0],                             Address offset: 0x2C */
-  __IO uint32_t RESERVED2[4];   /*!< Reserved,                                                 Address offset: 0x30 - 0x3C */
-  __IO uint32_t RESERVED3[8];   /*!< Reserved,                                                 Address offset: 0x40 - 0x5C */
-  __IO uint32_t RESERVED4[8];   /*!< Reserved,                                                 Address offset: 0x60 - 0x7C */
-  __IO uint32_t IMR1;           /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x80 */
-  __IO uint32_t EMR1;           /*!< EXTI wakeup with event mask register for cpu1 [31:0],     Address offset: 0x84 */
-  __IO uint32_t RESERVED5[2];   /*!< Reserved,                                                 Address offset: 0x88 - 0x8C */
-  __IO uint32_t IMR2;           /*!< EXTI wakeup with interrupt mask register for cpu1 [31:0], Address offset: 0x90 */
-  __IO uint32_t EMR2;           /*!< EXTI wakeup with event mask register for cpu1 [31:0],     Address offset: 0x94 */
-}EXTI_TypeDef;
-
-/**
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< FLASH Access control register,                      Address offset: 0x00      */
-  uint32_t RESERVED0;          /*!< Reserved,                                           Address offset: 0x04      */
-  __IO uint32_t KEYR;          /*!< FLASH Key register,                                 Address offset: 0x08      */
-  __IO uint32_t OPTKEYR;       /*!< FLASH Option Key register,                          Address offset: 0x0C      */
-  __IO uint32_t SR;            /*!< FLASH Status register,                              Address offset: 0x10      */
-  __IO uint32_t CR;            /*!< FLASH Control register,                             Address offset: 0x14      */
-  __IO uint32_t ECCR;          /*!< FLASH ECC register,                                 Address offset: 0x18      */
-  uint32_t RESERVED1;          /*!< Reserved,                                           Address offset: 0x1C      */
-  __IO uint32_t OPTR;          /*!< FLASH Option register,                              Address offset: 0x20      */
-  __IO uint32_t PCROP1ASR;     /*!< FLASH Bank 1 PCROP area A Start address register,   Address offset: 0x24      */
-  __IO uint32_t PCROP1AER;     /*!< FLASH Bank 1 PCROP area A End address register,     Address offset: 0x28      */
-  __IO uint32_t WRP1AR;        /*!< FLASH Bank 1 WRP area A address register,           Address offset: 0x2C      */
-  __IO uint32_t WRP1BR;        /*!< FLASH Bank 1 WRP area B address register,           Address offset: 0x30      */
-  __IO uint32_t PCROP1BSR;     /*!< FLASH Bank 1 PCROP area B Start address register,   Address offset: 0x34      */
-  __IO uint32_t PCROP1BER;     /*!< FLASH Bank 1 PCROP area B End address register,     Address offset: 0x38      */
-} FLASH_TypeDef;
-
-/**
-  * @brief General Purpose I/O
-  */
-typedef struct
-{
-  __IO uint32_t MODER;       /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;      /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;     /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;       /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;         /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;         /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;        /*!< GPIO port bit set/reset  register,     Address offset: 0x18      */
-  __IO uint32_t LCKR;        /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];      /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;         /*!< GPIO Bit Reset register,               Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/**
-  * @brief HW Semaphore HSEM
-  */
-typedef struct
-{
-  __IO uint32_t R[16];      /*!< HSEM 2-step write lock and read back registers, Address offset: 00h-3Ch  */
-   uint32_t  Reserved1[16]; /*!< Reserved                                        Address offset: 40h-7Ch  */
-  __IO uint32_t RLR[16];    /*!< HSEM 1-step read lock registers,                Address offset: 80h-BCh  */
-   uint32_t  Reserved2[16]; /*!< Reserved                                        Address offset: C0h-FCh  */
-  __IO uint32_t C1IER;      /*!< HSEM CPU1 interrupt enable register ,           Address offset: 100h     */
-  __IO uint32_t C1ICR;      /*!< HSEM CPU1 interrupt clear register ,            Address offset: 104h     */
-  __IO uint32_t C1ISR;      /*!< HSEM CPU1 interrupt status register ,           Address offset: 108h     */
-  __IO uint32_t C1MISR;     /*!< HSEM CPU1 masked interrupt status register ,    Address offset: 10Ch     */
-   uint32_t  Reserved[12];  /*!< Reserved                                        Address offset: 110h-13Ch*/
-  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                 Address offset: 140h     */
-  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,             Address offset: 144h     */
-} HSEM_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */
-  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */
-  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */
-  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */
-} HSEM_Common_TypeDef;
-
-/**
-  * @brief Inter-integrated Circuit Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;        /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;        /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;     /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR;    /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;         /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;         /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;        /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;        /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;        /*!< I2C Transmit data register,        Address offset: 0x28 */
-} I2C_TypeDef;
-
-/**
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;          /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;          /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;         /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;          /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR;        /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/**
-  * @brief LPTIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;         /*!< LPTIM Interrupt and Status register,                Address offset: 0x00 */
-  __IO uint32_t ICR;         /*!< LPTIM Interrupt Clear register,                     Address offset: 0x04 */
-  __IO uint32_t IER;         /*!< LPTIM Interrupt Enable register,                    Address offset: 0x08 */
-  __IO uint32_t CFGR;        /*!< LPTIM Configuration register,                       Address offset: 0x0C */
-  __IO uint32_t CR;          /*!< LPTIM Control register,                             Address offset: 0x10 */
-  __IO uint32_t CMP;         /*!< LPTIM Compare register,                             Address offset: 0x14 */
-  __IO uint32_t ARR;         /*!< LPTIM Autoreload register,                          Address offset: 0x18 */
-  __IO uint32_t CNT;         /*!< LPTIM Counter register,                             Address offset: 0x1C */
-  __IO uint32_t OR;          /*!< LPTIM Option register,                              Address offset: 0x20 */
-  __IO uint32_t RESERVED;    /*!< Reserved,                                           Address offset: 0x24 */
-  __IO uint32_t RCR;         /*!< LPTIM repetition register,                          Address offset: 0x28 */
-} LPTIM_TypeDef;
-
-/**
-  * @brief Public Key Accelerator (PKA)
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< PKA control register,                 Address offset: 0x00 */
-  __IO uint32_t SR;          /*!< PKA status register,                  Address offset: 0x04 */
-  __IO uint32_t CLRFR;       /*!< PKA clear flag register,              Address offset: 0x08 */
-  uint32_t  Reserved1[253];  /*!< Reserved                              Address offset: 0x000C-0x03FC*/
-  __IO uint32_t RAM[894];    /*!< PKA RAM,                              Address offset: 0x0400-0x11F4 */
-} PKA_TypeDef;
-
-/**
-  * @brief Power Control
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< PWR Power Control Register 1,                     Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< PWR Power Control Register 2,                     Address offset: 0x04 */
-  __IO uint32_t CR3;          /*!< PWR Power Control Register 3,                     Address offset: 0x08 */
-  __IO uint32_t CR4;          /*!< PWR Power Control Register 4,                     Address offset: 0x0C */
-  __IO uint32_t SR1;          /*!< PWR Power Status Register 1,                      Address offset: 0x10 */
-  __IO uint32_t SR2;          /*!< PWR Power Status Register 2,                      Address offset: 0x14 */
-  __IO uint32_t SCR;          /*!< PWR Power Status Reset Register,                  Address offset: 0x18 */
-  __IO uint32_t CR5;          /*!< PWR Power Control Register 5,                     Address offset: 0x1C */
-  __IO uint32_t PUCRA;        /*!< PWR Pull-Up Control Register of port A,           Address offset: 0x20 */
-  __IO uint32_t PDCRA;        /*!< PWR Pull-Down Control Register of port A,         Address offset: 0x24 */
-  __IO uint32_t PUCRB;        /*!< PWR Pull-Up Control Register of port B,           Address offset: 0x28 */
-  __IO uint32_t PDCRB;        /*!< PWR Pull-Down Control Register of port B,         Address offset: 0x2C */
-  __IO uint32_t PUCRC;        /*!< PWR Pull-Up Control Register of port C,           Address offset: 0x30 */
-  __IO uint32_t PDCRC;        /*!< PWR Pull-Down Control Register of port C,         Address offset: 0x34 */
-       uint32_t RESERVED0[8]; /*!< Reserved,                                         Address offset: 0x38-0x54 */
-  __IO uint32_t PUCRH;        /*!< PWR Pull-Up Control Register of port H,           Address offset: 0x58 */
-  __IO uint32_t PDCRH;        /*!< PWR Pull-Down Control Register of port H,         Address offset: 0x5C */
-       uint32_t RESERVED1[10];/*!< Reserved,                                         Address offset: 0x60-0x84 */
-  __IO uint32_t EXTSCR;       /*!< PWR Power Status Reset Register for CPU2,         Address offset: 0x88 */
-       uint32_t RESERVED2;    /*!< Reserved,                                         Address offset: 0x8C */
-  __IO uint32_t SUBGHZSPICR;  /*!< PWR SUBGHZSPI Control Register,                   Address offset: 0x90 */
-} PWR_TypeDef;
-
-/**
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;           /*!< RCC clock  Control Register,                                                    Address offset: 0x00 */
-  __IO uint32_t ICSCR;        /*!< RCC Internal Clock Sources Calibration Register,                                Address offset: 0x04 */
-  __IO uint32_t CFGR;         /*!< RCC Clocks Configuration Register,                                              Address offset: 0x08 */
-  __IO uint32_t PLLCFGR;      /*!< RCC System PLL configuration Register,                                          Address offset: 0x0C */
-uint32_t RESERVED0;           /*!< Reserved,                                                                       Address offset: 0x10 */
-uint32_t RESERVED1;           /*!< Reserved,                                                                       Address offset: 0x14 */
-  __IO uint32_t CIER;         /*!< RCC Clock Interrupt Enable Register,                                            Address offset: 0x18 */
-  __IO uint32_t CIFR;         /*!< RCC Clock Interrupt Flag Register,                                              Address offset: 0x1C */
-  __IO uint32_t CICR;         /*!< RCC Clock Interrupt Clear Register,                                             Address offset: 0x20 */
-uint32_t RESERVED2;           /*!< Reserved,                                                                       Address offset: 0x24 */
-  __IO uint32_t AHB1RSTR;     /*!< RCC AHB1 peripheral reset register,                                             Address offset: 0x28 */
-  __IO uint32_t AHB2RSTR;     /*!< RCC AHB2 peripheral reset register,                                             Address offset: 0x2C */
-  __IO uint32_t AHB3RSTR;     /*!< RCC AHB3 peripheral reset register,                                             Address offset: 0x30 */
-uint32_t RESERVED3;           /*!< Reserved,                                                                       Address offset: 0x34 */
-  __IO uint32_t APB1RSTR1;    /*!< RCC APB1 peripheral reset register 1,                                           Address offset: 0x38 */
-  __IO uint32_t APB1RSTR2;    /*!< RCC APB1 peripheral reset register 2,                                           Address offset: 0x3C */
-  __IO uint32_t APB2RSTR;     /*!< RCC APB2 peripheral reset register,                                             Address offset: 0x40 */
-  __IO uint32_t APB3RSTR;     /*!< RCC APB3 peripheral reset register,                                             Address offset: 0x44 */
-  __IO uint32_t AHB1ENR;      /*!< RCC AHB1 peripheral clocks enable register,                                     Address offset: 0x48 */
-  __IO uint32_t AHB2ENR;      /*!< RCC AHB2 peripheral clocks enable register,                                     Address offset: 0x4C */
-  __IO uint32_t AHB3ENR;      /*!< RCC AHB3 peripheral clocks enable register,                                     Address offset: 0x50 */
-uint32_t RESERVED4;           /*!< Reserved,                                                                       Address offset: 0x54 */
-  __IO uint32_t APB1ENR1;     /*!< RCC APB1 peripheral clocks enable register 1,                                   Address offset: 0x58 */
-  __IO uint32_t APB1ENR2;     /*!< RCC APB1 peripheral clocks enable register 2,                                   Address offset: 0x5C */
-  __IO uint32_t APB2ENR;      /*!< RCC APB2 peripheral clocks enable register,                                     Address offset: 0x60 */
-  __IO uint32_t APB3ENR;      /*!< RCC APB3 peripheral clocks enable register,                                     Address offset: 0x64 */
-  __IO uint32_t AHB1SMENR;    /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register,             Address offset: 0x68 */
-  __IO uint32_t AHB2SMENR;    /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register,             Address offset: 0x6C */
-  __IO uint32_t AHB3SMENR;    /*!< RCC AHB3 & AHB4 peripheral clocks enable in sleep and stop modes register,      Address offset: 0x70 */
-uint32_t RESERVED5;           /*!< Reserved,                                                                       Address offset: 0x74 */
-  __IO uint32_t APB1SMENR1;   /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1,      Address offset: 0x78 */
-  __IO uint32_t APB1SMENR2;   /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2,      Address offset: 0x7C */
-  __IO uint32_t APB2SMENR;    /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register,        Address offset: 0x80 */
-  __IO uint32_t APB3SMENR;    /*!< RCC APB3 peripheral clocks enable in sleep mode and stop modes register,        Address offset: 0x84 */
-  __IO uint32_t CCIPR;        /*!< RCC Peripherals Clock Configuration Independent Register,                       Address offset: 0x88 */
-uint32_t RESERVED6;           /*!< Reserved,                                                                       Address offset: 0x8C */
-  __IO uint32_t BDCR;         /*!< RCC Backup Domain Control Register,                                             Address offset: 0x90 */
-  __IO uint32_t CSR;          /*!< RCC Control and Status Register,                                                Address offset: 0x94 */
-uint32_t RESERVED7[28];       /*!< Reserved,                                                                       Address offset: 0x98-0x104 */
-  __IO uint32_t EXTCFGR;      /*!< RCC Extended Clock Recovery Register,                                           Address offset: 0x108 */
-} RCC_TypeDef;
-
-/**
-  * @brief RNG
-  */
-typedef struct
-{
-  __IO uint32_t CR;        /*!< RNG control register,             Address offset: 0x00 */
-  __IO uint32_t SR;        /*!< RNG status register,              Address offset: 0x04 */
-  __IO uint32_t DR;        /*!< RNG data register,                Address offset: 0x08 */
-  uint32_t      RESERVED0; /*!< Reserved,                         Address offset: 0x0C */
-  __IO uint32_t HTCR;      /*!< RNG health test control register, Address offset: 0x10 */
-} RNG_TypeDef;
-
-/**
-  * @brief RTC Specific device feature definitions
-  */
-#define RTC_BACKUP_NB       20u
-#define RTC_TAMP_NB         3u
-
-/**
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;          /*!< RTC time register,                              Address offset: 0x00 */
-  __IO uint32_t DR;          /*!< RTC date register,                              Address offset: 0x04 */
-  __IO uint32_t SSR;         /*!< RTC sub second register,                        Address offset: 0x08 */
-  __IO uint32_t ICSR;        /*!< RTC initialization control and status register, Address offset: 0x0C */
-  __IO uint32_t PRER;        /*!< RTC prescaler register,                         Address offset: 0x10 */
-  __IO uint32_t WUTR;        /*!< RTC wakeup timer register,                      Address offset: 0x14 */
-  __IO uint32_t CR;          /*!< RTC control register,                           Address offset: 0x18 */
-       uint32_t RESERVED0;   /*!< Reserved,                                       Address offset: 0x1C */
-       uint32_t RESERVED1;   /*!< Reserved,                                       Address offset: 0x20 */
-  __IO uint32_t WPR;         /*!< RTC write protection register,                  Address offset: 0x24 */
-  __IO uint32_t CALR;        /*!< RTC calibration register,                       Address offset: 0x28 */
-  __IO uint32_t SHIFTR;      /*!< RTC shift control register,                     Address offset: 0x2C */
-  __IO uint32_t TSTR;        /*!< RTC time stamp time register,                   Address offset: 0x30 */
-  __IO uint32_t TSDR;        /*!< RTC time stamp date register,                   Address offset: 0x34 */
-  __IO uint32_t TSSSR;       /*!< RTC time-stamp sub second register,             Address offset: 0x38 */
-       uint32_t RESERVED2;   /*!< Reserved,                                       Address offset: 0x3C */
-  __IO uint32_t ALRMAR;      /*!< RTC alarm A register,                           Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;    /*!< RTC alarm A sub second register,                Address offset: 0x44 */
-  __IO uint32_t ALRMBR;      /*!< RTC alarm B register,                           Address offset: 0x48 */
-  __IO uint32_t ALRMBSSR;    /*!< RTC alarm B sub second register,                Address offset: 0x4C */
-  __IO uint32_t SR;          /*!< RTC Status register,                            Address offset: 0x50 */
-  __IO uint32_t MISR;        /*!< RTC masked interrupt status register,           Address offset: 0x54 */
-       uint32_t RESERVED3;   /*!< Reserved,                                       Address offset: 0x58 */
-  __IO uint32_t SCR;         /*!< RTC status Clear register,                      Address offset: 0x5C */
-       uint32_t RESERVED4[4];/*!< Reserved,                                       Address offset: 0x58 */
-  __IO uint32_t ALRABINR;/*!< RTC alarm A binary mode register,                   Address offset: 0x70 */
-  __IO uint32_t ALRBBINR;/*!< RTC alarm B binary mode register,                   Address offset: 0x74 */
-} RTC_TypeDef;
-
-/**
-  * @brief Serial Peripheral Interface
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/**
-  * @brief System configuration controller
-  */
-typedef struct
-{
-  __IO uint32_t MEMRMP;            /*!< SYSCFG memory remap register                                            Address offset: 0x00       */
-  __IO uint32_t CFGR1;             /*!< SYSCFG configuration register 1,                                        Address offset: 0x04       */
-  __IO uint32_t EXTICR[4];         /*!< SYSCFG external interrupt configuration registers,                      Address offset: 0x08-0x14  */
-  __IO uint32_t SCSR;              /*!< SYSCFG SRAM2 control and status register,                               Address offset: 0x18       */
-  __IO uint32_t CFGR2;             /*!< SYSCFG configuration register 2,                                        Address offset: 0x1C       */
-  __IO uint32_t SWPR;              /*!< SYSCFG SRAM2 write protection register part,                            Address offset: 0x20       */
-  __IO uint32_t SKR;               /*!< SYSCFG SRAM2 key register,                                              Address offset: 0x24       */
-       uint32_t RESERVED1[120];    /*!< Reserved,                                                               Address offset: 0x28-0x204 */
-  __IO uint32_t RFDCR;             /*!< SYSCFG CPU2 radio debug control register,                               Address offset: 0x208      */
-} SYSCFG_TypeDef;
-
-/**
-  * @brief Tamper and backup registers
-  */
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TAMP configuration register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TAMP configuration register 2,            Address offset: 0x04 */
-  __IO uint32_t CR3;         /*!< TAMP configuration register 3,            Address offset: 0x08 */
-  __IO uint32_t FLTCR;       /*!< TAMP filter control register,             Address offset: 0x0C */
-       uint32_t RESERVED0[7];/*!< Reserved,                                 Address offset: 0x10 */
-  __IO uint32_t IER;         /*!< TAMP interrupt enable register,           Address offset: 0x2C */
-  __IO uint32_t SR;          /*!< TAMP status register,                     Address offset: 0x30 */
-  __IO uint32_t MISR;        /*!< TAMP masked interrupt status register,    Address offset: 0x34 */
-       uint32_t RESERVED1;   /*!< Reserved,                                 Address offset: 0x38 */
-  __IO uint32_t SCR;         /*!< TAMP status clear register,               Address offset: 0x3C */
-  __IO uint32_t COUNTR;      /*!< TAMP monotonic counter register,          Address offset: 0x40 */
-       uint32_t RESERVED2[47];/*!< Reserved,                                Address offset: 0x54 -- 0xFC */
-  __IO uint32_t BKP0R;       /*!< TAMP backup register 0,                   Address offset: 0x100 */
-  __IO uint32_t BKP1R;       /*!< TAMP backup register 1,                   Address offset: 0x104 */
-  __IO uint32_t BKP2R;       /*!< TAMP backup register 2,                   Address offset: 0x108 */
-  __IO uint32_t BKP3R;       /*!< TAMP backup register 3,                   Address offset: 0x10C */
-  __IO uint32_t BKP4R;       /*!< TAMP backup register 4,                   Address offset: 0x110 */
-  __IO uint32_t BKP5R;       /*!< TAMP backup register 5,                   Address offset: 0x114 */
-  __IO uint32_t BKP6R;       /*!< TAMP backup register 6,                   Address offset: 0x118 */
-  __IO uint32_t BKP7R;       /*!< TAMP backup register 7,                   Address offset: 0x11C */
-  __IO uint32_t BKP8R;       /*!< TAMP backup register 8,                   Address offset: 0x120 */
-  __IO uint32_t BKP9R;       /*!< TAMP backup register 9,                   Address offset: 0x124 */
-  __IO uint32_t BKP10R;      /*!< TAMP backup register 10,                  Address offset: 0x128 */
-  __IO uint32_t BKP11R;      /*!< TAMP backup register 11,                  Address offset: 0x12C */
-  __IO uint32_t BKP12R;      /*!< TAMP backup register 12,                  Address offset: 0x130 */
-  __IO uint32_t BKP13R;      /*!< TAMP backup register 13,                  Address offset: 0x134 */
-  __IO uint32_t BKP14R;      /*!< TAMP backup register 14,                  Address offset: 0x138 */
-  __IO uint32_t BKP15R;      /*!< TAMP backup register 15,                  Address offset: 0x13C */
-  __IO uint32_t BKP16R;      /*!< TAMP backup register 16,                  Address offset: 0x140 */
-  __IO uint32_t BKP17R;      /*!< TAMP backup register 17,                  Address offset: 0x144 */
-  __IO uint32_t BKP18R;      /*!< TAMP backup register 18,                  Address offset: 0x148 */
-  __IO uint32_t BKP19R;      /*!< TAMP backup register 19,                  Address offset: 0x14C */
-} TAMP_TypeDef;
-
-/**
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler register,                   Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */
-  __IO uint32_t OR1;         /*!< TIM option register                       Address offset: 0x50 */
-  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */
-  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */
-  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */
-  __IO uint32_t AF1;         /*!< TIM Alternate function option register 1, Address offset: 0x60 */
-  __IO uint32_t AF2;         /*!< TIM Alternate function option register 2, Address offset: 0x64 */
-} TIM_TypeDef;
-
-/**
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-typedef struct
-{
-  __IO uint32_t CR1;               /*!< USART Control register 1,                 Address offset: 0x00  */
-  __IO uint32_t CR2;               /*!< USART Control register 2,                 Address offset: 0x04  */
-  __IO uint32_t CR3;               /*!< USART Control register 3,                 Address offset: 0x08  */
-  __IO uint32_t BRR;               /*!< USART Baud rate register,                 Address offset: 0x0C  */
-  __IO uint32_t GTPR;              /*!< USART Guard time and prescaler register,  Address offset: 0x10  */
-  __IO uint32_t RTOR;              /*!< USART Receiver Time Out register,         Address offset: 0x14  */
-  __IO uint32_t RQR;               /*!< USART Request register,                   Address offset: 0x18  */
-  __IO uint32_t ISR;               /*!< USART Interrupt and status register,      Address offset: 0x1C  */
-  __IO uint32_t ICR;               /*!< USART Interrupt flag Clear register,      Address offset: 0x20  */
-  __IO uint32_t RDR;               /*!< USART Receive Data register,              Address offset: 0x24  */
-  __IO uint32_t TDR;               /*!< USART Transmit Data register,             Address offset: 0x28  */
-  __IO uint32_t PRESC;             /*!< USART Prescaler register,                 Address offset: 0x2C  */
-} USART_TypeDef;
-
-/**
-  * @brief VREFBUF
-  */
-typedef struct
-{
-  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */
-  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */
-} VREFBUF_TypeDef;
-
-/**
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;          /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;         /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;          /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-/*!< Boundary memory map */
-#define FLASH_BASE              0x08000000UL   /*!< FLASH(up to 256 KB) base address */
-#define SYSTEM_FLASH_BASE       0x1FFF0000UL   /*!< System FLASH(28Kb) base address */
-#define SRAM1_BASE              0x20000000UL   /*!< SRAM1(up to 32 KB) base address */
-#define SRAM2_BASE              0x20008000UL   /*!< SRAM2(up to 32 KB) base address */
-#define PERIPH_BASE             0x40000000UL   /*!< Peripheral base address */
-
-#define FLASH_SIZE              (((*((uint32_t *)FLASHSIZE_BASE)) & 0xFFFFU) << 10U)
-#define SRAM1_SIZE              0x00008000UL   /*!< SRAM1 default size : 32 kB */
-#define SRAM2_SIZE              0x00008000UL   /*!< SRAM2 default size : 32 kB  */
-
-/*!< Memory, OTP and Option bytes */
-#define OTP_AREA_BASE           (SYSTEM_FLASH_BASE + 0x00007000UL) /*!< OTP area : 1kB (0x1FFF7000 – 0x1FFF73FF)      */
-#define ENGI_BYTES_BASE         (SYSTEM_FLASH_BASE + 0x00007400UL) /*!< Engi Bytes : 1kB (0x1FFF7400 – 0x1FFF77FF)    */
-#define OPTION_BYTES_BASE       (SYSTEM_FLASH_BASE + 0x00007800UL) /*!< Option Bytes : 2kB (0x1FFF7800 – 0x1FFF7FFF)  */
-
-/*!< Device Electronic Signature */
-#define PACKAGE_BASE            (ENGI_BYTES_BASE + 0x00000100UL) /*!< Package data register base address     */
-#define UID64_BASE              (ENGI_BYTES_BASE + 0x00000180UL) /*!< 64-bit Unique device Identification    */
-#define UID_BASE                (ENGI_BYTES_BASE + 0x00000190UL) /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE          (ENGI_BYTES_BASE + 0x000001E0UL) /*!< Flash size data register base address  */
-
-#define SYSTEM_MEMORY_END_ADDR  (0x1FFF6FFFUL)   /*!< System Memory : 28KB (0x1FFF0000 – 0x1FFF6FFF)  */
-#define OTP_AREA_END_ADDR       (0x1FFF73FFUL)   /*!< OTP area : 1KB (0x1FFF7000 – 0x1FFF73FF)        */
-#define ENGI_BYTE_END_ADDR      (0x1FFF77FFUL)   /*!< Engi Bytes : 1kB (0x1FFF7400 – 0x1FFF77FF)      */
-#define OPTION_BYTE_END_ADDR    (0x1FFF7FFFUL)   /*!< Option Bytes : 2KB (0x1FFF7800 – 0x1FFF7FFF)    */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE         PERIPH_BASE
-#define APB2PERIPH_BASE         (PERIPH_BASE + 0x00010000UL)
-#define AHB1PERIPH_BASE         (PERIPH_BASE + 0x00020000UL)
-#define AHB2PERIPH_BASE         (PERIPH_BASE + 0x08000000UL)
-#define AHB3PERIPH_BASE         (PERIPH_BASE + 0x18000000UL)
-#define APB3PERIPH_BASE         (PERIPH_BASE + 0x18010000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE               (APB1PERIPH_BASE + 0x00000000UL)
-#define RTC_BASE                (APB1PERIPH_BASE + 0x00002800UL)
-#define WWDG_BASE               (APB1PERIPH_BASE + 0x00002C00UL)
-#define IWDG_BASE               (APB1PERIPH_BASE + 0x00003000UL)
-#define SPI2_BASE               (APB1PERIPH_BASE + 0x00003800UL)
-#define USART2_BASE             (APB1PERIPH_BASE + 0x00004400UL)
-#define I2C1_BASE               (APB1PERIPH_BASE + 0x00005400UL)
-#define I2C2_BASE               (APB1PERIPH_BASE + 0x00005800UL)
-#define I2C3_BASE               (APB1PERIPH_BASE + 0x00005C00UL)
-#define DAC_BASE                (APB1PERIPH_BASE + 0x00007400UL)
-#define LPTIM1_BASE             (APB1PERIPH_BASE + 0x00007C00UL)
-#define LPUART1_BASE            (APB1PERIPH_BASE + 0x00008000UL)
-#define LPTIM2_BASE             (APB1PERIPH_BASE + 0x00009400UL)
-#define LPTIM3_BASE             (APB1PERIPH_BASE + 0x00009800UL)
-#define TAMP_BASE               (APB1PERIPH_BASE + 0x0000B000UL)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE             (APB2PERIPH_BASE + 0x00000000UL)
-#define VREFBUF_BASE            (APB2PERIPH_BASE + 0x00000030UL)
-#define COMP1_BASE              (APB2PERIPH_BASE + 0x00000200UL)
-#define COMP2_BASE              (APB2PERIPH_BASE + 0x00000204UL)
-#define ADC_BASE                (APB2PERIPH_BASE + 0x00002400UL)
-#define ADC_COMMON_BASE         (APB2PERIPH_BASE + 0x00002708UL)
-#define TIM1_BASE               (APB2PERIPH_BASE + 0x00002C00UL)
-#define SPI1_BASE               (APB2PERIPH_BASE + 0x00003000UL)
-#define USART1_BASE             (APB2PERIPH_BASE + 0x00003800UL)
-#define TIM16_BASE              (APB2PERIPH_BASE + 0x00004400UL)
-#define TIM17_BASE              (APB2PERIPH_BASE + 0x00004800UL)
-
-/*!< AHB1 peripherals */
-#define DMA1_BASE               (AHB1PERIPH_BASE + 0x00000000UL)
-#define DMA2_BASE               (AHB1PERIPH_BASE + 0x00000400UL)
-#define DMAMUX1_BASE            (AHB1PERIPH_BASE + 0x00000800UL)
-#define CRC_BASE                (AHB1PERIPH_BASE + 0x00003000UL)
-
-#define DMA1_Channel1_BASE       (DMA1_BASE + 0x00000008UL)
-#define DMA1_Channel2_BASE       (DMA1_BASE + 0x0000001CUL)
-#define DMA1_Channel3_BASE       (DMA1_BASE + 0x00000030UL)
-#define DMA1_Channel4_BASE       (DMA1_BASE + 0x00000044UL)
-#define DMA1_Channel5_BASE       (DMA1_BASE + 0x00000058UL)
-#define DMA1_Channel6_BASE       (DMA1_BASE + 0x0000006CUL)
-#define DMA1_Channel7_BASE       (DMA1_BASE + 0x00000080UL)
-
-#define DMA2_Channel1_BASE       (DMA2_BASE + 0x00000008UL)
-#define DMA2_Channel2_BASE       (DMA2_BASE + 0x0000001CUL)
-#define DMA2_Channel3_BASE       (DMA2_BASE + 0x00000030UL)
-#define DMA2_Channel4_BASE       (DMA2_BASE + 0x00000044UL)
-#define DMA2_Channel5_BASE       (DMA2_BASE + 0x00000058UL)
-#define DMA2_Channel6_BASE       (DMA2_BASE + 0x0000006CUL)
-#define DMA2_Channel7_BASE       (DMA2_BASE + 0x00000080UL)
-
-#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)
-#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x00000004UL)
-#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x00000008UL)
-#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x0000000CUL)
-#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x00000010UL)
-#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x00000014UL)
-#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x00000018UL)
-#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x0000001CUL)
-#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x00000020UL)
-#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x00000024UL)
-#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x00000028UL)
-#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x0000002CUL)
-#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x00000030UL)
-#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x00000034UL)
-
-#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x00000100UL)
-#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x00000104UL)
-#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x00000108UL)
-#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x0000010CUL)
-
-#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x00000080UL)
-#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x00000140UL)
-
-/*!< AHB2 peripherals */
-#define IOPORT_BASE             (AHB2PERIPH_BASE + 0x00000000UL)
-#define GPIOA_BASE              (IOPORT_BASE + 0x00000000UL)
-#define GPIOB_BASE              (IOPORT_BASE + 0x00000400UL)
-#define GPIOC_BASE              (IOPORT_BASE + 0x00000800UL)
-#define GPIOH_BASE              (IOPORT_BASE + 0x00001C00UL)
-
-/*!< AHB3 peripherals */
-#define PWR_BASE                (AHB3PERIPH_BASE + 0x00000400UL)
-#define EXTI_BASE               (AHB3PERIPH_BASE + 0x00000800UL)
-#define RCC_BASE                (AHB3PERIPH_BASE + 0x00000000UL)
-#define RNG_BASE                (AHB3PERIPH_BASE + 0x00001000UL)
-#define HSEM_BASE               (AHB3PERIPH_BASE + 0x00001400UL)
-#define AES_BASE                (AHB3PERIPH_BASE + 0x00001800UL)
-#define PKA_BASE                (AHB3PERIPH_BASE + 0x00002000UL)
-#define FLASH_REG_BASE          (AHB3PERIPH_BASE + 0x00004000UL)
-
-/*!< APB3 peripherals */
-#define SUBGHZSPI_BASE          (APB3PERIPH_BASE + 0x00000000UL)
-
-/*!< Peripherals available on CPU1 external PPB bus */
-#define DBGMCU_BASE             (0xE0042000UL)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_declaration
-  * @{
-  */
-
-/* Peripherals available on APB1 bus */
-#define TIM2                    ((TIM_TypeDef *) TIM2_BASE)
-#define IWDG                    ((IWDG_TypeDef *) IWDG_BASE)
-#define WWDG                    ((WWDG_TypeDef *) WWDG_BASE)
-#define DAC                     ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1                  ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define LPTIM2                  ((LPTIM_TypeDef *) LPTIM2_BASE)
-#define LPTIM3                  ((LPTIM_TypeDef *) LPTIM3_BASE)
-#define RTC                     ((RTC_TypeDef *) RTC_BASE)
-#define SPI2                    ((SPI_TypeDef *) SPI2_BASE)
-#define I2C1                    ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                    ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                    ((I2C_TypeDef *) I2C3_BASE)
-#define TAMP                    ((TAMP_TypeDef *) TAMP_BASE)
-#define USART2                  ((USART_TypeDef *) USART2_BASE)
-#define LPUART1                 ((USART_TypeDef *) LPUART1_BASE)
-
-/* Peripherals available on APB2 bus */
-#define SYSCFG                  ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define VREFBUF                 ((VREFBUF_TypeDef *) VREFBUF_BASE)
-#define COMP1                   ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2                   ((COMP_TypeDef *) COMP2_BASE)
-#define COMP12_COMMON           ((COMP_Common_TypeDef *) COMP2_BASE)
-#define TIM1                    ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1                    ((SPI_TypeDef *) SPI1_BASE)
-#define ADC                     ((ADC_TypeDef *) ADC_BASE)
-#define ADC_COMMON              ((ADC_Common_TypeDef *) ADC_COMMON_BASE)
-#define TIM16                   ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17                   ((TIM_TypeDef *) TIM17_BASE)
-#define USART1                  ((USART_TypeDef *) USART1_BASE)
-
-/* Peripherals available on AHB1 bus */
-#define DMA1                    ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1           ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2           ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3           ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4           ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5           ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6           ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7           ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-
-#define DMA2                    ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1           ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2           ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3           ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4           ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5           ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DMA2_Channel6           ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
-#define DMA2_Channel7           ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
-
-#define DMAMUX1                 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
-#define DMAMUX1_Channel0        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
-#define DMAMUX1_Channel1        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
-#define DMAMUX1_Channel2        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
-#define DMAMUX1_Channel3        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
-#define DMAMUX1_Channel4        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
-#define DMAMUX1_Channel5        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
-#define DMAMUX1_Channel6        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
-#define DMAMUX1_Channel7        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
-#define DMAMUX1_Channel8        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
-#define DMAMUX1_Channel9        ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
-#define DMAMUX1_Channel10       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
-#define DMAMUX1_Channel11       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
-#define DMAMUX1_Channel12       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
-#define DMAMUX1_Channel13       ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
-
-#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
-#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
-#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
-#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
-
-#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
-#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
-
-#define CRC                     ((CRC_TypeDef *) CRC_BASE)
-
-/* Peripherals available on AHB2 bus */
-#define GPIOA                   ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB                   ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC                   ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOH                   ((GPIO_TypeDef *) GPIOH_BASE)
-
-/* Peripherals available on AH3 bus */
-#define AES                     ((AES_TypeDef *) AES_BASE)
-
-#define EXTI                    ((EXTI_TypeDef *) EXTI_BASE)
-#define RCC                     ((RCC_TypeDef *) RCC_BASE)
-#define PWR                     ((PWR_TypeDef *) PWR_BASE)
-#define RNG                     ((RNG_TypeDef *) RNG_BASE)
-#define HSEM                    ((HSEM_TypeDef *) HSEM_BASE)
-#define HSEM_COMMON             ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100U))
-#define PKA                     ((PKA_TypeDef *) PKA_BASE)
-#define FLASH                   ((FLASH_TypeDef *) FLASH_REG_BASE)
-
-/* Peripherals available on APB3 bus */
-#define SUBGHZSPI               ((SPI_TypeDef *) SUBGHZSPI_BASE)
-
-/* Peripherals available on CPU1 external PPB bus */
-#define DBGMCU                  ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-/** @addtogroup Hardware_Constant_Definition
-  * @{
-  */
-#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for ADC_ISR register  *******************/
-#define ADC_ISR_ADRDY_Pos              (0U)
-#define ADC_ISR_ADRDY_Msk              (0x1UL << ADC_ISR_ADRDY_Pos)            /*!< 0x00000001 */
-#define ADC_ISR_ADRDY                  ADC_ISR_ADRDY_Msk                       /*!< ADC ready flag */
-#define ADC_ISR_EOSMP_Pos              (1U)
-#define ADC_ISR_EOSMP_Msk              (0x1UL << ADC_ISR_EOSMP_Pos)            /*!< 0x00000002 */
-#define ADC_ISR_EOSMP                  ADC_ISR_EOSMP_Msk                       /*!< ADC group regular end of sampling flag */
-#define ADC_ISR_EOC_Pos                (2U)
-#define ADC_ISR_EOC_Msk                (0x1UL << ADC_ISR_EOC_Pos)              /*!< 0x00000004 */
-#define ADC_ISR_EOC                    ADC_ISR_EOC_Msk                         /*!< ADC group regular end of unitary conversion flag */
-#define ADC_ISR_EOS_Pos                (3U)
-#define ADC_ISR_EOS_Msk                (0x1UL << ADC_ISR_EOS_Pos)              /*!< 0x00000008 */
-#define ADC_ISR_EOS                    ADC_ISR_EOS_Msk                         /*!< ADC group regular end of sequence conversions flag */
-#define ADC_ISR_OVR_Pos                (4U)
-#define ADC_ISR_OVR_Msk                (0x1UL << ADC_ISR_OVR_Pos)              /*!< 0x00000010 */
-#define ADC_ISR_OVR                    ADC_ISR_OVR_Msk                         /*!< ADC group regular overrun flag */
-#define ADC_ISR_AWD1_Pos               (7U)
-#define ADC_ISR_AWD1_Msk               (0x1UL << ADC_ISR_AWD1_Pos)             /*!< 0x00000080 */
-#define ADC_ISR_AWD1                   ADC_ISR_AWD1_Msk                        /*!< ADC analog watchdog 1 flag */
-#define ADC_ISR_AWD2_Pos               (8U)
-#define ADC_ISR_AWD2_Msk               (0x1UL << ADC_ISR_AWD2_Pos)             /*!< 0x00000100 */
-#define ADC_ISR_AWD2                   ADC_ISR_AWD2_Msk                        /*!< ADC analog watchdog 2 flag */
-#define ADC_ISR_AWD3_Pos               (9U)
-#define ADC_ISR_AWD3_Msk               (0x1UL << ADC_ISR_AWD3_Pos)             /*!< 0x00000200 */
-#define ADC_ISR_AWD3                   ADC_ISR_AWD3_Msk                        /*!< ADC analog watchdog 3 flag */
-#define ADC_ISR_EOCAL_Pos              (11U)
-#define ADC_ISR_EOCAL_Msk              (0x1UL << ADC_ISR_EOCAL_Pos)            /*!< 0x00000800 */
-#define ADC_ISR_EOCAL                  ADC_ISR_EOCAL_Msk                       /*!< ADC end of calibration flag */
-#define ADC_ISR_CCRDY_Pos              (13U)
-#define ADC_ISR_CCRDY_Msk              (0x1UL << ADC_ISR_CCRDY_Pos)            /*!< 0x00002000 */
-#define ADC_ISR_CCRDY                  ADC_ISR_CCRDY_Msk                       /*!< ADC channel configuration ready flag */
-
-/********************  Bit definition for ADC_IER register  *******************/
-#define ADC_IER_ADRDYIE_Pos            (0U)
-#define ADC_IER_ADRDYIE_Msk            (0x1UL << ADC_IER_ADRDYIE_Pos)          /*!< 0x00000001 */
-#define ADC_IER_ADRDYIE                ADC_IER_ADRDYIE_Msk                     /*!< ADC ready interrupt */
-#define ADC_IER_EOSMPIE_Pos            (1U)
-#define ADC_IER_EOSMPIE_Msk            (0x1UL << ADC_IER_EOSMPIE_Pos)          /*!< 0x00000002 */
-#define ADC_IER_EOSMPIE                ADC_IER_EOSMPIE_Msk                     /*!< ADC group regular end of sampling interrupt */
-#define ADC_IER_EOCIE_Pos              (2U)
-#define ADC_IER_EOCIE_Msk              (0x1UL << ADC_IER_EOCIE_Pos)            /*!< 0x00000004 */
-#define ADC_IER_EOCIE                  ADC_IER_EOCIE_Msk                       /*!< ADC group regular end of unitary conversion interrupt */
-#define ADC_IER_EOSIE_Pos              (3U)
-#define ADC_IER_EOSIE_Msk              (0x1UL << ADC_IER_EOSIE_Pos)            /*!< 0x00000008 */
-#define ADC_IER_EOSIE                  ADC_IER_EOSIE_Msk                       /*!< ADC group regular end of sequence conversions interrupt */
-#define ADC_IER_OVRIE_Pos              (4U)
-#define ADC_IER_OVRIE_Msk              (0x1UL << ADC_IER_OVRIE_Pos)            /*!< 0x00000010 */
-#define ADC_IER_OVRIE                  ADC_IER_OVRIE_Msk                       /*!< ADC group regular overrun interrupt */
-#define ADC_IER_AWD1IE_Pos             (7U)
-#define ADC_IER_AWD1IE_Msk             (0x1UL << ADC_IER_AWD1IE_Pos)           /*!< 0x00000080 */
-#define ADC_IER_AWD1IE                 ADC_IER_AWD1IE_Msk                      /*!< ADC analog watchdog 1 interrupt */
-#define ADC_IER_AWD2IE_Pos             (8U)
-#define ADC_IER_AWD2IE_Msk             (0x1UL << ADC_IER_AWD2IE_Pos)           /*!< 0x00000100 */
-#define ADC_IER_AWD2IE                 ADC_IER_AWD2IE_Msk                      /*!< ADC analog watchdog 2 interrupt */
-#define ADC_IER_AWD3IE_Pos             (9U)
-#define ADC_IER_AWD3IE_Msk             (0x1UL << ADC_IER_AWD3IE_Pos)           /*!< 0x00000200 */
-#define ADC_IER_AWD3IE                 ADC_IER_AWD3IE_Msk                      /*!< ADC analog watchdog 3 interrupt */
-#define ADC_IER_EOCALIE_Pos            (11U)
-#define ADC_IER_EOCALIE_Msk            (0x1UL << ADC_IER_EOCALIE_Pos)          /*!< 0x00000800 */
-#define ADC_IER_EOCALIE                ADC_IER_EOCALIE_Msk                     /*!< ADC end of calibration interrupt */
-#define ADC_IER_CCRDYIE_Pos            (13U)
-#define ADC_IER_CCRDYIE_Msk            (0x1UL << ADC_IER_CCRDYIE_Pos)          /*!< 0x00002000 */
-#define ADC_IER_CCRDYIE                ADC_IER_CCRDYIE_Msk                     /*!< ADC channel configuration ready interrupt */
-
-/********************  Bit definition for ADC_CR register  ********************/
-#define ADC_CR_ADEN_Pos                (0U)
-#define ADC_CR_ADEN_Msk                (0x1UL << ADC_CR_ADEN_Pos)              /*!< 0x00000001 */
-#define ADC_CR_ADEN                    ADC_CR_ADEN_Msk                         /*!< ADC enable */
-#define ADC_CR_ADDIS_Pos               (1U)
-#define ADC_CR_ADDIS_Msk               (0x1UL << ADC_CR_ADDIS_Pos)             /*!< 0x00000002 */
-#define ADC_CR_ADDIS                   ADC_CR_ADDIS_Msk                        /*!< ADC disable */
-#define ADC_CR_ADSTART_Pos             (2U)
-#define ADC_CR_ADSTART_Msk             (0x1UL << ADC_CR_ADSTART_Pos)           /*!< 0x00000004 */
-#define ADC_CR_ADSTART                 ADC_CR_ADSTART_Msk                      /*!< ADC group regular conversion start */
-#define ADC_CR_ADSTP_Pos               (4U)
-#define ADC_CR_ADSTP_Msk               (0x1UL << ADC_CR_ADSTP_Pos)             /*!< 0x00000010 */
-#define ADC_CR_ADSTP                   ADC_CR_ADSTP_Msk                        /*!< ADC group regular conversion stop */
-#define ADC_CR_ADVREGEN_Pos            (28U)
-#define ADC_CR_ADVREGEN_Msk            (0x1UL << ADC_CR_ADVREGEN_Pos)          /*!< 0x10000000 */
-#define ADC_CR_ADVREGEN                ADC_CR_ADVREGEN_Msk                     /*!< ADC voltage regulator enable */
-#define ADC_CR_ADCAL_Pos               (31U)
-#define ADC_CR_ADCAL_Msk               (0x1UL << ADC_CR_ADCAL_Pos)             /*!< 0x80000000 */
-#define ADC_CR_ADCAL                   ADC_CR_ADCAL_Msk                        /*!< ADC calibration */
-
-/********************  Bit definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_DMAEN_Pos            (0U)
-#define ADC_CFGR1_DMAEN_Msk            (0x1UL << ADC_CFGR1_DMAEN_Pos)          /*!< 0x00000001 */
-#define ADC_CFGR1_DMAEN                ADC_CFGR1_DMAEN_Msk                     /*!< ADC DMA transfer enable */
-#define ADC_CFGR1_DMACFG_Pos           (1U)
-#define ADC_CFGR1_DMACFG_Msk           (0x1UL << ADC_CFGR1_DMACFG_Pos)         /*!< 0x00000002 */
-#define ADC_CFGR1_DMACFG               ADC_CFGR1_DMACFG_Msk                    /*!< ADC DMA transfer configuration */
-
-#define ADC_CFGR1_SCANDIR_Pos          (2U)
-#define ADC_CFGR1_SCANDIR_Msk          (0x1UL << ADC_CFGR1_SCANDIR_Pos)        /*!< 0x00000004 */
-#define ADC_CFGR1_SCANDIR              ADC_CFGR1_SCANDIR_Msk                   /*!< ADC group regular sequencer scan direction */
-
-#define ADC_CFGR1_RES_Pos              (3U)
-#define ADC_CFGR1_RES_Msk              (0x3UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000018 */
-#define ADC_CFGR1_RES                  ADC_CFGR1_RES_Msk                       /*!< ADC data resolution */
-#define ADC_CFGR1_RES_0                (0x1UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000008 */
-#define ADC_CFGR1_RES_1                (0x2UL << ADC_CFGR1_RES_Pos)            /*!< 0x00000010 */
-
-#define ADC_CFGR1_ALIGN_Pos            (5U)
-#define ADC_CFGR1_ALIGN_Msk            (0x1UL << ADC_CFGR1_ALIGN_Pos)          /*!< 0x00000020 */
-#define ADC_CFGR1_ALIGN                ADC_CFGR1_ALIGN_Msk                     /*!< ADC data alignement */
-
-#define ADC_CFGR1_EXTSEL_Pos           (6U)
-#define ADC_CFGR1_EXTSEL_Msk           (0x7UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x000001C0 */
-#define ADC_CFGR1_EXTSEL               ADC_CFGR1_EXTSEL_Msk                    /*!< ADC group regular external trigger source */
-#define ADC_CFGR1_EXTSEL_0             (0x1UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000040 */
-#define ADC_CFGR1_EXTSEL_1             (0x2UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000080 */
-#define ADC_CFGR1_EXTSEL_2             (0x4UL << ADC_CFGR1_EXTSEL_Pos)         /*!< 0x00000100 */
-
-#define ADC_CFGR1_EXTEN_Pos            (10U)
-#define ADC_CFGR1_EXTEN_Msk            (0x3UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000C00 */
-#define ADC_CFGR1_EXTEN                ADC_CFGR1_EXTEN_Msk                     /*!< ADC group regular external trigger polarity */
-#define ADC_CFGR1_EXTEN_0              (0x1UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000400 */
-#define ADC_CFGR1_EXTEN_1              (0x2UL << ADC_CFGR1_EXTEN_Pos)          /*!< 0x00000800 */
-
-#define ADC_CFGR1_OVRMOD_Pos           (12U)
-#define ADC_CFGR1_OVRMOD_Msk           (0x1UL << ADC_CFGR1_OVRMOD_Pos)         /*!< 0x00001000 */
-#define ADC_CFGR1_OVRMOD               ADC_CFGR1_OVRMOD_Msk                    /*!< ADC group regular overrun configuration */
-#define ADC_CFGR1_CONT_Pos             (13U)
-#define ADC_CFGR1_CONT_Msk             (0x1UL << ADC_CFGR1_CONT_Pos)           /*!< 0x00002000 */
-#define ADC_CFGR1_CONT                 ADC_CFGR1_CONT_Msk                      /*!< ADC group regular continuous conversion mode */
-#define ADC_CFGR1_WAIT_Pos             (14U)
-#define ADC_CFGR1_WAIT_Msk             (0x1UL << ADC_CFGR1_WAIT_Pos)           /*!< 0x00004000 */
-#define ADC_CFGR1_WAIT                 ADC_CFGR1_WAIT_Msk                      /*!< ADC low power auto wait */
-#define ADC_CFGR1_AUTOFF_Pos           (15U)
-#define ADC_CFGR1_AUTOFF_Msk           (0x1UL << ADC_CFGR1_AUTOFF_Pos)         /*!< 0x00008000 */
-#define ADC_CFGR1_AUTOFF               ADC_CFGR1_AUTOFF_Msk                    /*!< ADC low power auto power off */
-#define ADC_CFGR1_DISCEN_Pos           (16U)
-#define ADC_CFGR1_DISCEN_Msk           (0x1UL << ADC_CFGR1_DISCEN_Pos)         /*!< 0x00010000 */
-#define ADC_CFGR1_DISCEN               ADC_CFGR1_DISCEN_Msk                    /*!< ADC group regular sequencer discontinuous mode */
-#define ADC_CFGR1_CHSELRMOD_Pos        (21U)
-#define ADC_CFGR1_CHSELRMOD_Msk        (0x1UL << ADC_CFGR1_CHSELRMOD_Pos)      /*!< 0x00200000 */
-#define ADC_CFGR1_CHSELRMOD            ADC_CFGR1_CHSELRMOD_Msk                 /*!< ADC group regular sequencer mode */
-
-#define ADC_CFGR1_AWD1SGL_Pos          (22U)
-#define ADC_CFGR1_AWD1SGL_Msk          (0x1UL << ADC_CFGR1_AWD1SGL_Pos)        /*!< 0x00400000 */
-#define ADC_CFGR1_AWD1SGL              ADC_CFGR1_AWD1SGL_Msk                   /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
-#define ADC_CFGR1_AWD1EN_Pos           (23U)
-#define ADC_CFGR1_AWD1EN_Msk           (0x1UL << ADC_CFGR1_AWD1EN_Pos)         /*!< 0x00800000 */
-#define ADC_CFGR1_AWD1EN               ADC_CFGR1_AWD1EN_Msk                    /*!< ADC analog watchdog 1 enable on scope ADC group regular */
-
-#define ADC_CFGR1_AWD1CH_Pos           (26U)
-#define ADC_CFGR1_AWD1CH_Msk           (0x1FUL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x7C000000 */
-#define ADC_CFGR1_AWD1CH               ADC_CFGR1_AWD1CH_Msk                    /*!< ADC analog watchdog 1 monitored channel selection */
-#define ADC_CFGR1_AWD1CH_0             (0x01UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x04000000 */
-#define ADC_CFGR1_AWD1CH_1             (0x02UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x08000000 */
-#define ADC_CFGR1_AWD1CH_2             (0x04UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x10000000 */
-#define ADC_CFGR1_AWD1CH_3             (0x08UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x20000000 */
-#define ADC_CFGR1_AWD1CH_4             (0x10UL << ADC_CFGR1_AWD1CH_Pos)        /*!< 0x40000000 */
-
-/********************  Bit definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_OVSE_Pos             (0U)
-#define ADC_CFGR2_OVSE_Msk             (0x1UL << ADC_CFGR2_OVSE_Pos)           /*!< 0x00000001 */
-#define ADC_CFGR2_OVSE                 ADC_CFGR2_OVSE_Msk                      /*!< ADC oversampler enable on scope ADC group regular */
-
-#define ADC_CFGR2_OVSR_Pos             (2U)
-#define ADC_CFGR2_OVSR_Msk             (0x7UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x0000001C */
-#define ADC_CFGR2_OVSR                 ADC_CFGR2_OVSR_Msk                      /*!< ADC oversampling ratio */
-#define ADC_CFGR2_OVSR_0               (0x1UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000004 */
-#define ADC_CFGR2_OVSR_1               (0x2UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000008 */
-#define ADC_CFGR2_OVSR_2               (0x4UL << ADC_CFGR2_OVSR_Pos)           /*!< 0x00000010 */
-
-#define ADC_CFGR2_OVSS_Pos             (5U)
-#define ADC_CFGR2_OVSS_Msk             (0xFUL << ADC_CFGR2_OVSS_Pos)           /*!< 0x000001E0 */
-#define ADC_CFGR2_OVSS                 ADC_CFGR2_OVSS_Msk                      /*!< ADC oversampling shift */
-#define ADC_CFGR2_OVSS_0               (0x1UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000020 */
-#define ADC_CFGR2_OVSS_1               (0x2UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000040 */
-#define ADC_CFGR2_OVSS_2               (0x4UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000080 */
-#define ADC_CFGR2_OVSS_3               (0x8UL << ADC_CFGR2_OVSS_Pos)           /*!< 0x00000100 */
-
-#define ADC_CFGR2_TOVS_Pos             (9U)
-#define ADC_CFGR2_TOVS_Msk             (0x1UL << ADC_CFGR2_TOVS_Pos)           /*!< 0x00000200 */
-#define ADC_CFGR2_TOVS                 ADC_CFGR2_TOVS_Msk                      /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
-
-#define ADC_CFGR2_LFTRIG_Pos           (29U)
-#define ADC_CFGR2_LFTRIG_Msk           (0x1UL << ADC_CFGR2_LFTRIG_Pos)         /*!< 0x20000000 */
-#define ADC_CFGR2_LFTRIG               ADC_CFGR2_LFTRIG_Msk                    /*!< ADC low frequency trigger mode */
-
-#define ADC_CFGR2_CKMODE_Pos           (30U)
-#define ADC_CFGR2_CKMODE_Msk           (0x3UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0xC0000000 */
-#define ADC_CFGR2_CKMODE               ADC_CFGR2_CKMODE_Msk                    /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
-#define ADC_CFGR2_CKMODE_1             (0x2UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x80000000 */
-#define ADC_CFGR2_CKMODE_0             (0x1UL << ADC_CFGR2_CKMODE_Pos)         /*!< 0x40000000 */
-
-/********************  Bit definition for ADC_SMPR register  ******************/
-#define ADC_SMPR_SMP1_Pos              (0U)
-#define ADC_SMPR_SMP1_Msk              (0x7UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000007 */
-#define ADC_SMPR_SMP1                  ADC_SMPR_SMP1_Msk                       /*!< ADC group of channels sampling time 1 */
-#define ADC_SMPR_SMP1_0                (0x1UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000001 */
-#define ADC_SMPR_SMP1_1                (0x2UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000002 */
-#define ADC_SMPR_SMP1_2                (0x4UL << ADC_SMPR_SMP1_Pos)            /*!< 0x00000004 */
-
-#define ADC_SMPR_SMP2_Pos              (4U)
-#define ADC_SMPR_SMP2_Msk              (0x7UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000070 */
-#define ADC_SMPR_SMP2                  ADC_SMPR_SMP2_Msk                       /*!< ADC group of channels sampling time 2 */
-#define ADC_SMPR_SMP2_0                (0x1UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000010 */
-#define ADC_SMPR_SMP2_1                (0x2UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000020 */
-#define ADC_SMPR_SMP2_2                (0x4UL << ADC_SMPR_SMP2_Pos)            /*!< 0x00000040 */
-
-#define ADC_SMPR_SMPSEL_Pos            (8U)
-#define ADC_SMPR_SMPSEL_Msk            (0x3FFFFUL << ADC_SMPR_SMPSEL_Pos)      /*!< 0x03FFFF00 */
-#define ADC_SMPR_SMPSEL                ADC_SMPR_SMPSEL_Msk                     /*!< ADC all channels sampling time selection */
-#define ADC_SMPR_SMPSEL0_Pos           (8U)
-#define ADC_SMPR_SMPSEL0_Msk           (0x1UL << ADC_SMPR_SMPSEL0_Pos)         /*!< 0x00000100 */
-#define ADC_SMPR_SMPSEL0               ADC_SMPR_SMPSEL0_Msk                    /*!< ADC channel 0 sampling time selection */
-#define ADC_SMPR_SMPSEL1_Pos           (9U)
-#define ADC_SMPR_SMPSEL1_Msk           (0x1UL << ADC_SMPR_SMPSEL1_Pos)         /*!< 0x00000200 */
-#define ADC_SMPR_SMPSEL1               ADC_SMPR_SMPSEL1_Msk                    /*!< ADC channel 1 sampling time selection */
-#define ADC_SMPR_SMPSEL2_Pos           (10U)
-#define ADC_SMPR_SMPSEL2_Msk           (0x1UL << ADC_SMPR_SMPSEL2_Pos)         /*!< 0x00000400 */
-#define ADC_SMPR_SMPSEL2               ADC_SMPR_SMPSEL2_Msk                    /*!< ADC channel 2 sampling time selection */
-#define ADC_SMPR_SMPSEL3_Pos           (11U)
-#define ADC_SMPR_SMPSEL3_Msk           (0x1UL << ADC_SMPR_SMPSEL3_Pos)         /*!< 0x00000800 */
-#define ADC_SMPR_SMPSEL3               ADC_SMPR_SMPSEL3_Msk                    /*!< ADC channel 3 sampling time selection */
-#define ADC_SMPR_SMPSEL4_Pos           (12U)
-#define ADC_SMPR_SMPSEL4_Msk           (0x1UL << ADC_SMPR_SMPSEL4_Pos)         /*!< 0x00001000 */
-#define ADC_SMPR_SMPSEL4               ADC_SMPR_SMPSEL4_Msk                    /*!< ADC channel 4 sampling time selection */
-#define ADC_SMPR_SMPSEL5_Pos           (13U)
-#define ADC_SMPR_SMPSEL5_Msk           (0x1UL << ADC_SMPR_SMPSEL5_Pos)         /*!< 0x00002000 */
-#define ADC_SMPR_SMPSEL5               ADC_SMPR_SMPSEL5_Msk                    /*!< ADC channel 5 sampling time selection */
-#define ADC_SMPR_SMPSEL6_Pos           (14U)
-#define ADC_SMPR_SMPSEL6_Msk           (0x1UL << ADC_SMPR_SMPSEL6_Pos)         /*!< 0x00004000 */
-#define ADC_SMPR_SMPSEL6               ADC_SMPR_SMPSEL6_Msk                    /*!< ADC channel 6 sampling time selection */
-#define ADC_SMPR_SMPSEL7_Pos           (15U)
-#define ADC_SMPR_SMPSEL7_Msk           (0x1UL << ADC_SMPR_SMPSEL7_Pos)         /*!< 0x00008000 */
-#define ADC_SMPR_SMPSEL7               ADC_SMPR_SMPSEL7_Msk                    /*!< ADC channel 7 sampling time selection */
-#define ADC_SMPR_SMPSEL8_Pos           (16U)
-#define ADC_SMPR_SMPSEL8_Msk           (0x1UL << ADC_SMPR_SMPSEL8_Pos)         /*!< 0x00010000 */
-#define ADC_SMPR_SMPSEL8               ADC_SMPR_SMPSEL8_Msk                    /*!< ADC channel 8 sampling time selection */
-#define ADC_SMPR_SMPSEL9_Pos           (17U)
-#define ADC_SMPR_SMPSEL9_Msk           (0x1UL << ADC_SMPR_SMPSEL9_Pos)         /*!< 0x00020000 */
-#define ADC_SMPR_SMPSEL9               ADC_SMPR_SMPSEL9_Msk                    /*!< ADC channel 9 sampling time selection */
-#define ADC_SMPR_SMPSEL10_Pos          (18U)
-#define ADC_SMPR_SMPSEL10_Msk          (0x1UL << ADC_SMPR_SMPSEL10_Pos)        /*!< 0x00040000 */
-#define ADC_SMPR_SMPSEL10              ADC_SMPR_SMPSEL10_Msk                   /*!< ADC channel 10 sampling time selection */
-#define ADC_SMPR_SMPSEL11_Pos          (19U)
-#define ADC_SMPR_SMPSEL11_Msk          (0x1UL << ADC_SMPR_SMPSEL11_Pos)        /*!< 0x00080000 */
-#define ADC_SMPR_SMPSEL11              ADC_SMPR_SMPSEL11_Msk                   /*!< ADC channel 11 sampling time selection */
-#define ADC_SMPR_SMPSEL12_Pos          (20U)
-#define ADC_SMPR_SMPSEL12_Msk          (0x1UL << ADC_SMPR_SMPSEL12_Pos)        /*!< 0x00100000 */
-#define ADC_SMPR_SMPSEL12              ADC_SMPR_SMPSEL12_Msk                   /*!< ADC channel 12 sampling time selection */
-#define ADC_SMPR_SMPSEL13_Pos          (21U)
-#define ADC_SMPR_SMPSEL13_Msk          (0x1UL << ADC_SMPR_SMPSEL13_Pos)        /*!< 0x00200000 */
-#define ADC_SMPR_SMPSEL13              ADC_SMPR_SMPSEL13_Msk                   /*!< ADC channel 13 sampling time selection */
-#define ADC_SMPR_SMPSEL14_Pos          (22U)
-#define ADC_SMPR_SMPSEL14_Msk          (0x1UL << ADC_SMPR_SMPSEL14_Pos)        /*!< 0x00400000 */
-#define ADC_SMPR_SMPSEL14              ADC_SMPR_SMPSEL14_Msk                   /*!< ADC channel 14 sampling time selection */
-#define ADC_SMPR_SMPSEL15_Pos          (23U)
-#define ADC_SMPR_SMPSEL15_Msk          (0x1UL << ADC_SMPR_SMPSEL15_Pos)        /*!< 0x00800000 */
-#define ADC_SMPR_SMPSEL15              ADC_SMPR_SMPSEL15_Msk                   /*!< ADC channel 15 sampling time selection */
-#define ADC_SMPR_SMPSEL16_Pos          (24U)
-#define ADC_SMPR_SMPSEL16_Msk          (0x1UL << ADC_SMPR_SMPSEL16_Pos)        /*!< 0x01000000 */
-#define ADC_SMPR_SMPSEL16              ADC_SMPR_SMPSEL16_Msk                   /*!< ADC channel 16 sampling time selection */
-#define ADC_SMPR_SMPSEL17_Pos          (25U)
-#define ADC_SMPR_SMPSEL17_Msk          (0x1UL << ADC_SMPR_SMPSEL17_Pos)        /*!< 0x02000000 */
-#define ADC_SMPR_SMPSEL17              ADC_SMPR_SMPSEL17_Msk                   /*!< ADC channel 17 sampling time selection */
-
-/********************  Bit definition for ADC_TR1 register  *******************/
-#define ADC_TR1_LT1_Pos                (0U)
-#define ADC_TR1_LT1_Msk                (0xFFFUL << ADC_TR1_LT1_Pos)            /*!< 0x00000FFF */
-#define ADC_TR1_LT1                    ADC_TR1_LT1_Msk                         /*!< ADC analog watchdog 1 threshold low */
-#define ADC_TR1_LT1_0                  (0x001UL << ADC_TR1_LT1_Pos)            /*!< 0x00000001 */
-#define ADC_TR1_LT1_1                  (0x002UL << ADC_TR1_LT1_Pos)            /*!< 0x00000002 */
-#define ADC_TR1_LT1_2                  (0x004UL << ADC_TR1_LT1_Pos)            /*!< 0x00000004 */
-#define ADC_TR1_LT1_3                  (0x008UL << ADC_TR1_LT1_Pos)            /*!< 0x00000008 */
-#define ADC_TR1_LT1_4                  (0x010UL << ADC_TR1_LT1_Pos)            /*!< 0x00000010 */
-#define ADC_TR1_LT1_5                  (0x020UL << ADC_TR1_LT1_Pos)            /*!< 0x00000020 */
-#define ADC_TR1_LT1_6                  (0x040UL << ADC_TR1_LT1_Pos)            /*!< 0x00000040 */
-#define ADC_TR1_LT1_7                  (0x080UL << ADC_TR1_LT1_Pos)            /*!< 0x00000080 */
-#define ADC_TR1_LT1_8                  (0x100UL << ADC_TR1_LT1_Pos)            /*!< 0x00000100 */
-#define ADC_TR1_LT1_9                  (0x200UL << ADC_TR1_LT1_Pos)            /*!< 0x00000200 */
-#define ADC_TR1_LT1_10                 (0x400UL << ADC_TR1_LT1_Pos)            /*!< 0x00000400 */
-#define ADC_TR1_LT1_11                 (0x800UL << ADC_TR1_LT1_Pos)            /*!< 0x00000800 */
-
-#define ADC_TR1_HT1_Pos                (16U)
-#define ADC_TR1_HT1_Msk                (0xFFFUL << ADC_TR1_HT1_Pos)            /*!< 0x0FFF0000 */
-#define ADC_TR1_HT1                    ADC_TR1_HT1_Msk                         /*!< ADC Analog watchdog 1 threshold high */
-#define ADC_TR1_HT1_0                  (0x001UL << ADC_TR1_HT1_Pos)            /*!< 0x00010000 */
-#define ADC_TR1_HT1_1                  (0x002UL << ADC_TR1_HT1_Pos)            /*!< 0x00020000 */
-#define ADC_TR1_HT1_2                  (0x004UL << ADC_TR1_HT1_Pos)            /*!< 0x00040000 */
-#define ADC_TR1_HT1_3                  (0x008UL << ADC_TR1_HT1_Pos)            /*!< 0x00080000 */
-#define ADC_TR1_HT1_4                  (0x010UL << ADC_TR1_HT1_Pos)            /*!< 0x00100000 */
-#define ADC_TR1_HT1_5                  (0x020UL << ADC_TR1_HT1_Pos)            /*!< 0x00200000 */
-#define ADC_TR1_HT1_6                  (0x040UL << ADC_TR1_HT1_Pos)            /*!< 0x00400000 */
-#define ADC_TR1_HT1_7                  (0x080UL << ADC_TR1_HT1_Pos)            /*!< 0x00800000 */
-#define ADC_TR1_HT1_8                  (0x100UL << ADC_TR1_HT1_Pos)            /*!< 0x01000000 */
-#define ADC_TR1_HT1_9                  (0x200UL << ADC_TR1_HT1_Pos)            /*!< 0x02000000 */
-#define ADC_TR1_HT1_10                 (0x400UL << ADC_TR1_HT1_Pos)            /*!< 0x04000000 */
-#define ADC_TR1_HT1_11                 (0x800UL << ADC_TR1_HT1_Pos)            /*!< 0x08000000 */
-
-/********************  Bit definition for ADC_TR2 register  *******************/
-#define ADC_TR2_LT2_Pos                (0U)
-#define ADC_TR2_LT2_Msk                (0xFFFUL << ADC_TR2_LT2_Pos)            /*!< 0x00000FFF */
-#define ADC_TR2_LT2                    ADC_TR2_LT2_Msk                         /*!< ADC analog watchdog 2 threshold low */
-#define ADC_TR2_LT2_0                  (0x001UL << ADC_TR2_LT2_Pos)            /*!< 0x00000001 */
-#define ADC_TR2_LT2_1                  (0x002UL << ADC_TR2_LT2_Pos)            /*!< 0x00000002 */
-#define ADC_TR2_LT2_2                  (0x004UL << ADC_TR2_LT2_Pos)            /*!< 0x00000004 */
-#define ADC_TR2_LT2_3                  (0x008UL << ADC_TR2_LT2_Pos)            /*!< 0x00000008 */
-#define ADC_TR2_LT2_4                  (0x010UL << ADC_TR2_LT2_Pos)            /*!< 0x00000010 */
-#define ADC_TR2_LT2_5                  (0x020UL << ADC_TR2_LT2_Pos)            /*!< 0x00000020 */
-#define ADC_TR2_LT2_6                  (0x040UL << ADC_TR2_LT2_Pos)            /*!< 0x00000040 */
-#define ADC_TR2_LT2_7                  (0x080UL << ADC_TR2_LT2_Pos)            /*!< 0x00000080 */
-#define ADC_TR2_LT2_8                  (0x100UL << ADC_TR2_LT2_Pos)            /*!< 0x00000100 */
-#define ADC_TR2_LT2_9                  (0x200UL << ADC_TR2_LT2_Pos)            /*!< 0x00000200 */
-#define ADC_TR2_LT2_10                 (0x400UL << ADC_TR2_LT2_Pos)            /*!< 0x00000400 */
-#define ADC_TR2_LT2_11                 (0x800UL << ADC_TR2_LT2_Pos)            /*!< 0x00000800 */
-
-#define ADC_TR2_HT2_Pos                (16U)
-#define ADC_TR2_HT2_Msk                (0xFFFUL << ADC_TR2_HT2_Pos)            /*!< 0x0FFF0000 */
-#define ADC_TR2_HT2                    ADC_TR2_HT2_Msk                         /*!< ADC analog watchdog 2 threshold high */
-#define ADC_TR2_HT2_0                  (0x001UL << ADC_TR2_HT2_Pos)            /*!< 0x00010000 */
-#define ADC_TR2_HT2_1                  (0x002UL << ADC_TR2_HT2_Pos)            /*!< 0x00020000 */
-#define ADC_TR2_HT2_2                  (0x004UL << ADC_TR2_HT2_Pos)            /*!< 0x00040000 */
-#define ADC_TR2_HT2_3                  (0x008UL << ADC_TR2_HT2_Pos)            /*!< 0x00080000 */
-#define ADC_TR2_HT2_4                  (0x010UL << ADC_TR2_HT2_Pos)            /*!< 0x00100000 */
-#define ADC_TR2_HT2_5                  (0x020UL << ADC_TR2_HT2_Pos)            /*!< 0x00200000 */
-#define ADC_TR2_HT2_6                  (0x040UL << ADC_TR2_HT2_Pos)            /*!< 0x00400000 */
-#define ADC_TR2_HT2_7                  (0x080UL << ADC_TR2_HT2_Pos)            /*!< 0x00800000 */
-#define ADC_TR2_HT2_8                  (0x100UL << ADC_TR2_HT2_Pos)            /*!< 0x01000000 */
-#define ADC_TR2_HT2_9                  (0x200UL << ADC_TR2_HT2_Pos)            /*!< 0x02000000 */
-#define ADC_TR2_HT2_10                 (0x400UL << ADC_TR2_HT2_Pos)            /*!< 0x04000000 */
-#define ADC_TR2_HT2_11                 (0x800UL << ADC_TR2_HT2_Pos)            /*!< 0x08000000 */
-
-/********************  Bit definition for ADC_CHSELR register  ****************/
-#define ADC_CHSELR_CHSEL_Pos           (0U)
-#define ADC_CHSELR_CHSEL_Msk           (0x3FFFFUL << ADC_CHSELR_CHSEL_Pos)     /*!< 0x0003FFFF */
-#define ADC_CHSELR_CHSEL               ADC_CHSELR_CHSEL_Msk                    /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL17_Pos         (17U)
-#define ADC_CHSELR_CHSEL17_Msk         (0x1UL << ADC_CHSELR_CHSEL17_Pos)       /*!< 0x00020000 */
-#define ADC_CHSELR_CHSEL17             ADC_CHSELR_CHSEL17_Msk                  /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL16_Pos         (16U)
-#define ADC_CHSELR_CHSEL16_Msk         (0x1UL << ADC_CHSELR_CHSEL16_Pos)       /*!< 0x00010000 */
-#define ADC_CHSELR_CHSEL16             ADC_CHSELR_CHSEL16_Msk                  /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL15_Pos         (15U)
-#define ADC_CHSELR_CHSEL15_Msk         (0x1UL << ADC_CHSELR_CHSEL15_Pos)       /*!< 0x00008000 */
-#define ADC_CHSELR_CHSEL15             ADC_CHSELR_CHSEL15_Msk                  /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL14_Pos         (14U)
-#define ADC_CHSELR_CHSEL14_Msk         (0x1UL << ADC_CHSELR_CHSEL14_Pos)       /*!< 0x00004000 */
-#define ADC_CHSELR_CHSEL14             ADC_CHSELR_CHSEL14_Msk                  /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL13_Pos         (13U)
-#define ADC_CHSELR_CHSEL13_Msk         (0x1UL << ADC_CHSELR_CHSEL13_Pos)       /*!< 0x00002000 */
-#define ADC_CHSELR_CHSEL13             ADC_CHSELR_CHSEL13_Msk                  /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL12_Pos         (12U)
-#define ADC_CHSELR_CHSEL12_Msk         (0x1UL << ADC_CHSELR_CHSEL12_Pos)       /*!< 0x00001000 */
-#define ADC_CHSELR_CHSEL12             ADC_CHSELR_CHSEL12_Msk                  /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL11_Pos         (11U)
-#define ADC_CHSELR_CHSEL11_Msk         (0x1UL << ADC_CHSELR_CHSEL11_Pos)       /*!< 0x00000800 */
-#define ADC_CHSELR_CHSEL11             ADC_CHSELR_CHSEL11_Msk                  /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL10_Pos         (10U)
-#define ADC_CHSELR_CHSEL10_Msk         (0x1UL << ADC_CHSELR_CHSEL10_Pos)       /*!< 0x00000400 */
-#define ADC_CHSELR_CHSEL10             ADC_CHSELR_CHSEL10_Msk                  /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL9_Pos          (9U)
-#define ADC_CHSELR_CHSEL9_Msk          (0x1UL << ADC_CHSELR_CHSEL9_Pos)        /*!< 0x00000200 */
-#define ADC_CHSELR_CHSEL9              ADC_CHSELR_CHSEL9_Msk                   /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL8_Pos          (8U)
-#define ADC_CHSELR_CHSEL8_Msk          (0x1UL << ADC_CHSELR_CHSEL8_Pos)        /*!< 0x00000100 */
-#define ADC_CHSELR_CHSEL8              ADC_CHSELR_CHSEL8_Msk                   /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL7_Pos          (7U)
-#define ADC_CHSELR_CHSEL7_Msk          (0x1UL << ADC_CHSELR_CHSEL7_Pos)        /*!< 0x00000080 */
-#define ADC_CHSELR_CHSEL7              ADC_CHSELR_CHSEL7_Msk                   /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL6_Pos          (6U)
-#define ADC_CHSELR_CHSEL6_Msk          (0x1UL << ADC_CHSELR_CHSEL6_Pos)        /*!< 0x00000040 */
-#define ADC_CHSELR_CHSEL6              ADC_CHSELR_CHSEL6_Msk                   /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL5_Pos          (5U)
-#define ADC_CHSELR_CHSEL5_Msk          (0x1UL << ADC_CHSELR_CHSEL5_Pos)        /*!< 0x00000020 */
-#define ADC_CHSELR_CHSEL5              ADC_CHSELR_CHSEL5_Msk                   /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL4_Pos          (4U)
-#define ADC_CHSELR_CHSEL4_Msk          (0x1UL << ADC_CHSELR_CHSEL4_Pos)        /*!< 0x00000010 */
-#define ADC_CHSELR_CHSEL4              ADC_CHSELR_CHSEL4_Msk                   /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL3_Pos          (3U)
-#define ADC_CHSELR_CHSEL3_Msk          (0x1UL << ADC_CHSELR_CHSEL3_Pos)        /*!< 0x00000008 */
-#define ADC_CHSELR_CHSEL3              ADC_CHSELR_CHSEL3_Msk                   /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL2_Pos          (2U)
-#define ADC_CHSELR_CHSEL2_Msk          (0x1UL << ADC_CHSELR_CHSEL2_Pos)        /*!< 0x00000004 */
-#define ADC_CHSELR_CHSEL2              ADC_CHSELR_CHSEL2_Msk                   /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL1_Pos          (1U)
-#define ADC_CHSELR_CHSEL1_Msk          (0x1UL << ADC_CHSELR_CHSEL1_Pos)        /*!< 0x00000002 */
-#define ADC_CHSELR_CHSEL1              ADC_CHSELR_CHSEL1_Msk                   /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
-#define ADC_CHSELR_CHSEL0_Pos          (0U)
-#define ADC_CHSELR_CHSEL0_Msk          (0x1UL << ADC_CHSELR_CHSEL0_Pos)        /*!< 0x00000001 */
-#define ADC_CHSELR_CHSEL0              ADC_CHSELR_CHSEL0_Msk                   /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
-
-#define ADC_CHSELR_SQ_ALL_Pos          (0U)
-#define ADC_CHSELR_SQ_ALL_Msk          (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */
-#define ADC_CHSELR_SQ_ALL              ADC_CHSELR_SQ_ALL_Msk                   /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */
-
-#define ADC_CHSELR_SQ8_Pos             (28U)
-#define ADC_CHSELR_SQ8_Msk             (0xFUL << ADC_CHSELR_SQ8_Pos)           /*!< 0xF0000000 */
-#define ADC_CHSELR_SQ8                 ADC_CHSELR_SQ8_Msk                      /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ8_0               (0x1UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x10000000 */
-#define ADC_CHSELR_SQ8_1               (0x2UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x20000000 */
-#define ADC_CHSELR_SQ8_2               (0x4UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x40000000 */
-#define ADC_CHSELR_SQ8_3               (0x8UL << ADC_CHSELR_SQ8_Pos)           /*!< 0x80000000 */
-
-#define ADC_CHSELR_SQ7_Pos             (24U)
-#define ADC_CHSELR_SQ7_Msk             (0xFUL << ADC_CHSELR_SQ7_Pos)           /*!< 0x0F000000 */
-#define ADC_CHSELR_SQ7                 ADC_CHSELR_SQ7_Msk                      /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ7_0               (0x1UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x01000000 */
-#define ADC_CHSELR_SQ7_1               (0x2UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x02000000 */
-#define ADC_CHSELR_SQ7_2               (0x4UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x04000000 */
-#define ADC_CHSELR_SQ7_3               (0x8UL << ADC_CHSELR_SQ7_Pos)           /*!< 0x08000000 */
-
-#define ADC_CHSELR_SQ6_Pos             (20U)
-#define ADC_CHSELR_SQ6_Msk             (0xFUL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00F00000 */
-#define ADC_CHSELR_SQ6                 ADC_CHSELR_SQ6_Msk                      /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ6_0               (0x1UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00100000 */
-#define ADC_CHSELR_SQ6_1               (0x2UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00200000 */
-#define ADC_CHSELR_SQ6_2               (0x4UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00400000 */
-#define ADC_CHSELR_SQ6_3               (0x8UL << ADC_CHSELR_SQ6_Pos)           /*!< 0x00800000 */
-
-#define ADC_CHSELR_SQ5_Pos             (16U)
-#define ADC_CHSELR_SQ5_Msk             (0xFUL << ADC_CHSELR_SQ5_Pos)           /*!< 0x000F0000 */
-#define ADC_CHSELR_SQ5                 ADC_CHSELR_SQ5_Msk                      /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ5_0               (0x1UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00010000 */
-#define ADC_CHSELR_SQ5_1               (0x2UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00020000 */
-#define ADC_CHSELR_SQ5_2               (0x4UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00040000 */
-#define ADC_CHSELR_SQ5_3               (0x8UL << ADC_CHSELR_SQ5_Pos)           /*!< 0x00080000 */
-
-#define ADC_CHSELR_SQ4_Pos             (12U)
-#define ADC_CHSELR_SQ4_Msk             (0xFUL << ADC_CHSELR_SQ4_Pos)           /*!< 0x0000F000 */
-#define ADC_CHSELR_SQ4                 ADC_CHSELR_SQ4_Msk                      /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ4_0               (0x1UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00001000 */
-#define ADC_CHSELR_SQ4_1               (0x2UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00002000 */
-#define ADC_CHSELR_SQ4_2               (0x4UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00004000 */
-#define ADC_CHSELR_SQ4_3               (0x8UL << ADC_CHSELR_SQ4_Pos)           /*!< 0x00008000 */
-
-#define ADC_CHSELR_SQ3_Pos             (8U)
-#define ADC_CHSELR_SQ3_Msk             (0xFUL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000F00 */
-#define ADC_CHSELR_SQ3                 ADC_CHSELR_SQ3_Msk                      /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ3_0               (0x1UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000100 */
-#define ADC_CHSELR_SQ3_1               (0x2UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000200 */
-#define ADC_CHSELR_SQ3_2               (0x4UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000400 */
-#define ADC_CHSELR_SQ3_3               (0x8UL << ADC_CHSELR_SQ3_Pos)           /*!< 0x00000800 */
-
-#define ADC_CHSELR_SQ2_Pos             (4U)
-#define ADC_CHSELR_SQ2_Msk             (0xFUL << ADC_CHSELR_SQ2_Pos)           /*!< 0x000000F0 */
-#define ADC_CHSELR_SQ2                 ADC_CHSELR_SQ2_Msk                      /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ2_0               (0x1UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000010 */
-#define ADC_CHSELR_SQ2_1               (0x2UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000020 */
-#define ADC_CHSELR_SQ2_2               (0x4UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000040 */
-#define ADC_CHSELR_SQ2_3               (0x8UL << ADC_CHSELR_SQ2_Pos)           /*!< 0x00000080 */
-
-#define ADC_CHSELR_SQ1_Pos             (0U)
-#define ADC_CHSELR_SQ1_Msk             (0xFUL << ADC_CHSELR_SQ1_Pos)           /*!< 0x0000000F */
-#define ADC_CHSELR_SQ1                 ADC_CHSELR_SQ1_Msk                      /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */
-#define ADC_CHSELR_SQ1_0               (0x1UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000001 */
-#define ADC_CHSELR_SQ1_1               (0x2UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000002 */
-#define ADC_CHSELR_SQ1_2               (0x4UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000004 */
-#define ADC_CHSELR_SQ1_3               (0x8UL << ADC_CHSELR_SQ1_Pos)           /*!< 0x00000008 */
-
-/********************  Bit definition for ADC_TR3 register  *******************/
-#define ADC_TR3_LT3_Pos                (0U)
-#define ADC_TR3_LT3_Msk                (0xFFFUL << ADC_TR3_LT3_Pos)            /*!< 0x00000FFF */
-#define ADC_TR3_LT3                    ADC_TR3_LT3_Msk                         /*!< ADC analog watchdog 3 threshold low */
-#define ADC_TR3_LT3_0                  (0x001UL << ADC_TR3_LT3_Pos)            /*!< 0x00000001 */
-#define ADC_TR3_LT3_1                  (0x002UL << ADC_TR3_LT3_Pos)            /*!< 0x00000002 */
-#define ADC_TR3_LT3_2                  (0x004UL << ADC_TR3_LT3_Pos)            /*!< 0x00000004 */
-#define ADC_TR3_LT3_3                  (0x008UL << ADC_TR3_LT3_Pos)            /*!< 0x00000008 */
-#define ADC_TR3_LT3_4                  (0x010UL << ADC_TR3_LT3_Pos)            /*!< 0x00000010 */
-#define ADC_TR3_LT3_5                  (0x020UL << ADC_TR3_LT3_Pos)            /*!< 0x00000020 */
-#define ADC_TR3_LT3_6                  (0x040UL << ADC_TR3_LT3_Pos)            /*!< 0x00000040 */
-#define ADC_TR3_LT3_7                  (0x080UL << ADC_TR3_LT3_Pos)            /*!< 0x00000080 */
-#define ADC_TR3_LT3_8                  (0x100UL << ADC_TR3_LT3_Pos)            /*!< 0x00000100 */
-#define ADC_TR3_LT3_9                  (0x200UL << ADC_TR3_LT3_Pos)            /*!< 0x00000200 */
-#define ADC_TR3_LT3_10                 (0x400UL << ADC_TR3_LT3_Pos)            /*!< 0x00000400 */
-#define ADC_TR3_LT3_11                 (0x800UL << ADC_TR3_LT3_Pos)            /*!< 0x00000800 */
-
-#define ADC_TR3_HT3_Pos                (16U)
-#define ADC_TR3_HT3_Msk                (0xFFFUL << ADC_TR3_HT3_Pos)            /*!< 0x0FFF0000 */
-#define ADC_TR3_HT3                    ADC_TR3_HT3_Msk                         /*!< ADC analog watchdog 3 threshold high */
-#define ADC_TR3_HT3_0                  (0x001UL << ADC_TR3_HT3_Pos)            /*!< 0x00010000 */
-#define ADC_TR3_HT3_1                  (0x002UL << ADC_TR3_HT3_Pos)            /*!< 0x00020000 */
-#define ADC_TR3_HT3_2                  (0x004UL << ADC_TR3_HT3_Pos)            /*!< 0x00040000 */
-#define ADC_TR3_HT3_3                  (0x008UL << ADC_TR3_HT3_Pos)            /*!< 0x00080000 */
-#define ADC_TR3_HT3_4                  (0x010UL << ADC_TR3_HT3_Pos)            /*!< 0x00100000 */
-#define ADC_TR3_HT3_5                  (0x020UL << ADC_TR3_HT3_Pos)            /*!< 0x00200000 */
-#define ADC_TR3_HT3_6                  (0x040UL << ADC_TR3_HT3_Pos)            /*!< 0x00400000 */
-#define ADC_TR3_HT3_7                  (0x080UL << ADC_TR3_HT3_Pos)            /*!< 0x00800000 */
-#define ADC_TR3_HT3_8                  (0x100UL << ADC_TR3_HT3_Pos)            /*!< 0x01000000 */
-#define ADC_TR3_HT3_9                  (0x200UL << ADC_TR3_HT3_Pos)            /*!< 0x02000000 */
-#define ADC_TR3_HT3_10                 (0x400UL << ADC_TR3_HT3_Pos)            /*!< 0x04000000 */
-#define ADC_TR3_HT3_11                 (0x800UL << ADC_TR3_HT3_Pos)            /*!< 0x08000000 */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos                (0U)
-#define ADC_DR_DATA_Msk                (0xFFFFUL << ADC_DR_DATA_Pos)           /*!< 0x0000FFFF */
-#define ADC_DR_DATA                    ADC_DR_DATA_Msk                         /*!< ADC group regular conversion data */
-#define ADC_DR_DATA_0                  (0x0001UL << ADC_DR_DATA_Pos)           /*!< 0x00000001 */
-#define ADC_DR_DATA_1                  (0x0002UL << ADC_DR_DATA_Pos)           /*!< 0x00000002 */
-#define ADC_DR_DATA_2                  (0x0004UL << ADC_DR_DATA_Pos)           /*!< 0x00000004 */
-#define ADC_DR_DATA_3                  (0x0008UL << ADC_DR_DATA_Pos)           /*!< 0x00000008 */
-#define ADC_DR_DATA_4                  (0x0010UL << ADC_DR_DATA_Pos)           /*!< 0x00000010 */
-#define ADC_DR_DATA_5                  (0x0020UL << ADC_DR_DATA_Pos)           /*!< 0x00000020 */
-#define ADC_DR_DATA_6                  (0x0040UL << ADC_DR_DATA_Pos)           /*!< 0x00000040 */
-#define ADC_DR_DATA_7                  (0x0080UL << ADC_DR_DATA_Pos)           /*!< 0x00000080 */
-#define ADC_DR_DATA_8                  (0x0100UL << ADC_DR_DATA_Pos)           /*!< 0x00000100 */
-#define ADC_DR_DATA_9                  (0x0200UL << ADC_DR_DATA_Pos)           /*!< 0x00000200 */
-#define ADC_DR_DATA_10                 (0x0400UL << ADC_DR_DATA_Pos)           /*!< 0x00000400 */
-#define ADC_DR_DATA_11                 (0x0800UL << ADC_DR_DATA_Pos)           /*!< 0x00000800 */
-#define ADC_DR_DATA_12                 (0x1000UL << ADC_DR_DATA_Pos)           /*!< 0x00001000 */
-#define ADC_DR_DATA_13                 (0x2000UL << ADC_DR_DATA_Pos)           /*!< 0x00002000 */
-#define ADC_DR_DATA_14                 (0x4000UL << ADC_DR_DATA_Pos)           /*!< 0x00004000 */
-#define ADC_DR_DATA_15                 (0x8000UL << ADC_DR_DATA_Pos)           /*!< 0x00008000 */
-
-/********************  Bit definition for ADC_AWD2CR register  ****************/
-#define ADC_AWD2CR_AWD2CH_Pos          (0U)
-#define ADC_AWD2CR_AWD2CH_Msk          (0x3FFFFUL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x0003FFFF */
-#define ADC_AWD2CR_AWD2CH              ADC_AWD2CR_AWD2CH_Msk                   /*!< ADC analog watchdog 2 monitored channel selection */
-#define ADC_AWD2CR_AWD2CH_0            (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000001 */
-#define ADC_AWD2CR_AWD2CH_1            (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000002 */
-#define ADC_AWD2CR_AWD2CH_2            (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000004 */
-#define ADC_AWD2CR_AWD2CH_3            (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000008 */
-#define ADC_AWD2CR_AWD2CH_4            (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000010 */
-#define ADC_AWD2CR_AWD2CH_5            (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000020 */
-#define ADC_AWD2CR_AWD2CH_6            (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000040 */
-#define ADC_AWD2CR_AWD2CH_7            (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000080 */
-#define ADC_AWD2CR_AWD2CH_8            (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000100 */
-#define ADC_AWD2CR_AWD2CH_9            (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000200 */
-#define ADC_AWD2CR_AWD2CH_10           (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000400 */
-#define ADC_AWD2CR_AWD2CH_11           (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00000800 */
-#define ADC_AWD2CR_AWD2CH_12           (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00001000 */
-#define ADC_AWD2CR_AWD2CH_13           (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00002000 */
-#define ADC_AWD2CR_AWD2CH_14           (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00004000 */
-#define ADC_AWD2CR_AWD2CH_15           (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00008000 */
-#define ADC_AWD2CR_AWD2CH_16           (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00010000 */
-#define ADC_AWD2CR_AWD2CH_17           (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)    /*!< 0x00020000 */
-
-/********************  Bit definition for ADC_AWD3CR register  ****************/
-#define ADC_AWD3CR_AWD3CH_Pos          (0U)
-#define ADC_AWD3CR_AWD3CH_Msk          (0x3FFFFUL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x0003FFFF */
-#define ADC_AWD3CR_AWD3CH              ADC_AWD3CR_AWD3CH_Msk                   /*!< ADC analog watchdog 3 monitored channel selection */
-#define ADC_AWD3CR_AWD3CH_0            (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000001 */
-#define ADC_AWD3CR_AWD3CH_1            (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000002 */
-#define ADC_AWD3CR_AWD3CH_2            (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000004 */
-#define ADC_AWD3CR_AWD3CH_3            (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000008 */
-#define ADC_AWD3CR_AWD3CH_4            (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000010 */
-#define ADC_AWD3CR_AWD3CH_5            (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000020 */
-#define ADC_AWD3CR_AWD3CH_6            (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000040 */
-#define ADC_AWD3CR_AWD3CH_7            (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000080 */
-#define ADC_AWD3CR_AWD3CH_8            (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000100 */
-#define ADC_AWD3CR_AWD3CH_9            (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000200 */
-#define ADC_AWD3CR_AWD3CH_10           (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000400 */
-#define ADC_AWD3CR_AWD3CH_11           (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00000800 */
-#define ADC_AWD3CR_AWD3CH_12           (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00001000 */
-#define ADC_AWD3CR_AWD3CH_13           (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00002000 */
-#define ADC_AWD3CR_AWD3CH_14           (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00004000 */
-#define ADC_AWD3CR_AWD3CH_15           (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00008000 */
-#define ADC_AWD3CR_AWD3CH_16           (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00010000 */
-#define ADC_AWD3CR_AWD3CH_17           (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)    /*!< 0x00020000 */
-
-/********************  Bit definition for ADC_CALFACT register  ***************/
-#define ADC_CALFACT_CALFACT_Pos        (0U)
-#define ADC_CALFACT_CALFACT_Msk        (0x7FUL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x0000007F */
-#define ADC_CALFACT_CALFACT            ADC_CALFACT_CALFACT_Msk                 /*!< ADC calibration factor in single-ended mode */
-#define ADC_CALFACT_CALFACT_0          (0x01UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000001 */
-#define ADC_CALFACT_CALFACT_1          (0x02UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000002 */
-#define ADC_CALFACT_CALFACT_2          (0x04UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000004 */
-#define ADC_CALFACT_CALFACT_3          (0x08UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000008 */
-#define ADC_CALFACT_CALFACT_4          (0x10UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000010 */
-#define ADC_CALFACT_CALFACT_5          (0x20UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000020 */
-#define ADC_CALFACT_CALFACT_6          (0x40UL << ADC_CALFACT_CALFACT_Pos)     /*!< 0x00000040 */
-
-/*************************  ADC Common registers  *****************************/
-/********************  Bit definition for ADC_CCR register  *******************/
-#define ADC_CCR_PRESC_Pos              (18U)
-#define ADC_CCR_PRESC_Msk              (0xFUL << ADC_CCR_PRESC_Pos)            /*!< 0x003C0000 */
-#define ADC_CCR_PRESC                  ADC_CCR_PRESC_Msk                       /*!< ADC common clock prescaler, only for clock source asynchronous */
-#define ADC_CCR_PRESC_0                (0x1UL << ADC_CCR_PRESC_Pos)            /*!< 0x00040000 */
-#define ADC_CCR_PRESC_1                (0x2UL << ADC_CCR_PRESC_Pos)            /*!< 0x00080000 */
-#define ADC_CCR_PRESC_2                (0x4UL << ADC_CCR_PRESC_Pos)            /*!< 0x00100000 */
-#define ADC_CCR_PRESC_3                (0x8UL << ADC_CCR_PRESC_Pos)            /*!< 0x00200000 */
-
-#define ADC_CCR_VREFEN_Pos             (22U)
-#define ADC_CCR_VREFEN_Msk             (0x1UL << ADC_CCR_VREFEN_Pos)           /*!< 0x00400000 */
-#define ADC_CCR_VREFEN                 ADC_CCR_VREFEN_Msk                      /*!< ADC internal path to VrefInt enable */
-#define ADC_CCR_TSEN_Pos               (23U)
-#define ADC_CCR_TSEN_Msk               (0x1UL << ADC_CCR_TSEN_Pos)             /*!< 0x00800000 */
-#define ADC_CCR_TSEN                   ADC_CCR_TSEN_Msk                        /*!< ADC internal path to temperature sensor enable */
-#define ADC_CCR_VBATEN_Pos             (24U)
-#define ADC_CCR_VBATEN_Msk             (0x1UL << ADC_CCR_VBATEN_Pos)           /*!< 0x01000000 */
-#define ADC_CCR_VBATEN                 ADC_CCR_VBATEN_Msk                      /*!< ADC internal path to battery voltage enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/**********************  Bit definition for COMP_CSR register  ****************/
-#define COMP_CSR_EN_Pos            (0U)
-#define COMP_CSR_EN_Msk            (0x1UL << COMP_CSR_EN_Pos)                  /*!< 0x00000001 */
-#define COMP_CSR_EN                COMP_CSR_EN_Msk                             /*!< Comparator enable */
-
-#define COMP_CSR_PWRMODE_Pos       (2U)
-#define COMP_CSR_PWRMODE_Msk       (0x3UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x0000000C */
-#define COMP_CSR_PWRMODE           COMP_CSR_PWRMODE_Msk                        /*!< Comparator power mode */
-#define COMP_CSR_PWRMODE_0         (0x1UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000004 */
-#define COMP_CSR_PWRMODE_1         (0x2UL << COMP_CSR_PWRMODE_Pos)             /*!< 0x00000008 */
-
-#define COMP_CSR_INMSEL_Pos        (4U)
-#define COMP_CSR_INMSEL_Msk        (0x7UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000070 */
-#define COMP_CSR_INMSEL            COMP_CSR_INMSEL_Msk                         /*!< Comparator input minus selection */
-#define COMP_CSR_INMSEL_0          (0x1UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000010 */
-#define COMP_CSR_INMSEL_1          (0x2UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000020 */
-#define COMP_CSR_INMSEL_2          (0x4UL << COMP_CSR_INMSEL_Pos)              /*!< 0x00000040 */
-
-#define COMP_CSR_INPSEL_Pos        (7U)
-#define COMP_CSR_INPSEL_Msk        (0x3UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000180 */
-#define COMP_CSR_INPSEL            COMP_CSR_INPSEL_Msk                         /*!< Comparator input plus selection */
-#define COMP_CSR_INPSEL_0          (0x1UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000080 */
-#define COMP_CSR_INPSEL_1          (0x2UL << COMP_CSR_INPSEL_Pos)              /*!< 0x00000100 */
-
-#define COMP_CSR_WINMODE_Pos       (9U)
-#define COMP_CSR_WINMODE_Msk       (0x1UL << COMP_CSR_WINMODE_Pos)             /*!< 0x00000200 */
-#define COMP_CSR_WINMODE           COMP_CSR_WINMODE_Msk                        /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
-
-#define COMP_CSR_POLARITY_Pos      (15U)
-#define COMP_CSR_POLARITY_Msk      (0x1UL << COMP_CSR_POLARITY_Pos)            /*!< 0x00008000 */
-#define COMP_CSR_POLARITY          COMP_CSR_POLARITY_Msk                       /*!< Comparator output polarity */
-
-#define COMP_CSR_HYST_Pos          (16U)
-#define COMP_CSR_HYST_Msk          (0x3UL << COMP_CSR_HYST_Pos)                /*!< 0x00030000 */
-#define COMP_CSR_HYST              COMP_CSR_HYST_Msk                           /*!< Comparator hysteresis */
-#define COMP_CSR_HYST_0            (0x1UL << COMP_CSR_HYST_Pos)                /*!< 0x00010000 */
-#define COMP_CSR_HYST_1            (0x2UL << COMP_CSR_HYST_Pos)                /*!< 0x00020000 */
-
-#define COMP_CSR_BLANKING_Pos      (18U)
-#define COMP_CSR_BLANKING_Msk      (0x7UL << COMP_CSR_BLANKING_Pos)            /*!< 0x001C0000 */
-#define COMP_CSR_BLANKING          COMP_CSR_BLANKING_Msk                       /*!< Comparator blanking source */
-#define COMP_CSR_BLANKING_0        (0x1UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00040000 */
-#define COMP_CSR_BLANKING_1        (0x2UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00080000 */
-#define COMP_CSR_BLANKING_2        (0x4UL << COMP_CSR_BLANKING_Pos)            /*!< 0x00100000 */
-
-#define COMP_CSR_BRGEN_Pos         (22U)
-#define COMP_CSR_BRGEN_Msk         (0x1UL << COMP_CSR_BRGEN_Pos)               /*!< 0x00400000 */
-#define COMP_CSR_BRGEN             COMP_CSR_BRGEN_Msk                          /*!< Comparator voltage scaler enable */
-#define COMP_CSR_SCALEN_Pos        (23U)
-#define COMP_CSR_SCALEN_Msk        (0x1UL << COMP_CSR_SCALEN_Pos)              /*!< 0x00800000 */
-#define COMP_CSR_SCALEN            COMP_CSR_SCALEN_Msk                         /*!< Comparator scaler bridge enable */
-
-#define COMP_CSR_INMESEL_Pos       (25U)
-#define COMP_CSR_INMESEL_Msk       (0x3UL << COMP_CSR_INMESEL_Pos)             /*!< 0x06000000 */
-#define COMP_CSR_INMESEL           COMP_CSR_INMESEL_Msk                        /*!< Comparator input minus extended selection */
-#define COMP_CSR_INMESEL_0         (0x1UL << COMP_CSR_INMESEL_Pos)             /*!< 0x02000000 */
-#define COMP_CSR_INMESEL_1         (0x2UL << COMP_CSR_INMESEL_Pos)             /*!< 0x04000000 */
-
-#define COMP_CSR_VALUE_Pos         (30U)
-#define COMP_CSR_VALUE_Msk         (0x1UL << COMP_CSR_VALUE_Pos)               /*!< 0x40000000 */
-#define COMP_CSR_VALUE             COMP_CSR_VALUE_Msk                          /*!< Comparator output level */
-
-#define COMP_CSR_LOCK_Pos          (31U)
-#define COMP_CSR_LOCK_Msk          (0x1UL << COMP_CSR_LOCK_Pos)                /*!< 0x80000000 */
-#define COMP_CSR_LOCK              COMP_CSR_LOCK_Msk                           /*!< Comparator lock */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/*
-* @brief Specific device feature definitions
-*/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)
-#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
-#define DAC_CR_TEN1_Pos             (1U)
-#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (2U)
-#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000004 */
-#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */
-#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */
-#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)
-#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)
-#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)
-#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)
-#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
-#define DAC_CR_CEN1_Pos             (14U)
-#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
-#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos    (0U)
-#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos    (4U)
-#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos     (0U)
-#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos       (0U)
-#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)
-#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_CAL_FLAG1_Pos        (14U)
-#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
-#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
-#define DAC_SR_BWST1_Pos            (15U)
-#define DAC_SR_BWST1_Msk            (0x1UL << DAC_SR_BWST1_Pos)                /*!< 0x00008000 */
-#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */
-
-/*******************  Bit definition for DAC_CCR register  ********************/
-#define DAC_CCR_OTRIM1_Pos          (0U)
-#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
-#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
-
-/*******************  Bit definition for DAC_MCR register  *******************/
-#define DAC_MCR_MODE1_Pos           (0U)
-#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
-#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
-#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */
-#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */
-#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */
-
-/******************  Bit definition for DAC_SHSR1 register  ******************/
-#define DAC_SHSR1_TSAMPLE1_Pos      (0U)
-#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
-#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
-
-/******************  Bit definition for DAC_SHHR register  ******************/
-#define DAC_SHHR_THOLD1_Pos         (0U)
-#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
-#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
-
-/******************  Bit definition for DAC_SHRR register  ******************/
-#define DAC_SHRR_TREFRESH1_Pos      (0U)
-#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
-#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM_Pos          (0U)
-#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */
-#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */
-#define LPTIM_ISR_ARRM_Pos          (1U)
-#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */
-#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG_Pos       (2U)
-#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */
-#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK_Pos         (3U)
-#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */
-#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK_Pos         (4U)
-#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */
-#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP_Pos            (5U)
-#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */
-#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN_Pos          (6U)
-#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */
-#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */
-#define LPTIM_ISR_UE_Pos            (7U)
-#define LPTIM_ISR_UE_Msk            (0x1UL << LPTIM_ISR_UE_Pos)                /*!< 0x00000080 */
-#define LPTIM_ISR_UE                LPTIM_ISR_UE_Msk                           /*!< Update event occurrence */
-#define LPTIM_ISR_REPOK_Pos         (8U)
-#define LPTIM_ISR_REPOK_Msk         (0x1UL << LPTIM_ISR_REPOK_Pos)              /*!< 0x00000100 */
-#define LPTIM_ISR_REPOK             LPTIM_ISR_REPOK_Msk                         /*!< Repetition register update OK */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF_Pos        (0U)
-#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */
-#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF_Pos        (1U)
-#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */
-#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)
-#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */
-#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF_Pos       (3U)
-#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */
-#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF_Pos       (4U)
-#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */
-#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF_Pos          (5U)
-#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */
-#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF_Pos        (6U)
-#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */
-#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */
-#define LPTIM_ICR_UECF_Pos          (7U)
-#define LPTIM_ICR_UECF_Msk          (0x1UL << LPTIM_ICR_UECF_Pos)              /*!< 0x00000080 */
-#define LPTIM_ICR_UECF              LPTIM_ICR_UECF_Msk                         /*!< Update event Clear Flag */
-#define LPTIM_ICR_REPOKCF_Pos       (8U)
-#define LPTIM_ICR_REPOKCF_Msk       (0x1UL << LPTIM_ICR_REPOKCF_Pos)           /*!< 0x00000100 */
-#define LPTIM_ICR_REPOKCF           LPTIM_ICR_REPOKCF_Msk                      /*!< Repetition register update OK Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE_Pos        (0U)
-#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */
-#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE_Pos        (1U)
-#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */
-#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE_Pos     (2U)
-#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */
-#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE_Pos       (3U)
-#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */
-#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE_Pos       (4U)
-#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */
-#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE_Pos          (5U)
-#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */
-#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE_Pos        (6U)
-#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */
-#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */
-#define LPTIM_IER_UEIE_Pos          (7U)
-#define LPTIM_IER_UEIE_Msk          (0x1UL << LPTIM_IER_UEIE_Pos)              /*!< 0x00000080 */
-#define LPTIM_IER_UEIE              LPTIM_IER_UEIE_Msk                         /*!< Update event Interrupt Enable */
-#define LPTIM_IER_REPOKIE_Pos       (8U)
-#define LPTIM_IER_REPOKIE_Msk       (0x1UL << LPTIM_IER_REPOKIE_Pos)           /*!< 0x00000100 */
-#define LPTIM_IER_REPOKIE           LPTIM_IER_REPOKIE_Msk                      /*!< Repetition register update OK Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL_Pos        (0U)
-#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */
-#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL_Pos        (1U)
-#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */
-#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000002 */
-#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000004 */
-
-#define LPTIM_CFGR_CKFLT_Pos        (3U)
-#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */
-#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000008 */
-#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000010 */
-
-#define LPTIM_CFGR_TRGFLT_Pos       (6U)
-#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */
-#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000040 */
-#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x00000080 */
-
-#define LPTIM_CFGR_PRESC_Pos        (9U)
-#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */
-#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000200 */
-#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000400 */
-#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000800 */
-
-#define LPTIM_CFGR_TRIGSEL_Pos      (13U)
-#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */
-#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00002000 */
-#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00004000 */
-#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x00008000 */
-
-#define LPTIM_CFGR_TRIGEN_Pos       (17U)
-#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */
-#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00020000 */
-#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00040000 */
-
-#define LPTIM_CFGR_TIMOUT_Pos       (19U)
-#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */
-#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */
-#define LPTIM_CFGR_WAVE_Pos         (20U)
-#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */
-#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL_Pos       (21U)
-#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */
-#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD_Pos      (22U)
-#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */
-#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE_Pos    (23U)
-#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */
-#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC_Pos          (24U)
-#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */
-#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE_Pos         (0U)
-#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */
-#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT_Pos        (1U)
-#define LPTIM_CR_SNGSTRT_Msk        (0x1UL << LPTIM_CR_SNGSTRT_Pos)            /*!< 0x00000002 */
-#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT_Pos        (2U)
-#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */
-#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */
-#define LPTIM_CR_COUNTRST_Pos       (3U)
-#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */
-#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Counter reset */
-#define LPTIM_CR_RSTARE_Pos         (4U)
-#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */
-#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Reset after read enable */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP_Pos           (0U)
-#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */
-#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR_Pos           (0U)
-#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */
-#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT_Pos           (0U)
-#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */
-#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */
-
-/******************  Bit definition for LPTIM_OR register  ********************/
-#define LPTIM_OR_OR_Pos             (0U)
-#define LPTIM_OR_OR_Msk             (0x3UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000003 */
-#define LPTIM_OR_OR                 LPTIM_OR_OR_Msk                            /*!< OR[1:0] bits (Remap selection) */
-#define LPTIM_OR_OR_0               (0x1UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000001 */
-#define LPTIM_OR_OR_1               (0x2UL << LPTIM_OR_OR_Pos)                 /*!< 0x00000002 */
-
-/******************  Bit definition for LPTIM_RCR register  *******************/
-#define LPTIM_RCR_REP_Pos           (0U)
-#define LPTIM_RCR_REP_Msk           (0xFFUL << LPTIM_RCR_REP_Pos)              /*!< 0x000000FF */
-#define LPTIM_RCR_REP               LPTIM_RCR_REP_Msk                          /*!<Repetition Counter Value */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE_Pos             (0U)
-#define USART_CR1_UE_Msk             (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00000001 */
-#define USART_CR1_UE                 USART_CR1_UE_Msk                          /*!< USART Enable */
-#define USART_CR1_UESM_Pos           (1U)
-#define USART_CR1_UESM_Msk           (0x1UL << USART_CR1_UESM_Pos)             /*!< 0x00000002 */
-#define USART_CR1_UESM               USART_CR1_UESM_Msk                        /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE_Pos             (2U)
-#define USART_CR1_RE_Msk             (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                 USART_CR1_RE_Msk                          /*!< Receiver Enable */
-#define USART_CR1_TE_Pos             (3U)
-#define USART_CR1_TE_Msk             (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                 USART_CR1_TE_Msk                          /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE_Pos         (4U)
-#define USART_CR1_IDLEIE_Msk         (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE             USART_CR1_IDLEIE_Msk                      /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE_RXFNEIE_Pos   (5U)
-#define USART_CR1_RXNEIE_RXFNEIE_Msk   (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
-#define USART_CR1_RXNEIE_RXFNEIE       USART_CR1_RXNEIE_RXFNEIE_Msk            /*!< RXNE/RXFIFO not empty Interrupt Enable */
-#define USART_CR1_TCIE_Pos           (6U)
-#define USART_CR1_TCIE_Msk           (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE               USART_CR1_TCIE_Msk                        /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_TXFNFIE_Pos  (7U)
-#define USART_CR1_TXEIE_TXFNFIE_Msk   (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)   /*!< 0x00000080 */
-#define USART_CR1_TXEIE_TXFNFIE       USART_CR1_TXEIE_TXFNFIE_Msk              /*!< TXE/TXFIFO not full Interrupt Enable */
-#define USART_CR1_PEIE_Pos           (8U)
-#define USART_CR1_PEIE_Msk           (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE               USART_CR1_PEIE_Msk                        /*!< PE Interrupt Enable */
-#define USART_CR1_PS_Pos             (9U)
-#define USART_CR1_PS_Msk             (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                 USART_CR1_PS_Msk                          /*!< Parity Selection */
-#define USART_CR1_PCE_Pos            (10U)
-#define USART_CR1_PCE_Msk            (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                USART_CR1_PCE_Msk                         /*!< Parity Control Enable */
-#define USART_CR1_WAKE_Pos           (11U)
-#define USART_CR1_WAKE_Msk           (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE               USART_CR1_WAKE_Msk                        /*!< Receiver Wakeup method */
-#define USART_CR1_M_Pos              (12U)
-#define USART_CR1_M_Msk              (0x10001UL << USART_CR1_M_Pos)            /*!< 0x10001000 */
-#define USART_CR1_M                  USART_CR1_M_Msk                           /*!< Word length */
-#define USART_CR1_M0_Pos             (12U)
-#define USART_CR1_M0_Msk             (0x1UL << USART_CR1_M0_Pos)               /*!< 0x00001000 */
-#define USART_CR1_M0                 USART_CR1_M0_Msk                          /*!< Word length - Bit 0 */
-#define USART_CR1_MME_Pos            (13U)
-#define USART_CR1_MME_Msk            (0x1UL << USART_CR1_MME_Pos)              /*!< 0x00002000 */
-#define USART_CR1_MME                USART_CR1_MME_Msk                         /*!< Mute Mode Enable */
-#define USART_CR1_CMIE_Pos           (14U)
-#define USART_CR1_CMIE_Msk           (0x1UL << USART_CR1_CMIE_Pos)             /*!< 0x00004000 */
-#define USART_CR1_CMIE               USART_CR1_CMIE_Msk                        /*!< Character match interrupt enable */
-#define USART_CR1_OVER8_Pos          (15U)
-#define USART_CR1_OVER8_Msk          (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8              USART_CR1_OVER8_Msk                       /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT_Pos           (16U)
-#define USART_CR1_DEDT_Msk           (0x1FUL << USART_CR1_DEDT_Pos)            /*!< 0x001F0000 */
-#define USART_CR1_DEDT               USART_CR1_DEDT_Msk                        /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0             (0x01UL << USART_CR1_DEDT_Pos)            /*!< 0x00010000 */
-#define USART_CR1_DEDT_1             (0x02UL << USART_CR1_DEDT_Pos)            /*!< 0x00020000 */
-#define USART_CR1_DEDT_2             (0x04UL << USART_CR1_DEDT_Pos)            /*!< 0x00040000 */
-#define USART_CR1_DEDT_3             (0x08UL << USART_CR1_DEDT_Pos)            /*!< 0x00080000 */
-#define USART_CR1_DEDT_4             (0x10UL << USART_CR1_DEDT_Pos)            /*!< 0x00100000 */
-#define USART_CR1_DEAT_Pos           (21U)
-#define USART_CR1_DEAT_Msk           (0x1FUL << USART_CR1_DEAT_Pos)            /*!< 0x03E00000 */
-#define USART_CR1_DEAT               USART_CR1_DEAT_Msk                        /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0             (0x01UL << USART_CR1_DEAT_Pos)            /*!< 0x00200000 */
-#define USART_CR1_DEAT_1             (0x02UL << USART_CR1_DEAT_Pos)            /*!< 0x00400000 */
-#define USART_CR1_DEAT_2             (0x04UL << USART_CR1_DEAT_Pos)            /*!< 0x00800000 */
-#define USART_CR1_DEAT_3             (0x08UL << USART_CR1_DEAT_Pos)            /*!< 0x01000000 */
-#define USART_CR1_DEAT_4             (0x10UL << USART_CR1_DEAT_Pos)            /*!< 0x02000000 */
-#define USART_CR1_RTOIE_Pos          (26U)
-#define USART_CR1_RTOIE_Msk          (0x1UL << USART_CR1_RTOIE_Pos)            /*!< 0x04000000 */
-#define USART_CR1_RTOIE              USART_CR1_RTOIE_Msk                       /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE_Pos          (27U)
-#define USART_CR1_EOBIE_Msk          (0x1UL << USART_CR1_EOBIE_Pos)            /*!< 0x08000000 */
-#define USART_CR1_EOBIE              USART_CR1_EOBIE_Msk                       /*!< End of Block interrupt enable */
-#define USART_CR1_M1_Pos             (28U)
-#define USART_CR1_M1_Msk             (0x1UL << USART_CR1_M1_Pos)               /*!< 0x10000000 */
-#define USART_CR1_M1                 USART_CR1_M1_Msk                          /*!< Word length - Bit 1 */
-#define USART_CR1_FIFOEN_Pos         (29U)
-#define USART_CR1_FIFOEN_Msk         (0x1UL << USART_CR1_FIFOEN_Pos)           /*!< 0x20000000 */
-#define USART_CR1_FIFOEN             USART_CR1_FIFOEN_Msk                      /*!< FIFO mode enable */
-#define USART_CR1_TXFEIE_Pos         (30U)
-#define USART_CR1_TXFEIE_Msk         (0x1UL << USART_CR1_TXFEIE_Pos)           /*!< 0x40000000 */
-#define USART_CR1_TXFEIE             USART_CR1_TXFEIE_Msk                      /*!< TXFIFO empty interrupt enable */
-#define USART_CR1_RXFFIE_Pos         (31U)
-#define USART_CR1_RXFFIE_Msk         (0x1UL << USART_CR1_RXFFIE_Pos)           /*!< 0x80000000 */
-#define USART_CR1_RXFFIE             USART_CR1_RXFFIE_Msk                      /*!< RXFIFO Full interrupt enable */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_SLVEN_Pos          (0U)
-#define USART_CR2_SLVEN_Msk          (0x1UL << USART_CR2_SLVEN_Pos)            /*!< 0x00000001 */
-#define USART_CR2_SLVEN              USART_CR2_SLVEN_Msk                       /*!< Synchronous Slave mode enable */
-#define USART_CR2_DIS_NSS_Pos        (3U)
-#define USART_CR2_DIS_NSS_Msk        (0x1UL << USART_CR2_DIS_NSS_Pos)          /*!< 0x00000008 */
-#define USART_CR2_DIS_NSS            USART_CR2_DIS_NSS_Msk                     /*!< NSS input pin disable for SPI slave selection */
-#define USART_CR2_ADDM7_Pos          (4U)
-#define USART_CR2_ADDM7_Msk          (0x1UL << USART_CR2_ADDM7_Pos)            /*!< 0x00000010 */
-#define USART_CR2_ADDM7              USART_CR2_ADDM7_Msk                       /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL_Pos           (5U)
-#define USART_CR2_LBDL_Msk           (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL               USART_CR2_LBDL_Msk                        /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE_Pos          (6U)
-#define USART_CR2_LBDIE_Msk          (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE              USART_CR2_LBDIE_Msk                       /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos           (8U)
-#define USART_CR2_LBCL_Msk           (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL               USART_CR2_LBCL_Msk                        /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA_Pos           (9U)
-#define USART_CR2_CPHA_Msk           (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA               USART_CR2_CPHA_Msk                        /*!< Clock Phase */
-#define USART_CR2_CPOL_Pos           (10U)
-#define USART_CR2_CPOL_Msk           (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL               USART_CR2_CPOL_Msk                        /*!< Clock Polarity */
-#define USART_CR2_CLKEN_Pos          (11U)
-#define USART_CR2_CLKEN_Msk          (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN              USART_CR2_CLKEN_Msk                       /*!< Clock Enable */
-#define USART_CR2_STOP_Pos           (12U)
-#define USART_CR2_STOP_Msk           (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP               USART_CR2_STOP_Msk                        /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0             (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x00001000 */
-#define USART_CR2_STOP_1             (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x00002000 */
-#define USART_CR2_LINEN_Pos          (14U)
-#define USART_CR2_LINEN_Msk          (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN              USART_CR2_LINEN_Msk                       /*!< LIN mode enable */
-#define USART_CR2_SWAP_Pos           (15U)
-#define USART_CR2_SWAP_Msk           (0x1UL << USART_CR2_SWAP_Pos)             /*!< 0x00008000 */
-#define USART_CR2_SWAP               USART_CR2_SWAP_Msk                        /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV_Pos          (16U)
-#define USART_CR2_RXINV_Msk          (0x1UL << USART_CR2_RXINV_Pos)            /*!< 0x00010000 */
-#define USART_CR2_RXINV              USART_CR2_RXINV_Msk                       /*!< RX pin active level inversion */
-#define USART_CR2_TXINV_Pos          (17U)
-#define USART_CR2_TXINV_Msk          (0x1UL << USART_CR2_TXINV_Pos)            /*!< 0x00020000 */
-#define USART_CR2_TXINV              USART_CR2_TXINV_Msk                       /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV_Pos        (18U)
-#define USART_CR2_DATAINV_Msk        (0x1UL << USART_CR2_DATAINV_Pos)          /*!< 0x00040000 */
-#define USART_CR2_DATAINV            USART_CR2_DATAINV_Msk                     /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST_Pos       (19U)
-#define USART_CR2_MSBFIRST_Msk       (0x1UL << USART_CR2_MSBFIRST_Pos)         /*!< 0x00080000 */
-#define USART_CR2_MSBFIRST           USART_CR2_MSBFIRST_Msk                    /*!< Most Significant Bit First */
-#define USART_CR2_ABREN_Pos          (20U)
-#define USART_CR2_ABREN_Msk          (0x1UL << USART_CR2_ABREN_Pos)            /*!< 0x00100000 */
-#define USART_CR2_ABREN              USART_CR2_ABREN_Msk                       /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE_Pos        (21U)
-#define USART_CR2_ABRMODE_Msk        (0x3UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00600000 */
-#define USART_CR2_ABRMODE            USART_CR2_ABRMODE_Msk                     /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0          (0x1UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00200000 */
-#define USART_CR2_ABRMODE_1          (0x2UL << USART_CR2_ABRMODE_Pos)          /*!< 0x00400000 */
-#define USART_CR2_RTOEN_Pos          (23U)
-#define USART_CR2_RTOEN_Msk          (0x1UL << USART_CR2_RTOEN_Pos)            /*!< 0x00800000 */
-#define USART_CR2_RTOEN              USART_CR2_RTOEN_Msk                       /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD_Pos            (24U)
-#define USART_CR2_ADD_Msk            (0xFFUL << USART_CR2_ADD_Pos)             /*!< 0xFF000000 */
-#define USART_CR2_ADD                USART_CR2_ADD_Msk                         /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos            (0U)
-#define USART_CR3_EIE_Msk            (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                USART_CR3_EIE_Msk                         /*!< Error Interrupt Enable */
-#define USART_CR3_IREN_Pos           (1U)
-#define USART_CR3_IREN_Msk           (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN               USART_CR3_IREN_Msk                        /*!< IrDA mode Enable */
-#define USART_CR3_IRLP_Pos           (2U)
-#define USART_CR3_IRLP_Msk           (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP               USART_CR3_IRLP_Msk                        /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL_Pos          (3U)
-#define USART_CR3_HDSEL_Msk          (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL              USART_CR3_HDSEL_Msk                       /*!< Half-Duplex Selection */
-#define USART_CR3_NACK_Pos           (4U)
-#define USART_CR3_NACK_Msk           (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK               USART_CR3_NACK_Msk                        /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN_Pos           (5U)
-#define USART_CR3_SCEN_Msk           (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN               USART_CR3_SCEN_Msk                        /*!< SmartCard mode enable */
-#define USART_CR3_DMAR_Pos           (6U)
-#define USART_CR3_DMAR_Msk           (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR               USART_CR3_DMAR_Msk                        /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT_Pos           (7U)
-#define USART_CR3_DMAT_Msk           (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT               USART_CR3_DMAT_Msk                        /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE_Pos           (8U)
-#define USART_CR3_RTSE_Msk           (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE               USART_CR3_RTSE_Msk                        /*!< RTS Enable */
-#define USART_CR3_CTSE_Pos           (9U)
-#define USART_CR3_CTSE_Msk           (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE               USART_CR3_CTSE_Msk                        /*!< CTS Enable */
-#define USART_CR3_CTSIE_Pos          (10U)
-#define USART_CR3_CTSIE_Msk          (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE              USART_CR3_CTSIE_Msk                       /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT_Pos         (11U)
-#define USART_CR3_ONEBIT_Msk         (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT             USART_CR3_ONEBIT_Msk                      /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS_Pos         (12U)
-#define USART_CR3_OVRDIS_Msk         (0x1UL << USART_CR3_OVRDIS_Pos)           /*!< 0x00001000 */
-#define USART_CR3_OVRDIS             USART_CR3_OVRDIS_Msk                      /*!< Overrun Disable */
-#define USART_CR3_DDRE_Pos           (13U)
-#define USART_CR3_DDRE_Msk           (0x1UL << USART_CR3_DDRE_Pos)             /*!< 0x00002000 */
-#define USART_CR3_DDRE               USART_CR3_DDRE_Msk                        /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM_Pos            (14U)
-#define USART_CR3_DEM_Msk            (0x1UL << USART_CR3_DEM_Pos)              /*!< 0x00004000 */
-#define USART_CR3_DEM                USART_CR3_DEM_Msk                         /*!< Driver Enable Mode */
-#define USART_CR3_DEP_Pos            (15U)
-#define USART_CR3_DEP_Msk            (0x1UL << USART_CR3_DEP_Pos)              /*!< 0x00008000 */
-#define USART_CR3_DEP                USART_CR3_DEP_Msk                         /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT_Pos        (17U)
-#define USART_CR3_SCARCNT_Msk        (0x7UL << USART_CR3_SCARCNT_Pos)          /*!< 0x000E0000 */
-#define USART_CR3_SCARCNT            USART_CR3_SCARCNT_Msk                     /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0          (0x1UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00020000 */
-#define USART_CR3_SCARCNT_1          (0x2UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00040000 */
-#define USART_CR3_SCARCNT_2          (0x4UL << USART_CR3_SCARCNT_Pos)          /*!< 0x00080000 */
-#define USART_CR3_WUS_Pos            (20U)
-#define USART_CR3_WUS_Msk            (0x3UL << USART_CR3_WUS_Pos)              /*!< 0x00300000 */
-#define USART_CR3_WUS                USART_CR3_WUS_Msk                         /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0              (0x1UL << USART_CR3_WUS_Pos)              /*!< 0x00100000 */
-#define USART_CR3_WUS_1              (0x2UL << USART_CR3_WUS_Pos)              /*!< 0x00200000 */
-#define USART_CR3_WUFIE_Pos          (22U)
-#define USART_CR3_WUFIE_Msk          (0x1UL << USART_CR3_WUFIE_Pos)            /*!< 0x00400000 */
-#define USART_CR3_WUFIE              USART_CR3_WUFIE_Msk                       /*!< Wake Up Interrupt Enable */
-#define USART_CR3_TXFTIE_Pos         (23U)
-#define USART_CR3_TXFTIE_Msk         (0x1UL << USART_CR3_TXFTIE_Pos)           /*!< 0x00800000 */
-#define USART_CR3_TXFTIE             USART_CR3_TXFTIE_Msk                      /*!< TXFIFO threshold interrupt enable */
-#define USART_CR3_TCBGTIE_Pos        (24U)
-#define USART_CR3_TCBGTIE_Msk        (0x1UL << USART_CR3_TCBGTIE_Pos)          /*!< 0x01000000 */
-#define USART_CR3_TCBGTIE            USART_CR3_TCBGTIE_Msk                     /*!< Transmission Complete Before Guard Time Interrupt Enable */
-#define USART_CR3_RXFTCFG_Pos        (25U)
-#define USART_CR3_RXFTCFG_Msk        (0x7UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x0E000000 */
-#define USART_CR3_RXFTCFG            USART_CR3_RXFTCFG_Msk                     /*!< RXFIFO FIFO threshold configuration */
-#define USART_CR3_RXFTCFG_0          (0x1UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x02000000 */
-#define USART_CR3_RXFTCFG_1          (0x2UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x04000000 */
-#define USART_CR3_RXFTCFG_2          (0x4UL << USART_CR3_RXFTCFG_Pos)          /*!< 0x08000000 */
-#define USART_CR3_RXFTIE_Pos         (28U)
-#define USART_CR3_RXFTIE_Msk         (0x1UL << USART_CR3_RXFTIE_Pos)           /*!< 0x10000000 */
-#define USART_CR3_RXFTIE             USART_CR3_RXFTIE_Msk                      /*!< RXFIFO threshold interrupt enable */
-#define USART_CR3_TXFTCFG_Pos        (29U)
-#define USART_CR3_TXFTCFG_Msk        (0x7UL << USART_CR3_TXFTCFG_Pos)          /*!< 0xE0000000 */
-#define USART_CR3_TXFTCFG            USART_CR3_TXFTCFG_Msk                     /*!< TXFIFO threshold configuration */
-#define USART_CR3_TXFTCFG_0          (0x1UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x20000000 */
-#define USART_CR3_TXFTCFG_1          (0x2UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x40000000 */
-#define USART_CR3_TXFTCFG_2          (0x4UL << USART_CR3_TXFTCFG_Pos)          /*!< 0x80000000 */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_BRR                ((uint16_t)0xFFFF)                        /*!< USART  Baud rate register [15:0] */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos           (0U)
-#define USART_GTPR_PSC_Msk           (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC               USART_GTPR_PSC_Msk                        /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT_Pos            (8U)
-#define USART_GTPR_GT_Msk            (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                USART_GTPR_GT_Msk                         /*!< GT[7:0] bits (Guard time value) */
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO_Pos           (0U)
-#define USART_RTOR_RTO_Msk           (0xFFFFFFUL << USART_RTOR_RTO_Pos)        /*!< 0x00FFFFFF */
-#define USART_RTOR_RTO               USART_RTOR_RTO_Msk                        /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN_Pos          (24U)
-#define USART_RTOR_BLEN_Msk          (0xFFUL << USART_RTOR_BLEN_Pos)           /*!< 0xFF000000 */
-#define USART_RTOR_BLEN              USART_RTOR_BLEN_Msk                       /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ        ((uint16_t)0x0001)                              /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ        ((uint16_t)0x0002)                              /*!< Send Break Request */
-#define USART_RQR_MMRQ         ((uint16_t)0x0004)                              /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ        ((uint16_t)0x0008)                              /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ        ((uint16_t)0x0010)                              /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE_Pos             (0U)
-#define USART_ISR_PE_Msk             (0x1UL << USART_ISR_PE_Pos)               /*!< 0x00000001 */
-#define USART_ISR_PE                 USART_ISR_PE_Msk                          /*!< Parity Error */
-#define USART_ISR_FE_Pos             (1U)
-#define USART_ISR_FE_Msk             (0x1UL << USART_ISR_FE_Pos)               /*!< 0x00000002 */
-#define USART_ISR_FE                 USART_ISR_FE_Msk                          /*!< Framing Error */
-#define USART_ISR_NE_Pos             (2U)
-#define USART_ISR_NE_Msk             (0x1UL << USART_ISR_NE_Pos)               /*!< 0x00000004 */
-#define USART_ISR_NE                 USART_ISR_NE_Msk                          /*!< Noise detected Flag */
-#define USART_ISR_ORE_Pos            (3U)
-#define USART_ISR_ORE_Msk            (0x1UL << USART_ISR_ORE_Pos)              /*!< 0x00000008 */
-#define USART_ISR_ORE                USART_ISR_ORE_Msk                         /*!< OverRun Error */
-#define USART_ISR_IDLE_Pos           (4U)
-#define USART_ISR_IDLE_Msk           (0x1UL << USART_ISR_IDLE_Pos)             /*!< 0x00000010 */
-#define USART_ISR_IDLE               USART_ISR_IDLE_Msk                        /*!< IDLE line detected */
-#define USART_ISR_RXNE_RXFNE_Pos     (5U)
-#define USART_ISR_RXNE_RXFNE_Msk     (0x1UL << USART_ISR_RXNE_RXFNE_Pos)      /*!< 0x00000020 */
-#define USART_ISR_RXNE_RXFNE         USART_ISR_RXNE_RXFNE_Msk                /*!< Read Data Register Not Empty/RXFIFO Not Empty */
-#define USART_ISR_TC_Pos             (6U)
-#define USART_ISR_TC_Msk             (0x1UL << USART_ISR_TC_Pos)               /*!< 0x00000040 */
-#define USART_ISR_TC                 USART_ISR_TC_Msk                          /*!< Transmission Complete */
-#define USART_ISR_TXE_TXFNF_Pos      (7U)
-#define USART_ISR_TXE_TXFNF_Msk      (0x1UL << USART_ISR_TXE_TXFNF_Pos)       /*!< 0x00000080 */
-#define USART_ISR_TXE_TXFNF          USART_ISR_TXE_TXFNF_Msk                  /*!< Transmit Data Register Empty/TXFIFO Not Full */
-#define USART_ISR_LBDF_Pos           (8U)
-#define USART_ISR_LBDF_Msk           (0x1UL << USART_ISR_LBDF_Pos)             /*!< 0x00000100 */
-#define USART_ISR_LBDF               USART_ISR_LBDF_Msk                        /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF_Pos          (9U)
-#define USART_ISR_CTSIF_Msk          (0x1UL << USART_ISR_CTSIF_Pos)            /*!< 0x00000200 */
-#define USART_ISR_CTSIF              USART_ISR_CTSIF_Msk                       /*!< CTS interrupt flag */
-#define USART_ISR_CTS_Pos            (10U)
-#define USART_ISR_CTS_Msk            (0x1UL << USART_ISR_CTS_Pos)              /*!< 0x00000400 */
-#define USART_ISR_CTS                USART_ISR_CTS_Msk                         /*!< CTS flag */
-#define USART_ISR_RTOF_Pos           (11U)
-#define USART_ISR_RTOF_Msk           (0x1UL << USART_ISR_RTOF_Pos)             /*!< 0x00000800 */
-#define USART_ISR_RTOF               USART_ISR_RTOF_Msk                        /*!< Receiver Time Out */
-#define USART_ISR_EOBF_Pos           (12U)
-#define USART_ISR_EOBF_Msk           (0x1UL << USART_ISR_EOBF_Pos)             /*!< 0x00001000 */
-#define USART_ISR_EOBF               USART_ISR_EOBF_Msk                        /*!< End Of Block Flag */
-#define USART_ISR_UDR_Pos            (13U)
-#define USART_ISR_UDR_Msk            (0x1UL << USART_ISR_UDR_Pos)              /*!< 0x00002000 */
-#define USART_ISR_UDR                 USART_ISR_UDR_Msk                        /*!< SPI Slave Underrun Error Flag */
-#define USART_ISR_ABRE_Pos           (14U)
-#define USART_ISR_ABRE_Msk           (0x1UL << USART_ISR_ABRE_Pos)             /*!< 0x00004000 */
-#define USART_ISR_ABRE               USART_ISR_ABRE_Msk                        /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF_Pos           (15U)
-#define USART_ISR_ABRF_Msk           (0x1UL << USART_ISR_ABRF_Pos)             /*!< 0x00008000 */
-#define USART_ISR_ABRF               USART_ISR_ABRF_Msk                        /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY_Pos           (16U)
-#define USART_ISR_BUSY_Msk           (0x1UL << USART_ISR_BUSY_Pos)             /*!< 0x00010000 */
-#define USART_ISR_BUSY               USART_ISR_BUSY_Msk                        /*!< Busy Flag */
-#define USART_ISR_CMF_Pos            (17U)
-#define USART_ISR_CMF_Msk            (0x1UL << USART_ISR_CMF_Pos)              /*!< 0x00020000 */
-#define USART_ISR_CMF                USART_ISR_CMF_Msk                         /*!< Character Match Flag */
-#define USART_ISR_SBKF_Pos           (18U)
-#define USART_ISR_SBKF_Msk           (0x1UL << USART_ISR_SBKF_Pos)             /*!< 0x00040000 */
-#define USART_ISR_SBKF               USART_ISR_SBKF_Msk                        /*!< Send Break Flag */
-#define USART_ISR_RWU_Pos            (19U)
-#define USART_ISR_RWU_Msk            (0x1UL << USART_ISR_RWU_Pos)              /*!< 0x00080000 */
-#define USART_ISR_RWU                USART_ISR_RWU_Msk                         /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF_Pos            (20U)
-#define USART_ISR_WUF_Msk            (0x1UL << USART_ISR_WUF_Pos)              /*!< 0x00100000 */
-#define USART_ISR_WUF                USART_ISR_WUF_Msk                         /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK_Pos          (21U)
-#define USART_ISR_TEACK_Msk          (0x1UL << USART_ISR_TEACK_Pos)            /*!< 0x00200000 */
-#define USART_ISR_TEACK              USART_ISR_TEACK_Msk                       /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK_Pos          (22U)
-#define USART_ISR_REACK_Msk          (0x1UL << USART_ISR_REACK_Pos)            /*!< 0x00400000 */
-#define USART_ISR_REACK              USART_ISR_REACK_Msk                       /*!< Receive Enable Acknowledge Flag */
-#define USART_ISR_TXFE_Pos           (23U)
-#define USART_ISR_TXFE_Msk           (0x1UL << USART_ISR_TXFE_Pos)             /*!< 0x00800000 */
-#define USART_ISR_TXFE               USART_ISR_TXFE_Msk                        /*!< TXFIFO Empty Flag */
-#define USART_ISR_RXFF_Pos           (24U)
-#define USART_ISR_RXFF_Msk           (0x1UL << USART_ISR_RXFF_Pos)             /*!< 0x01000000 */
-#define USART_ISR_RXFF               USART_ISR_RXFF_Msk                        /*!< RXFIFO Full Flag */
-#define USART_ISR_TCBGT_Pos          (25U)
-#define USART_ISR_TCBGT_Msk          (0x1UL << USART_ISR_TCBGT_Pos)            /*!< 0x02000000 */
-#define USART_ISR_TCBGT              USART_ISR_TCBGT_Msk                       /*!< Transmission Complete Before Guard Time Completion Flag */
-#define USART_ISR_RXFT_Pos           (26U)
-#define USART_ISR_RXFT_Msk           (0x1UL << USART_ISR_RXFT_Pos)             /*!< 0x04000000 */
-#define USART_ISR_RXFT               USART_ISR_RXFT_Msk                        /*!< RXFIFO Threshold Flag */
-#define USART_ISR_TXFT_Pos           (27U)
-#define USART_ISR_TXFT_Msk           (0x1UL << USART_ISR_TXFT_Pos)             /*!< 0x08000000 */
-#define USART_ISR_TXFT               USART_ISR_TXFT_Msk                        /*!< TXFIFO Threshold Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF_Pos           (0U)
-#define USART_ICR_PECF_Msk           (0x1UL << USART_ICR_PECF_Pos)             /*!< 0x00000001 */
-#define USART_ICR_PECF               USART_ICR_PECF_Msk                        /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF_Pos           (1U)
-#define USART_ICR_FECF_Msk           (0x1UL << USART_ICR_FECF_Pos)             /*!< 0x00000002 */
-#define USART_ICR_FECF               USART_ICR_FECF_Msk                        /*!< Framing Error Clear Flag */
-#define USART_ICR_NECF_Pos           (2U)
-#define USART_ICR_NECF_Msk           (0x1UL << USART_ICR_NECF_Pos)             /*!< 0x00000004 */
-#define USART_ICR_NECF               USART_ICR_NECF_Msk                        /*!< Noise Error detected Clear Flag */
-#define USART_ICR_ORECF_Pos          (3U)
-#define USART_ICR_ORECF_Msk          (0x1UL << USART_ICR_ORECF_Pos)            /*!< 0x00000008 */
-#define USART_ICR_ORECF              USART_ICR_ORECF_Msk                       /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF_Pos         (4U)
-#define USART_ICR_IDLECF_Msk         (0x1UL << USART_ICR_IDLECF_Pos)           /*!< 0x00000010 */
-#define USART_ICR_IDLECF             USART_ICR_IDLECF_Msk                      /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TXFECF_Pos         (5U)
-#define USART_ICR_TXFECF_Msk         (0x1UL << USART_ICR_TXFECF_Pos)           /*!< 0x00000020 */
-#define USART_ICR_TXFECF             USART_ICR_TXFECF_Msk                      /*!< TXFIFO Empty Clear Flag */
-#define USART_ICR_TCCF_Pos           (6U)
-#define USART_ICR_TCCF_Msk           (0x1UL << USART_ICR_TCCF_Pos)             /*!< 0x00000040 */
-#define USART_ICR_TCCF               USART_ICR_TCCF_Msk                        /*!< Transmission Complete Clear Flag */
-#define USART_ICR_TCBGTCF_Pos        (7U)
-#define USART_ICR_TCBGTCF_Msk        (0x1UL << USART_ICR_TCBGTCF_Pos)          /*!< 0x00000080 */
-#define USART_ICR_TCBGTCF            USART_ICR_TCBGTCF_Msk                     /*!< Transmission Complete Before Guard Time Clear Flag */
-#define USART_ICR_LBDCF_Pos          (8U)
-#define USART_ICR_LBDCF_Msk          (0x1UL << USART_ICR_LBDCF_Pos)            /*!< 0x00000100 */
-#define USART_ICR_LBDCF              USART_ICR_LBDCF_Msk                       /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF_Pos          (9U)
-#define USART_ICR_CTSCF_Msk          (0x1UL << USART_ICR_CTSCF_Pos)            /*!< 0x00000200 */
-#define USART_ICR_CTSCF              USART_ICR_CTSCF_Msk                       /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF_Pos          (11U)
-#define USART_ICR_RTOCF_Msk          (0x1UL << USART_ICR_RTOCF_Pos)            /*!< 0x00000800 */
-#define USART_ICR_RTOCF              USART_ICR_RTOCF_Msk                       /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF_Pos          (12U)
-#define USART_ICR_EOBCF_Msk          (0x1UL << USART_ICR_EOBCF_Pos)            /*!< 0x00001000 */
-#define USART_ICR_EOBCF              USART_ICR_EOBCF_Msk                       /*!< End Of Block Clear Flag */
-#define USART_ICR_UDRCF_Pos          (13U)
-#define USART_ICR_UDRCF_Msk          (0x1UL << USART_ICR_UDRCF_Pos)            /*!< 0x00002000 */
-#define USART_ICR_UDRCF              USART_ICR_UDRCF_Msk                       /*!< SPI Slave Underrun Clear Flag */
-#define USART_ICR_CMCF_Pos           (17U)
-#define USART_ICR_CMCF_Msk           (0x1UL << USART_ICR_CMCF_Pos)             /*!< 0x00020000 */
-#define USART_ICR_CMCF               USART_ICR_CMCF_Msk                        /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF_Pos           (20U)
-#define USART_ICR_WUCF_Msk           (0x1UL << USART_ICR_WUCF_Pos)             /*!< 0x00100000 */
-#define USART_ICR_WUCF               USART_ICR_WUCF_Msk                        /*!< Wake Up from stop mode Clear Flag */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR_Pos             (0U)
-#define USART_RDR_RDR_Msk             (0x1FFUL << USART_RDR_RDR_Pos)           /*!< 0x000001FF */
-#define USART_RDR_RDR                 USART_RDR_RDR_Msk                        /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR_Pos             (0U)
-#define USART_TDR_TDR_Msk             (0x1FFUL << USART_TDR_TDR_Pos)           /*!< 0x000001FF */
-#define USART_TDR_TDR                 USART_TDR_TDR_Msk                        /*!< TDR[8:0] bits (Transmit Data value) */
-
-/*******************  Bit definition for USART_PRESC register  ****************/
-#define USART_PRESC_PRESCALER_Pos    (0U)
-#define USART_PRESC_PRESCALER_Msk    (0xFUL << USART_PRESC_PRESCALER_Pos)      /*!< 0x0000000F */
-#define USART_PRESC_PRESCALER        USART_PRESC_PRESCALER_Msk                 /*!< PRESCALER[3:0] bits (Clock prescaler) */
-#define USART_PRESC_PRESCALER_0      (0x1UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000001 */
-#define USART_PRESC_PRESCALER_1      (0x2UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000002 */
-#define USART_PRESC_PRESCALER_2      (0x4UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000004 */
-#define USART_PRESC_PRESCALER_3      (0x8UL << USART_PRESC_PRESCALER_Pos)      /*!< 0x00000008 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos            (0U)
-#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */
-#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos          (0U)
-#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)                   /*!< 0x000000FF */
-#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 8-bits data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos         (0U)
-#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */
-#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE_Pos      (3U)
-#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */
-#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000008 */
-#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000010 */
-#define CRC_CR_REV_IN_Pos        (5U)
-#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */
-#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000020 */
-#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000040 */
-#define CRC_CR_REV_OUT_Pos       (7U)
-#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */
-#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT_Pos        (0U)
-#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */
-#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL_Pos          (0U)
-#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */
-#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Advanced Encryption Standard (AES)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for AES_CR register  *********************/
-#define AES_CR_EN_Pos            (0U)
-#define AES_CR_EN_Msk            (0x1UL << AES_CR_EN_Pos)                      /*!< 0x00000001 */
-#define AES_CR_EN                AES_CR_EN_Msk                                 /*!< AES Enable */
-#define AES_CR_DATATYPE_Pos      (1U)
-#define AES_CR_DATATYPE_Msk      (0x3UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000006 */
-#define AES_CR_DATATYPE          AES_CR_DATATYPE_Msk                           /*!< Data type selection */
-#define AES_CR_DATATYPE_0        (0x1UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000002 */
-#define AES_CR_DATATYPE_1        (0x2UL << AES_CR_DATATYPE_Pos)                /*!< 0x00000004 */
-
-#define AES_CR_MODE_Pos          (3U)
-#define AES_CR_MODE_Msk          (0x3UL << AES_CR_MODE_Pos)                    /*!< 0x00000018 */
-#define AES_CR_MODE              AES_CR_MODE_Msk                               /*!< AES Mode Of Operation */
-#define AES_CR_MODE_0            (0x1UL << AES_CR_MODE_Pos)                    /*!< 0x00000008 */
-#define AES_CR_MODE_1            (0x2UL << AES_CR_MODE_Pos)                    /*!< 0x00000010 */
-
-#define AES_CR_CHMOD_Pos         (5U)
-#define AES_CR_CHMOD_Msk         (0x803UL << AES_CR_CHMOD_Pos)                 /*!< 0x00010060 */
-#define AES_CR_CHMOD             AES_CR_CHMOD_Msk                              /*!< AES Chaining Mode */
-#define AES_CR_CHMOD_0           (0x001UL << AES_CR_CHMOD_Pos)                 /*!< 0x00000020 */
-#define AES_CR_CHMOD_1           (0x002UL << AES_CR_CHMOD_Pos)                 /*!< 0x00000040 */
-#define AES_CR_CHMOD_2           (0x800UL << AES_CR_CHMOD_Pos)                 /*!< 0x00010000 */
-
-#define AES_CR_CCFC_Pos          (7U)
-#define AES_CR_CCFC_Msk          (0x1UL << AES_CR_CCFC_Pos)                    /*!< 0x00000080 */
-#define AES_CR_CCFC              AES_CR_CCFC_Msk                               /*!< Computation Complete Flag Clear */
-#define AES_CR_ERRC_Pos          (8U)
-#define AES_CR_ERRC_Msk          (0x1UL << AES_CR_ERRC_Pos)                    /*!< 0x00000100 */
-#define AES_CR_ERRC              AES_CR_ERRC_Msk                               /*!< Error Clear */
-#define AES_CR_CCFIE_Pos         (9U)
-#define AES_CR_CCFIE_Msk         (0x1UL << AES_CR_CCFIE_Pos)                   /*!< 0x00000200 */
-#define AES_CR_CCFIE             AES_CR_CCFIE_Msk                              /*!< Computation Complete Flag Interrupt Enable */
-#define AES_CR_ERRIE_Pos         (10U)
-#define AES_CR_ERRIE_Msk         (0x1UL << AES_CR_ERRIE_Pos)                   /*!< 0x00000400 */
-#define AES_CR_ERRIE             AES_CR_ERRIE_Msk                              /*!< Error Interrupt Enable */
-#define AES_CR_DMAINEN_Pos       (11U)
-#define AES_CR_DMAINEN_Msk       (0x1UL << AES_CR_DMAINEN_Pos)                 /*!< 0x00000800 */
-#define AES_CR_DMAINEN           AES_CR_DMAINEN_Msk                            /*!< Enable data input phase DMA management  */
-#define AES_CR_DMAOUTEN_Pos      (12U)
-#define AES_CR_DMAOUTEN_Msk      (0x1UL << AES_CR_DMAOUTEN_Pos)                /*!< 0x00001000 */
-#define AES_CR_DMAOUTEN          AES_CR_DMAOUTEN_Msk                           /*!< Enable data output phase DMA management */
-
-#define AES_CR_GCMPH_Pos         (13U)
-#define AES_CR_GCMPH_Msk         (0x3UL << AES_CR_GCMPH_Pos)                   /*!< 0x00006000 */
-#define AES_CR_GCMPH             AES_CR_GCMPH_Msk                              /*!< GCM Phase */
-#define AES_CR_GCMPH_0           (0x1UL << AES_CR_GCMPH_Pos)                   /*!< 0x00002000 */
-#define AES_CR_GCMPH_1           (0x2UL << AES_CR_GCMPH_Pos)                   /*!< 0x00004000 */
-
-#define AES_CR_KEYSIZE_Pos       (18U)
-#define AES_CR_KEYSIZE_Msk       (0x1UL << AES_CR_KEYSIZE_Pos)                 /*!< 0x00040000 */
-#define AES_CR_KEYSIZE           AES_CR_KEYSIZE_Msk                            /*!< Key size selection */
-
-#define AES_CR_NPBLB_Pos         (20U)
-#define AES_CR_NPBLB_Msk         (0xFUL << AES_CR_NPBLB_Pos)                   /*!< 0x00F00000 */
-#define AES_CR_NPBLB             AES_CR_NPBLB_Msk                              /*!< Number of padding bytes in last payload block */
-#define AES_CR_NPBLB_0           (0x1UL << AES_CR_NPBLB_Pos)                   /*!< 0x00100000 */
-#define AES_CR_NPBLB_1           (0x2UL << AES_CR_NPBLB_Pos)                   /*!< 0x00200000 */
-#define AES_CR_NPBLB_2           (0x4UL << AES_CR_NPBLB_Pos)                   /*!< 0x00400000 */
-#define AES_CR_NPBLB_3           (0x8UL << AES_CR_NPBLB_Pos)                   /*!< 0x00800000 */
-
-/*******************  Bit definition for AES_SR register  *********************/
-#define AES_SR_CCF_Pos           (0U)
-#define AES_SR_CCF_Msk           (0x1UL << AES_SR_CCF_Pos)                     /*!< 0x00000001 */
-#define AES_SR_CCF               AES_SR_CCF_Msk                                /*!< Computation Complete Flag */
-#define AES_SR_RDERR_Pos         (1U)
-#define AES_SR_RDERR_Msk         (0x1UL << AES_SR_RDERR_Pos)                   /*!< 0x00000002 */
-#define AES_SR_RDERR             AES_SR_RDERR_Msk                              /*!< Read Error Flag */
-#define AES_SR_WRERR_Pos         (2U)
-#define AES_SR_WRERR_Msk         (0x1UL << AES_SR_WRERR_Pos)                   /*!< 0x00000004 */
-#define AES_SR_WRERR             AES_SR_WRERR_Msk                              /*!< Write Error Flag */
-#define AES_SR_BUSY_Pos          (3U)
-#define AES_SR_BUSY_Msk          (0x1UL << AES_SR_BUSY_Pos)                    /*!< 0x00000008 */
-#define AES_SR_BUSY              AES_SR_BUSY_Msk                               /*!< Busy Flag */
-
-/*******************  Bit definition for AES_DINR register  *******************/
-#define AES_DINR_Pos             (0U)
-#define AES_DINR_Msk             (0xFFFFFFFFUL << AES_DINR_Pos)                /*!< 0xFFFFFFFF */
-#define AES_DINR                 AES_DINR_Msk                                  /*!< AES Data Input Register */
-
-/*******************  Bit definition for AES_DOUTR register  ******************/
-#define AES_DOUTR_Pos            (0U)
-#define AES_DOUTR_Msk            (0xFFFFFFFFUL << AES_DOUTR_Pos)               /*!< 0xFFFFFFFF */
-#define AES_DOUTR                AES_DOUTR_Msk                                 /*!< AES Data Output Register */
-
-/*******************  Bit definition for AES_KEYR0 register  ******************/
-#define AES_KEYR0_Pos            (0U)
-#define AES_KEYR0_Msk            (0xFFFFFFFFUL << AES_KEYR0_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR0                AES_KEYR0_Msk                                 /*!< AES Key Register 0 */
-
-/*******************  Bit definition for AES_KEYR1 register  ******************/
-#define AES_KEYR1_Pos            (0U)
-#define AES_KEYR1_Msk            (0xFFFFFFFFUL << AES_KEYR1_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR1                AES_KEYR1_Msk                                 /*!< AES Key Register 1 */
-
-/*******************  Bit definition for AES_KEYR2 register  ******************/
-#define AES_KEYR2_Pos            (0U)
-#define AES_KEYR2_Msk            (0xFFFFFFFFUL << AES_KEYR2_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR2                AES_KEYR2_Msk                                 /*!< AES Key Register 2 */
-
-/*******************  Bit definition for AES_KEYR3 register  ******************/
-#define AES_KEYR3_Pos            (0U)
-#define AES_KEYR3_Msk            (0xFFFFFFFFUL << AES_KEYR3_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR3                AES_KEYR3_Msk                                 /*!< AES Key Register 3 */
-
-/*******************  Bit definition for AES_KEYR4 register  ******************/
-#define AES_KEYR4_Pos            (0U)
-#define AES_KEYR4_Msk            (0xFFFFFFFFUL << AES_KEYR4_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR4                AES_KEYR4_Msk                                 /*!< AES Key Register 4 */
-
-/*******************  Bit definition for AES_KEYR5 register  ******************/
-#define AES_KEYR5_Pos            (0U)
-#define AES_KEYR5_Msk            (0xFFFFFFFFUL << AES_KEYR5_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR5                AES_KEYR5_Msk                                 /*!< AES Key Register 5 */
-
-/*******************  Bit definition for AES_KEYR6 register  ******************/
-#define AES_KEYR6_Pos            (0U)
-#define AES_KEYR6_Msk            (0xFFFFFFFFUL << AES_KEYR6_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR6                AES_KEYR6_Msk                                 /*!< AES Key Register 6 */
-
-/*******************  Bit definition for AES_KEYR7 register  ******************/
-#define AES_KEYR7_Pos            (0U)
-#define AES_KEYR7_Msk            (0xFFFFFFFFUL << AES_KEYR7_Pos)               /*!< 0xFFFFFFFF */
-#define AES_KEYR7                AES_KEYR7_Msk                                 /*!< AES Key Register 7 */
-
-/*******************  Bit definition for AES_IVR0 register   ******************/
-#define AES_IVR0_Pos             (0U)
-#define AES_IVR0_Msk             (0xFFFFFFFFUL << AES_IVR0_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR0                 AES_IVR0_Msk                                  /*!< AES Initialization Vector Register 0 */
-
-/*******************  Bit definition for AES_IVR1 register   ******************/
-#define AES_IVR1_Pos             (0U)
-#define AES_IVR1_Msk             (0xFFFFFFFFUL << AES_IVR1_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR1                 AES_IVR1_Msk                                  /*!< AES Initialization Vector Register 1 */
-
-/*******************  Bit definition for AES_IVR2 register   ******************/
-#define AES_IVR2_Pos             (0U)
-#define AES_IVR2_Msk             (0xFFFFFFFFUL << AES_IVR2_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR2                 AES_IVR2_Msk                                  /*!< AES Initialization Vector Register 2 */
-
-/*******************  Bit definition for AES_IVR3 register   ******************/
-#define AES_IVR3_Pos             (0U)
-#define AES_IVR3_Msk             (0xFFFFFFFFUL << AES_IVR3_Pos)                /*!< 0xFFFFFFFF */
-#define AES_IVR3                 AES_IVR3_Msk                                  /*!< AES Initialization Vector Register 3 */
-
-/*******************  Bit definition for AES_SUSP0R register  ******************/
-#define AES_SUSP0R_Pos           (0U)
-#define AES_SUSP0R_Msk           (0xFFFFFFFFUL << AES_SUSP0R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP0R               AES_SUSP0R_Msk                                /*!< AES Suspend registers 0 */
-
-/*******************  Bit definition for AES_SUSP1R register  ******************/
-#define AES_SUSP1R_Pos           (0U)
-#define AES_SUSP1R_Msk           (0xFFFFFFFFUL << AES_SUSP1R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP1R               AES_SUSP1R_Msk                                /*!< AES Suspend registers 1 */
-
-/*******************  Bit definition for AES_SUSP2R register  ******************/
-#define AES_SUSP2R_Pos           (0U)
-#define AES_SUSP2R_Msk           (0xFFFFFFFFUL << AES_SUSP2R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP2R               AES_SUSP2R_Msk                                /*!< AES Suspend registers 2 */
-
-/*******************  Bit definition for AES_SUSP3R register  ******************/
-#define AES_SUSP3R_Pos           (0U)
-#define AES_SUSP3R_Msk           (0xFFFFFFFFUL << AES_SUSP3R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP3R               AES_SUSP3R_Msk                                /*!< AES Suspend registers 3 */
-
-/*******************  Bit definition for AES_SUSP4R register  ******************/
-#define AES_SUSP4R_Pos           (0U)
-#define AES_SUSP4R_Msk           (0xFFFFFFFFUL << AES_SUSP4R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP4R               AES_SUSP4R_Msk                                /*!< AES Suspend registers 4 */
-
-/*******************  Bit definition for AES_SUSP5R register  ******************/
-#define AES_SUSP5R_Pos           (0U)
-#define AES_SUSP5R_Msk           (0xFFFFFFFFUL << AES_SUSP5R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP5R               AES_SUSP5R_Msk                                /*!< AES Suspend registers 5 */
-
-/*******************  Bit definition for AES_SUSP6R register  ******************/
-#define AES_SUSP6R_Pos           (0U)
-#define AES_SUSP6R_Msk           (0xFFFFFFFFUL << AES_SUSP6R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP6R               AES_SUSP6R_Msk                                /*!< AES Suspend registers 6 */
-
-/*******************  Bit definition for AES_SUSP7R register  ******************/
-#define AES_SUSP7R_Pos           (0U)
-#define AES_SUSP7R_Msk           (0xFFFFFFFFUL << AES_SUSP7R_Pos)              /*!< 0xFFFFFFFF */
-#define AES_SUSP7R               AES_SUSP7R_Msk                                /*!< AES Suspend registers 7 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1_Pos       (0U)
-#define DMA_ISR_GIF1_Msk       (0x1UL << DMA_ISR_GIF1_Pos)                     /*!< 0x00000001 */
-#define DMA_ISR_GIF1           DMA_ISR_GIF1_Msk                                /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1_Pos      (1U)
-#define DMA_ISR_TCIF1_Msk      (0x1UL << DMA_ISR_TCIF1_Pos)                    /*!< 0x00000002 */
-#define DMA_ISR_TCIF1          DMA_ISR_TCIF1_Msk                               /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1_Pos      (2U)
-#define DMA_ISR_HTIF1_Msk      (0x1UL << DMA_ISR_HTIF1_Pos)                    /*!< 0x00000004 */
-#define DMA_ISR_HTIF1          DMA_ISR_HTIF1_Msk                               /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1_Pos      (3U)
-#define DMA_ISR_TEIF1_Msk      (0x1UL << DMA_ISR_TEIF1_Pos)                    /*!< 0x00000008 */
-#define DMA_ISR_TEIF1          DMA_ISR_TEIF1_Msk                               /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2_Pos       (4U)
-#define DMA_ISR_GIF2_Msk       (0x1UL << DMA_ISR_GIF2_Pos)                     /*!< 0x00000010 */
-#define DMA_ISR_GIF2           DMA_ISR_GIF2_Msk                                /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2_Pos      (5U)
-#define DMA_ISR_TCIF2_Msk      (0x1UL << DMA_ISR_TCIF2_Pos)                    /*!< 0x00000020 */
-#define DMA_ISR_TCIF2          DMA_ISR_TCIF2_Msk                               /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2_Pos      (6U)
-#define DMA_ISR_HTIF2_Msk      (0x1UL << DMA_ISR_HTIF2_Pos)                    /*!< 0x00000040 */
-#define DMA_ISR_HTIF2          DMA_ISR_HTIF2_Msk                               /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2_Pos      (7U)
-#define DMA_ISR_TEIF2_Msk      (0x1UL << DMA_ISR_TEIF2_Pos)                    /*!< 0x00000080 */
-#define DMA_ISR_TEIF2          DMA_ISR_TEIF2_Msk                               /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3_Pos       (8U)
-#define DMA_ISR_GIF3_Msk       (0x1UL << DMA_ISR_GIF3_Pos)                     /*!< 0x00000100 */
-#define DMA_ISR_GIF3           DMA_ISR_GIF3_Msk                                /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3_Pos      (9U)
-#define DMA_ISR_TCIF3_Msk      (0x1UL << DMA_ISR_TCIF3_Pos)                    /*!< 0x00000200 */
-#define DMA_ISR_TCIF3          DMA_ISR_TCIF3_Msk                               /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3_Pos      (10U)
-#define DMA_ISR_HTIF3_Msk      (0x1UL << DMA_ISR_HTIF3_Pos)                    /*!< 0x00000400 */
-#define DMA_ISR_HTIF3          DMA_ISR_HTIF3_Msk                               /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3_Pos      (11U)
-#define DMA_ISR_TEIF3_Msk      (0x1UL << DMA_ISR_TEIF3_Pos)                    /*!< 0x00000800 */
-#define DMA_ISR_TEIF3          DMA_ISR_TEIF3_Msk                               /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4_Pos       (12U)
-#define DMA_ISR_GIF4_Msk       (0x1UL << DMA_ISR_GIF4_Pos)                     /*!< 0x00001000 */
-#define DMA_ISR_GIF4           DMA_ISR_GIF4_Msk                                /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4_Pos      (13U)
-#define DMA_ISR_TCIF4_Msk      (0x1UL << DMA_ISR_TCIF4_Pos)                    /*!< 0x00002000 */
-#define DMA_ISR_TCIF4          DMA_ISR_TCIF4_Msk                               /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4_Pos      (14U)
-#define DMA_ISR_HTIF4_Msk      (0x1UL << DMA_ISR_HTIF4_Pos)                    /*!< 0x00004000 */
-#define DMA_ISR_HTIF4          DMA_ISR_HTIF4_Msk                               /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4_Pos      (15U)
-#define DMA_ISR_TEIF4_Msk      (0x1UL << DMA_ISR_TEIF4_Pos)                    /*!< 0x00008000 */
-#define DMA_ISR_TEIF4          DMA_ISR_TEIF4_Msk                               /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5_Pos       (16U)
-#define DMA_ISR_GIF5_Msk       (0x1UL << DMA_ISR_GIF5_Pos)                     /*!< 0x00010000 */
-#define DMA_ISR_GIF5           DMA_ISR_GIF5_Msk                                /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5_Pos      (17U)
-#define DMA_ISR_TCIF5_Msk      (0x1UL << DMA_ISR_TCIF5_Pos)                    /*!< 0x00020000 */
-#define DMA_ISR_TCIF5          DMA_ISR_TCIF5_Msk                               /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5_Pos      (18U)
-#define DMA_ISR_HTIF5_Msk      (0x1UL << DMA_ISR_HTIF5_Pos)                    /*!< 0x00040000 */
-#define DMA_ISR_HTIF5          DMA_ISR_HTIF5_Msk                               /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5_Pos      (19U)
-#define DMA_ISR_TEIF5_Msk      (0x1UL << DMA_ISR_TEIF5_Pos)                    /*!< 0x00080000 */
-#define DMA_ISR_TEIF5          DMA_ISR_TEIF5_Msk                               /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6_Pos       (20U)
-#define DMA_ISR_GIF6_Msk       (0x1UL << DMA_ISR_GIF6_Pos)                     /*!< 0x00100000 */
-#define DMA_ISR_GIF6           DMA_ISR_GIF6_Msk                                /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6_Pos      (21U)
-#define DMA_ISR_TCIF6_Msk      (0x1UL << DMA_ISR_TCIF6_Pos)                    /*!< 0x00200000 */
-#define DMA_ISR_TCIF6          DMA_ISR_TCIF6_Msk                               /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6_Pos      (22U)
-#define DMA_ISR_HTIF6_Msk      (0x1UL << DMA_ISR_HTIF6_Pos)                    /*!< 0x00400000 */
-#define DMA_ISR_HTIF6          DMA_ISR_HTIF6_Msk                               /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6_Pos      (23U)
-#define DMA_ISR_TEIF6_Msk      (0x1UL << DMA_ISR_TEIF6_Pos)                    /*!< 0x00800000 */
-#define DMA_ISR_TEIF6          DMA_ISR_TEIF6_Msk                               /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7_Pos       (24U)
-#define DMA_ISR_GIF7_Msk       (0x1UL << DMA_ISR_GIF7_Pos)                     /*!< 0x01000000 */
-#define DMA_ISR_GIF7           DMA_ISR_GIF7_Msk                                /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7_Pos      (25U)
-#define DMA_ISR_TCIF7_Msk      (0x1UL << DMA_ISR_TCIF7_Pos)                    /*!< 0x02000000 */
-#define DMA_ISR_TCIF7          DMA_ISR_TCIF7_Msk                               /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7_Pos      (26U)
-#define DMA_ISR_HTIF7_Msk      (0x1UL << DMA_ISR_HTIF7_Pos)                    /*!< 0x04000000 */
-#define DMA_ISR_HTIF7          DMA_ISR_HTIF7_Msk                               /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7_Pos      (27U)
-#define DMA_ISR_TEIF7_Msk      (0x1UL << DMA_ISR_TEIF7_Pos)                    /*!< 0x08000000 */
-#define DMA_ISR_TEIF7          DMA_ISR_TEIF7_Msk                               /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1_Pos     (0U)
-#define DMA_IFCR_CGIF1_Msk     (0x1UL << DMA_IFCR_CGIF1_Pos)                   /*!< 0x00000001 */
-#define DMA_IFCR_CGIF1         DMA_IFCR_CGIF1_Msk                              /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1_Pos    (1U)
-#define DMA_IFCR_CTCIF1_Msk    (0x1UL << DMA_IFCR_CTCIF1_Pos)                  /*!< 0x00000002 */
-#define DMA_IFCR_CTCIF1        DMA_IFCR_CTCIF1_Msk                             /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1_Pos    (2U)
-#define DMA_IFCR_CHTIF1_Msk    (0x1UL << DMA_IFCR_CHTIF1_Pos)                  /*!< 0x00000004 */
-#define DMA_IFCR_CHTIF1        DMA_IFCR_CHTIF1_Msk                             /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1_Pos    (3U)
-#define DMA_IFCR_CTEIF1_Msk    (0x1UL << DMA_IFCR_CTEIF1_Pos)                  /*!< 0x00000008 */
-#define DMA_IFCR_CTEIF1        DMA_IFCR_CTEIF1_Msk                             /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2_Pos     (4U)
-#define DMA_IFCR_CGIF2_Msk     (0x1UL << DMA_IFCR_CGIF2_Pos)                   /*!< 0x00000010 */
-#define DMA_IFCR_CGIF2         DMA_IFCR_CGIF2_Msk                              /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2_Pos    (5U)
-#define DMA_IFCR_CTCIF2_Msk    (0x1UL << DMA_IFCR_CTCIF2_Pos)                  /*!< 0x00000020 */
-#define DMA_IFCR_CTCIF2        DMA_IFCR_CTCIF2_Msk                             /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2_Pos    (6U)
-#define DMA_IFCR_CHTIF2_Msk    (0x1UL << DMA_IFCR_CHTIF2_Pos)                  /*!< 0x00000040 */
-#define DMA_IFCR_CHTIF2        DMA_IFCR_CHTIF2_Msk                             /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2_Pos    (7U)
-#define DMA_IFCR_CTEIF2_Msk    (0x1UL << DMA_IFCR_CTEIF2_Pos)                  /*!< 0x00000080 */
-#define DMA_IFCR_CTEIF2        DMA_IFCR_CTEIF2_Msk                             /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3_Pos     (8U)
-#define DMA_IFCR_CGIF3_Msk     (0x1UL << DMA_IFCR_CGIF3_Pos)                   /*!< 0x00000100 */
-#define DMA_IFCR_CGIF3         DMA_IFCR_CGIF3_Msk                              /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3_Pos    (9U)
-#define DMA_IFCR_CTCIF3_Msk    (0x1UL << DMA_IFCR_CTCIF3_Pos)                  /*!< 0x00000200 */
-#define DMA_IFCR_CTCIF3        DMA_IFCR_CTCIF3_Msk                             /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3_Pos    (10U)
-#define DMA_IFCR_CHTIF3_Msk    (0x1UL << DMA_IFCR_CHTIF3_Pos)                  /*!< 0x00000400 */
-#define DMA_IFCR_CHTIF3        DMA_IFCR_CHTIF3_Msk                             /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3_Pos    (11U)
-#define DMA_IFCR_CTEIF3_Msk    (0x1UL << DMA_IFCR_CTEIF3_Pos)                  /*!< 0x00000800 */
-#define DMA_IFCR_CTEIF3        DMA_IFCR_CTEIF3_Msk                             /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4_Pos     (12U)
-#define DMA_IFCR_CGIF4_Msk     (0x1UL << DMA_IFCR_CGIF4_Pos)                   /*!< 0x00001000 */
-#define DMA_IFCR_CGIF4         DMA_IFCR_CGIF4_Msk                              /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4_Pos    (13U)
-#define DMA_IFCR_CTCIF4_Msk    (0x1UL << DMA_IFCR_CTCIF4_Pos)                  /*!< 0x00002000 */
-#define DMA_IFCR_CTCIF4        DMA_IFCR_CTCIF4_Msk                             /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4_Pos    (14U)
-#define DMA_IFCR_CHTIF4_Msk    (0x1UL << DMA_IFCR_CHTIF4_Pos)                  /*!< 0x00004000 */
-#define DMA_IFCR_CHTIF4        DMA_IFCR_CHTIF4_Msk                             /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4_Pos    (15U)
-#define DMA_IFCR_CTEIF4_Msk    (0x1UL << DMA_IFCR_CTEIF4_Pos)                  /*!< 0x00008000 */
-#define DMA_IFCR_CTEIF4        DMA_IFCR_CTEIF4_Msk                             /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5_Pos     (16U)
-#define DMA_IFCR_CGIF5_Msk     (0x1UL << DMA_IFCR_CGIF5_Pos)                   /*!< 0x00010000 */
-#define DMA_IFCR_CGIF5         DMA_IFCR_CGIF5_Msk                              /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5_Pos    (17U)
-#define DMA_IFCR_CTCIF5_Msk    (0x1UL << DMA_IFCR_CTCIF5_Pos)                  /*!< 0x00020000 */
-#define DMA_IFCR_CTCIF5        DMA_IFCR_CTCIF5_Msk                             /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5_Pos    (18U)
-#define DMA_IFCR_CHTIF5_Msk    (0x1UL << DMA_IFCR_CHTIF5_Pos)                  /*!< 0x00040000 */
-#define DMA_IFCR_CHTIF5        DMA_IFCR_CHTIF5_Msk                             /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5_Pos    (19U)
-#define DMA_IFCR_CTEIF5_Msk    (0x1UL << DMA_IFCR_CTEIF5_Pos)                  /*!< 0x00080000 */
-#define DMA_IFCR_CTEIF5        DMA_IFCR_CTEIF5_Msk                             /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6_Pos     (20U)
-#define DMA_IFCR_CGIF6_Msk     (0x1UL << DMA_IFCR_CGIF6_Pos)                   /*!< 0x00100000 */
-#define DMA_IFCR_CGIF6         DMA_IFCR_CGIF6_Msk                              /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6_Pos    (21U)
-#define DMA_IFCR_CTCIF6_Msk    (0x1UL << DMA_IFCR_CTCIF6_Pos)                  /*!< 0x00200000 */
-#define DMA_IFCR_CTCIF6        DMA_IFCR_CTCIF6_Msk                             /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6_Pos    (22U)
-#define DMA_IFCR_CHTIF6_Msk    (0x1UL << DMA_IFCR_CHTIF6_Pos)                  /*!< 0x00400000 */
-#define DMA_IFCR_CHTIF6        DMA_IFCR_CHTIF6_Msk                             /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6_Pos    (23U)
-#define DMA_IFCR_CTEIF6_Msk    (0x1UL << DMA_IFCR_CTEIF6_Pos)                  /*!< 0x00800000 */
-#define DMA_IFCR_CTEIF6        DMA_IFCR_CTEIF6_Msk                             /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7_Pos     (24U)
-#define DMA_IFCR_CGIF7_Msk     (0x1UL << DMA_IFCR_CGIF7_Pos)                   /*!< 0x01000000 */
-#define DMA_IFCR_CGIF7         DMA_IFCR_CGIF7_Msk                              /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7_Pos    (25U)
-#define DMA_IFCR_CTCIF7_Msk    (0x1UL << DMA_IFCR_CTCIF7_Pos)                  /*!< 0x02000000 */
-#define DMA_IFCR_CTCIF7        DMA_IFCR_CTCIF7_Msk                             /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7_Pos    (26U)
-#define DMA_IFCR_CHTIF7_Msk    (0x1UL << DMA_IFCR_CHTIF7_Pos)                  /*!< 0x04000000 */
-#define DMA_IFCR_CHTIF7        DMA_IFCR_CHTIF7_Msk                             /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7_Pos    (27U)
-#define DMA_IFCR_CTEIF7_Msk    (0x1UL << DMA_IFCR_CTEIF7_Pos)                  /*!< 0x08000000 */
-#define DMA_IFCR_CTEIF7        DMA_IFCR_CTEIF7_Msk                             /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN_Pos         (0U)
-#define DMA_CCR_EN_Msk         (0x1UL << DMA_CCR_EN_Pos)                       /*!< 0x00000001 */
-#define DMA_CCR_EN             DMA_CCR_EN_Msk                                  /*!< Channel enable                      */
-#define DMA_CCR_TCIE_Pos       (1U)
-#define DMA_CCR_TCIE_Msk       (0x1UL << DMA_CCR_TCIE_Pos)                     /*!< 0x00000002 */
-#define DMA_CCR_TCIE           DMA_CCR_TCIE_Msk                                /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE_Pos       (2U)
-#define DMA_CCR_HTIE_Msk       (0x1UL << DMA_CCR_HTIE_Pos)                     /*!< 0x00000004 */
-#define DMA_CCR_HTIE           DMA_CCR_HTIE_Msk                                /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE_Pos       (3U)
-#define DMA_CCR_TEIE_Msk       (0x1UL << DMA_CCR_TEIE_Pos)                     /*!< 0x00000008 */
-#define DMA_CCR_TEIE           DMA_CCR_TEIE_Msk                                /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR_Pos        (4U)
-#define DMA_CCR_DIR_Msk        (0x1UL << DMA_CCR_DIR_Pos)                      /*!< 0x00000010 */
-#define DMA_CCR_DIR            DMA_CCR_DIR_Msk                                 /*!< Data transfer direction             */
-#define DMA_CCR_CIRC_Pos       (5U)
-#define DMA_CCR_CIRC_Msk       (0x1UL << DMA_CCR_CIRC_Pos)                     /*!< 0x00000020 */
-#define DMA_CCR_CIRC           DMA_CCR_CIRC_Msk                                /*!< Circular mode                       */
-#define DMA_CCR_PINC_Pos       (6U)
-#define DMA_CCR_PINC_Msk       (0x1UL << DMA_CCR_PINC_Pos)                     /*!< 0x00000040 */
-#define DMA_CCR_PINC           DMA_CCR_PINC_Msk                                /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC_Pos       (7U)
-#define DMA_CCR_MINC_Msk       (0x1UL << DMA_CCR_MINC_Pos)                     /*!< 0x00000080 */
-#define DMA_CCR_MINC           DMA_CCR_MINC_Msk                                /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE_Pos      (8U)
-#define DMA_CCR_PSIZE_Msk      (0x3UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000300 */
-#define DMA_CCR_PSIZE          DMA_CCR_PSIZE_Msk                               /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0        (0x1UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000100 */
-#define DMA_CCR_PSIZE_1        (0x2UL << DMA_CCR_PSIZE_Pos)                    /*!< 0x00000200 */
-
-#define DMA_CCR_MSIZE_Pos      (10U)
-#define DMA_CCR_MSIZE_Msk      (0x3UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000C00 */
-#define DMA_CCR_MSIZE          DMA_CCR_MSIZE_Msk                               /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0        (0x1UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000400 */
-#define DMA_CCR_MSIZE_1        (0x2UL << DMA_CCR_MSIZE_Pos)                    /*!< 0x00000800 */
-
-#define DMA_CCR_PL_Pos         (12U)
-#define DMA_CCR_PL_Msk         (0x3UL << DMA_CCR_PL_Pos)                       /*!< 0x00003000 */
-#define DMA_CCR_PL             DMA_CCR_PL_Msk                                  /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0           (0x1UL << DMA_CCR_PL_Pos)                       /*!< 0x00001000 */
-#define DMA_CCR_PL_1           (0x2UL << DMA_CCR_PL_Pos)                       /*!< 0x00002000 */
-
-#define DMA_CCR_MEM2MEM_Pos    (14U)
-#define DMA_CCR_MEM2MEM_Msk    (0x1UL << DMA_CCR_MEM2MEM_Pos)                  /*!< 0x00004000 */
-#define DMA_CCR_MEM2MEM        DMA_CCR_MEM2MEM_Msk                             /*!< Memory to memory mode               */
-
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT_Pos      (0U)
-#define DMA_CNDTR_NDT_Msk      (0x3FFFFUL << DMA_CNDTR_NDT_Pos)                /*!< 0x0003FFFF */
-#define DMA_CNDTR_NDT          DMA_CNDTR_NDT_Msk                               /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA_Pos        (0U)
-#define DMA_CPAR_PA_Msk        (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)               /*!< 0xFFFFFFFF */
-#define DMA_CPAR_PA            DMA_CPAR_PA_Msk                                 /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA_Pos        (0U)
-#define DMA_CMAR_MA_Msk        (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)               /*!< 0xFFFFFFFF */
-#define DMA_CMAR_MA            DMA_CMAR_MA_Msk                                 /*!< Memory Address                      */
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMAMUX Controller                              */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMAMUX_CxCR register  **************/
-#define DMAMUX_CxCR_DMAREQ_ID_Pos              (0U)
-#define DMAMUX_CxCR_DMAREQ_ID_Msk              (0x7FUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x0000007F */
-#define DMAMUX_CxCR_DMAREQ_ID                  DMAMUX_CxCR_DMAREQ_ID_Msk       /*!< DMA Request ID                       */
-#define DMAMUX_CxCR_DMAREQ_ID_0                (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
-#define DMAMUX_CxCR_DMAREQ_ID_1                (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
-#define DMAMUX_CxCR_DMAREQ_ID_2                (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
-#define DMAMUX_CxCR_DMAREQ_ID_3                (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
-#define DMAMUX_CxCR_DMAREQ_ID_4                (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
-#define DMAMUX_CxCR_DMAREQ_ID_5                (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
-#define DMAMUX_CxCR_DMAREQ_ID_6                (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
-#define DMAMUX_CxCR_SOIE_Pos                   (8U)
-#define DMAMUX_CxCR_SOIE_Msk                   (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
-#define DMAMUX_CxCR_SOIE                       DMAMUX_CxCR_SOIE_Msk            /*!< Synchro overrun interrupt enable     */
-#define DMAMUX_CxCR_EGE_Pos                    (9U)
-#define DMAMUX_CxCR_EGE_Msk                    (0x1UL << DMAMUX_CxCR_EGE_Pos)  /*!< 0x00000200 */
-#define DMAMUX_CxCR_EGE                        DMAMUX_CxCR_EGE_Msk             /*!< Event generation interrupt enable    */
-#define DMAMUX_CxCR_SE_Pos                     (16U)
-#define DMAMUX_CxCR_SE_Msk                     (0x1UL << DMAMUX_CxCR_SE_Pos)   /*!< 0x00010000 */
-#define DMAMUX_CxCR_SE                         DMAMUX_CxCR_SE_Msk              /*!< Synchronization enable               */
-#define DMAMUX_CxCR_SPOL_Pos                   (17U)
-#define DMAMUX_CxCR_SPOL_Msk                   (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
-#define DMAMUX_CxCR_SPOL                       DMAMUX_CxCR_SPOL_Msk            /*!< Synchronization polarity             */
-#define DMAMUX_CxCR_SPOL_0                     (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
-#define DMAMUX_CxCR_SPOL_1                     (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
-#define DMAMUX_CxCR_NBREQ_Pos                  (19U)
-#define DMAMUX_CxCR_NBREQ_Msk                  (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
-#define DMAMUX_CxCR_NBREQ                      DMAMUX_CxCR_NBREQ_Msk           /*!< Number of request                    */
-#define DMAMUX_CxCR_NBREQ_0                    (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
-#define DMAMUX_CxCR_NBREQ_1                    (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
-#define DMAMUX_CxCR_NBREQ_2                    (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
-#define DMAMUX_CxCR_NBREQ_3                    (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
-#define DMAMUX_CxCR_NBREQ_4                    (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
-#define DMAMUX_CxCR_SYNC_ID_Pos                (24U)
-#define DMAMUX_CxCR_SYNC_ID_Msk                (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
-#define DMAMUX_CxCR_SYNC_ID                    DMAMUX_CxCR_SYNC_ID_Msk         /*!< Synchronization ID                   */
-#define DMAMUX_CxCR_SYNC_ID_0                  (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
-#define DMAMUX_CxCR_SYNC_ID_1                  (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
-#define DMAMUX_CxCR_SYNC_ID_2                  (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
-#define DMAMUX_CxCR_SYNC_ID_3                  (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
-#define DMAMUX_CxCR_SYNC_ID_4                  (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
-
-/*******************  Bits definition for DMAMUX_CSR register  **************/
-#define DMAMUX_CSR_SOF0_Pos                    (0U)
-#define DMAMUX_CSR_SOF0_Msk                    (0x1UL << DMAMUX_CSR_SOF0_Pos)  /*!< 0x00000001 */
-#define DMAMUX_CSR_SOF0                        DMAMUX_CSR_SOF0_Msk             /*!< Synchronization Overrun Flag 0       */
-#define DMAMUX_CSR_SOF1_Pos                    (1U)
-#define DMAMUX_CSR_SOF1_Msk                    (0x1UL << DMAMUX_CSR_SOF1_Pos)  /*!< 0x00000002 */
-#define DMAMUX_CSR_SOF1                        DMAMUX_CSR_SOF1_Msk             /*!< Synchronization Overrun Flag 1       */
-#define DMAMUX_CSR_SOF2_Pos                    (2U)
-#define DMAMUX_CSR_SOF2_Msk                    (0x1UL << DMAMUX_CSR_SOF2_Pos)  /*!< 0x00000004 */
-#define DMAMUX_CSR_SOF2                        DMAMUX_CSR_SOF2_Msk             /*!< Synchronization Overrun Flag 2       */
-#define DMAMUX_CSR_SOF3_Pos                    (3U)
-#define DMAMUX_CSR_SOF3_Msk                    (0x1UL << DMAMUX_CSR_SOF3_Pos)  /*!< 0x00000008 */
-#define DMAMUX_CSR_SOF3                        DMAMUX_CSR_SOF3_Msk             /*!< Synchronization Overrun Flag 3       */
-#define DMAMUX_CSR_SOF4_Pos                    (4U)
-#define DMAMUX_CSR_SOF4_Msk                    (0x1UL << DMAMUX_CSR_SOF4_Pos)  /*!< 0x00000010 */
-#define DMAMUX_CSR_SOF4                        DMAMUX_CSR_SOF4_Msk             /*!< Synchronization Overrun Flag 4       */
-#define DMAMUX_CSR_SOF5_Pos                    (5U)
-#define DMAMUX_CSR_SOF5_Msk                    (0x1UL << DMAMUX_CSR_SOF5_Pos)  /*!< 0x00000020 */
-#define DMAMUX_CSR_SOF5                        DMAMUX_CSR_SOF5_Msk             /*!< Synchronization Overrun Flag 5       */
-#define DMAMUX_CSR_SOF6_Pos                    (6U)
-#define DMAMUX_CSR_SOF6_Msk                    (0x1UL << DMAMUX_CSR_SOF6_Pos)  /*!< 0x00000040 */
-#define DMAMUX_CSR_SOF6                        DMAMUX_CSR_SOF6_Msk             /*!< Synchronization Overrun Flag 6       */
-#define DMAMUX_CSR_SOF7_Pos                    (7U)
-#define DMAMUX_CSR_SOF7_Msk                    (0x1UL << DMAMUX_CSR_SOF7_Pos)  /*!< 0x00000080 */
-#define DMAMUX_CSR_SOF7                        DMAMUX_CSR_SOF7_Msk             /*!< Synchronization Overrun Flag 7       */
-#define DMAMUX_CSR_SOF8_Pos                    (8U)
-#define DMAMUX_CSR_SOF8_Msk                    (0x1UL << DMAMUX_CSR_SOF8_Pos)  /*!< 0x00000100 */
-#define DMAMUX_CSR_SOF8                        DMAMUX_CSR_SOF8_Msk             /*!< Synchronization Overrun Flag 8       */
-#define DMAMUX_CSR_SOF9_Pos                    (9U)
-#define DMAMUX_CSR_SOF9_Msk                    (0x1UL << DMAMUX_CSR_SOF9_Pos)  /*!< 0x00000200 */
-#define DMAMUX_CSR_SOF9                        DMAMUX_CSR_SOF9_Msk             /*!< Synchronization Overrun Flag 9       */
-#define DMAMUX_CSR_SOF10_Pos                   (10U)
-#define DMAMUX_CSR_SOF10_Msk                   (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
-#define DMAMUX_CSR_SOF10                       DMAMUX_CSR_SOF10_Msk            /*!< Synchronization Overrun Flag 10      */
-#define DMAMUX_CSR_SOF11_Pos                   (11U)
-#define DMAMUX_CSR_SOF11_Msk                   (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
-#define DMAMUX_CSR_SOF11                       DMAMUX_CSR_SOF11_Msk            /*!< Synchronization Overrun Flag 11      */
-#define DMAMUX_CSR_SOF12_Pos                   (12U)
-#define DMAMUX_CSR_SOF12_Msk                   (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
-#define DMAMUX_CSR_SOF12                       DMAMUX_CSR_SOF12_Msk            /*!< Synchronization Overrun Flag 12      */
-#define DMAMUX_CSR_SOF13_Pos                   (13U)
-#define DMAMUX_CSR_SOF13_Msk                   (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
-#define DMAMUX_CSR_SOF13                       DMAMUX_CSR_SOF13_Msk            /*!< Synchronization Overrun Flag 13      */
-
-/********************  Bits definition for DMAMUX_CFR register  **************/
-#define DMAMUX_CFR_CSOF0_Pos                   (0U)
-#define DMAMUX_CFR_CSOF0_Msk                   (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
-#define DMAMUX_CFR_CSOF0                       DMAMUX_CFR_CSOF0_Msk            /*!< Clear Overrun Flag 0                 */
-#define DMAMUX_CFR_CSOF1_Pos                   (1U)
-#define DMAMUX_CFR_CSOF1_Msk                   (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
-#define DMAMUX_CFR_CSOF1                       DMAMUX_CFR_CSOF1_Msk            /*!< Clear Overrun Flag 1                 */
-#define DMAMUX_CFR_CSOF2_Pos                   (2U)
-#define DMAMUX_CFR_CSOF2_Msk                   (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
-#define DMAMUX_CFR_CSOF2                       DMAMUX_CFR_CSOF2_Msk            /*!< Clear Overrun Flag 2                 */
-#define DMAMUX_CFR_CSOF3_Pos                   (3U)
-#define DMAMUX_CFR_CSOF3_Msk                   (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
-#define DMAMUX_CFR_CSOF3                       DMAMUX_CFR_CSOF3_Msk            /*!< Clear Overrun Flag 3                 */
-#define DMAMUX_CFR_CSOF4_Pos                   (4U)
-#define DMAMUX_CFR_CSOF4_Msk                   (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
-#define DMAMUX_CFR_CSOF4                       DMAMUX_CFR_CSOF4_Msk            /*!< Clear Overrun Flag 4                 */
-#define DMAMUX_CFR_CSOF5_Pos                   (5U)
-#define DMAMUX_CFR_CSOF5_Msk                   (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
-#define DMAMUX_CFR_CSOF5                       DMAMUX_CFR_CSOF5_Msk            /*!< Clear Overrun Flag 5                 */
-#define DMAMUX_CFR_CSOF6_Pos                   (6U)
-#define DMAMUX_CFR_CSOF6_Msk                   (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
-#define DMAMUX_CFR_CSOF6                       DMAMUX_CFR_CSOF6_Msk            /*!< Clear Overrun Flag 6                 */
-#define DMAMUX_CFR_CSOF7_Pos                   (7U)
-#define DMAMUX_CFR_CSOF7_Msk                   (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
-#define DMAMUX_CFR_CSOF7                       DMAMUX_CFR_CSOF7_Msk            /*!< Clear Overrun Flag 7                 */
-#define DMAMUX_CFR_CSOF8_Pos                   (8U)
-#define DMAMUX_CFR_CSOF8_Msk                   (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
-#define DMAMUX_CFR_CSOF8                       DMAMUX_CFR_CSOF8_Msk            /*!< Clear Overrun Flag 8                 */
-#define DMAMUX_CFR_CSOF9_Pos                   (9U)
-#define DMAMUX_CFR_CSOF9_Msk                   (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
-#define DMAMUX_CFR_CSOF9                       DMAMUX_CFR_CSOF9_Msk            /*!< Clear Overrun Flag 9                 */
-#define DMAMUX_CFR_CSOF10_Pos                  (10U)
-#define DMAMUX_CFR_CSOF10_Msk                  (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
-#define DMAMUX_CFR_CSOF10                      DMAMUX_CFR_CSOF10_Msk           /*!< Clear Overrun Flag 10                */
-#define DMAMUX_CFR_CSOF11_Pos                  (11U)
-#define DMAMUX_CFR_CSOF11_Msk                  (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
-#define DMAMUX_CFR_CSOF11                      DMAMUX_CFR_CSOF11_Msk           /*!< Clear Overrun Flag 11                */
-#define DMAMUX_CFR_CSOF12_Pos                  (12U)
-#define DMAMUX_CFR_CSOF12_Msk                  (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
-#define DMAMUX_CFR_CSOF12                      DMAMUX_CFR_CSOF12_Msk           /*!< Clear Overrun Flag 12                */
-#define DMAMUX_CFR_CSOF13_Pos                  (13U)
-#define DMAMUX_CFR_CSOF13_Msk                  (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
-#define DMAMUX_CFR_CSOF13                      DMAMUX_CFR_CSOF13_Msk           /*!< Clear Overrun Flag 13                */
-
-/********************  Bits definition for DMAMUX_RGxCR register  ************/
-#define DMAMUX_RGxCR_SIG_ID_Pos                (0U)
-#define DMAMUX_RGxCR_SIG_ID_Msk                (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
-#define DMAMUX_RGxCR_SIG_ID                    DMAMUX_RGxCR_SIG_ID_Msk         /*!< Signal ID                            */
-#define DMAMUX_RGxCR_SIG_ID_0                  (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
-#define DMAMUX_RGxCR_SIG_ID_1                  (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
-#define DMAMUX_RGxCR_SIG_ID_2                  (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
-#define DMAMUX_RGxCR_SIG_ID_3                  (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
-#define DMAMUX_RGxCR_SIG_ID_4                  (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
-#define DMAMUX_RGxCR_OIE_Pos                   (8U)
-#define DMAMUX_RGxCR_OIE_Msk                   (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
-#define DMAMUX_RGxCR_OIE                       DMAMUX_RGxCR_OIE_Msk            /*!< Overrun interrupt enable             */
-#define DMAMUX_RGxCR_GE_Pos                    (16U)
-#define DMAMUX_RGxCR_GE_Msk                    (0x1UL << DMAMUX_RGxCR_GE_Pos)  /*!< 0x00010000 */
-#define DMAMUX_RGxCR_GE                        DMAMUX_RGxCR_GE_Msk             /*!< Generation enable                    */
-#define DMAMUX_RGxCR_GPOL_Pos                  (17U)
-#define DMAMUX_RGxCR_GPOL_Msk                  (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
-#define DMAMUX_RGxCR_GPOL                      DMAMUX_RGxCR_GPOL_Msk           /*!< Generation polarity                  */
-#define DMAMUX_RGxCR_GPOL_0                    (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
-#define DMAMUX_RGxCR_GPOL_1                    (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
-#define DMAMUX_RGxCR_GNBREQ_Pos                (19U)
-#define DMAMUX_RGxCR_GNBREQ_Msk                (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
-#define DMAMUX_RGxCR_GNBREQ                    DMAMUX_RGxCR_GNBREQ_Msk          /*!< Number of request                    */
-#define DMAMUX_RGxCR_GNBREQ_0                  (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
-#define DMAMUX_RGxCR_GNBREQ_1                  (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
-#define DMAMUX_RGxCR_GNBREQ_2                  (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
-#define DMAMUX_RGxCR_GNBREQ_3                  (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
-#define DMAMUX_RGxCR_GNBREQ_4                  (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
-
-/********************  Bits definition for DMAMUX_RGSR register  **************/
-#define DMAMUX_RGSR_OF0_Pos                    (0U)
-#define DMAMUX_RGSR_OF0_Msk                    (0x1UL << DMAMUX_RGSR_OF0_Pos)  /*!< 0x00000001 */
-#define DMAMUX_RGSR_OF0                        DMAMUX_RGSR_OF0_Msk             /*!< Overrun flag 0                       */
-#define DMAMUX_RGSR_OF1_Pos                    (1U)
-#define DMAMUX_RGSR_OF1_Msk                    (0x1UL << DMAMUX_RGSR_OF1_Pos)  /*!< 0x00000002 */
-#define DMAMUX_RGSR_OF1                        DMAMUX_RGSR_OF1_Msk             /*!< Overrun flag 1                       */
-#define DMAMUX_RGSR_OF2_Pos                    (2U)
-#define DMAMUX_RGSR_OF2_Msk                    (0x1UL << DMAMUX_RGSR_OF2_Pos)  /*!< 0x00000004 */
-#define DMAMUX_RGSR_OF2                        DMAMUX_RGSR_OF2_Msk             /*!< Overrun flag 2                       */
-#define DMAMUX_RGSR_OF3_Pos                    (3U)
-#define DMAMUX_RGSR_OF3_Msk                    (0x1UL << DMAMUX_RGSR_OF3_Pos)  /*!< 0x00000008 */
-#define DMAMUX_RGSR_OF3                        DMAMUX_RGSR_OF3_Msk             /*!< Overrun flag 3                       */
-
-/********************  Bits definition for DMAMUX_RGCFR register  **************/
-#define DMAMUX_RGCFR_COF0_Pos                  (0U)
-#define DMAMUX_RGCFR_COF0_Msk                  (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
-#define DMAMUX_RGCFR_COF0                      DMAMUX_RGCFR_COF0_Msk           /*!< Clear Overrun flag 0                 */
-#define DMAMUX_RGCFR_COF1_Pos                  (1U)
-#define DMAMUX_RGCFR_COF1_Msk                  (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
-#define DMAMUX_RGCFR_COF1                      DMAMUX_RGCFR_COF1_Msk           /*!< Clear Overrun flag 1                 */
-#define DMAMUX_RGCFR_COF2_Pos                  (2U)
-#define DMAMUX_RGCFR_COF2_Msk                  (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
-#define DMAMUX_RGCFR_COF2                      DMAMUX_RGCFR_COF2_Msk           /*!< Clear Overrun flag 2                 */
-#define DMAMUX_RGCFR_COF3_Pos                  (3U)
-#define DMAMUX_RGCFR_COF3_Msk                  (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
-#define DMAMUX_RGCFR_COF3                      DMAMUX_RGCFR_COF3_Msk           /*!< Clear Overrun flag 3                 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Asynchronous Interrupt/Event Controller                 */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for EXTI_RTSR1 register  ******************/
-#define EXTI_RTSR1_RT0_Pos       (0U)
-#define EXTI_RTSR1_RT0_Msk       (0x1UL << EXTI_RTSR1_RT0_Pos)                 /*!< 0x00000001 */
-#define EXTI_RTSR1_RT0           EXTI_RTSR1_RT0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR1_RT1_Pos       (1U)
-#define EXTI_RTSR1_RT1_Msk       (0x1UL << EXTI_RTSR1_RT1_Pos)                 /*!< 0x00000002 */
-#define EXTI_RTSR1_RT1           EXTI_RTSR1_RT1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR1_RT2_Pos       (2U)
-#define EXTI_RTSR1_RT2_Msk       (0x1UL << EXTI_RTSR1_RT2_Pos)                 /*!< 0x00000004 */
-#define EXTI_RTSR1_RT2           EXTI_RTSR1_RT2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR1_RT3_Pos       (3U)
-#define EXTI_RTSR1_RT3_Msk       (0x1UL << EXTI_RTSR1_RT3_Pos)                 /*!< 0x00000008 */
-#define EXTI_RTSR1_RT3           EXTI_RTSR1_RT3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR1_RT4_Pos       (4U)
-#define EXTI_RTSR1_RT4_Msk       (0x1UL << EXTI_RTSR1_RT4_Pos)                 /*!< 0x00000010 */
-#define EXTI_RTSR1_RT4           EXTI_RTSR1_RT4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR1_RT5_Pos       (5U)
-#define EXTI_RTSR1_RT5_Msk       (0x1UL << EXTI_RTSR1_RT5_Pos)                 /*!< 0x00000020 */
-#define EXTI_RTSR1_RT5           EXTI_RTSR1_RT5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR1_RT6_Pos       (6U)
-#define EXTI_RTSR1_RT6_Msk       (0x1UL << EXTI_RTSR1_RT6_Pos)                 /*!< 0x00000040 */
-#define EXTI_RTSR1_RT6           EXTI_RTSR1_RT6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR1_RT7_Pos       (7U)
-#define EXTI_RTSR1_RT7_Msk       (0x1UL << EXTI_RTSR1_RT7_Pos)                 /*!< 0x00000080 */
-#define EXTI_RTSR1_RT7           EXTI_RTSR1_RT7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR1_RT8_Pos       (8U)
-#define EXTI_RTSR1_RT8_Msk       (0x1UL << EXTI_RTSR1_RT8_Pos)                 /*!< 0x00000100 */
-#define EXTI_RTSR1_RT8           EXTI_RTSR1_RT8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR1_RT9_Pos       (9U)
-#define EXTI_RTSR1_RT9_Msk       (0x1UL << EXTI_RTSR1_RT9_Pos)                 /*!< 0x00000200 */
-#define EXTI_RTSR1_RT9           EXTI_RTSR1_RT9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR1_RT10_Pos      (10U)
-#define EXTI_RTSR1_RT10_Msk      (0x1UL << EXTI_RTSR1_RT10_Pos)                /*!< 0x00000400 */
-#define EXTI_RTSR1_RT10          EXTI_RTSR1_RT10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR1_RT11_Pos      (11U)
-#define EXTI_RTSR1_RT11_Msk      (0x1UL << EXTI_RTSR1_RT11_Pos)                /*!< 0x00000800 */
-#define EXTI_RTSR1_RT11          EXTI_RTSR1_RT11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR1_RT12_Pos      (12U)
-#define EXTI_RTSR1_RT12_Msk      (0x1UL << EXTI_RTSR1_RT12_Pos)                /*!< 0x00001000 */
-#define EXTI_RTSR1_RT12          EXTI_RTSR1_RT12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR1_RT13_Pos      (13U)
-#define EXTI_RTSR1_RT13_Msk      (0x1UL << EXTI_RTSR1_RT13_Pos)                /*!< 0x00002000 */
-#define EXTI_RTSR1_RT13          EXTI_RTSR1_RT13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR1_RT14_Pos      (14U)
-#define EXTI_RTSR1_RT14_Msk      (0x1UL << EXTI_RTSR1_RT14_Pos)                /*!< 0x00004000 */
-#define EXTI_RTSR1_RT14          EXTI_RTSR1_RT14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR1_RT15_Pos      (15U)
-#define EXTI_RTSR1_RT15_Msk      (0x1UL << EXTI_RTSR1_RT15_Pos)                /*!< 0x00008000 */
-#define EXTI_RTSR1_RT15          EXTI_RTSR1_RT15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR1_RT16_Pos      (16U)
-#define EXTI_RTSR1_RT16_Msk      (0x1UL << EXTI_RTSR1_RT16_Pos)                /*!< 0x00010000 */
-#define EXTI_RTSR1_RT16          EXTI_RTSR1_RT16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR1_RT21_Pos      (21U)
-#define EXTI_RTSR1_RT21_Msk      (0x1UL << EXTI_RTSR1_RT21_Pos)                /*!< 0x00200000 */
-#define EXTI_RTSR1_RT21          EXTI_RTSR1_RT21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR1_RT22_Pos      (22U)
-#define EXTI_RTSR1_RT22_Msk      (0x1UL << EXTI_RTSR1_RT22_Pos)                /*!< 0x00400000 */
-#define EXTI_RTSR1_RT22          EXTI_RTSR1_RT22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR1 register  ******************/
-#define EXTI_FTSR1_FT0_Pos       (0U)
-#define EXTI_FTSR1_FT0_Msk       (0x1UL << EXTI_FTSR1_FT0_Pos)                 /*!< 0x00000001 */
-#define EXTI_FTSR1_FT0           EXTI_FTSR1_FT0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR1_FT1_Pos       (1U)
-#define EXTI_FTSR1_FT1_Msk       (0x1UL << EXTI_FTSR1_FT1_Pos)                 /*!< 0x00000002 */
-#define EXTI_FTSR1_FT1           EXTI_FTSR1_FT1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR1_FT2_Pos       (2U)
-#define EXTI_FTSR1_FT2_Msk       (0x1UL << EXTI_FTSR1_FT2_Pos)                 /*!< 0x00000004 */
-#define EXTI_FTSR1_FT2           EXTI_FTSR1_FT2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR1_FT3_Pos       (3U)
-#define EXTI_FTSR1_FT3_Msk       (0x1UL << EXTI_FTSR1_FT3_Pos)                 /*!< 0x00000008 */
-#define EXTI_FTSR1_FT3           EXTI_FTSR1_FT3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR1_FT4_Pos       (4U)
-#define EXTI_FTSR1_FT4_Msk       (0x1UL << EXTI_FTSR1_FT4_Pos)                 /*!< 0x00000010 */
-#define EXTI_FTSR1_FT4           EXTI_FTSR1_FT4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR1_FT5_Pos       (5U)
-#define EXTI_FTSR1_FT5_Msk       (0x1UL << EXTI_FTSR1_FT5_Pos)                 /*!< 0x00000020 */
-#define EXTI_FTSR1_FT5           EXTI_FTSR1_FT5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR1_FT6_Pos       (6U)
-#define EXTI_FTSR1_FT6_Msk       (0x1UL << EXTI_FTSR1_FT6_Pos)                 /*!< 0x00000040 */
-#define EXTI_FTSR1_FT6           EXTI_FTSR1_FT6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR1_FT7_Pos       (7U)
-#define EXTI_FTSR1_FT7_Msk       (0x1UL << EXTI_FTSR1_FT7_Pos)                 /*!< 0x00000080 */
-#define EXTI_FTSR1_FT7           EXTI_FTSR1_FT7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR1_FT8_Pos       (8U)
-#define EXTI_FTSR1_FT8_Msk       (0x1UL << EXTI_FTSR1_FT8_Pos)                 /*!< 0x00000100 */
-#define EXTI_FTSR1_FT8           EXTI_FTSR1_FT8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR1_FT9_Pos       (9U)
-#define EXTI_FTSR1_FT9_Msk       (0x1UL << EXTI_FTSR1_FT9_Pos)                 /*!< 0x00000200 */
-#define EXTI_FTSR1_FT9           EXTI_FTSR1_FT9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR1_FT10_Pos      (10U)
-#define EXTI_FTSR1_FT10_Msk      (0x1UL << EXTI_FTSR1_FT10_Pos)                /*!< 0x00000400 */
-#define EXTI_FTSR1_FT10          EXTI_FTSR1_FT10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR1_FT11_Pos      (11U)
-#define EXTI_FTSR1_FT11_Msk      (0x1UL << EXTI_FTSR1_FT11_Pos)                /*!< 0x00000800 */
-#define EXTI_FTSR1_FT11          EXTI_FTSR1_FT11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR1_FT12_Pos      (12U)
-#define EXTI_FTSR1_FT12_Msk      (0x1UL << EXTI_FTSR1_FT12_Pos)                /*!< 0x00001000 */
-#define EXTI_FTSR1_FT12          EXTI_FTSR1_FT12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR1_FT13_Pos      (13U)
-#define EXTI_FTSR1_FT13_Msk      (0x1UL << EXTI_FTSR1_FT13_Pos)                /*!< 0x00002000 */
-#define EXTI_FTSR1_FT13          EXTI_FTSR1_FT13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR1_FT14_Pos      (14U)
-#define EXTI_FTSR1_FT14_Msk      (0x1UL << EXTI_FTSR1_FT14_Pos)                /*!< 0x00004000 */
-#define EXTI_FTSR1_FT14          EXTI_FTSR1_FT14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR1_FT15_Pos      (15U)
-#define EXTI_FTSR1_FT15_Msk      (0x1UL << EXTI_FTSR1_FT15_Pos)                /*!< 0x00008000 */
-#define EXTI_FTSR1_FT15          EXTI_FTSR1_FT15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR1_FT16_Pos      (16U)
-#define EXTI_FTSR1_FT16_Msk      (0x1UL << EXTI_FTSR1_FT16_Pos)                /*!< 0x00010000 */
-#define EXTI_FTSR1_FT16          EXTI_FTSR1_FT16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR1_FT21_Pos      (21U)
-#define EXTI_FTSR1_FT21_Msk      (0x1UL << EXTI_FTSR1_FT21_Pos)                /*!< 0x00200000 */
-#define EXTI_FTSR1_FT21          EXTI_FTSR1_FT21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR1_FT22_Pos      (22U)
-#define EXTI_FTSR1_FT22_Msk      (0x1UL << EXTI_FTSR1_FT22_Pos)                /*!< 0x00400000 */
-#define EXTI_FTSR1_FT22          EXTI_FTSR1_FT22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER1 register  *****************/
-#define EXTI_SWIER1_SWI0_Pos     (0U)
-#define EXTI_SWIER1_SWI0_Msk     (0x1UL << EXTI_SWIER1_SWI0_Pos)               /*!< 0x00000001 */
-#define EXTI_SWIER1_SWI0         EXTI_SWIER1_SWI0_Msk                          /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER1_SWI1_Pos     (1U)
-#define EXTI_SWIER1_SWI1_Msk     (0x1UL << EXTI_SWIER1_SWI1_Pos)               /*!< 0x00000002 */
-#define EXTI_SWIER1_SWI1         EXTI_SWIER1_SWI1_Msk                          /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER1_SWI2_Pos     (2U)
-#define EXTI_SWIER1_SWI2_Msk     (0x1UL << EXTI_SWIER1_SWI2_Pos)               /*!< 0x00000004 */
-#define EXTI_SWIER1_SWI2         EXTI_SWIER1_SWI2_Msk                          /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER1_SWI3_Pos     (3U)
-#define EXTI_SWIER1_SWI3_Msk     (0x1UL << EXTI_SWIER1_SWI3_Pos)               /*!< 0x00000008 */
-#define EXTI_SWIER1_SWI3         EXTI_SWIER1_SWI3_Msk                          /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER1_SWI4_Pos     (4U)
-#define EXTI_SWIER1_SWI4_Msk     (0x1UL << EXTI_SWIER1_SWI4_Pos)               /*!< 0x00000010 */
-#define EXTI_SWIER1_SWI4         EXTI_SWIER1_SWI4_Msk                          /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER1_SWI5_Pos     (5U)
-#define EXTI_SWIER1_SWI5_Msk     (0x1UL << EXTI_SWIER1_SWI5_Pos)               /*!< 0x00000020 */
-#define EXTI_SWIER1_SWI5         EXTI_SWIER1_SWI5_Msk                          /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER1_SWI6_Pos     (6U)
-#define EXTI_SWIER1_SWI6_Msk     (0x1UL << EXTI_SWIER1_SWI6_Pos)               /*!< 0x00000040 */
-#define EXTI_SWIER1_SWI6         EXTI_SWIER1_SWI6_Msk                          /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER1_SWI7_Pos     (7U)
-#define EXTI_SWIER1_SWI7_Msk     (0x1UL << EXTI_SWIER1_SWI7_Pos)               /*!< 0x00000080 */
-#define EXTI_SWIER1_SWI7         EXTI_SWIER1_SWI7_Msk                          /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER1_SWI8_Pos     (8U)
-#define EXTI_SWIER1_SWI8_Msk     (0x1UL << EXTI_SWIER1_SWI8_Pos)               /*!< 0x00000100 */
-#define EXTI_SWIER1_SWI8         EXTI_SWIER1_SWI8_Msk                          /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER1_SWI9_Pos     (9U)
-#define EXTI_SWIER1_SWI9_Msk     (0x1UL << EXTI_SWIER1_SWI9_Pos)               /*!< 0x00000200 */
-#define EXTI_SWIER1_SWI9         EXTI_SWIER1_SWI9_Msk                          /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER1_SWI10_Pos    (10U)
-#define EXTI_SWIER1_SWI10_Msk    (0x1UL << EXTI_SWIER1_SWI10_Pos)              /*!< 0x00000400 */
-#define EXTI_SWIER1_SWI10        EXTI_SWIER1_SWI10_Msk                         /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER1_SWI11_Pos    (11U)
-#define EXTI_SWIER1_SWI11_Msk    (0x1UL << EXTI_SWIER1_SWI11_Pos)              /*!< 0x00000800 */
-#define EXTI_SWIER1_SWI11        EXTI_SWIER1_SWI11_Msk                         /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER1_SWI12_Pos    (12U)
-#define EXTI_SWIER1_SWI12_Msk    (0x1UL << EXTI_SWIER1_SWI12_Pos)              /*!< 0x00001000 */
-#define EXTI_SWIER1_SWI12        EXTI_SWIER1_SWI12_Msk                         /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER1_SWI13_Pos    (13U)
-#define EXTI_SWIER1_SWI13_Msk    (0x1UL << EXTI_SWIER1_SWI13_Pos)              /*!< 0x00002000 */
-#define EXTI_SWIER1_SWI13        EXTI_SWIER1_SWI13_Msk                         /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER1_SWI14_Pos    (14U)
-#define EXTI_SWIER1_SWI14_Msk    (0x1UL << EXTI_SWIER1_SWI14_Pos)              /*!< 0x00004000 */
-#define EXTI_SWIER1_SWI14        EXTI_SWIER1_SWI14_Msk                         /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER1_SWI15_Pos    (15U)
-#define EXTI_SWIER1_SWI15_Msk    (0x1UL << EXTI_SWIER1_SWI15_Pos)              /*!< 0x00008000 */
-#define EXTI_SWIER1_SWI15        EXTI_SWIER1_SWI15_Msk                         /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER1_SWI16_Pos    (16U)
-#define EXTI_SWIER1_SWI16_Msk    (0x1UL << EXTI_SWIER1_SWI16_Pos)              /*!< 0x00010000 */
-#define EXTI_SWIER1_SWI16        EXTI_SWIER1_SWI16_Msk                         /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER1_SWI21_Pos    (21U)
-#define EXTI_SWIER1_SWI21_Msk    (0x1UL << EXTI_SWIER1_SWI21_Pos)              /*!< 0x00200000 */
-#define EXTI_SWIER1_SWI21        EXTI_SWIER1_SWI21_Msk                         /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER1_SWI22_Pos    (22U)
-#define EXTI_SWIER1_SWI22_Msk    (0x1UL << EXTI_SWIER1_SWI22_Pos)              /*!< 0x00400000 */
-#define EXTI_SWIER1_SWI22        EXTI_SWIER1_SWI22_Msk                         /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR1 register  *******************/
-#define EXTI_PR1_PIF0_Pos        (0U)
-#define EXTI_PR1_PIF0_Msk        (0x1UL << EXTI_PR1_PIF0_Pos)                  /*!< 0x00000001 */
-#define EXTI_PR1_PIF0            EXTI_PR1_PIF0_Msk                             /*!< Pending bit for line 0 */
-#define EXTI_PR1_PIF1_Pos        (1U)
-#define EXTI_PR1_PIF1_Msk        (0x1UL << EXTI_PR1_PIF1_Pos)                  /*!< 0x00000002 */
-#define EXTI_PR1_PIF1            EXTI_PR1_PIF1_Msk                             /*!< Pending bit for line 1 */
-#define EXTI_PR1_PIF2_Pos        (2U)
-#define EXTI_PR1_PIF2_Msk        (0x1UL << EXTI_PR1_PIF2_Pos)                  /*!< 0x00000004 */
-#define EXTI_PR1_PIF2            EXTI_PR1_PIF2_Msk                             /*!< Pending bit for line 2 */
-#define EXTI_PR1_PIF3_Pos        (3U)
-#define EXTI_PR1_PIF3_Msk        (0x1UL << EXTI_PR1_PIF3_Pos)                  /*!< 0x00000008 */
-#define EXTI_PR1_PIF3            EXTI_PR1_PIF3_Msk                             /*!< Pending bit for line 3 */
-#define EXTI_PR1_PIF4_Pos        (4U)
-#define EXTI_PR1_PIF4_Msk        (0x1UL << EXTI_PR1_PIF4_Pos)                  /*!< 0x00000010 */
-#define EXTI_PR1_PIF4            EXTI_PR1_PIF4_Msk                             /*!< Pending bit for line 4 */
-#define EXTI_PR1_PIF5_Pos        (5U)
-#define EXTI_PR1_PIF5_Msk        (0x1UL << EXTI_PR1_PIF5_Pos)                  /*!< 0x00000020 */
-#define EXTI_PR1_PIF5            EXTI_PR1_PIF5_Msk                             /*!< Pending bit for line 5 */
-#define EXTI_PR1_PIF6_Pos        (6U)
-#define EXTI_PR1_PIF6_Msk        (0x1UL << EXTI_PR1_PIF6_Pos)                  /*!< 0x00000040 */
-#define EXTI_PR1_PIF6            EXTI_PR1_PIF6_Msk                             /*!< Pending bit for line 6 */
-#define EXTI_PR1_PIF7_Pos        (7U)
-#define EXTI_PR1_PIF7_Msk        (0x1UL << EXTI_PR1_PIF7_Pos)                  /*!< 0x00000080 */
-#define EXTI_PR1_PIF7            EXTI_PR1_PIF7_Msk                             /*!< Pending bit for line 7 */
-#define EXTI_PR1_PIF8_Pos        (8U)
-#define EXTI_PR1_PIF8_Msk        (0x1UL << EXTI_PR1_PIF8_Pos)                  /*!< 0x00000100 */
-#define EXTI_PR1_PIF8            EXTI_PR1_PIF8_Msk                             /*!< Pending bit for line 8 */
-#define EXTI_PR1_PIF9_Pos        (9U)
-#define EXTI_PR1_PIF9_Msk        (0x1UL << EXTI_PR1_PIF9_Pos)                  /*!< 0x00000200 */
-#define EXTI_PR1_PIF9            EXTI_PR1_PIF9_Msk                             /*!< Pending bit for line 9 */
-#define EXTI_PR1_PIF10_Pos       (10U)
-#define EXTI_PR1_PIF10_Msk       (0x1UL << EXTI_PR1_PIF10_Pos)                 /*!< 0x00000400 */
-#define EXTI_PR1_PIF10           EXTI_PR1_PIF10_Msk                            /*!< Pending bit for line 10 */
-#define EXTI_PR1_PIF11_Pos       (11U)
-#define EXTI_PR1_PIF11_Msk       (0x1UL << EXTI_PR1_PIF11_Pos)                 /*!< 0x00000800 */
-#define EXTI_PR1_PIF11           EXTI_PR1_PIF11_Msk                            /*!< Pending bit for line 11 */
-#define EXTI_PR1_PIF12_Pos       (12U)
-#define EXTI_PR1_PIF12_Msk       (0x1UL << EXTI_PR1_PIF12_Pos)                 /*!< 0x00001000 */
-#define EXTI_PR1_PIF12           EXTI_PR1_PIF12_Msk                            /*!< Pending bit for line 12 */
-#define EXTI_PR1_PIF13_Pos       (13U)
-#define EXTI_PR1_PIF13_Msk       (0x1UL << EXTI_PR1_PIF13_Pos)                 /*!< 0x00002000 */
-#define EXTI_PR1_PIF13           EXTI_PR1_PIF13_Msk                            /*!< Pending bit for line 13 */
-#define EXTI_PR1_PIF14_Pos       (14U)
-#define EXTI_PR1_PIF14_Msk       (0x1UL << EXTI_PR1_PIF14_Pos)                 /*!< 0x00004000 */
-#define EXTI_PR1_PIF14           EXTI_PR1_PIF14_Msk                            /*!< Pending bit for line 14 */
-#define EXTI_PR1_PIF15_Pos       (15U)
-#define EXTI_PR1_PIF15_Msk       (0x1UL << EXTI_PR1_PIF15_Pos)                 /*!< 0x00008000 */
-#define EXTI_PR1_PIF15           EXTI_PR1_PIF15_Msk                            /*!< Pending bit for line 15 */
-#define EXTI_PR1_PIF16_Pos       (16U)
-#define EXTI_PR1_PIF16_Msk       (0x1UL << EXTI_PR1_PIF16_Pos)                 /*!< 0x00010000 */
-#define EXTI_PR1_PIF16           EXTI_PR1_PIF16_Msk                            /*!< Pending bit for line 16 */
-#define EXTI_PR1_PIF21_Pos       (21U)
-#define EXTI_PR1_PIF21_Msk       (0x1UL << EXTI_PR1_PIF21_Pos)                 /*!< 0x00200000 */
-#define EXTI_PR1_PIF21           EXTI_PR1_PIF21_Msk                            /*!< Pending bit for line 21 */
-#define EXTI_PR1_PIF22_Pos       (22U)
-#define EXTI_PR1_PIF22_Msk       (0x1UL << EXTI_PR1_PIF22_Pos)                 /*!< 0x00400000 */
-#define EXTI_PR1_PIF22           EXTI_PR1_PIF22_Msk                            /*!< Pending bit for line 22 */
-
-/******************  Bit definition for EXTI_RTSR2 register  ******************/
-#define EXTI_RTSR2_RT34_Pos      (2U)
-#define EXTI_RTSR2_RT34_Msk      (0x1UL << EXTI_RTSR2_RT34_Pos)                /*!< 0x00000004 */
-#define EXTI_RTSR2_RT34          EXTI_RTSR2_RT34_Msk                           /*!< Rising trigger event configuration bit of line 34 */
-#define EXTI_RTSR2_RT45_Pos      (13U)
-#define EXTI_RTSR2_RT45_Msk      (0x1UL << EXTI_RTSR2_RT45_Pos)                /*!< 0x00002000 */
-#define EXTI_RTSR2_RT45          EXTI_RTSR2_RT45_Msk                           /*!< Rising trigger event configuration bit of line 45 */
-
-/******************  Bit definition for EXTI_FTSR2 register  ******************/
-#define EXTI_FTSR2_FT34_Pos      (2U)
-#define EXTI_FTSR2_FT34_Msk      (0x1UL << EXTI_FTSR2_FT34_Pos)                /*!< 0x00000004 */
-#define EXTI_FTSR2_FT34          EXTI_FTSR2_FT34_Msk                           /*!< Falling trigger event configuration bit of line 34 */
-#define EXTI_FTSR2_FT45_Pos      (13U)
-#define EXTI_FTSR2_FT45_Msk      (0x1UL << EXTI_FTSR2_FT45_Pos)                /*!< 0x00002000 */
-#define EXTI_FTSR2_FT45          EXTI_FTSR2_FT45_Msk                           /*!< Falling trigger event configuration bit of line 45 */
-
-/******************  Bit definition for EXTI_SWIER2 register  *****************/
-#define EXTI_SWIER2_SWI34_Pos    (2U)
-#define EXTI_SWIER2_SWI34_Msk    (0x1UL << EXTI_SWIER2_SWI34_Pos)              /*!< 0x00000004 */
-#define EXTI_SWIER2_SWI34        EXTI_SWIER2_SWI34_Msk                         /*!< Software Interrupt on line 34 */
-#define EXTI_SWIER2_SWI45_Pos    (13U)
-#define EXTI_SWIER2_SWI45_Msk    (0x1UL << EXTI_SWIER2_SWI45_Pos)              /*!< 0x00002000 */
-#define EXTI_SWIER2_SWI45        EXTI_SWIER2_SWI45_Msk                         /*!< Software Interrupt on line 45 */
-
-/*******************  Bit definition for EXTI_PR2 register  *******************/
-#define EXTI_PR2_PIF34_Pos       (2U)
-#define EXTI_PR2_PIF34_Msk       (0x1UL << EXTI_PR2_PIF34_Pos)                 /*!< 0x00000004 */
-#define EXTI_PR2_PIF34           EXTI_PR2_PIF34_Msk                            /*!< Pending bit for line 34 */
-#define EXTI_PR2_PIF45_Pos       (13U)
-#define EXTI_PR2_PIF45_Msk       (0x1UL << EXTI_PR2_PIF45_Pos)                 /*!< 0x00002000 */
-#define EXTI_PR2_PIF45           EXTI_PR2_PIF45_Msk                            /*!< Pending bit for line 45 */
-
-/********************  Bits definition for EXTI_IMR1 register  **************/
-#define EXTI_IMR1_IM0_Pos        (0U)
-#define EXTI_IMR1_IM0_Msk        (0x1UL << EXTI_IMR1_IM0_Pos)                  /*!< 0x00000001 */
-#define EXTI_IMR1_IM0            EXTI_IMR1_IM0_Msk                             /*!< CPU1 Interrupt Mask on line 0 */
-#define EXTI_IMR1_IM1_Pos        (1U)
-#define EXTI_IMR1_IM1_Msk        (0x1UL << EXTI_IMR1_IM1_Pos)                  /*!< 0x00000002 */
-#define EXTI_IMR1_IM1            EXTI_IMR1_IM1_Msk                             /*!< CPU1 Interrupt Mask on line 1 */
-#define EXTI_IMR1_IM2_Pos        (2U)
-#define EXTI_IMR1_IM2_Msk        (0x1UL << EXTI_IMR1_IM2_Pos)                  /*!< 0x00000004 */
-#define EXTI_IMR1_IM2            EXTI_IMR1_IM2_Msk                             /*!< CPU1 Interrupt Mask on line 2 */
-#define EXTI_IMR1_IM3_Pos        (3U)
-#define EXTI_IMR1_IM3_Msk        (0x1UL << EXTI_IMR1_IM3_Pos)                  /*!< 0x00000008 */
-#define EXTI_IMR1_IM3            EXTI_IMR1_IM3_Msk                             /*!< CPU1 Interrupt Mask on line 3 */
-#define EXTI_IMR1_IM4_Pos        (4U)
-#define EXTI_IMR1_IM4_Msk        (0x1UL << EXTI_IMR1_IM4_Pos)                  /*!< 0x00000010 */
-#define EXTI_IMR1_IM4            EXTI_IMR1_IM4_Msk                             /*!< CPU1 Interrupt Mask on line 4 */
-#define EXTI_IMR1_IM5_Pos        (5U)
-#define EXTI_IMR1_IM5_Msk        (0x1UL << EXTI_IMR1_IM5_Pos)                  /*!< 0x00000020 */
-#define EXTI_IMR1_IM5            EXTI_IMR1_IM5_Msk                             /*!< CPU1 Interrupt Mask on line 5 */
-#define EXTI_IMR1_IM6_Pos        (6U)
-#define EXTI_IMR1_IM6_Msk        (0x1UL << EXTI_IMR1_IM6_Pos)                  /*!< 0x00000040 */
-#define EXTI_IMR1_IM6            EXTI_IMR1_IM6_Msk                             /*!< CPU1 Interrupt Mask on line 6 */
-#define EXTI_IMR1_IM7_Pos        (7U)
-#define EXTI_IMR1_IM7_Msk        (0x1UL << EXTI_IMR1_IM7_Pos)                  /*!< 0x00000080 */
-#define EXTI_IMR1_IM7            EXTI_IMR1_IM7_Msk                             /*!< CPU1 Interrupt Mask on line 7 */
-#define EXTI_IMR1_IM8_Pos        (8U)
-#define EXTI_IMR1_IM8_Msk        (0x1UL << EXTI_IMR1_IM8_Pos)                  /*!< 0x00000100 */
-#define EXTI_IMR1_IM8            EXTI_IMR1_IM8_Msk                             /*!< CPU1 Interrupt Mask on line 8 */
-#define EXTI_IMR1_IM9_Pos        (9U)
-#define EXTI_IMR1_IM9_Msk        (0x1UL << EXTI_IMR1_IM9_Pos)                  /*!< 0x00000200 */
-#define EXTI_IMR1_IM9            EXTI_IMR1_IM9_Msk                             /*!< CPU1 Interrupt Mask on line 9 */
-#define EXTI_IMR1_IM10_Pos       (10U)
-#define EXTI_IMR1_IM10_Msk       (0x1UL << EXTI_IMR1_IM10_Pos)                 /*!< 0x00000400 */
-#define EXTI_IMR1_IM10           EXTI_IMR1_IM10_Msk                            /*!< CPU1 Interrupt Mask on line 10 */
-#define EXTI_IMR1_IM11_Pos       (11U)
-#define EXTI_IMR1_IM11_Msk       (0x1UL << EXTI_IMR1_IM11_Pos)                 /*!< 0x00000800 */
-#define EXTI_IMR1_IM11           EXTI_IMR1_IM11_Msk                            /*!< CPU1 Interrupt Mask on line 11 */
-#define EXTI_IMR1_IM12_Pos       (12U)
-#define EXTI_IMR1_IM12_Msk       (0x1UL << EXTI_IMR1_IM12_Pos)                 /*!< 0x00001000 */
-#define EXTI_IMR1_IM12           EXTI_IMR1_IM12_Msk                            /*!< CPU1 Interrupt Mask on line 12 */
-#define EXTI_IMR1_IM13_Pos       (13U)
-#define EXTI_IMR1_IM13_Msk       (0x1UL << EXTI_IMR1_IM13_Pos)                 /*!< 0x00002000 */
-#define EXTI_IMR1_IM13           EXTI_IMR1_IM13_Msk                            /*!< CPU1 Interrupt Mask on line 13 */
-#define EXTI_IMR1_IM14_Pos       (14U)
-#define EXTI_IMR1_IM14_Msk       (0x1UL << EXTI_IMR1_IM14_Pos)                 /*!< 0x00004000 */
-#define EXTI_IMR1_IM14           EXTI_IMR1_IM14_Msk                            /*!< CPU1 Interrupt Mask on line 14 */
-#define EXTI_IMR1_IM15_Pos       (15U)
-#define EXTI_IMR1_IM15_Msk       (0x1UL << EXTI_IMR1_IM15_Pos)                 /*!< 0x00008000 */
-#define EXTI_IMR1_IM15           EXTI_IMR1_IM15_Msk                            /*!< CPU1 Interrupt Mask on line 15 */
-#define EXTI_IMR1_IM16_Pos       (16U)
-#define EXTI_IMR1_IM16_Msk       (0x1UL << EXTI_IMR1_IM16_Pos)                 /*!< 0x00010000 */
-#define EXTI_IMR1_IM16           EXTI_IMR1_IM16_Msk                            /*!< CPU1 Interrupt Mask on line 16 */
-#define EXTI_IMR1_IM17_Pos       (17U)
-#define EXTI_IMR1_IM17_Msk       (0x1UL << EXTI_IMR1_IM17_Pos)                 /*!< 0x00020000 */
-#define EXTI_IMR1_IM17           EXTI_IMR1_IM17_Msk                            /*!< CPU1 Interrupt Mask on line 17 */
-#define EXTI_IMR1_IM18_Pos       (18U)
-#define EXTI_IMR1_IM18_Msk       (0x1UL << EXTI_IMR1_IM18_Pos)                 /*!< 0x00040000 */
-#define EXTI_IMR1_IM18           EXTI_IMR1_IM18_Msk                            /*!< CPU1 Interrupt Mask on line 18 */
-#define EXTI_IMR1_IM19_Pos       (19U)
-#define EXTI_IMR1_IM19_Msk       (0x1UL << EXTI_IMR1_IM19_Pos)                 /*!< 0x00080000 */
-#define EXTI_IMR1_IM19           EXTI_IMR1_IM19_Msk                            /*!< CPU1 Interrupt Mask on line 19 */
-#define EXTI_IMR1_IM20_Pos       (20U)
-#define EXTI_IMR1_IM20_Msk       (0x1UL << EXTI_IMR1_IM20_Pos)                 /*!< 0x00100000 */
-#define EXTI_IMR1_IM20           EXTI_IMR1_IM20_Msk                            /*!< CPU1 Interrupt Mask on line 20 */
-#define EXTI_IMR1_IM21_Pos       (21U)
-#define EXTI_IMR1_IM21_Msk       (0x1UL << EXTI_IMR1_IM21_Pos)                 /*!< 0x00200000 */
-#define EXTI_IMR1_IM21           EXTI_IMR1_IM21_Msk                            /*!< CPU1 Interrupt Mask on line 21 */
-#define EXTI_IMR1_IM22_Pos       (22U)
-#define EXTI_IMR1_IM22_Msk       (0x1UL << EXTI_IMR1_IM22_Pos)                 /*!< 0x00400000 */
-#define EXTI_IMR1_IM22           EXTI_IMR1_IM22_Msk                            /*!< CPU1 Interrupt Mask on line 22 */
-#define EXTI_IMR1_IM23_Pos       (23U)
-#define EXTI_IMR1_IM23_Msk       (0x1UL << EXTI_IMR1_IM23_Pos)                 /*!< 0x00800000 */
-#define EXTI_IMR1_IM23           EXTI_IMR1_IM23_Msk                            /*!< CPU1 Interrupt Mask on line 23 */
-#define EXTI_IMR1_IM24_Pos       (24U)
-#define EXTI_IMR1_IM24_Msk       (0x1UL << EXTI_IMR1_IM24_Pos)                 /*!< 0x01000000 */
-#define EXTI_IMR1_IM24           EXTI_IMR1_IM24_Msk                            /*!< CPU1 Interrupt Mask on line 24 */
-#define EXTI_IMR1_IM25_Pos       (25U)
-#define EXTI_IMR1_IM25_Msk       (0x1UL << EXTI_IMR1_IM25_Pos)                 /*!< 0x02000000 */
-#define EXTI_IMR1_IM25           EXTI_IMR1_IM25_Msk                            /*!< CPU1 Interrupt Mask on line 25 */
-#define EXTI_IMR1_IM26_Pos       (26U)
-#define EXTI_IMR1_IM26_Msk       (0x1UL << EXTI_IMR1_IM26_Pos)                 /*!< 0x04000000 */
-#define EXTI_IMR1_IM26           EXTI_IMR1_IM26_Msk                            /*!< CPU1 Interrupt Mask on line 26 */
-#define EXTI_IMR1_IM27_Pos       (27U)
-#define EXTI_IMR1_IM27_Msk       (0x1UL << EXTI_IMR1_IM27_Pos)                 /*!< 0x08000000 */
-#define EXTI_IMR1_IM27           EXTI_IMR1_IM27_Msk                            /*!< CPU1 Interrupt Mask on line 27 */
-#define EXTI_IMR1_IM28_Pos       (28U)
-#define EXTI_IMR1_IM28_Msk       (0x1UL << EXTI_IMR1_IM28_Pos)                 /*!< 0x10000000 */
-#define EXTI_IMR1_IM28           EXTI_IMR1_IM28_Msk                            /*!< CPU1 Interrupt Mask on line 28 */
-#define EXTI_IMR1_IM29_Pos       (29U)
-#define EXTI_IMR1_IM29_Msk       (0x1UL << EXTI_IMR1_IM29_Pos)                 /*!< 0x20000000 */
-#define EXTI_IMR1_IM29           EXTI_IMR1_IM29_Msk                            /*!< CPU1 Interrupt Mask on line 29 */
-#define EXTI_IMR1_IM30_Pos       (30U)
-#define EXTI_IMR1_IM30_Msk       (0x1UL << EXTI_IMR1_IM30_Pos)                 /*!< 0x40000000 */
-#define EXTI_IMR1_IM30           EXTI_IMR1_IM30_Msk                            /*!< CPU1 Interrupt Mask on line 30 */
-#define EXTI_IMR1_IM31_Pos       (31U)
-#define EXTI_IMR1_IM31_Msk       (0x1UL << EXTI_IMR1_IM31_Pos)                 /*!< 0x80000000 */
-#define EXTI_IMR1_IM31           EXTI_IMR1_IM31_Msk                            /*!< CPU1 Interrupt Mask on line 31 */
-
-/********************  Bits definition for EXTI_EMR1 register  **************/
-#define EXTI_EMR1_EM0_Pos        (0U)
-#define EXTI_EMR1_EM0_Msk        (0x1UL << EXTI_EMR1_EM0_Pos)                  /*!< 0x00000001 */
-#define EXTI_EMR1_EM0            EXTI_EMR1_EM0_Msk                             /*!< CPU1 Event Mask on line 0 */
-#define EXTI_EMR1_EM1_Pos        (1U)
-#define EXTI_EMR1_EM1_Msk        (0x1UL << EXTI_EMR1_EM1_Pos)                  /*!< 0x00000002 */
-#define EXTI_EMR1_EM1            EXTI_EMR1_EM1_Msk                             /*!< CPU1 Event Mask on line 1 */
-#define EXTI_EMR1_EM2_Pos        (2U)
-#define EXTI_EMR1_EM2_Msk        (0x1UL << EXTI_EMR1_EM2_Pos)                  /*!< 0x00000004 */
-#define EXTI_EMR1_EM2            EXTI_EMR1_EM2_Msk                             /*!< CPU1 Event Mask on line 2 */
-#define EXTI_EMR1_EM3_Pos        (3U)
-#define EXTI_EMR1_EM3_Msk        (0x1UL << EXTI_EMR1_EM3_Pos)                  /*!< 0x00000008 */
-#define EXTI_EMR1_EM3            EXTI_EMR1_EM3_Msk                             /*!< CPU1 Event Mask on line 3 */
-#define EXTI_EMR1_EM4_Pos        (4U)
-#define EXTI_EMR1_EM4_Msk        (0x1UL << EXTI_EMR1_EM4_Pos)                  /*!< 0x00000010 */
-#define EXTI_EMR1_EM4            EXTI_EMR1_EM4_Msk                             /*!< CPU1 Event Mask on line 4 */
-#define EXTI_EMR1_EM5_Pos        (5U)
-#define EXTI_EMR1_EM5_Msk        (0x1UL << EXTI_EMR1_EM5_Pos)                  /*!< 0x00000020 */
-#define EXTI_EMR1_EM5            EXTI_EMR1_EM5_Msk                             /*!< CPU1 Event Mask on line 5 */
-#define EXTI_EMR1_EM6_Pos        (6U)
-#define EXTI_EMR1_EM6_Msk        (0x1UL << EXTI_EMR1_EM6_Pos)                  /*!< 0x00000040 */
-#define EXTI_EMR1_EM6            EXTI_EMR1_EM6_Msk                             /*!< CPU1 Event Mask on line 6 */
-#define EXTI_EMR1_EM7_Pos        (7U)
-#define EXTI_EMR1_EM7_Msk        (0x1UL << EXTI_EMR1_EM7_Pos)                  /*!< 0x00000080 */
-#define EXTI_EMR1_EM7            EXTI_EMR1_EM7_Msk                             /*!< CPU1 Event Mask on line 7 */
-#define EXTI_EMR1_EM8_Pos        (8U)
-#define EXTI_EMR1_EM8_Msk        (0x1UL << EXTI_EMR1_EM8_Pos)                  /*!< 0x00000100 */
-#define EXTI_EMR1_EM8            EXTI_EMR1_EM8_Msk                             /*!< CPU1 Event Mask on line 8 */
-#define EXTI_EMR1_EM9_Pos        (9U)
-#define EXTI_EMR1_EM9_Msk        (0x1UL << EXTI_EMR1_EM9_Pos)                  /*!< 0x00000200 */
-#define EXTI_EMR1_EM9            EXTI_EMR1_EM9_Msk                             /*!< CPU1 Event Mask on line 9 */
-#define EXTI_EMR1_EM10_Pos       (10U)
-#define EXTI_EMR1_EM10_Msk       (0x1UL << EXTI_EMR1_EM10_Pos)                 /*!< 0x00000400 */
-#define EXTI_EMR1_EM10           EXTI_EMR1_EM10_Msk                            /*!< CPU1 Event Mask on line 10 */
-#define EXTI_EMR1_EM11_Pos       (11U)
-#define EXTI_EMR1_EM11_Msk       (0x1UL << EXTI_EMR1_EM11_Pos)                 /*!< 0x00000800 */
-#define EXTI_EMR1_EM11           EXTI_EMR1_EM11_Msk                            /*!< CPU1 Event Mask on line 11 */
-#define EXTI_EMR1_EM12_Pos       (12U)
-#define EXTI_EMR1_EM12_Msk       (0x1UL << EXTI_EMR1_EM12_Pos)                 /*!< 0x00001000 */
-#define EXTI_EMR1_EM12           EXTI_EMR1_EM12_Msk                            /*!< CPU1 Event Mask on line 12 */
-#define EXTI_EMR1_EM13_Pos       (13U)
-#define EXTI_EMR1_EM13_Msk       (0x1UL << EXTI_EMR1_EM13_Pos)                 /*!< 0x00002000 */
-#define EXTI_EMR1_EM13           EXTI_EMR1_EM13_Msk                            /*!< CPU1 Event Mask on line 13 */
-#define EXTI_EMR1_EM14_Pos       (14U)
-#define EXTI_EMR1_EM14_Msk       (0x1UL << EXTI_EMR1_EM14_Pos)                 /*!< 0x00004000 */
-#define EXTI_EMR1_EM14           EXTI_EMR1_EM14_Msk                            /*!< CPU1 Event Mask on line 14 */
-#define EXTI_EMR1_EM15_Pos       (15U)
-#define EXTI_EMR1_EM15_Msk       (0x1UL << EXTI_EMR1_EM15_Pos)                 /*!< 0x00008000 */
-#define EXTI_EMR1_EM15           EXTI_EMR1_EM15_Msk                            /*!< CPU1 Event Mask on line 15 */
-#define EXTI_EMR1_EM17_Pos       (17U)
-#define EXTI_EMR1_EM17_Msk       (0x1UL << EXTI_EMR1_EM17_Pos)                 /*!< 0x00020000 */
-#define EXTI_EMR1_EM17           EXTI_EMR1_EM17_Msk                            /*!< CPU1 Event Mask on line 17 */
-#define EXTI_EMR1_EM19_Pos       (19U)
-#define EXTI_EMR1_EM19_Msk       (0x1UL << EXTI_EMR1_EM19_Pos)                 /*!< 0x00080000 */
-#define EXTI_EMR1_EM19           EXTI_EMR1_EM19_Msk                            /*!< CPU1 Event Mask on line 19 */
-#define EXTI_EMR1_EM20_Pos       (20U)
-#define EXTI_EMR1_EM20_Msk       (0x1UL << EXTI_EMR1_EM20_Pos)                 /*!< 0x00100000 */
-#define EXTI_EMR1_EM20           EXTI_EMR1_EM20_Msk                            /*!< CPU1 Event Mask on line 20 */
-#define EXTI_EMR1_EM21_Pos       (21U)
-#define EXTI_EMR1_EM21_Msk       (0x1UL << EXTI_EMR1_EM21_Pos)                 /*!< 0x00200000 */
-#define EXTI_EMR1_EM21           EXTI_EMR1_EM21_Msk                            /*!< CPU1 Event Mask on line 21 */
-#define EXTI_EMR1_EM22_Pos       (22U)
-#define EXTI_EMR1_EM22_Msk       (0x1UL << EXTI_EMR1_EM22_Pos)                 /*!< 0x00400000 */
-#define EXTI_EMR1_EM22           EXTI_EMR1_EM22_Msk                            /*!< CPU1 Event Mask on line 22 */
-
-/********************  Bits definition for EXTI_IMR2 register  **************/
-#define EXTI_IMR2_IM34_Pos       (2U)
-#define EXTI_IMR2_IM34_Msk       (0x1UL << EXTI_IMR2_IM34_Pos)                 /*!< 0x00000004 */
-#define EXTI_IMR2_IM34           EXTI_IMR2_IM34_Msk                            /*!< CPU1 Interrupt Mask on line 34 */
-#define EXTI_IMR2_IM38_Pos       (6U)
-#define EXTI_IMR2_IM38_Msk       (0x1UL << EXTI_IMR2_IM38_Pos)                 /*!< 0x00000040 */
-#define EXTI_IMR2_IM38           EXTI_IMR2_IM38_Msk                            /*!< CPU1 Interrupt Mask on line 38 */
-#define EXTI_IMR2_IM42_Pos       (10U)
-#define EXTI_IMR2_IM42_Msk       (0x1UL << EXTI_IMR2_IM42_Pos)                 /*!< 0x00000400 */
-#define EXTI_IMR2_IM42           EXTI_IMR2_IM42_Msk                            /*!< CPU1 Interrupt Mask on line 42 */
-#define EXTI_IMR2_IM43_Pos       (11U)
-#define EXTI_IMR2_IM43_Msk       (0x1UL << EXTI_IMR2_IM43_Pos)                 /*!< 0x00000800 */
-#define EXTI_IMR2_IM43           EXTI_IMR2_IM43_Msk                            /*!< CPU1 Interrupt Mask on line 43 */
-#define EXTI_IMR2_IM44_Pos       (12U)
-#define EXTI_IMR2_IM44_Msk       (0x1UL << EXTI_IMR2_IM44_Pos)                 /*!< 0x00001000 */
-#define EXTI_IMR2_IM44           EXTI_IMR2_IM44_Msk                            /*!< CPU1 Interrupt Mask on line 44 */
-#define EXTI_IMR2_IM45_Pos       (13U)
-#define EXTI_IMR2_IM45_Msk       (0x1UL << EXTI_IMR2_IM45_Pos)                 /*!< 0x00002000 */
-#define EXTI_IMR2_IM45           EXTI_IMR2_IM45_Msk                            /*!< CPU1 Interrupt Mask on line 45 */
-#define EXTI_IMR2_IM46_Pos       (14U)
-#define EXTI_IMR2_IM46_Msk       (0x1UL << EXTI_IMR2_IM46_Pos)                 /*!< 0x00004000 */
-#define EXTI_IMR2_IM46           EXTI_IMR2_IM46_Msk                            /*!< CPU1 Interrupt Mask on line 46 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY_Pos               (0U)
-#define FLASH_ACR_LATENCY_Msk               (0x7UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000007 */
-#define FLASH_ACR_LATENCY                   FLASH_ACR_LATENCY_Msk              /*!< Latency                                             */
-#define FLASH_ACR_LATENCY_0                 (0x1UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
-#define FLASH_ACR_LATENCY_1                 (0x2UL << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000002 */
-#define FLASH_ACR_PRFTEN_Pos                (8U)
-#define FLASH_ACR_PRFTEN_Msk                (0x1UL << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000100 */
-#define FLASH_ACR_PRFTEN                    FLASH_ACR_PRFTEN_Msk               /*!< Prefetch enable                                     */
-#define FLASH_ACR_ICEN_Pos                  (9U)
-#define FLASH_ACR_ICEN_Msk                  (0x1UL << FLASH_ACR_ICEN_Pos)      /*!< 0x00000200 */
-#define FLASH_ACR_ICEN                      FLASH_ACR_ICEN_Msk                 /*!< Instruction cache enable                            */
-#define FLASH_ACR_DCEN_Pos                  (10U)
-#define FLASH_ACR_DCEN_Msk                  (0x1UL << FLASH_ACR_DCEN_Pos)      /*!< 0x00000400 */
-#define FLASH_ACR_DCEN                      FLASH_ACR_DCEN_Msk                 /*!< Data cache enable                                   */
-#define FLASH_ACR_ICRST_Pos                 (11U)
-#define FLASH_ACR_ICRST_Msk                 (0x1UL << FLASH_ACR_ICRST_Pos)     /*!< 0x00000800 */
-#define FLASH_ACR_ICRST                     FLASH_ACR_ICRST_Msk                /*!< Instruction cache reset                             */
-#define FLASH_ACR_DCRST_Pos                 (12U)
-#define FLASH_ACR_DCRST_Msk                 (0x1UL << FLASH_ACR_DCRST_Pos)     /*!< 0x00001000 */
-#define FLASH_ACR_DCRST                     FLASH_ACR_DCRST_Msk                /*!< Data cache reset                                    */
-#define FLASH_ACR_PES_Pos                   (15U)
-#define FLASH_ACR_PES_Msk                   (0x1UL << FLASH_ACR_PES_Pos)       /*!< 0x00008000 */
-#define FLASH_ACR_PES                       FLASH_ACR_PES_Msk                  /*!< Program/erase suspend request                       */
-#define FLASH_ACR_EMPTY_Pos                 (16U)
-#define FLASH_ACR_EMPTY_Msk                 (0x1UL << FLASH_ACR_EMPTY_Pos)     /*!< 0x00010000 */
-#define FLASH_ACR_EMPTY                     FLASH_ACR_EMPTY_Msk                /*!< Flash use area empty                                */
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP_Pos                    (0U)
-#define FLASH_SR_EOP_Msk                    (0x1UL << FLASH_SR_EOP_Pos)        /*!< 0x00000001 */
-#define FLASH_SR_EOP                        FLASH_SR_EOP_Msk                   /*!< End of Operation                                    */
-#define FLASH_SR_OPERR_Pos                  (1U)
-#define FLASH_SR_OPERR_Msk                  (0x1UL << FLASH_SR_OPERR_Pos)      /*!< 0x00000002 */
-#define FLASH_SR_OPERR                      FLASH_SR_OPERR_Msk                 /*!< Operation error                                     */
-#define FLASH_SR_PROGERR_Pos                (3U)
-#define FLASH_SR_PROGERR_Msk                (0x1UL << FLASH_SR_PROGERR_Pos)    /*!< 0x00000008 */
-#define FLASH_SR_PROGERR                    FLASH_SR_PROGERR_Msk               /*!< Programming error                                   */
-#define FLASH_SR_WRPERR_Pos                 (4U)
-#define FLASH_SR_WRPERR_Msk                 (0x1UL << FLASH_SR_WRPERR_Pos)     /*!< 0x00000010 */
-#define FLASH_SR_WRPERR                     FLASH_SR_WRPERR_Msk                /*!< Write protection error                              */
-#define FLASH_SR_PGAERR_Pos                 (5U)
-#define FLASH_SR_PGAERR_Msk                 (0x1UL << FLASH_SR_PGAERR_Pos)     /*!< 0x00000020 */
-#define FLASH_SR_PGAERR                     FLASH_SR_PGAERR_Msk                /*!< Programming alignment error                         */
-#define FLASH_SR_SIZERR_Pos                 (6U)
-#define FLASH_SR_SIZERR_Msk                 (0x1UL << FLASH_SR_SIZERR_Pos)     /*!< 0x00000040 */
-#define FLASH_SR_SIZERR                     FLASH_SR_SIZERR_Msk                /*!< Size error                                          */
-#define FLASH_SR_PGSERR_Pos                 (7U)
-#define FLASH_SR_PGSERR_Msk                 (0x1UL << FLASH_SR_PGSERR_Pos)     /*!< 0x00000080 */
-#define FLASH_SR_PGSERR                     FLASH_SR_PGSERR_Msk                /*!< Programming sequence error                          */
-#define FLASH_SR_MISERR_Pos                 (8U)
-#define FLASH_SR_MISERR_Msk                 (0x1UL << FLASH_SR_MISERR_Pos)     /*!< 0x00000100 */
-#define FLASH_SR_MISERR                     FLASH_SR_MISERR_Msk                /*!< Fast programming data miss error                    */
-#define FLASH_SR_FASTERR_Pos                (9U)
-#define FLASH_SR_FASTERR_Msk                (0x1UL << FLASH_SR_FASTERR_Pos)    /*!< 0x00000200 */
-#define FLASH_SR_FASTERR                    FLASH_SR_FASTERR_Msk               /*!< Fast programming error                              */
-#define FLASH_SR_OPTNV_Pos                  (13U)
-#define FLASH_SR_OPTNV_Msk                  (0x1UL << FLASH_SR_OPTNV_Pos)     /*!< 0x00002000 */
-#define FLASH_SR_OPTNV                      FLASH_SR_OPTNV_Msk                /*!< User option OPTVAL indication                       */
-#define FLASH_SR_RDERR_Pos                  (14U)
-#define FLASH_SR_RDERR_Msk                  (0x1UL << FLASH_SR_RDERR_Pos)      /*!< 0x00004000 */
-#define FLASH_SR_RDERR                      FLASH_SR_RDERR_Msk                 /*!< PCROP read error                                    */
-#define FLASH_SR_OPTVERR_Pos                (15U)
-#define FLASH_SR_OPTVERR_Msk                (0x1UL << FLASH_SR_OPTVERR_Pos)    /*!< 0x00008000 */
-#define FLASH_SR_OPTVERR                    FLASH_SR_OPTVERR_Msk               /*!< Option validity error                               */
-#define FLASH_SR_BSY_Pos                    (16U)
-#define FLASH_SR_BSY_Msk                    (0x1UL << FLASH_SR_BSY_Pos)        /*!< 0x00010000 */
-#define FLASH_SR_BSY                        FLASH_SR_BSY_Msk                   /*!< Flash Busy                                          */
-#define FLASH_SR_CFGBSY_Pos                 (18U)
-#define FLASH_SR_CFGBSY_Msk                 (0x1UL << FLASH_SR_CFGBSY_Pos)     /*!< 0x00040000 */
-#define FLASH_SR_CFGBSY                     FLASH_SR_CFGBSY_Msk                /*!< Programming or erase configuration busy             */
-#define FLASH_SR_PESD_Pos                   (19U)
-#define FLASH_SR_PESD_Msk                   (0x1UL << FLASH_SR_PESD_Pos)       /*!< 0x00080000 */
-#define FLASH_SR_PESD                       FLASH_SR_PESD_Msk                  /*!< Programming/erase operation suspended               */
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG_Pos                     (0U)
-#define FLASH_CR_PG_Msk                     (0x1UL << FLASH_CR_PG_Pos)         /*!< 0x00000001 */
-#define FLASH_CR_PG                         FLASH_CR_PG_Msk                    /*!< Flash programming                                   */
-#define FLASH_CR_PER_Pos                    (1U)
-#define FLASH_CR_PER_Msk                    (0x1UL << FLASH_CR_PER_Pos)        /*!< 0x00000002 */
-#define FLASH_CR_PER                        FLASH_CR_PER_Msk                   /*!< Page erase                                          */
-#define FLASH_CR_MER_Pos                    (2U)
-#define FLASH_CR_MER_Msk                    (0x1UL << FLASH_CR_MER_Pos)        /*!< 0x00000004 */
-#define FLASH_CR_MER                        FLASH_CR_MER_Msk                   /*!< Mass erase                                          */
-#define FLASH_CR_PNB_Pos                    (3U)
-#define FLASH_CR_PNB_Msk                    (0x7FUL << FLASH_CR_PNB_Pos)       /*!< 0x000003F8 */
-#define FLASH_CR_PNB                        FLASH_CR_PNB_Msk                   /*!< Page number selection mask                          */
-#define FLASH_CR_STRT_Pos                   (16U)
-#define FLASH_CR_STRT_Msk                   (0x1UL << FLASH_CR_STRT_Pos)       /*!< 0x00010000 */
-#define FLASH_CR_STRT                       FLASH_CR_STRT_Msk                  /*!< Start an erase operation                            */
-#define FLASH_CR_OPTSTRT_Pos                (17U)
-#define FLASH_CR_OPTSTRT_Msk                (0x1UL << FLASH_CR_OPTSTRT_Pos)    /*!< 0x00020000 */
-#define FLASH_CR_OPTSTRT                    FLASH_CR_OPTSTRT_Msk               /*!< Options modification start                          */
-#define FLASH_CR_FSTPG_Pos                  (18U)
-#define FLASH_CR_FSTPG_Msk                  (0x1UL << FLASH_CR_FSTPG_Pos)      /*!< 0x00040000 */
-#define FLASH_CR_FSTPG                      FLASH_CR_FSTPG_Msk                 /*!< Fast programming                                    */
-#define FLASH_CR_EOPIE_Pos                  (24U)
-#define FLASH_CR_EOPIE_Msk                  (0x1UL << FLASH_CR_EOPIE_Pos)      /*!< 0x01000000 */
-#define FLASH_CR_EOPIE                      FLASH_CR_EOPIE_Msk                 /*!< End of operation interrupt enable                   */
-#define FLASH_CR_ERRIE_Pos                  (25U)
-#define FLASH_CR_ERRIE_Msk                  (0x1UL << FLASH_CR_ERRIE_Pos)      /*!< 0x02000000 */
-#define FLASH_CR_ERRIE                      FLASH_CR_ERRIE_Msk                 /*!< Error interrupt enable                              */
-#define FLASH_CR_RDERRIE_Pos                (26U)
-#define FLASH_CR_RDERRIE_Msk                (0x1UL << FLASH_CR_RDERRIE_Pos)    /*!< 0x04000000 */
-#define FLASH_CR_RDERRIE                    FLASH_CR_RDERRIE_Msk               /*!< PCROP read error interrupt enable                   */
-#define FLASH_CR_OBL_LAUNCH_Pos             (27U)
-#define FLASH_CR_OBL_LAUNCH_Msk             (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
-#define FLASH_CR_OBL_LAUNCH                 FLASH_CR_OBL_LAUNCH_Msk            /*!< Force the option bute loading                       */
-#define FLASH_CR_OPTLOCK_Pos                (30U)
-#define FLASH_CR_OPTLOCK_Msk                (0x1UL << FLASH_CR_OPTLOCK_Pos)    /*!< 0x40000000 */
-#define FLASH_CR_OPTLOCK                    FLASH_CR_OPTLOCK_Msk               /*!< Options lock                                        */
-#define FLASH_CR_LOCK_Pos                   (31U)
-#define FLASH_CR_LOCK_Msk                   (0x1UL << FLASH_CR_LOCK_Pos)       /*!< 0x80000000 */
-#define FLASH_CR_LOCK                       FLASH_CR_LOCK_Msk                  /*!< Flash control register lock                         */
-
-/*******************  Bits definition for FLASH_ECCR register  ****************/
-#define FLASH_ECCR_ADDR_ECC_Pos             (0U)
-#define FLASH_ECCR_ADDR_ECC_Msk             (0x1FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0001FFFF */
-#define FLASH_ECCR_ADDR_ECC                 FLASH_ECCR_ADDR_ECC_Msk            /*!< double-word address ECC fail                        */
-#define FLASH_ECCR_SYSF_ECC_Pos             (20U)
-#define FLASH_ECCR_SYSF_ECC_Msk             (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00100000 */
-#define FLASH_ECCR_SYSF_ECC                 FLASH_ECCR_SYSF_ECC_Msk            /*!< System flash ECC fail                               */
-#define FLASH_ECCR_ECCCIE_Pos               (24U)
-#define FLASH_ECCR_ECCCIE_Msk               (0x1UL << FLASH_ECCR_ECCCIE_Pos)   /*!< 0x01000000 */
-#define FLASH_ECCR_ECCCIE                   FLASH_ECCR_ECCCIE_Msk              /*!< ECC correction interrupt enable                     */
-#define FLASH_ECCR_CPUID_Pos                (26U)
-#define FLASH_ECCR_CPUID_Msk                (0x7UL << FLASH_ECCR_CPUID_Pos)    /*!< 0x1C000000 */
-#define FLASH_ECCR_CPUID                    FLASH_ECCR_CPUID_Msk               /*!< CPU identification                                  */
-#define FLASH_ECCR_ECCC_Pos                 (30U)
-#define FLASH_ECCR_ECCC_Msk                 (0x1UL << FLASH_ECCR_ECCC_Pos)     /*!< 0x40000000 */
-#define FLASH_ECCR_ECCC                     FLASH_ECCR_ECCC_Msk                /*!< ECC correction                                      */
-#define FLASH_ECCR_ECCD_Pos                 (31U)
-#define FLASH_ECCR_ECCD_Msk                 (0x1UL << FLASH_ECCR_ECCD_Pos)     /*!< 0x80000000 */
-#define FLASH_ECCR_ECCD                     FLASH_ECCR_ECCD_Msk                /*!< ECC detection                                       */
-
-/*******************  Bits definition for FLASH_OPTR register  ****************/
-#define FLASH_OPTR_RDP_Pos                  (0U)
-#define FLASH_OPTR_RDP_Msk                  (0xFFUL << FLASH_OPTR_RDP_Pos)     /*!< 0x000000FF */
-#define FLASH_OPTR_RDP                      FLASH_OPTR_RDP_Msk                 /*!< Read protection level                               */
-#define FLASH_OPTR_ESE_Pos                  (8U)
-#define FLASH_OPTR_ESE_Msk                  (0x1UL << FLASH_OPTR_ESE_Pos)      /*!< 0x00000100 */
-#define FLASH_OPTR_ESE                      FLASH_OPTR_ESE_Msk                 /*!< Security enable                                     */
-#define FLASH_OPTR_BOR_LEV_Pos              (9U)
-#define FLASH_OPTR_BOR_LEV_Msk              (0x7UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000E00 */
-#define FLASH_OPTR_BOR_LEV                  FLASH_OPTR_BOR_LEV_Msk             /*!< BOR reset level mask                                */
-#define FLASH_OPTR_BOR_LEV_0                (0x1UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000200 */
-#define FLASH_OPTR_BOR_LEV_1                (0x2UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000400 */
-#define FLASH_OPTR_BOR_LEV_2                (0x4UL << FLASH_OPTR_BOR_LEV_Pos)  /*!< 0x00000800 */
-#define FLASH_OPTR_nRST_STOP_Pos            (12U)
-#define FLASH_OPTR_nRST_STOP_Msk            (0x1UL << FLASH_OPTR_nRST_STOP_Pos)/*!< 0x00001000 */
-#define FLASH_OPTR_nRST_STOP                FLASH_OPTR_nRST_STOP_Msk           /*!< Reset option in Stop mode                           */
-#define FLASH_OPTR_nRST_STDBY_Pos           (13U)
-#define FLASH_OPTR_nRST_STDBY_Msk           (0x1UL << FLASH_OPTR_nRST_STDBY_Pos)/*!< 0x00002000 */
-#define FLASH_OPTR_nRST_STDBY               FLASH_OPTR_nRST_STDBY_Msk          /*!< Reset option in Standby mode                        */
-#define FLASH_OPTR_nRST_SHDW_Pos            (14U)
-#define FLASH_OPTR_nRST_SHDW_Msk            (0x1UL << FLASH_OPTR_nRST_SHDW_Pos)/*!< 0x00004000 */
-#define FLASH_OPTR_nRST_SHDW                FLASH_OPTR_nRST_SHDW_Msk           /*!< Reset option in Shutdown mode                       */
-#define FLASH_OPTR_IWDG_SW_Pos              (16U)
-#define FLASH_OPTR_IWDG_SW_Msk              (0x1UL << FLASH_OPTR_IWDG_SW_Pos)  /*!< 0x00010000 */
-#define FLASH_OPTR_IWDG_SW                  FLASH_OPTR_IWDG_SW_Msk             /*!< Independent watchdog selection                      */
-#define FLASH_OPTR_IWDG_STOP_Pos            (17U)
-#define FLASH_OPTR_IWDG_STOP_Msk            (0x1UL << FLASH_OPTR_IWDG_STOP_Pos)/*!< 0x00020000 */
-#define FLASH_OPTR_IWDG_STOP                FLASH_OPTR_IWDG_STOP_Msk           /*!< Independent watchdog counter option in Stop mode    */
-#define FLASH_OPTR_IWDG_STDBY_Pos           (18U)
-#define FLASH_OPTR_IWDG_STDBY_Msk           (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos)/*!< 0x00040000 */
-#define FLASH_OPTR_IWDG_STDBY               FLASH_OPTR_IWDG_STDBY_Msk          /*!< Independent watchdog counter option in Standby mode */
-#define FLASH_OPTR_WWDG_SW_Pos              (19U)
-#define FLASH_OPTR_WWDG_SW_Msk              (0x1UL << FLASH_OPTR_WWDG_SW_Pos)  /*!< 0x00080000 */
-#define FLASH_OPTR_WWDG_SW                  FLASH_OPTR_WWDG_SW_Msk             /*!< Window watchdog selection                           */
-#define FLASH_OPTR_nBOOT1_Pos               (23U)
-#define FLASH_OPTR_nBOOT1_Msk               (0x1UL << FLASH_OPTR_nBOOT1_Pos)   /*!< 0x00800000 */
-#define FLASH_OPTR_nBOOT1                   FLASH_OPTR_nBOOT1_Msk              /*!< Boot Configuration                                  */
-#define FLASH_OPTR_SRAM2_PE_Pos             (24U)
-#define FLASH_OPTR_SRAM2_PE_Msk             (0x1UL << FLASH_OPTR_SRAM2_PE_Pos) /*!< 0x01000000 */
-#define FLASH_OPTR_SRAM2_PE                 FLASH_OPTR_SRAM2_PE_Msk            /*!< SRAM2 parity check enable                           */
-#define FLASH_OPTR_SRAM_RST_Pos             (25U)
-#define FLASH_OPTR_SRAM_RST_Msk             (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x02000000 */
-#define FLASH_OPTR_SRAM_RST                 FLASH_OPTR_SRAM_RST_Msk            /*!< SRAM1 and SRAM2 erase option when system reset      */
-#define FLASH_OPTR_nSWBOOT0_Pos             (26U)
-#define FLASH_OPTR_nSWBOOT0_Msk             (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
-#define FLASH_OPTR_nSWBOOT0                 FLASH_OPTR_nSWBOOT0_Msk            /*!< Software BOOT0                                      */
-#define FLASH_OPTR_nBOOT0_Pos               (27U)
-#define FLASH_OPTR_nBOOT0_Msk               (0x1UL << FLASH_OPTR_nBOOT0_Pos)   /*!< 0x08000000 */
-#define FLASH_OPTR_nBOOT0                   FLASH_OPTR_nBOOT0_Msk              /*!< BOOT0 option bit                                    */
-#define FLASH_OPTR_BOOT_LOCK_Pos            (30U)
-#define FLASH_OPTR_BOOT_LOCK_Msk            (0x1UL << FLASH_OPTR_BOOT_LOCK_Pos)/*!< 0x40000000 */
-#define FLASH_OPTR_BOOT_LOCK                FLASH_OPTR_BOOT_LOCK_Msk           /*!< CPU1 Boot Lock enable option bit                    */
-
-/******************  Bits definition for FLASH_PCROP1ASR register  ************/
-#define FLASH_PCROP1ASR_PCROP1A_STRT_Pos    (0U)
-#define FLASH_PCROP1ASR_PCROP1A_STRT_Msk    (0xFFUL << FLASH_PCROP1ASR_PCROP1A_STRT_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1ASR_PCROP1A_STRT        FLASH_PCROP1ASR_PCROP1A_STRT_Msk   /*!< PCROP area A start offset                           */
-
-/******************  Bits definition for FLASH_PCROP1AER register  ************/
-#define FLASH_PCROP1AER_PCROP1A_END_Pos     (0U)
-#define FLASH_PCROP1AER_PCROP1A_END_Msk     (0xFFUL << FLASH_PCROP1AER_PCROP1A_END_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1AER_PCROP1A_END         FLASH_PCROP1AER_PCROP1A_END_Msk    /*!< PCROP area A end offset                             */
-#define FLASH_PCROP1AER_PCROP_RDP_Pos       (31U)
-#define FLASH_PCROP1AER_PCROP_RDP_Msk       (0x1UL << FLASH_PCROP1AER_PCROP_RDP_Pos)/*!< 0x80000000 */
-#define FLASH_PCROP1AER_PCROP_RDP           FLASH_PCROP1AER_PCROP_RDP_Msk      /*!< PCROP area preserved when RDP level decreased       */
-
-/******************  Bits definition for FLASH_WRP1AR register  ***************/
-#define FLASH_WRP1AR_WRP1A_STRT_Pos         (0U)
-#define FLASH_WRP1AR_WRP1A_STRT_Msk         (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
-#define FLASH_WRP1AR_WRP1A_STRT             FLASH_WRP1AR_WRP1A_STRT_Msk        /*!< WRP area A start offset                             */
-#define FLASH_WRP1AR_WRP1A_END_Pos          (16U)
-#define FLASH_WRP1AR_WRP1A_END_Msk          (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
-#define FLASH_WRP1AR_WRP1A_END              FLASH_WRP1AR_WRP1A_END_Msk         /*!< WRP area A end offset                               */
-
-/******************  Bits definition for FLASH_WRP1BR register  ***************/
-#define FLASH_WRP1BR_WRP1B_STRT_Pos         (0U)
-#define FLASH_WRP1BR_WRP1B_STRT_Msk         (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
-#define FLASH_WRP1BR_WRP1B_STRT             FLASH_WRP1BR_WRP1B_STRT_Msk        /*!< WRP area B start offset                             */
-#define FLASH_WRP1BR_WRP1B_END_Pos          (16U)
-#define FLASH_WRP1BR_WRP1B_END_Msk          (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
-#define FLASH_WRP1BR_WRP1B_END              FLASH_WRP1BR_WRP1B_END_Msk         /*!< WRP area B end offset                               */
-
-/******************  Bits definition for FLASH_PCROP1BSR register  ************/
-#define FLASH_PCROP1BSR_PCROP1B_STRT_Pos    (0U)
-#define FLASH_PCROP1BSR_PCROP1B_STRT_Msk    (0xFFUL << FLASH_PCROP1BSR_PCROP1B_STRT_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1BSR_PCROP1B_STRT        FLASH_PCROP1BSR_PCROP1B_STRT_Msk   /*!< PCROP area B start offset                           */
-
-/******************  Bits definition for FLASH_PCROP1BER register  ************/
-#define FLASH_PCROP1BER_PCROP1B_END_Pos     (0U)
-#define FLASH_PCROP1BER_PCROP1B_END_Msk     (0xFFUL << FLASH_PCROP1BER_PCROP1B_END_Pos)/*!< 0x000000FF */
-#define FLASH_PCROP1BER_PCROP1B_END         FLASH_PCROP1BER_PCROP1B_END_Msk    /*!< PCROP area B end offset                             */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0_Pos           (0U)
-#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */
-#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk
-#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000001 */
-#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000002 */
-#define GPIO_MODER_MODE1_Pos           (2U)
-#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */
-#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk
-#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000004 */
-#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)         /*!< 0x00000008 */
-#define GPIO_MODER_MODE2_Pos           (4U)
-#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */
-#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk
-#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000010 */
-#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000020 */
-#define GPIO_MODER_MODE3_Pos           (6U)
-#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */
-#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk
-#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000040 */
-#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)         /*!< 0x00000080 */
-#define GPIO_MODER_MODE4_Pos           (8U)
-#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */
-#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk
-#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000100 */
-#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000200 */
-#define GPIO_MODER_MODE5_Pos           (10U)
-#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */
-#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk
-#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000400 */
-#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000800 */
-#define GPIO_MODER_MODE6_Pos           (12U)
-#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */
-#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk
-#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00001000 */
-#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00002000 */
-#define GPIO_MODER_MODE7_Pos           (14U)
-#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */
-#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk
-#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00004000 */
-#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)         /*!< 0x00008000 */
-#define GPIO_MODER_MODE8_Pos           (16U)
-#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */
-#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk
-#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00010000 */
-#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00020000 */
-#define GPIO_MODER_MODE9_Pos           (18U)
-#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */
-#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk
-#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00040000 */
-#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)         /*!< 0x00080000 */
-#define GPIO_MODER_MODE10_Pos          (20U)
-#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */
-#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk
-#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00100000 */
-#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00200000 */
-#define GPIO_MODER_MODE11_Pos          (22U)
-#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */
-#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk
-#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00400000 */
-#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00800000 */
-#define GPIO_MODER_MODE12_Pos          (24U)
-#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */
-#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk
-#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)        /*!< 0x01000000 */
-#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)        /*!< 0x02000000 */
-#define GPIO_MODER_MODE13_Pos          (26U)
-#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */
-#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk
-#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)        /*!< 0x04000000 */
-#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)        /*!< 0x08000000 */
-#define GPIO_MODER_MODE14_Pos          (28U)
-#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */
-#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk
-#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)        /*!< 0x10000000 */
-#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)        /*!< 0x20000000 */
-#define GPIO_MODER_MODE15_Pos          (30U)
-#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */
-#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk
-#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)        /*!< 0x40000000 */
-#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)        /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT0_Pos            (0U)
-#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */
-#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk
-#define GPIO_OTYPER_OT1_Pos            (1U)
-#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */
-#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk
-#define GPIO_OTYPER_OT2_Pos            (2U)
-#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */
-#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk
-#define GPIO_OTYPER_OT3_Pos            (3U)
-#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */
-#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk
-#define GPIO_OTYPER_OT4_Pos            (4U)
-#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */
-#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk
-#define GPIO_OTYPER_OT5_Pos            (5U)
-#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */
-#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk
-#define GPIO_OTYPER_OT6_Pos            (6U)
-#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */
-#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk
-#define GPIO_OTYPER_OT7_Pos            (7U)
-#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */
-#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk
-#define GPIO_OTYPER_OT8_Pos            (8U)
-#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */
-#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk
-#define GPIO_OTYPER_OT9_Pos            (9U)
-#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */
-#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk
-#define GPIO_OTYPER_OT10_Pos           (10U)
-#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */
-#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk
-#define GPIO_OTYPER_OT11_Pos           (11U)
-#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */
-#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk
-#define GPIO_OTYPER_OT12_Pos           (12U)
-#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */
-#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk
-#define GPIO_OTYPER_OT13_Pos           (13U)
-#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */
-#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk
-#define GPIO_OTYPER_OT14_Pos           (14U)
-#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */
-#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk
-#define GPIO_OTYPER_OT15_Pos           (15U)
-#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */
-#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)
-#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */
-#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk
-#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000001 */
-#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000002 */
-#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)
-#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */
-#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk
-#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000004 */
-#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x00000008 */
-#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)
-#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */
-#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk
-#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000010 */
-#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000020 */
-#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)
-#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */
-#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk
-#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000040 */
-#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x00000080 */
-#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)
-#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */
-#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk
-#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000100 */
-#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000200 */
-#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)
-#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */
-#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk
-#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000400 */
-#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000800 */
-#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)
-#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */
-#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk
-#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00001000 */
-#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00002000 */
-#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)
-#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */
-#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk
-#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00004000 */
-#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x00008000 */
-#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)
-#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */
-#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk
-#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00010000 */
-#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00020000 */
-#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)
-#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */
-#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk
-#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00040000 */
-#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x00080000 */
-#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)
-#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */
-#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk
-#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00100000 */
-#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00200000 */
-#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)
-#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */
-#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk
-#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00400000 */
-#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00800000 */
-#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)
-#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */
-#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk
-#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x01000000 */
-#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x02000000 */
-#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)
-#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */
-#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk
-#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x04000000 */
-#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x08000000 */
-#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)
-#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */
-#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk
-#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x10000000 */
-#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x20000000 */
-#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)
-#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */
-#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk
-#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x40000000 */
-#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPD0_Pos           (0U)
-#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk
-#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos           (2U)
-#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk
-#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos           (4U)
-#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk
-#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos           (6U)
-#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk
-#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos           (8U)
-#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk
-#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos           (10U)
-#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk
-#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos           (12U)
-#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk
-#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos           (14U)
-#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk
-#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos           (16U)
-#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk
-#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos           (18U)
-#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk
-#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos          (20U)
-#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk
-#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos          (22U)
-#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk
-#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos          (24U)
-#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk
-#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos          (26U)
-#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk
-#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos          (28U)
-#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk
-#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos          (30U)
-#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk
-#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos               (0U)
-#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */
-#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk
-#define GPIO_IDR_ID1_Pos               (1U)
-#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */
-#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk
-#define GPIO_IDR_ID2_Pos               (2U)
-#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */
-#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk
-#define GPIO_IDR_ID3_Pos               (3U)
-#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */
-#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk
-#define GPIO_IDR_ID4_Pos               (4U)
-#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */
-#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk
-#define GPIO_IDR_ID5_Pos               (5U)
-#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */
-#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk
-#define GPIO_IDR_ID6_Pos               (6U)
-#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */
-#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk
-#define GPIO_IDR_ID7_Pos               (7U)
-#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */
-#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk
-#define GPIO_IDR_ID8_Pos               (8U)
-#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */
-#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk
-#define GPIO_IDR_ID9_Pos               (9U)
-#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */
-#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk
-#define GPIO_IDR_ID10_Pos              (10U)
-#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */
-#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk
-#define GPIO_IDR_ID11_Pos              (11U)
-#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */
-#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk
-#define GPIO_IDR_ID12_Pos              (12U)
-#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */
-#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk
-#define GPIO_IDR_ID13_Pos              (13U)
-#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */
-#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk
-#define GPIO_IDR_ID14_Pos              (14U)
-#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */
-#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk
-#define GPIO_IDR_ID15_Pos              (15U)
-#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */
-#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_OD0_Pos               (0U)
-#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */
-#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk
-#define GPIO_ODR_OD1_Pos               (1U)
-#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */
-#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk
-#define GPIO_ODR_OD2_Pos               (2U)
-#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */
-#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk
-#define GPIO_ODR_OD3_Pos               (3U)
-#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */
-#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk
-#define GPIO_ODR_OD4_Pos               (4U)
-#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */
-#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk
-#define GPIO_ODR_OD5_Pos               (5U)
-#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */
-#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk
-#define GPIO_ODR_OD6_Pos               (6U)
-#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */
-#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk
-#define GPIO_ODR_OD7_Pos               (7U)
-#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */
-#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk
-#define GPIO_ODR_OD8_Pos               (8U)
-#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */
-#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk
-#define GPIO_ODR_OD9_Pos               (9U)
-#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */
-#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk
-#define GPIO_ODR_OD10_Pos              (10U)
-#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */
-#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk
-#define GPIO_ODR_OD11_Pos              (11U)
-#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */
-#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk
-#define GPIO_ODR_OD12_Pos              (12U)
-#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */
-#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk
-#define GPIO_ODR_OD13_Pos              (13U)
-#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */
-#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk
-#define GPIO_ODR_OD14_Pos              (14U)
-#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */
-#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk
-#define GPIO_ODR_OD15_Pos              (15U)
-#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */
-#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS0_Pos              (0U)
-#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */
-#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk
-#define GPIO_BSRR_BS1_Pos              (1U)
-#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */
-#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk
-#define GPIO_BSRR_BS2_Pos              (2U)
-#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */
-#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk
-#define GPIO_BSRR_BS3_Pos              (3U)
-#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */
-#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk
-#define GPIO_BSRR_BS4_Pos              (4U)
-#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */
-#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk
-#define GPIO_BSRR_BS5_Pos              (5U)
-#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */
-#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk
-#define GPIO_BSRR_BS6_Pos              (6U)
-#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */
-#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk
-#define GPIO_BSRR_BS7_Pos              (7U)
-#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */
-#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk
-#define GPIO_BSRR_BS8_Pos              (8U)
-#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */
-#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk
-#define GPIO_BSRR_BS9_Pos              (9U)
-#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */
-#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk
-#define GPIO_BSRR_BS10_Pos             (10U)
-#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */
-#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk
-#define GPIO_BSRR_BS11_Pos             (11U)
-#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */
-#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk
-#define GPIO_BSRR_BS12_Pos             (12U)
-#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */
-#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk
-#define GPIO_BSRR_BS13_Pos             (13U)
-#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */
-#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk
-#define GPIO_BSRR_BS14_Pos             (14U)
-#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */
-#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk
-#define GPIO_BSRR_BS15_Pos             (15U)
-#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */
-#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk
-#define GPIO_BSRR_BR0_Pos              (16U)
-#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */
-#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk
-#define GPIO_BSRR_BR1_Pos              (17U)
-#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */
-#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk
-#define GPIO_BSRR_BR2_Pos              (18U)
-#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */
-#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk
-#define GPIO_BSRR_BR3_Pos              (19U)
-#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */
-#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk
-#define GPIO_BSRR_BR4_Pos              (20U)
-#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */
-#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk
-#define GPIO_BSRR_BR5_Pos              (21U)
-#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */
-#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk
-#define GPIO_BSRR_BR6_Pos              (22U)
-#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */
-#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk
-#define GPIO_BSRR_BR7_Pos              (23U)
-#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */
-#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk
-#define GPIO_BSRR_BR8_Pos              (24U)
-#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */
-#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk
-#define GPIO_BSRR_BR9_Pos              (25U)
-#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */
-#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk
-#define GPIO_BSRR_BR10_Pos             (26U)
-#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */
-#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk
-#define GPIO_BSRR_BR11_Pos             (27U)
-#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */
-#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk
-#define GPIO_BSRR_BR12_Pos             (28U)
-#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */
-#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk
-#define GPIO_BSRR_BR13_Pos             (29U)
-#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */
-#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk
-#define GPIO_BSRR_BR14_Pos             (30U)
-#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */
-#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk
-#define GPIO_BSRR_BR15_Pos             (31U)
-#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */
-#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk
-
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0_Pos             (0U)
-#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk
-#define GPIO_LCKR_LCK1_Pos             (1U)
-#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk
-#define GPIO_LCKR_LCK2_Pos             (2U)
-#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk
-#define GPIO_LCKR_LCK3_Pos             (3U)
-#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk
-#define GPIO_LCKR_LCK4_Pos             (4U)
-#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk
-#define GPIO_LCKR_LCK5_Pos             (5U)
-#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk
-#define GPIO_LCKR_LCK6_Pos             (6U)
-#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk
-#define GPIO_LCKR_LCK7_Pos             (7U)
-#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk
-#define GPIO_LCKR_LCK8_Pos             (8U)
-#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk
-#define GPIO_LCKR_LCK9_Pos             (9U)
-#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk
-#define GPIO_LCKR_LCK10_Pos            (10U)
-#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk
-#define GPIO_LCKR_LCK11_Pos            (11U)
-#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk
-#define GPIO_LCKR_LCK12_Pos            (12U)
-#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk
-#define GPIO_LCKR_LCK13_Pos            (13U)
-#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk
-#define GPIO_LCKR_LCK14_Pos            (14U)
-#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk
-#define GPIO_LCKR_LCK15_Pos            (15U)
-#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk
-#define GPIO_LCKR_LCKK_Pos             (16U)
-#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk
-
-/****************** Bit definition for GPIO_AFRL register *********************/
-#define GPIO_AFRL_AFSEL0_Pos           (0U)
-#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk
-#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000001 */
-#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000002 */
-#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000004 */
-#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x00000008 */
-#define GPIO_AFRL_AFSEL1_Pos           (4U)
-#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk
-#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000010 */
-#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000020 */
-#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000040 */
-#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x00000080 */
-#define GPIO_AFRL_AFSEL2_Pos           (8U)
-#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk
-#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000100 */
-#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000200 */
-#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000400 */
-#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000800 */
-#define GPIO_AFRL_AFSEL3_Pos           (12U)
-#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk
-#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00001000 */
-#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00002000 */
-#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00004000 */
-#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x00008000 */
-#define GPIO_AFRL_AFSEL4_Pos           (16U)
-#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk
-#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00010000 */
-#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00020000 */
-#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00040000 */
-#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x00080000 */
-#define GPIO_AFRL_AFSEL5_Pos           (20U)
-#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk
-#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00100000 */
-#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00200000 */
-#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00400000 */
-#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00800000 */
-#define GPIO_AFRL_AFSEL6_Pos           (24U)
-#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk
-#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x01000000 */
-#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x02000000 */
-#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x04000000 */
-#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x08000000 */
-#define GPIO_AFRL_AFSEL7_Pos           (28U)
-#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk
-#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x10000000 */
-#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x20000000 */
-#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x40000000 */
-#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0x80000000 */
-
-/****************** Bit definition for GPIO_AFRH register *********************/
-#define GPIO_AFRH_AFSEL8_Pos           (0U)
-#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk
-#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000001 */
-#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000002 */
-#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000004 */
-#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x00000008 */
-#define GPIO_AFRH_AFSEL9_Pos           (4U)
-#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk
-#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000010 */
-#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000020 */
-#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000040 */
-#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x00000080 */
-#define GPIO_AFRH_AFSEL10_Pos          (8U)
-#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk
-#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000100 */
-#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000200 */
-#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000400 */
-#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000800 */
-#define GPIO_AFRH_AFSEL11_Pos          (12U)
-#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk
-#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00001000 */
-#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00002000 */
-#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00004000 */
-#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x00008000 */
-#define GPIO_AFRH_AFSEL12_Pos          (16U)
-#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk
-#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00010000 */
-#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00020000 */
-#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00040000 */
-#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x00080000 */
-#define GPIO_AFRH_AFSEL13_Pos          (20U)
-#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk
-#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00100000 */
-#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00200000 */
-#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00400000 */
-#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00800000 */
-#define GPIO_AFRH_AFSEL14_Pos          (24U)
-#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk
-#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x01000000 */
-#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x02000000 */
-#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x04000000 */
-#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x08000000 */
-#define GPIO_AFRH_AFSEL15_Pos          (28U)
-#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk
-#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x10000000 */
-#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x20000000 */
-#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x40000000 */
-#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0x80000000 */
-
-/******************  Bits definition for GPIO_BRR register  ******************/
-#define GPIO_BRR_BR0_Pos               (0U)
-#define GPIO_BRR_BR0_Msk               (0x1UL << GPIO_BRR_BR0_Pos)             /*!< 0x00000001 */
-#define GPIO_BRR_BR0                   GPIO_BRR_BR0_Msk
-#define GPIO_BRR_BR1_Pos               (1U)
-#define GPIO_BRR_BR1_Msk               (0x1UL << GPIO_BRR_BR1_Pos)             /*!< 0x00000002 */
-#define GPIO_BRR_BR1                   GPIO_BRR_BR1_Msk
-#define GPIO_BRR_BR2_Pos               (2U)
-#define GPIO_BRR_BR2_Msk               (0x1UL << GPIO_BRR_BR2_Pos)             /*!< 0x00000004 */
-#define GPIO_BRR_BR2                   GPIO_BRR_BR2_Msk
-#define GPIO_BRR_BR3_Pos               (3U)
-#define GPIO_BRR_BR3_Msk               (0x1UL << GPIO_BRR_BR3_Pos)             /*!< 0x00000008 */
-#define GPIO_BRR_BR3                   GPIO_BRR_BR3_Msk
-#define GPIO_BRR_BR4_Pos               (4U)
-#define GPIO_BRR_BR4_Msk               (0x1UL << GPIO_BRR_BR4_Pos)             /*!< 0x00000010 */
-#define GPIO_BRR_BR4                   GPIO_BRR_BR4_Msk
-#define GPIO_BRR_BR5_Pos               (5U)
-#define GPIO_BRR_BR5_Msk               (0x1UL << GPIO_BRR_BR5_Pos)             /*!< 0x00000020 */
-#define GPIO_BRR_BR5                   GPIO_BRR_BR5_Msk
-#define GPIO_BRR_BR6_Pos               (6U)
-#define GPIO_BRR_BR6_Msk               (0x1UL << GPIO_BRR_BR6_Pos)             /*!< 0x00000040 */
-#define GPIO_BRR_BR6                   GPIO_BRR_BR6_Msk
-#define GPIO_BRR_BR7_Pos               (7U)
-#define GPIO_BRR_BR7_Msk               (0x1UL << GPIO_BRR_BR7_Pos)             /*!< 0x00000080 */
-#define GPIO_BRR_BR7                   GPIO_BRR_BR7_Msk
-#define GPIO_BRR_BR8_Pos               (8U)
-#define GPIO_BRR_BR8_Msk               (0x1UL << GPIO_BRR_BR8_Pos)             /*!< 0x00000100 */
-#define GPIO_BRR_BR8                   GPIO_BRR_BR8_Msk
-#define GPIO_BRR_BR9_Pos               (9U)
-#define GPIO_BRR_BR9_Msk               (0x1UL << GPIO_BRR_BR9_Pos)             /*!< 0x00000200 */
-#define GPIO_BRR_BR9                   GPIO_BRR_BR9_Msk
-#define GPIO_BRR_BR10_Pos              (10U)
-#define GPIO_BRR_BR10_Msk              (0x1UL << GPIO_BRR_BR10_Pos)            /*!< 0x00000400 */
-#define GPIO_BRR_BR10                  GPIO_BRR_BR10_Msk
-#define GPIO_BRR_BR11_Pos              (11U)
-#define GPIO_BRR_BR11_Msk              (0x1UL << GPIO_BRR_BR11_Pos)            /*!< 0x00000800 */
-#define GPIO_BRR_BR11                  GPIO_BRR_BR11_Msk
-#define GPIO_BRR_BR12_Pos              (12U)
-#define GPIO_BRR_BR12_Msk              (0x1UL << GPIO_BRR_BR12_Pos)            /*!< 0x00001000 */
-#define GPIO_BRR_BR12                  GPIO_BRR_BR12_Msk
-#define GPIO_BRR_BR13_Pos              (13U)
-#define GPIO_BRR_BR13_Msk              (0x1UL << GPIO_BRR_BR13_Pos)            /*!< 0x00002000 */
-#define GPIO_BRR_BR13                  GPIO_BRR_BR13_Msk
-#define GPIO_BRR_BR14_Pos              (14U)
-#define GPIO_BRR_BR14_Msk              (0x1UL << GPIO_BRR_BR14_Pos)            /*!< 0x00004000 */
-#define GPIO_BRR_BR14                  GPIO_BRR_BR14_Msk
-#define GPIO_BRR_BR15_Pos              (15U)
-#define GPIO_BRR_BR15_Msk              (0x1UL << GPIO_BRR_BR15_Pos)            /*!< 0x00008000 */
-#define GPIO_BRR_BR15                  GPIO_BRR_BR15_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                        HSEM HW Semaphore                                   */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for HSEM_R register  ********************/
-#define HSEM_R_PROCID_Pos        (0U)
-#define HSEM_R_PROCID_Msk        (0xFFUL << HSEM_R_PROCID_Pos)                 /*!< 0x000000FF */
-#define HSEM_R_PROCID            HSEM_R_PROCID_Msk                             /*!<Semaphore ProcessID */
-#define HSEM_R_COREID_Pos        (8U)
-#define HSEM_R_COREID_Msk        (0xFUL << HSEM_R_COREID_Pos)                  /*!< 0x00000F00 */
-#define HSEM_R_COREID            HSEM_R_COREID_Msk                             /*!<Semaphore CoreID. */
-#define HSEM_R_LOCK_Pos          (31U)
-#define HSEM_R_LOCK_Msk          (0x1UL << HSEM_R_LOCK_Pos)                    /*!< 0x80000000 */
-#define HSEM_R_LOCK              HSEM_R_LOCK_Msk                               /*!<Lock indication. */
-
-/********************  Bit definition for HSEM_RLR register  ******************/
-#define HSEM_RLR_PROCID_Pos      (0U)
-#define HSEM_RLR_PROCID_Msk      (0xFFUL << HSEM_RLR_PROCID_Pos)               /*!< 0x000000FF */
-#define HSEM_RLR_PROCID          HSEM_RLR_PROCID_Msk                           /*!<Semaphore ProcessID */
-#define HSEM_RLR_COREID_Pos      (8U)
-#define HSEM_RLR_COREID_Msk      (0xFUL << HSEM_RLR_COREID_Pos)                /*!< 0x00000F00 */
-#define HSEM_RLR_COREID          HSEM_RLR_COREID_Msk                           /*!<Semaphore CoreID. */
-#define HSEM_RLR_LOCK_Pos        (31U)
-#define HSEM_RLR_LOCK_Msk        (0x1UL << HSEM_RLR_LOCK_Pos)                  /*!< 0x80000000 */
-#define HSEM_RLR_LOCK            HSEM_RLR_LOCK_Msk                             /*!<Lock indication. */
-
-/********************  Bit definition for HSEM_C1IER register  ****************/
-#define HSEM_C1IER_ISE0_Pos      (0U)
-#define HSEM_C1IER_ISE0_Msk      (0x1UL << HSEM_C1IER_ISE0_Pos)                /*!< 0x00000001 */
-#define HSEM_C1IER_ISE0          HSEM_C1IER_ISE0_Msk                           /*!<semaphore 0 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE1_Pos      (1U)
-#define HSEM_C1IER_ISE1_Msk      (0x1UL << HSEM_C1IER_ISE1_Pos)                /*!< 0x00000002 */
-#define HSEM_C1IER_ISE1          HSEM_C1IER_ISE1_Msk                           /*!<semaphore 1 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE2_Pos      (2U)
-#define HSEM_C1IER_ISE2_Msk      (0x1UL << HSEM_C1IER_ISE2_Pos)                /*!< 0x00000004 */
-#define HSEM_C1IER_ISE2          HSEM_C1IER_ISE2_Msk                           /*!<semaphore 2 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE3_Pos      (3U)
-#define HSEM_C1IER_ISE3_Msk      (0x1UL << HSEM_C1IER_ISE3_Pos)                /*!< 0x00000008 */
-#define HSEM_C1IER_ISE3          HSEM_C1IER_ISE3_Msk                           /*!<semaphore 3 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE4_Pos      (4U)
-#define HSEM_C1IER_ISE4_Msk      (0x1UL << HSEM_C1IER_ISE4_Pos)                /*!< 0x00000010 */
-#define HSEM_C1IER_ISE4          HSEM_C1IER_ISE4_Msk                           /*!<semaphore 4 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE5_Pos      (5U)
-#define HSEM_C1IER_ISE5_Msk      (0x1UL << HSEM_C1IER_ISE5_Pos)                /*!< 0x00000020 */
-#define HSEM_C1IER_ISE5          HSEM_C1IER_ISE5_Msk                           /*!<semaphore 5 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE6_Pos      (6U)
-#define HSEM_C1IER_ISE6_Msk      (0x1UL << HSEM_C1IER_ISE6_Pos)                /*!< 0x00000040 */
-#define HSEM_C1IER_ISE6          HSEM_C1IER_ISE6_Msk                           /*!<semaphore 6 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE7_Pos      (7U)
-#define HSEM_C1IER_ISE7_Msk      (0x1UL << HSEM_C1IER_ISE7_Pos)                /*!< 0x00000080 */
-#define HSEM_C1IER_ISE7          HSEM_C1IER_ISE7_Msk                           /*!<semaphore 7 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE8_Pos      (8U)
-#define HSEM_C1IER_ISE8_Msk      (0x1UL << HSEM_C1IER_ISE8_Pos)                /*!< 0x00000100 */
-#define HSEM_C1IER_ISE8          HSEM_C1IER_ISE8_Msk                           /*!<semaphore 8 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE9_Pos      (9U)
-#define HSEM_C1IER_ISE9_Msk      (0x1UL << HSEM_C1IER_ISE9_Pos)                /*!< 0x00000200 */
-#define HSEM_C1IER_ISE9          HSEM_C1IER_ISE9_Msk                           /*!<semaphore 9 CPU1 interrupt enable bit.  */
-#define HSEM_C1IER_ISE10_Pos     (10U)
-#define HSEM_C1IER_ISE10_Msk     (0x1UL << HSEM_C1IER_ISE10_Pos)               /*!< 0x00000400 */
-#define HSEM_C1IER_ISE10         HSEM_C1IER_ISE10_Msk                          /*!<semaphore 10 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE11_Pos     (11U)
-#define HSEM_C1IER_ISE11_Msk     (0x1UL << HSEM_C1IER_ISE11_Pos)               /*!< 0x00000800 */
-#define HSEM_C1IER_ISE11         HSEM_C1IER_ISE11_Msk                          /*!<semaphore 11 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE12_Pos     (12U)
-#define HSEM_C1IER_ISE12_Msk     (0x1UL << HSEM_C1IER_ISE12_Pos)               /*!< 0x00001000 */
-#define HSEM_C1IER_ISE12         HSEM_C1IER_ISE12_Msk                          /*!<semaphore 12 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE13_Pos     (13U)
-#define HSEM_C1IER_ISE13_Msk     (0x1UL << HSEM_C1IER_ISE13_Pos)               /*!< 0x00002000 */
-#define HSEM_C1IER_ISE13         HSEM_C1IER_ISE13_Msk                          /*!<semaphore 13 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE14_Pos     (14U)
-#define HSEM_C1IER_ISE14_Msk     (0x1UL << HSEM_C1IER_ISE14_Pos)               /*!< 0x00004000 */
-#define HSEM_C1IER_ISE14         HSEM_C1IER_ISE14_Msk                          /*!<semaphore 14 CPU1 interrupt enable bit. */
-#define HSEM_C1IER_ISE15_Pos     (15U)
-#define HSEM_C1IER_ISE15_Msk     (0x1UL << HSEM_C1IER_ISE15_Pos)               /*!< 0x00008000 */
-#define HSEM_C1IER_ISE15         HSEM_C1IER_ISE15_Msk                          /*!<semaphore 15 CPU1 interrupt enable bit. */
-
-/********************  Bit definition for HSEM_C1ICR register  *****************/
-#define HSEM_C1ICR_ISC0_Pos      (0U)
-#define HSEM_C1ICR_ISC0_Msk      (0x1UL << HSEM_C1ICR_ISC0_Pos)                /*!< 0x00000001 */
-#define HSEM_C1ICR_ISC0          HSEM_C1ICR_ISC0_Msk                           /*!<semaphore 0 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC1_Pos      (1U)
-#define HSEM_C1ICR_ISC1_Msk      (0x1UL << HSEM_C1ICR_ISC1_Pos)                /*!< 0x00000002 */
-#define HSEM_C1ICR_ISC1          HSEM_C1ICR_ISC1_Msk                           /*!<semaphore 1 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC2_Pos      (2U)
-#define HSEM_C1ICR_ISC2_Msk      (0x1UL << HSEM_C1ICR_ISC2_Pos)                /*!< 0x00000004 */
-#define HSEM_C1ICR_ISC2          HSEM_C1ICR_ISC2_Msk                           /*!<semaphore 2 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC3_Pos      (3U)
-#define HSEM_C1ICR_ISC3_Msk      (0x1UL << HSEM_C1ICR_ISC3_Pos)                /*!< 0x00000008 */
-#define HSEM_C1ICR_ISC3          HSEM_C1ICR_ISC3_Msk                           /*!<semaphore 3 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC4_Pos      (4U)
-#define HSEM_C1ICR_ISC4_Msk      (0x1UL << HSEM_C1ICR_ISC4_Pos)                /*!< 0x00000010 */
-#define HSEM_C1ICR_ISC4          HSEM_C1ICR_ISC4_Msk                           /*!<semaphore 4 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC5_Pos      (5U)
-#define HSEM_C1ICR_ISC5_Msk      (0x1UL << HSEM_C1ICR_ISC5_Pos)                /*!< 0x00000020 */
-#define HSEM_C1ICR_ISC5          HSEM_C1ICR_ISC5_Msk                           /*!<semaphore 5 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC6_Pos      (6U)
-#define HSEM_C1ICR_ISC6_Msk      (0x1UL << HSEM_C1ICR_ISC6_Pos)                /*!< 0x00000040 */
-#define HSEM_C1ICR_ISC6          HSEM_C1ICR_ISC6_Msk                           /*!<semaphore 6 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC7_Pos      (7U)
-#define HSEM_C1ICR_ISC7_Msk      (0x1UL << HSEM_C1ICR_ISC7_Pos)                /*!< 0x00000080 */
-#define HSEM_C1ICR_ISC7          HSEM_C1ICR_ISC7_Msk                           /*!<semaphore 7 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC8_Pos      (8U)
-#define HSEM_C1ICR_ISC8_Msk      (0x1UL << HSEM_C1ICR_ISC8_Pos)                /*!< 0x00000100 */
-#define HSEM_C1ICR_ISC8          HSEM_C1ICR_ISC8_Msk                           /*!<semaphore 8 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC9_Pos      (9U)
-#define HSEM_C1ICR_ISC9_Msk      (0x1UL << HSEM_C1ICR_ISC9_Pos)                /*!< 0x00000200 */
-#define HSEM_C1ICR_ISC9          HSEM_C1ICR_ISC9_Msk                           /*!<semaphore 9 CPU1 interrupt clear bit.  */
-#define HSEM_C1ICR_ISC10_Pos     (10U)
-#define HSEM_C1ICR_ISC10_Msk     (0x1UL << HSEM_C1ICR_ISC10_Pos)               /*!< 0x00000400 */
-#define HSEM_C1ICR_ISC10         HSEM_C1ICR_ISC10_Msk                          /*!<semaphore 10 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC11_Pos     (11U)
-#define HSEM_C1ICR_ISC11_Msk     (0x1UL << HSEM_C1ICR_ISC11_Pos)               /*!< 0x00000800 */
-#define HSEM_C1ICR_ISC11         HSEM_C1ICR_ISC11_Msk                          /*!<semaphore 11 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC12_Pos     (12U)
-#define HSEM_C1ICR_ISC12_Msk     (0x1UL << HSEM_C1ICR_ISC12_Pos)               /*!< 0x00001000 */
-#define HSEM_C1ICR_ISC12         HSEM_C1ICR_ISC12_Msk                          /*!<semaphore 12 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC13_Pos     (13U)
-#define HSEM_C1ICR_ISC13_Msk     (0x1UL << HSEM_C1ICR_ISC13_Pos)               /*!< 0x00002000 */
-#define HSEM_C1ICR_ISC13         HSEM_C1ICR_ISC13_Msk                          /*!<semaphore 13 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC14_Pos     (14U)
-#define HSEM_C1ICR_ISC14_Msk     (0x1UL << HSEM_C1ICR_ISC14_Pos)               /*!< 0x00004000 */
-#define HSEM_C1ICR_ISC14         HSEM_C1ICR_ISC14_Msk                          /*!<semaphore 14 CPU1 interrupt clear bit. */
-#define HSEM_C1ICR_ISC15_Pos     (15U)
-#define HSEM_C1ICR_ISC15_Msk     (0x1UL << HSEM_C1ICR_ISC15_Pos)               /*!< 0x00008000 */
-#define HSEM_C1ICR_ISC15         HSEM_C1ICR_ISC15_Msk                          /*!<semaphore 15 CPU1 interrupt clear bit. */
-
-/********************  Bit definition for HSEM_C1ISR register  *****************/
-#define HSEM_C1ISR_ISF0_Pos      (0U)
-#define HSEM_C1ISR_ISF0_Msk      (0x1UL << HSEM_C1ISR_ISF0_Pos)                /*!< 0x00000001 */
-#define HSEM_C1ISR_ISF0          HSEM_C1ISR_ISF0_Msk                           /*!<semaphore 0 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF1_Pos      (1U)
-#define HSEM_C1ISR_ISF1_Msk      (0x1UL << HSEM_C1ISR_ISF1_Pos)                /*!< 0x00000002 */
-#define HSEM_C1ISR_ISF1          HSEM_C1ISR_ISF1_Msk                           /*!<semaphore 1 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF2_Pos      (2U)
-#define HSEM_C1ISR_ISF2_Msk      (0x1UL << HSEM_C1ISR_ISF2_Pos)                /*!< 0x00000004 */
-#define HSEM_C1ISR_ISF2          HSEM_C1ISR_ISF2_Msk                           /*!<semaphore 2 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF3_Pos      (3U)
-#define HSEM_C1ISR_ISF3_Msk      (0x1UL << HSEM_C1ISR_ISF3_Pos)                /*!< 0x00000008 */
-#define HSEM_C1ISR_ISF3          HSEM_C1ISR_ISF3_Msk                           /*!<semaphore 3 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF4_Pos      (4U)
-#define HSEM_C1ISR_ISF4_Msk      (0x1UL << HSEM_C1ISR_ISF4_Pos)                /*!< 0x00000010 */
-#define HSEM_C1ISR_ISF4          HSEM_C1ISR_ISF4_Msk                           /*!<semaphore 4 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF5_Pos      (5U)
-#define HSEM_C1ISR_ISF5_Msk      (0x1UL << HSEM_C1ISR_ISF5_Pos)                /*!< 0x00000020 */
-#define HSEM_C1ISR_ISF5          HSEM_C1ISR_ISF5_Msk                           /*!<semaphore 5 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF6_Pos      (6U)
-#define HSEM_C1ISR_ISF6_Msk      (0x1UL << HSEM_C1ISR_ISF6_Pos)                /*!< 0x00000040 */
-#define HSEM_C1ISR_ISF6          HSEM_C1ISR_ISF6_Msk                           /*!<semaphore 6 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF7_Pos      (7U)
-#define HSEM_C1ISR_ISF7_Msk      (0x1UL << HSEM_C1ISR_ISF7_Pos)                /*!< 0x00000080 */
-#define HSEM_C1ISR_ISF7          HSEM_C1ISR_ISF7_Msk                           /*!<semaphore 7 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF8_Pos      (8U)
-#define HSEM_C1ISR_ISF8_Msk      (0x1UL << HSEM_C1ISR_ISF8_Pos)                /*!< 0x00000100 */
-#define HSEM_C1ISR_ISF8          HSEM_C1ISR_ISF8_Msk                           /*!<semaphore 8 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF9_Pos      (9U)
-#define HSEM_C1ISR_ISF9_Msk      (0x1UL << HSEM_C1ISR_ISF9_Pos)                /*!< 0x00000200 */
-#define HSEM_C1ISR_ISF9          HSEM_C1ISR_ISF9_Msk                           /*!<semaphore 9 CPU1 interrupt status bit.  */
-#define HSEM_C1ISR_ISF10_Pos     (10U)
-#define HSEM_C1ISR_ISF10_Msk     (0x1UL << HSEM_C1ISR_ISF10_Pos)               /*!< 0x00000400 */
-#define HSEM_C1ISR_ISF10         HSEM_C1ISR_ISF10_Msk                          /*!<semaphore 10 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF11_Pos     (11U)
-#define HSEM_C1ISR_ISF11_Msk     (0x1UL << HSEM_C1ISR_ISF11_Pos)               /*!< 0x00000800 */
-#define HSEM_C1ISR_ISF11         HSEM_C1ISR_ISF11_Msk                          /*!<semaphore 11 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF12_Pos     (12U)
-#define HSEM_C1ISR_ISF12_Msk     (0x1UL << HSEM_C1ISR_ISF12_Pos)               /*!< 0x00001000 */
-#define HSEM_C1ISR_ISF12         HSEM_C1ISR_ISF12_Msk                          /*!<semaphore 12 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF13_Pos     (13U)
-#define HSEM_C1ISR_ISF13_Msk     (0x1UL << HSEM_C1ISR_ISF13_Pos)               /*!< 0x00002000 */
-#define HSEM_C1ISR_ISF13         HSEM_C1ISR_ISF13_Msk                          /*!<semaphore 13 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF14_Pos     (14U)
-#define HSEM_C1ISR_ISF14_Msk     (0x1UL << HSEM_C1ISR_ISF14_Pos)               /*!< 0x00004000 */
-#define HSEM_C1ISR_ISF14         HSEM_C1ISR_ISF14_Msk                          /*!<semaphore 14 CPU1 interrupt status bit. */
-#define HSEM_C1ISR_ISF15_Pos     (15U)
-#define HSEM_C1ISR_ISF15_Msk     (0x1UL << HSEM_C1ISR_ISF15_Pos)               /*!< 0x00008000 */
-#define HSEM_C1ISR_ISF15         HSEM_C1ISR_ISF15_Msk                          /*!<semaphore 15 CPU1 interrupt status bit. */
-
-/********************  Bit definition for HSEM_C1MISR register  *****************/
-#define HSEM_C1MISR_MISF0_Pos     (0U)
-#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)               /*!< 0x00000001 */
-#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                          /*!<semaphore 0 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF1_Pos     (1U)
-#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)               /*!< 0x00000002 */
-#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                          /*!<semaphore 1 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF2_Pos     (2U)
-#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)               /*!< 0x00000004 */
-#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                          /*!<semaphore 2 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF3_Pos     (3U)
-#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)               /*!< 0x00000008 */
-#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                          /*!<semaphore 3 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF4_Pos     (4U)
-#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)               /*!< 0x00000010 */
-#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                          /*!<semaphore 4 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF5_Pos     (5U)
-#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)               /*!< 0x00000020 */
-#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                          /*!<semaphore 5 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF6_Pos     (6U)
-#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)               /*!< 0x00000040 */
-#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                          /*!<semaphore 6 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF7_Pos     (7U)
-#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)               /*!< 0x00000080 */
-#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                          /*!<semaphore 7 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF8_Pos     (8U)
-#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)               /*!< 0x00000100 */
-#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                          /*!<semaphore 8 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF9_Pos     (9U)
-#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)               /*!< 0x00000200 */
-#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                          /*!<semaphore 9 CPU1 interrupt masked status bit.  */
-#define HSEM_C1MISR_MISF10_Pos    (10U)
-#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)              /*!< 0x00000400 */
-#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                         /*!<semaphore 10 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF11_Pos    (11U)
-#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)              /*!< 0x00000800 */
-#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                         /*!<semaphore 11 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF12_Pos    (12U)
-#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)              /*!< 0x00001000 */
-#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                         /*!<semaphore 12 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF13_Pos    (13U)
-#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)              /*!< 0x00002000 */
-#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                         /*!<semaphore 13 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF14_Pos    (14U)
-#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)              /*!< 0x00004000 */
-#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                         /*!<semaphore 14 CPU1 interrupt masked status bit. */
-#define HSEM_C1MISR_MISF15_Pos    (15U)
-#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)              /*!< 0x00008000 */
-#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                         /*!<semaphore 15 CPU1 interrupt masked status bit. */
-
-/********************  Bit definition for HSEM_C2IER register  *****************/
-#define HSEM_C2IER_ISE0_Pos      (0U)
-#define HSEM_C2IER_ISE0_Msk      (0x1UL << HSEM_C2IER_ISE0_Pos)                /*!< 0x00000001 */
-#define HSEM_C2IER_ISE0          HSEM_C2IER_ISE0_Msk                           /*!<semaphore 0 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE1_Pos      (1U)
-#define HSEM_C2IER_ISE1_Msk      (0x1UL << HSEM_C2IER_ISE1_Pos)                /*!< 0x00000002 */
-#define HSEM_C2IER_ISE1          HSEM_C2IER_ISE1_Msk                           /*!<semaphore 1 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE2_Pos      (2U)
-#define HSEM_C2IER_ISE2_Msk      (0x1UL << HSEM_C2IER_ISE2_Pos)                /*!< 0x00000004 */
-#define HSEM_C2IER_ISE2          HSEM_C2IER_ISE2_Msk                           /*!<semaphore 2 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE3_Pos      (3U)
-#define HSEM_C2IER_ISE3_Msk      (0x1UL << HSEM_C2IER_ISE3_Pos)                /*!< 0x00000008 */
-#define HSEM_C2IER_ISE3          HSEM_C2IER_ISE3_Msk                           /*!<semaphore 3 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE4_Pos      (4U)
-#define HSEM_C2IER_ISE4_Msk      (0x1UL << HSEM_C2IER_ISE4_Pos)                /*!< 0x00000010 */
-#define HSEM_C2IER_ISE4          HSEM_C2IER_ISE4_Msk                           /*!<semaphore 4 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE5_Pos      (5U)
-#define HSEM_C2IER_ISE5_Msk      (0x1UL << HSEM_C2IER_ISE5_Pos)                /*!< 0x00000020 */
-#define HSEM_C2IER_ISE5          HSEM_C2IER_ISE5_Msk                           /*!<semaphore 5 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE6_Pos      (6U)
-#define HSEM_C2IER_ISE6_Msk      (0x1UL << HSEM_C2IER_ISE6_Pos)                /*!< 0x00000040 */
-#define HSEM_C2IER_ISE6          HSEM_C2IER_ISE6_Msk                           /*!<semaphore 6 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE7_Pos      (7U)
-#define HSEM_C2IER_ISE7_Msk      (0x1UL << HSEM_C2IER_ISE7_Pos)                /*!< 0x00000080 */
-#define HSEM_C2IER_ISE7          HSEM_C2IER_ISE7_Msk                           /*!<semaphore 7 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE8_Pos      (8U)
-#define HSEM_C2IER_ISE8_Msk      (0x1UL << HSEM_C2IER_ISE8_Pos)                /*!< 0x00000100 */
-#define HSEM_C2IER_ISE8          HSEM_C2IER_ISE8_Msk                           /*!<semaphore 8 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE9_Pos      (9U)
-#define HSEM_C2IER_ISE9_Msk      (0x1UL << HSEM_C2IER_ISE9_Pos)                /*!< 0x00000200 */
-#define HSEM_C2IER_ISE9          HSEM_C2IER_ISE9_Msk                           /*!<semaphore 9 CPU2 interrupt enable bit.  */
-#define HSEM_C2IER_ISE10_Pos     (10U)
-#define HSEM_C2IER_ISE10_Msk     (0x1UL << HSEM_C2IER_ISE10_Pos)               /*!< 0x00000400 */
-#define HSEM_C2IER_ISE10         HSEM_C2IER_ISE10_Msk                          /*!<semaphore 10 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE11_Pos     (11U)
-#define HSEM_C2IER_ISE11_Msk     (0x1UL << HSEM_C2IER_ISE11_Pos)               /*!< 0x00000800 */
-#define HSEM_C2IER_ISE11         HSEM_C2IER_ISE11_Msk                          /*!<semaphore 11 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE12_Pos     (12U)
-#define HSEM_C2IER_ISE12_Msk     (0x1UL << HSEM_C2IER_ISE12_Pos)               /*!< 0x00001000 */
-#define HSEM_C2IER_ISE12         HSEM_C2IER_ISE12_Msk                          /*!<semaphore 12 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE13_Pos     (13U)
-#define HSEM_C2IER_ISE13_Msk     (0x1UL << HSEM_C2IER_ISE13_Pos)               /*!< 0x00002000 */
-#define HSEM_C2IER_ISE13         HSEM_C2IER_ISE13_Msk                          /*!<semaphore 13 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE14_Pos     (14U)
-#define HSEM_C2IER_ISE14_Msk     (0x1UL << HSEM_C2IER_ISE14_Pos)               /*!< 0x00004000 */
-#define HSEM_C2IER_ISE14         HSEM_C2IER_ISE14_Msk                          /*!<semaphore 14 CPU2 interrupt enable bit. */
-#define HSEM_C2IER_ISE15_Pos     (15U)
-#define HSEM_C2IER_ISE15_Msk     (0x1UL << HSEM_C2IER_ISE15_Pos)               /*!< 0x00008000 */
-#define HSEM_C2IER_ISE15         HSEM_C2IER_ISE15_Msk                          /*!<semaphore 15 CPU2 interrupt enable bit. */
-
-/********************  Bit definition for HSEM_C2ICR register  *****************/
-#define HSEM_C2ICR_ISC0_Pos      (0U)
-#define HSEM_C2ICR_ISC0_Msk      (0x1UL << HSEM_C2ICR_ISC0_Pos)                /*!< 0x00000001 */
-#define HSEM_C2ICR_ISC0          HSEM_C2ICR_ISC0_Msk                           /*!<semaphore 0 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC1_Pos      (1U)
-#define HSEM_C2ICR_ISC1_Msk      (0x1UL << HSEM_C2ICR_ISC1_Pos)                /*!< 0x00000002 */
-#define HSEM_C2ICR_ISC1          HSEM_C2ICR_ISC1_Msk                           /*!<semaphore 1 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC2_Pos      (2U)
-#define HSEM_C2ICR_ISC2_Msk      (0x1UL << HSEM_C2ICR_ISC2_Pos)                /*!< 0x00000004 */
-#define HSEM_C2ICR_ISC2          HSEM_C2ICR_ISC2_Msk                           /*!<semaphore 2 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC3_Pos      (3U)
-#define HSEM_C2ICR_ISC3_Msk      (0x1UL << HSEM_C2ICR_ISC3_Pos)                /*!< 0x00000008 */
-#define HSEM_C2ICR_ISC3          HSEM_C2ICR_ISC3_Msk                           /*!<semaphore 3 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC4_Pos      (4U)
-#define HSEM_C2ICR_ISC4_Msk      (0x1UL << HSEM_C2ICR_ISC4_Pos)                /*!< 0x00000010 */
-#define HSEM_C2ICR_ISC4          HSEM_C2ICR_ISC4_Msk                           /*!<semaphore 4 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC5_Pos      (5U)
-#define HSEM_C2ICR_ISC5_Msk      (0x1UL << HSEM_C2ICR_ISC5_Pos)                /*!< 0x00000020 */
-#define HSEM_C2ICR_ISC5          HSEM_C2ICR_ISC5_Msk                           /*!<semaphore 5 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC6_Pos      (6U)
-#define HSEM_C2ICR_ISC6_Msk      (0x1UL << HSEM_C2ICR_ISC6_Pos)                /*!< 0x00000040 */
-#define HSEM_C2ICR_ISC6          HSEM_C2ICR_ISC6_Msk                           /*!<semaphore 6 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC7_Pos      (7U)
-#define HSEM_C2ICR_ISC7_Msk      (0x1UL << HSEM_C2ICR_ISC7_Pos)                /*!< 0x00000080 */
-#define HSEM_C2ICR_ISC7          HSEM_C2ICR_ISC7_Msk                           /*!<semaphore 7 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC8_Pos      (8U)
-#define HSEM_C2ICR_ISC8_Msk      (0x1UL << HSEM_C2ICR_ISC8_Pos)                /*!< 0x00000100 */
-#define HSEM_C2ICR_ISC8          HSEM_C2ICR_ISC8_Msk                           /*!<semaphore 8 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC9_Pos      (9U)
-#define HSEM_C2ICR_ISC9_Msk      (0x1UL << HSEM_C2ICR_ISC9_Pos)                /*!< 0x00000200 */
-#define HSEM_C2ICR_ISC9          HSEM_C2ICR_ISC9_Msk                           /*!<semaphore 9 CPU2 interrupt clear bit.  */
-#define HSEM_C2ICR_ISC10_Pos     (10U)
-#define HSEM_C2ICR_ISC10_Msk     (0x1UL << HSEM_C2ICR_ISC10_Pos)               /*!< 0x00000400 */
-#define HSEM_C2ICR_ISC10         HSEM_C2ICR_ISC10_Msk                          /*!<semaphore 10 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC11_Pos     (11U)
-#define HSEM_C2ICR_ISC11_Msk     (0x1UL << HSEM_C2ICR_ISC11_Pos)               /*!< 0x00000800 */
-#define HSEM_C2ICR_ISC11         HSEM_C2ICR_ISC11_Msk                          /*!<semaphore 11 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC12_Pos     (12U)
-#define HSEM_C2ICR_ISC12_Msk     (0x1UL << HSEM_C2ICR_ISC12_Pos)               /*!< 0x00001000 */
-#define HSEM_C2ICR_ISC12         HSEM_C2ICR_ISC12_Msk                          /*!<semaphore 12 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC13_Pos     (13U)
-#define HSEM_C2ICR_ISC13_Msk     (0x1UL << HSEM_C2ICR_ISC13_Pos)               /*!< 0x00002000 */
-#define HSEM_C2ICR_ISC13         HSEM_C2ICR_ISC13_Msk                          /*!<semaphore 13 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC14_Pos     (14U)
-#define HSEM_C2ICR_ISC14_Msk     (0x1UL << HSEM_C2ICR_ISC14_Pos)               /*!< 0x00004000 */
-#define HSEM_C2ICR_ISC14         HSEM_C2ICR_ISC14_Msk                          /*!<semaphore 14 CPU2 interrupt clear bit. */
-#define HSEM_C2ICR_ISC15_Pos     (15U)
-#define HSEM_C2ICR_ISC15_Msk     (0x1UL << HSEM_C2ICR_ISC15_Pos)               /*!< 0x00008000 */
-#define HSEM_C2ICR_ISC15         HSEM_C2ICR_ISC15_Msk                          /*!<semaphore 15 CPU2 interrupt clear bit. */
-
-/********************  Bit definition for HSEM_C2ISR register  *****************/
-#define HSEM_C2ISR_ISF0_Pos      (0U)
-#define HSEM_C2ISR_ISF0_Msk      (0x1UL << HSEM_C2ISR_ISF0_Pos)                /*!< 0x00000001 */
-#define HSEM_C2ISR_ISF0          HSEM_C2ISR_ISF0_Msk                           /*!<semaphore 0 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF1_Pos      (1U)
-#define HSEM_C2ISR_ISF1_Msk      (0x1UL << HSEM_C2ISR_ISF1_Pos)                /*!< 0x00000002 */
-#define HSEM_C2ISR_ISF1          HSEM_C2ISR_ISF1_Msk                           /*!<semaphore 1 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF2_Pos      (2U)
-#define HSEM_C2ISR_ISF2_Msk      (0x1UL << HSEM_C2ISR_ISF2_Pos)                /*!< 0x00000004 */
-#define HSEM_C2ISR_ISF2          HSEM_C2ISR_ISF2_Msk                           /*!<semaphore 2 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF3_Pos      (3U)
-#define HSEM_C2ISR_ISF3_Msk      (0x1UL << HSEM_C2ISR_ISF3_Pos)                /*!< 0x00000008 */
-#define HSEM_C2ISR_ISF3          HSEM_C2ISR_ISF3_Msk                           /*!<semaphore 3 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF4_Pos      (4U)
-#define HSEM_C2ISR_ISF4_Msk      (0x1UL << HSEM_C2ISR_ISF4_Pos)                /*!< 0x00000010 */
-#define HSEM_C2ISR_ISF4          HSEM_C2ISR_ISF4_Msk                           /*!<semaphore 4 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF5_Pos      (5U)
-#define HSEM_C2ISR_ISF5_Msk      (0x1UL << HSEM_C2ISR_ISF5_Pos)                /*!< 0x00000020 */
-#define HSEM_C2ISR_ISF5          HSEM_C2ISR_ISF5_Msk                           /*!<semaphore 5 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF6_Pos      (6U)
-#define HSEM_C2ISR_ISF6_Msk      (0x1UL << HSEM_C2ISR_ISF6_Pos)                /*!< 0x00000040 */
-#define HSEM_C2ISR_ISF6          HSEM_C2ISR_ISF6_Msk                           /*!<semaphore 6 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF7_Pos      (7U)
-#define HSEM_C2ISR_ISF7_Msk      (0x1UL << HSEM_C2ISR_ISF7_Pos)                /*!< 0x00000080 */
-#define HSEM_C2ISR_ISF7          HSEM_C2ISR_ISF7_Msk                           /*!<semaphore 7 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF8_Pos      (8U)
-#define HSEM_C2ISR_ISF8_Msk      (0x1UL << HSEM_C2ISR_ISF8_Pos)                /*!< 0x00000100 */
-#define HSEM_C2ISR_ISF8          HSEM_C2ISR_ISF8_Msk                           /*!<semaphore 8 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF9_Pos      (9U)
-#define HSEM_C2ISR_ISF9_Msk      (0x1UL << HSEM_C2ISR_ISF9_Pos)                /*!< 0x00000200 */
-#define HSEM_C2ISR_ISF9          HSEM_C2ISR_ISF9_Msk                           /*!<semaphore 9 CPU2 interrupt status bit.  */
-#define HSEM_C2ISR_ISF10_Pos     (10U)
-#define HSEM_C2ISR_ISF10_Msk     (0x1UL << HSEM_C2ISR_ISF10_Pos)               /*!< 0x00000400 */
-#define HSEM_C2ISR_ISF10         HSEM_C2ISR_ISF10_Msk                          /*!<semaphore 10 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF11_Pos     (11U)
-#define HSEM_C2ISR_ISF11_Msk     (0x1UL << HSEM_C2ISR_ISF11_Pos)               /*!< 0x00000800 */
-#define HSEM_C2ISR_ISF11         HSEM_C2ISR_ISF11_Msk                          /*!<semaphore 11 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF12_Pos     (12U)
-#define HSEM_C2ISR_ISF12_Msk     (0x1UL << HSEM_C2ISR_ISF12_Pos)               /*!< 0x00001000 */
-#define HSEM_C2ISR_ISF12         HSEM_C2ISR_ISF12_Msk                          /*!<semaphore 12 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF13_Pos     (13U)
-#define HSEM_C2ISR_ISF13_Msk     (0x1UL << HSEM_C2ISR_ISF13_Pos)               /*!< 0x00002000 */
-#define HSEM_C2ISR_ISF13         HSEM_C2ISR_ISF13_Msk                          /*!<semaphore 13 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF14_Pos     (14U)
-#define HSEM_C2ISR_ISF14_Msk     (0x1UL << HSEM_C2ISR_ISF14_Pos)               /*!< 0x00004000 */
-#define HSEM_C2ISR_ISF14         HSEM_C2ISR_ISF14_Msk                          /*!<semaphore 14 CPU2 interrupt status bit. */
-#define HSEM_C2ISR_ISF15_Pos     (15U)
-#define HSEM_C2ISR_ISF15_Msk     (0x1UL << HSEM_C2ISR_ISF15_Pos)               /*!< 0x00008000 */
-#define HSEM_C2ISR_ISF15         HSEM_C2ISR_ISF15_Msk                          /*!<semaphore 15 CPU2 interrupt status bit. */
-
-/********************  Bit definition for HSEM_C2MISR register  *****************/
-#define HSEM_C2MISR_MISF0_Pos     (0U)
-#define HSEM_C2MISR_MISF0_Msk     (0x1UL << HSEM_C2MISR_MISF0_Pos)               /*!< 0x00000001 */
-#define HSEM_C2MISR_MISF0         HSEM_C2MISR_MISF0_Msk                          /*!<semaphore 0 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF1_Pos     (1U)
-#define HSEM_C2MISR_MISF1_Msk     (0x1UL << HSEM_C2MISR_MISF1_Pos)               /*!< 0x00000002 */
-#define HSEM_C2MISR_MISF1         HSEM_C2MISR_MISF1_Msk                          /*!<semaphore 1 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF2_Pos     (2U)
-#define HSEM_C2MISR_MISF2_Msk     (0x1UL << HSEM_C2MISR_MISF2_Pos)               /*!< 0x00000004 */
-#define HSEM_C2MISR_MISF2         HSEM_C2MISR_MISF2_Msk                          /*!<semaphore 2 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF3_Pos     (3U)
-#define HSEM_C2MISR_MISF3_Msk     (0x1UL << HSEM_C2MISR_MISF3_Pos)               /*!< 0x00000008 */
-#define HSEM_C2MISR_MISF3         HSEM_C2MISR_MISF3_Msk                          /*!<semaphore 3 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF4_Pos     (4U)
-#define HSEM_C2MISR_MISF4_Msk     (0x1UL << HSEM_C2MISR_MISF4_Pos)               /*!< 0x00000010 */
-#define HSEM_C2MISR_MISF4         HSEM_C2MISR_MISF4_Msk                          /*!<semaphore 4 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF5_Pos     (5U)
-#define HSEM_C2MISR_MISF5_Msk     (0x1UL << HSEM_C2MISR_MISF5_Pos)               /*!< 0x00000020 */
-#define HSEM_C2MISR_MISF5         HSEM_C2MISR_MISF5_Msk                          /*!<semaphore 5 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF6_Pos     (6U)
-#define HSEM_C2MISR_MISF6_Msk     (0x1UL << HSEM_C2MISR_MISF6_Pos)               /*!< 0x00000040 */
-#define HSEM_C2MISR_MISF6         HSEM_C2MISR_MISF6_Msk                          /*!<semaphore 6 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF7_Pos     (7U)
-#define HSEM_C2MISR_MISF7_Msk     (0x1UL << HSEM_C2MISR_MISF7_Pos)               /*!< 0x00000080 */
-#define HSEM_C2MISR_MISF7         HSEM_C2MISR_MISF7_Msk                          /*!<semaphore 7 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF8_Pos     (8U)
-#define HSEM_C2MISR_MISF8_Msk     (0x1UL << HSEM_C2MISR_MISF8_Pos)               /*!< 0x00000100 */
-#define HSEM_C2MISR_MISF8         HSEM_C2MISR_MISF8_Msk                          /*!<semaphore 8 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF9_Pos     (9U)
-#define HSEM_C2MISR_MISF9_Msk     (0x1UL << HSEM_C2MISR_MISF9_Pos)               /*!< 0x00000200 */
-#define HSEM_C2MISR_MISF9         HSEM_C2MISR_MISF9_Msk                          /*!<semaphore 9 CPU2 interrupt masked status bit.  */
-#define HSEM_C2MISR_MISF10_Pos    (10U)
-#define HSEM_C2MISR_MISF10_Msk    (0x1UL << HSEM_C2MISR_MISF10_Pos)              /*!< 0x00000400 */
-#define HSEM_C2MISR_MISF10        HSEM_C2MISR_MISF10_Msk                         /*!<semaphore 10 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF11_Pos    (11U)
-#define HSEM_C2MISR_MISF11_Msk    (0x1UL << HSEM_C2MISR_MISF11_Pos)              /*!< 0x00000800 */
-#define HSEM_C2MISR_MISF11        HSEM_C2MISR_MISF11_Msk                         /*!<semaphore 11 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF12_Pos    (12U)
-#define HSEM_C2MISR_MISF12_Msk    (0x1UL << HSEM_C2MISR_MISF12_Pos)              /*!< 0x00001000 */
-#define HSEM_C2MISR_MISF12        HSEM_C2MISR_MISF12_Msk                         /*!<semaphore 12 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF13_Pos    (13U)
-#define HSEM_C2MISR_MISF13_Msk    (0x1UL << HSEM_C2MISR_MISF13_Pos)              /*!< 0x00002000 */
-#define HSEM_C2MISR_MISF13        HSEM_C2MISR_MISF13_Msk                         /*!<semaphore 13 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF14_Pos    (14U)
-#define HSEM_C2MISR_MISF14_Msk    (0x1UL << HSEM_C2MISR_MISF14_Pos)              /*!< 0x00004000 */
-#define HSEM_C2MISR_MISF14        HSEM_C2MISR_MISF14_Msk                         /*!<semaphore 14 CPU2 interrupt masked status bit. */
-#define HSEM_C2MISR_MISF15_Pos    (15U)
-#define HSEM_C2MISR_MISF15_Msk    (0x1UL << HSEM_C2MISR_MISF15_Pos)              /*!< 0x00008000 */
-#define HSEM_C2MISR_MISF15        HSEM_C2MISR_MISF15_Msk                         /*!<semaphore 15 CPU2 interrupt masked status bit. */
-
-/********************  Bit definition for HSEM_CR register  *****************/
-#define HSEM_CR_COREID_Pos       (8U)
-#define HSEM_CR_COREID_Msk       (0xFUL << HSEM_CR_COREID_Pos)                 /*!< 0x00000F00 */
-#define HSEM_CR_COREID           HSEM_CR_COREID_Msk                            /*!<CoreID of semaphores to be cleared. */
-#define HSEM_CR_COREID_CPU1      (0x4U << HSEM_CR_COREID_Pos)
-#define HSEM_CR_COREID_CPU2      (0x8U << HSEM_CR_COREID_Pos)
-#define HSEM_CR_COREID_CURRENT   HSEM_CR_COREID_CPU1
-#define HSEM_CR_KEY_Pos          (16U)
-#define HSEM_CR_KEY_Msk          (0xFFFFUL << HSEM_CR_KEY_Pos)                 /*!< 0xFFFF0000 */
-#define HSEM_CR_KEY              HSEM_CR_KEY_Msk                               /*!<semaphores clear key. */
-
-/********************  Bit definition for HSEM_KEYR register  *****************/
-#define HSEM_KEYR_KEY_Pos        (16U)
-#define HSEM_KEYR_KEY_Msk        (0xFFFFUL << HSEM_KEYR_KEY_Pos)               /*!< 0xFFFF0000 */
-#define HSEM_KEYR_KEY            HSEM_KEYR_KEY_Msk                             /*!<semaphores clear key. */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       Public Key Accelerator (PKA)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bits definition for PKA_CR register  **************/
-#define PKA_CR_EN_Pos              (0U)
-#define PKA_CR_EN_Msk              (0x1UL << PKA_CR_EN_Pos)                /*!< 0x00000001 */
-#define PKA_CR_EN                  PKA_CR_EN_Msk                           /*!< PKA enable */
-#define PKA_CR_START_Pos           (1U)
-#define PKA_CR_START_Msk           (0x1UL << PKA_CR_START_Pos)             /*!< 0x00000002 */
-#define PKA_CR_START               PKA_CR_START_Msk                        /*!< Start operation */
-#define PKA_CR_MODE_Pos            (8U)
-#define PKA_CR_MODE_Msk            (0x3FUL << PKA_CR_MODE_Pos)             /*!< 0x00003F00 */
-#define PKA_CR_MODE                PKA_CR_MODE_Msk                         /*!< MODE[5:0] PKA operation code */
-#define PKA_CR_MODE_0              (0x01UL << PKA_CR_MODE_Pos)             /*!< 0x00000100 */
-#define PKA_CR_MODE_1              (0x02UL << PKA_CR_MODE_Pos)             /*!< 0x00000200 */
-#define PKA_CR_MODE_2              (0x04UL << PKA_CR_MODE_Pos)             /*!< 0x00000400 */
-#define PKA_CR_MODE_3              (0x08UL << PKA_CR_MODE_Pos)             /*!< 0x00000800 */
-#define PKA_CR_MODE_4              (0x10UL << PKA_CR_MODE_Pos)             /*!< 0x00001000 */
-#define PKA_CR_MODE_5              (0x20UL << PKA_CR_MODE_Pos)             /*!< 0x00002000 */
-#define PKA_CR_PROCENDIE_Pos       (17U)
-#define PKA_CR_PROCENDIE_Msk       (0x1UL << PKA_CR_PROCENDIE_Pos)         /*!< 0x00020000 */
-#define PKA_CR_PROCENDIE           PKA_CR_PROCENDIE_Msk                    /*!< End of operation interrupt enable */
-#define PKA_CR_RAMERRIE_Pos        (19U)
-#define PKA_CR_RAMERRIE_Msk        (0x1UL << PKA_CR_RAMERRIE_Pos)          /*!< 0x00080000 */
-#define PKA_CR_RAMERRIE            PKA_CR_RAMERRIE_Msk                     /*!< RAM error interrupt enable */
-#define PKA_CR_ADDRERRIE_Pos       (20U)
-#define PKA_CR_ADDRERRIE_Msk       (0x1UL << PKA_CR_ADDRERRIE_Pos)         /*!< 0x00100000 */
-#define PKA_CR_ADDRERRIE           PKA_CR_ADDRERRIE_Msk                    /*!< RAM error interrupt enable */
-
-/*******************  Bits definition for PKA_SR register  **************/
-#define PKA_SR_BUSY_Pos            (16U)
-#define PKA_SR_BUSY_Msk            (0x1UL << PKA_SR_BUSY_Pos)              /*!< 0x00010000 */
-#define PKA_SR_BUSY                PKA_SR_BUSY_Msk                         /*!< PKA operation is in progress */
-#define PKA_SR_PROCENDF_Pos        (17U)
-#define PKA_SR_PROCENDF_Msk        (0x1UL << PKA_SR_PROCENDF_Pos)          /*!< 0x00020000 */
-#define PKA_SR_PROCENDF            PKA_SR_PROCENDF_Msk                     /*!< PKA end of operation flag */
-#define PKA_SR_RAMERRF_Pos         (19U)
-#define PKA_SR_RAMERRF_Msk         (0x1UL << PKA_SR_RAMERRF_Pos)           /*!< 0x00080000 */
-#define PKA_SR_RAMERRF             PKA_SR_RAMERRF_Msk                      /*!< PKA RAM error flag */
-#define PKA_SR_ADDRERRF_Pos        (20U)
-#define PKA_SR_ADDRERRF_Msk        (0x1UL << PKA_SR_ADDRERRF_Pos)          /*!< 0x00100000 */
-#define PKA_SR_ADDRERRF            PKA_SR_ADDRERRF_Msk                     /*!< Address error flag */
-
-/*******************  Bits definition for PKA_CLRFR register  **************/
-#define PKA_CLRFR_PROCENDFC_Pos    (17U)
-#define PKA_CLRFR_PROCENDFC_Msk    (0x1UL << PKA_CLRFR_PROCENDFC_Pos)      /*!< 0x00020000 */
-#define PKA_CLRFR_PROCENDFC        PKA_CLRFR_PROCENDFC_Msk                 /*!< Clear PKA end of operation flag */
-#define PKA_CLRFR_RAMERRFC_Pos     (19U)
-#define PKA_CLRFR_RAMERRFC_Msk     (0x1UL << PKA_CLRFR_RAMERRFC_Pos)       /*!< 0x00080000 */
-#define PKA_CLRFR_RAMERRFC         PKA_CLRFR_RAMERRFC_Msk                  /*!< Clear PKA RAM error flag */
-#define PKA_CLRFR_ADDRERRFC_Pos    (20U)
-#define PKA_CLRFR_ADDRERRFC_Msk    (0x1UL << PKA_CLRFR_ADDRERRFC_Pos)      /*!< 0x00100000 */
-#define PKA_CLRFR_ADDRERRFC        PKA_CLRFR_ADDRERRFC_Msk                 /*!< Clear address error flag */
-
-/*******************  Bits definition for PKA RAM  *************************/
-#define PKA_RAM_OFFSET                            0x400U                           /*!< PKA RAM address offset */
-
-/* Compute Montgomery parameter input data */
-#define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS       ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_MONTGOMERY_PARAM_IN_MODULUS           ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Compute Montgomery parameter output data */
-#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER        ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Output Montgomery parameter */
-
-/* Compute modular exponentiation input data */
-#define PKA_MODULAR_EXP_IN_EXP_NB_BITS            ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent number of bits */
-#define PKA_MODULAR_EXP_IN_OP_NB_BITS             ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM       ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Input storage area for Montgomery parameter */
-#define PKA_MODULAR_EXP_IN_EXPONENT_BASE          ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input base of the exponentiation */
-#define PKA_MODULAR_EXP_IN_EXPONENT               ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent to process */
-#define PKA_MODULAR_EXP_IN_MODULUS                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Compute modular exponentiation output data */
-#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM      ((0x594U - PKA_RAM_OFFSET)>>2)   /*!< Output storage area for Montgomery parameter */
-#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC1          ((0x724U - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 1 */
-#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC2          ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 2 */
-#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE         ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Output base of the exponentiation */
-#define PKA_MODULAR_EXP_OUT_SM_ALGO_ACC3          ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Output SM algorithm accumulator 3 */
-
-/* Compute ECC scalar multiplication input data */
-#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS         ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input exponent number of bits */
-#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS          ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN        ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_ECC_SCALAR_MUL_IN_A_COEFF             ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_ECC_SCALAR_MUL_IN_MOD_GF              ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM    ((0x4B4U - PKA_RAM_OFFSET)>>2)   /*!< Input storage area for Montgomery parameter */
-#define PKA_ECC_SCALAR_MUL_IN_K                   ((0x508U - PKA_RAM_OFFSET)>>2)   /*!< Input 'k' of KP */
-#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X     ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y     ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-
-/* Compute ECC scalar multiplication output data */
-#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X           ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Output result X coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y           ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Output result Y coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_X1     ((0xDE8U - PKA_RAM_OFFSET)>>2)   /*!< Output last double X1 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Y1     ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Output last double Y1 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_LAST_DOUBLE_Z1     ((0xE90U - PKA_RAM_OFFSET)>>2)   /*!< Output last double Z1 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_X2     ((0xEE4U - PKA_RAM_OFFSET)>>2)   /*!< Output check point X2 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Y2     ((0xF38U - PKA_RAM_OFFSET)>>2)   /*!< Output check point Y2 coordinate */
-#define PKA_ECC_SCALAR_MUL_OUT_CHECK_POINT_Z2     ((0xF8CU - PKA_RAM_OFFSET)>>2)   /*!< Output check point Z2 coordinate */
-
-/* Point check input data */
-#define PKA_POINT_CHECK_IN_MOD_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_POINT_CHECK_IN_A_COEFF_SIGN           ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_POINT_CHECK_IN_A_COEFF                ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_POINT_CHECK_IN_B_COEFF                ((0x7FCU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'b' coefficient */
-#define PKA_POINT_CHECK_IN_MOD_GF                 ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_POINT_CHECK_IN_INITIAL_POINT_X        ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y        ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-
-/* Point check output data */
-#define PKA_POINT_CHECK_OUT_ERROR                 ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Output error */
-
-/* ECDSA signature input data */
-#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS           ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input order number of bits */
-#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS             ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN            ((0x408U - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_ECDSA_SIGN_IN_A_COEFF                 ((0x40CU - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_ECDSA_SIGN_IN_MOD_GF                  ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_ECDSA_SIGN_IN_K                       ((0x508U - PKA_RAM_OFFSET)>>2)   /*!< Input k value of the ECDSA */
-#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X         ((0x55CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y         ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-#define PKA_ECDSA_SIGN_IN_HASH_E                  ((0xDE8U - PKA_RAM_OFFSET)>>2)   /*!< Input e, hash of the message */
-#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D           ((0xE3CU - PKA_RAM_OFFSET)>>2)   /*!< Input d, private key */
-#define PKA_ECDSA_SIGN_IN_ORDER_N                 ((0xE94U - PKA_RAM_OFFSET)>>2)   /*!< Input n, order of the curve */
-
-/* ECDSA signature output data */
-#define PKA_ECDSA_SIGN_OUT_ERROR                  ((0xEE8U - PKA_RAM_OFFSET)>>2)   /*!< Output error */
-#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R            ((0x700U - PKA_RAM_OFFSET)>>2)   /*!< Output signature r */
-#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S            ((0x754U - PKA_RAM_OFFSET)>>2)   /*!< Output signature s */
-#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X          ((0x103CU - PKA_RAM_OFFSET)>>2)   /*!< Output final point kP X coordinate */
-#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y          ((0x1090U - PKA_RAM_OFFSET)>>2)   /*!< Output final point kP Y coordinate */
-
-/* ECDSA verification input data */
-#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS          ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input order number of bits */
-#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS            ((0x4B4U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus number of bits */
-#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN           ((0x45CU - PKA_RAM_OFFSET)>>2)   /*!< Input sign of the 'a' coefficient */
-#define PKA_ECDSA_VERIF_IN_A_COEFF                ((0x460U - PKA_RAM_OFFSET)>>2)   /*!< Input ECC curve 'a' coefficient */
-#define PKA_ECDSA_VERIF_IN_MOD_GF                 ((0x4B8U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus GF(p) */
-#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X        ((0x5E8U - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P X coordinate */
-#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y        ((0x63CU - PKA_RAM_OFFSET)>>2)   /*!< Input initial point P Y coordinate */
-#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X     ((0xF40U - PKA_RAM_OFFSET)>>2)   /*!< Input public key point X coordinate */
-#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y     ((0xF94U - PKA_RAM_OFFSET)>>2)   /*!< Input public key point Y coordinate */
-#define PKA_ECDSA_VERIF_IN_SIGNATURE_R            ((0x1098U - PKA_RAM_OFFSET)>>2)   /*!< Input r, part of the signature */
-#define PKA_ECDSA_VERIF_IN_SIGNATURE_S            ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input s, part of the signature */
-#define PKA_ECDSA_VERIF_IN_HASH_E                 ((0xFE8U - PKA_RAM_OFFSET)>>2)   /*!< Input e, hash of the message */
-#define PKA_ECDSA_VERIF_IN_ORDER_N                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input n, order of the curve */
-
-/* ECDSA verification output data */
-#define PKA_ECDSA_VERIF_OUT_RESULT                ((0x5B0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* RSA CRT exponentiation input data */
-#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operands number of bits */
-#define PKA_RSA_CRT_EXP_IN_DP_CRT                 ((0x65CU - PKA_RAM_OFFSET)>>2)   /*!< Input Dp CRT parameter */
-#define PKA_RSA_CRT_EXP_IN_DQ_CRT                 ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Input Dq CRT parameter */
-#define PKA_RSA_CRT_EXP_IN_QINV_CRT               ((0x7ECU - PKA_RAM_OFFSET)>>2)   /*!< Input qInv CRT parameter */
-#define PKA_RSA_CRT_EXP_IN_PRIME_P                ((0x97CU - PKA_RAM_OFFSET)>>2)   /*!< Input Prime p */
-#define PKA_RSA_CRT_EXP_IN_PRIME_Q                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input Prime q */
-#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE          ((0xEECU - PKA_RAM_OFFSET)>>2)   /*!< Input base of the exponentiation */
-
-/* RSA CRT exponentiation output data */
-#define PKA_RSA_CRT_EXP_OUT_RESULT                ((0x724U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular reduction input data */
-#define PKA_MODULAR_REDUC_IN_OP_LENGTH            ((0x400U - PKA_RAM_OFFSET)>>2)   /*!< Input operand length */
-#define PKA_MODULAR_REDUC_IN_OPERAND              ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand */
-#define PKA_MODULAR_REDUC_IN_MOD_LENGTH           ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus length */
-#define PKA_MODULAR_REDUC_IN_MODULUS              ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Modular reduction output data */
-#define PKA_MODULAR_REDUC_OUT_RESULT              ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Arithmetic addition input data */
-#define PKA_ARITHMETIC_ADD_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_ADD_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_ADD_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Arithmetic addition output data */
-#define PKA_ARITHMETIC_ADD_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Arithmetic substraction input data */
-#define PKA_ARITHMETIC_SUB_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_SUB_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_SUB_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Arithmetic substraction output data */
-#define PKA_ARITHMETIC_SUB_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Arithmetic multiplication input data */
-#define PKA_ARITHMETIC_MUL_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_MUL_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_MUL_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Arithmetic multiplication output data */
-#define PKA_ARITHMETIC_MUL_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Comparison input data */
-#define PKA_COMPARISON_NB_BITS                    ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_COMPARISON_IN_OP1                     ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_COMPARISON_IN_OP2                     ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Comparison output data */
-#define PKA_COMPARISON_OUT_RESULT                 ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular addition input data */
-#define PKA_MODULAR_ADD_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_ADD_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MODULAR_ADD_IN_OP2                    ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_MODULAR_ADD_IN_OP3_MOD                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 (modulus) */
-
-/* Modular addition output data */
-#define PKA_MODULAR_ADD_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular inversion input data */
-#define PKA_MODULAR_INV_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_INV_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MODULAR_INV_IN_OP2_MOD                ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 (modulus) */
-
-/* Modular inversion output data */
-#define PKA_MODULAR_INV_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Modular substraction input data */
-#define PKA_MODULAR_SUB_NB_BITS                   ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MODULAR_SUB_IN_OP1                    ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MODULAR_SUB_IN_OP2                    ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_MODULAR_SUB_IN_OP3_MOD                ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op3 */
-
-/* Modular substraction output data */
-#define PKA_MODULAR_SUB_OUT_RESULT                ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Montgomery multiplication input data */
-#define PKA_MONTGOMERY_MUL_NB_BITS                ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_MONTGOMERY_MUL_IN_OP1                 ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_MONTGOMERY_MUL_IN_OP2                 ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_MONTGOMERY_MUL_IN_OP3_MOD             ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input modulus */
-
-/* Montgomery multiplication output data */
-#define PKA_MONTGOMERY_MUL_OUT_RESULT             ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/* Generic Arithmetic input data */
-#define PKA_ARITHMETIC_ALL_OPS_NB_BITS            ((0x404U - PKA_RAM_OFFSET)>>2)   /*!< Input operand number of bits */
-#define PKA_ARITHMETIC_ALL_OPS_IN_OP1             ((0x8B4U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op1 */
-#define PKA_ARITHMETIC_ALL_OPS_IN_OP2             ((0xA44U - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-#define PKA_ARITHMETIC_ALL_OPS_IN_OP3             ((0xD5CU - PKA_RAM_OFFSET)>>2)   /*!< Input operand op2 */
-
-/* Generic Arithmetic output data */
-#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT         ((0xBD0U - PKA_RAM_OFFSET)>>2)   /*!< Output result */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Power Control                                */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR1 register  ********************/
-#define PWR_CR1_LPMS_Pos               (0U)
-#define PWR_CR1_LPMS_Msk               (0x7UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000007 */
-#define PWR_CR1_LPMS                   PWR_CR1_LPMS_Msk                        /*!< Low Power Mode Selection for CPU1 */
-#define PWR_CR1_LPMS_0                 (0x1UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000001 */
-#define PWR_CR1_LPMS_1                 (0x2UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000002 */
-#define PWR_CR1_LPMS_2                 (0x4UL << PWR_CR1_LPMS_Pos)             /*!< 0x00000004 */
-
-#define PWR_CR1_SUBGHZSPINSSSEL_Pos    (3U)
-#define PWR_CR1_SUBGHZSPINSSSEL_Msk    (0x1UL << PWR_CR1_SUBGHZSPINSSSEL_Pos)  /*!< 0x00000008 */
-#define PWR_CR1_SUBGHZSPINSSSEL        PWR_CR1_SUBGHZSPINSSSEL_Msk             /*!< Sub-GHz radio SPI NSS source select */
-
-#define PWR_CR1_FPDR_Pos               (4U)
-#define PWR_CR1_FPDR_Msk               (0x1UL << PWR_CR1_FPDR_Pos)             /*!< 0x00000010 */
-#define PWR_CR1_FPDR                   PWR_CR1_FPDR_Msk                        /*!< Flash power down mode during LPrun for CPU1 */
-
-#define PWR_CR1_FPDS_Pos               (5U)
-#define PWR_CR1_FPDS_Msk               (0x1UL << PWR_CR1_FPDS_Pos)             /*!< 0x00000020 */
-#define PWR_CR1_FPDS                   PWR_CR1_FPDS_Msk                        /*!< Flash power down mode during LPsleep for CPU1 */
-
-#define PWR_CR1_DBP_Pos                (8U)
-#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */
-#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Backup Domain write protection */
-
-#define PWR_CR1_VOS_Pos                (9U)
-#define PWR_CR1_VOS_Msk                (0x3UL << PWR_CR1_VOS_Pos)              /*!< 0x00000600 */
-#define PWR_CR1_VOS                    PWR_CR1_VOS_Msk                         /*!< Voltage scaling range selection */
-#define PWR_CR1_VOS_0                  (0x1UL << PWR_CR1_VOS_Pos)              /*!< 0x00000200 */
-#define PWR_CR1_VOS_1                  (0x2UL << PWR_CR1_VOS_Pos)              /*!< 0x00000400 */
-
-#define PWR_CR1_LPR_Pos                (14U)
-#define PWR_CR1_LPR_Msk                (0x1UL << PWR_CR1_LPR_Pos)              /*!< 0x00004000 */
-#define PWR_CR1_LPR                    PWR_CR1_LPR_Msk                         /*!< Regulator Low-Power Run mode */
-
-/********************  Bit definition for PWR_CR2 register  ********************/
-#define PWR_CR2_PVDE_Pos               (0U)
-#define PWR_CR2_PVDE_Msk               (0x1UL << PWR_CR2_PVDE_Pos)             /*!< 0x00000001 */
-#define PWR_CR2_PVDE                   PWR_CR2_PVDE_Msk                        /*!< Power voltage detector enable */
-
-#define PWR_CR2_PLS_Pos                (1U)
-#define PWR_CR2_PLS_Msk                (0x7UL << PWR_CR2_PLS_Pos)              /*!< 0x0000000E */
-#define PWR_CR2_PLS                    PWR_CR2_PLS_Msk                         /*!< Power voltage detector level selection */
-#define PWR_CR2_PLS_0                  (0x1UL << PWR_CR2_PLS_Pos)              /*!< 0x00000002 */
-#define PWR_CR2_PLS_1                  (0x2UL << PWR_CR2_PLS_Pos)              /*!< 0x00000004 */
-#define PWR_CR2_PLS_2                  (0x4UL << PWR_CR2_PLS_Pos)              /*!< 0x00000008 */
-
-#define PWR_CR2_PVME3_Pos              (6U)
-#define PWR_CR2_PVME3_Msk              (0x1UL << PWR_CR2_PVME3_Pos)            /*!< 0x00000040 */
-#define PWR_CR2_PVME3                  PWR_CR2_PVME3_Msk                       /*!< Peripherical Voltage Monitor Vdda Enable */
-
-/********************  Bit definition for PWR_CR3 register  ********************/
-#define PWR_CR3_EWUP_Pos               (0U)
-#define PWR_CR3_EWUP_Msk               (0x07UL << PWR_CR3_EWUP_Pos)            /*!< 0x00000007 */
-#define PWR_CR3_EWUP                   PWR_CR3_EWUP_Msk                        /*!< Enable all external Wake-Up lines  */
-#define PWR_CR3_EWUP1_Pos              (0U)
-#define PWR_CR3_EWUP1_Msk              (0x1UL << PWR_CR3_EWUP1_Pos)            /*!< 0x00000001 */
-#define PWR_CR3_EWUP1                  PWR_CR3_EWUP1_Msk                       /*!< Enable external WKUP Pin 1 [line 0] */
-#define PWR_CR3_EWUP2_Pos              (1U)
-#define PWR_CR3_EWUP2_Msk              (0x1UL << PWR_CR3_EWUP2_Pos)            /*!< 0x00000002 */
-#define PWR_CR3_EWUP2                  PWR_CR3_EWUP2_Msk                       /*!< Enable external WKUP Pin 2 [line 1] */
-#define PWR_CR3_EWUP3_Pos              (2U)
-#define PWR_CR3_EWUP3_Msk              (0x1UL << PWR_CR3_EWUP3_Pos)            /*!< 0x00000004 */
-#define PWR_CR3_EWUP3                  PWR_CR3_EWUP3_Msk                       /*!< Enable external WKUP Pin 3 [line 2] */
-
-#define PWR_CR3_ULPEN_Pos              (7U)
-#define PWR_CR3_ULPEN_Msk              (0x1UL << PWR_CR3_ULPEN_Pos)            /*!< 0x00000080 */
-#define PWR_CR3_ULPEN                  PWR_CR3_ULPEN_Msk                       /*!< Enable periodical sampling of supply voltage in Stop and Standby modes for detecting condition of PDR and BOR reset */
-
-#define PWR_CR3_EWPVD_Pos              (8U)
-#define PWR_CR3_EWPVD_Msk              (0x1UL << PWR_CR3_EWPVD_Pos)            /*!< 0x00000100 */
-#define PWR_CR3_EWPVD                  PWR_CR3_EWPVD_Msk                       /*!< Enable wakeup PVD for CPU1 */
-
-#define PWR_CR3_RRS_Pos                (9U)
-#define PWR_CR3_RRS_Msk                (0x1UL << PWR_CR3_RRS_Pos)              /*!< 0x00000200 */
-#define PWR_CR3_RRS                    PWR_CR3_RRS_Msk                         /*!< SRAM2 retention in STANDBY mode */
-
-#define PWR_CR3_APC_Pos                (10U)
-#define PWR_CR3_APC_Msk                (0x1UL << PWR_CR3_APC_Pos)              /*!< 0x00000400 */
-#define PWR_CR3_APC                    PWR_CR3_APC_Msk                         /*!< Apply pull-up and pull-down configuration for CPU1 */
-
-#define PWR_CR3_EWRFBUSY_Pos           (11U)
-#define PWR_CR3_EWRFBUSY_Msk           (0x1UL << PWR_CR3_EWRFBUSY_Pos)         /*!< 0x00008000 */
-#define PWR_CR3_EWRFBUSY                PWR_CR3_EWRFBUSY_Msk                   /*!< Enable Radio busy IRQ and wake-up for CPU1 */
-#define PWR_CR3_EWRFIRQ_Pos            (13U)
-#define PWR_CR3_EWRFIRQ_Msk            (0x1UL << PWR_CR3_EWRFIRQ_Pos)          /*!< 0x00020000 */
-#define PWR_CR3_EWRFIRQ                PWR_CR3_EWRFIRQ_Msk                     /*!< Enable Radio IRQ[2:0] and wake-up for CPU1 */
-
-#define PWR_CR3_EIWUL_Pos              (15U)
-#define PWR_CR3_EIWUL_Msk              (0x1UL << PWR_CR3_EIWUL_Pos)            /*!< 0x00080000 */
-#define PWR_CR3_EIWUL                  PWR_CR3_EIWUL_Msk                       /*!< Internal Wake-Up line interrupt for CPU1 */
-
-/********************  Bit definition for PWR_CR4 register  ********************/
-#define PWR_CR4_WP1_Pos                (0U)
-#define PWR_CR4_WP1_Msk                (0x1UL << PWR_CR4_WP1_Pos)              /*!< 0x00000001 */
-#define PWR_CR4_WP1                    PWR_CR4_WP1_Msk                         /*!< Wake-Up Pin 1 [line 0] polarity */
-#define PWR_CR4_WP2_Pos                (1U)
-#define PWR_CR4_WP2_Msk                (0x1UL << PWR_CR4_WP2_Pos)              /*!< 0x00000002 */
-#define PWR_CR4_WP2                    PWR_CR4_WP2_Msk                         /*!< Wake-Up Pin 2 [line 1] polarity */
-#define PWR_CR4_WP3_Pos                (2U)
-#define PWR_CR4_WP3_Msk                (0x1UL << PWR_CR4_WP3_Pos)              /*!< 0x00000004 */
-#define PWR_CR4_WP3                    PWR_CR4_WP3_Msk                         /*!< Wake-Up Pin 3 [line 2] polarity */
-
-#define PWR_CR4_VBE_Pos                (8U)
-#define PWR_CR4_VBE_Msk                (0x1UL << PWR_CR4_VBE_Pos)              /*!< 0x00000100 */
-#define PWR_CR4_VBE                    PWR_CR4_VBE_Msk                         /*!< VBAT battery charging enable  */
-#define PWR_CR4_VBRS_Pos               (9U)
-#define PWR_CR4_VBRS_Msk               (0x1UL << PWR_CR4_VBRS_Pos)             /*!< 0x00000200 */
-#define PWR_CR4_VBRS                   PWR_CR4_VBRS_Msk                        /*!< VBAT battery charging resistor selection */
-
-#define PWR_CR4_WRFBUSYP_Pos           (11U)
-#define PWR_CR4_WRFBUSYP_Msk           (0x1UL << PWR_CR4_WRFBUSYP_Pos)         /*!< 0x00008000 */
-#define PWR_CR4_WRFBUSYP               PWR_CR4_WRFBUSYP_Msk                    /*!< Wake-up radio busy polarity */
-
-/********************  Bit definition for PWR_SR1 register  ********************/
-#define PWR_SR1_WUF_Pos                (0U)
-#define PWR_SR1_WUF_Msk                (0x1FUL << PWR_SR1_WUF_Pos)             /*!< 0x00000007 */
-#define PWR_SR1_WUF                    PWR_SR1_WUF_Msk                         /*!< Wakeup Flags of all pins */
-#define PWR_SR1_WUF1_Pos               (0U)
-#define PWR_SR1_WUF1_Msk               (0x1UL << PWR_SR1_WUF1_Pos)             /*!< 0x00000001 */
-#define PWR_SR1_WUF1                   PWR_SR1_WUF1_Msk                        /*!< Wakeup Pin 1 [Flag 0] */
-#define PWR_SR1_WUF2_Pos               (1U)
-#define PWR_SR1_WUF2_Msk               (0x1UL << PWR_SR1_WUF2_Pos)             /*!< 0x00000002 */
-#define PWR_SR1_WUF2                   PWR_SR1_WUF2_Msk                        /*!< Wakeup Pin 2 [Flag 1] */
-#define PWR_SR1_WUF3_Pos               (2U)
-#define PWR_SR1_WUF3_Msk               (0x1UL << PWR_SR1_WUF3_Pos)             /*!< 0x00000004 */
-#define PWR_SR1_WUF3                   PWR_SR1_WUF3_Msk                        /*!< Wakeup Pin 3 [Flag 2] */
-
-#define PWR_SR1_WPVDF_Pos              (8U)
-#define PWR_SR1_WPVDF_Msk              (0x1UL << PWR_SR1_WPVDF_Pos)            /*!< 0x00000100 */
-#define PWR_SR1_WPVDF                  PWR_SR1_WPVDF_Msk                       /*!< Wakeup PVD flag */
-
-#define PWR_SR1_WRFBUSYF_Pos           (11U)
-#define PWR_SR1_WRFBUSYF_Msk           (0x1UL << PWR_SR1_WRFBUSYF_Pos)          /*!< 0x00000800 */
-#define PWR_SR1_WRFBUSYF               PWR_SR1_WRFBUSYF_Msk                     /*!< Wakeup radio busy flag */
-
-#define PWR_SR1_WUFI_Pos               (15U)
-#define PWR_SR1_WUFI_Msk               (0x1UL << PWR_SR1_WUFI_Pos)             /*!< 0x00008000 */
-#define PWR_SR1_WUFI                   PWR_SR1_WUFI_Msk                        /*!< Internal wakeup interrupt flag */
-
-/********************  Bit definition for PWR_SR2 register  ********************/
-#define PWR_SR2_RFBUSYS_Pos            (1U)
-#define PWR_SR2_RFBUSYS_Msk            (0x1UL << PWR_SR2_RFBUSYS_Pos)          /*!< 0x00000002 */
-#define PWR_SR2_RFBUSYS                PWR_SR2_RFBUSYS_Msk                     /*!< Radio busy signal status */
-
-#define PWR_SR2_RFBUSYMS_Pos           (2U)
-#define PWR_SR2_RFBUSYMS_Msk           (0x1UL << PWR_SR2_RFBUSYMS_Pos)         /*!< 0x00000004 */
-#define PWR_SR2_RFBUSYMS               PWR_SR2_RFBUSYMS_Msk                    /*!< Radio busy masked signal status */
-
-#define PWR_SR2_SMPSRDY_Pos            (3U)
-#define PWR_SR2_SMPSRDY_Msk            (0x1UL << PWR_SR2_SMPSRDY_Pos)          /*!< 0x00000008 */
-#define PWR_SR2_SMPSRDY                PWR_SR2_SMPSRDY_Msk                     /*!< SMPS ready flag */
-#define PWR_SR2_LDORDY_Pos             (4U)
-#define PWR_SR2_LDORDY_Msk             (0x1UL << PWR_SR2_LDORDY_Pos)           /*!< 0x00000010 */
-#define PWR_SR2_LDORDY                 PWR_SR2_LDORDY_Msk                      /*!< LDO ready flag */
-
-#define PWR_SR2_RFEOLF_Pos             (5U)
-#define PWR_SR2_RFEOLF_Msk             (0x1UL << PWR_SR2_RFEOLF_Pos)           /*!< 0x00000020 */
-#define PWR_SR2_RFEOLF                 PWR_SR2_RFEOLF_Msk                      /*!< Radio end of life flag */
-
-#define PWR_SR2_REGMRS_Pos             (6U)
-#define PWR_SR2_REGMRS_Msk             (0x1UL << PWR_SR2_REGMRS_Pos)           /*!< 0x00000040 */
-#define PWR_SR2_REGMRS                 PWR_SR2_REGMRS_Msk                      /*!< Main regulator status */
-
-#define PWR_SR2_FLASHRDY_Pos           (7U)
-#define PWR_SR2_FLASHRDY_Msk           (0x1UL << PWR_SR2_FLASHRDY_Pos)         /*!< 0x00000080 */
-#define PWR_SR2_FLASHRDY               PWR_SR2_FLASHRDY_Msk                    /*!< Flash ready */
-
-#define PWR_SR2_REGLPS_Pos             (8U)
-#define PWR_SR2_REGLPS_Msk             (0x1UL << PWR_SR2_REGLPS_Pos)           /*!< 0x00000100 */
-#define PWR_SR2_REGLPS                 PWR_SR2_REGLPS_Msk                      /*!< Low-power regulator ready */
-#define PWR_SR2_REGLPF_Pos             (9U)
-#define PWR_SR2_REGLPF_Msk             (0x1UL << PWR_SR2_REGLPF_Pos)           /*!< 0x00000200 */
-#define PWR_SR2_REGLPF                 PWR_SR2_REGLPF_Msk                      /*!< Low-power regulator being used */
-
-#define PWR_SR2_VOSF_Pos               (10U)
-#define PWR_SR2_VOSF_Msk               (0x1UL << PWR_SR2_VOSF_Pos)             /*!< 0x00000400 */
-#define PWR_SR2_VOSF                   PWR_SR2_VOSF_Msk                        /*!< Voltage scaling flag    */
-#define PWR_SR2_PVDO_Pos               (11U)
-#define PWR_SR2_PVDO_Msk               (0x1UL << PWR_SR2_PVDO_Pos)             /*!< 0x00000800 */
-#define PWR_SR2_PVDO                   PWR_SR2_PVDO_Msk                        /*!< Power voltage detector output */
-
-#define PWR_SR2_PVMO3_Pos              (14U)
-#define PWR_SR2_PVMO3_Msk              (0x1UL << PWR_SR2_PVMO3_Pos)            /*!< 0x00004000 */
-#define PWR_SR2_PVMO3                  PWR_SR2_PVMO3_Msk                       /*!< Peripheral voltage monitor output 3: VDDA vs. 1.62V */
-
-/********************  Bit definition for PWR_SCR register  ********************/
-#define PWR_SCR_CWUF_Pos               (0U)
-#define PWR_SCR_CWUF_Msk               (0x7UL << PWR_SCR_CWUF_Pos)             /*!< 0x00000007 */
-#define PWR_SCR_CWUF                   PWR_SCR_CWUF_Msk                        /*!< Clear Wake-up Flags for all pins */
-#define PWR_SCR_CWUF1_Pos              (0U)
-#define PWR_SCR_CWUF1_Msk              (0x1UL << PWR_SCR_CWUF1_Pos)            /*!< 0x00000001 */
-#define PWR_SCR_CWUF1                  PWR_SCR_CWUF1_Msk                       /*!< Clear Wake-up Pin 1 [Flag 0] */
-#define PWR_SCR_CWUF2_Pos              (1U)
-#define PWR_SCR_CWUF2_Msk              (0x1UL << PWR_SCR_CWUF2_Pos)            /*!< 0x00000002 */
-#define PWR_SCR_CWUF2                  PWR_SCR_CWUF2_Msk                       /*!< Clear Wake-up Pin 2 [Flag 1] */
-#define PWR_SCR_CWUF3_Pos              (2U)
-#define PWR_SCR_CWUF3_Msk              (0x1UL << PWR_SCR_CWUF3_Pos)            /*!< 0x00000004 */
-#define PWR_SCR_CWUF3                  PWR_SCR_CWUF3_Msk                       /*!< Clear Wake-up Pin 3 [Flag 2] */
-
-#define PWR_SCR_CWPVDF_Pos             (8U)
-#define PWR_SCR_CWPVDF_Msk             (0x1UL << PWR_SCR_CWPVDF_Pos)           /*!< 0x00000100 */
-#define PWR_SCR_CWPVDF                 PWR_SCR_CWPVDF_Msk                      /*!< Clear wakeup PVD interrupt flag */
-
-#define PWR_SCR_CWRFBUSYF_Pos          (11U)
-#define PWR_SCR_CWRFBUSYF_Msk          (0x1UL << PWR_SCR_CWRFBUSYF_Pos)        /*!< 0x00000800 */
-#define PWR_SCR_CWRFBUSYF              PWR_SCR_CWRFBUSYF_Msk                   /*!< Clear Radio busy interrupt flag */
-
-/********************  Bit definition for PWR_CR5 register  ********************/
-#define PWR_CR5_RFEOLEN_Pos            (14U)
-#define PWR_CR5_RFEOLEN_Msk            (0x1UL << PWR_CR5_RFEOLEN_Pos)           /*!< 0x00004000 */
-#define PWR_CR5_RFEOLEN                PWR_CR5_RFEOLEN_Msk                      /*!< Enable Radio End Of Life detector enabled */
-
-#define PWR_CR5_SMPSEN_Pos             (15U)
-#define PWR_CR5_SMPSEN_Msk             (0x1UL << PWR_CR5_SMPSEN_Pos)           /*!< 0x00008000 */
-#define PWR_CR5_SMPSEN                 PWR_CR5_SMPSEN_Msk                      /*!< Enable SMPS Step Down converter SMPS mode enable */
-
-/********************  Bit definition for PWR_PUCRA register  *****************/
-#define PWR_PUCRA_PA0_Pos              (0U)
-#define PWR_PUCRA_PA0_Msk              (0x1UL << PWR_PUCRA_PA0_Pos)            /*!< 0x00000001 */
-#define PWR_PUCRA_PA0                  PWR_PUCRA_PA0_Msk                       /*!< Pin PA0 Pull-Up set */
-#define PWR_PUCRA_PA1_Pos              (1U)
-#define PWR_PUCRA_PA1_Msk              (0x1UL << PWR_PUCRA_PA1_Pos)            /*!< 0x00000002 */
-#define PWR_PUCRA_PA1                  PWR_PUCRA_PA1_Msk                       /*!< Pin PA1 Pull-Up set */
-#define PWR_PUCRA_PA2_Pos              (2U)
-#define PWR_PUCRA_PA2_Msk              (0x1UL << PWR_PUCRA_PA2_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRA_PA2                  PWR_PUCRA_PA2_Msk                       /*!< Pin PA2 Pull-Up set */
-#define PWR_PUCRA_PA3_Pos              (3U)
-#define PWR_PUCRA_PA3_Msk              (0x1UL << PWR_PUCRA_PA3_Pos)            /*!< 0x00000008 */
-#define PWR_PUCRA_PA3                  PWR_PUCRA_PA3_Msk                       /*!< Pin PA3 Pull-Up set */
-#define PWR_PUCRA_PA4_Pos              (4U)
-#define PWR_PUCRA_PA4_Msk              (0x1UL << PWR_PUCRA_PA4_Pos)            /*!< 0x00000010 */
-#define PWR_PUCRA_PA4                  PWR_PUCRA_PA4_Msk                       /*!< Pin PA4 Pull-Up set */
-#define PWR_PUCRA_PA5_Pos              (5U)
-#define PWR_PUCRA_PA5_Msk              (0x1UL << PWR_PUCRA_PA5_Pos)            /*!< 0x00000020 */
-#define PWR_PUCRA_PA5                  PWR_PUCRA_PA5_Msk                       /*!< Pin PA5 Pull-Up set */
-#define PWR_PUCRA_PA6_Pos              (6U)
-#define PWR_PUCRA_PA6_Msk              (0x1UL << PWR_PUCRA_PA6_Pos)            /*!< 0x00000040 */
-#define PWR_PUCRA_PA6                  PWR_PUCRA_PA6_Msk                       /*!< Pin PA6 Pull-Up set */
-#define PWR_PUCRA_PA7_Pos              (7U)
-#define PWR_PUCRA_PA7_Msk              (0x1UL << PWR_PUCRA_PA7_Pos)            /*!< 0x00000080 */
-#define PWR_PUCRA_PA7                  PWR_PUCRA_PA7_Msk                       /*!< Pin PA7 Pull-Up set */
-#define PWR_PUCRA_PA8_Pos              (8U)
-#define PWR_PUCRA_PA8_Msk              (0x1UL << PWR_PUCRA_PA8_Pos)            /*!< 0x00000100 */
-#define PWR_PUCRA_PA8                  PWR_PUCRA_PA8_Msk                       /*!< Pin PA8 Pull-Up set */
-#define PWR_PUCRA_PA9_Pos              (9U)
-#define PWR_PUCRA_PA9_Msk              (0x1UL << PWR_PUCRA_PA9_Pos)            /*!< 0x00000200 */
-#define PWR_PUCRA_PA9                  PWR_PUCRA_PA9_Msk                       /*!< Pin PA9 Pull-Up set */
-#define PWR_PUCRA_PA10_Pos             (10U)
-#define PWR_PUCRA_PA10_Msk             (0x1UL << PWR_PUCRA_PA10_Pos)           /*!< 0x00000400 */
-#define PWR_PUCRA_PA10                 PWR_PUCRA_PA10_Msk                      /*!< Pin PA10 Pull-Up set */
-#define PWR_PUCRA_PA11_Pos             (11U)
-#define PWR_PUCRA_PA11_Msk             (0x1UL << PWR_PUCRA_PA11_Pos)           /*!< 0x00000800 */
-#define PWR_PUCRA_PA11                 PWR_PUCRA_PA11_Msk                      /*!< Pin PA11 Pull-Up set */
-#define PWR_PUCRA_PA12_Pos             (12U)
-#define PWR_PUCRA_PA12_Msk             (0x1UL << PWR_PUCRA_PA12_Pos)           /*!< 0x00001000 */
-#define PWR_PUCRA_PA12                 PWR_PUCRA_PA12_Msk                      /*!< Pin PA12 Pull-Up set */
-#define PWR_PUCRA_PA13_Pos             (13U)
-#define PWR_PUCRA_PA13_Msk             (0x1UL << PWR_PUCRA_PA13_Pos)           /*!< 0x00002000 */
-#define PWR_PUCRA_PA13                 PWR_PUCRA_PA13_Msk                      /*!< Pin PA13 Pull-Up set */
-#define PWR_PUCRA_PA14_Pos             (14U)
-#define PWR_PUCRA_PA14_Msk             (0x1UL << PWR_PUCRA_PA14_Pos)           /*!< 0x00004000 */
-#define PWR_PUCRA_PA14                 PWR_PUCRA_PA14_Msk                      /*!< Pin PA14 Pull-Up set */
-#define PWR_PUCRA_PA15_Pos             (15U)
-#define PWR_PUCRA_PA15_Msk             (0x1UL << PWR_PUCRA_PA15_Pos)           /*!< 0x00008000 */
-#define PWR_PUCRA_PA15                 PWR_PUCRA_PA15_Msk                      /*!< Pin PA15 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRA register  *****************/
-#define PWR_PDCRA_PA0_Pos              (0U)
-#define PWR_PDCRA_PA0_Msk              (0x1UL << PWR_PDCRA_PA0_Pos)            /*!< 0x00000001 */
-#define PWR_PDCRA_PA0                  PWR_PDCRA_PA0_Msk                       /*!< Pin PA0 Pull-Down set */
-#define PWR_PDCRA_PA1_Pos              (1U)
-#define PWR_PDCRA_PA1_Msk              (0x1UL << PWR_PDCRA_PA1_Pos)            /*!< 0x00000002 */
-#define PWR_PDCRA_PA1                  PWR_PDCRA_PA1_Msk                       /*!< Pin PA1 Pull-Down set */
-#define PWR_PDCRA_PA2_Pos              (2U)
-#define PWR_PDCRA_PA2_Msk              (0x1UL << PWR_PDCRA_PA2_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRA_PA2                  PWR_PDCRA_PA2_Msk                       /*!< Pin PA2 Pull-Down set */
-#define PWR_PDCRA_PA3_Pos              (3U)
-#define PWR_PDCRA_PA3_Msk              (0x1UL << PWR_PDCRA_PA3_Pos)            /*!< 0x00000008 */
-#define PWR_PDCRA_PA3                  PWR_PDCRA_PA3_Msk                       /*!< Pin PA3 Pull-Down set */
-#define PWR_PDCRA_PA4_Pos              (4U)
-#define PWR_PDCRA_PA4_Msk              (0x1UL << PWR_PDCRA_PA4_Pos)            /*!< 0x00000010 */
-#define PWR_PDCRA_PA4                  PWR_PDCRA_PA4_Msk                       /*!< Pin PA4 Pull-Down set */
-#define PWR_PDCRA_PA5_Pos              (5U)
-#define PWR_PDCRA_PA5_Msk              (0x1UL << PWR_PDCRA_PA5_Pos)            /*!< 0x00000020 */
-#define PWR_PDCRA_PA5                  PWR_PDCRA_PA5_Msk                       /*!< Pin PA5 Pull-Down set */
-#define PWR_PDCRA_PA6_Pos              (6U)
-#define PWR_PDCRA_PA6_Msk              (0x1UL << PWR_PDCRA_PA6_Pos)            /*!< 0x00000040 */
-#define PWR_PDCRA_PA6                  PWR_PDCRA_PA6_Msk                       /*!< Pin PA6 Pull-Down set */
-#define PWR_PDCRA_PA7_Pos              (7U)
-#define PWR_PDCRA_PA7_Msk              (0x1UL << PWR_PDCRA_PA7_Pos)            /*!< 0x00000080 */
-#define PWR_PDCRA_PA7                  PWR_PDCRA_PA7_Msk                       /*!< Pin PA7 Pull-Down set */
-#define PWR_PDCRA_PA8_Pos              (8U)
-#define PWR_PDCRA_PA8_Msk              (0x1UL << PWR_PDCRA_PA8_Pos)            /*!< 0x00000100 */
-#define PWR_PDCRA_PA8                  PWR_PDCRA_PA8_Msk                       /*!< Pin PA8 Pull-Down set */
-#define PWR_PDCRA_PA9_Pos              (9U)
-#define PWR_PDCRA_PA9_Msk              (0x1UL << PWR_PDCRA_PA9_Pos)            /*!< 0x00000200 */
-#define PWR_PDCRA_PA9                  PWR_PDCRA_PA9_Msk                       /*!< Pin PA9 Pull-Down set */
-#define PWR_PDCRA_PA10_Pos             (10U)
-#define PWR_PDCRA_PA10_Msk             (0x1UL << PWR_PDCRA_PA10_Pos)           /*!< 0x00000400 */
-#define PWR_PDCRA_PA10                 PWR_PDCRA_PA10_Msk                      /*!< Pin PA10 Pull-Down set */
-#define PWR_PDCRA_PA11_Pos             (11U)
-#define PWR_PDCRA_PA11_Msk             (0x1UL << PWR_PDCRA_PA11_Pos)           /*!< 0x00000800 */
-#define PWR_PDCRA_PA11                 PWR_PDCRA_PA11_Msk                      /*!< Pin PA11 Pull-Down set */
-#define PWR_PDCRA_PA12_Pos             (12U)
-#define PWR_PDCRA_PA12_Msk             (0x1UL << PWR_PDCRA_PA12_Pos)           /*!< 0x00001000 */
-#define PWR_PDCRA_PA12                 PWR_PDCRA_PA12_Msk                      /*!< Pin PA12 Pull-Down set */
-#define PWR_PDCRA_PA13_Pos             (13U)
-#define PWR_PDCRA_PA13_Msk             (0x1UL << PWR_PDCRA_PA13_Pos)           /*!< 0x00002000 */
-#define PWR_PDCRA_PA13                 PWR_PDCRA_PA13_Msk                      /*!< Pin PA13 Pull-Down set */
-#define PWR_PDCRA_PA14_Pos             (14U)
-#define PWR_PDCRA_PA14_Msk             (0x1UL << PWR_PDCRA_PA14_Pos)           /*!< 0x00004000 */
-#define PWR_PDCRA_PA14                 PWR_PDCRA_PA14_Msk                      /*!< Pin PA14 Pull-Down set */
-#define PWR_PDCRA_PA15_Pos             (15U)
-#define PWR_PDCRA_PA15_Msk             (0x1UL << PWR_PDCRA_PA15_Pos)           /*!< 0x00008000 */
-#define PWR_PDCRA_PA15                 PWR_PDCRA_PA15_Msk                      /*!< Pin PA15 Pull-Down set */
-
-/********************  Bit definition for PWR_PUCRB register  *****************/
-#define PWR_PUCRB_PB0_Pos              (0U)
-#define PWR_PUCRB_PB0_Msk              (0x1UL << PWR_PUCRB_PB0_Pos)            /*!< 0x00000001 */
-#define PWR_PUCRB_PB0                  PWR_PUCRB_PB0_Msk                       /*!< Pin PB0 Pull-Up set */
-#define PWR_PUCRB_PB1_Pos              (1U)
-#define PWR_PUCRB_PB1_Msk              (0x1UL << PWR_PUCRB_PB1_Pos)            /*!< 0x00000002 */
-#define PWR_PUCRB_PB1                  PWR_PUCRB_PB1_Msk                       /*!< Pin PB1 Pull-Up set */
-#define PWR_PUCRB_PB2_Pos              (2U)
-#define PWR_PUCRB_PB2_Msk              (0x1UL << PWR_PUCRB_PB2_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRB_PB2                  PWR_PUCRB_PB2_Msk                       /*!< Pin PB2 Pull-Up set */
-#define PWR_PUCRB_PB3_Pos              (3U)
-#define PWR_PUCRB_PB3_Msk              (0x1UL << PWR_PUCRB_PB3_Pos)            /*!< 0x00000008 */
-#define PWR_PUCRB_PB3                  PWR_PUCRB_PB3_Msk                       /*!< Pin PB3 Pull-Up set */
-#define PWR_PUCRB_PB4_Pos              (4U)
-#define PWR_PUCRB_PB4_Msk              (0x1UL << PWR_PUCRB_PB4_Pos)            /*!< 0x00000010 */
-#define PWR_PUCRB_PB4                  PWR_PUCRB_PB4_Msk                       /*!< Pin PB4 Pull-Up set */
-#define PWR_PUCRB_PB5_Pos              (5U)
-#define PWR_PUCRB_PB5_Msk              (0x1UL << PWR_PUCRB_PB5_Pos)            /*!< 0x00000020 */
-#define PWR_PUCRB_PB5                  PWR_PUCRB_PB5_Msk                       /*!< Pin PB5 Pull-Up set */
-#define PWR_PUCRB_PB6_Pos              (6U)
-#define PWR_PUCRB_PB6_Msk              (0x1UL << PWR_PUCRB_PB6_Pos)            /*!< 0x00000040 */
-#define PWR_PUCRB_PB6                  PWR_PUCRB_PB6_Msk                       /*!< Pin PB6 Pull-Up set */
-#define PWR_PUCRB_PB7_Pos              (7U)
-#define PWR_PUCRB_PB7_Msk              (0x1UL << PWR_PUCRB_PB7_Pos)            /*!< 0x00000080 */
-#define PWR_PUCRB_PB7                  PWR_PUCRB_PB7_Msk                       /*!< Pin PB7 Pull-Up set */
-#define PWR_PUCRB_PB8_Pos              (8U)
-#define PWR_PUCRB_PB8_Msk              (0x1UL << PWR_PUCRB_PB8_Pos)            /*!< 0x00000100 */
-#define PWR_PUCRB_PB8                  PWR_PUCRB_PB8_Msk                       /*!< Pin PB8 Pull-Up set */
-#define PWR_PUCRB_PB9_Pos              (9U)
-#define PWR_PUCRB_PB9_Msk              (0x1UL << PWR_PUCRB_PB9_Pos)            /*!< 0x00000200 */
-#define PWR_PUCRB_PB9                  PWR_PUCRB_PB9_Msk                       /*!< Pin PB9 Pull-Up set */
-#define PWR_PUCRB_PB10_Pos             (10U)
-#define PWR_PUCRB_PB10_Msk             (0x1UL << PWR_PUCRB_PB10_Pos)           /*!< 0x00000400 */
-#define PWR_PUCRB_PB10                 PWR_PUCRB_PB10_Msk                      /*!< Pin PB10 Pull-Up set */
-#define PWR_PUCRB_PB11_Pos             (11U)
-#define PWR_PUCRB_PB11_Msk             (0x1UL << PWR_PUCRB_PB11_Pos)           /*!< 0x00000800 */
-#define PWR_PUCRB_PB11                 PWR_PUCRB_PB11_Msk                      /*!< Pin PB11 Pull-Up set */
-#define PWR_PUCRB_PB12_Pos             (12U)
-#define PWR_PUCRB_PB12_Msk             (0x1UL << PWR_PUCRB_PB12_Pos)           /*!< 0x00001000 */
-#define PWR_PUCRB_PB12                 PWR_PUCRB_PB12_Msk                      /*!< Pin PB12 Pull-Up set */
-#define PWR_PUCRB_PB13_Pos             (13U)
-#define PWR_PUCRB_PB13_Msk             (0x1UL << PWR_PUCRB_PB13_Pos)           /*!< 0x00002000 */
-#define PWR_PUCRB_PB13                 PWR_PUCRB_PB13_Msk                      /*!< Pin PB13 Pull-Up set */
-#define PWR_PUCRB_PB14_Pos             (14U)
-#define PWR_PUCRB_PB14_Msk             (0x1UL << PWR_PUCRB_PB14_Pos)           /*!< 0x00004000 */
-#define PWR_PUCRB_PB14                 PWR_PUCRB_PB14_Msk                      /*!< Pin PB14 Pull-Up set */
-#define PWR_PUCRB_PB15_Pos             (15U)
-#define PWR_PUCRB_PB15_Msk             (0x1UL << PWR_PUCRB_PB15_Pos)           /*!< 0x00008000 */
-#define PWR_PUCRB_PB15                 PWR_PUCRB_PB15_Msk                      /*!< Pin PB15 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRB register  *****************/
-#define PWR_PDCRB_PB0_Pos              (0U)
-#define PWR_PDCRB_PB0_Msk              (0x1UL << PWR_PDCRB_PB0_Pos)            /*!< 0x00000001 */
-#define PWR_PDCRB_PB0                  PWR_PDCRB_PB0_Msk                       /*!< Pin PB0 Pull-Down set */
-#define PWR_PDCRB_PB1_Pos              (1U)
-#define PWR_PDCRB_PB1_Msk              (0x1UL << PWR_PDCRB_PB1_Pos)            /*!< 0x00000002 */
-#define PWR_PDCRB_PB1                  PWR_PDCRB_PB1_Msk                       /*!< Pin PB1 Pull-Down set */
-#define PWR_PDCRB_PB2_Pos              (2U)
-#define PWR_PDCRB_PB2_Msk              (0x1UL << PWR_PDCRB_PB2_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRB_PB2                  PWR_PDCRB_PB2_Msk                       /*!< Pin PB2 Pull-Down set */
-#define PWR_PDCRB_PB3_Pos              (3U)
-#define PWR_PDCRB_PB3_Msk              (0x1UL << PWR_PDCRB_PB3_Pos)            /*!< 0x00000008 */
-#define PWR_PDCRB_PB3                  PWR_PDCRB_PB3_Msk                       /*!< Pin PB3 Pull-Down set */
-#define PWR_PDCRB_PB4_Pos              (4U)
-#define PWR_PDCRB_PB4_Msk              (0x1UL << PWR_PDCRB_PB4_Pos)            /*!< 0x00000010 */
-#define PWR_PDCRB_PB4                  PWR_PDCRB_PB4_Msk                       /*!< Pin PB4 Pull-Down set */
-#define PWR_PDCRB_PB5_Pos              (5U)
-#define PWR_PDCRB_PB5_Msk              (0x1UL << PWR_PDCRB_PB5_Pos)            /*!< 0x00000020 */
-#define PWR_PDCRB_PB5                  PWR_PDCRB_PB5_Msk                       /*!< Pin PB5 Pull-Down set */
-#define PWR_PDCRB_PB6_Pos              (6U)
-#define PWR_PDCRB_PB6_Msk              (0x1UL << PWR_PDCRB_PB6_Pos)            /*!< 0x00000040 */
-#define PWR_PDCRB_PB6                  PWR_PDCRB_PB6_Msk                       /*!< Pin PB6 Pull-Down set */
-#define PWR_PDCRB_PB7_Pos              (7U)
-#define PWR_PDCRB_PB7_Msk              (0x1UL << PWR_PDCRB_PB7_Pos)            /*!< 0x00000080 */
-#define PWR_PDCRB_PB7                  PWR_PDCRB_PB7_Msk                       /*!< Pin PB7 Pull-Down set */
-#define PWR_PDCRB_PB8_Pos              (8U)
-#define PWR_PDCRB_PB8_Msk              (0x1UL << PWR_PDCRB_PB8_Pos)            /*!< 0x00000100 */
-#define PWR_PDCRB_PB8                  PWR_PDCRB_PB8_Msk                       /*!< Pin PB8 Pull-Down set */
-#define PWR_PDCRB_PB9_Pos              (9U)
-#define PWR_PDCRB_PB9_Msk              (0x1UL << PWR_PDCRB_PB9_Pos)            /*!< 0x00000200 */
-#define PWR_PDCRB_PB9                  PWR_PDCRB_PB9_Msk                       /*!< Pin PB9 Pull-Down set */
-#define PWR_PDCRB_PB10_Pos             (10U)
-#define PWR_PDCRB_PB10_Msk             (0x1UL << PWR_PDCRB_PB10_Pos)           /*!< 0x00000400 */
-#define PWR_PDCRB_PB10                 PWR_PDCRB_PB10_Msk                      /*!< Pin PB10 Pull-Down set */
-#define PWR_PDCRB_PB11_Pos             (11U)
-#define PWR_PDCRB_PB11_Msk             (0x1UL << PWR_PDCRB_PB11_Pos)           /*!< 0x00000800 */
-#define PWR_PDCRB_PB11                 PWR_PDCRB_PB11_Msk                      /*!< Pin PB11 Pull-Down set */
-#define PWR_PDCRB_PB12_Pos             (12U)
-#define PWR_PDCRB_PB12_Msk             (0x1UL << PWR_PDCRB_PB12_Pos)           /*!< 0x00001000 */
-#define PWR_PDCRB_PB12                 PWR_PDCRB_PB12_Msk                      /*!< Pin PB12 Pull-Down set */
-#define PWR_PDCRB_PB13_Pos             (13U)
-#define PWR_PDCRB_PB13_Msk             (0x1UL << PWR_PDCRB_PB13_Pos)           /*!< 0x00002000 */
-#define PWR_PDCRB_PB13                 PWR_PDCRB_PB13_Msk                      /*!< Pin PB13 Pull-Down set */
-#define PWR_PDCRB_PB14_Pos             (14U)
-#define PWR_PDCRB_PB14_Msk             (0x1UL << PWR_PDCRB_PB14_Pos)           /*!< 0x00004000 */
-#define PWR_PDCRB_PB14                 PWR_PDCRB_PB14_Msk                      /*!< Pin PB14 Pull-Down set */
-#define PWR_PDCRB_PB15_Pos             (15U)
-#define PWR_PDCRB_PB15_Msk             (0x1UL << PWR_PDCRB_PB15_Pos)           /*!< 0x00008000 */
-#define PWR_PDCRB_PB15                 PWR_PDCRB_PB15_Msk                      /*!< Pin PB15 Pull-Down set */
-
-/********************  Bit definition for PWR_PUCRC register  *****************/
-#define PWR_PUCRC_PC0_Pos              (0U)
-#define PWR_PUCRC_PC0_Msk              (0x1UL << PWR_PUCRC_PC0_Pos)            /*!< 0x00000001 */
-#define PWR_PUCRC_PC0                  PWR_PUCRC_PC0_Msk                       /*!< Pin PC0 Pull-Up set */
-#define PWR_PUCRC_PC1_Pos              (1U)
-#define PWR_PUCRC_PC1_Msk              (0x1UL << PWR_PUCRC_PC1_Pos)            /*!< 0x00000002 */
-#define PWR_PUCRC_PC1                  PWR_PUCRC_PC1_Msk                       /*!< Pin PC1 Pull-Up set */
-#define PWR_PUCRC_PC2_Pos              (2U)
-#define PWR_PUCRC_PC2_Msk              (0x1UL << PWR_PUCRC_PC2_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRC_PC2                  PWR_PUCRC_PC2_Msk                       /*!< Pin PC2 Pull-Up set */
-#define PWR_PUCRC_PC3_Pos              (3U)
-#define PWR_PUCRC_PC3_Msk              (0x1UL << PWR_PUCRC_PC3_Pos)            /*!< 0x00000008 */
-#define PWR_PUCRC_PC3                  PWR_PUCRC_PC3_Msk                       /*!< Pin PC3 Pull-Up set */
-#define PWR_PUCRC_PC4_Pos              (4U)
-#define PWR_PUCRC_PC4_Msk              (0x1UL << PWR_PUCRC_PC4_Pos)            /*!< 0x00000010 */
-#define PWR_PUCRC_PC4                  PWR_PUCRC_PC4_Msk                       /*!< Pin PC4 Pull-Up set */
-#define PWR_PUCRC_PC5_Pos              (5U)
-#define PWR_PUCRC_PC5_Msk              (0x1UL << PWR_PUCRC_PC5_Pos)            /*!< 0x00000020 */
-#define PWR_PUCRC_PC5                  PWR_PUCRC_PC5_Msk                       /*!< Pin PC5 Pull-Up set */
-#define PWR_PUCRC_PC6_Pos              (6U)
-#define PWR_PUCRC_PC6_Msk              (0x1UL << PWR_PUCRC_PC6_Pos)            /*!< 0x00000040 */
-#define PWR_PUCRC_PC6                  PWR_PUCRC_PC6_Msk                       /*!< Pin PC6 Pull-Up set */
-#define PWR_PUCRC_PC13_Pos             (13U)
-#define PWR_PUCRC_PC13_Msk             (0x1UL << PWR_PUCRC_PC13_Pos)           /*!< 0x00002000 */
-#define PWR_PUCRC_PC13                 PWR_PUCRC_PC13_Msk                      /*!< Pin PC13 Pull-Up set */
-#define PWR_PUCRC_PC14_Pos             (14U)
-#define PWR_PUCRC_PC14_Msk             (0x1UL << PWR_PUCRC_PC14_Pos)           /*!< 0x00004000 */
-#define PWR_PUCRC_PC14                 PWR_PUCRC_PC14_Msk                      /*!< Pin PC14 Pull-Up set */
-#define PWR_PUCRC_PC15_Pos             (15U)
-#define PWR_PUCRC_PC15_Msk             (0x1UL << PWR_PUCRC_PC15_Pos)           /*!< 0x00008000 */
-#define PWR_PUCRC_PC15                 PWR_PUCRC_PC15_Msk                      /*!< Pin PC15 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRC register  *****************/
-#define PWR_PDCRC_PC0_Pos              (0U)
-#define PWR_PDCRC_PC0_Msk              (0x1UL << PWR_PDCRC_PC0_Pos)            /*!< 0x00000001 */
-#define PWR_PDCRC_PC0                  PWR_PDCRC_PC0_Msk                       /*!< Pin PC0 Pull-Down set */
-#define PWR_PDCRC_PC1_Pos              (1U)
-#define PWR_PDCRC_PC1_Msk              (0x1UL << PWR_PDCRC_PC1_Pos)            /*!< 0x00000002 */
-#define PWR_PDCRC_PC1                  PWR_PDCRC_PC1_Msk                       /*!< Pin PC1 Pull-Down set */
-#define PWR_PDCRC_PC2_Pos              (2U)
-#define PWR_PDCRC_PC2_Msk              (0x1UL << PWR_PDCRC_PC2_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRC_PC2                  PWR_PDCRC_PC2_Msk                       /*!< Pin PC2 Pull-Down set */
-#define PWR_PDCRC_PC3_Pos              (3U)
-#define PWR_PDCRC_PC3_Msk              (0x1UL << PWR_PDCRC_PC3_Pos)            /*!< 0x00000008 */
-#define PWR_PDCRC_PC3                  PWR_PDCRC_PC3_Msk                       /*!< Pin PC3 Pull-Down set */
-#define PWR_PDCRC_PC4_Pos              (4U)
-#define PWR_PDCRC_PC4_Msk              (0x1UL << PWR_PDCRC_PC4_Pos)            /*!< 0x00000010 */
-#define PWR_PDCRC_PC4                  PWR_PDCRC_PC4_Msk                       /*!< Pin PC4 Pull-Down set */
-#define PWR_PDCRC_PC5_Pos              (5U)
-#define PWR_PDCRC_PC5_Msk              (0x1UL << PWR_PDCRC_PC5_Pos)            /*!< 0x00000020 */
-#define PWR_PDCRC_PC5                  PWR_PDCRC_PC5_Msk                       /*!< Pin PC5 Pull-Down set */
-#define PWR_PDCRC_PC6_Pos              (6U)
-#define PWR_PDCRC_PC6_Msk              (0x1UL << PWR_PDCRC_PC6_Pos)            /*!< 0x00000040 */
-#define PWR_PDCRC_PC6                  PWR_PDCRC_PC6_Msk                       /*!< Pin PC6 Pull-Down set */
-#define PWR_PDCRC_PC13_Pos             (13U)
-#define PWR_PDCRC_PC13_Msk             (0x1UL << PWR_PDCRC_PC13_Pos)           /*!< 0x00002000 */
-#define PWR_PDCRC_PC13                 PWR_PDCRC_PC13_Msk                      /*!< Pin PC13 Pull-Down set */
-#define PWR_PDCRC_PC14_Pos             (14U)
-#define PWR_PDCRC_PC14_Msk             (0x1UL << PWR_PDCRC_PC14_Pos)           /*!< 0x00004000 */
-#define PWR_PDCRC_PC14                 PWR_PDCRC_PC14_Msk                      /*!< Pin PC14 Pull-Down set */
-#define PWR_PDCRC_PC15_Pos             (15U)
-#define PWR_PDCRC_PC15_Msk             (0x1UL << PWR_PDCRC_PC15_Pos)           /*!< 0x00008000 */
-#define PWR_PDCRC_PC15                 PWR_PDCRC_PC15_Msk                      /*!< Pin PC15 Pull-Down set */
-
-/********************  Bit definition for PWR_PUCRH register  *****************/
-#define PWR_PUCRH_PH3_Pos              (3U)
-#define PWR_PUCRH_PH3_Msk              (0x1UL << PWR_PUCRH_PH3_Pos)            /*!< 0x00000004 */
-#define PWR_PUCRH_PH3                  PWR_PUCRH_PH3_Msk                       /*!< Pin PH3 Pull-Up set */
-
-/********************  Bit definition for PWR_PDCRH register  *****************/
-#define PWR_PDCRH_PH3_Pos              (3U)
-#define PWR_PDCRH_PH3_Msk              (0x1UL << PWR_PDCRH_PH3_Pos)            /*!< 0x00000004 */
-#define PWR_PDCRH_PH3                  PWR_PDCRH_PH3_Msk                       /*!< Pin PH3 Pull-Down set */
-
-/********************  Bit definition for PWR_EXTSCR register  ********************/
-#define PWR_EXTSCR_C1CSSF_Pos          (0U)
-#define PWR_EXTSCR_C1CSSF_Msk          (0x1UL << PWR_EXTSCR_C1CSSF_Pos)        /*!< 0x00000001 */
-#define PWR_EXTSCR_C1CSSF              PWR_EXTSCR_C1CSSF_Msk                   /*!< Clear standby and stop flags for CPU1 */
-
-#define PWR_EXTSCR_C1SBF_Pos           (8U)
-#define PWR_EXTSCR_C1SBF_Msk           (0x1UL << PWR_EXTSCR_C1SBF_Pos)         /*!< 0x00000100 */
-#define PWR_EXTSCR_C1SBF               PWR_EXTSCR_C1SBF_Msk                    /*!< System standby flag for CPU1 */
-#define PWR_EXTSCR_C1STOP2F_Pos        (9U)
-#define PWR_EXTSCR_C1STOP2F_Msk        (0x1UL << PWR_EXTSCR_C1STOP2F_Pos)      /*!< 0x00000200 */
-#define PWR_EXTSCR_C1STOP2F            PWR_EXTSCR_C1STOP2F_Msk                 /*!< System stop2 flag for CPU1 */
-#define PWR_EXTSCR_C1STOPF_Pos         (10U)
-#define PWR_EXTSCR_C1STOPF_Msk         (0x1UL << PWR_EXTSCR_C1STOPF_Pos)       /*!< 0x00000400 */
-#define PWR_EXTSCR_C1STOPF             PWR_EXTSCR_C1STOPF_Msk                  /*!< System stop0 or stop1 flag for CPU1 */
-
-#define PWR_EXTSCR_C1DS_Pos            (14U)
-#define PWR_EXTSCR_C1DS_Msk            (0x1UL << PWR_EXTSCR_C1DS_Pos)          /*!< 0x00004000 */
-#define PWR_EXTSCR_C1DS                PWR_EXTSCR_C1DS_Msk                     /*!< CPU1 deepsleep mode flag */
-
-/********************  Bit definition for PWR_SUBGHZSPICR register  ********************/
-#define PWR_SUBGHZSPICR_NSS_Pos         (15U)
-#define PWR_SUBGHZSPICR_NSS_Msk         (0x1UL << PWR_SUBGHZSPICR_NSS_Pos)       /*!< 0x00008000 */
-#define PWR_SUBGHZSPICR_NSS             PWR_SUBGHZSPICR_NSS_Msk                  /*!< Sub-GHz radio SUBGHZSPI_NSS control */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RCC_CR register  *****************/
-#define RCC_CR_MSION_Pos                     (0U)
-#define RCC_CR_MSION_Msk                     (0x1UL << RCC_CR_MSION_Pos)       /*!< 0x00000001 */
-#define RCC_CR_MSION                         RCC_CR_MSION_Msk                  /*!< Internal Multi Speed oscillator (MSI) clock enable */
-#define RCC_CR_MSIRDY_Pos                    (1U)
-#define RCC_CR_MSIRDY_Msk                    (0x1UL << RCC_CR_MSIRDY_Pos)      /*!< 0x00000002 */
-#define RCC_CR_MSIRDY                        RCC_CR_MSIRDY_Msk                 /*!< Internal Multi Speed oscillator (MSI) clock ready flag */
-#define RCC_CR_MSIPLLEN_Pos                  (2U)
-#define RCC_CR_MSIPLLEN_Msk                  (0x1UL << RCC_CR_MSIPLLEN_Pos)    /*!< 0x00000004 */
-#define RCC_CR_MSIPLLEN                      RCC_CR_MSIPLLEN_Msk               /*!< Internal Multi Speed oscillator (MSI) PLL enable */
-#define RCC_CR_MSIRGSEL_Pos                  (3U)
-#define RCC_CR_MSIRGSEL_Msk                  (0x1UL << RCC_CR_MSIRGSEL_Pos)    /*!< 0x00000008 */
-#define RCC_CR_MSIRGSEL                      RCC_CR_MSIRGSEL_Msk               /*!< Internal Multi Speed oscillator (MSI) range selection */
-
-/*!< MSIRANGE configuration : 12 frequency ranges available */
-#define RCC_CR_MSIRANGE_Pos                  (4U)
-#define RCC_CR_MSIRANGE_Msk                  (0xFUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000F0 */
-#define RCC_CR_MSIRANGE                      RCC_CR_MSIRANGE_Msk               /*!< Internal Multi Speed oscillator (MSI) clock Range */
-#define RCC_CR_MSIRANGE_0                    (0x0UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000000 */
-#define RCC_CR_MSIRANGE_1                    (0x1UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000010 */
-#define RCC_CR_MSIRANGE_2                    (0x2UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000020 */
-#define RCC_CR_MSIRANGE_3                    (0x3UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000030 */
-#define RCC_CR_MSIRANGE_4                    (0x4UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000040 */
-#define RCC_CR_MSIRANGE_5                    (0x5UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000050 */
-#define RCC_CR_MSIRANGE_6                    (0x6UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000060 */
-#define RCC_CR_MSIRANGE_7                    (0x7UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000070 */
-#define RCC_CR_MSIRANGE_8                    (0x8UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000080 */
-#define RCC_CR_MSIRANGE_9                    (0x9UL << RCC_CR_MSIRANGE_Pos)    /*!< 0x00000090 */
-#define RCC_CR_MSIRANGE_10                   (0xAUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000A0 */
-#define RCC_CR_MSIRANGE_11                   (0xBUL << RCC_CR_MSIRANGE_Pos)    /*!< 0x000000B0 */
-
-#define RCC_CR_HSION_Pos                     (8U)
-#define RCC_CR_HSION_Msk                     (0x1UL << RCC_CR_HSION_Pos)       /*!< 0x00000100 */
-#define RCC_CR_HSION                         RCC_CR_HSION_Msk                  /*!< Internal High Speed oscillator (HSI16) clock enable */
-#define RCC_CR_HSIKERON_Pos                  (9U)
-#define RCC_CR_HSIKERON_Msk                  (0x1UL << RCC_CR_HSIKERON_Pos)    /*!< 0x00000200 */
-#define RCC_CR_HSIKERON                      RCC_CR_HSIKERON_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY_Pos                    (10U)
-#define RCC_CR_HSIRDY_Msk                    (0x1UL << RCC_CR_HSIRDY_Pos)      /*!< 0x00000400 */
-#define RCC_CR_HSIRDY                        RCC_CR_HSIRDY_Msk                 /*!< Internal High Speed oscillator (HSI16) clock ready flag */
-#define RCC_CR_HSIASFS_Pos                   (11U)
-#define RCC_CR_HSIASFS_Msk                   (0x1UL << RCC_CR_HSIASFS_Pos)     /*!< 0x00000800 */
-#define RCC_CR_HSIASFS                       RCC_CR_HSIASFS_Msk                /*!< HSI16 Automatic Start from Stop */
-#define RCC_CR_HSIKERDY_Pos                  (12U)
-#define RCC_CR_HSIKERDY_Msk                  (0x1UL << RCC_CR_HSIKERDY_Pos)     /*!< 0x00001000 */
-#define RCC_CR_HSIKERDY                       RCC_CR_HSIKERDY_Msk               /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel ready flag*/
-
-#define RCC_CR_HSEON_Pos                     (16U)
-#define RCC_CR_HSEON_Msk                     (0x1UL << RCC_CR_HSEON_Pos)       /*!< 0x00010000 */
-#define RCC_CR_HSEON                         RCC_CR_HSEON_Msk                  /*!< External High Speed oscillator (HSE) clock enable */
-#define RCC_CR_HSERDY_Pos                    (17U)
-#define RCC_CR_HSERDY_Msk                    (0x1UL << RCC_CR_HSERDY_Pos)      /*!< 0x00020000 */
-#define RCC_CR_HSERDY                        RCC_CR_HSERDY_Msk                 /*!< External High Speed oscillator (HSE) clock ready */
-#define RCC_CR_CSSON_Pos                     (19U)
-#define RCC_CR_CSSON_Msk                     (0x1UL << RCC_CR_CSSON_Pos)       /*!< 0x00080000 */
-#define RCC_CR_CSSON                         RCC_CR_CSSON_Msk                  /*!< HSE Clock Security System enable */
-#define RCC_CR_HSEPRE_Pos                    (20U)
-#define RCC_CR_HSEPRE_Msk                    (0x1UL << RCC_CR_HSEPRE_Pos)       /*!< 0x00100000 */
-#define RCC_CR_HSEPRE                        RCC_CR_HSEPRE_Msk                  /*!< HSE sysclk prescaler */
-#define RCC_CR_HSEBYPPWR_Pos                 (21U)
-#define RCC_CR_HSEBYPPWR_Msk                 (0x1UL << RCC_CR_HSEBYPPWR_Pos)    /*!< 0x00200000 */
-#define RCC_CR_HSEBYPPWR                     RCC_CR_HSEBYPPWR_Msk               /*!< Enable HSE32 VDDTCXO */
-
-#define RCC_CR_PLLON_Pos                     (24U)
-#define RCC_CR_PLLON_Msk                     (0x1UL << RCC_CR_PLLON_Pos)       /*!< 0x01000000 */
-#define RCC_CR_PLLON                         RCC_CR_PLLON_Msk                  /*!< System PLL clock enable */
-#define RCC_CR_PLLRDY_Pos                    (25U)
-#define RCC_CR_PLLRDY_Msk                    (0x1UL << RCC_CR_PLLRDY_Pos)      /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                        RCC_CR_PLLRDY_Msk                 /*!< System PLL clock ready */
-
-/********************  Bit definition for RCC_ICSCR register  ***************/
-/*!< MSICAL configuration */
-#define RCC_ICSCR_MSICAL_Pos                 (0U)
-#define RCC_ICSCR_MSICAL_Msk                 (0xFFUL << RCC_ICSCR_MSICAL_Pos)  /*!< 0x000000FF */
-#define RCC_ICSCR_MSICAL                     RCC_ICSCR_MSICAL_Msk              /*!< MSICAL[7:0] bits */
-
-/*!< MSITRIM configuration */
-#define RCC_ICSCR_MSITRIM_Pos                (8U)
-#define RCC_ICSCR_MSITRIM_Msk                (0xFFUL << RCC_ICSCR_MSITRIM_Pos) /*!< 0x0000FF00 */
-#define RCC_ICSCR_MSITRIM                    RCC_ICSCR_MSITRIM_Msk             /*!< MSITRIM[7:0] bits */
-
-/*!< HSICAL configuration */
-#define RCC_ICSCR_HSICAL_Pos                 (16U)
-#define RCC_ICSCR_HSICAL_Msk                 (0xFFUL << RCC_ICSCR_HSICAL_Pos)  /*!< 0x00FF0000 */
-#define RCC_ICSCR_HSICAL                     RCC_ICSCR_HSICAL_Msk              /*!< HSICAL[7:0] bits */
-
-/*!< HSITRIM configuration */
-#define RCC_ICSCR_HSITRIM_Pos                (24U)
-#define RCC_ICSCR_HSITRIM_Msk                (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
-#define RCC_ICSCR_HSITRIM                    RCC_ICSCR_HSITRIM_Msk             /*!< HSITRIM[6:0] bits */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                      (0U)
-#define RCC_CFGR_SW_Msk                      (0x3UL << RCC_CFGR_SW_Pos)        /*!< 0x00000003 */
-#define RCC_CFGR_SW                          RCC_CFGR_SW_Msk                   /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                        (0x1UL << RCC_CFGR_SW_Pos)        /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                        (0x2UL << RCC_CFGR_SW_Pos)        /*!< 0x00000002 */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                     (2U)
-#define RCC_CFGR_SWS_Msk                     (0x3UL << RCC_CFGR_SWS_Pos)       /*!< 0x0000000C */
-#define RCC_CFGR_SWS                         RCC_CFGR_SWS_Msk                  /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                       (0x1UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                       (0x2UL << RCC_CFGR_SWS_Pos)       /*!< 0x00000008 */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                    (4U)
-#define RCC_CFGR_HPRE_Msk                    (0xFUL << RCC_CFGR_HPRE_Pos)      /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                        RCC_CFGR_HPRE_Msk                 /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                      (0x1UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                      (0x2UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                      (0x4UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                      (0x8UL << RCC_CFGR_HPRE_Pos)      /*!< 0x00000080 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                   (8U)
-#define RCC_CFGR_PPRE1_Msk                   (0x7UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000700 */
-#define RCC_CFGR_PPRE1                       RCC_CFGR_PPRE1_Msk                /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                     (0x1UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000100 */
-#define RCC_CFGR_PPRE1_1                     (0x2UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000200 */
-#define RCC_CFGR_PPRE1_2                     (0x4UL << RCC_CFGR_PPRE1_Pos)     /*!< 0x00000400 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                   (11U)
-#define RCC_CFGR_PPRE2_Msk                   (0x7UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00003800 */
-#define RCC_CFGR_PPRE2                       RCC_CFGR_PPRE2_Msk                /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                     (0x1UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00000800 */
-#define RCC_CFGR_PPRE2_1                     (0x2UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00001000 */
-#define RCC_CFGR_PPRE2_2                     (0x4UL << RCC_CFGR_PPRE2_Pos)     /*!< 0x00002000 */
-
-/*!< STOPWUCK configuration */
-#define RCC_CFGR_STOPWUCK_Pos                (15U)
-#define RCC_CFGR_STOPWUCK_Msk                (0x1UL << RCC_CFGR_STOPWUCK_Pos)  /*!< 0x00008000 */
-#define RCC_CFGR_STOPWUCK                    RCC_CFGR_STOPWUCK_Msk             /*!< Wake Up from stop and CSS backup clock selection */
-
-/*!< HPREF configuration */
-#define RCC_CFGR_HPREF_Pos                   (16U)
-#define RCC_CFGR_HPREF_Msk                   (0x1UL << RCC_CFGR_HPREF_Pos)     /*!< 0x00010000 */
-#define RCC_CFGR_HPREF                       RCC_CFGR_HPREF_Msk                /*!< AHB prescaler flag */
-
-/*!< PPRE1F configuration */
-#define RCC_CFGR_PPRE1F_Pos                  (17U)
-#define RCC_CFGR_PPRE1F_Msk                  (0x1UL << RCC_CFGR_PPRE1F_Pos)    /*!< 0x00020000 */
-#define RCC_CFGR_PPRE1F                      RCC_CFGR_PPRE1F_Msk               /*!< CPU1 APB1 prescaler flag */
-
-/*!< PPRE2F configuration */
-#define RCC_CFGR_PPRE2F_Pos                  (18U)
-#define RCC_CFGR_PPRE2F_Msk                  (0x1UL << RCC_CFGR_PPRE2F_Pos)    /*!< 0x00040000 */
-#define RCC_CFGR_PPRE2F                      RCC_CFGR_PPRE2F_Msk               /*!< APB2 prescaler flag */
-
-/*!< MCOSEL configuration */
-#define RCC_CFGR_MCOSEL_Pos                  (24U)
-#define RCC_CFGR_MCOSEL_Msk                  (0xFUL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x0F000000 */
-#define RCC_CFGR_MCOSEL                      RCC_CFGR_MCOSEL_Msk               /*!< MCOSEL [3:0] bits (Clock output selection) */
-#define RCC_CFGR_MCOSEL_0                    (0x1UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x01000000 */
-#define RCC_CFGR_MCOSEL_1                    (0x2UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x02000000 */
-#define RCC_CFGR_MCOSEL_2                    (0x4UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x04000000 */
-#define RCC_CFGR_MCOSEL_3                    (0x8UL << RCC_CFGR_MCOSEL_Pos)    /*!< 0x08000000 */
-
-/*!< MCOPRE configuration */
-#define RCC_CFGR_MCOPRE_Pos                  (28U)
-#define RCC_CFGR_MCOPRE_Msk                  (0x7UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x70000000 */
-#define RCC_CFGR_MCOPRE                      RCC_CFGR_MCOPRE_Msk               /*!< MCO prescaler */
-#define RCC_CFGR_MCOPRE_0                    (0x1UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x10000000 */
-#define RCC_CFGR_MCOPRE_1                    (0x2UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x20000000 */
-#define RCC_CFGR_MCOPRE_2                    (0x4UL << RCC_CFGR_MCOPRE_Pos)    /*!< 0x40000000 */
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define RCC_PLLCFGR_PLLSRC_Pos               (0U)
-#define RCC_PLLCFGR_PLLSRC_Msk               (0x3UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000003 */
-#define RCC_PLLCFGR_PLLSRC                   RCC_PLLCFGR_PLLSRC_Msk
-#define RCC_PLLCFGR_PLLSRC_0                 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000001 */
-#define RCC_PLLCFGR_PLLSRC_1                 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos)/*!< 0x00000002 */
-
-#define RCC_PLLCFGR_PLLM_Pos                 (4U)
-#define RCC_PLLCFGR_PLLM_Msk                 (0x7UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000070 */
-#define RCC_PLLCFGR_PLLM                     RCC_PLLCFGR_PLLM_Msk
-#define RCC_PLLCFGR_PLLM_0                   (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
-#define RCC_PLLCFGR_PLLM_1                   (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
-#define RCC_PLLCFGR_PLLM_2                   (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
-
-#define RCC_PLLCFGR_PLLN_Pos                 (8U)
-#define RCC_PLLCFGR_PLLN_Msk                 (0x7FUL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00007F00 */
-#define RCC_PLLCFGR_PLLN                     RCC_PLLCFGR_PLLN_Msk
-#define RCC_PLLCFGR_PLLN_0                   (0x01UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000100 */
-#define RCC_PLLCFGR_PLLN_1                   (0x02UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000200 */
-#define RCC_PLLCFGR_PLLN_2                   (0x04UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000400 */
-#define RCC_PLLCFGR_PLLN_3                   (0x08UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00000800 */
-#define RCC_PLLCFGR_PLLN_4                   (0x10UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00001000 */
-#define RCC_PLLCFGR_PLLN_5                   (0x20UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00002000 */
-#define RCC_PLLCFGR_PLLN_6                   (0x40UL << RCC_PLLCFGR_PLLN_Pos)/*!< 0x00004000 */
-
-#define RCC_PLLCFGR_PLLPEN_Pos               (16U)
-#define RCC_PLLCFGR_PLLPEN_Msk               (0x1UL << RCC_PLLCFGR_PLLPEN_Pos)/*!< 0x00010000 */
-#define RCC_PLLCFGR_PLLPEN                   RCC_PLLCFGR_PLLPEN_Msk
-#define RCC_PLLCFGR_PLLP_Pos                 (17U)
-#define RCC_PLLCFGR_PLLP_Msk                 (0x1FUL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x003E0000 */
-#define RCC_PLLCFGR_PLLP                     RCC_PLLCFGR_PLLP_Msk
-#define RCC_PLLCFGR_PLLP_0                   (0x01UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00020000 */
-#define RCC_PLLCFGR_PLLP_1                   (0x02UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00040000 */
-#define RCC_PLLCFGR_PLLP_2                   (0x04UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00080000 */
-#define RCC_PLLCFGR_PLLP_3                   (0x08UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00100000 */
-#define RCC_PLLCFGR_PLLP_4                   (0x10UL << RCC_PLLCFGR_PLLP_Pos)/*!< 0x00200000 */
-
-#define RCC_PLLCFGR_PLLQEN_Pos               (24U)
-#define RCC_PLLCFGR_PLLQEN_Msk               (0x1UL << RCC_PLLCFGR_PLLQEN_Pos)/*!< 0x01000000 */
-#define RCC_PLLCFGR_PLLQEN                   RCC_PLLCFGR_PLLQEN_Msk
-#define RCC_PLLCFGR_PLLQ_Pos                 (25U)
-#define RCC_PLLCFGR_PLLQ_Msk                 (0x7UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x0E000000 */
-#define RCC_PLLCFGR_PLLQ                     RCC_PLLCFGR_PLLQ_Msk
-#define RCC_PLLCFGR_PLLQ_0                   (0x1UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x02000000 */
-#define RCC_PLLCFGR_PLLQ_1                   (0x2UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x04000000 */
-#define RCC_PLLCFGR_PLLQ_2                   (0x4UL << RCC_PLLCFGR_PLLQ_Pos)/*!< 0x08000000 */
-
-#define RCC_PLLCFGR_PLLREN_Pos               (28U)
-#define RCC_PLLCFGR_PLLREN_Msk               (0x1UL << RCC_PLLCFGR_PLLREN_Pos)/*!< 0x10000000 */
-#define RCC_PLLCFGR_PLLREN                   RCC_PLLCFGR_PLLREN_Msk
-#define RCC_PLLCFGR_PLLR_Pos                 (29U)
-#define RCC_PLLCFGR_PLLR_Msk                 (0x7UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0xE0000000 */
-#define RCC_PLLCFGR_PLLR                     RCC_PLLCFGR_PLLR_Msk
-#define RCC_PLLCFGR_PLLR_0                   (0x1UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x20000000 */
-#define RCC_PLLCFGR_PLLR_1                   (0x2UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x40000000 */
-#define RCC_PLLCFGR_PLLR_2                   (0x4UL << RCC_PLLCFGR_PLLR_Pos)/*!< 0x80000000 */
-
-
-/********************  Bit definition for RCC_CIER register  ******************/
-#define RCC_CIER_LSIRDYIE_Pos                (0U)
-#define RCC_CIER_LSIRDYIE_Msk                (0x1UL << RCC_CIER_LSIRDYIE_Pos)  /*!< 0x00000001 */
-#define RCC_CIER_LSIRDYIE                    RCC_CIER_LSIRDYIE_Msk
-#define RCC_CIER_LSERDYIE_Pos                (1U)
-#define RCC_CIER_LSERDYIE_Msk                (0x1UL << RCC_CIER_LSERDYIE_Pos)   /*!< 0x00000002 */
-#define RCC_CIER_LSERDYIE                    RCC_CIER_LSERDYIE_Msk
-#define RCC_CIER_MSIRDYIE_Pos                (2U)
-#define RCC_CIER_MSIRDYIE_Msk                (0x1UL << RCC_CIER_MSIRDYIE_Pos)   /*!< 0x00000004 */
-#define RCC_CIER_MSIRDYIE                    RCC_CIER_MSIRDYIE_Msk
-#define RCC_CIER_HSIRDYIE_Pos                (3U)
-#define RCC_CIER_HSIRDYIE_Msk                (0x1UL << RCC_CIER_HSIRDYIE_Pos)   /*!< 0x00000008 */
-#define RCC_CIER_HSIRDYIE                    RCC_CIER_HSIRDYIE_Msk
-#define RCC_CIER_HSERDYIE_Pos                (4U)
-#define RCC_CIER_HSERDYIE_Msk                (0x1UL << RCC_CIER_HSERDYIE_Pos)   /*!< 0x00000010 */
-#define RCC_CIER_HSERDYIE                    RCC_CIER_HSERDYIE_Msk
-#define RCC_CIER_PLLRDYIE_Pos                (5U)
-#define RCC_CIER_PLLRDYIE_Msk                (0x1UL << RCC_CIER_PLLRDYIE_Pos)/*!< 0x00000020 */
-#define RCC_CIER_PLLRDYIE                    RCC_CIER_PLLRDYIE_Msk
-#define RCC_CIER_LSECSSIE_Pos                (9U)
-#define RCC_CIER_LSECSSIE_Msk                (0x1UL << RCC_CIER_LSECSSIE_Pos)   /*!< 0x00000200 */
-#define RCC_CIER_LSECSSIE                    RCC_CIER_LSECSSIE_Msk
-
-/********************  Bit definition for RCC_CIFR register  ******************/
-#define RCC_CIFR_LSIRDYF_Pos                 (0U)
-#define RCC_CIFR_LSIRDYF_Msk                 (0x1UL << RCC_CIFR_LSIRDYF_Pos)  /*!< 0x00000001 */
-#define RCC_CIFR_LSIRDYF                     RCC_CIFR_LSIRDYF_Msk
-#define RCC_CIFR_LSERDYF_Pos                 (1U)
-#define RCC_CIFR_LSERDYF_Msk                 (0x1UL << RCC_CIFR_LSERDYF_Pos)   /*!< 0x00000002 */
-#define RCC_CIFR_LSERDYF                     RCC_CIFR_LSERDYF_Msk
-#define RCC_CIFR_MSIRDYF_Pos                 (2U)
-#define RCC_CIFR_MSIRDYF_Msk                 (0x1UL << RCC_CIFR_MSIRDYF_Pos)   /*!< 0x00000004 */
-#define RCC_CIFR_MSIRDYF                     RCC_CIFR_MSIRDYF_Msk
-#define RCC_CIFR_HSIRDYF_Pos                 (3U)
-#define RCC_CIFR_HSIRDYF_Msk                 (0x1UL << RCC_CIFR_HSIRDYF_Pos)   /*!< 0x00000008 */
-#define RCC_CIFR_HSIRDYF                     RCC_CIFR_HSIRDYF_Msk
-#define RCC_CIFR_HSERDYF_Pos                 (4U)
-#define RCC_CIFR_HSERDYF_Msk                 (0x1UL << RCC_CIFR_HSERDYF_Pos)   /*!< 0x00000010 */
-#define RCC_CIFR_HSERDYF                     RCC_CIFR_HSERDYF_Msk
-#define RCC_CIFR_PLLRDYF_Pos                 (5U)
-#define RCC_CIFR_PLLRDYF_Msk                 (0x1UL << RCC_CIFR_PLLRDYF_Pos)/*!< 0x00000020 */
-#define RCC_CIFR_PLLRDYF                     RCC_CIFR_PLLRDYF_Msk
-#define RCC_CIFR_CSSF_Pos                    (8U)
-#define RCC_CIFR_CSSF_Msk                    (0x1UL << RCC_CIFR_CSSF_Pos)   /*!< 0x00000100 */
-#define RCC_CIFR_CSSF                        RCC_CIFR_CSSF_Msk
-#define RCC_CIFR_LSECSSF_Pos                 (9U)
-#define RCC_CIFR_LSECSSF_Msk                 (0x1UL << RCC_CIFR_LSECSSF_Pos)   /*!< 0x00000200 */
-#define RCC_CIFR_LSECSSF                     RCC_CIFR_LSECSSF_Msk
-
-/********************  Bit definition for RCC_CICR register  ******************/
-#define RCC_CICR_LSIRDYC_Pos                (0U)
-#define RCC_CICR_LSIRDYC_Msk                (0x1UL << RCC_CICR_LSIRDYC_Pos)  /*!< 0x00000001 */
-#define RCC_CICR_LSIRDYC                    RCC_CICR_LSIRDYC_Msk
-#define RCC_CICR_LSERDYC_Pos                (1U)
-#define RCC_CICR_LSERDYC_Msk                (0x1UL << RCC_CICR_LSERDYC_Pos)   /*!< 0x00000002 */
-#define RCC_CICR_LSERDYC                    RCC_CICR_LSERDYC_Msk
-#define RCC_CICR_MSIRDYC_Pos                (2U)
-#define RCC_CICR_MSIRDYC_Msk                (0x1UL << RCC_CICR_MSIRDYC_Pos)   /*!< 0x00000004 */
-#define RCC_CICR_MSIRDYC                    RCC_CICR_MSIRDYC_Msk
-#define RCC_CICR_HSIRDYC_Pos                (3U)
-#define RCC_CICR_HSIRDYC_Msk                (0x1UL << RCC_CICR_HSIRDYC_Pos)   /*!< 0x00000008 */
-#define RCC_CICR_HSIRDYC                    RCC_CICR_HSIRDYC_Msk
-#define RCC_CICR_HSERDYC_Pos                (4U)
-#define RCC_CICR_HSERDYC_Msk                (0x1UL << RCC_CICR_HSERDYC_Pos)   /*!< 0x00000010 */
-#define RCC_CICR_HSERDYC                    RCC_CICR_HSERDYC_Msk
-#define RCC_CICR_PLLRDYC_Pos                (5U)
-#define RCC_CICR_PLLRDYC_Msk                (0x1UL << RCC_CICR_PLLRDYC_Pos)/*!< 0x00000020 */
-#define RCC_CICR_PLLRDYC                    RCC_CICR_PLLRDYC_Msk
-#define RCC_CICR_CSSC_Pos                   (8U)
-#define RCC_CICR_CSSC_Msk                   (0x1UL << RCC_CICR_CSSC_Pos)   /*!< 0x00000100 */
-#define RCC_CICR_CSSC                       RCC_CICR_CSSC_Msk
-#define RCC_CICR_LSECSSC_Pos                (9U)
-#define RCC_CICR_LSECSSC_Msk                (0x1UL << RCC_CICR_LSECSSC_Pos)   /*!< 0x00000200 */
-#define RCC_CICR_LSECSSC                    RCC_CICR_LSECSSC_Msk
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define RCC_AHB1RSTR_DMA1RST_Pos             (0U)
-#define RCC_AHB1RSTR_DMA1RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
-#define RCC_AHB1RSTR_DMA1RST                 RCC_AHB1RSTR_DMA1RST_Msk
-#define RCC_AHB1RSTR_DMA2RST_Pos             (1U)
-#define RCC_AHB1RSTR_DMA2RST_Msk             (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
-#define RCC_AHB1RSTR_DMA2RST                 RCC_AHB1RSTR_DMA2RST_Msk
-#define RCC_AHB1RSTR_DMAMUX1RST_Pos          (2U)
-#define RCC_AHB1RSTR_DMAMUX1RST_Msk          (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
-#define RCC_AHB1RSTR_DMAMUX1RST              RCC_AHB1RSTR_DMAMUX1RST_Msk
-#define RCC_AHB1RSTR_CRCRST_Pos              (12U)
-#define RCC_AHB1RSTR_CRCRST_Msk              (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
-#define RCC_AHB1RSTR_CRCRST                  RCC_AHB1RSTR_CRCRST_Msk
-
-/********************  Bit definition for RCC_AHB2RSTR register  ***************/
-#define RCC_AHB2RSTR_GPIOARST_Pos           (0U)
-#define RCC_AHB2RSTR_GPIOARST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
-#define RCC_AHB2RSTR_GPIOARST               RCC_AHB2RSTR_GPIOARST_Msk
-#define RCC_AHB2RSTR_GPIOBRST_Pos           (1U)
-#define RCC_AHB2RSTR_GPIOBRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
-#define RCC_AHB2RSTR_GPIOBRST               RCC_AHB2RSTR_GPIOBRST_Msk
-#define RCC_AHB2RSTR_GPIOCRST_Pos           (2U)
-#define RCC_AHB2RSTR_GPIOCRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
-#define RCC_AHB2RSTR_GPIOCRST               RCC_AHB2RSTR_GPIOCRST_Msk
-#define RCC_AHB2RSTR_GPIOHRST_Pos           (7U)
-#define RCC_AHB2RSTR_GPIOHRST_Msk           (0x1UL << RCC_AHB2RSTR_GPIOHRST_Pos)/*!< 0x00000080 */
-#define RCC_AHB2RSTR_GPIOHRST               RCC_AHB2RSTR_GPIOHRST_Msk
-
-/********************  Bit definition for RCC_AHB3RSTR register  ***************/
-#define RCC_AHB3RSTR_PKARST_Pos             (16U)
-#define RCC_AHB3RSTR_PKARST_Msk             (0x1UL << RCC_AHB3RSTR_PKARST_Pos) /*!< 0x00010000 */
-#define RCC_AHB3RSTR_PKARST                 RCC_AHB3RSTR_PKARST_Msk
-#define RCC_AHB3RSTR_AESRST_Pos             (17U)
-#define RCC_AHB3RSTR_AESRST_Msk             (0x1UL << RCC_AHB3RSTR_AESRST_Pos)/*!< 0x00020000 */
-#define RCC_AHB3RSTR_AESRST                 RCC_AHB3RSTR_AESRST_Msk
-#define RCC_AHB3RSTR_RNGRST_Pos             (18U)
-#define RCC_AHB3RSTR_RNGRST_Msk             (0x1UL << RCC_AHB3RSTR_RNGRST_Pos)/*!< 0x00040000 */
-#define RCC_AHB3RSTR_RNGRST                 RCC_AHB3RSTR_RNGRST_Msk
-
-#define RCC_AHB3RSTR_HSEMRST_Pos            (19U)
-#define RCC_AHB3RSTR_HSEMRST_Msk            (0x1UL << RCC_AHB3RSTR_HSEMRST_Pos)/*!< 0x00080000 */
-#define RCC_AHB3RSTR_HSEMRST                RCC_AHB3RSTR_HSEMRST_Msk
-#define RCC_AHB3RSTR_FLASHRST_Pos           (25U)
-#define RCC_AHB3RSTR_FLASHRST_Msk           (0x1UL << RCC_AHB3RSTR_FLASHRST_Pos) /*!< 0x02000000 */
-#define RCC_AHB3RSTR_FLASHRST               RCC_AHB3RSTR_FLASHRST_Msk
-
-/********************  Bit definition for RCC_APB1RSTR1 register  **************/
-#define RCC_APB1RSTR1_TIM2RST_Pos           (0U)
-#define RCC_APB1RSTR1_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
-#define RCC_APB1RSTR1_TIM2RST               RCC_APB1RSTR1_TIM2RST_Msk
-#define RCC_APB1RSTR1_SPI2RST_Pos           (14U)
-#define RCC_APB1RSTR1_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
-#define RCC_APB1RSTR1_SPI2RST               RCC_APB1RSTR1_SPI2RST_Msk
-#define RCC_APB1RSTR1_USART2RST_Pos         (17U)
-#define RCC_APB1RSTR1_USART2RST_Msk         (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
-#define RCC_APB1RSTR1_USART2RST             RCC_APB1RSTR1_USART2RST_Msk
-#define RCC_APB1RSTR1_I2C1RST_Pos           (21U)
-#define RCC_APB1RSTR1_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
-#define RCC_APB1RSTR1_I2C1RST               RCC_APB1RSTR1_I2C1RST_Msk
-#define RCC_APB1RSTR1_I2C2RST_Pos           (22U)
-#define RCC_APB1RSTR1_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
-#define RCC_APB1RSTR1_I2C2RST               RCC_APB1RSTR1_I2C2RST_Msk
-#define RCC_APB1RSTR1_I2C3RST_Pos           (23U)
-#define RCC_APB1RSTR1_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x00800000 */
-#define RCC_APB1RSTR1_I2C3RST               RCC_APB1RSTR1_I2C3RST_Msk
-#define RCC_APB1RSTR1_DACRST_Pos            (29U)
-#define RCC_APB1RSTR1_DACRST_Msk            (0x1UL << RCC_APB1RSTR1_DACRST_Pos)/*!< 0x20000000 */
-#define RCC_APB1RSTR1_DACRST                RCC_APB1RSTR1_DACRST_Msk
-#define RCC_APB1RSTR1_LPTIM1RST_Pos         (31U)
-#define RCC_APB1RSTR1_LPTIM1RST_Msk         (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
-#define RCC_APB1RSTR1_LPTIM1RST             RCC_APB1RSTR1_LPTIM1RST_Msk
-
-/********************  Bit definition for RCC_APB1RSTR2 register  **************/
-#define RCC_APB1RSTR2_LPUART1RST_Pos        (0U)
-#define RCC_APB1RSTR2_LPUART1RST_Msk        (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
-#define RCC_APB1RSTR2_LPUART1RST            RCC_APB1RSTR2_LPUART1RST_Msk
-#define RCC_APB1RSTR2_LPTIM2RST_Pos         (5U)
-#define RCC_APB1RSTR2_LPTIM2RST_Msk         (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos)/*!< 0x00000020 */
-#define RCC_APB1RSTR2_LPTIM2RST             RCC_APB1RSTR2_LPTIM2RST_Msk
-#define RCC_APB1RSTR2_LPTIM3RST_Pos         (6U)
-#define RCC_APB1RSTR2_LPTIM3RST_Msk         (0x1UL << RCC_APB1RSTR2_LPTIM3RST_Pos)/*!< 0x00000040 */
-#define RCC_APB1RSTR2_LPTIM3RST             RCC_APB1RSTR2_LPTIM3RST_Msk
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define RCC_APB2RSTR_ADCRST_Pos             (9U)
-#define RCC_APB2RSTR_ADCRST_Msk             (0x1UL << RCC_APB2RSTR_ADCRST_Pos)/*!< 0x00000200 */
-#define RCC_APB2RSTR_ADCRST                 RCC_APB2RSTR_ADCRST_Msk
-#define RCC_APB2RSTR_TIM1RST_Pos            (11U)
-#define RCC_APB2RSTR_TIM1RST_Msk            (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
-#define RCC_APB2RSTR_TIM1RST                RCC_APB2RSTR_TIM1RST_Msk
-#define RCC_APB2RSTR_SPI1RST_Pos            (12U)
-#define RCC_APB2RSTR_SPI1RST_Msk            (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk
-#define RCC_APB2RSTR_USART1RST_Pos          (14U)
-#define RCC_APB2RSTR_USART1RST_Msk          (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
-#define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk
-#define RCC_APB2RSTR_TIM16RST_Pos           (17U)
-#define RCC_APB2RSTR_TIM16RST_Msk           (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
-#define RCC_APB2RSTR_TIM16RST               RCC_APB2RSTR_TIM16RST_Msk
-#define RCC_APB2RSTR_TIM17RST_Pos           (18U)
-#define RCC_APB2RSTR_TIM17RST_Msk           (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
-#define RCC_APB2RSTR_TIM17RST               RCC_APB2RSTR_TIM17RST_Msk
-
-/********************  Bit definition for RCC_APB3RSTR register  **************/
-#define RCC_APB3RSTR_SUBGHZSPIRST_Pos            (0U)
-#define RCC_APB3RSTR_SUBGHZSPIRST_Msk            (0x1UL << RCC_APB3RSTR_SUBGHZSPIRST_Pos) /*!< 0x00000001 */
-#define RCC_APB3RSTR_SUBGHZSPIRST                RCC_APB3RSTR_SUBGHZSPIRST_Msk
-
-/********************  Bit definition for RCC_AHB1ENR register  ****************/
-#define RCC_AHB1ENR_DMA1EN_Pos              (0U)
-#define RCC_AHB1ENR_DMA1EN_Msk              (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)  /*!< 0x00000001 */
-#define RCC_AHB1ENR_DMA1EN                  RCC_AHB1ENR_DMA1EN_Msk
-#define RCC_AHB1ENR_DMA2EN_Pos              (1U)
-#define RCC_AHB1ENR_DMA2EN_Msk              (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)  /*!< 0x00000002 */
-#define RCC_AHB1ENR_DMA2EN                  RCC_AHB1ENR_DMA2EN_Msk
-#define RCC_AHB1ENR_DMAMUX1EN_Pos           (2U)
-#define RCC_AHB1ENR_DMAMUX1EN_Msk           (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
-#define RCC_AHB1ENR_DMAMUX1EN               RCC_AHB1ENR_DMAMUX1EN_Msk
-#define RCC_AHB1ENR_CRCEN_Pos               (12U)
-#define RCC_AHB1ENR_CRCEN_Msk               (0x1UL << RCC_AHB1ENR_CRCEN_Pos)   /*!< 0x00001000 */
-#define RCC_AHB1ENR_CRCEN                   RCC_AHB1ENR_CRCEN_Msk
-
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-#define RCC_AHB2ENR_GPIOAEN_Pos             (0U)
-#define RCC_AHB2ENR_GPIOAEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos) /*!< 0x00000001 */
-#define RCC_AHB2ENR_GPIOAEN                 RCC_AHB2ENR_GPIOAEN_Msk
-#define RCC_AHB2ENR_GPIOBEN_Pos             (1U)
-#define RCC_AHB2ENR_GPIOBEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos) /*!< 0x00000002 */
-#define RCC_AHB2ENR_GPIOBEN                 RCC_AHB2ENR_GPIOBEN_Msk
-#define RCC_AHB2ENR_GPIOCEN_Pos             (2U)
-#define RCC_AHB2ENR_GPIOCEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos) /*!< 0x00000004 */
-#define RCC_AHB2ENR_GPIOCEN                 RCC_AHB2ENR_GPIOCEN_Msk
-#define RCC_AHB2ENR_GPIOHEN_Pos             (7U)
-#define RCC_AHB2ENR_GPIOHEN_Msk             (0x1UL << RCC_AHB2ENR_GPIOHEN_Pos) /*!< 0x00000080 */
-#define RCC_AHB2ENR_GPIOHEN                 RCC_AHB2ENR_GPIOHEN_Msk
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-#define RCC_AHB3ENR_PKAEN_Pos               (16U)
-#define RCC_AHB3ENR_PKAEN_Msk               (0x1UL << RCC_AHB3ENR_PKAEN_Pos)   /*!< 0x00010000 */
-#define RCC_AHB3ENR_PKAEN                   RCC_AHB3ENR_PKAEN_Msk
-#define RCC_AHB3ENR_AESEN_Pos               (17U)
-#define RCC_AHB3ENR_AESEN_Msk               (0x1UL << RCC_AHB3ENR_AESEN_Pos)/*!< 0x00020000 */
-#define RCC_AHB3ENR_AESEN                   RCC_AHB3ENR_AESEN_Msk
-#define RCC_AHB3ENR_RNGEN_Pos               (18U)
-#define RCC_AHB3ENR_RNGEN_Msk               (0x1UL << RCC_AHB3ENR_RNGEN_Pos)  /*!< 0x00040000 */
-#define RCC_AHB3ENR_RNGEN                   RCC_AHB3ENR_RNGEN_Msk
-#define RCC_AHB3ENR_HSEMEN_Pos              (19U)
-#define RCC_AHB3ENR_HSEMEN_Msk              (0x1UL << RCC_AHB3ENR_HSEMEN_Pos)  /*!< 0x00080000 */
-#define RCC_AHB3ENR_HSEMEN                  RCC_AHB3ENR_HSEMEN_Msk
-#define RCC_AHB3ENR_FLASHEN_Pos             (25U)
-#define RCC_AHB3ENR_FLASHEN_Msk             (0x1UL << RCC_AHB3ENR_FLASHEN_Pos)   /*!< 0x02000000 */
-#define RCC_AHB3ENR_FLASHEN                 RCC_AHB3ENR_FLASHEN_Msk
-
-/********************  Bit definition for RCC_APB1ENR1 register  **************/
-#define RCC_APB1ENR1_TIM2EN_Pos             (0U)
-#define RCC_APB1ENR1_TIM2EN_Msk             (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) /*!< 0x00000001 */
-#define RCC_APB1ENR1_TIM2EN                 RCC_APB1ENR1_TIM2EN_Msk
-#define RCC_APB1ENR1_RTCAPBEN_Pos           (10U)
-#define RCC_APB1ENR1_RTCAPBEN_Msk           (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
-#define RCC_APB1ENR1_RTCAPBEN               RCC_APB1ENR1_RTCAPBEN_Msk
-#define RCC_APB1ENR1_WWDGEN_Pos             (11U)
-#define RCC_APB1ENR1_WWDGEN_Msk             (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1ENR1_WWDGEN                 RCC_APB1ENR1_WWDGEN_Msk
-#define RCC_APB1ENR1_SPI2EN_Pos             (14U)
-#define RCC_APB1ENR1_SPI2EN_Msk             (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) /*!< 0x00004000 */
-#define RCC_APB1ENR1_SPI2EN                 RCC_APB1ENR1_SPI2EN_Msk
-#define RCC_APB1ENR1_USART2EN_Pos           (17U)
-#define RCC_APB1ENR1_USART2EN_Msk           (0x1UL << RCC_APB1ENR1_USART2EN_Pos) /*!< 0x00020000 */
-#define RCC_APB1ENR1_USART2EN               RCC_APB1ENR1_USART2EN_Msk
-#define RCC_APB1ENR1_I2C1EN_Pos             (21U)
-#define RCC_APB1ENR1_I2C1EN_Msk             (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) /*!< 0x00200000 */
-#define RCC_APB1ENR1_I2C1EN                 RCC_APB1ENR1_I2C1EN_Msk
-#define RCC_APB1ENR1_I2C2EN_Pos             (22U)
-#define RCC_APB1ENR1_I2C2EN_Msk             (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) /*!< 0x00400000 */
-#define RCC_APB1ENR1_I2C2EN                 RCC_APB1ENR1_I2C2EN_Msk
-#define RCC_APB1ENR1_I2C3EN_Pos             (23U)
-#define RCC_APB1ENR1_I2C3EN_Msk             (0x1UL << RCC_APB1ENR1_I2C3EN_Pos) /*!< 0x00800000 */
-#define RCC_APB1ENR1_I2C3EN                 RCC_APB1ENR1_I2C3EN_Msk
-#define RCC_APB1ENR1_DACEN_Pos              (29U)
-#define RCC_APB1ENR1_DACEN_Msk              (0x1UL << RCC_APB1ENR1_DACEN_Pos)/*!< 0x20000000 */
-#define RCC_APB1ENR1_DACEN                  RCC_APB1ENR1_DACEN_Msk
-#define RCC_APB1ENR1_LPTIM1EN_Pos           (31U)
-#define RCC_APB1ENR1_LPTIM1EN_Msk           (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
-#define RCC_APB1ENR1_LPTIM1EN               RCC_APB1ENR1_LPTIM1EN_Msk
-
-/********************  Bit definition for RCC_APB1ENR2 register  **************/
-#define RCC_APB1ENR2_LPUART1EN_Pos          (0U)
-#define RCC_APB1ENR2_LPUART1EN_Msk         (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
-#define RCC_APB1ENR2_LPUART1EN              RCC_APB1ENR2_LPUART1EN_Msk
-#define RCC_APB1ENR2_LPTIM2EN_Pos           (5U)
-#define RCC_APB1ENR2_LPTIM2EN_Msk           (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos)/*!< 0x00000020 */
-#define RCC_APB1ENR2_LPTIM2EN               RCC_APB1ENR2_LPTIM2EN_Msk
-#define RCC_APB1ENR2_LPTIM3EN_Pos           (6U)
-#define RCC_APB1ENR2_LPTIM3EN_Msk           (0x1UL << RCC_APB1ENR2_LPTIM3EN_Pos)/*!< 0x00000040 */
-#define RCC_APB1ENR2_LPTIM3EN               RCC_APB1ENR2_LPTIM3EN_Msk
-
-/********************  Bit definition for RCC_APB2ENR register  **************/
-#define RCC_APB2ENR_ADCEN_Pos               (9U)
-#define RCC_APB2ENR_ADCEN_Msk               (0x1UL << RCC_APB2ENR_ADCEN_Pos)  /*!< 0x00000200 */
-#define RCC_APB2ENR_ADCEN                   RCC_APB2ENR_ADCEN_Msk
-#define RCC_APB2ENR_TIM1EN_Pos              (11U)
-#define RCC_APB2ENR_TIM1EN_Msk              (0x1UL << RCC_APB2ENR_TIM1EN_Pos)  /*!< 0x00000800 */
-#define RCC_APB2ENR_TIM1EN                  RCC_APB2ENR_TIM1EN_Msk
-#define RCC_APB2ENR_SPI1EN_Pos              (12U)
-#define RCC_APB2ENR_SPI1EN_Msk              (0x1UL << RCC_APB2ENR_SPI1EN_Pos)  /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk
-#define RCC_APB2ENR_USART1EN_Pos            (14U)
-#define RCC_APB2ENR_USART1EN_Msk            (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
-#define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk
-#define RCC_APB2ENR_TIM16EN_Pos             (17U)
-#define RCC_APB2ENR_TIM16EN_Msk             (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
-#define RCC_APB2ENR_TIM16EN                 RCC_APB2ENR_TIM16EN_Msk
-#define RCC_APB2ENR_TIM17EN_Pos             (18U)
-#define RCC_APB2ENR_TIM17EN_Msk             (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
-#define RCC_APB2ENR_TIM17EN                 RCC_APB2ENR_TIM17EN_Msk
-
-/********************  Bit definition for RCC_APB3ENR register  **************/
-#define RCC_APB3ENR_SUBGHZSPIEN_Pos         (0U)
-#define RCC_APB3ENR_SUBGHZSPIEN_Msk         (0x1UL << RCC_APB3ENR_SUBGHZSPIEN_Pos)/*!< 0x00000001 */
-#define RCC_APB3ENR_SUBGHZSPIEN             RCC_APB3ENR_SUBGHZSPIEN_Msk
-
-/********************  Bit definition for RCC_AHB1SMENR register  ****************/
-#define RCC_AHB1SMENR_DMA1SMEN_Pos          (0U)
-#define RCC_AHB1SMENR_DMA1SMEN_Msk          (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
-#define RCC_AHB1SMENR_DMA1SMEN              RCC_AHB1SMENR_DMA1SMEN_Msk
-#define RCC_AHB1SMENR_DMA2SMEN_Pos          (1U)
-#define RCC_AHB1SMENR_DMA2SMEN_Msk          (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
-#define RCC_AHB1SMENR_DMA2SMEN              RCC_AHB1SMENR_DMA2SMEN_Msk
-#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos       (2U)
-#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk       (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
-#define RCC_AHB1SMENR_DMAMUX1SMEN           RCC_AHB1SMENR_DMAMUX1SMEN_Msk
-#define RCC_AHB1SMENR_CRCSMEN_Pos           (12U)
-#define RCC_AHB1SMENR_CRCSMEN_Msk           (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
-#define RCC_AHB1SMENR_CRCSMEN               RCC_AHB1SMENR_CRCSMEN_Msk
-
-/********************  Bit definition for RCC_AHB2SMENR register  ***************/
-#define RCC_AHB2SMENR_GPIOASMEN_Pos         (0U)
-#define RCC_AHB2SMENR_GPIOASMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
-#define RCC_AHB2SMENR_GPIOASMEN             RCC_AHB2SMENR_GPIOASMEN_Msk
-#define RCC_AHB2SMENR_GPIOBSMEN_Pos         (1U)
-#define RCC_AHB2SMENR_GPIOBSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
-#define RCC_AHB2SMENR_GPIOBSMEN             RCC_AHB2SMENR_GPIOBSMEN_Msk
-#define RCC_AHB2SMENR_GPIOCSMEN_Pos         (2U)
-#define RCC_AHB2SMENR_GPIOCSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
-#define RCC_AHB2SMENR_GPIOCSMEN             RCC_AHB2SMENR_GPIOCSMEN_Msk
-#define RCC_AHB2SMENR_GPIOHSMEN_Pos         (7U)
-#define RCC_AHB2SMENR_GPIOHSMEN_Msk         (0x1UL << RCC_AHB2SMENR_GPIOHSMEN_Pos)/*!< 0x00000080 */
-#define RCC_AHB2SMENR_GPIOHSMEN             RCC_AHB2SMENR_GPIOHSMEN_Msk
-
-/********************  Bit definition for RCC_AHB3SMENR register  ***************/
-#define RCC_AHB3SMENR_PKASMEN_Pos           (16U)
-#define RCC_AHB3SMENR_PKASMEN_Msk           (0x1UL << RCC_AHB3SMENR_PKASMEN_Pos) /*!< 0x00010000 */
-#define RCC_AHB3SMENR_PKASMEN               RCC_AHB3SMENR_PKASMEN_Msk
-#define RCC_AHB3SMENR_AESSMEN_Pos           (17U)
-#define RCC_AHB3SMENR_AESSMEN_Msk           (0x1UL << RCC_AHB3SMENR_AESSMEN_Pos) /*!< 0x00020000 */
-#define RCC_AHB3SMENR_AESSMEN               RCC_AHB3SMENR_AESSMEN_Msk
-#define RCC_AHB3SMENR_RNGSMEN_Pos           (18U)
-#define RCC_AHB3SMENR_RNGSMEN_Msk           (0x1UL << RCC_AHB3SMENR_RNGSMEN_Pos)/*!< 0x00040000 */
-#define RCC_AHB3SMENR_RNGSMEN               RCC_AHB3SMENR_RNGSMEN_Msk
-#define RCC_AHB3SMENR_SRAM1SMEN_Pos         (23U)
-#define RCC_AHB3SMENR_SRAM1SMEN_Msk         (0x1UL << RCC_AHB3SMENR_SRAM1SMEN_Pos)/*!< 0x00800000 */
-#define RCC_AHB3SMENR_SRAM1SMEN             RCC_AHB3SMENR_SRAM1SMEN_Msk
-#define RCC_AHB3SMENR_SRAM2SMEN_Pos         (24U)
-#define RCC_AHB3SMENR_SRAM2SMEN_Msk         (0x1UL << RCC_AHB3SMENR_SRAM2SMEN_Pos)/*!< 0x01000000 */
-#define RCC_AHB3SMENR_SRAM2SMEN             RCC_AHB3SMENR_SRAM2SMEN_Msk
-#define RCC_AHB3SMENR_FLASHSMEN_Pos         (25U)
-#define RCC_AHB3SMENR_FLASHSMEN_Msk         (0x1UL << RCC_AHB3SMENR_FLASHSMEN_Pos)/*!< 0x02000000 */
-#define RCC_AHB3SMENR_FLASHSMEN             RCC_AHB3SMENR_FLASHSMEN_Msk
-
-/********************  Bit definition for RCC_APB1SMENR1 register  **************/
-#define RCC_APB1SMENR1_TIM2SMEN_Pos         (0U)
-#define RCC_APB1SMENR1_TIM2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
-#define RCC_APB1SMENR1_TIM2SMEN             RCC_APB1SMENR1_TIM2SMEN_Msk
-#define RCC_APB1SMENR1_RTCAPBSMEN_Pos       (10U)
-#define RCC_APB1SMENR1_RTCAPBSMEN_Msk       (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
-#define RCC_APB1SMENR1_RTCAPBSMEN           RCC_APB1SMENR1_RTCAPBSMEN_Msk
-#define RCC_APB1SMENR1_WWDGSMEN_Pos         (11U)
-#define RCC_APB1SMENR1_WWDGSMEN_Msk         (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
-#define RCC_APB1SMENR1_WWDGSMEN             RCC_APB1SMENR1_WWDGSMEN_Msk
-#define RCC_APB1SMENR1_SPI2SMEN_Pos         (14U)
-#define RCC_APB1SMENR1_SPI2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
-#define RCC_APB1SMENR1_SPI2SMEN             RCC_APB1SMENR1_SPI2SMEN_Msk
-#define RCC_APB1SMENR1_USART2SMEN_Pos       (17U)
-#define RCC_APB1SMENR1_USART2SMEN_Msk       (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
-#define RCC_APB1SMENR1_USART2SMEN           RCC_APB1SMENR1_USART2SMEN_Msk
-#define RCC_APB1SMENR1_I2C1SMEN_Pos         (21U)
-#define RCC_APB1SMENR1_I2C1SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
-#define RCC_APB1SMENR1_I2C1SMEN             RCC_APB1SMENR1_I2C1SMEN_Msk
-#define RCC_APB1SMENR1_I2C2SMEN_Pos         (22U)
-#define RCC_APB1SMENR1_I2C2SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
-#define RCC_APB1SMENR1_I2C2SMEN             RCC_APB1SMENR1_I2C2SMEN_Msk
-#define RCC_APB1SMENR1_I2C3SMEN_Pos         (23U)
-#define RCC_APB1SMENR1_I2C3SMEN_Msk         (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x00800000 */
-#define RCC_APB1SMENR1_I2C3SMEN             RCC_APB1SMENR1_I2C3SMEN_Msk
-#define RCC_APB1SMENR1_DACSMEN_Pos          (29U)
-#define RCC_APB1SMENR1_DACSMEN_Msk          (0x1UL << RCC_APB1SMENR1_DACSMEN_Pos)/*!< 0x20000000 */
-#define RCC_APB1SMENR1_DACSMEN              RCC_APB1SMENR1_DACSMEN_Msk
-#define RCC_APB1SMENR1_LPTIM1SMEN_Pos       (31U)
-#define RCC_APB1SMENR1_LPTIM1SMEN_Msk       (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
-#define RCC_APB1SMENR1_LPTIM1SMEN           RCC_APB1SMENR1_LPTIM1SMEN_Msk
-
-/********************  Bit definition for RCC_APB1SMENR2 register  **************/
-#define RCC_APB1SMENR2_LPUART1SMEN_Pos      (0U)
-#define RCC_APB1SMENR2_LPUART1SMEN_Msk      (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
-#define RCC_APB1SMENR2_LPUART1SMEN          RCC_APB1SMENR2_LPUART1SMEN_Msk
-#define RCC_APB1SMENR2_LPTIM2SMEN_Pos       (5U)
-#define RCC_APB1SMENR2_LPTIM2SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos)/*!< 0x00000020 */
-#define RCC_APB1SMENR2_LPTIM2SMEN           RCC_APB1SMENR2_LPTIM2SMEN_Msk
-#define RCC_APB1SMENR2_LPTIM3SMEN_Pos       (6U)
-#define RCC_APB1SMENR2_LPTIM3SMEN_Msk       (0x1UL << RCC_APB1SMENR2_LPTIM3SMEN_Pos)/*!< 0x00000040 */
-#define RCC_APB1SMENR2_LPTIM3SMEN           RCC_APB1SMENR2_LPTIM3SMEN_Msk
-
-/********************  Bit definition for RCC_APB2SMENR register  **************/
-#define RCC_APB2SMENR_ADCSMEN_Pos           (9U)
-#define RCC_APB2SMENR_ADCSMEN_Msk           (0x1UL << RCC_APB2SMENR_ADCSMEN_Pos)/*!< 0x00000200 */
-#define RCC_APB2SMENR_ADCSMEN               RCC_APB2SMENR_ADCSMEN_Msk
-#define RCC_APB2SMENR_TIM1SMEN_Pos          (11U)
-#define RCC_APB2SMENR_TIM1SMEN_Msk          (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
-#define RCC_APB2SMENR_TIM1SMEN              RCC_APB2SMENR_TIM1SMEN_Msk
-#define RCC_APB2SMENR_SPI1SMEN_Pos          (12U)
-#define RCC_APB2SMENR_SPI1SMEN_Msk          (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
-#define RCC_APB2SMENR_SPI1SMEN              RCC_APB2SMENR_SPI1SMEN_Msk
-#define RCC_APB2SMENR_USART1SMEN_Pos        (14U)
-#define RCC_APB2SMENR_USART1SMEN_Msk        (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
-#define RCC_APB2SMENR_USART1SMEN            RCC_APB2SMENR_USART1SMEN_Msk
-#define RCC_APB2SMENR_TIM16SMEN_Pos         (17U)
-#define RCC_APB2SMENR_TIM16SMEN_Msk         (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
-#define RCC_APB2SMENR_TIM16SMEN             RCC_APB2SMENR_TIM16SMEN_Msk
-#define RCC_APB2SMENR_TIM17SMEN_Pos         (18U)
-#define RCC_APB2SMENR_TIM17SMEN_Msk         (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
-#define RCC_APB2SMENR_TIM17SMEN             RCC_APB2SMENR_TIM17SMEN_Msk
-
-/********************  Bit definition for RCC_APB3SMENR register  **************/
-#define RCC_APB3SMENR_SUBGHZSPISMEN_Pos     (0U)
-#define RCC_APB3SMENR_SUBGHZSPISMEN_Msk     (0x1UL << RCC_APB3SMENR_SUBGHZSPISMEN_Pos)/*!< 0x00000001 */
-#define RCC_APB3SMENR_SUBGHZSPISMEN         RCC_APB3SMENR_SUBGHZSPISMEN_Msk
-
-/********************  Bit definition for RCC_CCIPR register  ******************/
-#define RCC_CCIPR_USART1SEL_Pos             (0U)
-#define RCC_CCIPR_USART1SEL_Msk             (0x3UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */
-#define RCC_CCIPR_USART1SEL                 RCC_CCIPR_USART1SEL_Msk
-#define RCC_CCIPR_USART1SEL_0               (0x1UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */
-#define RCC_CCIPR_USART1SEL_1               (0x2UL << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */
-
-#define RCC_CCIPR_USART2SEL_Pos             (2U)
-#define RCC_CCIPR_USART2SEL_Msk             (0x3UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */
-#define RCC_CCIPR_USART2SEL                 RCC_CCIPR_USART2SEL_Msk
-#define RCC_CCIPR_USART2SEL_0               (0x1UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */
-#define RCC_CCIPR_USART2SEL_1               (0x2UL << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */
-
-#define RCC_CCIPR_I2S2SEL_Pos               (8U)
-#define RCC_CCIPR_I2S2SEL_Msk               (0x3UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000300 */
-#define RCC_CCIPR_I2S2SEL                   RCC_CCIPR_I2S2SEL_Msk
-#define RCC_CCIPR_I2S2SEL_0                 (0x1UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000100 */
-#define RCC_CCIPR_I2S2SEL_1                 (0x2UL << RCC_CCIPR_I2S2SEL_Pos) /*!< 0x00000200 */
-
-#define RCC_CCIPR_LPUART1SEL_Pos            (10U)
-#define RCC_CCIPR_LPUART1SEL_Msk            (0x3UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */
-#define RCC_CCIPR_LPUART1SEL                RCC_CCIPR_LPUART1SEL_Msk
-#define RCC_CCIPR_LPUART1SEL_0              (0x1UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000400 */
-#define RCC_CCIPR_LPUART1SEL_1              (0x2UL << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000800 */
-
-#define RCC_CCIPR_I2C1SEL_Pos               (12U)
-#define RCC_CCIPR_I2C1SEL_Msk               (0x3UL << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00003000 */
-#define RCC_CCIPR_I2C1SEL                   RCC_CCIPR_I2C1SEL_Msk
-#define RCC_CCIPR_I2C1SEL_0                 (0x1UL << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00001000 */
-#define RCC_CCIPR_I2C1SEL_1                 (0x2UL << RCC_CCIPR_I2C1SEL_Pos)   /*!< 0x00002000 */
-
-#define RCC_CCIPR_I2C2SEL_Pos               (14U)
-#define RCC_CCIPR_I2C2SEL_Msk               (0x3UL << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x0000C000 */
-#define RCC_CCIPR_I2C2SEL                   RCC_CCIPR_I2C2SEL_Msk
-#define RCC_CCIPR_I2C2SEL_0                 (0x1UL << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00004000 */
-#define RCC_CCIPR_I2C2SEL_1                 (0x2UL << RCC_CCIPR_I2C2SEL_Pos)   /*!< 0x00008000 */
-
-#define RCC_CCIPR_I2C3SEL_Pos               (16U)
-#define RCC_CCIPR_I2C3SEL_Msk               (0x3UL << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00030000 */
-#define RCC_CCIPR_I2C3SEL                   RCC_CCIPR_I2C3SEL_Msk
-#define RCC_CCIPR_I2C3SEL_0                 (0x1UL << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00010000 */
-#define RCC_CCIPR_I2C3SEL_1                 (0x2UL << RCC_CCIPR_I2C3SEL_Pos)   /*!< 0x00020000 */
-
-#define RCC_CCIPR_LPTIM1SEL_Pos             (18U)
-#define RCC_CCIPR_LPTIM1SEL_Msk             (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */
-#define RCC_CCIPR_LPTIM1SEL                 RCC_CCIPR_LPTIM1SEL_Msk
-#define RCC_CCIPR_LPTIM1SEL_0               (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */
-#define RCC_CCIPR_LPTIM1SEL_1               (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */
-
-#define RCC_CCIPR_LPTIM2SEL_Pos             (20U)
-#define RCC_CCIPR_LPTIM2SEL_Msk             (0x3UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00300000 */
-#define RCC_CCIPR_LPTIM2SEL                 RCC_CCIPR_LPTIM2SEL_Msk
-#define RCC_CCIPR_LPTIM2SEL_0               (0x1UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00100000 */
-#define RCC_CCIPR_LPTIM2SEL_1               (0x2UL << RCC_CCIPR_LPTIM2SEL_Pos) /*!< 0x00200000 */
-
-#define RCC_CCIPR_LPTIM3SEL_Pos             (22U)
-#define RCC_CCIPR_LPTIM3SEL_Msk             (0x3UL << RCC_CCIPR_LPTIM3SEL_Pos)   /*!< 0x00C00000 */
-#define RCC_CCIPR_LPTIM3SEL                 RCC_CCIPR_LPTIM3SEL_Msk
-#define RCC_CCIPR_LPTIM3SEL_0               (0x1UL << RCC_CCIPR_LPTIM3SEL_Pos)   /*!< 0x00400000 */
-#define RCC_CCIPR_LPTIM3SEL_1               (0x2UL << RCC_CCIPR_LPTIM3SEL_Pos)   /*!< 0x00800000 */
-
-#define RCC_CCIPR_ADCSEL_Pos                (28U)
-#define RCC_CCIPR_ADCSEL_Msk                (0x3UL << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x30000000 */
-#define RCC_CCIPR_ADCSEL                    RCC_CCIPR_ADCSEL_Msk
-#define RCC_CCIPR_ADCSEL_0                  (0x1UL << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x10000000 */
-#define RCC_CCIPR_ADCSEL_1                  (0x2UL << RCC_CCIPR_ADCSEL_Pos)    /*!< 0x20000000 */
-
-#define RCC_CCIPR_RNGSEL_Pos                (30U)
-#define RCC_CCIPR_RNGSEL_Msk                (0x3UL << RCC_CCIPR_RNGSEL_Pos)    /*!< 0xC0000000 */
-#define RCC_CCIPR_RNGSEL                    RCC_CCIPR_RNGSEL_Msk
-#define RCC_CCIPR_RNGSEL_0                  (0x1UL << RCC_CCIPR_RNGSEL_Pos)    /*!< 0x40000000 */
-#define RCC_CCIPR_RNGSEL_1                  (0x2UL << RCC_CCIPR_RNGSEL_Pos)    /*!< 0x80000000 */
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define RCC_BDCR_LSEON_Pos                  (0U)
-#define RCC_BDCR_LSEON_Msk                  (0x1UL << RCC_BDCR_LSEON_Pos)      /*!< 0x00000001 */
-#define RCC_BDCR_LSEON                      RCC_BDCR_LSEON_Msk
-#define RCC_BDCR_LSERDY_Pos                 (1U)
-#define RCC_BDCR_LSERDY_Msk                 (0x1UL << RCC_BDCR_LSERDY_Pos)     /*!< 0x00000002 */
-#define RCC_BDCR_LSERDY                     RCC_BDCR_LSERDY_Msk
-#define RCC_BDCR_LSEBYP_Pos                 (2U)
-#define RCC_BDCR_LSEBYP_Msk                 (0x1UL << RCC_BDCR_LSEBYP_Pos)     /*!< 0x00000004 */
-#define RCC_BDCR_LSEBYP                     RCC_BDCR_LSEBYP_Msk
-
-#define RCC_BDCR_LSEDRV_Pos                 (3U)
-#define RCC_BDCR_LSEDRV_Msk                 (0x3UL << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000018 */
-#define RCC_BDCR_LSEDRV                     RCC_BDCR_LSEDRV_Msk
-#define RCC_BDCR_LSEDRV_0                   (0x1UL << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000008 */
-#define RCC_BDCR_LSEDRV_1                   (0x2UL << RCC_BDCR_LSEDRV_Pos)     /*!< 0x00000010 */
-
-#define RCC_BDCR_LSECSSON_Pos               (5U)
-#define RCC_BDCR_LSECSSON_Msk               (0x1UL << RCC_BDCR_LSECSSON_Pos)   /*!< 0x00000020 */
-#define RCC_BDCR_LSECSSON                   RCC_BDCR_LSECSSON_Msk
-#define RCC_BDCR_LSECSSD_Pos                (6U)
-#define RCC_BDCR_LSECSSD_Msk                (0x1UL << RCC_BDCR_LSECSSD_Pos)    /*!< 0x00000040 */
-#define RCC_BDCR_LSECSSD                    RCC_BDCR_LSECSSD_Msk
-#define RCC_BDCR_LSESYSEN_Pos               (7U)
-#define RCC_BDCR_LSESYSEN_Msk               (0x1UL << RCC_BDCR_LSESYSEN_Pos)   /*!< 0x00000080 */
-#define RCC_BDCR_LSESYSEN                   RCC_BDCR_LSESYSEN_Msk
-
-#define RCC_BDCR_RTCSEL_Pos                 (8U)
-#define RCC_BDCR_RTCSEL_Msk                 (0x3UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000300 */
-#define RCC_BDCR_RTCSEL                     RCC_BDCR_RTCSEL_Msk
-#define RCC_BDCR_RTCSEL_0                   (0x1UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000100 */
-#define RCC_BDCR_RTCSEL_1                   (0x2UL << RCC_BDCR_RTCSEL_Pos)     /*!< 0x00000200 */
-
-#define RCC_BDCR_LSESYSRDY_Pos              (11U)
-#define RCC_BDCR_LSESYSRDY_Msk              (0x1UL << RCC_BDCR_LSESYSRDY_Pos) /*!< 0x00000800 */
-#define RCC_BDCR_LSESYSRDY                  RCC_BDCR_LSESYSRDY_Msk
-
-#define RCC_BDCR_RTCEN_Pos                  (15U)
-#define RCC_BDCR_RTCEN_Msk                  (0x1UL << RCC_BDCR_RTCEN_Pos)      /*!< 0x00008000 */
-#define RCC_BDCR_RTCEN                      RCC_BDCR_RTCEN_Msk
-
-#define RCC_BDCR_BDRST_Pos                  (16U)
-#define RCC_BDCR_BDRST_Msk                  (0x1UL << RCC_BDCR_BDRST_Pos)      /*!< 0x00010000 */
-#define RCC_BDCR_BDRST                      RCC_BDCR_BDRST_Msk
-
-#define RCC_BDCR_LSCOEN_Pos                 (24U)
-#define RCC_BDCR_LSCOEN_Msk                 (0x1UL << RCC_BDCR_LSCOEN_Pos)     /*!< 0x01000000 */
-#define RCC_BDCR_LSCOEN                     RCC_BDCR_LSCOEN_Msk
-#define RCC_BDCR_LSCOSEL_Pos                (25U)
-#define RCC_BDCR_LSCOSEL_Msk                (0x1UL << RCC_BDCR_LSCOSEL_Pos)    /*!< 0x02000000 */
-#define RCC_BDCR_LSCOSEL                    RCC_BDCR_LSCOSEL_Msk
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                  (0U)
-#define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)      /*!< 0x00000001 */
-#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk
-#define RCC_CSR_LSIRDY_Pos                 (1U)
-#define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)     /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk
-#define RCC_CSR_LSIPRE_Pos                 (4U)
-#define RCC_CSR_LSIPRE_Msk                 (0x1UL << RCC_CSR_LSIPRE_Pos)     /*!< 0x00000010 */
-#define RCC_CSR_LSIPRE                     RCC_CSR_LSIPRE_Msk
-
-#define RCC_CSR_MSISRANGE_Pos              (8U)
-#define RCC_CSR_MSISRANGE_Msk              (0xFUL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000F00 */
-#define RCC_CSR_MSISRANGE                  RCC_CSR_MSISRANGE_Msk
-#define RCC_CSR_MSISRANGE_1                (0x4UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000400 */
-#define RCC_CSR_MSISRANGE_2                (0x5UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000500 */
-#define RCC_CSR_MSISRANGE_4                (0x6UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000600 */
-#define RCC_CSR_MSISRANGE_8                (0x7UL << RCC_CSR_MSISRANGE_Pos)  /*!< 0x00000700 */
-
-#define RCC_CSR_RFRSTF_Pos                  (14U)
-#define RCC_CSR_RFRSTF_Msk                  (0x1UL << RCC_CSR_RFRSTF_Pos)      /*!< 0x0004000 */
-#define RCC_CSR_RFRSTF                      RCC_CSR_RFRSTF_Msk
-#define RCC_CSR_RFRST_Pos                   (15U)
-#define RCC_CSR_RFRST_Msk                   (0x1UL << RCC_CSR_RFRST_Pos)       /*!< 0x0008000 */
-#define RCC_CSR_RFRST                       RCC_CSR_RFRST_Msk
-
-#define RCC_CSR_RMVF_Pos                    (23U)
-#define RCC_CSR_RMVF_Msk                    (0x1UL << RCC_CSR_RMVF_Pos)        /*!< 0x00800000 */
-#define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk
-#define RCC_CSR_RFILARSTF_Pos               (24U)
-#define RCC_CSR_RFILARSTF_Msk               (0x1UL << RCC_CSR_RFILARSTF_Pos)   /*!< 0x01000000 */
-#define RCC_CSR_RFILARSTF                   RCC_CSR_RFILARSTF_Msk
-#define RCC_CSR_OBLRSTF_Pos                 (25U)
-#define RCC_CSR_OBLRSTF_Msk                 (0x1UL << RCC_CSR_OBLRSTF_Pos)     /*!< 0x02000000 */
-#define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk
-#define RCC_CSR_PINRSTF_Pos                 (26U)
-#define RCC_CSR_PINRSTF_Msk                 (0x1UL << RCC_CSR_PINRSTF_Pos)     /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk
-#define RCC_CSR_BORRSTF_Pos                 (27U)
-#define RCC_CSR_BORRSTF_Msk                 (0x1UL << RCC_CSR_BORRSTF_Pos)     /*!< 0x08000000 */
-#define RCC_CSR_BORRSTF                     RCC_CSR_BORRSTF_Msk
-#define RCC_CSR_SFTRSTF_Pos                 (28U)
-#define RCC_CSR_SFTRSTF_Msk                 (0x1UL << RCC_CSR_SFTRSTF_Pos)     /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk
-#define RCC_CSR_IWDGRSTF_Pos                (29U)
-#define RCC_CSR_IWDGRSTF_Msk                (0x1UL << RCC_CSR_IWDGRSTF_Pos)    /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk
-#define RCC_CSR_WWDGRSTF_Pos                (30U)
-#define RCC_CSR_WWDGRSTF_Msk                (0x1UL << RCC_CSR_WWDGRSTF_Pos)    /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk
-#define RCC_CSR_LPWRRSTF_Pos                (31U)
-#define RCC_CSR_LPWRRSTF_Msk                (0x1UL << RCC_CSR_LPWRRSTF_Pos)    /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk
-
-/********************  Bit definition for RCC_EXTCFGR register  *******************/
-#define RCC_EXTCFGR_SHDHPRE_Pos             (0U)
-#define RCC_EXTCFGR_SHDHPRE_Msk             (0xFUL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x0000000F */
-#define RCC_EXTCFGR_SHDHPRE                 RCC_EXTCFGR_SHDHPRE_Msk
-#define RCC_EXTCFGR_SHDHPRE_0               (0x1UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000001 */
-#define RCC_EXTCFGR_SHDHPRE_1               (0x2UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000002 */
-#define RCC_EXTCFGR_SHDHPRE_2               (0x4UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000004 */
-#define RCC_EXTCFGR_SHDHPRE_3               (0x8UL << RCC_EXTCFGR_SHDHPRE_Pos) /*!< 0x00000008 */
-
-#define RCC_EXTCFGR_SHDHPREF_Pos            (16U)
-#define RCC_EXTCFGR_SHDHPREF_Msk            (0x1UL << RCC_EXTCFGR_SHDHPREF_Pos)/*!< 0x00010000 */
-#define RCC_EXTCFGR_SHDHPREF                RCC_EXTCFGR_SHDHPREF_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions
- */
-#define RNG_VER_3_2
-
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos         (2U)
-#define RNG_CR_RNGEN_Msk         (0x1UL << RNG_CR_RNGEN_Pos)                   /*!< 0x00000004 */
-#define RNG_CR_RNGEN             RNG_CR_RNGEN_Msk
-#define RNG_CR_IE_Pos            (3U)
-#define RNG_CR_IE_Msk            (0x1UL << RNG_CR_IE_Pos)                      /*!< 0x00000008 */
-#define RNG_CR_IE                RNG_CR_IE_Msk
-#define RNG_CR_CED_Pos           (5U)
-#define RNG_CR_CED_Msk           (0x1UL << RNG_CR_CED_Pos)                     /*!< 0x00000020 */
-#define RNG_CR_CED               RNG_CR_CED_Msk
-#define RNG_CR_RNG_CONFIG3_Pos   (8U)
-#define RNG_CR_RNG_CONFIG3_Msk   (0xFUL << RNG_CR_RNG_CONFIG3_Pos)              /*!< 0x00000F00 */
-#define RNG_CR_RNG_CONFIG3       RNG_CR_RNG_CONFIG3_Msk
-#define RNG_CR_NISTC_Pos         (12U)
-#define RNG_CR_NISTC_Msk         (0x1UL << RNG_CR_NISTC_Pos)                   /*!< 0x00001000 */
-#define RNG_CR_NISTC             RNG_CR_NISTC_Msk
-#define RNG_CR_RNG_CONFIG2_Pos   (13U)
-#define RNG_CR_RNG_CONFIG2_Msk   (0x7UL << RNG_CR_RNG_CONFIG2_Pos)              /*!< 0x0000E000 */
-#define RNG_CR_RNG_CONFIG2       RNG_CR_RNG_CONFIG2_Msk
-#define RNG_CR_CLKDIV_Pos        (16U)
-#define RNG_CR_CLKDIV_Msk        (0xFUL << RNG_CR_CLKDIV_Pos)                  /*!< 0x000F0000 */
-#define RNG_CR_CLKDIV            RNG_CR_CLKDIV_Msk
-#define RNG_CR_CLKDIV_0          (0x1UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00010000 */
-#define RNG_CR_CLKDIV_1          (0x2UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00020000 */
-#define RNG_CR_CLKDIV_2          (0x4UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00040000 */
-#define RNG_CR_CLKDIV_3          (0x8UL << RNG_CR_CLKDIV_Pos)                  /*!< 0x00080000 */
-#define RNG_CR_RNG_CONFIG1_Pos   (20U)
-#define RNG_CR_RNG_CONFIG1_Msk   (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)             /*!< 0x03F00000 */
-#define RNG_CR_RNG_CONFIG1       RNG_CR_RNG_CONFIG1_Msk
-#define RNG_CR_CONDRST_Pos       (30U)
-#define RNG_CR_CONDRST_Msk       (0x1UL << RNG_CR_CONDRST_Pos)                 /*!< 0x40000000 */
-#define RNG_CR_CONDRST           RNG_CR_CONDRST_Msk
-#define RNG_CR_CONFIGLOCK_Pos    (31U)
-#define RNG_CR_CONFIGLOCK_Msk    (0x1UL << RNG_CR_CONFIGLOCK_Pos)              /*!< 0x80000000 */
-#define RNG_CR_CONFIGLOCK        RNG_CR_CONFIGLOCK_Msk
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)
-#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk
-#define RNG_SR_CECS_Pos     (1U)
-#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk
-#define RNG_SR_SECS_Pos     (2U)
-#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk
-#define RNG_SR_CEIS_Pos     (5U)
-#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk
-#define RNG_SR_SEIS_Pos     (6U)
-#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk
-
-/********************  Bits definition for RNG_DR register  *******************/
-#define RNG_DR_RNDATA_Pos        (0U)
-#define RNG_DR_RNDATA_Msk        (0xFFFFFFFFUL << RNG_DR_RNDATA_Pos)       /*!< 0xFFFFFFFF */
-#define RNG_DR_RNDATA            RNG_DR_RNDATA_Msk
-
-/********************  Bits definition for RNG_HTCR register  *****************/
-#define RNG_HTCR_HTCFG_Pos       (0U)
-#define RNG_HTCR_HTCFG_Msk       (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)      /*!< 0xFFFFFFFF */
-#define RNG_HTCR_HTCFG           RNG_HTCR_HTCFG_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                (22U)
-#define RTC_TR_PM_Msk                (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
-#define RTC_TR_PM                    RTC_TR_PM_Msk
-#define RTC_TR_HT_Pos                (20U)
-#define RTC_TR_HT_Msk                (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
-#define RTC_TR_HT                    RTC_TR_HT_Msk
-#define RTC_TR_HT_0                  (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
-#define RTC_TR_HT_1                  (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                (16U)
-#define RTC_TR_HU_Msk                (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
-#define RTC_TR_HU                    RTC_TR_HU_Msk
-#define RTC_TR_HU_0                  (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
-#define RTC_TR_HU_1                  (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
-#define RTC_TR_HU_2                  (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
-#define RTC_TR_HU_3                  (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos               (12U)
-#define RTC_TR_MNT_Msk               (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
-#define RTC_TR_MNT                   RTC_TR_MNT_Msk
-#define RTC_TR_MNT_0                 (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
-#define RTC_TR_MNT_1                 (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
-#define RTC_TR_MNT_2                 (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos               (8U)
-#define RTC_TR_MNU_Msk               (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
-#define RTC_TR_MNU                   RTC_TR_MNU_Msk
-#define RTC_TR_MNU_0                 (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
-#define RTC_TR_MNU_1                 (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
-#define RTC_TR_MNU_2                 (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
-#define RTC_TR_MNU_3                 (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                (4U)
-#define RTC_TR_ST_Msk                (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
-#define RTC_TR_ST                    RTC_TR_ST_Msk
-#define RTC_TR_ST_0                  (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
-#define RTC_TR_ST_1                  (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
-#define RTC_TR_ST_2                  (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                (0U)
-#define RTC_TR_SU_Msk                (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
-#define RTC_TR_SU                    RTC_TR_SU_Msk
-#define RTC_TR_SU_0                  (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
-#define RTC_TR_SU_1                  (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
-#define RTC_TR_SU_2                  (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
-#define RTC_TR_SU_3                  (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                (20U)
-#define RTC_DR_YT_Msk                (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
-#define RTC_DR_YT                    RTC_DR_YT_Msk
-#define RTC_DR_YT_0                  (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
-#define RTC_DR_YT_1                  (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
-#define RTC_DR_YT_2                  (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
-#define RTC_DR_YT_3                  (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                (16U)
-#define RTC_DR_YU_Msk                (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
-#define RTC_DR_YU                    RTC_DR_YU_Msk
-#define RTC_DR_YU_0                  (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
-#define RTC_DR_YU_1                  (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
-#define RTC_DR_YU_2                  (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
-#define RTC_DR_YU_3                  (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos               (13U)
-#define RTC_DR_WDU_Msk               (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
-#define RTC_DR_WDU                   RTC_DR_WDU_Msk
-#define RTC_DR_WDU_0                 (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
-#define RTC_DR_WDU_1                 (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
-#define RTC_DR_WDU_2                 (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                (12U)
-#define RTC_DR_MT_Msk                (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
-#define RTC_DR_MT                    RTC_DR_MT_Msk
-#define RTC_DR_MU_Pos                (8U)
-#define RTC_DR_MU_Msk                (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
-#define RTC_DR_MU                    RTC_DR_MU_Msk
-#define RTC_DR_MU_0                  (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
-#define RTC_DR_MU_1                  (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
-#define RTC_DR_MU_2                  (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
-#define RTC_DR_MU_3                  (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                (4U)
-#define RTC_DR_DT_Msk                (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
-#define RTC_DR_DT                    RTC_DR_DT_Msk
-#define RTC_DR_DT_0                  (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
-#define RTC_DR_DT_1                  (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                (0U)
-#define RTC_DR_DU_Msk                (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
-#define RTC_DR_DU                    RTC_DR_DU_Msk
-#define RTC_DR_DU_0                  (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
-#define RTC_DR_DU_1                  (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
-#define RTC_DR_DU_2                  (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
-#define RTC_DR_DU_3                  (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos               (0U)
-#define RTC_SSR_SS_Msk               (0xFFFFFFFFUL << RTC_SSR_SS_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_SSR_SS                   RTC_SSR_SS_Msk
-
-/********************  Bits definition for RTC_ICSR register  ******************/
-#define RTC_ICSR_RECALPF_Pos         (16U)
-#define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */
-#define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk
-#define RTC_ICSR_BCDU_Pos            (10U)
-#define RTC_ICSR_BCDU_Msk            (0x7UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00001C00 */
-#define RTC_ICSR_BCDU                RTC_ICSR_BCDU_Msk
-#define RTC_ICSR_BCDU_0              (0x1UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00000400 */
-#define RTC_ICSR_BCDU_1              (0x2UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00000800 */
-#define RTC_ICSR_BCDU_2              (0x4UL << RTC_ICSR_BCDU_Pos)              /*!< 0x00001000 */
-#define RTC_ICSR_BIN_Pos             (8U)
-#define RTC_ICSR_BIN_Msk             (0x3UL << RTC_ICSR_BIN_Pos)               /*!< 0x00000300 */
-#define RTC_ICSR_BIN                 RTC_ICSR_BIN_Msk
-#define RTC_ICSR_BIN_0               (0x1UL << RTC_ICSR_BIN_Pos)               /*!< 0x00000100 */
-#define RTC_ICSR_BIN_1               (0x2UL << RTC_ICSR_BIN_Pos)               /*!< 0x00000200 */
-#define RTC_ICSR_INIT_Pos            (7U)
-#define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */
-#define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk
-#define RTC_ICSR_INITF_Pos           (6U)
-#define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */
-#define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk
-#define RTC_ICSR_RSF_Pos             (5U)
-#define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */
-#define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk
-#define RTC_ICSR_INITS_Pos           (4U)
-#define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */
-#define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk
-#define RTC_ICSR_SHPF_Pos            (3U)
-#define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */
-#define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk
-#define RTC_ICSR_WUTWF_Pos           (2U)
-#define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */
-#define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos        (16U)
-#define RTC_PRER_PREDIV_A_Msk        (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A            RTC_PRER_PREDIV_A_Msk
-#define RTC_PRER_PREDIV_S_Pos        (0U)
-#define RTC_PRER_PREDIV_S_Msk        (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S            RTC_PRER_PREDIV_S_Msk
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUTOCLR_Pos         (16U)
-#define RTC_WUTR_WUTOCLR_Msk         (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos)        /*!< 0x0000FFFF */
-#define RTC_WUTR_WUTOCLR             RTC_WUTR_WUTOCLR_Msk
-#define RTC_WUTR_WUT_Pos             (0U)
-#define RTC_WUTR_WUT_Msk             (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                 RTC_WUTR_WUT_Msk
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_OUT2EN_Pos            (31U)
-#define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */
-#define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */
-#define RTC_CR_TAMPALRM_TYPE_Pos     (30U)
-#define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */
-#define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */
-#define RTC_CR_TAMPALRM_PU_Pos       (29U)
-#define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */
-#define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */
-#define RTC_CR_TAMPOE_Pos            (26U)
-#define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */
-#define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */
-#define RTC_CR_TAMPTS_Pos            (25U)
-#define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */
-#define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */
-#define RTC_CR_ITSE_Pos              (24U)
-#define RTC_CR_ITSE_Msk              (0x1UL << RTC_CR_ITSE_Pos)                /*!< 0x01000000 */
-#define RTC_CR_ITSE                  RTC_CR_ITSE_Msk                           /*!<Timestamp on internal event enable  */
-#define RTC_CR_COE_Pos               (23U)
-#define RTC_CR_COE_Msk               (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
-#define RTC_CR_COE                   RTC_CR_COE_Msk
-#define RTC_CR_OSEL_Pos              (21U)
-#define RTC_CR_OSEL_Msk              (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
-#define RTC_CR_OSEL                  RTC_CR_OSEL_Msk
-#define RTC_CR_OSEL_0                (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
-#define RTC_CR_POL_Pos               (20U)
-#define RTC_CR_POL_Msk               (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
-#define RTC_CR_POL                   RTC_CR_POL_Msk
-#define RTC_CR_COSEL_Pos             (19U)
-#define RTC_CR_COSEL_Msk             (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
-#define RTC_CR_COSEL                 RTC_CR_COSEL_Msk
-#define RTC_CR_BKP_Pos               (18U)
-#define RTC_CR_BKP_Msk               (0x1UL << RTC_CR_BKP_Pos)                 /*!< 0x00040000 */
-#define RTC_CR_BKP                   RTC_CR_BKP_Msk
-#define RTC_CR_SUB1H_Pos             (17U)
-#define RTC_CR_SUB1H_Msk             (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
-#define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk
-#define RTC_CR_ADD1H_Pos             (16U)
-#define RTC_CR_ADD1H_Msk             (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
-#define RTC_CR_ADD1H                 RTC_CR_ADD1H_Msk
-#define RTC_CR_TSIE_Pos              (15U)
-#define RTC_CR_TSIE_Msk              (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
-#define RTC_CR_TSIE                  RTC_CR_TSIE_Msk
-#define RTC_CR_WUTIE_Pos             (14U)
-#define RTC_CR_WUTIE_Msk             (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
-#define RTC_CR_WUTIE                 RTC_CR_WUTIE_Msk
-#define RTC_CR_ALRBIE_Pos            (13U)
-#define RTC_CR_ALRBIE_Msk            (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                RTC_CR_ALRBIE_Msk
-#define RTC_CR_ALRAIE_Pos            (12U)
-#define RTC_CR_ALRAIE_Msk            (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                RTC_CR_ALRAIE_Msk
-#define RTC_CR_TSE_Pos               (11U)
-#define RTC_CR_TSE_Msk               (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
-#define RTC_CR_TSE                   RTC_CR_TSE_Msk
-#define RTC_CR_WUTE_Pos              (10U)
-#define RTC_CR_WUTE_Msk              (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
-#define RTC_CR_WUTE                  RTC_CR_WUTE_Msk
-#define RTC_CR_ALRBE_Pos             (9U)
-#define RTC_CR_ALRBE_Msk             (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
-#define RTC_CR_ALRBE                 RTC_CR_ALRBE_Msk
-#define RTC_CR_ALRAE_Pos             (8U)
-#define RTC_CR_ALRAE_Msk             (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
-#define RTC_CR_ALRAE                 RTC_CR_ALRAE_Msk
-#define RTC_CR_SSRUIE_Pos            (7U)
-#define RTC_CR_SSRUIE_Msk            (0x1UL << RTC_CR_SSRUIE_Pos)              /*!< 0x00000080 */
-#define RTC_CR_SSRUIE                RTC_CR_SSRUIE_Msk
-#define RTC_CR_FMT_Pos               (6U)
-#define RTC_CR_FMT_Msk               (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
-#define RTC_CR_FMT                   RTC_CR_FMT_Msk
-#define RTC_CR_BYPSHAD_Pos           (5U)
-#define RTC_CR_BYPSHAD_Msk           (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD               RTC_CR_BYPSHAD_Msk
-#define RTC_CR_REFCKON_Pos           (4U)
-#define RTC_CR_REFCKON_Msk           (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
-#define RTC_CR_REFCKON               RTC_CR_REFCKON_Msk
-#define RTC_CR_TSEDGE_Pos            (3U)
-#define RTC_CR_TSEDGE_Msk            (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                RTC_CR_TSEDGE_Msk
-#define RTC_CR_WUCKSEL_Pos           (0U)
-#define RTC_CR_WUCKSEL_Msk           (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL               RTC_CR_WUCKSEL_Msk
-#define RTC_CR_WUCKSEL_0             (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1             (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2             (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos              (0U)
-#define RTC_WPR_KEY_Msk              (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
-#define RTC_WPR_KEY                  RTC_WPR_KEY_Msk
-
-/********************  Bits definition for RTC_CALR register  *****************/
-#define RTC_CALR_CALP_Pos            (15U)
-#define RTC_CALR_CALP_Msk            (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
-#define RTC_CALR_CALP                RTC_CALR_CALP_Msk
-#define RTC_CALR_CALW8_Pos           (14U)
-#define RTC_CALR_CALW8_Msk           (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
-#define RTC_CALR_CALW8               RTC_CALR_CALW8_Msk
-#define RTC_CALR_CALW16_Pos          (13U)
-#define RTC_CALR_CALW16_Msk          (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
-#define RTC_CALR_LPCAL               RTC_CALR_LPCAL_Msk
-#define RTC_CALR_LPCAL_Pos           (12U)
-#define RTC_CALR_LPCAL_Msk           (0x1UL << RTC_CALR_LPCAL_Pos)             /*!< 0x00001000 */
-#define RTC_CALR_CALW16              RTC_CALR_CALW16_Msk
-#define RTC_CALR_CALM_Pos            (0U)
-#define RTC_CALR_CALM_Msk            (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
-#define RTC_CALR_CALM                RTC_CALR_CALM_Msk
-#define RTC_CALR_CALM_0              (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
-#define RTC_CALR_CALM_1              (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
-#define RTC_CALR_CALM_2              (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
-#define RTC_CALR_CALM_3              (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
-#define RTC_CALR_CALM_4              (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
-#define RTC_CALR_CALM_5              (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
-#define RTC_CALR_CALM_6              (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
-#define RTC_CALR_CALM_7              (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
-#define RTC_CALR_CALM_8              (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_ADD1S_Pos         (31U)
-#define RTC_SHIFTR_ADD1S_Msk         (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S             RTC_SHIFTR_ADD1S_Msk
-#define RTC_SHIFTR_SUBFS_Pos         (0U)
-#define RTC_SHIFTR_SUBFS_Msk         (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS             RTC_SHIFTR_SUBFS_Msk
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos              (22U)
-#define RTC_TSTR_PM_Msk              (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
-#define RTC_TSTR_PM                  RTC_TSTR_PM_Msk                           
-#define RTC_TSTR_HT_Pos              (20U)
-#define RTC_TSTR_HT_Msk              (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
-#define RTC_TSTR_HT                  RTC_TSTR_HT_Msk
-#define RTC_TSTR_HT_0                (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos              (16U)
-#define RTC_TSTR_HU_Msk              (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
-#define RTC_TSTR_HU                  RTC_TSTR_HU_Msk
-#define RTC_TSTR_HU_0                (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos             (12U)
-#define RTC_TSTR_MNT_Msk             (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
-#define RTC_TSTR_MNT                 RTC_TSTR_MNT_Msk
-#define RTC_TSTR_MNT_0               (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1               (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2               (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos             (8U)
-#define RTC_TSTR_MNU_Msk             (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                 RTC_TSTR_MNU_Msk
-#define RTC_TSTR_MNU_0               (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1               (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2               (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3               (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos              (4U)
-#define RTC_TSTR_ST_Msk              (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
-#define RTC_TSTR_ST                  RTC_TSTR_ST_Msk
-#define RTC_TSTR_ST_0                (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos              (0U)
-#define RTC_TSTR_SU_Msk              (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
-#define RTC_TSTR_SU                  RTC_TSTR_SU_Msk
-#define RTC_TSTR_SU_0                (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos             (13U)
-#define RTC_TSDR_WDU_Msk             (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                 RTC_TSDR_WDU_Msk                          
-#define RTC_TSDR_WDU_0               (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1               (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2               (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos              (12U)
-#define RTC_TSDR_MT_Msk              (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
-#define RTC_TSDR_MT                  RTC_TSDR_MT_Msk
-#define RTC_TSDR_MU_Pos              (8U)
-#define RTC_TSDR_MU_Msk              (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
-#define RTC_TSDR_MU                  RTC_TSDR_MU_Msk
-#define RTC_TSDR_MU_0                (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos              (4U)
-#define RTC_TSDR_DT_Msk              (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
-#define RTC_TSDR_DT                  RTC_TSDR_DT_Msk
-#define RTC_TSDR_DT_0                (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos              (0U)
-#define RTC_TSDR_DU_Msk              (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
-#define RTC_TSDR_DU                  RTC_TSDR_DU_Msk
-#define RTC_TSDR_DU_0                (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos             (0U)
-#define RTC_TSSSR_SS_Msk             (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos)        /*!< 0xFFFFFFFF */
-#define RTC_TSSSR_SS                 RTC_TSSSR_SS_Msk                          
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos          (31U)
-#define RTC_ALRMAR_MSK4_Msk          (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4              RTC_ALRMAR_MSK4_Msk
-#define RTC_ALRMAR_WDSEL_Pos         (30U)
-#define RTC_ALRMAR_WDSEL_Msk         (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL             RTC_ALRMAR_WDSEL_Msk
-#define RTC_ALRMAR_DT_Pos            (28U)
-#define RTC_ALRMAR_DT_Msk            (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                RTC_ALRMAR_DT_Msk
-#define RTC_ALRMAR_DT_0              (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1              (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos            (24U)
-#define RTC_ALRMAR_DU_Msk            (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                RTC_ALRMAR_DU_Msk
-#define RTC_ALRMAR_DU_0              (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1              (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2              (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3              (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos          (23U)
-#define RTC_ALRMAR_MSK3_Msk          (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3              RTC_ALRMAR_MSK3_Msk
-#define RTC_ALRMAR_PM_Pos            (22U)
-#define RTC_ALRMAR_PM_Msk            (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                RTC_ALRMAR_PM_Msk
-#define RTC_ALRMAR_HT_Pos            (20U)
-#define RTC_ALRMAR_HT_Msk            (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                RTC_ALRMAR_HT_Msk
-#define RTC_ALRMAR_HT_0              (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1              (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos            (16U)
-#define RTC_ALRMAR_HU_Msk            (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                RTC_ALRMAR_HU_Msk
-#define RTC_ALRMAR_HU_0              (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1              (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2              (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3              (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos          (15U)
-#define RTC_ALRMAR_MSK2_Msk          (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2              RTC_ALRMAR_MSK2_Msk
-#define RTC_ALRMAR_MNT_Pos           (12U)
-#define RTC_ALRMAR_MNT_Msk           (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT               RTC_ALRMAR_MNT_Msk
-#define RTC_ALRMAR_MNT_0             (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1             (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2             (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos           (8U)
-#define RTC_ALRMAR_MNU_Msk           (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU               RTC_ALRMAR_MNU_Msk
-#define RTC_ALRMAR_MNU_0             (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1             (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2             (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3             (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos          (7U)
-#define RTC_ALRMAR_MSK1_Msk          (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1              RTC_ALRMAR_MSK1_Msk
-#define RTC_ALRMAR_ST_Pos            (4U)
-#define RTC_ALRMAR_ST_Msk            (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                RTC_ALRMAR_ST_Msk
-#define RTC_ALRMAR_ST_0              (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1              (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2              (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos            (0U)
-#define RTC_ALRMAR_SU_Msk            (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                RTC_ALRMAR_SU_Msk
-#define RTC_ALRMAR_SU_0              (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1              (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2              (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3              (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_SSCLR_Pos       (31U)
-#define RTC_ALRMASSR_SSCLR_Msk       (0x1UL << RTC_ALRMASSR_SSCLR_Pos)         /*!< 0x80000000 */
-#define RTC_ALRMASSR_SSCLR           RTC_ALRMASSR_SSCLR_Msk
-#define RTC_ALRMASSR_MASKSS_Pos      (24U)
-#define RTC_ALRMASSR_MASKSS_Msk      (0x3FUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS          RTC_ALRMASSR_MASKSS_Msk
-#define RTC_ALRMASSR_MASKSS_0        (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1        (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2        (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3        (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMASSR_MASKSS_4        (0x10UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMASSR_MASKSS_5        (0x20UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos          (0U)
-#define RTC_ALRMASSR_SS_Msk          (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS              RTC_ALRMASSR_SS_Msk
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos          (31U)
-#define RTC_ALRMBR_MSK4_Msk          (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4              RTC_ALRMBR_MSK4_Msk
-#define RTC_ALRMBR_WDSEL_Pos         (30U)
-#define RTC_ALRMBR_WDSEL_Msk         (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL             RTC_ALRMBR_WDSEL_Msk
-#define RTC_ALRMBR_DT_Pos            (28U)
-#define RTC_ALRMBR_DT_Msk            (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                RTC_ALRMBR_DT_Msk
-#define RTC_ALRMBR_DT_0              (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1              (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos            (24U)
-#define RTC_ALRMBR_DU_Msk            (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                RTC_ALRMBR_DU_Msk
-#define RTC_ALRMBR_DU_0              (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1              (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2              (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3              (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos          (23U)
-#define RTC_ALRMBR_MSK3_Msk          (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3              RTC_ALRMBR_MSK3_Msk
-#define RTC_ALRMBR_PM_Pos            (22U)
-#define RTC_ALRMBR_PM_Msk            (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                RTC_ALRMBR_PM_Msk
-#define RTC_ALRMBR_HT_Pos            (20U)
-#define RTC_ALRMBR_HT_Msk            (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                RTC_ALRMBR_HT_Msk
-#define RTC_ALRMBR_HT_0              (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1              (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos            (16U)
-#define RTC_ALRMBR_HU_Msk            (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                RTC_ALRMBR_HU_Msk
-#define RTC_ALRMBR_HU_0              (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1              (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2              (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3              (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos          (15U)
-#define RTC_ALRMBR_MSK2_Msk          (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2              RTC_ALRMBR_MSK2_Msk
-#define RTC_ALRMBR_MNT_Pos           (12U)
-#define RTC_ALRMBR_MNT_Msk           (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT               RTC_ALRMBR_MNT_Msk
-#define RTC_ALRMBR_MNT_0             (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1             (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2             (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos           (8U)
-#define RTC_ALRMBR_MNU_Msk           (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU               RTC_ALRMBR_MNU_Msk
-#define RTC_ALRMBR_MNU_0             (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1             (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2             (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3             (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos          (7U)
-#define RTC_ALRMBR_MSK1_Msk          (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1              RTC_ALRMBR_MSK1_Msk
-#define RTC_ALRMBR_ST_Pos            (4U)
-#define RTC_ALRMBR_ST_Msk            (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                RTC_ALRMBR_ST_Msk
-#define RTC_ALRMBR_ST_0              (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1              (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2              (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos            (0U)
-#define RTC_ALRMBR_SU_Msk            (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                RTC_ALRMBR_SU_Msk
-#define RTC_ALRMBR_SU_0              (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1              (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2              (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3              (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_SSCLR_Pos       (31U)
-#define RTC_ALRMBSSR_SSCLR_Msk       (0x1UL << RTC_ALRMBSSR_SSCLR_Pos)         /*!< 0x80000000 */
-#define RTC_ALRMBSSR_SSCLR           RTC_ALRMBSSR_SSCLR_Msk
-#define RTC_ALRMBSSR_MASKSS_Pos      (24U)
-#define RTC_ALRMBSSR_MASKSS_Msk      (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS          RTC_ALRMBSSR_MASKSS_Msk
-#define RTC_ALRMBSSR_MASKSS_0        (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1        (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2        (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3        (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMBSSR_MASKSS_4        (0x10UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x10000000 */
-#define RTC_ALRMBSSR_MASKSS_5        (0x20UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x20000000 */
-#define RTC_ALRMBSSR_SS_Pos          (0U)
-#define RTC_ALRMBSSR_SS_Msk          (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS              RTC_ALRMBSSR_SS_Msk
-
-/********************  Bits definition for RTC_SR register  *******************/
-#define RTC_SR_SSRUF_Pos             (6U)
-#define RTC_SR_SSRUF_Msk             (0x1UL << RTC_SR_SSRUF_Pos)               /*!< 0x00000040 */
-#define RTC_SR_SSRUF                 RTC_SR_SSRUF_Msk
-#define RTC_SR_ITSF_Pos              (5U)
-#define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                /*!< 0x00000020 */
-#define RTC_SR_ITSF                  RTC_SR_ITSF_Msk
-#define RTC_SR_TSOVF_Pos             (4U)
-#define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)               /*!< 0x00000010 */
-#define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk
-#define RTC_SR_TSF_Pos               (3U)
-#define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                 /*!< 0x00000008 */
-#define RTC_SR_TSF                   RTC_SR_TSF_Msk
-#define RTC_SR_WUTF_Pos              (2U)
-#define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                /*!< 0x00000004 */
-#define RTC_SR_WUTF                  RTC_SR_WUTF_Msk
-#define RTC_SR_ALRBF_Pos             (1U)
-#define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)               /*!< 0x00000002 */
-#define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk
-#define RTC_SR_ALRAF_Pos             (0U)
-#define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)               /*!< 0x00000001 */
-#define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk
-
-/********************  Bits definition for RTC_MISR register  *****************/
-#define RTC_MISR_SSRUMF_Pos          (6U)
-#define RTC_MISR_SSRUMF_Msk          (0x1UL << RTC_MISR_SSRUMF_Pos)            /*!< 0x00000040 */
-#define RTC_MISR_SSRUMF              RTC_MISR_SSRUMF_Msk
-#define RTC_MISR_ITSMF_Pos           (5U)
-#define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)             /*!< 0x00000020 */
-#define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk
-#define RTC_MISR_TSOVMF_Pos          (4U)
-#define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)            /*!< 0x00000010 */
-#define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk
-#define RTC_MISR_TSMF_Pos            (3U)
-#define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)              /*!< 0x00000008 */
-#define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk
-#define RTC_MISR_WUTMF_Pos           (2U)
-#define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)             /*!< 0x00000004 */
-#define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk
-#define RTC_MISR_ALRBMF_Pos          (1U)
-#define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)            /*!< 0x00000002 */
-#define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk
-#define RTC_MISR_ALRAMF_Pos          (0U)
-#define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)            /*!< 0x00000001 */
-#define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk
-
-/********************  Bits definition for RTC_SCR register  ******************/
-#define RTC_SCR_CSSRUF_Pos           (6U)
-#define RTC_SCR_CSSRUF_Msk           (0x1UL << RTC_SCR_CSSRUF_Pos)             /*!< 0x00000040 */
-#define RTC_SCR_CSSRUF               RTC_SCR_CSSRUF_Msk
-#define RTC_SCR_CITSF_Pos            (5U)
-#define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)              /*!< 0x00000020 */
-#define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk
-#define RTC_SCR_CTSOVF_Pos           (4U)
-#define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)             /*!< 0x00000010 */
-#define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk
-#define RTC_SCR_CTSF_Pos             (3U)
-#define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)               /*!< 0x00000008 */
-#define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk
-#define RTC_SCR_CWUTF_Pos            (2U)
-#define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)              /*!< 0x00000004 */
-#define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk
-#define RTC_SCR_CALRBF_Pos           (1U)
-#define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)             /*!< 0x00000002 */
-#define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk
-#define RTC_SCR_CALRAF_Pos           (0U)
-#define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)             /*!< 0x00000001 */
-#define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk
-
-/********************  Bits definition for RTC_ALRABINR register  ******************/
-#define RTC_ALRABINR_SS_Pos          (0U)
-#define RTC_ALRABINR_SS_Msk          (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos)     /*!< 0xFFFFFFFF */
-#define RTC_ALRABINR_SS              RTC_ALRABINR_SS_Msk
-
-/********************  Bits definition for RTC_ALRBBINR register  ******************/
-#define RTC_ALRBBINR_SS_Pos          (0U)
-#define RTC_ALRBBINR_SS_Msk          (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos)     /*!< 0xFFFFFFFF */
-#define RTC_ALRBBINR_SS              RTC_ALRBBINR_SS_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
-#define SPI_CR1_CPOL_Pos            (1U)
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
-#define SPI_CR1_MSTR_Pos            (2U)
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
-
-#define SPI_CR1_BR_Pos              (3U)
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                  /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                  /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                  /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                  /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos             (6U)
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
-#define SPI_CR1_LSBFIRST_Pos        (7U)
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)            /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
-#define SPI_CR1_SSI_Pos             (8U)
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
-#define SPI_CR1_SSM_Pos             (9U)
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                 /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
-#define SPI_CR1_RXONLY_Pos          (10U)
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)              /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
-#define SPI_CR1_CRCL_Pos            (11U)
-#define SPI_CR1_CRCL_Msk            (0x1UL << SPI_CR1_CRCL_Pos)                /*!< 0x00000800 */
-#define SPI_CR1_CRCL                SPI_CR1_CRCL_Msk                           /*!< CRC Length */
-#define SPI_CR1_CRCNEXT_Pos         (12U)
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)             /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
-#define SPI_CR1_CRCEN_Pos           (13U)
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)               /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
-#define SPI_CR1_BIDIOE_Pos          (14U)
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)              /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)            /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)             /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN_Pos         (1U)
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)             /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE_Pos            (2U)
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!< SS Output Enable */
-#define SPI_CR2_NSSP_Pos            (3U)
-#define SPI_CR2_NSSP_Msk            (0x1UL << SPI_CR2_NSSP_Pos)                /*!< 0x00000008 */
-#define SPI_CR2_NSSP                SPI_CR2_NSSP_Msk                           /*!< NSS pulse management Enable */
-#define SPI_CR2_FRF_Pos             (4U)
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                 /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE_Pos           (5U)
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)               /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE_Pos          (6U)
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)              /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)               /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!< Tx buffer Empty Interrupt Enable */
-#define SPI_CR2_DS_Pos              (8U)
-#define SPI_CR2_DS_Msk              (0xFUL << SPI_CR2_DS_Pos)                  /*!< 0x00000F00 */
-#define SPI_CR2_DS                  SPI_CR2_DS_Msk                             /*!< DS[3:0] Data Size */
-#define SPI_CR2_DS_0                (0x1UL << SPI_CR2_DS_Pos)                  /*!< 0x00000100 */
-#define SPI_CR2_DS_1                (0x2UL << SPI_CR2_DS_Pos)                  /*!< 0x00000200 */
-#define SPI_CR2_DS_2                (0x4UL << SPI_CR2_DS_Pos)                  /*!< 0x00000400 */
-#define SPI_CR2_DS_3                (0x8UL << SPI_CR2_DS_Pos)                  /*!< 0x00000800 */
-#define SPI_CR2_FRXTH_Pos           (12U)
-#define SPI_CR2_FRXTH_Msk           (0x1UL << SPI_CR2_FRXTH_Pos)               /*!< 0x00001000 */
-#define SPI_CR2_FRXTH               SPI_CR2_FRXTH_Msk                          /*!< FIFO reception Threshold */
-#define SPI_CR2_LDMARX_Pos          (13U)
-#define SPI_CR2_LDMARX_Msk          (0x1UL << SPI_CR2_LDMARX_Pos)              /*!< 0x00002000 */
-#define SPI_CR2_LDMARX              SPI_CR2_LDMARX_Msk                         /*!< Last DMA transfer for reception */
-#define SPI_CR2_LDMATX_Pos          (14U)
-#define SPI_CR2_LDMATX_Msk          (0x1UL << SPI_CR2_LDMATX_Pos)              /*!< 0x00004000 */
-#define SPI_CR2_LDMATX              SPI_CR2_LDMATX_Msk                         /*!< Last DMA transfer for transmission */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                 /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                  /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)               /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
-#define SPI_SR_CRCERR_Pos           (4U)
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)               /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */
-#define SPI_SR_MODF_Pos             (5U)
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!< Mode fault */
-#define SPI_SR_OVR_Pos              (6U)
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!< Overrun flag */
-#define SPI_SR_BSY_Pos              (7U)
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                  /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!< Busy flag */
-#define SPI_SR_FRE_Pos              (8U)
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                  /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!< TI frame format error */
-#define SPI_SR_FRLVL_Pos            (9U)
-#define SPI_SR_FRLVL_Msk            (0x3UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000600 */
-#define SPI_SR_FRLVL                SPI_SR_FRLVL_Msk                           /*!< FIFO Reception Level */
-#define SPI_SR_FRLVL_0              (0x1UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000200 */
-#define SPI_SR_FRLVL_1              (0x2UL << SPI_SR_FRLVL_Pos)                /*!< 0x00000400 */
-#define SPI_SR_FTLVL_Pos            (11U)
-#define SPI_SR_FTLVL_Msk            (0x3UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001800 */
-#define SPI_SR_FTLVL                SPI_SR_FTLVL_Msk                           /*!< FIFO Transmission Level */
-#define SPI_SR_FTLVL_0              (0x1UL << SPI_SR_FTLVL_Pos)                /*!< 0x00000800 */
-#define SPI_SR_FTLVL_1              (0x2UL << SPI_SR_FTLVL_Pos)                /*!< 0x00001000 */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)        /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)         /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)         /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000004 */
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000020 */
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x00000200 */
-#define SPI_I2SCFGR_I2SE_Pos        (10U)
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)            /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-#define SPI_I2SCFGR_ASTRTEN_Pos     (12U)
-#define SPI_I2SCFGR_ASTRTEN_Msk     (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos)         /*!< 0x00001000 */
-#define SPI_I2SCFGR_ASTRTEN         SPI_I2SCFGR_ASTRTEN_Msk                    /*!<Asynchronous start enable */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)           /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD_Pos           (8U)
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)               /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)             /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Tamper and backup register (TAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for TAMP_CR1 register  *****************/
-#define TAMP_CR1_TAMP1E_Pos          (0U)
-#define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */
-#define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk
-#define TAMP_CR1_TAMP2E_Pos          (1U)
-#define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */
-#define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk
-#define TAMP_CR1_TAMP3E_Pos          (2U)
-#define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */
-#define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk
-#define TAMP_CR1_ITAMP3E_Pos         (18U)
-#define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */
-#define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk
-#define TAMP_CR1_ITAMP5E_Pos         (20U)
-#define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */
-#define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk
-#define TAMP_CR1_ITAMP6E_Pos         (21U)
-#define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x0020000 */
-#define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk
-#define TAMP_CR1_ITAMP8E_Pos         (23U)
-#define TAMP_CR1_ITAMP8E_Msk         (0x1UL << TAMP_CR1_ITAMP8E_Pos)           /*!< 0x00800000 */
-#define TAMP_CR1_ITAMP8E             TAMP_CR1_ITAMP8E_Msk
-
-/********************  Bits definition for TAMP_CR2 register  *****************/
-#define TAMP_CR2_TAMP1NOERASE_Pos    (0U)
-#define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */
-#define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk
-#define TAMP_CR2_TAMP2NOERASE_Pos    (1U)
-#define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */
-#define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk
-#define TAMP_CR2_TAMP3NOERASE_Pos    (2U)
-#define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */
-#define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk
-#define TAMP_CR2_TAMP1MSK_Pos        (16U)
-#define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)          /*!< 0x00010000 */
-#define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk
-#define TAMP_CR2_TAMP2MSK_Pos        (17U)
-#define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)          /*!< 0x00020000 */
-#define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk
-#define TAMP_CR2_TAMP3MSK_Pos        (18U)
-#define TAMP_CR2_TAMP3MSK_Msk        (0x1UL << TAMP_CR2_TAMP3MSK_Pos)          /*!< 0x00040000 */
-#define TAMP_CR2_TAMP3MSK            TAMP_CR2_TAMP3MSK_Msk
-#define TAMP_CR2_BKERASE_Pos         (23U)
-#define TAMP_CR2_BKERASE_Msk         (0x1UL << TAMP_CR2_BKERASE_Pos)           /*!< 0x00800000 */
-#define TAMP_CR2_BKERASE             TAMP_CR2_BKERASE_Msk
-#define TAMP_CR2_TAMP1TRG_Pos        (24U)
-#define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */
-#define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk
-#define TAMP_CR2_TAMP2TRG_Pos        (25U)
-#define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */
-#define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk
-#define TAMP_CR2_TAMP3TRG_Pos        (26U)
-#define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x02000000 */
-#define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk
-
-/********************  Bits definition for TAMP_CR3 register  *****************/
-#define TAMP_CR3_ITAMP3NOER_Pos      (2U)
-#define TAMP_CR3_ITAMP3NOER_Msk      (0x1UL << TAMP_CR3_ITAMP3NOER_Pos)        /*!< 0x00000004 */
-#define TAMP_CR3_ITAMP3NOER          TAMP_CR3_ITAMP3NOER_Msk
-#define TAMP_CR3_ITAMP5NOER_Pos      (4U)
-#define TAMP_CR3_ITAMP5NOER_Msk      (0x1UL << TAMP_CR3_ITAMP5NOER_Pos)        /*!< 0x00000010 */
-#define TAMP_CR3_ITAMP5NOER          TAMP_CR3_ITAMP5NOER_Msk
-#define TAMP_CR3_ITAMP6NOER_Pos      (5U)
-#define TAMP_CR3_ITAMP6NOER_Msk      (0x1UL << TAMP_CR3_ITAMP6NOER_Pos)        /*!< 0x00000020 */
-#define TAMP_CR3_ITAMP6NOER          TAMP_CR3_ITAMP6NOER_Msk
-#define TAMP_CR3_ITAMP8NOER_Pos      (7U)
-#define TAMP_CR3_ITAMP8NOER_Msk      (0x1UL << TAMP_CR3_ITAMP8NOER_Pos)        /*!< 0x00800000 */
-#define TAMP_CR3_ITAMP8NOER          TAMP_CR3_ITAMP8NOER_Msk
-
-/********************  Bits definition for TAMP_FLTCR register  ***************/
-#define TAMP_FLTCR_TAMPFREQ_Pos      (0U)
-#define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000007 */
-#define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk
-#define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000001 */
-#define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000002 */
-#define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)        /*!< 0x00000004 */
-#define TAMP_FLTCR_TAMPFLT_Pos       (3U)
-#define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000018 */
-#define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk
-#define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000008 */
-#define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)         /*!< 0x00000010 */
-#define TAMP_FLTCR_TAMPPRCH_Pos      (5U)
-#define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000060 */
-#define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk
-#define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000020 */
-#define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)        /*!< 0x00000040 */
-#define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)
-#define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)       /*!< 0x00000080 */
-#define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk
-
-/********************  Bits definition for TAMP_IER register  *****************/
-#define TAMP_IER_TAMP1IE_Pos         (0U)
-#define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */
-#define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk
-#define TAMP_IER_TAMP2IE_Pos         (1U)
-#define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */
-#define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk
-#define TAMP_IER_TAMP3IE_Pos         (2U)
-#define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */
-#define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk
-#define TAMP_IER_ITAMP3IE_Pos        (18U)
-#define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */
-#define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk
-#define TAMP_IER_ITAMP5IE_Pos        (20U)
-#define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */
-#define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk
-#define TAMP_IER_ITAMP6IE_Pos        (21U)
-#define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x0020000 */
-#define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk
-#define TAMP_IER_ITAMP8IE_Pos        (23U)
-#define TAMP_IER_ITAMP8IE_Msk        (0x1UL << TAMP_IER_ITAMP8IE_Pos)          /*!< 0x00800000 */
-#define TAMP_IER_ITAMP8IE            TAMP_IER_ITAMP8IE_Msk
-
-/********************  Bits definition for TAMP_SR register  *****************/
-#define TAMP_SR_TAMP1F_Pos           (0U)
-#define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)             /*!< 0x00000001 */
-#define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk
-#define TAMP_SR_TAMP2F_Pos           (1U)
-#define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)            /*!< 0x00000002 */
-#define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk
-#define TAMP_SR_TAMP3F_Pos           (2U)
-#define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)             /*!< 0x00000004 */
-#define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk
-#define TAMP_SR_ITAMP3F_Pos          (18U)
-#define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)           /*!< 0x00040000 */
-#define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk
-#define TAMP_SR_ITAMP5F_Pos          (20U)
-#define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)           /*!< 0x00100000 */
-#define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk
-#define TAMP_SR_ITAMP6F_Pos          (21U)
-#define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)           /*!< 0x0020000 */
-#define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk
-#define TAMP_SR_ITAMP8F_Pos          (23U)
-#define TAMP_SR_ITAMP8F_Msk          (0x1UL << TAMP_SR_ITAMP8F_Pos)           /*!< 0x00800000 */
-#define TAMP_SR_ITAMP8F              TAMP_SR_ITAMP8F_Msk
-
-/********************  Bits definition for TAMP_MISR register  ************ *****/
-#define TAMP_MISR_TAMP1MF_Pos        (0U)
-#define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)          /*!< 0x00000001 */
-#define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk
-#define TAMP_MISR_TAMP2MF_Pos        (1U)
-#define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)          /*!< 0x00000002 */
-#define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk
-#define TAMP_MISR_TAMP3MF_Pos        (2U)
-#define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)          /*!< 0x00000004 */
-#define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk
-#define TAMP_MISR_ITAMP3MF_Pos       (18U)
-#define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)           /*!< 0x00040000 */
-#define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk
-#define TAMP_MISR_ITAMP5MF_Pos       (20U)
-#define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)           /*!< 0x00100000 */
-#define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk
-#define TAMP_MISR_ITAMP6MF_Pos       (21U)
-#define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)           /*!< 0x0020000 */
-#define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk
-#define TAMP_MISR_ITAMP8MF_Pos       (23U)
-#define TAMP_MISR_ITAMP8MF_Msk       (0x1UL << TAMP_MISR_ITAMP8MF_Pos)           /*!< 0x00800000 */
-#define TAMP_MISR_ITAMP8MF           TAMP_MISR_ITAMP8MF_Msk
-
-/********************  Bits definition for TAMP_SMISR register  ************ *****/
-#define TAMP_SMISR_TAMP1MF_Pos       (0U)
-#define TAMP_SMISR_TAMP1MF_Msk       (0x1UL << TAMP_SMISR_TAMP1MF_Pos)         /*!< 0x00000001 */
-#define TAMP_SMISR_TAMP1MF           TAMP_SMISR_TAMP1MF_Msk
-#define TAMP_SMISR_TAMP2MF_Pos       (1U)
-#define TAMP_SMISR_TAMP2MF_Msk       (0x1UL << TAMP_SMISR_TAMP2MF_Pos)         /*!< 0x00000002 */
-#define TAMP_SMISR_TAMP2MF           TAMP_SMISR_TAMP2MF_Msk
-#define TAMP_SMISR_TAMP3MF_Pos       (2U)
-#define TAMP_SMISR_TAMP3MF_Msk       (0x1UL << TAMP_SMISR_TAMP3MF_Pos)         /*!< 0x00000004 */
-#define TAMP_SMISR_TAMP3MF           TAMP_SMISR_TAMP3MF_Msk
-#define TAMP_SMISR_ITAMP3MF_Pos      (18U)
-#define TAMP_SMISR_ITAMP3MF_Msk      (0x1UL << TAMP_SMISR_ITAMP3MF_Pos)        /*!< 0x00040000 */
-#define TAMP_SMISR_ITAMP3MF          TAMP_SMISR_ITAMP3MF_Msk
-#define TAMP_SMISR_ITAMP5MF_Pos      (20U)
-#define TAMP_SMISR_ITAMP5MF_Msk      (0x1UL << TAMP_SMISR_ITAMP5MF_Pos)        /*!< 0x00100000 */
-#define TAMP_SMISR_ITAMP5MF          TAMP_SMISR_ITAMP5MF_Msk
-#define TAMP_SMISR_ITAMP6MF_Pos      (21U)
-#define TAMP_SMISR_ITAMP6MF_Msk      (0x1UL << TAMP_SMISR_ITAMP6MF_Pos)        /*!< 0x0020000 */
-#define TAMP_SMISR_ITAMP6MF          TAMP_SMISR_ITAMP6MF_Msk
-#define TAMP_SMISR_ITAMP8MF_Pos      (23U)
-#define TAMP_SMISR_ITAMP8MF_Msk      (0x1UL << TAMP_SMISR_ITAMP8MF_Pos)        /*!< 0x00800000 */
-#define TAMP_SMISR_ITAMP8MF          TAMP_SMISR_ITAMP8MF_Msk
-
-/********************  Bits definition for TAMP_SCR register  *****************/
-#define TAMP_SCR_CTAMP1F_Pos         (0U)
-#define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)           /*!< 0x00000001 */
-#define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk
-#define TAMP_SCR_CTAMP2F_Pos         (1U)
-#define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)           /*!< 0x00000002 */
-#define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk
-#define TAMP_SCR_CTAMP3F_Pos         (2U)
-#define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)           /*!< 0x00000004 */
-#define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk
-#define TAMP_SCR_CITAMP3F_Pos        (18U)
-#define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)          /*!< 0x00040000 */
-#define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk
-#define TAMP_SCR_CITAMP5F_Pos        (20U)
-#define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)          /*!< 0x00100000 */
-#define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk
-#define TAMP_SCR_CITAMP6F_Pos        (21U)
-#define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)          /*!< 0x0020000 */
-#define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk
-#define TAMP_SCR_CITAMP8F_Pos        (23U)
-#define TAMP_SCR_CITAMP8F_Msk        (0x1UL << TAMP_SCR_CITAMP8F_Pos)          /*!< 0x00800000 */
-#define TAMP_SCR_CITAMP8F            TAMP_SCR_CITAMP8F_Msk
-
-/********************  Bits definition for TAMP_COUNTR register  ***************/
-#define TAMP_COUNTR_Pos               (0U)
-#define TAMP_COUNTR_Msk               (0xFFFFFFFFUL << TAMP_COUNTR_Pos)        /*!< 0xFFFFFFFF */
-#define TAMP_COUNTR                   TAMP_COUNTR_Msk
-
-/********************  Bits definition for TAMP_BKP0R register  ***************/
-#define TAMP_BKP0R_Pos               (0U)
-#define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP0R                   TAMP_BKP0R_Msk
-
-/********************  Bits definition for TAMP_BKP1R register  ****************/
-#define TAMP_BKP1R_Pos               (0U)
-#define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP1R                   TAMP_BKP1R_Msk
-
-/********************  Bits definition for TAMP_BKP2R register  ****************/
-#define TAMP_BKP2R_Pos               (0U)
-#define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP2R                   TAMP_BKP2R_Msk
-
-/********************  Bits definition for TAMP_BKP3R register  ****************/
-#define TAMP_BKP3R_Pos               (0U)
-#define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP3R                   TAMP_BKP3R_Msk
-
-/********************  Bits definition for TAMP_BKP4R register  ****************/
-#define TAMP_BKP4R_Pos               (0U)
-#define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP4R                   TAMP_BKP4R_Msk
-
-/********************  Bits definition for TAMP_BKP5R register  ****************/
-#define TAMP_BKP5R_Pos               (0U)
-#define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP5R                   TAMP_BKP5R_Msk
-
-/********************  Bits definition for TAMP_BKP6R register  ****************/
-#define TAMP_BKP6R_Pos               (0U)
-#define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP6R                   TAMP_BKP6R_Msk
-
-/********************  Bits definition for TAMP_BKP7R register  ****************/
-#define TAMP_BKP7R_Pos               (0U)
-#define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP7R                   TAMP_BKP7R_Msk
-
-/********************  Bits definition for TAMP_BKP8R register  ****************/
-#define TAMP_BKP8R_Pos               (0U)
-#define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP8R                   TAMP_BKP8R_Msk
-
-/********************  Bits definition for TAMP_BKP9R register  ****************/
-#define TAMP_BKP9R_Pos               (0U)
-#define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */
-#define TAMP_BKP9R                   TAMP_BKP9R_Msk
-
-/********************  Bits definition for TAMP_BKP10R register  ***************/
-#define TAMP_BKP10R_Pos              (0U)
-#define TAMP_BKP10R_Msk              (0xFFFFFFFFUL << TAMP_BKP10R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP10R                  TAMP_BKP10R_Msk
-
-/********************  Bits definition for TAMP_BKP11R register  ***************/
-#define TAMP_BKP11R_Pos              (0U)
-#define TAMP_BKP11R_Msk              (0xFFFFFFFFUL << TAMP_BKP11R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP11R                  TAMP_BKP11R_Msk
-
-/********************  Bits definition for TAMP_BKP12R register  ***************/
-#define TAMP_BKP12R_Pos              (0U)
-#define TAMP_BKP12R_Msk              (0xFFFFFFFFUL << TAMP_BKP12R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP12R                  TAMP_BKP12R_Msk
-
-/********************  Bits definition for TAMP_BKP13R register  ***************/
-#define TAMP_BKP13R_Pos              (0U)
-#define TAMP_BKP13R_Msk              (0xFFFFFFFFUL << TAMP_BKP13R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP13R                  TAMP_BKP13R_Msk
-
-/********************  Bits definition for TAMP_BKP14R register  ***************/
-#define TAMP_BKP14R_Pos              (0U)
-#define TAMP_BKP14R_Msk              (0xFFFFFFFFUL << TAMP_BKP14R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP14R                  TAMP_BKP14R_Msk
-
-/********************  Bits definition for TAMP_BKP15R register  ***************/
-#define TAMP_BKP15R_Pos              (0U)
-#define TAMP_BKP15R_Msk              (0xFFFFFFFFUL << TAMP_BKP15R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP15R                  TAMP_BKP15R_Msk
-
-/********************  Bits definition for TAMP_BKP16R register  ***************/
-#define TAMP_BKP16R_Pos              (0U)
-#define TAMP_BKP16R_Msk              (0xFFFFFFFFUL << TAMP_BKP16R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP16R                  TAMP_BKP16R_Msk
-
-/********************  Bits definition for TAMP_BKP17R register  ***************/
-#define TAMP_BKP17R_Pos              (0U)
-#define TAMP_BKP17R_Msk              (0xFFFFFFFFUL << TAMP_BKP17R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP17R                  TAMP_BKP17R_Msk
-
-/********************  Bits definition for TAMP_BKP18R register  ***************/
-#define TAMP_BKP18R_Pos              (0U)
-#define TAMP_BKP18R_Msk              (0xFFFFFFFFUL << TAMP_BKP18R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP18R                  TAMP_BKP18R_Msk
-
-/********************  Bits definition for TAMP_BKP19R register  ***************/
-#define TAMP_BKP19R_Pos              (0U)
-#define TAMP_BKP19R_Msk              (0xFFFFFFFFUL << TAMP_BKP19R_Pos)         /*!< 0xFFFFFFFF */
-#define TAMP_BKP19R                  TAMP_BKP19R_Msk
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  (SYSCFG memory remap register) ***********************************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos              (0U)
-#define SYSCFG_MEMRMP_MEM_MODE_Msk              (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000007 */
-#define SYSCFG_MEMRMP_MEM_MODE                  SYSCFG_MEMRMP_MEM_MODE_Msk                      /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0                (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1                (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000002 */
-#define SYSCFG_MEMRMP_MEM_MODE_2                (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos)           /*!< 0x00000004 */
-
-/*****************  Bit definition for SYSCFG_CFGR1 register  (SYSCFG configuration register 1) ****************************************************************/
-#define SYSCFG_CFGR1_BOOSTEN_Pos                (8U)
-#define SYSCFG_CFGR1_BOOSTEN_Msk                (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos)             /*!< 0x00000100 */
-#define SYSCFG_CFGR1_BOOSTEN                    SYSCFG_CFGR1_BOOSTEN_Msk                        /*!< I/O analog switch voltage booster enable                  */
-#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos            (16U)
-#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)         /*!< 0x00010000 */
-#define SYSCFG_CFGR1_I2C_PB6_FMP                SYSCFG_CFGR1_I2C_PB6_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB6 */
-#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos            (17U)
-#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)         /*!< 0x00020000 */
-#define SYSCFG_CFGR1_I2C_PB7_FMP                SYSCFG_CFGR1_I2C_PB7_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB7 */
-#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos            (18U)
-#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)         /*!< 0x00040000 */
-#define SYSCFG_CFGR1_I2C_PB8_FMP                SYSCFG_CFGR1_I2C_PB8_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB8 */
-#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos            (19U)
-#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk            (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)         /*!< 0x00080000 */
-#define SYSCFG_CFGR1_I2C_PB9_FMP                SYSCFG_CFGR1_I2C_PB9_FMP_Msk                    /*!< Fast-mode Plus (Fm+) driving capability activation on PB9 */
-#define SYSCFG_CFGR1_I2C1_FMP_Pos               (20U)
-#define SYSCFG_CFGR1_I2C1_FMP_Msk               (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos)            /*!< 0x00100000 */
-#define SYSCFG_CFGR1_I2C1_FMP                   SYSCFG_CFGR1_I2C1_FMP_Msk                       /*!< I2C1 Fast-mode Plus (Fm+) driving capability activation   */
-#define SYSCFG_CFGR1_I2C2_FMP_Pos               (21U)
-#define SYSCFG_CFGR1_I2C2_FMP_Msk               (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos)            /*!< 0x00200000 */
-#define SYSCFG_CFGR1_I2C2_FMP                   SYSCFG_CFGR1_I2C2_FMP_Msk                       /*!< I2C2 Fast-mode Plus (Fm+) driving capability activation   */
-#define SYSCFG_CFGR1_I2C3_FMP_Pos               (22U)
-#define SYSCFG_CFGR1_I2C3_FMP_Msk               (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos)            /*!< 0x00400000 */
-#define SYSCFG_CFGR1_I2C3_FMP                   SYSCFG_CFGR1_I2C3_FMP_Msk                       /*!< I2C3 Fast-mode Plus (Fm+) driving capability activation   */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  (External interrupt configuration register 1) ********************************/
-#define SYSCFG_EXTICR1_EXTI0_Pos                (0U)
-#define SYSCFG_EXTICR1_EXTI0_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos)             /*!< 0x00000007 */
-#define SYSCFG_EXTICR1_EXTI0                    SYSCFG_EXTICR1_EXTI0_Msk                        /*!< External Interrupt Line 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos                (4U)
-#define SYSCFG_EXTICR1_EXTI1_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos)             /*!< 0x00000070 */
-#define SYSCFG_EXTICR1_EXTI1                    SYSCFG_EXTICR1_EXTI1_Msk                        /*!< External Interrupt Line 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos                (8U)
-#define SYSCFG_EXTICR1_EXTI2_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos)             /*!< 0x00000700 */
-#define SYSCFG_EXTICR1_EXTI2                    SYSCFG_EXTICR1_EXTI2_Msk                        /*!< External Interrupt Line 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos                (12U)
-#define SYSCFG_EXTICR1_EXTI3_Msk                (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos)             /*!< 0x00007000 */
-#define SYSCFG_EXTICR1_EXTI3                    SYSCFG_EXTICR1_EXTI3_Msk                        /*!< External Interrupt Line 3 configuration */
-
-/**
-  * @brief  External Interrupt Line 0 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA                 (0x00000000U)   /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB                 (0x00000001U)   /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC                 (0x00000002U)   /*!< PC[0] pin */
-
-/**
-  * @brief  External Interrupt Line 1 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI1_PA                 (0x00000000U)   /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB                 (0x00000010U)   /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC                 (0x00000020U)   /*!< PC[1] pin */
-
-/**
-  * @brief  External Interrupt Line 2 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA                 (0x00000000U)   /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB                 (0x00000100U)   /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC                 (0x00000200U)   /*!< PC[2] pin */
-
-/**
-  * @brief  External Interrupt Line 3 Source Input configuration
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA                 (0x00000000U)   /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB                 (0x00001000U)   /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC                 (0x00002000U)   /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  (External interrupt configuration register 2) ********************************/
-#define SYSCFG_EXTICR2_EXTI4_Pos                (0U)
-#define SYSCFG_EXTICR2_EXTI4_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos)             /*!< 0x00000007 */
-#define SYSCFG_EXTICR2_EXTI4                    SYSCFG_EXTICR2_EXTI4_Msk                        /*!< External Interrupt Line 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos                (4U)
-#define SYSCFG_EXTICR2_EXTI5_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos)             /*!< 0x00000070 */
-#define SYSCFG_EXTICR2_EXTI5                    SYSCFG_EXTICR2_EXTI5_Msk                        /*!< External Interrupt Line 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos                (8U)
-#define SYSCFG_EXTICR2_EXTI6_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos)             /*!< 0x00000700 */
-#define SYSCFG_EXTICR2_EXTI6                    SYSCFG_EXTICR2_EXTI6_Msk                        /*!< External Interrupt Line 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos                (12U)
-#define SYSCFG_EXTICR2_EXTI7_Msk                (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos)             /*!< 0x00007000 */
-#define SYSCFG_EXTICR2_EXTI7                    SYSCFG_EXTICR2_EXTI7_Msk                        /*!< External Interrupt Line 7 configuration */
-
-/**
-  * @brief  External Interrupt Line 4 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA                 (0x00000000U)   /*!< PA[4] pin  */
-#define SYSCFG_EXTICR2_EXTI4_PB                 (0x00000001U)   /*!< PB[4] pin  */
-#define SYSCFG_EXTICR2_EXTI4_PC                 (0x00000002U)   /*!< PC[4] pin  */
-
-/**
-  * @brief  External Interrupt Line 5 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA                 (0x00000000U)   /*!< PA[5] pin  */
-#define SYSCFG_EXTICR2_EXTI5_PB                 (0x00000010U)   /*!< PB[5] pin  */
-#define SYSCFG_EXTICR2_EXTI5_PC                 (0x00000020U)   /*!< PC[5] pin  */
-
-/**
-  * @brief  External Interrupt Line 6 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA                 (0x00000000U)   /*!< PA[6] pin  */
-#define SYSCFG_EXTICR2_EXTI6_PB                 (0x00000100U)   /*!< PB[6] pin  */
-#define SYSCFG_EXTICR2_EXTI6_PC                 (0x00000200U)   /*!< PC[6] pin  */
-
-/**
-  * @brief  External Interrupt Line 7 Source Input configuration
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA                 (0x00000000U)   /*!< PA[7] pin  */
-#define SYSCFG_EXTICR2_EXTI7_PB                 (0x00001000U)   /*!< PB[7] pin  */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  (External interrupt configuration register 3) ********************************/
-#define SYSCFG_EXTICR3_EXTI8_Pos                (0U)
-#define SYSCFG_EXTICR3_EXTI8_Msk                (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos)             /*!< 0x00000007 */
-#define SYSCFG_EXTICR3_EXTI8                    SYSCFG_EXTICR3_EXTI8_Msk                        /*!< External Interrupt Line 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos                (4U)
-#define SYSCFG_EXTICR3_EXTI9_Msk                (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos)             /*!< 0x00000070 */
-#define SYSCFG_EXTICR3_EXTI9                    SYSCFG_EXTICR3_EXTI9_Msk                        /*!< External Interrupt Line 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos               (8U)
-#define SYSCFG_EXTICR3_EXTI10_Msk               (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos)            /*!< 0x00000700 */
-#define SYSCFG_EXTICR3_EXTI10                   SYSCFG_EXTICR3_EXTI10_Msk                       /*!< External Interrupt Line 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos               (12U)
-#define SYSCFG_EXTICR3_EXTI11_Msk               (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)            /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                   SYSCFG_EXTICR3_EXTI11_Msk                       /*!< External Interrupt Line 11 configuration */
-
-/**
-  * @brief  External Interrupt Line 8 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA                 (0x00000000U)   /*!< PA[8] pin  */
-#define SYSCFG_EXTICR3_EXTI8_PB                 (0x00000001U)   /*!< PB[8] pin  */
-
-/**
-  * @brief  External Interrupt Line 9 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA                 (0x00000000U)   /*!< PA[9] pin  */
-#define SYSCFG_EXTICR3_EXTI9_PB                 (0x00000010U)   /*!< PB[9] pin  */
-
-/**
-  * @brief  External Interrupt Line 10 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA                (0x00000000U)   /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB                (0x00000100U)   /*!< PB[10] pin */
-
-/**
-  * @brief  External Interrupt Line 11 Source Input configuration
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA                (0x00000000U)   /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB                (0x00001000U)   /*!< PB[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  (External interrupt configuration register 4) *********************************/
-#define SYSCFG_EXTICR4_EXTI12_Pos               (0U)
-#define SYSCFG_EXTICR4_EXTI12_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos)            /*!< 0x00000007 */
-#define SYSCFG_EXTICR4_EXTI12                   SYSCFG_EXTICR4_EXTI12_Msk                       /*!< External Interrupt Line 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos               (4U)
-#define SYSCFG_EXTICR4_EXTI13_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos)            /*!< 0x00000070 */
-#define SYSCFG_EXTICR4_EXTI13                   SYSCFG_EXTICR4_EXTI13_Msk                       /*!< External Interrupt Line 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos               (8U)
-#define SYSCFG_EXTICR4_EXTI14_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos)            /*!< 0x00000700 */
-#define SYSCFG_EXTICR4_EXTI14                   SYSCFG_EXTICR4_EXTI14_Msk                       /*!< External Interrupt Line 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos               (12U)
-#define SYSCFG_EXTICR4_EXTI15_Msk               (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos)            /*!< 0x00007000 */
-#define SYSCFG_EXTICR4_EXTI15                   SYSCFG_EXTICR4_EXTI15_Msk                       /*!< External Interrupt Line 15 configuration */
-
-/**
-  * @brief  External Interrupt Line 12 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA                (0x00000000U)   /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB                (0x00000001U)   /*!< PB[12] pin */
-
-/**
-  * @brief  External Interrupt Line 13 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA                (0x00000000U)   /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB                (0x00000010U)   /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC                (0x00000020U)   /*!< PC[13] pin */
-
-/**
-  * @brief  External Interrupt Line 14 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA                (0x00000000U)   /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB                (0x00000100U)   /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC                (0x00000200U)   /*!< PC[14] pin */
-
-/**
-  * @brief  External Interrupt Line 15 Source Input configuration
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA                (0x00000000U)   /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB                (0x00001000U)   /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC                (0x00002000U)   /*!< PC[15] pin */
-
-/*****************  Bit definition for SYSCFG_SCSR register  (SYSCFG SRAM control and status register) **********************************************************/
-#define SYSCFG_SCSR_SRAM2ER_Pos                 (0U)
-#define SYSCFG_SCSR_SRAM2ER_Msk                 (0x1UL << SYSCFG_SCSR_SRAM2ER_Pos)               /*!< 0x00000001 */
-#define SYSCFG_SCSR_SRAM2ER                     SYSCFG_SCSR_SRAM2ER_Msk                          /*!< SRAM2 Erase                                      */
-#define SYSCFG_SCSR_SRAMBSY_Pos                 (1U)
-#define SYSCFG_SCSR_SRAMBSY_Msk                 (0x1UL << SYSCFG_SCSR_SRAMBSY_Pos)              /*!< 0x00000002 */
-#define SYSCFG_SCSR_SRAMBSY                     SYSCFG_SCSR_SRAMBSY_Msk                         /*!< SRAM2 and SRAM1 busy by erase operation                    */
-#define SYSCFG_SCSR_PKASRAMBSY_Pos              (8U)
-#define SYSCFG_SCSR_PKASRAMBSY_Msk              (0x1UL << SYSCFG_SCSR_PKASRAMBSY_Pos)           /*!< 0x00000100 */
-#define SYSCFG_SCSR_PKASRAMBSY                  SYSCFG_SCSR_PKASRAMBSY_Msk                      /*!< PKA SRAM busy by erase operation                           */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  (SYSCFG configuration register 2) *****************************************************************/
-#define SYSCFG_CFGR2_CLL_Pos                    (0U)
-#define SYSCFG_CFGR2_CLL_Msk                    (0x1UL << SYSCFG_CFGR2_CLL_Pos)                 /*!< 0x00000001 */
-#define SYSCFG_CFGR2_CLL                        SYSCFG_CFGR2_CLL_Msk                            /*!< Cortex M4 LOCKUP (hardfault) output enable                 */
-#define SYSCFG_CFGR2_SPL_Pos                    (1U)
-#define SYSCFG_CFGR2_SPL_Msk                    (0x1UL << SYSCFG_CFGR2_SPL_Pos)                 /*!< 0x00000002 */
-#define SYSCFG_CFGR2_SPL                        SYSCFG_CFGR2_SPL_Msk                            /*!< SRAM2 Parity Lock                                          */
-#define SYSCFG_CFGR2_PVDL_Pos                   (2U)
-#define SYSCFG_CFGR2_PVDL_Msk                   (0x1UL << SYSCFG_CFGR2_PVDL_Pos)                /*!< 0x00000004 */
-#define SYSCFG_CFGR2_PVDL                       SYSCFG_CFGR2_PVDL_Msk                           /*!< PVD Lock                                                   */
-#define SYSCFG_CFGR2_ECCL_Pos                   (3U)
-#define SYSCFG_CFGR2_ECCL_Msk                   (0x1UL << SYSCFG_CFGR2_ECCL_Pos)                /*!< 0x00000008 */
-#define SYSCFG_CFGR2_ECCL                       SYSCFG_CFGR2_ECCL_Msk                           /*!< ECC Lock                                                   */
-#define SYSCFG_CFGR2_SPF_Pos                    (8U)
-#define SYSCFG_CFGR2_SPF_Msk                    (0x1UL << SYSCFG_CFGR2_SPF_Pos)                 /*!< 0x00000100 */
-#define SYSCFG_CFGR2_SPF                        SYSCFG_CFGR2_SPF_Msk                            /*!< SRAM2 Parity Lock                                          */
-
-/*****************  Bit definition for SYSCFG_SWPR register  (SYSCFG SRAM2 write protection register) ***********************************************************/
-#define SYSCFG_SWPR_PAGE0_Pos                   (0U)
-#define SYSCFG_SWPR_PAGE0_Msk                   (0x1UL << SYSCFG_SWPR_PAGE0_Pos)                /*!< 0x00000001 */
-#define SYSCFG_SWPR_PAGE0                       SYSCFG_SWPR_PAGE0_Msk                           /*!< SRAM2 Write protection page 0 (0x20008000 – 0x200083FF)    */
-#define SYSCFG_SWPR_PAGE1_Pos                   (1U)
-#define SYSCFG_SWPR_PAGE1_Msk                   (0x1UL << SYSCFG_SWPR_PAGE1_Pos)                /*!< 0x00000002 */
-#define SYSCFG_SWPR_PAGE1                       SYSCFG_SWPR_PAGE1_Msk                           /*!< SRAM2 Write protection page 1 (0x20008400 – 0x200087FF)    */
-#define SYSCFG_SWPR_PAGE2_Pos                   (2U)
-#define SYSCFG_SWPR_PAGE2_Msk                   (0x1UL << SYSCFG_SWPR_PAGE2_Pos)                /*!< 0x00000004 */
-#define SYSCFG_SWPR_PAGE2                       SYSCFG_SWPR_PAGE2_Msk                           /*!< SRAM2 Write protection page 2 (0x20008800 – 0x20008BFF)    */
-#define SYSCFG_SWPR_PAGE3_Pos                   (3U)
-#define SYSCFG_SWPR_PAGE3_Msk                   (0x1UL << SYSCFG_SWPR_PAGE3_Pos)                /*!< 0x00000008 */
-#define SYSCFG_SWPR_PAGE3                       SYSCFG_SWPR_PAGE3_Msk                           /*!< SRAM2 Write protection page 3 (0x20008C00 – 0x20008FFF)    */
-#define SYSCFG_SWPR_PAGE4_Pos                   (4U)
-#define SYSCFG_SWPR_PAGE4_Msk                   (0x1UL << SYSCFG_SWPR_PAGE4_Pos)                /*!< 0x00000010 */
-#define SYSCFG_SWPR_PAGE4                       SYSCFG_SWPR_PAGE4_Msk                           /*!< SRAM2 Write protection page 4 (0x20009000 – 0x200093FF)    */
-#define SYSCFG_SWPR_PAGE5_Pos                   (5U)
-#define SYSCFG_SWPR_PAGE5_Msk                   (0x1UL << SYSCFG_SWPR_PAGE5_Pos)                /*!< 0x00000020 */
-#define SYSCFG_SWPR_PAGE5                       SYSCFG_SWPR_PAGE5_Msk                           /*!< SRAM2 Write protection page 5 (0x20009400 – 0x200097FF)    */
-#define SYSCFG_SWPR_PAGE6_Pos                   (6U)
-#define SYSCFG_SWPR_PAGE6_Msk                   (0x1UL << SYSCFG_SWPR_PAGE6_Pos)                /*!< 0x00000040 */
-#define SYSCFG_SWPR_PAGE6                       SYSCFG_SWPR_PAGE6_Msk                           /*!< SRAM2 Write protection page 6 (0x20009800 – 0x20009BFF)    */
-#define SYSCFG_SWPR_PAGE7_Pos                   (7U)
-#define SYSCFG_SWPR_PAGE7_Msk                   (0x1UL << SYSCFG_SWPR_PAGE7_Pos)                /*!< 0x00000080 */
-#define SYSCFG_SWPR_PAGE7                       SYSCFG_SWPR_PAGE7_Msk                           /*!< SRAM2 Write protection page 7 (0x20009C00 – 0x20009FFF)    */
-#define SYSCFG_SWPR_PAGE8_Pos                   (8U)
-#define SYSCFG_SWPR_PAGE8_Msk                   (0x1UL << SYSCFG_SWPR_PAGE8_Pos)                /*!< 0x00000100 */
-#define SYSCFG_SWPR_PAGE8                       SYSCFG_SWPR_PAGE8_Msk                           /*!< SRAM2 Write protection page 8 (0x2000A000 – 0x2000A3FF)    */
-#define SYSCFG_SWPR_PAGE9_Pos                   (9U)
-#define SYSCFG_SWPR_PAGE9_Msk                   (0x1UL << SYSCFG_SWPR_PAGE9_Pos)                /*!< 0x00000200 */
-#define SYSCFG_SWPR_PAGE9                       SYSCFG_SWPR_PAGE9_Msk                           /*!< SRAM2 Write protection page 9 (0x2000A400 – 0x2000A7FF)    */
-#define SYSCFG_SWPR_PAGE10_Pos                  (10U)
-#define SYSCFG_SWPR_PAGE10_Msk                  (0x1UL << SYSCFG_SWPR_PAGE10_Pos)               /*!< 0x00000400 */
-#define SYSCFG_SWPR_PAGE10                      SYSCFG_SWPR_PAGE10_Msk                          /*!< SRAM2 Write protection page 10 (0x2000A800 – 0x2000ABFF)   */
-#define SYSCFG_SWPR_PAGE11_Pos                  (11U)
-#define SYSCFG_SWPR_PAGE11_Msk                  (0x1UL << SYSCFG_SWPR_PAGE11_Pos)               /*!< 0x00000800 */
-#define SYSCFG_SWPR_PAGE11                      SYSCFG_SWPR_PAGE11_Msk                          /*!< SRAM2 Write protection page 11 (0x2000AC00 – 0x2000AFFF)   */
-#define SYSCFG_SWPR_PAGE12_Pos                  (12U)
-#define SYSCFG_SWPR_PAGE12_Msk                  (0x1UL << SYSCFG_SWPR_PAGE12_Pos)               /*!< 0x00001000 */
-#define SYSCFG_SWPR_PAGE12                      SYSCFG_SWPR_PAGE12_Msk                          /*!< SRAM2 Write protection page 12 (0x2000B000 – 0x2000B3FF)   */
-#define SYSCFG_SWPR_PAGE13_Pos                  (13U)
-#define SYSCFG_SWPR_PAGE13_Msk                  (0x1UL << SYSCFG_SWPR_PAGE13_Pos)               /*!< 0x00002000 */
-#define SYSCFG_SWPR_PAGE13                      SYSCFG_SWPR_PAGE13_Msk                          /*!< SRAM2 Write protection page 13 (0x2000B400 – 0x2000B7FF)   */
-#define SYSCFG_SWPR_PAGE14_Pos                  (14U)
-#define SYSCFG_SWPR_PAGE14_Msk                  (0x1UL << SYSCFG_SWPR_PAGE14_Pos)               /*!< 0x00004000 */
-#define SYSCFG_SWPR_PAGE14                      SYSCFG_SWPR_PAGE14_Msk                          /*!< SRAM2 Write protection page 14 (0x2000B800 – 0x2000BBFF)   */
-#define SYSCFG_SWPR_PAGE15_Pos                  (15U)
-#define SYSCFG_SWPR_PAGE15_Msk                  (0x1UL << SYSCFG_SWPR_PAGE15_Pos)               /*!< 0x00008000 */
-#define SYSCFG_SWPR_PAGE15                      SYSCFG_SWPR_PAGE15_Msk                          /*!< SRAM2 Write protection page 15 (0x2000BC00 – 0x2000BFFF)   */
-#define SYSCFG_SWPR_PAGE16_Pos                  (16U)
-#define SYSCFG_SWPR_PAGE16_Msk                  (0x1UL << SYSCFG_SWPR_PAGE16_Pos)               /*!< 0x00010000 */
-#define SYSCFG_SWPR_PAGE16                      SYSCFG_SWPR_PAGE16_Msk                          /*!< SRAM2 Write protection page 16 (0x2000C000 – 0x2000C3FF)   */
-#define SYSCFG_SWPR_PAGE17_Pos                  (17U)
-#define SYSCFG_SWPR_PAGE17_Msk                  (0x1UL << SYSCFG_SWPR_PAGE17_Pos)               /*!< 0x00020000 */
-#define SYSCFG_SWPR_PAGE17                      SYSCFG_SWPR_PAGE17_Msk                          /*!< SRAM2 Write protection page 17 (0x2000C400 – 0x2000C7FF)   */
-#define SYSCFG_SWPR_PAGE18_Pos                  (18U)
-#define SYSCFG_SWPR_PAGE18_Msk                  (0x1UL << SYSCFG_SWPR_PAGE18_Pos)               /*!< 0x00040000 */
-#define SYSCFG_SWPR_PAGE18                      SYSCFG_SWPR_PAGE18_Msk                          /*!< SRAM2 Write protection page 18 (0x2000C800 – 0x2000CBFF)   */
-#define SYSCFG_SWPR_PAGE19_Pos                  (19U)
-#define SYSCFG_SWPR_PAGE19_Msk                  (0x1UL << SYSCFG_SWPR_PAGE19_Pos)               /*!< 0x00080000 */
-#define SYSCFG_SWPR_PAGE19                      SYSCFG_SWPR_PAGE19_Msk                          /*!< SRAM2 Write protection page 19 (0x2000CC00 – 0x2000CFFF)   */
-#define SYSCFG_SWPR_PAGE20_Pos                  (20U)
-#define SYSCFG_SWPR_PAGE20_Msk                  (0x1UL << SYSCFG_SWPR_PAGE20_Pos)               /*!< 0x00100000 */
-#define SYSCFG_SWPR_PAGE20                      SYSCFG_SWPR_PAGE20_Msk                          /*!< SRAM2 Write protection page 20 (0x2000D000 – 0x2000D3FF)   */
-#define SYSCFG_SWPR_PAGE21_Pos                  (21U)
-#define SYSCFG_SWPR_PAGE21_Msk                  (0x1UL << SYSCFG_SWPR_PAGE21_Pos)               /*!< 0x00200000 */
-#define SYSCFG_SWPR_PAGE21                      SYSCFG_SWPR_PAGE21_Msk                          /*!< SRAM2 Write protection page 21 (0x2000D400 – 0x2000D7FF)   */
-#define SYSCFG_SWPR_PAGE22_Pos                  (22U)
-#define SYSCFG_SWPR_PAGE22_Msk                  (0x1UL << SYSCFG_SWPR_PAGE22_Pos)               /*!< 0x00400000 */
-#define SYSCFG_SWPR_PAGE22                      SYSCFG_SWPR_PAGE22_Msk                          /*!< SRAM2 Write protection page 22 (0x2000D800 – 0x2000DBFF)   */
-#define SYSCFG_SWPR_PAGE23_Pos                  (23U)
-#define SYSCFG_SWPR_PAGE23_Msk                  (0x1UL << SYSCFG_SWPR_PAGE23_Pos)               /*!< 0x00800000 */
-#define SYSCFG_SWPR_PAGE23                      SYSCFG_SWPR_PAGE23_Msk                          /*!< SRAM2 Write protection page 23 (0x2000DC00 – 0x2000DFFF)   */
-#define SYSCFG_SWPR_PAGE24_Pos                  (24U)
-#define SYSCFG_SWPR_PAGE24_Msk                  (0x1UL << SYSCFG_SWPR_PAGE24_Pos)               /*!< 0x01000000 */
-#define SYSCFG_SWPR_PAGE24                      SYSCFG_SWPR_PAGE24_Msk                          /*!< SRAM2 Write protection page 24 (0x2000E000 – 0x2000E3FF)   */
-#define SYSCFG_SWPR_PAGE25_Pos                  (25U)
-#define SYSCFG_SWPR_PAGE25_Msk                  (0x1UL << SYSCFG_SWPR_PAGE25_Pos)               /*!< 0x02000000 */
-#define SYSCFG_SWPR_PAGE25                      SYSCFG_SWPR_PAGE25_Msk                          /*!< SRAM2 Write protection page 25 (0x2000E400 – 0x2000E7FF)   */
-#define SYSCFG_SWPR_PAGE26_Pos                  (26U)
-#define SYSCFG_SWPR_PAGE26_Msk                  (0x1UL << SYSCFG_SWPR_PAGE26_Pos)               /*!< 0x04000000 */
-#define SYSCFG_SWPR_PAGE26                      SYSCFG_SWPR_PAGE26_Msk                          /*!< SRAM2 Write protection page 26 (0x2000E800 – 0x2000EBFF)   */
-#define SYSCFG_SWPR_PAGE27_Pos                  (27U)
-#define SYSCFG_SWPR_PAGE27_Msk                  (0x1UL << SYSCFG_SWPR_PAGE27_Pos)               /*!< 0x08000000 */
-#define SYSCFG_SWPR_PAGE27                      SYSCFG_SWPR_PAGE27_Msk                          /*!< SRAM2 Write protection page 27 (0x2000EC00 – 0x2000EFFF)   */
-#define SYSCFG_SWPR_PAGE28_Pos                  (28U)
-#define SYSCFG_SWPR_PAGE28_Msk                  (0x1UL << SYSCFG_SWPR_PAGE28_Pos)               /*!< 0x10000000 */
-#define SYSCFG_SWPR_PAGE28                      SYSCFG_SWPR_PAGE28_Msk                          /*!< SRAM2 Write protection page 28 (0x2000F000 – 0x2000F3FF)   */
-#define SYSCFG_SWPR_PAGE29_Pos                  (29U)
-#define SYSCFG_SWPR_PAGE29_Msk                  (0x1UL << SYSCFG_SWPR_PAGE29_Pos)               /*!< 0x20000000 */
-#define SYSCFG_SWPR_PAGE29                      SYSCFG_SWPR_PAGE29_Msk                          /*!< SRAM2 Write protection page 29 (0x2000F400 – 0x2000F7FF)   */
-#define SYSCFG_SWPR_PAGE30_Pos                  (30U)
-#define SYSCFG_SWPR_PAGE30_Msk                  (0x1UL << SYSCFG_SWPR_PAGE30_Pos)               /*!< 0x40000000 */
-#define SYSCFG_SWPR_PAGE30                      SYSCFG_SWPR_PAGE30_Msk                          /*!< SRAM2 Write protection page 30 (0x2000F800 – 0x2000FBFF)   */
-#define SYSCFG_SWPR_PAGE31_Pos                  (31U)
-#define SYSCFG_SWPR_PAGE31_Msk                  (0x1UL << SYSCFG_SWPR_PAGE31_Pos)               /*!< 0x80000000 */
-#define SYSCFG_SWPR_PAGE31                      SYSCFG_SWPR_PAGE31_Msk                          /*!< SRAM2 Write protection page 31 (0x2000FC00 – 0x2000FFFF)   */
-
-/*****************  Bit definition for SYSCFG_SKR register  (SYSCFG SRAM2 key register) *************************************************************************/
-#define SYSCFG_SKR_KEY_Pos                      (0U)
-#define SYSCFG_SKR_KEY_Msk                      (0xFFUL << SYSCFG_SKR_KEY_Pos)                  /*!< 0x000000FF */
-#define SYSCFG_SKR_KEY                          SYSCFG_SKR_KEY_Msk                              /*!< SRAM2 write protection key for software erase              */
-
-/**************************************  Bit definition for SYSCFG_RFDCR register (SYSCFG radio debug control register) ************************************************/
-#define SYSCFG_RFDCR_RFTBSEL_Pos                (0U)
-#define SYSCFG_RFDCR_RFTBSEL_Msk                (0x1UL << SYSCFG_RFDCR_RFTBSEL_Pos)             /*!< 0x00000001 */
-#define SYSCFG_RFDCR_RFTBSEL                    SYSCFG_RFDCR_RFTBSEL_Msk                        /*!< Radio debug test bus selection                                    */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface (I2C)              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE_Pos               (0U)
-#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */
-#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */
-#define I2C_CR1_TXIE_Pos             (1U)
-#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */
-#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */
-#define I2C_CR1_RXIE_Pos             (2U)
-#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */
-#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE_Pos           (3U)
-#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */
-#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE_Pos           (4U)
-#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */
-#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE_Pos           (5U)
-#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */
-#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE_Pos             (6U)
-#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */
-#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE_Pos            (7U)
-#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */
-#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */
-#define I2C_CR1_DNF_Pos              (8U)
-#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */
-#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF_Pos           (12U)
-#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */
-#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN_Pos          (14U)
-#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */
-#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN_Pos          (15U)
-#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */
-#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */
-#define I2C_CR1_SBC_Pos              (16U)
-#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */
-#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH_Pos        (17U)
-#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */
-#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN_Pos            (18U)
-#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */
-#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN_Pos             (19U)
-#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */
-#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */
-#define I2C_CR1_SMBHEN_Pos           (20U)
-#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */
-#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN_Pos           (21U)
-#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */
-#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN_Pos          (22U)
-#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */
-#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */
-#define I2C_CR1_PECEN_Pos            (23U)
-#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */
-#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD_Pos             (0U)
-#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */
-#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN_Pos           (10U)
-#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */
-#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10_Pos            (11U)
-#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */
-#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R_Pos          (12U)
-#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */
-#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START_Pos            (13U)
-#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */
-#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */
-#define I2C_CR2_STOP_Pos             (14U)
-#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */
-#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK_Pos             (15U)
-#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */
-#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES_Pos           (16U)
-#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */
-#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */
-#define I2C_CR2_RELOAD_Pos           (24U)
-#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */
-#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND_Pos          (25U)
-#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */
-#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE_Pos          (26U)
-#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */
-#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1_Pos             (0U)
-#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */
-#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE_Pos         (10U)
-#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */
-#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN_Pos           (15U)
-#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */
-#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2_Pos             (1U)
-#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */
-#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK_Pos          (8U)
-#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */
-#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */
-#define I2C_OAR2_OA2NOMASK           (0x00000000UL)                            /*!< No mask                                        */
-#define I2C_OAR2_OA2MASK01_Pos       (8U)
-#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */
-#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared   */
-#define I2C_OAR2_OA2MASK02_Pos       (9U)
-#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */
-#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
-#define I2C_OAR2_OA2MASK03_Pos       (8U)
-#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */
-#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
-#define I2C_OAR2_OA2MASK04_Pos       (10U)
-#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */
-#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
-#define I2C_OAR2_OA2MASK05_Pos       (8U)
-#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */
-#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
-#define I2C_OAR2_OA2MASK06_Pos       (9U)
-#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */
-#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared   */
-#define I2C_OAR2_OA2MASK07_Pos       (8U)
-#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */
-#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done      */
-#define I2C_OAR2_OA2EN_Pos           (15U)
-#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */
-#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL_Pos         (0U)
-#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */
-#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH_Pos         (8U)
-#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */
-#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL_Pos       (16U)
-#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */
-#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL_Pos       (20U)
-#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */
-#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */
-#define I2C_TIMINGR_PRESC_Pos        (28U)
-#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */
-#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)
-#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */
-#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE_Pos       (12U)
-#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */
-#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)
-#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */
-#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)
-#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */
-#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)
-#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */
-#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE_Pos              (0U)
-#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */
-#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */
-#define I2C_ISR_TXIS_Pos             (1U)
-#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */
-#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE_Pos             (2U)
-#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */
-#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */
-#define I2C_ISR_ADDR_Pos             (3U)
-#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */
-#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF_Pos            (4U)
-#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */
-#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */
-#define I2C_ISR_STOPF_Pos            (5U)
-#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */
-#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */
-#define I2C_ISR_TC_Pos               (6U)
-#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */
-#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR_Pos              (7U)
-#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */
-#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */
-#define I2C_ISR_BERR_Pos             (8U)
-#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */
-#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */
-#define I2C_ISR_ARLO_Pos             (9U)
-#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */
-#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */
-#define I2C_ISR_OVR_Pos              (10U)
-#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */
-#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR_Pos           (11U)
-#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */
-#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT_Pos          (12U)
-#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */
-#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT_Pos            (13U)
-#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */
-#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */
-#define I2C_ISR_BUSY_Pos             (15U)
-#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */
-#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */
-#define I2C_ISR_DIR_Pos              (16U)
-#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */
-#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE_Pos          (17U)
-#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */
-#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF_Pos           (3U)
-#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */
-#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF_Pos           (4U)
-#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */
-#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF_Pos           (5U)
-#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */
-#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF_Pos           (8U)
-#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */
-#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF_Pos           (9U)
-#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */
-#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF_Pos            (10U)
-#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */
-#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF_Pos            (11U)
-#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */
-#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF_Pos         (12U)
-#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */
-#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF_Pos          (13U)
-#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */
-#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC_Pos             (0U)
-#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */
-#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA_Pos          (0U)
-#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */
-#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA_Pos          (0U)
-#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */
-#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos      (0U)
-#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */
-#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos       (0U)
-#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */
-#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */
-#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                         /*!< 0x00000001 */
-#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                         /*!< 0x00000002 */
-#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                         /*!< 0x00000004 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos      (0U)
-#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */
-#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos      (0U)
-#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */
-#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU_Pos      (1U)
-#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */
-#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU_Pos      (2U)
-#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */
-#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN_Pos    (0U)
-#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */
-#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 VREFBUF                                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for VREFBUF_CSR register  ****************/
-#define VREFBUF_CSR_ENVR_Pos    (0U)
-#define VREFBUF_CSR_ENVR_Msk    (0x1UL << VREFBUF_CSR_ENVR_Pos)                /*!< 0x00000001 */
-#define VREFBUF_CSR_ENVR        VREFBUF_CSR_ENVR_Msk                           /*!<Voltage reference buffer enable */
-#define VREFBUF_CSR_HIZ_Pos     (1U)
-#define VREFBUF_CSR_HIZ_Msk     (0x1UL << VREFBUF_CSR_HIZ_Pos)                 /*!< 0x00000002 */
-#define VREFBUF_CSR_HIZ         VREFBUF_CSR_HIZ_Msk                            /*!<High impedance mode             */
-#define VREFBUF_CSR_VRS_Pos     (2U)
-#define VREFBUF_CSR_VRS_Msk     (0x1UL << VREFBUF_CSR_VRS_Pos)                 /*!< 0x00000004 */
-#define VREFBUF_CSR_VRS         VREFBUF_CSR_VRS_Msk                            /*!<Voltage reference buffer ready  */
-#define VREFBUF_CSR_VRR_Pos     (3U)
-#define VREFBUF_CSR_VRR_Msk     (0x1UL << VREFBUF_CSR_VRR_Pos)                 /*!< 0x00000008 */
-#define VREFBUF_CSR_VRR         VREFBUF_CSR_VRR_Msk                            /*!<Voltage reference scale         */
-
-/*******************  Bit definition for VREFBUF_CCR register  ******************/
-#define VREFBUF_CCR_TRIM_Pos    (0U)
-#define VREFBUF_CCR_TRIM_Msk    (0x3FUL << VREFBUF_CCR_TRIM_Pos)               /*!< 0x0000003F */
-#define VREFBUF_CCR_TRIM        VREFBUF_CCR_TRIM_Msk                           /*!<TRIM[5:0] bits (Trimming code)  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                      /*!< 0x00000001 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                      /*!< 0x00000002 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                      /*!< 0x00000004 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                      /*!< 0x00000008 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                      /*!< 0x00000010 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                      /*!< 0x00000020 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                      /*!< 0x00000040 */
-
-#define WWDG_CR_WDGA_Pos        (7U)
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                     /*!< 0x00000001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                     /*!< 0x00000002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                     /*!< 0x00000004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                     /*!< 0x00000008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                     /*!< 0x00000010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                     /*!< 0x00000020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                     /*!< 0x00000040 */
-
-#define WWDG_CFR_EWI_Pos        (9U)
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
-
-#define WWDG_CFR_WDGTB_Pos      (11U)
-#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00000800 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00001000 */
-#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00002000 */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                Debug MCU                                   */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                          (0U)
-#define DBGMCU_IDCODE_DEV_ID_Msk                          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                              DBGMCU_IDCODE_DEV_ID_Msk
-#define DBGMCU_IDCODE_REV_ID_Pos                          (16U)
-#define DBGMCU_IDCODE_REV_ID_Msk                          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                              DBGMCU_IDCODE_REV_ID_Msk
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                           (0U)
-#define DBGMCU_CR_DBG_SLEEP_Msk                           (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)  /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                               DBGMCU_CR_DBG_SLEEP_Msk
-#define DBGMCU_CR_DBG_STOP_Pos                            (1U)
-#define DBGMCU_CR_DBG_STOP_Msk                            (0x1UL << DBGMCU_CR_DBG_STOP_Pos)   /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                                DBGMCU_CR_DBG_STOP_Msk
-#define DBGMCU_CR_DBG_STANDBY_Pos                         (2U)
-#define DBGMCU_CR_DBG_STANDBY_Msk                         (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                             DBGMCU_CR_DBG_STANDBY_Msk
-
-/********************  Bit definition for DBGMCU_APB1FZR1 register  ***********/
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos                 (0U)
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)  /*!< 0x00000001 */
-#define DBGMCU_APB1FZR1_DBG_TIM2_STOP                     DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos                  (10U)
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk                  (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)   /*!< 0x00000400 */
-#define DBGMCU_APB1FZR1_DBG_RTC_STOP                      DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos                 (11U)
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)  /*!< 0x00000800 */
-#define DBGMCU_APB1FZR1_DBG_WWDG_STOP                     DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos                 (12U)
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)  /*!< 0x00001000 */
-#define DBGMCU_APB1FZR1_DBG_IWDG_STOP                     DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos                 (21U)
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)  /*!< 0x00200000 */
-#define DBGMCU_APB1FZR1_DBG_I2C1_STOP                     DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos                 (22U)
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)  /*!< 0x00400000 */
-#define DBGMCU_APB1FZR1_DBG_I2C2_STOP                     DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos                 (23U)
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk                 (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)  /*!< 0x00800000 */
-#define DBGMCU_APB1FZR1_DBG_I2C3_STOP                     DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos               (31U)
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk               (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
-#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP                   DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
-
-/********************  Bit definition for DBGMCU_APB1FZR2 register  ***********/
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos               (5U)
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk               (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos)/*!< 0x00000020 */
-#define DBGMCU_APB1FZR2_DBG_LPTIM2_STOP                   DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk
-#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Pos               (6U)
-#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk               (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Pos)/*!< 0x00000040 */
-#define DBGMCU_APB1FZR2_DBG_LPTIM3_STOP                   DBGMCU_APB1FZR2_DBG_LPTIM3_STOP_Msk
-
-/********************  Bit definition for DBGMCU_APB2FZR register  ************/
-#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos                  (11U)
-#define DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk                  (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos)/*!< 0x000000800 */
-#define DBGMCU_APB2FZR_DBG_TIM1_STOP                      DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk
-#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos                 (17U)
-#define DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk                 (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
-#define DBGMCU_APB2FZR_DBG_TIM16_STOP                     DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk
-#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos                 (18U)
-#define DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk                 (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
-#define DBGMCU_APB2FZR_DBG_TIM17_STOP                     DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */
-#define TIM_CR1_UDIS_Pos          (1U)
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */
-#define TIM_CR1_URS_Pos           (2U)
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */
-#define TIM_CR1_DIR_Pos           (4U)
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */
-
-#define TIM_CR1_CMS_Pos           (5U)
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD_Pos           (8U)
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000200 */
-
-#define TIM_CR1_UIFREMAP_Pos      (11U)
-#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */
-#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCPC_Pos          (0U)
-#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */
-#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS_Pos          (2U)
-#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */
-#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS_Pos          (3U)
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS_Pos           (4U)
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-#define TIM_CR2_OIS1_Pos          (8U)
-#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */
-#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N_Pos         (9U)
-#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */
-#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2_Pos          (10U)
-#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */
-#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N_Pos         (11U)
-#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */
-#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3_Pos          (12U)
-#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */
-#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N_Pos         (13U)
-#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */
-#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4_Pos          (14U)
-#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */
-#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */
-#define TIM_CR2_OIS5_Pos          (16U)
-#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */
-#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 5 (OC5 output) */
-#define TIM_CR2_OIS6_Pos          (18U)
-#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00040000 */
-#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 6 (OC6 output) */
-
-#define TIM_CR2_MMS2_Pos          (20U)
-#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */
-#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00100000 */
-#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00200000 */
-#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00400000 */
-#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                  /*!< 0x00800000 */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)
-#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000001 */
-#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000002 */
-#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)              /*!< 0x00000004 */
-#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010000 */
-
-#define TIM_SMCR_OCCS_Pos         (3U)
-#define TIM_SMCR_OCCS_Msk         (0x1UL << TIM_SMCR_OCCS_Pos)                 /*!< 0x00000008 */
-#define TIM_SMCR_OCCS             TIM_SMCR_OCCS_Msk                            /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS_Pos           (4U)
-#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)               /*!< 0x00000010 */
-#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)               /*!< 0x00000020 */
-#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)               /*!< 0x00000040 */
-#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)               /*!< 0x00100000 */
-#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)               /*!< 0x00200000 */
-
-#define TIM_SMCR_MSM_Pos          (7U)
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF_Pos          (8U)
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00001000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00002000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */
-#define TIM_SMCR_ETP_Pos          (15U)
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE_Pos        (2U)
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE_Pos        (3U)
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE_Pos        (4U)
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE_Pos        (5U)
-#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */
-#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */
-#define TIM_DIER_TIE_Pos          (6U)
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */
-#define TIM_DIER_BIE_Pos          (7U)
-#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */
-#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */
-#define TIM_DIER_UDE_Pos          (8U)
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE_Pos        (9U)
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE_Pos        (13U)
-#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */
-#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */
-#define TIM_DIER_TDE_Pos          (14U)
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF_Pos          (1U)
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF_Pos          (2U)
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF_Pos          (3U)
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF_Pos          (4U)
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF_Pos          (5U)
-#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */
-#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */
-#define TIM_SR_TIF_Pos            (6U)
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF_Pos            (7U)
-#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */
-#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */
-#define TIM_SR_B2IF_Pos           (8U)
-#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */
-#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break 2 interrupt Flag */
-#define TIM_SR_CC1OF_Pos          (9U)
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-#define TIM_SR_SBIF_Pos           (13U)
-#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */
-#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!<System Break interrupt Flag */
-#define TIM_SR_CC5IF_Pos          (16U)
-#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */
-#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */
-#define TIM_SR_CC6IF_Pos          (17U)
-#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */
-#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */
-
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */
-#define TIM_EGR_CC1G_Pos          (1U)
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G_Pos          (2U)
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G_Pos          (3U)
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G_Pos          (4U)
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG_Pos          (5U)
-#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */
-#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG_Pos            (6U)
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */
-#define TIM_EGR_BG_Pos            (7U)
-#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */
-#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */
-#define TIM_EGR_B2G_Pos           (8U)
-#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */
-#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break 2 Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE_Pos       (3U)
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)
-#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000010 */
-#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000020 */
-#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00000040 */
-#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010000 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1 Clear Enable */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE_Pos       (11U)
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)
-#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00001000 */
-#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00002000 */
-#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x00004000 */
-#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01000000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-#define TIM_CCMR1_IC1PSC_Pos      (2U)
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x00000008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                /*!< 0x00000080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00001000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00002000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00004000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE_Pos       (3U)
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)
-#define TIM_CCMR2_OC3M_Msk        (0x1007UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x0001UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000010 */
-#define TIM_CCMR2_OC3M_1          (0x0002UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000020 */
-#define TIM_CCMR2_OC3M_2          (0x0004UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00000040 */
-#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)             /*!< 0x00010000 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE_Pos       (11U)
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)
-#define TIM_CCMR2_OC4M_Msk        (0x1007UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x0001UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00001000 */
-#define TIM_CCMR2_OC4M_1          (0x0002UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00002000 */
-#define TIM_CCMR2_OC4M_2          (0x0004UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x00004000 */
-#define TIM_CCMR2_OC4M_3          (0x1000UL << TIM_CCMR2_OC4M_Pos)             /*!< 0x01000000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-#define TIM_CCMR2_IC3PSC_Pos      (2U)
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x00000008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                /*!< 0x00000080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00001000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00002000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00004000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                /*!< 0x00008000 */
-
-/******************  Bit definition for TIM_CCMR3 register  *******************/
-#define TIM_CCMR3_OC5FE_Pos       (2U)
-#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */
-#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */
-#define TIM_CCMR3_OC5PE_Pos       (3U)
-#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */
-#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */
-
-#define TIM_CCMR3_OC5M_Pos        (4U)
-#define TIM_CCMR3_OC5M_Msk        (0x1007UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010070 */
-#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
-#define TIM_CCMR3_OC5M_0          (0x0001UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000010 */
-#define TIM_CCMR3_OC5M_1          (0x0002UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000020 */
-#define TIM_CCMR3_OC5M_2          (0x0004UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00000040 */
-#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)             /*!< 0x00010000 */
-
-#define TIM_CCMR3_OC5CE_Pos       (7U)
-#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */
-#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */
-
-#define TIM_CCMR3_OC6FE_Pos       (10U)
-#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */
-#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 6 Fast enable */
-#define TIM_CCMR3_OC6PE_Pos       (11U)
-#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */
-#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 6 Preload enable */
-
-#define TIM_CCMR3_OC6M_Pos        (12U)
-#define TIM_CCMR3_OC6M_Msk        (0x1007UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01007000 */
-#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
-#define TIM_CCMR3_OC6M_0          (0x0001UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00001000 */
-#define TIM_CCMR3_OC6M_1          (0x0002UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00002000 */
-#define TIM_CCMR3_OC6M_2          (0x0004UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x00004000 */
-#define TIM_CCMR3_OC6M_3          (0x1000UL << TIM_CCMR3_OC6M_Pos)             /*!< 0x01000000 */
-
-#define TIM_CCMR3_OC6CE_Pos       (15U)
-#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */
-#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 6 Clear Enable */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P_Pos         (1U)
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE_Pos        (2U)
-#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */
-#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP_Pos        (3U)
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P_Pos         (5U)
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE_Pos        (6U)
-#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */
-#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP_Pos        (7U)
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P_Pos         (9U)
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE_Pos        (10U)
-#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */
-#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP_Pos        (11U)
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P_Pos         (13U)
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP_Pos        (15U)
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-#define TIM_CCER_CC5E_Pos         (16U)
-#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */
-#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */
-#define TIM_CCER_CC5P_Pos         (17U)
-#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */
-#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */
-#define TIM_CCER_CC6E_Pos         (20U)
-#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */
-#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */
-#define TIM_CCER_CC6P_Pos         (21U)
-#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */
-#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)
-#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */
-#define TIM_CNT_UIFCPY_Pos        (31U)
-#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */
-#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy (if UIFREMAP=1) */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)
-#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<Actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define TIM_RCR_REP_Pos           (0U)
-#define TIM_RCR_REP_Msk           (0xFFFFUL << TIM_RCR_REP_Pos)                /*!< 0x0000FFFF */
-#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)
-#define TIM_CCR1_CCR1_Msk         (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)
-#define TIM_CCR2_CCR2_Msk         (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)
-#define TIM_CCR3_CCR3_Msk         (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)
-#define TIM_CCR4_CCR4_Msk         (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos)          /*!< 0xFFFFFFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_CCR5 register  *******************/
-#define TIM_CCR5_CCR5_Pos         (0U)
-#define TIM_CCR5_CCR5_Msk         (0xFFFFUL << TIM_CCR5_CCR5_Pos)              /*!< 0x0000FFFF */
-#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */
-#define TIM_CCR5_GC5C1_Pos        (29U)
-#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */
-#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */
-#define TIM_CCR5_GC5C2_Pos        (30U)
-#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */
-#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */
-#define TIM_CCR5_GC5C3_Pos        (31U)
-#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */
-#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */
-
-/*******************  Bit definition for TIM_CCR6 register  *******************/
-#define TIM_CCR6_CCR6_Pos         (0U)
-#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */
-#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define TIM_BDTR_DTG_Pos          (0U)
-#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
-#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
-#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
-#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
-#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
-#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
-#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
-#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
-#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000080 */
-
-#define TIM_BDTR_LOCK_Pos         (8U)
-#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
-#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
-#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000200 */
-
-#define TIM_BDTR_OSSI_Pos         (10U)
-#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
-#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR_Pos         (11U)
-#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
-#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE_Pos          (12U)
-#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
-#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
-#define TIM_BDTR_BKP_Pos          (13U)
-#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
-#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
-#define TIM_BDTR_AOE_Pos          (14U)
-#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
-#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
-#define TIM_BDTR_MOE_Pos          (15U)
-#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
-#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
-
-#define TIM_BDTR_BKF_Pos          (16U)
-#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
-#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break 1 */
-#define TIM_BDTR_BK2F_Pos         (20U)
-#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */
-#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break 2 */
-
-#define TIM_BDTR_BK2E_Pos         (24U)
-#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */
-#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break 2 */
-#define TIM_BDTR_BK2P_Pos         (25U)
-#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */
-#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break 2 */
-
-
-#define TIM_BDTR_BKDSRM_Pos       (26U)
-#define TIM_BDTR_BKDSRM_Msk       (0x1UL << TIM_BDTR_BKDSRM_Pos)               /*!< 0x04000000 */
-#define TIM_BDTR_BKDSRM           TIM_BDTR_BKDSRM_Msk                          /*!<Break disarming/re-arming */
-#define TIM_BDTR_BK2DSRM_Pos      (27U)
-#define TIM_BDTR_BK2DSRM_Msk      (0x1UL << TIM_BDTR_BK2DSRM_Pos)              /*!< 0x08000000 */
-#define TIM_BDTR_BK2DSRM          TIM_BDTR_BK2DSRM_Msk                         /*!<Break2 disarming/re-arming */
-
-#define TIM_BDTR_BKBID_Pos        (28U)
-#define TIM_BDTR_BKBID_Msk        (0x1UL << TIM_BDTR_BKBID_Pos)                /*!< 0x10000000 */
-#define TIM_BDTR_BKBID            TIM_BDTR_BKBID_Msk                           /*!<Break BIDirectional */
-#define TIM_BDTR_BK2BID_Pos       (29U)
-#define TIM_BDTR_BK2BID_Msk       (0x1UL << TIM_BDTR_BK2BID_Pos)               /*!< 0x20000000 */
-#define TIM_BDTR_BK2BID           TIM_BDTR_BK2BID_Msk                          /*!<Break2 BIDirectional */
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                  /*!< 0x00000010 */
-
-#define TIM_DCR_DBL_Pos           (8U)
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                  /*!< 0x00000800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                  /*!< 0x00001000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM1_OR1 register  ******************/
-#define TIM1_OR1_ETR_ADC_RMP_Pos   (0U)
-#define TIM1_OR1_ETR_ADC_RMP_Msk   (0x3UL << TIM1_OR1_ETR_ADC_RMP_Pos)         /*!< 0x00000003 */
-#define TIM1_OR1_ETR_ADC_RMP       TIM1_OR1_ETR_ADC_RMP_Msk                    /*!< TIM1_ETR_ADC remapping capability */
-#define TIM1_OR1_ETR_ADC_RMP_0     (0x1UL << TIM1_OR1_ETR_ADC_RMP_Pos)         /*!< 0x00000001 */
-#define TIM1_OR1_ETR_ADC_RMP_1     (0x2UL << TIM1_OR1_ETR_ADC_RMP_Pos)         /*!< 0x00000002 */
-#define TIM1_OR1_TI1_RMP_Pos       (4U)
-#define TIM1_OR1_TI1_RMP_Msk       (0x1UL << TIM1_OR1_TI1_RMP_Pos)             /*!< 0x00000010 */
-#define TIM1_OR1_TI1_RMP           TIM1_OR1_TI1_RMP_Msk                        /*!< Input Capture 1 remap*/
-
-/*******************  Bit definition for TIM2_OR1 register  ******************/
-#define TIM2_OR1_TI4_RMP_Pos       (2U)
-#define TIM2_OR1_TI4_RMP_Msk       (0x3UL << TIM2_OR1_TI4_RMP_Pos)             /*!< 0x0000000C */
-#define TIM2_OR1_TI4_RMP           TIM2_OR1_TI4_RMP_Msk                        /*!< TI4 RMA[1:0]Input capture 4 remap*/
-#define TIM2_OR1_TI4_RMP_0         (0x1UL << TIM2_OR1_TI4_RMP_Pos)             /*!< 0x00000004 */
-#define TIM2_OR1_TI4_RMP_1         (0x2UL << TIM2_OR1_TI4_RMP_Pos)             /*!< 0x00000008 */
-#define TIM2_OR1_ETR_RMP_Pos       (1U)
-#define TIM2_OR1_ETR_RMP_Msk       (0x1UL << TIM2_OR1_ETR_RMP_Pos)             /*!< 0x00000002 */
-#define TIM2_OR1_ETR_RMP           TIM2_OR1_ETR_RMP_Msk                        /*!< External trigger remap*/
-
-/*******************  Bit definition for TIM16_OR1 register  *****************/
-#define TIM16_OR1_TI1_RMP_Pos      (0U)
-#define TIM16_OR1_TI1_RMP_Msk      (0x3UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000003 */
-#define TIM16_OR1_TI1_RMP          TIM16_OR1_TI1_RMP_Msk                       /*!<Timer 16 input 1 connection. */
-#define TIM16_OR1_TI1_RMP_0        (0x1UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */
-#define TIM16_OR1_TI1_RMP_1        (0x2UL << TIM16_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */
-
-/*******************  Bit definition for TIM17_OR1 register  *****************/
-#define TIM17_OR1_TI1_RMP_Pos      (0U)
-#define TIM17_OR1_TI1_RMP_Msk      (0x3UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000003 */
-#define TIM17_OR1_TI1_RMP          TIM17_OR1_TI1_RMP_Msk                       /*!<Timer 17 input 1 connection. */
-#define TIM17_OR1_TI1_RMP_0        (0x1UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000001 */
-#define TIM17_OR1_TI1_RMP_1        (0x2UL << TIM17_OR1_TI1_RMP_Pos)            /*!< 0x00000002 */
-
-/*******************  Bit definition for TIM1_AF1 register  *******************/
-#define TIM1_AF1_BKINE_Pos        (0U)
-#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
-#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
-#define TIM1_AF1_BKCMP1E_Pos      (1U)                                         
-#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
-#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
-#define TIM1_AF1_BKCMP2E_Pos      (2U)                                         
-#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
-#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
-#define TIM1_AF1_BKINP_Pos        (9U)                                         
-#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
-#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
-#define TIM1_AF1_BKCMP1P_Pos      (10U)                                        
-#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
-#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
-#define TIM1_AF1_BKCMP2P_Pos      (11U)                                        
-#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
-#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BRK COMP2 input polarity */
-#define TIM1_AF1_ETRSEL_Pos       (14U)                                        
-#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
-#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
-#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00004000 */
-#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00008000 */
-#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00010000 */
-#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x00020000 */
-
-/*******************  Bit definition for TIM2_AF1 register  *******************/
-#define TIM2_AF1_ETRSEL_Pos       (14U)
-#define TIM2_AF1_ETRSEL_Msk       (0xFUL << TIM2_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */
-#define TIM2_AF1_ETRSEL           (0x00003C000)                                /*!< External trigger source selection */
-#define TIM2_AF1_ETRSEL_0         (0x000004000)                                /*!< Bit_0 */
-#define TIM2_AF1_ETRSEL_1         (0x000008000)                                /*!< Bit_1 */
-#define TIM2_AF1_ETRSEL_2         (0x000010000)                                /*!< Bit_2 */
-#define TIM2_AF1_ETRSEL_3         (0x000020000)                                /*!< Bit_3 */
-
-/*******************  Bit definition for TIM16_AF1 register  *******************/
-#define TIM16_AF1_BKINE_Pos       (0U)
-#define TIM16_AF1_BKINE_Msk       (0x1UL << TIM16_AF1_BKINE_Pos)               /*!< 0x00000001 */
-#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BRK BKIN input enable */
-#define TIM16_AF1_BKCMP1E_Pos     (1U)
-#define TIM16_AF1_BKCMP1E_Msk     (0x1UL << TIM16_AF1_BKCMP1E_Pos)             /*!< 0x00000002 */
-#define TIM16_AF1_BKCMP1E         TIM16_AF1_BKCMP1E_Msk                        /*!<BRK COMP1 enable */
-#define TIM16_AF1_BKCMP2E_Pos     (2U)                                         
-#define TIM16_AF1_BKCMP2E_Msk     (0x1UL << TIM16_AF1_BKCMP2E_Pos)             /*!< 0x00000004 */
-#define TIM16_AF1_BKCMP2E         TIM16_AF1_BKCMP2E_Msk                        /*!<BRK COMP2 enable */
-#define TIM16_AF1_BKINP_Pos       (9U)                                         
-#define TIM16_AF1_BKINP_Msk       (0x1UL << TIM16_AF1_BKINP_Pos)               /*!< 0x00000200 */
-#define TIM16_AF1_BKINP           TIM16_AF1_BKINP_Msk                          /*!<BRK BKIN2 input polarity */
-#define TIM16_AF1_BKCMP1P_Pos     (10U)                                        
-#define TIM16_AF1_BKCMP1P_Msk     (0x1UL << TIM16_AF1_BKCMP1P_Pos)             /*!< 0x00000400 */
-#define TIM16_AF1_BKCMP1P         TIM16_AF1_BKCMP1P_Msk                        /*!<BRK COMP1 input polarity */
-#define TIM16_AF1_BKCMP2P_Pos     (11U)                                        
-#define TIM16_AF1_BKCMP2P_Msk     (0x1UL << TIM16_AF1_BKCMP2P_Pos)             /*!< 0x00000800 */
-#define TIM16_AF1_BKCMP2P         TIM16_AF1_BKCMP2P_Msk                        /*!<BRK COMP2 input polarity */
-
-/*******************  Bit definition for TIM17_AF1 register  *******************/
-#define TIM17_AF1_BKINE_Pos       (0U)
-#define TIM17_AF1_BKINE_Msk       (0x1UL << TIM17_AF1_BKINE_Pos)               /*!< 0x00000001 */
-#define TIM17_AF1_BKINE           TIM17_AF1_BKINE_Msk                          /*!<BRK BKIN input enable */
-#define TIM17_AF1_BKCMP1E_Pos     (1U)
-#define TIM17_AF1_BKCMP1E_Msk     (0x1UL << TIM17_AF1_BKCMP1E_Pos)             /*!< 0x00000002 */
-#define TIM17_AF1_BKCMP1E         TIM17_AF1_BKCMP1E_Msk                        /*!<BRK COMP1 enable */
-#define TIM17_AF1_BKCMP2E_Pos     (2U)                                         
-#define TIM17_AF1_BKCMP2E_Msk     (0x1UL << TIM17_AF1_BKCMP2E_Pos)             /*!< 0x00000004 */
-#define TIM17_AF1_BKCMP2E         TIM17_AF1_BKCMP2E_Msk                        /*!<BRK COMP2 enable */
-#define TIM17_AF1_BKINP_Pos       (9U)                                         
-#define TIM17_AF1_BKINP_Msk       (0x1UL << TIM17_AF1_BKINP_Pos)               /*!< 0x00000200 */
-#define TIM17_AF1_BKINP           TIM17_AF1_BKINP_Msk                          /*!<BRK BKIN2 input polarity */
-#define TIM17_AF1_BKCMP1P_Pos     (10U)                                        
-#define TIM17_AF1_BKCMP1P_Msk     (0x1UL << TIM17_AF1_BKCMP1P_Pos)             /*!< 0x00000400 */
-#define TIM17_AF1_BKCMP1P         TIM17_AF1_BKCMP1P_Msk                        /*!<BRK COMP1 input polarity */
-#define TIM17_AF1_BKCMP2P_Pos     (11U)                                        
-#define TIM17_AF1_BKCMP2P_Msk     (0x1UL << TIM17_AF1_BKCMP2P_Pos)             /*!< 0x00000800 */
-#define TIM17_AF1_BKCMP2P         TIM17_AF1_BKCMP2P_Msk                        /*!<BRK COMP2 input polarity */
-
-/*******************  Bit definition for TIM1_AF2 register  *******************/
-#define TIM1_AF2_BK2INE_Pos       (0U)
-#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */
-#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BRK2 BKIN2 input enable */
-#define TIM1_AF2_BK2CMP1E_Pos     (1U)                                         
-#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */
-#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BRK2 COMP1 enable */
-#define TIM1_AF2_BK2CMP2E_Pos     (2U)                                         
-#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */
-#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BRK2 COMP2 enable */
-#define TIM1_AF2_BK2INP_Pos       (9U)                                         
-#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */
-#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRK2 BKIN2 input polarity */
-#define TIM1_AF2_BK2CMP1P_Pos     (10U)                                        
-#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */
-#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BRK2 COMP1 input polarity */
-#define TIM1_AF2_BK2CMP2P_Pos     (11U)                                        
-#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */
-#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BRK2 COMP2 input polarity */
-
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC_COMMON)
-
-/******************************* AES Instances ********************************/
-#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5) || \
-                                       ((INSTANCE) == DMA2_Channel6) || \
-                                       ((INSTANCE) == DMA2_Channel7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************* GPIO AF Instances ****************************/
-#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/**************************** GPIO Lock Instances *****************************/
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/****************** I2C Instances : wakeup capability from stop modes *********/
-#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************* SMBUS Instances ******************************/
-#define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************** HSEM Instances *******************************/
-#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
-
-#define HSEM_CPU1_COREID   (0x00000004U) /* Semaphore Core ID */
-#define HSEM_CPU2_COREID   (0x00000008U) /* Semaphore Core ID */
-
-#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/
-#define HSEM_SEMID_MAX     (15U)      /* HSEM ID Max */
-
-#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */
-#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */
-
-#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */
-#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */
-
-/******************************** PKA Instances *******************************/
-#define IS_PKA_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == PKA)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
-
-/****************************** RTC Instances *********************************/
-#define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SUBGHZSPI))
-
-/******************************** SUBGHZSPI Instances *************************/
-#define IS_SUBGHZ_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SUBGHZSPI)
-#define IS_SUBGHZ_MODULATION_SUPPORTED(COMMAND,PACKET_TYPE)  (1U == 1U)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \
-                                         ((INSTANCE) == LPTIM2) || \
-                                         ((INSTANCE) == LPTIM3))
-
-/****************** LPTIM Instances : Encoder mode ****************************/
-#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM16)  || \
-                                         ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting 32 bits counter ****************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : supporting the break function *************/
-#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
-                                            ((INSTANCE) == TIM16)   || \
-                                            ((INSTANCE) == TIM17))
-
-/************** TIM Instances : supporting Break source selection *************/
-#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                               ((INSTANCE) == TIM16)  || \
-                                               ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting 2 break inputs *****************/
-#define IS_TIM_BKIN2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM16)  || \
-                                         ((INSTANCE) == TIM17))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : at least 5 capture/compare channels *******/
-#define IS_TIM_CC5_INSTANCE(INSTANCE)      ((INSTANCE) == TIM1)
-
-/****************** TIM Instances : at least 6 capture/compare channels *******/
-#define IS_TIM_CC6_INSTANCE(INSTANCE)      ((INSTANCE) == TIM1)
-
-/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2)   || \
-                                            ((INSTANCE) == TIM16)  || \
-                                            ((INSTANCE) == TIM17))
-
-/******************* TIM Instances : Timer input selection ********************/
-#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
-                                         ((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM16)   || \
-                                         ((INSTANCE) == TIM17))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-        ((((INSTANCE) == TIM1) &&                  \
-           (((CHANNEL) == TIM_CHANNEL_1) ||          \
-            ((CHANNEL) == TIM_CHANNEL_2) ||          \
-            ((CHANNEL) == TIM_CHANNEL_3) ||          \
-            ((CHANNEL) == TIM_CHANNEL_4) ||          \
-            ((CHANNEL) == TIM_CHANNEL_5) ||          \
-            ((CHANNEL) == TIM_CHANNEL_6)))           \
-           ||                                        \
-           (((INSTANCE) == TIM2) &&                  \
-           (((CHANNEL) == TIM_CHANNEL_1) ||          \
-            ((CHANNEL) == TIM_CHANNEL_2) ||          \
-            ((CHANNEL) == TIM_CHANNEL_3) ||          \
-            ((CHANNEL) == TIM_CHANNEL_4)))           \
-           ||                                        \
-           (((INSTANCE) == TIM16) &&                 \
-           (((CHANNEL) == TIM_CHANNEL_1)))           \
-           ||                                        \
-           (((INSTANCE) == TIM17) &&                 \
-            (((CHANNEL) == TIM_CHANNEL_1))))
-
-/****************** TIM Instances : supporting complementary output(s) ********/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM17) &&                   \
-     ((CHANNEL) == TIM_CHANNEL_1))              \
-    ||                                          \
-    (((INSTANCE) == TIM16) &&                   \
-     ((CHANNEL) == TIM_CHANNEL_1)))
-
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
-                                                    ((INSTANCE) == TIM2)    || \
-                                                    ((INSTANCE) == TIM16)   || \
-                                                    ((INSTANCE) == TIM17))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
-#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/****************** TIM Instances : supporting commutation event generation ***/
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \
-                                                     ((INSTANCE) == TIM16)   || \
-                                                     ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting counting mode selection ********/
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
-                                                      ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting Hall sensor interface **********/
-#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
-
-/**************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2))
-
-/************* TIM Instances : supporting ETR source selection ***************/
-#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                             ((INSTANCE) == TIM2))
-
-/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : supporting OCxREF clear *******************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
-                                                       ((INSTANCE) == TIM2))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
-                                            ((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM16) || \
-                                            ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting repetition counter *************/
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
-                                                       ((INSTANCE) == TIM16) || \
-                                                       ((INSTANCE) == TIM17))
-
-/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
-#define IS_TIM_TRGO2_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
-                                            ((INSTANCE) == TIM2))
-
-/************ TIM Instances : Advanced timers  ********************************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* USART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/****************** UART Instances : Auto Baud Rate detection ****************/
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : SPI Slave selection mode ***************/
-#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                              ((INSTANCE) == USART2))
-
-/****************** UART Instances : Driver Enable *****************/
-#define IS_UART_FIFO_INSTANCE(INSTANCE)     (((INSTANCE) == USART1) || \
-                                             ((INSTANCE) == USART2) || \
-                                             ((INSTANCE) == LPUART1))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/******************** LPUART Instance *****************************************/
-#define IS_LPUART_INSTANCE(INSTANCE)    ((INSTANCE) == LPUART1)
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32WLE5xx_H */
-
-/**
-  * @}
-  */
-
-  /**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h

@@ -1,282 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS STM32WLxx Device Peripheral Access Layer Header File.
-  *
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The STM32WLxx device used in the target application
-  *              - To use or not the peripheral’s drivers in application code(i.e.
-  *                code will be based on direct access to peripheral’s registers
-  *                rather than drivers API), this option is controlled by
-  *                "#define USE_HAL_DRIVER"
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2020(-2021) STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32wlxx
-  * @{
-  */
-
-#ifndef __STM32WLxx_H
-#define __STM32WLxx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-/**
-  * @brief STM32 Family
-  */
-#if !defined (STM32WL)
-#define STM32WL
-#endif /* STM32WL */
-
-/* Uncomment the line below according to the target STM32WL device used in your
-   application
-  */
-
-#if !defined (STM32WL55xx) && !defined (STM32WL54xx) && !defined (STM32WLE5xx) && !defined (STM32WLE4xx)
-  /* #define STM32WL55xx */   /*!< STM32WL55xx Devices */
-  /* #define STM32WL54xx */   /*!< STM32WL54xx Devices */
-  /* #define STM32WLE5xx */   /*!< STM32WLE5xx Devices */
-  /* #define STM32WLE4xx */   /*!< STM32WLE4xx Devices */
-#endif
-
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will
-   be based on direct access to peripherals registers
-   */
-  /*#define USE_HAL_DRIVER */
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS Device version number
-  */
-#define __STM32WLxx_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32WLxx_CMSIS_VERSION_SUB1   (0x01U) /*!< [23:16] sub1 version */
-#define __STM32WLxx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
-#define __STM32WLxx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
-#define __STM32WLxx_CMSIS_DEVICE_VERSION        ((__STM32WLxx_CMSIS_VERSION_MAIN << 24)\
-                                                |(__STM32WLxx_CMSIS_VERSION_SUB1 << 16)\
-                                                |(__STM32WLxx_CMSIS_VERSION_SUB2 << 8 )\
-                                                |(__STM32WLxx_CMSIS_VERSION_RC))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-
-#if defined(STM32WL55xx)
-  #include "stm32wl55xx.h"
-#elif defined(STM32WLE5xx)
-  #include "stm32wle5xx.h"
-#elif defined(STM32WL54xx)
-  #include "stm32wl54xx.h"
-#elif defined(STM32WLE4xx)
-  #include "stm32wle4xx.h"
-#else
- #error "Please select first the target STM32WLxx device used in your application, for instance xxx (in stm32wlxx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */
-typedef enum
-{
-  RESET = 0,
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum
-{
-  DISABLE = 0,
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum
-{
-  ERROR = 0,
-  SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#if defined(CORE_CM0PLUS)
-/* Use of interrupt control for register exclusive access (privileged mode only) */
-/* Atomic 32-bit register access macro to set one or several bits */
-#define ATOMIC_SET_BIT(REG, BIT) \
-  do {                           \
-    uint32_t primask;            \
-    primask = __get_PRIMASK();   \
-    __set_PRIMASK(1);            \
-    SET_BIT((REG), (BIT));       \
-    __set_PRIMASK(primask);      \
-  } while(0)
-
-/* Atomic 32-bit register access macro to clear one or several bits */
-#define ATOMIC_CLEAR_BIT(REG, BIT) \
-  do {                             \
-    uint32_t primask;              \
-    primask = __get_PRIMASK();     \
-    __set_PRIMASK(1);              \
-    CLEAR_BIT((REG), (BIT));       \
-    __set_PRIMASK(primask);        \
-  } while(0)
-
-/* Atomic 32-bit register access macro to clear and set one or several bits */
-#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
-  do {                                            \
-    uint32_t primask;                             \
-    primask = __get_PRIMASK();                    \
-    __set_PRIMASK(1);                             \
-    MODIFY_REG((REG), (CLEARMSK), (SETMASK));     \
-    __set_PRIMASK(primask);                       \
-  } while(0)
-
-/* Atomic 16-bit register access macro to set one or several bits */
-#define ATOMIC_SETH_BIT(REG, BIT)   ATOMIC_SET_BIT(REG, BIT)
-
-/* Atomic 16-bit register access macro to clear one or several bits */
-#define ATOMIC_CLEARH_BIT(REG, BIT) ATOMIC_CLEAR_BIT(REG, BIT)
-
-/* Atomic 16-bit register access macro to clear and set one or several bits */
-#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)
-
-#else
-/* Use of CMSIS compiler intrinsics for register exclusive access */
-/* Atomic 32-bit register access macro to set one or several bits */
-#define ATOMIC_SET_BIT(REG, BIT)                             \
-  do {                                                       \
-    uint32_t val;                                            \
-    do {                                                     \
-      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \
-    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
-  } while(0)
-
-/* Atomic 32-bit register access macro to clear one or several bits */
-#define ATOMIC_CLEAR_BIT(REG, BIT)                           \
-  do {                                                       \
-    uint32_t val;                                            \
-    do {                                                     \
-      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \
-    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
-  } while(0)
-
-/* Atomic 32-bit register access macro to clear and set one or several bits */
-#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \
-  do {                                                                     \
-    uint32_t val;                                                          \
-    do {                                                                   \
-      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
-    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \
-  } while(0)
-
-/* Atomic 16-bit register access macro to set one or several bits */
-#define ATOMIC_SETH_BIT(REG, BIT)                            \
-  do {                                                       \
-    uint16_t val;                                            \
-    do {                                                     \
-      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \
-    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
-  } while(0)
-
-/* Atomic 16-bit register access macro to clear one or several bits */
-#define ATOMIC_CLEARH_BIT(REG, BIT)                          \
-  do {                                                       \
-    uint16_t val;                                            \
-    do {                                                     \
-      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \
-    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
-  } while(0)
-
-/* Atomic 16-bit register access macro to clear and set one or several bits */
-#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \
-  do {                                                                     \
-    uint16_t val;                                                          \
-    do {                                                                   \
-      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
-    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \
-  } while(0)
-
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
-#endif /* CORE_CM0PLUS */
-
-/**
-  * @}
-  */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32wlxx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32WLxx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h

@@ -1,106 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32wlxx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex Device System Source File for STM32WLxx devices.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2020(-2021) STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32wlxx_system
-  * @{
-  */
-
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32WLXX_H
-#define __SYSTEM_STM32WLXX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include <stdint.h>
-
-/** @addtogroup STM32WLxx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32WLxx_System_Exported_types
-  * @{
-  */
-  /* The SystemCoreClock variable is updated in three ways:
-      1) from within HAL_Init()
-      2) by calling CMSIS function SystemCoreClockUpdate()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-  */
-
-extern uint32_t SystemCoreClock;            /*!< System Clock Frequency */
-
-extern const uint32_t AHBPrescTable[16];    /*!< AHB prescalers table values */
-extern const uint32_t APBPrescTable[8];     /*!< APB prescalers table values */
-extern const uint32_t MSIRangeTable[16];    /*!< MSI ranges table values     */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32WLxx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32WLxx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32WLxx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32WLXX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Release_Notes.html

@@ -1,97 +0,0 @@
-<!DOCTYPE html>
-<html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
-<head>
-  <meta charset="utf-8" />
-  <meta name="generator" content="pandoc" />
-  <meta name="viewport" content="width=device-width, initial-scale=1.0, user-scalable=yes" />
-  <title>Release Notes for STM32WLxx CMSIS</title>
-  <style type="text/css">
-      code{white-space: pre-wrap;}
-      span.smallcaps{font-variant: small-caps;}
-      span.underline{text-decoration: underline;}
-      div.column{display: inline-block; vertical-align: top; width: 50%;}
-  </style>
-  <link rel="stylesheet" href="_htmresc/mini-st_2020.css" />
-  <!--[if lt IE 9]>
-    <script src="//cdnjs.cloudflare.com/ajax/libs/html5shiv/3.7.3/html5shiv-printshiv.min.js"></script>
-  <![endif]-->
-  <link rel="icon" type="image/x-icon" href="_htmresc/favicon.png" />
-</head>
-<body>
-<div class="row">
-<div class="col-sm-12 col-lg-4">
-<center>
-<h1 id="release-notes-for">Release Notes for</h1>
-<h1 id="stm32wlxx-cmsis"><mark>STM32WLxx CMSIS</mark></h1>
-<p>Copyright © 2020 STMicroelectronics<br />
-</p>
-<a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo_2020.png" alt="ST logo" /></a>
-</center>
-<h1 id="purpose">Purpose</h1>
-<p>This driver provides the CMSIS device for the stm32WLxx products. This covers</p>
-<ul>
-<li>STM32WL55xx devices</li>
-<li>STM32WL54xx devices</li>
-<li>STM32WLE5xx devices</li>
-<li>STM32WLE4xx devices</li>
-</ul>
-<p>This driver is composed of the descriptions of the registers under “Include” directory.</p>
-<p>Various template file are provided to easily build an application. They can be adapted to fit applications requirements.</p>
-<ul>
-<li>Templates/system_stm32WLxx.c contains the initialization code referred as SystemInit.</li>
-<li>Startup files are provided as example for IAR©, KEIL© and STM32CubeIDE©.</li>
-<li>Linker files are provided as example for IAR©, KEIL© and STM32CubeIDE©.</li>
-</ul>
-</div>
-<div class="col-sm-12 col-lg-8">
-<h1 id="update-history">Update History</h1>
-<div class="collapse">
-<input type="checkbox" id="collapse-section2" checked aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 16-June-2021</strong></label>
-<div>
-<h2 id="main-changes">Main Changes</h2>
-<ul>
-<li>Add atomic register access services:
-<ul>
-<li>32-bit register access: ATOMIC_SET_BIT(), ATOMIC_CLEAR_BIT(), ATOMIC_MODIFY_REG()</li>
-<li>16-bit register access: ATOMIC_SETH_BIT(), ATOMIC_CLEARH_BIT(), ATOMIC_MODIFYH_BIT()</li>
-</ul></li>
-<li>Add define LSI_STARTUP_TIME used in default IWDG timeout calculation (HAL_IWDG_DEFAULT_TIMEOUT)</li>
-<li>Add reference to user manual for customization of CubeIDE linker files</li>
-</ul>
-<h2 id="known-limitations">Known Limitations</h2>
-<p>None</p>
-<h2 id="dependencies">Dependencies</h2>
-<p>None</p>
-<h2 id="notes">Notes</h2>
-<p>None</p>
-</div>
-</div>
-<div class="collapse">
-<input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 28-October-2020</strong></label>
-<div>
-<h2 id="main-changes-1">Main Changes</h2>
-<p><strong>First Official Release</strong></p>
-<h2 id="contents">Contents</h2>
-<p>First official release of CMSIS drivers for STM32WLxx lines</p>
-<h2 id="known-limitations-1">Known Limitations</h2>
-<p>None</p>
-<h2 id="dependencies-1">Dependencies</h2>
-<p>None</p>
-<h2 id="notes-1">Notes</h2>
-<p>None</p>
-</div>
-</div>
-</div>
-</div>
-<footer class="sticky">
-<div class="columns">
-<div class="column" style="width:95%;">
-<p>For complete documentation on STM32WLxx, visit: <a href="http://www.st.com/stm32wl">www.st.com/stm32wl</a></p>
-<p><em>This release note uses up to date web standards and, for this reason, should not be opened with Internet Explorer but preferably with popular browsers such as Google Chrome, Mozilla Firefox, Opera or Microsoft Edge.</em></p>
-</div><div class="column" style="width:5%;">
-<p><abbr title="Based on template cx566953 version 2.0">Info</abbr></p>
-</div>
-</div>
-</footer>
-</body>
-</html>

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/linker/stm32wl54xx_flash_cm0plus.sct

@@ -1,19 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08020000 0x00020000  {    ; load region size_region
-  ; FLASH part dedicated to M0+
-  ER_IROM1 0x08020000 0x00020000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; Non-backup SRAM1 dedicated to M0+
-  RW_IRAM1 0x20004000 0x00004000  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-  ; Backup SRAM2 dedicated to M0+
-  RW_IRAM2 0x2000C000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
-  }
-}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/linker/stm32wl54xx_flash_cm4.sct

@@ -1,19 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00020000  {    ; load region size_region
-  ; FLASH part dedicated to M4
-  ER_IROM1 0x08000000 0x00020000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; Non-backup SRAM1 dedicated to M4
-  RW_IRAM1 0x20000000 0x00004000  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-  ; Backup SRAM2 dedicated to M4
-  RW_IRAM2 0x20008000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
-  }
-}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/linker/stm32wl55xx_flash_cm0plus.sct

@@ -1,19 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08020000 0x00020000  {    ; load region size_region
-  ; FLASH part dedicated to M0+
-  ER_IROM1 0x08020000 0x00020000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; Non-backup SRAM1 dedicated to M0+
-  RW_IRAM1 0x20004000 0x00004000  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-  ; Backup SRAM2 dedicated to M0+
-  RW_IRAM2 0x2000C000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
-  }
-}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/linker/stm32wl55xx_flash_cm4.sct

@@ -1,19 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00020000  {    ; load region size_region
-  ; FLASH part dedicated to M4
-  ER_IROM1 0x08000000 0x00020000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; Non-backup SRAM1 dedicated to M4
-  RW_IRAM1 0x20000000 0x00004000  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-  ; Backup SRAM2 dedicated to M4
-  RW_IRAM2 0x20008000 EMPTY 0x00004000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
-  }
-}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/linker/stm32wle4xx_flash.sct

@@ -1,19 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
-  ; FLASH
-  ER_IROM1 0x08000000 0x00040000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; Non-backup SRAM1
-  RW_IRAM1 0x20000000 0x00008000  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-  ; Backup SRAM2
-  RW_IRAM2 0x20008000 EMPTY 0x00008000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
-  }
-}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/linker/stm32wle5xx_flash.sct

@@ -1,19 +0,0 @@
-; *************************************************************
-; *** Scatter-Loading Description File generated by uVision ***
-; *************************************************************
-
-LR_IROM1 0x08000000 0x00040000  {    ; load region size_region
-  ; FLASH
-  ER_IROM1 0x08000000 0x00040000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-  ; Non-backup SRAM1
-  RW_IRAM1 0x20000000 0x00008000  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-  ; Backup SRAM2
-  RW_IRAM2 0x20008000 EMPTY 0x00008000  {  ; to be modified accordingly to user project. Can be NoInit data for backup usage, RW, ZI region, etc...
-  }
-}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wl54xx_cm0plus.s

@@ -1,253 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32wl54xx_cm0plus.s
-;* Author             : MCD Application Team
-;* Description        : STM32WL54xx devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2020(2021) STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                     ; Top of Stack
-                DCD     Reset_Handler                    ; Reset Handler
-                DCD     NMI_Handler                      ; NMI Handler
-                DCD     HardFault_Handler                ; Hard Fault Handler
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
-                DCD     SVC_Handler                      ; SVCall Handler
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
-                DCD     PendSV_Handler                   ; PendSV Handler
-                DCD     SysTick_Handler                  ; SysTick Handler
-
-                ; External Interrupts                    
-                DCD     TZIC_ILA_IRQHandler              ; Security Interrupt controller illegal access Interrupts
-                DCD     PVD_PVM_IRQHandler               ; PVD and PVM detector
-                DCD     RTC_LSECSS_IRQHandler            ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
-                DCD     RCC_FLASH_C1SEV_IRQHandler       ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
-                DCD     EXTI1_0_IRQHandler               ; EXTI Line 1:0 Interrupts
-                DCD     EXTI3_2_IRQHandler               ; XTI Line 3:2 Interrupts
-                DCD     EXTI15_4_IRQHandler              ; EXTI Line 15:4 interrupts
-                DCD     ADC_COMP_DAC_IRQHandler          ; ADC, COMP1, COMP2, DAC Interrupts
-                DCD     DMA1_Channel1_2_3_IRQHandler     ; DMA1 Channel 1 to 3 Interrupts
-                DCD     DMA1_Channel4_5_6_7_IRQHandler   ; DMA1 Channels 4, 5, 6, 7 Interrupts
-                DCD     DMA2_DMAMUX1_OVR_IRQHandler      ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts          
-                DCD     LPTIM1_IRQHandler                ; LPTIM1 global Interrupt
-                DCD     LPTIM2_IRQHandler                ; LPTIM2 global Interrupt
-                DCD     LPTIM3_IRQHandler                ; LPTIM3 global Interrupt
-                DCD     TIM1_IRQHandler                  ; TIM1 Interrupt
-                DCD     TIM2_IRQHandler                  ; TIM2 Interrupt
-                DCD     TIM16_IRQHandler                 ; TIM16 Interrupt
-                DCD     TIM17_IRQHandler                 ; TIM17 Interrupt
-                DCD     IPCC_C2_RX_C2_TX_IRQHandler      ; IPCC RX Occupied and TX Free Interrupt Interrupts
-                DCD     HSEM_IRQHandler                  ; Semaphore Interrupt
-                DCD     RNG_IRQHandler                   ; RNG Interrupt
-                DCD     AES_PKA_IRQHandler               ; AES and PKA Interrupts
-                DCD     I2C1_IRQHandler                  ; I2C1 Event and Error Interrupt
-                DCD     I2C2_IRQHandler                  ; I2C2 Event and Error Interrupt
-                DCD     I2C3_IRQHandler                  ; I2C3 Event and Error Interrupt
-                DCD     SPI1_IRQHandler                  ; SPI1 Interrupts
-                DCD     SPI2_IRQHandler                  ; SPI2 Interrupt
-                DCD     USART1_IRQHandler                ; USART1 Interrupt
-                DCD     USART2_IRQHandler                ; USART2 Interrupt
-                DCD     LPUART1_IRQHandler               ; LPUART1 Interrupt
-                DCD     SUBGHZSPI_IRQHandler             ; SUBGHZSPI Interrupt
-                DCD     SUBGHZ_Radio_IRQHandler          ; SUBGHZ Radio Interrupt
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  SystemInit
-        IMPORT  __main
-
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-                EXPORT  TZIC_ILA_IRQHandler            [WEAK]
-                EXPORT  PVD_PVM_IRQHandler             [WEAK]
-                EXPORT  RTC_LSECSS_IRQHandler          [WEAK]
-                EXPORT  RCC_FLASH_C1SEV_IRQHandler     [WEAK]
-                EXPORT  EXTI1_0_IRQHandler             [WEAK]
-                EXPORT  EXTI3_2_IRQHandler             [WEAK]
-                EXPORT  EXTI15_4_IRQHandler            [WEAK]
-                EXPORT  ADC_COMP_DAC_IRQHandler        [WEAK]
-                EXPORT  DMA1_Channel1_2_3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  DMA2_DMAMUX1_OVR_IRQHandler    [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  LPTIM2_IRQHandler              [WEAK]
-                EXPORT  LPTIM3_IRQHandler              [WEAK]
-                EXPORT  TIM1_IRQHandler                [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM16_IRQHandler               [WEAK]
-                EXPORT  TIM17_IRQHandler               [WEAK]
-                EXPORT  IPCC_C2_RX_C2_TX_IRQHandler    [WEAK]
-                EXPORT  HSEM_IRQHandler                [WEAK]
-                EXPORT  RNG_IRQHandler                 [WEAK]
-                EXPORT  AES_PKA_IRQHandler             [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  I2C3_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  LPUART1_IRQHandler             [WEAK]
-                EXPORT  SUBGHZSPI_IRQHandler           [WEAK]
-                EXPORT  SUBGHZ_Radio_IRQHandler        [WEAK]
-
-TZIC_ILA_IRQHandler
-PVD_PVM_IRQHandler
-RTC_LSECSS_IRQHandler
-RCC_FLASH_C1SEV_IRQHandler
-EXTI1_0_IRQHandler
-EXTI3_2_IRQHandler
-EXTI15_4_IRQHandler
-ADC_COMP_DAC_IRQHandler
-DMA1_Channel1_2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-DMA2_DMAMUX1_OVR_IRQHandler   
-LPTIM1_IRQHandler
-LPTIM2_IRQHandler
-LPTIM3_IRQHandler
-TIM1_IRQHandler
-TIM2_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-IPCC_C2_RX_C2_TX_IRQHandler
-HSEM_IRQHandler
-RNG_IRQHandler
-AES_PKA_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-I2C3_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-LPUART1_IRQHandler
-SUBGHZSPI_IRQHandler
-SUBGHZ_Radio_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-
-                 ELSE
-
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wl54xx_cm4.s

@@ -1,365 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32wl54xx_cm4.s
-;* Author             : MCD Application Team
-;* Description        : STM32WL54xx devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2020(2021) STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                      ; Top of Stack
-                DCD     Reset_Handler                     ; Reset Handler
-                DCD     NMI_Handler                       ; NMI Handler
-                DCD     HardFault_Handler                 ; Hard Fault Handler
-                DCD     MemManage_Handler                 ; MPU Fault Handler
-                DCD     BusFault_Handler                  ; Bus Fault Handler
-                DCD     UsageFault_Handler                ; Usage Fault Handler
-                DCD     0                                 ; Reserved
-                DCD     0                                 ; Reserved
-                DCD     0                                 ; Reserved
-                DCD     0                                 ; Reserved
-                DCD     SVC_Handler                       ; SVCall Handler
-                DCD     DebugMon_Handler                  ; Debug Monitor Handler
-                DCD     0                                 ; Reserved
-                DCD     PendSV_Handler                    ; PendSV Handler
-                DCD     SysTick_Handler                   ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                   ; Window WatchDog
-                DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
-                DCD     TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
-                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
-                DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
-                DCD     RCC_IRQHandler                    ; RCC Interrupt
-                DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
-                DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
-                DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
-                DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
-                DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
-                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
-                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
-                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
-                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
-                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
-                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
-                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
-                DCD     ADC_IRQHandler                    ; ADC Interrupt
-                DCD     DAC_IRQHandler                    ; DAC Interrupt
-                DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
-                DCD     COMP_IRQHandler                   ; COMP1 and COMP2 Interrupts
-                DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
-                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
-                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupts
-                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Communication Interrupts
-                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
-                DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
-                DCD     TIM16_IRQHandler                  ; TIM16 Global Interrupt
-                DCD     TIM17_IRQHandler                  ; TIM17 Global Interrupt
-                DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
-                DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
-                DCD     I2C2_EV_IRQHandler                ; I2C2 Event Interrupt
-                DCD     I2C2_ER_IRQHandler                ; I2C2 Error Interrupt
-                DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
-                DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
-                DCD     USART1_IRQHandler                 ; USART1 Interrupt
-                DCD     USART2_IRQHandler                 ; USART2 Interrupt
-                DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
-                DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
-                DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
-                DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
-                DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
-                DCD     LPTIM3_IRQHandler                 ; LPTIM3 Interrupt
-                DCD     SUBGHZSPI_IRQHandler              ; SUBGHZSPI Interrupt
-                DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
-                DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
-                DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
-                DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
-                DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
-                DCD     SUBGHZ_Radio_IRQHandler           ; SUBGHZ Radio Interrupt
-                DCD     AES_IRQHandler                    ; AES Interrupt
-                DCD     RNG_IRQHandler                    ; RNG1 Interrupt
-                DCD     PKA_IRQHandler                    ; PKA Interrupt
-                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
-                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
-                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
-                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
-                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
-                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
-                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
-                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
-
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  SystemInit
-        IMPORT  __main
-
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler              [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler               [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler             [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                   [WEAK]
-                EXPORT  PVD_PVM_IRQHandler                [WEAK]
-                EXPORT  TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
-                EXPORT  FLASH_IRQHandler                  [WEAK]
-                EXPORT  RCC_IRQHandler                    [WEAK]
-                EXPORT  EXTI0_IRQHandler                  [WEAK]
-                EXPORT  EXTI1_IRQHandler                  [WEAK]
-                EXPORT  EXTI2_IRQHandler                  [WEAK]
-                EXPORT  EXTI3_IRQHandler                  [WEAK]
-                EXPORT  EXTI4_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
-                EXPORT  ADC_IRQHandler                    [WEAK]
-                EXPORT  DAC_IRQHandler                    [WEAK]
-                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
-                EXPORT  COMP_IRQHandler                   [WEAK]
-                EXPORT  EXTI9_5_IRQHandler                [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
-                EXPORT  TIM1_UP_IRQHandler                [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK]
-                EXPORT  TIM1_CC_IRQHandler                [WEAK]
-                EXPORT  TIM2_IRQHandler                   [WEAK]
-                EXPORT  TIM16_IRQHandler                  [WEAK]
-                EXPORT  TIM17_IRQHandler                  [WEAK]
-                EXPORT  I2C1_EV_IRQHandler                [WEAK]
-                EXPORT  I2C1_ER_IRQHandler                [WEAK]
-                EXPORT  I2C2_EV_IRQHandler                [WEAK]
-                EXPORT  I2C2_ER_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                   [WEAK]
-                EXPORT  SPI2_IRQHandler                   [WEAK]
-                EXPORT  USART1_IRQHandler                 [WEAK]
-                EXPORT  USART2_IRQHandler                 [WEAK]
-                EXPORT  LPUART1_IRQHandler                [WEAK]
-                EXPORT  LPTIM1_IRQHandler                 [WEAK]
-                EXPORT  LPTIM2_IRQHandler                 [WEAK]
-                EXPORT  EXTI15_10_IRQHandler              [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
-                EXPORT  LPTIM3_IRQHandler                 [WEAK]
-                EXPORT  SUBGHZSPI_IRQHandler              [WEAK]
-                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
-                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
-                EXPORT  HSEM_IRQHandler                   [WEAK]
-                EXPORT  I2C3_EV_IRQHandler                [WEAK]
-                EXPORT  I2C3_ER_IRQHandler                [WEAK]
-                EXPORT  SUBGHZ_Radio_IRQHandler           [WEAK]
-                EXPORT  AES_IRQHandler                    [WEAK]
-                EXPORT  RNG_IRQHandler                    [WEAK]
-                EXPORT  PKA_IRQHandler                    [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
-                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
-
-WWDG_IRQHandler
-PVD_PVM_IRQHandler
-TAMP_STAMP_LSECSS_SSRU_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC_IRQHandler
-DAC_IRQHandler
-C2SEV_PWR_C2H_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler                
-USART2_IRQHandler
-LPUART1_IRQHandler
-LPTIM1_IRQHandler
-LPTIM2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-LPTIM3_IRQHandler
-SUBGHZSPI_IRQHandler
-IPCC_C1_RX_IRQHandler
-IPCC_C1_TX_IRQHandler
-HSEM_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SUBGHZ_Radio_IRQHandler
-AES_IRQHandler
-RNG_IRQHandler
-PKA_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-DMA2_Channel6_IRQHandler
-DMA2_Channel7_IRQHandler
-DMAMUX1_OVR_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-
-                 ELSE
-
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wl55xx_cm0plus.s

@@ -1,253 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32wl55xx_cm0plus.s
-;* Author             : MCD Application Team
-;* Description        : STM32WL55xx devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2020(2021) STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                     ; Top of Stack
-                DCD     Reset_Handler                    ; Reset Handler
-                DCD     NMI_Handler                      ; NMI Handler
-                DCD     HardFault_Handler                ; Hard Fault Handler
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
-                DCD     SVC_Handler                      ; SVCall Handler
-                DCD     0                                ; Reserved
-                DCD     0                                ; Reserved
-                DCD     PendSV_Handler                   ; PendSV Handler
-                DCD     SysTick_Handler                  ; SysTick Handler
-
-                ; External Interrupts                    
-                DCD     TZIC_ILA_IRQHandler              ; Security Interrupt controller illegal access Interrupts
-                DCD     PVD_PVM_IRQHandler               ; PVD and PVM detector
-                DCD     RTC_LSECSS_IRQHandler            ; RTC Wakeup + RTC Tamper and TimeStamp + RTC Alarms (A & B) + SSR Underflow and LSECSS Interrupts
-                DCD     RCC_FLASH_C1SEV_IRQHandler       ; RCC1 and FLASH and CPU1 M4 SEV Interrupts
-                DCD     EXTI1_0_IRQHandler               ; EXTI Line 1:0 Interrupts
-                DCD     EXTI3_2_IRQHandler               ; XTI Line 3:2 Interrupts
-                DCD     EXTI15_4_IRQHandler              ; EXTI Line 15:4 interrupts
-                DCD     ADC_COMP_DAC_IRQHandler          ; ADC, COMP1, COMP2, DAC Interrupts
-                DCD     DMA1_Channel1_2_3_IRQHandler     ; DMA1 Channel 1 to 3 Interrupts
-                DCD     DMA1_Channel4_5_6_7_IRQHandler   ; DMA1 Channels 4, 5, 6, 7 Interrupts
-                DCD     DMA2_DMAMUX1_OVR_IRQHandler      ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts          
-                DCD     LPTIM1_IRQHandler                ; LPTIM1 global Interrupt
-                DCD     LPTIM2_IRQHandler                ; LPTIM2 global Interrupt
-                DCD     LPTIM3_IRQHandler                ; LPTIM3 global Interrupt
-                DCD     TIM1_IRQHandler                  ; TIM1 Interrupt
-                DCD     TIM2_IRQHandler                  ; TIM2 Interrupt
-                DCD     TIM16_IRQHandler                 ; TIM16 Interrupt
-                DCD     TIM17_IRQHandler                 ; TIM17 Interrupt
-                DCD     IPCC_C2_RX_C2_TX_IRQHandler      ; IPCC RX Occupied and TX Free Interrupt Interrupts
-                DCD     HSEM_IRQHandler                  ; Semaphore Interrupt
-                DCD     RNG_IRQHandler                   ; RNG Interrupt
-                DCD     AES_PKA_IRQHandler               ; AES and PKA Interrupts
-                DCD     I2C1_IRQHandler                  ; I2C1 Event and Error Interrupt
-                DCD     I2C2_IRQHandler                  ; I2C2 Event and Error Interrupt
-                DCD     I2C3_IRQHandler                  ; I2C3 Event and Error Interrupt
-                DCD     SPI1_IRQHandler                  ; SPI1 Interrupts
-                DCD     SPI2_IRQHandler                  ; SPI2 Interrupt
-                DCD     USART1_IRQHandler                ; USART1 Interrupt
-                DCD     USART2_IRQHandler                ; USART2 Interrupt
-                DCD     LPUART1_IRQHandler               ; LPUART1 Interrupt
-                DCD     SUBGHZSPI_IRQHandler             ; SUBGHZSPI Interrupt
-                DCD     SUBGHZ_Radio_IRQHandler          ; SUBGHZ Radio Interrupt
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  SystemInit
-        IMPORT  __main
-
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-                EXPORT  TZIC_ILA_IRQHandler            [WEAK]
-                EXPORT  PVD_PVM_IRQHandler             [WEAK]
-                EXPORT  RTC_LSECSS_IRQHandler          [WEAK]
-                EXPORT  RCC_FLASH_C1SEV_IRQHandler     [WEAK]
-                EXPORT  EXTI1_0_IRQHandler             [WEAK]
-                EXPORT  EXTI3_2_IRQHandler             [WEAK]
-                EXPORT  EXTI15_4_IRQHandler            [WEAK]
-                EXPORT  ADC_COMP_DAC_IRQHandler        [WEAK]
-                EXPORT  DMA1_Channel1_2_3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  DMA2_DMAMUX1_OVR_IRQHandler    [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  LPTIM2_IRQHandler              [WEAK]
-                EXPORT  LPTIM3_IRQHandler              [WEAK]
-                EXPORT  TIM1_IRQHandler                [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM16_IRQHandler               [WEAK]
-                EXPORT  TIM17_IRQHandler               [WEAK]
-                EXPORT  IPCC_C2_RX_C2_TX_IRQHandler    [WEAK]
-                EXPORT  HSEM_IRQHandler                [WEAK]
-                EXPORT  RNG_IRQHandler                 [WEAK]
-                EXPORT  AES_PKA_IRQHandler             [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  I2C3_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  LPUART1_IRQHandler             [WEAK]
-                EXPORT  SUBGHZSPI_IRQHandler           [WEAK]
-                EXPORT  SUBGHZ_Radio_IRQHandler        [WEAK]
-
-TZIC_ILA_IRQHandler
-PVD_PVM_IRQHandler
-RTC_LSECSS_IRQHandler
-RCC_FLASH_C1SEV_IRQHandler
-EXTI1_0_IRQHandler
-EXTI3_2_IRQHandler
-EXTI15_4_IRQHandler
-ADC_COMP_DAC_IRQHandler
-DMA1_Channel1_2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-DMA2_DMAMUX1_OVR_IRQHandler   
-LPTIM1_IRQHandler
-LPTIM2_IRQHandler
-LPTIM3_IRQHandler
-TIM1_IRQHandler
-TIM2_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-IPCC_C2_RX_C2_TX_IRQHandler
-HSEM_IRQHandler
-RNG_IRQHandler
-AES_PKA_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-I2C3_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-LPUART1_IRQHandler
-SUBGHZSPI_IRQHandler
-SUBGHZ_Radio_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-
-                 ELSE
-
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wl55xx_cm4.s

@@ -1,365 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32wl55xx_cm4.s
-;* Author             : MCD Application Team
-;* Description        : STM32WL55xx devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2020(2021) STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                      ; Top of Stack
-                DCD     Reset_Handler                     ; Reset Handler
-                DCD     NMI_Handler                       ; NMI Handler
-                DCD     HardFault_Handler                 ; Hard Fault Handler
-                DCD     MemManage_Handler                 ; MPU Fault Handler
-                DCD     BusFault_Handler                  ; Bus Fault Handler
-                DCD     UsageFault_Handler                ; Usage Fault Handler
-                DCD     0                                 ; Reserved
-                DCD     0                                 ; Reserved
-                DCD     0                                 ; Reserved
-                DCD     0                                 ; Reserved
-                DCD     SVC_Handler                       ; SVCall Handler
-                DCD     DebugMon_Handler                  ; Debug Monitor Handler
-                DCD     0                                 ; Reserved
-                DCD     PendSV_Handler                    ; PendSV Handler
-                DCD     SysTick_Handler                   ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                   ; Window WatchDog
-                DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
-                DCD     TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
-                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
-                DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
-                DCD     RCC_IRQHandler                    ; RCC Interrupt
-                DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
-                DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
-                DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
-                DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
-                DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
-                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
-                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
-                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
-                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
-                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
-                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
-                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
-                DCD     ADC_IRQHandler                    ; ADC Interrupt
-                DCD     DAC_IRQHandler                    ; DAC Interrupt
-                DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV and PWR CPU M0+ HOLD wakeup Interrupt
-                DCD     COMP_IRQHandler                   ; COMP1 and COMP2 Interrupts
-                DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
-                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
-                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupts
-                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Communication Interrupts
-                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
-                DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
-                DCD     TIM16_IRQHandler                  ; TIM16 Global Interrupt
-                DCD     TIM17_IRQHandler                  ; TIM17 Global Interrupt
-                DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
-                DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
-                DCD     I2C2_EV_IRQHandler                ; I2C2 Event Interrupt
-                DCD     I2C2_ER_IRQHandler                ; I2C2 Error Interrupt
-                DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
-                DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
-                DCD     USART1_IRQHandler                 ; USART1 Interrupt
-                DCD     USART2_IRQHandler                 ; USART2 Interrupt
-                DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
-                DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
-                DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
-                DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
-                DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
-                DCD     LPTIM3_IRQHandler                 ; LPTIM3 Interrupt
-                DCD     SUBGHZSPI_IRQHandler              ; SUBGHZSPI Interrupt
-                DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
-                DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
-                DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
-                DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
-                DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
-                DCD     SUBGHZ_Radio_IRQHandler           ; SUBGHZ Radio Interrupt
-                DCD     AES_IRQHandler                    ; AES Interrupt
-                DCD     RNG_IRQHandler                    ; RNG1 Interrupt
-                DCD     PKA_IRQHandler                    ; PKA Interrupt
-                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
-                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
-                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
-                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
-                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
-                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
-                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
-                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
-
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  SystemInit
-        IMPORT  __main
-
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler              [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler               [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler             [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                   [WEAK]
-                EXPORT  PVD_PVM_IRQHandler                [WEAK]
-                EXPORT  TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
-                EXPORT  FLASH_IRQHandler                  [WEAK]
-                EXPORT  RCC_IRQHandler                    [WEAK]
-                EXPORT  EXTI0_IRQHandler                  [WEAK]
-                EXPORT  EXTI1_IRQHandler                  [WEAK]
-                EXPORT  EXTI2_IRQHandler                  [WEAK]
-                EXPORT  EXTI3_IRQHandler                  [WEAK]
-                EXPORT  EXTI4_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
-                EXPORT  ADC_IRQHandler                    [WEAK]
-                EXPORT  DAC_IRQHandler                    [WEAK]
-                EXPORT  C2SEV_PWR_C2H_IRQHandler          [WEAK]
-                EXPORT  COMP_IRQHandler                   [WEAK]
-                EXPORT  EXTI9_5_IRQHandler                [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
-                EXPORT  TIM1_UP_IRQHandler                [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK]
-                EXPORT  TIM1_CC_IRQHandler                [WEAK]
-                EXPORT  TIM2_IRQHandler                   [WEAK]
-                EXPORT  TIM16_IRQHandler                  [WEAK]
-                EXPORT  TIM17_IRQHandler                  [WEAK]
-                EXPORT  I2C1_EV_IRQHandler                [WEAK]
-                EXPORT  I2C1_ER_IRQHandler                [WEAK]
-                EXPORT  I2C2_EV_IRQHandler                [WEAK]
-                EXPORT  I2C2_ER_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                   [WEAK]
-                EXPORT  SPI2_IRQHandler                   [WEAK]
-                EXPORT  USART1_IRQHandler                 [WEAK]
-                EXPORT  USART2_IRQHandler                 [WEAK]
-                EXPORT  LPUART1_IRQHandler                [WEAK]
-                EXPORT  LPTIM1_IRQHandler                 [WEAK]
-                EXPORT  LPTIM2_IRQHandler                 [WEAK]
-                EXPORT  EXTI15_10_IRQHandler              [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
-                EXPORT  LPTIM3_IRQHandler                 [WEAK]
-                EXPORT  SUBGHZSPI_IRQHandler              [WEAK]
-                EXPORT  IPCC_C1_RX_IRQHandler             [WEAK]
-                EXPORT  IPCC_C1_TX_IRQHandler             [WEAK]
-                EXPORT  HSEM_IRQHandler                   [WEAK]
-                EXPORT  I2C3_EV_IRQHandler                [WEAK]
-                EXPORT  I2C3_ER_IRQHandler                [WEAK]
-                EXPORT  SUBGHZ_Radio_IRQHandler           [WEAK]
-                EXPORT  AES_IRQHandler                    [WEAK]
-                EXPORT  RNG_IRQHandler                    [WEAK]
-                EXPORT  PKA_IRQHandler                    [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
-                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
-
-WWDG_IRQHandler
-PVD_PVM_IRQHandler
-TAMP_STAMP_LSECSS_SSRU_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC_IRQHandler
-DAC_IRQHandler
-C2SEV_PWR_C2H_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler                
-USART2_IRQHandler
-LPUART1_IRQHandler
-LPTIM1_IRQHandler
-LPTIM2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-LPTIM3_IRQHandler
-SUBGHZSPI_IRQHandler
-IPCC_C1_RX_IRQHandler
-IPCC_C1_TX_IRQHandler
-HSEM_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SUBGHZ_Radio_IRQHandler
-AES_IRQHandler
-RNG_IRQHandler
-PKA_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-DMA2_Channel6_IRQHandler
-DMA2_Channel7_IRQHandler
-DMAMUX1_OVR_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-
-                 ELSE
-
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wle4xx.s

@@ -1,359 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32wle4xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32WLE4xx devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2020(2021) STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                      ; Top of Stack
-                DCD     Reset_Handler                     ; Reset Handler
-                DCD     NMI_Handler                       ; NMI Handler
-                DCD     HardFault_Handler                 ; Hard Fault Handler
-                DCD     MemManage_Handler                 ; MPU Fault Handler
-                DCD     BusFault_Handler                  ; Bus Fault Handler
-                DCD     UsageFault_Handler                ; Usage Fault Handler
-                DCD     0                                 ; Reserved
-                DCD     0                                 ; Reserved
-                DCD     0                                 ; Reserved
-                DCD     0                                 ; Reserved
-                DCD     SVC_Handler                       ; SVCall Handler
-                DCD     DebugMon_Handler                  ; Debug Monitor Handler
-                DCD     0                                 ; Reserved
-                DCD     PendSV_Handler                    ; PendSV Handler
-                DCD     SysTick_Handler                   ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                   ; Window WatchDog
-                DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
-                DCD     TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
-                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
-                DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
-                DCD     RCC_IRQHandler                    ; RCC Interrupt
-                DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
-                DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
-                DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
-                DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
-                DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
-                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
-                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
-                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
-                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
-                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
-                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
-                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
-                DCD     ADC_IRQHandler                    ; ADC Interrupt
-                DCD     DAC_IRQHandler                    ; DAC Interrupt
-                DCD     0                                 ; Reserved
-                DCD     COMP_IRQHandler                   ; COMP1 and COMP2 Interrupts
-                DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
-                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
-                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupts
-                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Communication Interrupts
-                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
-                DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
-                DCD     TIM16_IRQHandler                  ; TIM16 Global Interrupt
-                DCD     TIM17_IRQHandler                  ; TIM17 Global Interrupt
-                DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
-                DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
-                DCD     I2C2_EV_IRQHandler                ; I2C2 Event Interrupt
-                DCD     I2C2_ER_IRQHandler                ; I2C2 Error Interrupt
-                DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
-                DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
-                DCD     USART1_IRQHandler                 ; USART1 Interrupt
-                DCD     USART2_IRQHandler                 ; USART2 Interrupt
-                DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
-                DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
-                DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
-                DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
-                DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
-                DCD     LPTIM3_IRQHandler                 ; LPTIM3 Interrupt
-                DCD     SUBGHZSPI_IRQHandler              ; SUBGHZSPI Interrupt
-                DCD     0                                 ; Reserved
-                DCD     0                                 ; Reserved
-                DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
-                DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
-                DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
-                DCD     SUBGHZ_Radio_IRQHandler           ; SUBGHZ Radio Interrupt
-                DCD     AES_IRQHandler                    ; AES Interrupt
-                DCD     RNG_IRQHandler                    ; RNG1 Interrupt
-                DCD     PKA_IRQHandler                    ; PKA Interrupt
-                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
-                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
-                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
-                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
-                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
-                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
-                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
-                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
-
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  SystemInit
-        IMPORT  __main
-
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler              [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler               [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler             [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                   [WEAK]
-                EXPORT  PVD_PVM_IRQHandler                [WEAK]
-                EXPORT  TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
-                EXPORT  FLASH_IRQHandler                  [WEAK]
-                EXPORT  RCC_IRQHandler                    [WEAK]
-                EXPORT  EXTI0_IRQHandler                  [WEAK]
-                EXPORT  EXTI1_IRQHandler                  [WEAK]
-                EXPORT  EXTI2_IRQHandler                  [WEAK]
-                EXPORT  EXTI3_IRQHandler                  [WEAK]
-                EXPORT  EXTI4_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
-                EXPORT  ADC_IRQHandler                    [WEAK]
-                EXPORT  DAC_IRQHandler                    [WEAK]
-                EXPORT  COMP_IRQHandler                   [WEAK]
-                EXPORT  EXTI9_5_IRQHandler                [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
-                EXPORT  TIM1_UP_IRQHandler                [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK]
-                EXPORT  TIM1_CC_IRQHandler                [WEAK]
-                EXPORT  TIM2_IRQHandler                   [WEAK]
-                EXPORT  TIM16_IRQHandler                  [WEAK]
-                EXPORT  TIM17_IRQHandler                  [WEAK]
-                EXPORT  I2C1_EV_IRQHandler                [WEAK]
-                EXPORT  I2C1_ER_IRQHandler                [WEAK]
-                EXPORT  I2C2_EV_IRQHandler                [WEAK]
-                EXPORT  I2C2_ER_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                   [WEAK]
-                EXPORT  SPI2_IRQHandler                   [WEAK]
-                EXPORT  USART1_IRQHandler                 [WEAK]
-                EXPORT  USART2_IRQHandler                 [WEAK]
-                EXPORT  LPUART1_IRQHandler                [WEAK]
-                EXPORT  LPTIM1_IRQHandler                 [WEAK]
-                EXPORT  LPTIM2_IRQHandler                 [WEAK]
-                EXPORT  EXTI15_10_IRQHandler              [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
-                EXPORT  LPTIM3_IRQHandler                 [WEAK]
-                EXPORT  SUBGHZSPI_IRQHandler              [WEAK]
-                EXPORT  HSEM_IRQHandler                   [WEAK]
-                EXPORT  I2C3_EV_IRQHandler                [WEAK]
-                EXPORT  I2C3_ER_IRQHandler                [WEAK]
-                EXPORT  SUBGHZ_Radio_IRQHandler           [WEAK]
-                EXPORT  AES_IRQHandler                    [WEAK]
-                EXPORT  RNG_IRQHandler                    [WEAK]
-                EXPORT  PKA_IRQHandler                    [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
-                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
-
-WWDG_IRQHandler
-PVD_PVM_IRQHandler
-TAMP_STAMP_LSECSS_SSRU_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler                
-USART2_IRQHandler
-LPUART1_IRQHandler
-LPTIM1_IRQHandler
-LPTIM2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-LPTIM3_IRQHandler
-SUBGHZSPI_IRQHandler
-HSEM_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SUBGHZ_Radio_IRQHandler
-AES_IRQHandler
-RNG_IRQHandler
-PKA_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-DMA2_Channel6_IRQHandler
-DMA2_Channel7_IRQHandler
-DMAMUX1_OVR_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-
-                 ELSE
-
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/arm/startup_stm32wle5xx.s

@@ -1,359 +0,0 @@
-;******************************************************************************
-;* File Name          : startup_stm32wle5xx.s
-;* Author             : MCD Application Team
-;* Description        : STM32WLE5xx devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the CortexM4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;******************************************************************************
-;* @attention
-;*
-;* Copyright (c) 2020(2021) STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;*
-;******************************************************************************
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000000
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp                      ; Top of Stack
-                DCD     Reset_Handler                     ; Reset Handler
-                DCD     NMI_Handler                       ; NMI Handler
-                DCD     HardFault_Handler                 ; Hard Fault Handler
-                DCD     MemManage_Handler                 ; MPU Fault Handler
-                DCD     BusFault_Handler                  ; Bus Fault Handler
-                DCD     UsageFault_Handler                ; Usage Fault Handler
-                DCD     0                                 ; Reserved
-                DCD     0                                 ; Reserved
-                DCD     0                                 ; Reserved
-                DCD     0                                 ; Reserved
-                DCD     SVC_Handler                       ; SVCall Handler
-                DCD     DebugMon_Handler                  ; Debug Monitor Handler
-                DCD     0                                 ; Reserved
-                DCD     PendSV_Handler                    ; PendSV Handler
-                DCD     SysTick_Handler                   ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                   ; Window WatchDog
-                DCD     PVD_PVM_IRQHandler                ; PVD and PVM detector
-                DCD     TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSR Underflow Interrupts
-                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
-                DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
-                DCD     RCC_IRQHandler                    ; RCC Interrupt
-                DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
-                DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
-                DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
-                DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrup
-                DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
-                DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
-                DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
-                DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
-                DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
-                DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
-                DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
-                DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
-                DCD     ADC_IRQHandler                    ; ADC Interrupt
-                DCD     DAC_IRQHandler                    ; DAC Interrupt
-                DCD     0                                 ; Reserved
-                DCD     COMP_IRQHandler                   ; COMP1 and COMP2 Interrupts
-                DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
-                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
-                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupts
-                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Communication Interrupts
-                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
-                DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
-                DCD     TIM16_IRQHandler                  ; TIM16 Global Interrupt
-                DCD     TIM17_IRQHandler                  ; TIM17 Global Interrupt
-                DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
-                DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
-                DCD     I2C2_EV_IRQHandler                ; I2C2 Event Interrupt
-                DCD     I2C2_ER_IRQHandler                ; I2C2 Error Interrupt
-                DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
-                DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
-                DCD     USART1_IRQHandler                 ; USART1 Interrupt
-                DCD     USART2_IRQHandler                 ; USART2 Interrupt
-                DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
-                DCD     LPTIM1_IRQHandler                 ; LPTIM1 Interrupt
-                DCD     LPTIM2_IRQHandler                 ; LPTIM2 Interrupt
-                DCD     EXTI15_10_IRQHandler              ; EXTI Lines1[15:10 ]Interrupts
-                DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
-                DCD     LPTIM3_IRQHandler                 ; LPTIM3 Interrupt
-                DCD     SUBGHZSPI_IRQHandler              ; SUBGHZSPI Interrupt
-                DCD     0                                 ; Reserved
-                DCD     0                                 ; Reserved
-                DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
-                DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
-                DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
-                DCD     SUBGHZ_Radio_IRQHandler           ; SUBGHZ Radio Interrupt
-                DCD     AES_IRQHandler                    ; AES Interrupt
-                DCD     RNG_IRQHandler                    ; RNG1 Interrupt
-                DCD     PKA_IRQHandler                    ; PKA Interrupt
-                DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
-                DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
-                DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
-                DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
-                DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
-                DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
-                DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
-                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
-
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  SystemInit
-        IMPORT  __main
-
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler              [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler               [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler             [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                   [WEAK]
-                EXPORT  PVD_PVM_IRQHandler                [WEAK]
-                EXPORT  TAMP_STAMP_LSECSS_SSRU_IRQHandler [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
-                EXPORT  FLASH_IRQHandler                  [WEAK]
-                EXPORT  RCC_IRQHandler                    [WEAK]
-                EXPORT  EXTI0_IRQHandler                  [WEAK]
-                EXPORT  EXTI1_IRQHandler                  [WEAK]
-                EXPORT  EXTI2_IRQHandler                  [WEAK]
-                EXPORT  EXTI3_IRQHandler                  [WEAK]
-                EXPORT  EXTI4_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler          [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler          [WEAK]
-                EXPORT  ADC_IRQHandler                    [WEAK]
-                EXPORT  DAC_IRQHandler                    [WEAK]
-                EXPORT  COMP_IRQHandler                   [WEAK]
-                EXPORT  EXTI9_5_IRQHandler                [WEAK]
-                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
-                EXPORT  TIM1_UP_IRQHandler                [WEAK]
-                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK]
-                EXPORT  TIM1_CC_IRQHandler                [WEAK]
-                EXPORT  TIM2_IRQHandler                   [WEAK]
-                EXPORT  TIM16_IRQHandler                  [WEAK]
-                EXPORT  TIM17_IRQHandler                  [WEAK]
-                EXPORT  I2C1_EV_IRQHandler                [WEAK]
-                EXPORT  I2C1_ER_IRQHandler                [WEAK]
-                EXPORT  I2C2_EV_IRQHandler                [WEAK]
-                EXPORT  I2C2_ER_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                   [WEAK]
-                EXPORT  SPI2_IRQHandler                   [WEAK]
-                EXPORT  USART1_IRQHandler                 [WEAK]
-                EXPORT  USART2_IRQHandler                 [WEAK]
-                EXPORT  LPUART1_IRQHandler                [WEAK]
-                EXPORT  LPTIM1_IRQHandler                 [WEAK]
-                EXPORT  LPTIM2_IRQHandler                 [WEAK]
-                EXPORT  EXTI15_10_IRQHandler              [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
-                EXPORT  LPTIM3_IRQHandler                 [WEAK]
-                EXPORT  SUBGHZSPI_IRQHandler              [WEAK]
-                EXPORT  HSEM_IRQHandler                   [WEAK]
-                EXPORT  I2C3_EV_IRQHandler                [WEAK]
-                EXPORT  I2C3_ER_IRQHandler                [WEAK]
-                EXPORT  SUBGHZ_Radio_IRQHandler           [WEAK]
-                EXPORT  AES_IRQHandler                    [WEAK]
-                EXPORT  RNG_IRQHandler                    [WEAK]
-                EXPORT  PKA_IRQHandler                    [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel6_IRQHandler          [WEAK]
-                EXPORT  DMA2_Channel7_IRQHandler          [WEAK]
-                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
-
-WWDG_IRQHandler
-PVD_PVM_IRQHandler
-TAMP_STAMP_LSECSS_SSRU_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-TIM1_BRK_IRQHandler
-TIM1_UP_IRQHandler
-TIM1_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler                
-USART2_IRQHandler
-LPUART1_IRQHandler
-LPTIM1_IRQHandler
-LPTIM2_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-LPTIM3_IRQHandler
-SUBGHZSPI_IRQHandler
-HSEM_IRQHandler
-I2C3_EV_IRQHandler
-I2C3_ER_IRQHandler
-SUBGHZ_Radio_IRQHandler
-AES_IRQHandler
-RNG_IRQHandler
-PKA_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-DMA2_Channel6_IRQHandler
-DMA2_Channel7_IRQHandler
-DMAMUX1_OVR_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
-                 IF      :DEF:__MICROLIB
-
-                 EXPORT  __initial_sp
-                 EXPORT  __heap_base
-                 EXPORT  __heap_limit
-
-                 ELSE
-
-                 IMPORT  __use_two_region_memory
-                 EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap
-
-                 LDR     R0, =  Heap_Mem
-                 LDR     R1, =(Stack_Mem + Stack_Size)
-                 LDR     R2, = (Heap_Mem +  Heap_Size)
-                 LDR     R3, = Stack_Mem
-                 BX      LR
-
-                 ALIGN
-
-                 ENDIF
-
-                 END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/linker/STM32WL54XX_FLASH_CM0PLUS.ld

@@ -1,178 +0,0 @@
-/*
-** LinkerScript
-** Note: For specific memory allocation, linker and startup files must be customized.
-**       Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script".
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
-
-_Min_Heap_Size  = 0x200; /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Memories definition */
-MEMORY
-{
-  ROM    (rx)    : ORIGIN = 0x08020000, LENGTH = 128K   /* Flash memory dedicated to CM0+ */
-  RAM1   (xrw)   : ORIGIN = 0x20004000, LENGTH = 16K    /* Non-backup SRAM1 dedicated to CM0+ */
-  RAM2   (xrw)   : ORIGIN = 0x2000C000, LENGTH = 16K    /* Backup SRAM2 dedicated to CM0+ */
-}
-
-/* Sections */
-SECTIONS
-{
-  /* The startup code into "ROM" Rom type memory */
-  .isr_vector :
-  {
-    . = ALIGN(8);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(8);
-  } >ROM
-
-  /* The program code and other data into "ROM" Rom type memory */
-  .text :
-  {
-    . = ALIGN(8);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(8);
-    _etext = .;        /* define a global symbols at end of code */
-  } >ROM
-
-  /* Constant data into "ROM" Rom type memory */
-  .rodata :
-  {
-    . = ALIGN(8);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(8);
-  } >ROM
-
-  .ARM.extab   : { 
-    . = ALIGN(8);
-    *(.ARM.extab* .gnu.linkonce.armextab.*)
-    . = ALIGN(8);
-  } >ROM
-  
-  .ARM : {
-    . = ALIGN(8);
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-    . = ALIGN(8);
-  } >ROM
-
-  .preinit_array     :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-  
-  .init_array :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-  
-  .fini_array :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-
-  /* Used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections into "SRAM1" Ram type memory */
-  .data : 
-  {
-    . = ALIGN(8);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(8);
-    _edata = .;        /* define a global symbol at data end */
-    
-  } >RAM1 AT> ROM
-
-  /* Uninitialized data section into "SRAM1" Ram type memory */
-  . = ALIGN(8);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss section */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(8);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM1
-
-  /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM0+ */
-  . = ALIGN(8);
-  RAM1_region :
-  {
-    _sRAM1_region = .;         /* define a global symbol at section start */
-    *(.RAM1_region)
-
-    . = ALIGN(8);
-    _eRAM1_region = .;         /* define a global symbol at section end */
-  } >RAM1
-
-  /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM0+ */
-  . = ALIGN(8);
-  RAM2_region :
-  {
-    _sRAM2_region = .;         /* define a global symbol at section start */
-    *(.RAM2_region)
-
-    . = ALIGN(8);
-    _eRAM2_region = .;         /* define a global symbol at section end */
-  } >RAM2
-
-  /* User_heap_stack section, used to check that there is enough "SRAM1" Ram  type memory left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM1
-
-  /* Remove information from the compiler libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/linker/STM32WL54XX_FLASH_CM4.ld

@@ -1,178 +0,0 @@
-/*
-** LinkerScript
-** Note: For specific memory allocation, linker and startup files must be customized.
-**       Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script".
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
-
-_Min_Heap_Size  = 0x200; /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Memories definition */
-MEMORY
-{
-  ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 128K   /* Flash memory dedicated to CM4 */
-  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 16K    /* Non-backup SRAM1 dedicated to CM4 */
-  RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 16K    /* Backup SRAM2 dedicated to CM4 */
-}
-
-/* Sections */
-SECTIONS
-{
-  /* The startup code into "ROM" Rom type memory */
-  .isr_vector :
-  {
-    . = ALIGN(8);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(8);
-  } >ROM
-
-  /* The program code and other data into "ROM" Rom type memory */
-  .text :
-  {
-    . = ALIGN(8);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(8);
-    _etext = .;        /* define a global symbols at end of code */
-  } >ROM
-
-  /* Constant data into "ROM" Rom type memory */
-  .rodata :
-  {
-    . = ALIGN(8);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(8);
-  } >ROM
-
-  .ARM.extab   : { 
-    . = ALIGN(8);
-    *(.ARM.extab* .gnu.linkonce.armextab.*)
-    . = ALIGN(8);
-  } >ROM
-  
-  .ARM : {
-    . = ALIGN(8);
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-    . = ALIGN(8);
-  } >ROM
-
-  .preinit_array     :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-  
-  .init_array :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-  
-  .fini_array :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-
-  /* Used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections into "SRAM1" Ram type memory */
-  .data : 
-  {
-    . = ALIGN(8);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(8);
-    _edata = .;        /* define a global symbol at data end */
-    
-  } >RAM1 AT> ROM
-
-  /* Uninitialized data section into "SRAM1" Ram type memory */
-  . = ALIGN(8);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss section */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(8);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM1
-
-  /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
-  . = ALIGN(8);
-  RAM1_region :
-  {
-    _sRAM1_region = .;         /* define a global symbol at section start */
-    *(.RAM1_region)
-
-    . = ALIGN(8);
-    _eRAM1_region = .;         /* define a global symbol at section end */
-  } >RAM1
-
-  /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
-  . = ALIGN(8);
-  RAM2_region :
-  {
-    _sRAM2_region = .;         /* define a global symbol at section start */
-    *(.RAM2_region)
-
-    . = ALIGN(8);
-    _eRAM2_region = .;         /* define a global symbol at section end */
-  } >RAM2
-
-  /* User_heap_stack section, used to check that there is enough "SRAM1" Ram  type memory left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM1
-
-  /* Remove information from the compiler libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/linker/STM32WL55XX_FLASH_CM0PLUS.ld

@@ -1,178 +0,0 @@
-/*
-** LinkerScript
-** Note: For specific memory allocation, linker and startup files must be customized.
-**       Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script".
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
-
-_Min_Heap_Size  = 0x200; /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Memories definition */
-MEMORY
-{
-  ROM    (rx)    : ORIGIN = 0x08020000, LENGTH = 128K   /* Flash memory dedicated to CM0+ */
-  RAM1   (xrw)   : ORIGIN = 0x20004000, LENGTH = 16K    /* Non-backup SRAM1 dedicated to CM0+ */
-  RAM2   (xrw)   : ORIGIN = 0x2000C000, LENGTH = 16K    /* Backup SRAM2 dedicated to CM0+ */
-}
-
-/* Sections */
-SECTIONS
-{
-  /* The startup code into "ROM" Rom type memory */
-  .isr_vector :
-  {
-    . = ALIGN(8);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(8);
-  } >ROM
-
-  /* The program code and other data into "ROM" Rom type memory */
-  .text :
-  {
-    . = ALIGN(8);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(8);
-    _etext = .;        /* define a global symbols at end of code */
-  } >ROM
-
-  /* Constant data into "ROM" Rom type memory */
-  .rodata :
-  {
-    . = ALIGN(8);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(8);
-  } >ROM
-
-  .ARM.extab   : { 
-    . = ALIGN(8);
-    *(.ARM.extab* .gnu.linkonce.armextab.*)
-    . = ALIGN(8);
-  } >ROM
-  
-  .ARM : {
-    . = ALIGN(8);
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-    . = ALIGN(8);
-  } >ROM
-
-  .preinit_array     :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-  
-  .init_array :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-  
-  .fini_array :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-
-  /* Used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections into "SRAM1" Ram type memory */
-  .data : 
-  {
-    . = ALIGN(8);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(8);
-    _edata = .;        /* define a global symbol at data end */
-    
-  } >RAM1 AT> ROM
-
-  /* Uninitialized data section into "SRAM1" Ram type memory */
-  . = ALIGN(8);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss section */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(8);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM1
-
-  /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM0+ */
-  . = ALIGN(8);
-  RAM1_region :
-  {
-    _sRAM1_region = .;         /* define a global symbol at section start */
-    *(.RAM1_region)
-
-    . = ALIGN(8);
-    _eRAM1_region = .;         /* define a global symbol at section end */
-  } >RAM1
-
-  /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM0+ */
-  . = ALIGN(8);
-  RAM2_region :
-  {
-    _sRAM2_region = .;         /* define a global symbol at section start */
-    *(.RAM2_region)
-
-    . = ALIGN(8);
-    _eRAM2_region = .;         /* define a global symbol at section end */
-  } >RAM2
-
-  /* User_heap_stack section, used to check that there is enough "SRAM1" Ram  type memory left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM1
-
-  /* Remove information from the compiler libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/linker/STM32WL55XX_FLASH_CM4.ld

@@ -1,178 +0,0 @@
-/*
-** LinkerScript
-** Note: For specific memory allocation, linker and startup files must be customized.
-**       Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script".
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
-
-_Min_Heap_Size  = 0x200; /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Memories definition */
-MEMORY
-{
-  ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 128K   /* Flash memory dedicated to CM4 */
-  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 16K    /* Non-backup SRAM1 dedicated to CM4 */
-  RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 16K    /* Backup SRAM2 dedicated to CM4 */
-}
-
-/* Sections */
-SECTIONS
-{
-  /* The startup code into "ROM" Rom type memory */
-  .isr_vector :
-  {
-    . = ALIGN(8);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(8);
-  } >ROM
-
-  /* The program code and other data into "ROM" Rom type memory */
-  .text :
-  {
-    . = ALIGN(8);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(8);
-    _etext = .;        /* define a global symbols at end of code */
-  } >ROM
-
-  /* Constant data into "ROM" Rom type memory */
-  .rodata :
-  {
-    . = ALIGN(8);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(8);
-  } >ROM
-
-  .ARM.extab   : { 
-    . = ALIGN(8);
-    *(.ARM.extab* .gnu.linkonce.armextab.*)
-    . = ALIGN(8);
-  } >ROM
-  
-  .ARM : {
-    . = ALIGN(8);
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-    . = ALIGN(8);
-  } >ROM
-
-  .preinit_array     :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-  
-  .init_array :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-  
-  .fini_array :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-
-  /* Used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections into "SRAM1" Ram type memory */
-  .data : 
-  {
-    . = ALIGN(8);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(8);
-    _edata = .;        /* define a global symbol at data end */
-    
-  } >RAM1 AT> ROM
-
-  /* Uninitialized data section into "SRAM1" Ram type memory */
-  . = ALIGN(8);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss section */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(8);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM1
-
-  /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
-  . = ALIGN(8);
-  RAM1_region :
-  {
-    _sRAM1_region = .;         /* define a global symbol at section start */
-    *(.RAM1_region)
-
-    . = ALIGN(8);
-    _eRAM1_region = .;         /* define a global symbol at section end */
-  } >RAM1
-
-  /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
-  . = ALIGN(8);
-  RAM2_region :
-  {
-    _sRAM2_region = .;         /* define a global symbol at section start */
-    *(.RAM2_region)
-
-    . = ALIGN(8);
-    _eRAM2_region = .;         /* define a global symbol at section end */
-  } >RAM2
-
-  /* User_heap_stack section, used to check that there is enough "SRAM1" Ram  type memory left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM1
-
-  /* Remove information from the compiler libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/linker/STM32WLE4XX_FLASH.ld

@@ -1,178 +0,0 @@
-/*
-** LinkerScript
-** Note: For specific memory allocation, linker and startup files must be customized.
-**       Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script".
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
-
-_Min_Heap_Size  = 0x200; /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Memories definition */
-MEMORY
-{
-  ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 256K
-  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 32K    /* Non-backup SRAM1 */
-  RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 32K    /* Backup SRAM2 */
-}
-
-/* Sections */
-SECTIONS
-{
-  /* The startup code into "ROM" Rom type memory */
-  .isr_vector :
-  {
-    . = ALIGN(8);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(8);
-  } >ROM
-
-  /* The program code and other data into "ROM" Rom type memory */
-  .text :
-  {
-    . = ALIGN(8);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(8);
-    _etext = .;        /* define a global symbols at end of code */
-  } >ROM
-
-  /* Constant data into "ROM" Rom type memory */
-  .rodata :
-  {
-    . = ALIGN(8);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(8);
-  } >ROM
-
-  .ARM.extab   : { 
-    . = ALIGN(8);
-    *(.ARM.extab* .gnu.linkonce.armextab.*)
-    . = ALIGN(8);
-  } >ROM
-  
-  .ARM : {
-    . = ALIGN(8);
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-    . = ALIGN(8);
-  } >ROM
-
-  .preinit_array     :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-  
-  .init_array :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-  
-  .fini_array :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-
-  /* Used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections into "SRAM1" Ram type memory */
-  .data : 
-  {
-    . = ALIGN(8);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(8);
-    _edata = .;        /* define a global symbol at data end */
-    
-  } >RAM1 AT> ROM
-
-  /* Uninitialized data section into "SRAM1" Ram type memory */
-  . = ALIGN(8);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss section */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(8);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM1
-
-  /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
-  . = ALIGN(8);
-  RAM1_region :
-  {
-    _sRAM1_region = .;         /* define a global symbol at section start */
-    *(.RAM1_region)
-
-    . = ALIGN(8);
-    _eRAM1_region = .;         /* define a global symbol at section end */
-  } >RAM1
-
-  /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
-  . = ALIGN(8);
-  RAM2_region :
-  {
-    _sRAM2_region = .;         /* define a global symbol at section start */
-    *(.RAM2_region)
-
-    . = ALIGN(8);
-    _eRAM2_region = .;         /* define a global symbol at section end */
-  } >RAM2
-
-  /* User_heap_stack section, used to check that there is enough "SRAM1" Ram  type memory left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM1
-
-  /* Remove information from the compiler libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/linker/STM32WLE5XX_FLASH.ld

@@ -1,178 +0,0 @@
-/*
-** LinkerScript
-** Note: For specific memory allocation, linker and startup files must be customized.
-**       Refer to STM32CubeIDE user guide (UM2609), chapter "Modify the linker script".
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-/* Highest address of the user mode stack */
-_estack = ORIGIN(RAM1) + LENGTH(RAM1); /* end of "SRAM1" Ram type memory */
-
-_Min_Heap_Size  = 0x200; /* required amount of heap  */
-_Min_Stack_Size = 0x400; /* required amount of stack */
-
-/* Memories definition */
-MEMORY
-{
-  ROM    (rx)    : ORIGIN = 0x08000000, LENGTH = 256K
-  RAM1   (xrw)   : ORIGIN = 0x20000000, LENGTH = 32K    /* Non-backup SRAM1 */
-  RAM2   (xrw)   : ORIGIN = 0x20008000, LENGTH = 32K    /* Backup SRAM2 */
-}
-
-/* Sections */
-SECTIONS
-{
-  /* The startup code into "ROM" Rom type memory */
-  .isr_vector :
-  {
-    . = ALIGN(8);
-    KEEP(*(.isr_vector)) /* Startup code */
-    . = ALIGN(8);
-  } >ROM
-
-  /* The program code and other data into "ROM" Rom type memory */
-  .text :
-  {
-    . = ALIGN(8);
-    *(.text)           /* .text sections (code) */
-    *(.text*)          /* .text* sections (code) */
-    *(.glue_7)         /* glue arm to thumb code */
-    *(.glue_7t)        /* glue thumb to arm code */
-    *(.eh_frame)
-
-    KEEP (*(.init))
-    KEEP (*(.fini))
-
-    . = ALIGN(8);
-    _etext = .;        /* define a global symbols at end of code */
-  } >ROM
-
-  /* Constant data into "ROM" Rom type memory */
-  .rodata :
-  {
-    . = ALIGN(8);
-    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
-    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
-    . = ALIGN(8);
-  } >ROM
-
-  .ARM.extab   : { 
-    . = ALIGN(8);
-    *(.ARM.extab* .gnu.linkonce.armextab.*)
-    . = ALIGN(8);
-  } >ROM
-  
-  .ARM : {
-    . = ALIGN(8);
-    __exidx_start = .;
-    *(.ARM.exidx*)
-    __exidx_end = .;
-    . = ALIGN(8);
-  } >ROM
-
-  .preinit_array     :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__preinit_array_start = .);
-    KEEP (*(.preinit_array*))
-    PROVIDE_HIDDEN (__preinit_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-  
-  .init_array :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__init_array_start = .);
-    KEEP (*(SORT(.init_array.*)))
-    KEEP (*(.init_array*))
-    PROVIDE_HIDDEN (__init_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-  
-  .fini_array :
-  {
-    . = ALIGN(8);
-    PROVIDE_HIDDEN (__fini_array_start = .);
-    KEEP (*(SORT(.fini_array.*)))
-    KEEP (*(.fini_array*))
-    PROVIDE_HIDDEN (__fini_array_end = .);
-    . = ALIGN(8);
-  } >ROM
-
-  /* Used by the startup to initialize data */
-  _sidata = LOADADDR(.data);
-
-  /* Initialized data sections into "SRAM1" Ram type memory */
-  .data : 
-  {
-    . = ALIGN(8);
-    _sdata = .;        /* create a global symbol at data start */
-    *(.data)           /* .data sections */
-    *(.data*)          /* .data* sections */
-
-    . = ALIGN(8);
-    _edata = .;        /* define a global symbol at data end */
-    
-  } >RAM1 AT> ROM
-
-  /* Uninitialized data section into "SRAM1" Ram type memory */
-  . = ALIGN(8);
-  .bss :
-  {
-    /* This is used by the startup in order to initialize the .bss section */
-    _sbss = .;         /* define a global symbol at bss start */
-    __bss_start__ = _sbss;
-    *(.bss)
-    *(.bss*)
-    *(COMMON)
-
-    . = ALIGN(8);
-    _ebss = .;         /* define a global symbol at bss end */
-    __bss_end__ = _ebss;
-  } >RAM1
-
-  /* Data section into "SRAM1" Ram type memory: Non-backup SRAM1 dedicated to CM4 */
-  . = ALIGN(8);
-  RAM1_region :
-  {
-    _sRAM1_region = .;         /* define a global symbol at section start */
-    *(.RAM1_region)
-
-    . = ALIGN(8);
-    _eRAM1_region = .;         /* define a global symbol at section end */
-  } >RAM1
-
-  /* Data section into "SRAM2" Ram type memory: Backup SRAM2 dedicated to CM4 */
-  . = ALIGN(8);
-  RAM2_region :
-  {
-    _sRAM2_region = .;         /* define a global symbol at section start */
-    *(.RAM2_region)
-
-    . = ALIGN(8);
-    _eRAM2_region = .;         /* define a global symbol at section end */
-  } >RAM2
-
-  /* User_heap_stack section, used to check that there is enough "SRAM1" Ram  type memory left */
-  ._user_heap_stack :
-  {
-    . = ALIGN(8);
-    PROVIDE ( end = . );
-    PROVIDE ( _end = . );
-    . = . + _Min_Heap_Size;
-    . = . + _Min_Stack_Size;
-    . = ALIGN(8);
-  } >RAM1
-
-  /* Remove information from the compiler libraries */
-  /DISCARD/ :
-  {
-    libc.a ( * )
-    libm.a ( * )
-    libgcc.a ( * )
-  }
-
-  .ARM.attributes 0 : { *(.ARM.attributes) }
-}

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wl54xx_cm0plus.s

@@ -1,303 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32wl54xx_cm0plus.s
-  * @author    MCD Application Team
-  * @brief     STM32WL54xx devices Cortex-M0+ vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address,
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2020(-2021) STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-.syntax unified
-.cpu cortex-m0plus
-.fpu softvfp
-.thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Call the clock system initialization function.*/
-  bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-  bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-
-LoopForever:
-    b LoopForever
-
-  .size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-  .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-
-/******************************************************************************
-*
-* The STM32WL54xx Cortex-M0+ vector table.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word	0
-  .word	0
-  .word	0
-  .word	0
-  .word	0
-  .word	0
-  .word	0
-  .word	SVC_Handler
-  .word	0
-  .word	0
-  .word	PendSV_Handler
-  .word	SysTick_Handler
-  .word	TZIC_ILA_IRQHandler                  			/* TZIC ILA Interrupt                                 */
-  .word	PVD_PVM_IRQHandler                   			/* PVD and PVM interrupt through EXTI                 */
-  .word	RTC_LSECSS_IRQHandler                			/* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
-  .word	RCC_FLASH_C1SEV_IRQHandler           			/* RCC and FLASH and CPU1 M4 SEV Interrupt            */
-  .word	EXTI1_0_IRQHandler                   			/* EXTI Line 1:0 Interrupt                            */
-  .word	EXTI3_2_IRQHandler                   			/* EXTI Line 3:2 Interrupt                            */
-  .word	EXTI15_4_IRQHandler                  			/* EXTI Line 15:4 interrupt                           */
-  .word	ADC_COMP_DAC_IRQHandler              			/* ADC, COMP1, COMP2, DAC Interrupt                   */
-  .word	DMA1_Channel1_2_3_IRQHandler         			/* DMA1 Channel 1 to 3 Interrupt                      */
-  .word	DMA1_Channel4_5_6_7_IRQHandler       			/* DMA1 Channels 4,5,6,7 Interrupt                    */
-  .word	DMA2_DMAMUX1_OVR_IRQHandler          			/* DMA2 Channels[1..7] and DMAMUX Overrun Interrupts  */
-  .word	LPTIM1_IRQHandler                    			/* LPTIM1 Global Interrupt                            */
-  .word	LPTIM2_IRQHandler                    			/* LPTIM2 Global Interrupt                            */
-  .word	LPTIM3_IRQHandler                    			/* LPTIM3 Global Interrupt                            */
-  .word	TIM1_IRQHandler                      			/* TIM1 Global Interrupt                              */
-  .word	TIM2_IRQHandler                      			/* TIM2 Global Interrupt                              */
-  .word	TIM16_IRQHandler                     			/* TIM16 Global Interrupt                             */
-  .word	TIM17_IRQHandler                     			/* TIM17 Global Interrupt                             */
-  .word	IPCC_C2_RX_C2_TX_IRQHandler          			/* IPCC RX Occupied and TX Free Interrupt Interrupt   */
-  .word	HSEM_IRQHandler                      			/* Semaphore Interrupt                                */
-  .word	RNG_IRQHandler                       			/* RNG Interrupt                                      */
-  .word	AES_PKA_IRQHandler                   			/* COMP1 and COMP2 interrupt through EXTI             */
-  .word	I2C1_IRQHandler                      			/* I2C1 Event and Error Interrupt                     */
-  .word	I2C2_IRQHandler                      			/* I2C2 Event and Error Interrupt                     */
-  .word	I2C3_IRQHandler                      			/* I2C3 Event and Error Interrupt                     */
-  .word	SPI1_IRQHandler                      			/* SPI1 Interrupt                                     */
-  .word	SPI2_IRQHandler                      			/* SPI2 Interrupt                                     */
-  .word	USART1_IRQHandler                    			/* USART1 Interrupt                                   */
-  .word	USART2_IRQHandler                    			/* USART2 Interrupt                                   */
-  .word	LPUART1_IRQHandler                   			/* LPUART1 Interrupt                                  */
-  .word	SUBGHZSPI_IRQHandler                 			/* SUBGHZSPI Interrupt                                */
-  .word	SUBGHZ_Radio_IRQHandler              			/* SUBGHZ Radio Interrupt                             */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-	.weak	NMI_Handler
-	.thumb_set NMI_Handler,Default_Handler
-
-	.weak	HardFault_Handler
-	.thumb_set HardFault_Handler,Default_Handler
-
-	.weak	SVC_Handler
-	.thumb_set SVC_Handler,Default_Handler
-
-	.weak	PendSV_Handler
-	.thumb_set PendSV_Handler,Default_Handler
-
-	.weak	SysTick_Handler
-	.thumb_set SysTick_Handler,Default_Handler
-
-	.weak	TZIC_ILA_IRQHandler
-	.thumb_set TZIC_ILA_IRQHandler,Default_Handler
-
-	.weak	PVD_PVM_IRQHandler
-	.thumb_set PVD_PVM_IRQHandler,Default_Handler
-
-	.weak	RTC_LSECSS_IRQHandler
-	.thumb_set RTC_LSECSS_IRQHandler,Default_Handler
-
-	.weak	RCC_FLASH_C1SEV_IRQHandler
-	.thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
-
-	.weak	EXTI1_0_IRQHandler
-	.thumb_set EXTI1_0_IRQHandler,Default_Handler
-
-	.weak	EXTI3_2_IRQHandler
-	.thumb_set EXTI3_2_IRQHandler,Default_Handler
-
-	.weak	EXTI15_4_IRQHandler
-	.thumb_set EXTI15_4_IRQHandler,Default_Handler
-
-	.weak	ADC_COMP_DAC_IRQHandler
-	.thumb_set ADC_COMP_DAC_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel1_2_3_IRQHandler
-	.thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel4_5_6_7_IRQHandler
-	.thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-	.weak	DMA2_DMAMUX1_OVR_IRQHandler
-	.thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
-
-	.weak	LPTIM1_IRQHandler
-	.thumb_set LPTIM1_IRQHandler,Default_Handler
-
-	.weak	LPTIM2_IRQHandler
-	.thumb_set LPTIM2_IRQHandler,Default_Handler
-
-	.weak	LPTIM3_IRQHandler
-	.thumb_set LPTIM3_IRQHandler,Default_Handler
-
-	.weak	TIM1_IRQHandler
-	.thumb_set TIM1_IRQHandler,Default_Handler
-
-	.weak	TIM2_IRQHandler
-	.thumb_set TIM2_IRQHandler,Default_Handler
-
-	.weak	TIM16_IRQHandler
-	.thumb_set TIM16_IRQHandler,Default_Handler
-
-	.weak	TIM17_IRQHandler
-	.thumb_set TIM17_IRQHandler,Default_Handler
-
-	.weak	IPCC_C2_RX_C2_TX_IRQHandler
-	.thumb_set IPCC_C2_RX_C2_TX_IRQHandler,Default_Handler
-
-	.weak	HSEM_IRQHandler
-	.thumb_set HSEM_IRQHandler,Default_Handler
-
-	.weak	RNG_IRQHandler
-	.thumb_set RNG_IRQHandler,Default_Handler
-
-	.weak	AES_PKA_IRQHandler
-	.thumb_set AES_PKA_IRQHandler,Default_Handler
-
-	.weak	I2C1_IRQHandler
-	.thumb_set I2C1_IRQHandler,Default_Handler
-
-	.weak	I2C2_IRQHandler
-	.thumb_set I2C2_IRQHandler,Default_Handler
-
-	.weak	I2C3_IRQHandler
-	.thumb_set I2C3_IRQHandler,Default_Handler
-
-	.weak	SPI1_IRQHandler
-	.thumb_set SPI1_IRQHandler,Default_Handler
-
-	.weak	SPI2_IRQHandler
-	.thumb_set SPI2_IRQHandler,Default_Handler
-
-	.weak	USART1_IRQHandler
-	.thumb_set USART1_IRQHandler,Default_Handler
-
-	.weak	USART2_IRQHandler
-	.thumb_set USART2_IRQHandler,Default_Handler
-
-	.weak	LPUART1_IRQHandler
-	.thumb_set LPUART1_IRQHandler,Default_Handler
-
-	.weak	SUBGHZSPI_IRQHandler
-	.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
-
-	.weak	SUBGHZ_Radio_IRQHandler
-	.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
-
-	.weak	SystemInit
-
-/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wl54xx_cm4.s

@@ -1,435 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32wl54xx_cm4.s
-  * @author    MCD Application Team
-  * @brief     STM32WL54xx devices Cortex-M4 vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address,
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M4 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2020(-2021) STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-.syntax unified
-.cpu cortex-m4
-.fpu softvfp
-.thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Call the clock system initialization function.*/
-  bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-  bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-
-LoopForever:
-    b LoopForever
-
-  .size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-  .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-
-/******************************************************************************
-*
-* The STM32WL54xx Cortex-M4 vector table.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word	MemManage_Handler
-  .word	BusFault_Handler
-  .word	UsageFault_Handler
-  .word	0
-  .word	0
-  .word	0
-  .word	0
-  .word	SVC_Handler
-  .word	DebugMon_Handler
-  .word	0
-  .word	PendSV_Handler
-  .word	SysTick_Handler
-  .word	WWDG_IRQHandler                      			/* Window Watchdog interrupt                          */
-  .word	PVD_PVM_IRQHandler                   			/* PVD and PVM interrupt through EXTI                 */
-  .word	TAMP_STAMP_LSECSS_SSRU_IRQHandler    			/* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
-  .word	RTC_WKUP_IRQHandler                  			/* RTC wakeup interrupt through EXTI[19]              */
-  .word	FLASH_IRQHandler                     			/* Flash memory global interrupt and Flash memory ECC */
-  .word	RCC_IRQHandler                       			/* RCC global interrupt                               */
-  .word	EXTI0_IRQHandler                     			/* EXTI line 0 interrupt                              */
-  .word	EXTI1_IRQHandler                     			/* EXTI line 1 interrupt                              */
-  .word	EXTI2_IRQHandler                     			/* EXTI line 2 interrupt                              */
-  .word	EXTI3_IRQHandler                     			/* EXTI line 3 interrupt                              */
-  .word	EXTI4_IRQHandler                     			/* EXTI line 4 interrupt                              */
-  .word	DMA1_Channel1_IRQHandler             			/* DMA1 channel 1 interrupt                           */
-  .word	DMA1_Channel2_IRQHandler             			/* DMA1 channel 2 interrupt                           */
-  .word	DMA1_Channel3_IRQHandler             			/* DMA1 channel 3 interrupt                           */
-  .word	DMA1_Channel4_IRQHandler             			/* DMA1 channel 4 interrupt                           */
-  .word	DMA1_Channel5_IRQHandler             			/* DMA1 channel 5 interrupt                           */
-  .word	DMA1_Channel6_IRQHandler             			/* DMA1 channel 6 interrupt                           */
-  .word	DMA1_Channel7_IRQHandler             			/* DMA1 channel 7 interrupt                           */
-  .word	ADC_IRQHandler                       			/* ADC interrupt                                      */
-  .word	DAC_IRQHandler                       			/* DAC interrupt                                      */
-  .word	C2SEV_PWR_C2H_IRQHandler             			/* CPU M0+ SEV Interrupt                              */
-  .word	COMP_IRQHandler                      			/* COMP1 and COMP2 interrupt through EXTI             */
-  .word	EXTI9_5_IRQHandler                   			/* EXTI line 9_5 interrupt                            */
-  .word	TIM1_BRK_IRQHandler                  			/* Timer 1 break interrupt                            */
-  .word	TIM1_UP_IRQHandler                   			/* Timer 1 Update                                     */
-  .word	TIM1_TRG_COM_IRQHandler              			/* Timer 1 trigger and communication                  */
-  .word	TIM1_CC_IRQHandler                   			/* Timer 1 capture compare interrupt                  */
-  .word	TIM2_IRQHandler                      			/* TIM2 global interrupt                              */
-  .word	TIM16_IRQHandler                     			/* Timer 16 global interrupt                          */
-  .word	TIM17_IRQHandler                     			/* Timer 17 global interrupt                          */
-  .word	I2C1_EV_IRQHandler                   			/* I2C1 event interrupt                               */
-  .word	I2C1_ER_IRQHandler                   			/* I2C1 event interrupt                               */
-  .word	I2C2_EV_IRQHandler                   			/* I2C2 error interrupt                               */
-  .word	I2C2_ER_IRQHandler                   			/* I2C2 error interrupt                               */
-  .word	SPI1_IRQHandler                      			/* SPI1 global interrupt                              */
-  .word	SPI2_IRQHandler                      			/* SPI2 global interrupt                              */
-  .word	USART1_IRQHandler                    			/* USART1 global interrupt                            */
-  .word	USART2_IRQHandler                    			/* USART2 global interrupt                            */
-  .word	LPUART1_IRQHandler                   			/* LPUART1 global interrupt                           */
-  .word	LPTIM1_IRQHandler                    			/* LPtimer 1 global interrupt                         */
-  .word	LPTIM2_IRQHandler                    			/* LPtimer 2 global interrupt                         */
-  .word	EXTI15_10_IRQHandler                 			/* EXTI line 15_10] interrupt through EXTI            */
-  .word	RTC_Alarm_IRQHandler                 			/* RTC Alarms A & B interrupt                         */
-  .word	LPTIM3_IRQHandler                    			/* LPtimer 3 global interrupt                         */
-  .word	SUBGHZSPI_IRQHandler                 			/* SUBGHZSPI global interrupt                         */
-  .word	IPCC_C1_RX_IRQHandler                			/* IPCC CPU1 RX occupied interrupt                    */
-  .word	IPCC_C1_TX_IRQHandler                			/* IPCC CPU1 RX free interrupt                        */
-  .word	HSEM_IRQHandler                      			/* Semaphore interrupt 0 to CPU1                      */
-  .word	I2C3_EV_IRQHandler                   			/* I2C3 event interrupt                               */
-  .word	I2C3_ER_IRQHandler                   			/* I2C3 error interrupt                               */
-  .word	SUBGHZ_Radio_IRQHandler              			/* Radio IRQs RFBUSY interrupt through EXTI           */
-  .word	AES_IRQHandler                       			/* AES global interrupt                               */
-  .word	RNG_IRQHandler                       			/* RNG interrupt                                      */
-  .word	PKA_IRQHandler                       			/* PKA interrupt                                      */
-  .word	DMA2_Channel1_IRQHandler             			/* DMA2 channel 1 interrupt                           */
-  .word	DMA2_Channel2_IRQHandler             			/* DMA2 channel 2 interrupt                           */
-  .word	DMA2_Channel3_IRQHandler             			/* DMA2 channel 3 interrupt                           */
-  .word	DMA2_Channel4_IRQHandler             			/* DMA2 channel 4 interrupt                           */
-  .word	DMA2_Channel5_IRQHandler             			/* DMA2 channel 5 interrupt                           */
-  .word	DMA2_Channel6_IRQHandler             			/* DMA2 channel 6 interrupt                           */
-  .word	DMA2_Channel7_IRQHandler             			/* DMA2 channel 7 interrupt                           */
-  .word	DMAMUX1_OVR_IRQHandler               			/* DMAMUX overrun interrupt                           */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-	.weak	NMI_Handler
-	.thumb_set NMI_Handler,Default_Handler
-
-	.weak	HardFault_Handler
-	.thumb_set HardFault_Handler,Default_Handler
-
-	.weak	MemManage_Handler
-	.thumb_set MemManage_Handler,Default_Handler
-
-	.weak	BusFault_Handler
-	.thumb_set BusFault_Handler,Default_Handler
-
-	.weak	UsageFault_Handler
-	.thumb_set UsageFault_Handler,Default_Handler
-
-	.weak	SVC_Handler
-	.thumb_set SVC_Handler,Default_Handler
-
-	.weak	DebugMon_Handler
-	.thumb_set DebugMon_Handler,Default_Handler
-
-	.weak	PendSV_Handler
-	.thumb_set PendSV_Handler,Default_Handler
-
-	.weak	SysTick_Handler
-	.thumb_set SysTick_Handler,Default_Handler
-
-	.weak	WWDG_IRQHandler
-	.thumb_set WWDG_IRQHandler,Default_Handler
-
-	.weak	PVD_PVM_IRQHandler
-	.thumb_set PVD_PVM_IRQHandler,Default_Handler
-
-	.weak	TAMP_STAMP_LSECSS_SSRU_IRQHandler
-	.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
-
-	.weak	RTC_WKUP_IRQHandler
-	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-	.weak	FLASH_IRQHandler
-	.thumb_set FLASH_IRQHandler,Default_Handler
-
-	.weak	RCC_IRQHandler
-	.thumb_set RCC_IRQHandler,Default_Handler
-
-	.weak	EXTI0_IRQHandler
-	.thumb_set EXTI0_IRQHandler,Default_Handler
-
-	.weak	EXTI1_IRQHandler
-	.thumb_set EXTI1_IRQHandler,Default_Handler
-
-	.weak	EXTI2_IRQHandler
-	.thumb_set EXTI2_IRQHandler,Default_Handler
-
-	.weak	EXTI3_IRQHandler
-	.thumb_set EXTI3_IRQHandler,Default_Handler
-
-	.weak	EXTI4_IRQHandler
-	.thumb_set EXTI4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel1_IRQHandler
-	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel2_IRQHandler
-	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel3_IRQHandler
-	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel4_IRQHandler
-	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel5_IRQHandler
-	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel6_IRQHandler
-	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel7_IRQHandler
-	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-	.weak	ADC_IRQHandler
-	.thumb_set ADC_IRQHandler,Default_Handler
-
-	.weak	DAC_IRQHandler
-	.thumb_set DAC_IRQHandler,Default_Handler
-
-	.weak	C2SEV_PWR_C2H_IRQHandler
-	.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
-
-	.weak	COMP_IRQHandler
-	.thumb_set COMP_IRQHandler,Default_Handler
-
-	.weak	EXTI9_5_IRQHandler
-	.thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-	.weak	TIM1_BRK_IRQHandler
-	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-	.weak	TIM1_UP_IRQHandler
-	.thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-	.weak	TIM1_TRG_COM_IRQHandler
-	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-	.weak	TIM1_CC_IRQHandler
-	.thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-	.weak	TIM2_IRQHandler
-	.thumb_set TIM2_IRQHandler,Default_Handler
-
-	.weak	TIM16_IRQHandler
-	.thumb_set TIM16_IRQHandler,Default_Handler
-
-	.weak	TIM17_IRQHandler
-	.thumb_set TIM17_IRQHandler,Default_Handler
-
-	.weak	I2C1_EV_IRQHandler
-	.thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-	.weak	I2C1_ER_IRQHandler
-	.thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-	.weak	I2C2_EV_IRQHandler
-	.thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-	.weak	I2C2_ER_IRQHandler
-	.thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-	.weak	SPI1_IRQHandler
-	.thumb_set SPI1_IRQHandler,Default_Handler
-
-	.weak	SPI2_IRQHandler
-	.thumb_set SPI2_IRQHandler,Default_Handler
-
-	.weak	USART1_IRQHandler
-	.thumb_set USART1_IRQHandler,Default_Handler
-
-	.weak	USART2_IRQHandler
-	.thumb_set USART2_IRQHandler,Default_Handler
-
-	.weak	LPUART1_IRQHandler
-	.thumb_set LPUART1_IRQHandler,Default_Handler
-
-	.weak	LPTIM1_IRQHandler
-	.thumb_set LPTIM1_IRQHandler,Default_Handler
-
-	.weak	LPTIM2_IRQHandler
-	.thumb_set LPTIM2_IRQHandler,Default_Handler
-
-	.weak	EXTI15_10_IRQHandler
-	.thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-	.weak	RTC_Alarm_IRQHandler
-	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-	.weak	LPTIM3_IRQHandler
-	.thumb_set LPTIM3_IRQHandler,Default_Handler
-
-	.weak	SUBGHZSPI_IRQHandler
-	.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
-
-	.weak	IPCC_C1_RX_IRQHandler
-	.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
-
-	.weak	IPCC_C1_TX_IRQHandler
-	.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
-
-	.weak	HSEM_IRQHandler
-	.thumb_set HSEM_IRQHandler,Default_Handler
-
-	.weak	I2C3_EV_IRQHandler
-	.thumb_set I2C3_EV_IRQHandler,Default_Handler
-
-	.weak	I2C3_ER_IRQHandler
-	.thumb_set I2C3_ER_IRQHandler,Default_Handler
-
-	.weak	SUBGHZ_Radio_IRQHandler
-	.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
-
-	.weak	AES_IRQHandler
-	.thumb_set AES_IRQHandler,Default_Handler
-
-	.weak	RNG_IRQHandler
-	.thumb_set RNG_IRQHandler,Default_Handler
-
-	.weak	PKA_IRQHandler
-	.thumb_set PKA_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel1_IRQHandler
-	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel2_IRQHandler
-	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel3_IRQHandler
-	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel4_IRQHandler
-	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel5_IRQHandler
-	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel6_IRQHandler
-	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel7_IRQHandler
-	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
-
-	.weak	DMAMUX1_OVR_IRQHandler
-	.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-
-	.weak	SystemInit
-
-/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wl55xx_cm0plus.s

@@ -1,303 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32wl55xx_cm0plus.s
-  * @author    MCD Application Team
-  * @brief     STM32WL55xx devices Cortex-M0+ vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address,
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2020(-2021) STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-.syntax unified
-.cpu cortex-m0plus
-.fpu softvfp
-.thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Call the clock system initialization function.*/
-  bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-  bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-
-LoopForever:
-    b LoopForever
-
-  .size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-  .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-
-/******************************************************************************
-*
-* The STM32WL55xx Cortex-M0+ vector table.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word	0
-  .word	0
-  .word	0
-  .word	0
-  .word	0
-  .word	0
-  .word	0
-  .word	SVC_Handler
-  .word	0
-  .word	0
-  .word	PendSV_Handler
-  .word	SysTick_Handler
-  .word	TZIC_ILA_IRQHandler                  			/* TZIC ILA Interrupt                                 */
-  .word	PVD_PVM_IRQHandler                   			/* PVD and PVM interrupt through EXTI                 */
-  .word	RTC_LSECSS_IRQHandler                			/* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
-  .word	RCC_FLASH_C1SEV_IRQHandler           			/* RCC and FLASH and CPU1 M4 SEV Interrupt            */
-  .word	EXTI1_0_IRQHandler                   			/* EXTI Line 1:0 Interrupt                            */
-  .word	EXTI3_2_IRQHandler                   			/* EXTI Line 3:2 Interrupt                            */
-  .word	EXTI15_4_IRQHandler                  			/* EXTI Line 15:4 interrupt                           */
-  .word	ADC_COMP_DAC_IRQHandler              			/* ADC, COMP1, COMP2, DAC Interrupt                   */
-  .word	DMA1_Channel1_2_3_IRQHandler         			/* DMA1 Channel 1 to 3 Interrupt                      */
-  .word	DMA1_Channel4_5_6_7_IRQHandler       			/* DMA1 Channels 4,5,6,7 Interrupt                    */
-  .word	DMA2_DMAMUX1_OVR_IRQHandler          			/* DMA2 Channels[1..7] and DMAMUX Overrun Interrupts  */
-  .word	LPTIM1_IRQHandler                    			/* LPTIM1 Global Interrupt                            */
-  .word	LPTIM2_IRQHandler                    			/* LPTIM2 Global Interrupt                            */
-  .word	LPTIM3_IRQHandler                    			/* LPTIM3 Global Interrupt                            */
-  .word	TIM1_IRQHandler                      			/* TIM1 Global Interrupt                              */
-  .word	TIM2_IRQHandler                      			/* TIM2 Global Interrupt                              */
-  .word	TIM16_IRQHandler                     			/* TIM16 Global Interrupt                             */
-  .word	TIM17_IRQHandler                     			/* TIM17 Global Interrupt                             */
-  .word	IPCC_C2_RX_C2_TX_IRQHandler          			/* IPCC RX Occupied and TX Free Interrupt Interrupt   */
-  .word	HSEM_IRQHandler                      			/* Semaphore Interrupt                                */
-  .word	RNG_IRQHandler                       			/* RNG Interrupt                                      */
-  .word	AES_PKA_IRQHandler                   			/* COMP1 and COMP2 interrupt through EXTI             */
-  .word	I2C1_IRQHandler                      			/* I2C1 Event and Error Interrupt                     */
-  .word	I2C2_IRQHandler                      			/* I2C2 Event and Error Interrupt                     */
-  .word	I2C3_IRQHandler                      			/* I2C3 Event and Error Interrupt                     */
-  .word	SPI1_IRQHandler                      			/* SPI1 Interrupt                                     */
-  .word	SPI2_IRQHandler                      			/* SPI2 Interrupt                                     */
-  .word	USART1_IRQHandler                    			/* USART1 Interrupt                                   */
-  .word	USART2_IRQHandler                    			/* USART2 Interrupt                                   */
-  .word	LPUART1_IRQHandler                   			/* LPUART1 Interrupt                                  */
-  .word	SUBGHZSPI_IRQHandler                 			/* SUBGHZSPI Interrupt                                */
-  .word	SUBGHZ_Radio_IRQHandler              			/* SUBGHZ Radio Interrupt                             */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-	.weak	NMI_Handler
-	.thumb_set NMI_Handler,Default_Handler
-
-	.weak	HardFault_Handler
-	.thumb_set HardFault_Handler,Default_Handler
-
-	.weak	SVC_Handler
-	.thumb_set SVC_Handler,Default_Handler
-
-	.weak	PendSV_Handler
-	.thumb_set PendSV_Handler,Default_Handler
-
-	.weak	SysTick_Handler
-	.thumb_set SysTick_Handler,Default_Handler
-
-	.weak	TZIC_ILA_IRQHandler
-	.thumb_set TZIC_ILA_IRQHandler,Default_Handler
-
-	.weak	PVD_PVM_IRQHandler
-	.thumb_set PVD_PVM_IRQHandler,Default_Handler
-
-	.weak	RTC_LSECSS_IRQHandler
-	.thumb_set RTC_LSECSS_IRQHandler,Default_Handler
-
-	.weak	RCC_FLASH_C1SEV_IRQHandler
-	.thumb_set RCC_FLASH_C1SEV_IRQHandler,Default_Handler
-
-	.weak	EXTI1_0_IRQHandler
-	.thumb_set EXTI1_0_IRQHandler,Default_Handler
-
-	.weak	EXTI3_2_IRQHandler
-	.thumb_set EXTI3_2_IRQHandler,Default_Handler
-
-	.weak	EXTI15_4_IRQHandler
-	.thumb_set EXTI15_4_IRQHandler,Default_Handler
-
-	.weak	ADC_COMP_DAC_IRQHandler
-	.thumb_set ADC_COMP_DAC_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel1_2_3_IRQHandler
-	.thumb_set DMA1_Channel1_2_3_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel4_5_6_7_IRQHandler
-	.thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-	.weak	DMA2_DMAMUX1_OVR_IRQHandler
-	.thumb_set DMA2_DMAMUX1_OVR_IRQHandler,Default_Handler
-
-	.weak	LPTIM1_IRQHandler
-	.thumb_set LPTIM1_IRQHandler,Default_Handler
-
-	.weak	LPTIM2_IRQHandler
-	.thumb_set LPTIM2_IRQHandler,Default_Handler
-
-	.weak	LPTIM3_IRQHandler
-	.thumb_set LPTIM3_IRQHandler,Default_Handler
-
-	.weak	TIM1_IRQHandler
-	.thumb_set TIM1_IRQHandler,Default_Handler
-
-	.weak	TIM2_IRQHandler
-	.thumb_set TIM2_IRQHandler,Default_Handler
-
-	.weak	TIM16_IRQHandler
-	.thumb_set TIM16_IRQHandler,Default_Handler
-
-	.weak	TIM17_IRQHandler
-	.thumb_set TIM17_IRQHandler,Default_Handler
-
-	.weak	IPCC_C2_RX_C2_TX_IRQHandler
-	.thumb_set IPCC_C2_RX_C2_TX_IRQHandler,Default_Handler
-
-	.weak	HSEM_IRQHandler
-	.thumb_set HSEM_IRQHandler,Default_Handler
-
-	.weak	RNG_IRQHandler
-	.thumb_set RNG_IRQHandler,Default_Handler
-
-	.weak	AES_PKA_IRQHandler
-	.thumb_set AES_PKA_IRQHandler,Default_Handler
-
-	.weak	I2C1_IRQHandler
-	.thumb_set I2C1_IRQHandler,Default_Handler
-
-	.weak	I2C2_IRQHandler
-	.thumb_set I2C2_IRQHandler,Default_Handler
-
-	.weak	I2C3_IRQHandler
-	.thumb_set I2C3_IRQHandler,Default_Handler
-
-	.weak	SPI1_IRQHandler
-	.thumb_set SPI1_IRQHandler,Default_Handler
-
-	.weak	SPI2_IRQHandler
-	.thumb_set SPI2_IRQHandler,Default_Handler
-
-	.weak	USART1_IRQHandler
-	.thumb_set USART1_IRQHandler,Default_Handler
-
-	.weak	USART2_IRQHandler
-	.thumb_set USART2_IRQHandler,Default_Handler
-
-	.weak	LPUART1_IRQHandler
-	.thumb_set LPUART1_IRQHandler,Default_Handler
-
-	.weak	SUBGHZSPI_IRQHandler
-	.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
-
-	.weak	SUBGHZ_Radio_IRQHandler
-	.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
-
-	.weak	SystemInit
-
-/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wl55xx_cm4.s

@@ -1,435 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32wl55xx_cm4.s
-  * @author    MCD Application Team
-  * @brief     STM32WL55xx devices Cortex-M4 vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address,
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M4 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2020(-2021) STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-.syntax unified
-.cpu cortex-m4
-.fpu softvfp
-.thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Call the clock system initialization function.*/
-  bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-  bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-
-LoopForever:
-    b LoopForever
-
-  .size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-  .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-
-/******************************************************************************
-*
-* The STM32WL55xx Cortex-M4 vector table.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word	MemManage_Handler
-  .word	BusFault_Handler
-  .word	UsageFault_Handler
-  .word	0
-  .word	0
-  .word	0
-  .word	0
-  .word	SVC_Handler
-  .word	DebugMon_Handler
-  .word	0
-  .word	PendSV_Handler
-  .word	SysTick_Handler
-  .word	WWDG_IRQHandler                      			/* Window Watchdog interrupt                          */
-  .word	PVD_PVM_IRQHandler                   			/* PVD and PVM interrupt through EXTI                 */
-  .word	TAMP_STAMP_LSECSS_SSRU_IRQHandler    			/* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
-  .word	RTC_WKUP_IRQHandler                  			/* RTC wakeup interrupt through EXTI[19]              */
-  .word	FLASH_IRQHandler                     			/* Flash memory global interrupt and Flash memory ECC */
-  .word	RCC_IRQHandler                       			/* RCC global interrupt                               */
-  .word	EXTI0_IRQHandler                     			/* EXTI line 0 interrupt                              */
-  .word	EXTI1_IRQHandler                     			/* EXTI line 1 interrupt                              */
-  .word	EXTI2_IRQHandler                     			/* EXTI line 2 interrupt                              */
-  .word	EXTI3_IRQHandler                     			/* EXTI line 3 interrupt                              */
-  .word	EXTI4_IRQHandler                     			/* EXTI line 4 interrupt                              */
-  .word	DMA1_Channel1_IRQHandler             			/* DMA1 channel 1 interrupt                           */
-  .word	DMA1_Channel2_IRQHandler             			/* DMA1 channel 2 interrupt                           */
-  .word	DMA1_Channel3_IRQHandler             			/* DMA1 channel 3 interrupt                           */
-  .word	DMA1_Channel4_IRQHandler             			/* DMA1 channel 4 interrupt                           */
-  .word	DMA1_Channel5_IRQHandler             			/* DMA1 channel 5 interrupt                           */
-  .word	DMA1_Channel6_IRQHandler             			/* DMA1 channel 6 interrupt                           */
-  .word	DMA1_Channel7_IRQHandler             			/* DMA1 channel 7 interrupt                           */
-  .word	ADC_IRQHandler                       			/* ADC interrupt                                      */
-  .word	DAC_IRQHandler                       			/* DAC interrupt                                      */
-  .word	C2SEV_PWR_C2H_IRQHandler             			/* CPU M0+ SEV Interrupt                              */
-  .word	COMP_IRQHandler                      			/* COMP1 and COMP2 interrupt through EXTI             */
-  .word	EXTI9_5_IRQHandler                   			/* EXTI line 9_5 interrupt                            */
-  .word	TIM1_BRK_IRQHandler                  			/* Timer 1 break interrupt                            */
-  .word	TIM1_UP_IRQHandler                   			/* Timer 1 Update                                     */
-  .word	TIM1_TRG_COM_IRQHandler              			/* Timer 1 trigger and communication                  */
-  .word	TIM1_CC_IRQHandler                   			/* Timer 1 capture compare interrupt                  */
-  .word	TIM2_IRQHandler                      			/* TIM2 global interrupt                              */
-  .word	TIM16_IRQHandler                     			/* Timer 16 global interrupt                          */
-  .word	TIM17_IRQHandler                     			/* Timer 17 global interrupt                          */
-  .word	I2C1_EV_IRQHandler                   			/* I2C1 event interrupt                               */
-  .word	I2C1_ER_IRQHandler                   			/* I2C1 event interrupt                               */
-  .word	I2C2_EV_IRQHandler                   			/* I2C2 error interrupt                               */
-  .word	I2C2_ER_IRQHandler                   			/* I2C2 error interrupt                               */
-  .word	SPI1_IRQHandler                      			/* SPI1 global interrupt                              */
-  .word	SPI2_IRQHandler                      			/* SPI2 global interrupt                              */
-  .word	USART1_IRQHandler                    			/* USART1 global interrupt                            */
-  .word	USART2_IRQHandler                    			/* USART2 global interrupt                            */
-  .word	LPUART1_IRQHandler                   			/* LPUART1 global interrupt                           */
-  .word	LPTIM1_IRQHandler                    			/* LPtimer 1 global interrupt                         */
-  .word	LPTIM2_IRQHandler                    			/* LPtimer 2 global interrupt                         */
-  .word	EXTI15_10_IRQHandler                 			/* EXTI line 15_10] interrupt through EXTI            */
-  .word	RTC_Alarm_IRQHandler                 			/* RTC Alarms A & B interrupt                         */
-  .word	LPTIM3_IRQHandler                    			/* LPtimer 3 global interrupt                         */
-  .word	SUBGHZSPI_IRQHandler                 			/* SUBGHZSPI global interrupt                         */
-  .word	IPCC_C1_RX_IRQHandler                			/* IPCC CPU1 RX occupied interrupt                    */
-  .word	IPCC_C1_TX_IRQHandler                			/* IPCC CPU1 RX free interrupt                        */
-  .word	HSEM_IRQHandler                      			/* Semaphore interrupt 0 to CPU1                      */
-  .word	I2C3_EV_IRQHandler                   			/* I2C3 event interrupt                               */
-  .word	I2C3_ER_IRQHandler                   			/* I2C3 error interrupt                               */
-  .word	SUBGHZ_Radio_IRQHandler              			/* Radio IRQs RFBUSY interrupt through EXTI           */
-  .word	AES_IRQHandler                       			/* AES global interrupt                               */
-  .word	RNG_IRQHandler                       			/* RNG interrupt                                      */
-  .word	PKA_IRQHandler                       			/* PKA interrupt                                      */
-  .word	DMA2_Channel1_IRQHandler             			/* DMA2 channel 1 interrupt                           */
-  .word	DMA2_Channel2_IRQHandler             			/* DMA2 channel 2 interrupt                           */
-  .word	DMA2_Channel3_IRQHandler             			/* DMA2 channel 3 interrupt                           */
-  .word	DMA2_Channel4_IRQHandler             			/* DMA2 channel 4 interrupt                           */
-  .word	DMA2_Channel5_IRQHandler             			/* DMA2 channel 5 interrupt                           */
-  .word	DMA2_Channel6_IRQHandler             			/* DMA2 channel 6 interrupt                           */
-  .word	DMA2_Channel7_IRQHandler             			/* DMA2 channel 7 interrupt                           */
-  .word	DMAMUX1_OVR_IRQHandler               			/* DMAMUX overrun interrupt                           */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-	.weak	NMI_Handler
-	.thumb_set NMI_Handler,Default_Handler
-
-	.weak	HardFault_Handler
-	.thumb_set HardFault_Handler,Default_Handler
-
-	.weak	MemManage_Handler
-	.thumb_set MemManage_Handler,Default_Handler
-
-	.weak	BusFault_Handler
-	.thumb_set BusFault_Handler,Default_Handler
-
-	.weak	UsageFault_Handler
-	.thumb_set UsageFault_Handler,Default_Handler
-
-	.weak	SVC_Handler
-	.thumb_set SVC_Handler,Default_Handler
-
-	.weak	DebugMon_Handler
-	.thumb_set DebugMon_Handler,Default_Handler
-
-	.weak	PendSV_Handler
-	.thumb_set PendSV_Handler,Default_Handler
-
-	.weak	SysTick_Handler
-	.thumb_set SysTick_Handler,Default_Handler
-
-	.weak	WWDG_IRQHandler
-	.thumb_set WWDG_IRQHandler,Default_Handler
-
-	.weak	PVD_PVM_IRQHandler
-	.thumb_set PVD_PVM_IRQHandler,Default_Handler
-
-	.weak	TAMP_STAMP_LSECSS_SSRU_IRQHandler
-	.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
-
-	.weak	RTC_WKUP_IRQHandler
-	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-	.weak	FLASH_IRQHandler
-	.thumb_set FLASH_IRQHandler,Default_Handler
-
-	.weak	RCC_IRQHandler
-	.thumb_set RCC_IRQHandler,Default_Handler
-
-	.weak	EXTI0_IRQHandler
-	.thumb_set EXTI0_IRQHandler,Default_Handler
-
-	.weak	EXTI1_IRQHandler
-	.thumb_set EXTI1_IRQHandler,Default_Handler
-
-	.weak	EXTI2_IRQHandler
-	.thumb_set EXTI2_IRQHandler,Default_Handler
-
-	.weak	EXTI3_IRQHandler
-	.thumb_set EXTI3_IRQHandler,Default_Handler
-
-	.weak	EXTI4_IRQHandler
-	.thumb_set EXTI4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel1_IRQHandler
-	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel2_IRQHandler
-	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel3_IRQHandler
-	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel4_IRQHandler
-	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel5_IRQHandler
-	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel6_IRQHandler
-	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel7_IRQHandler
-	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-	.weak	ADC_IRQHandler
-	.thumb_set ADC_IRQHandler,Default_Handler
-
-	.weak	DAC_IRQHandler
-	.thumb_set DAC_IRQHandler,Default_Handler
-
-	.weak	C2SEV_PWR_C2H_IRQHandler
-	.thumb_set C2SEV_PWR_C2H_IRQHandler,Default_Handler
-
-	.weak	COMP_IRQHandler
-	.thumb_set COMP_IRQHandler,Default_Handler
-
-	.weak	EXTI9_5_IRQHandler
-	.thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-	.weak	TIM1_BRK_IRQHandler
-	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-	.weak	TIM1_UP_IRQHandler
-	.thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-	.weak	TIM1_TRG_COM_IRQHandler
-	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-	.weak	TIM1_CC_IRQHandler
-	.thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-	.weak	TIM2_IRQHandler
-	.thumb_set TIM2_IRQHandler,Default_Handler
-
-	.weak	TIM16_IRQHandler
-	.thumb_set TIM16_IRQHandler,Default_Handler
-
-	.weak	TIM17_IRQHandler
-	.thumb_set TIM17_IRQHandler,Default_Handler
-
-	.weak	I2C1_EV_IRQHandler
-	.thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-	.weak	I2C1_ER_IRQHandler
-	.thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-	.weak	I2C2_EV_IRQHandler
-	.thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-	.weak	I2C2_ER_IRQHandler
-	.thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-	.weak	SPI1_IRQHandler
-	.thumb_set SPI1_IRQHandler,Default_Handler
-
-	.weak	SPI2_IRQHandler
-	.thumb_set SPI2_IRQHandler,Default_Handler
-
-	.weak	USART1_IRQHandler
-	.thumb_set USART1_IRQHandler,Default_Handler
-
-	.weak	USART2_IRQHandler
-	.thumb_set USART2_IRQHandler,Default_Handler
-
-	.weak	LPUART1_IRQHandler
-	.thumb_set LPUART1_IRQHandler,Default_Handler
-
-	.weak	LPTIM1_IRQHandler
-	.thumb_set LPTIM1_IRQHandler,Default_Handler
-
-	.weak	LPTIM2_IRQHandler
-	.thumb_set LPTIM2_IRQHandler,Default_Handler
-
-	.weak	EXTI15_10_IRQHandler
-	.thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-	.weak	RTC_Alarm_IRQHandler
-	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-	.weak	LPTIM3_IRQHandler
-	.thumb_set LPTIM3_IRQHandler,Default_Handler
-
-	.weak	SUBGHZSPI_IRQHandler
-	.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
-
-	.weak	IPCC_C1_RX_IRQHandler
-	.thumb_set IPCC_C1_RX_IRQHandler,Default_Handler
-
-	.weak	IPCC_C1_TX_IRQHandler
-	.thumb_set IPCC_C1_TX_IRQHandler,Default_Handler
-
-	.weak	HSEM_IRQHandler
-	.thumb_set HSEM_IRQHandler,Default_Handler
-
-	.weak	I2C3_EV_IRQHandler
-	.thumb_set I2C3_EV_IRQHandler,Default_Handler
-
-	.weak	I2C3_ER_IRQHandler
-	.thumb_set I2C3_ER_IRQHandler,Default_Handler
-
-	.weak	SUBGHZ_Radio_IRQHandler
-	.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
-
-	.weak	AES_IRQHandler
-	.thumb_set AES_IRQHandler,Default_Handler
-
-	.weak	RNG_IRQHandler
-	.thumb_set RNG_IRQHandler,Default_Handler
-
-	.weak	PKA_IRQHandler
-	.thumb_set PKA_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel1_IRQHandler
-	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel2_IRQHandler
-	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel3_IRQHandler
-	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel4_IRQHandler
-	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel5_IRQHandler
-	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel6_IRQHandler
-	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel7_IRQHandler
-	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
-
-	.weak	DMAMUX1_OVR_IRQHandler
-	.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-
-	.weak	SystemInit
-
-/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wle4xx.s

@@ -1,426 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32wle4xx.s
-  * @author    MCD Application Team
-  * @brief     STM32WLE4xx devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address,
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M4 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2020(-2021) STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-.syntax unified
-.cpu cortex-m4
-.fpu softvfp
-.thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Call the clock system initialization function.*/
-  bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-  bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-
-LoopForever:
-    b LoopForever
-
-  .size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-  .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-
-/******************************************************************************
-*
-* The STM32WLE4xx vector table.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word	MemManage_Handler
-  .word	BusFault_Handler
-  .word	UsageFault_Handler
-  .word	0
-  .word	0
-  .word	0
-  .word	0
-  .word	SVC_Handler
-  .word	DebugMon_Handler
-  .word	0
-  .word	PendSV_Handler
-  .word	SysTick_Handler
-  .word	WWDG_IRQHandler                      			/* Window Watchdog interrupt                          */
-  .word	PVD_PVM_IRQHandler                   			/* PVD and PVM interrupt through EXTI                 */
-  .word	TAMP_STAMP_LSECSS_SSRU_IRQHandler    			/* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
-  .word	RTC_WKUP_IRQHandler                  			/* RTC wakeup interrupt through EXTI[19]              */
-  .word	FLASH_IRQHandler                     			/* Flash memory global interrupt and Flash memory ECC */
-  .word	RCC_IRQHandler                       			/* RCC global interrupt                               */
-  .word	EXTI0_IRQHandler                     			/* EXTI line 0 interrupt                              */
-  .word	EXTI1_IRQHandler                     			/* EXTI line 1 interrupt                              */
-  .word	EXTI2_IRQHandler                     			/* EXTI line 2 interrupt                              */
-  .word	EXTI3_IRQHandler                     			/* EXTI line 3 interrupt                              */
-  .word	EXTI4_IRQHandler                     			/* EXTI line 4 interrupt                              */
-  .word	DMA1_Channel1_IRQHandler             			/* DMA1 channel 1 interrupt                           */
-  .word	DMA1_Channel2_IRQHandler             			/* DMA1 channel 2 interrupt                           */
-  .word	DMA1_Channel3_IRQHandler             			/* DMA1 channel 3 interrupt                           */
-  .word	DMA1_Channel4_IRQHandler             			/* DMA1 channel 4 interrupt                           */
-  .word	DMA1_Channel5_IRQHandler             			/* DMA1 channel 5 interrupt                           */
-  .word	DMA1_Channel6_IRQHandler             			/* DMA1 channel 6 interrupt                           */
-  .word	DMA1_Channel7_IRQHandler             			/* DMA1 channel 7 interrupt                           */
-  .word	ADC_IRQHandler                       			/* ADC interrupt                                      */
-  .word	DAC_IRQHandler                       			/* DAC interrupt                                      */
-  .word	0                                    			/* Reserved                                           */
-  .word	COMP_IRQHandler                      			/* COMP1 and COMP2 interrupt through EXTI             */
-  .word	EXTI9_5_IRQHandler                   			/* EXTI line 9_5 interrupt                            */
-  .word	TIM1_BRK_IRQHandler                  			/* Timer 1 break interrupt                            */
-  .word	TIM1_UP_IRQHandler                   			/* Timer 1 Update                                     */
-  .word	TIM1_TRG_COM_IRQHandler              			/* Timer 1 trigger and communication                  */
-  .word	TIM1_CC_IRQHandler                   			/* Timer 1 capture compare interrupt                  */
-  .word	TIM2_IRQHandler                      			/* TIM2 global interrupt                              */
-  .word	TIM16_IRQHandler                     			/* Timer 16 global interrupt                          */
-  .word	TIM17_IRQHandler                     			/* Timer 17 global interrupt                          */
-  .word	I2C1_EV_IRQHandler                   			/* I2C1 event interrupt                               */
-  .word	I2C1_ER_IRQHandler                   			/* I2C1 event interrupt                               */
-  .word	I2C2_EV_IRQHandler                   			/* I2C2 error interrupt                               */
-  .word	I2C2_ER_IRQHandler                   			/* I2C2 error interrupt                               */
-  .word	SPI1_IRQHandler                      			/* SPI1 global interrupt                              */
-  .word	SPI2_IRQHandler                      			/* SPI2 global interrupt                              */
-  .word	USART1_IRQHandler                    			/* USART1 global interrupt                            */
-  .word	USART2_IRQHandler                    			/* USART2 global interrupt                            */
-  .word	LPUART1_IRQHandler                   			/* LPUART1 global interrupt                           */
-  .word	LPTIM1_IRQHandler                    			/* LPtimer 1 global interrupt                         */
-  .word	LPTIM2_IRQHandler                    			/* LPtimer 2 global interrupt                         */
-  .word	EXTI15_10_IRQHandler                 			/* EXTI line 15_10] interrupt through EXTI            */
-  .word	RTC_Alarm_IRQHandler                 			/* RTC Alarms A & B interrupt                         */
-  .word	LPTIM3_IRQHandler                    			/* LPtimer 3 global interrupt                         */
-  .word	SUBGHZSPI_IRQHandler                 			/* SUBGHZSPI global interrupt                         */
-  .word	0                                    			/* Reserved                                           */
-  .word	0                                    			/* Reserved                                           */
-  .word	HSEM_IRQHandler                      			/* Semaphore interrupt 0 to CPU1                      */
-  .word	I2C3_EV_IRQHandler                   			/* I2C3 event interrupt                               */
-  .word	I2C3_ER_IRQHandler                   			/* I2C3 error interrupt                               */
-  .word	SUBGHZ_Radio_IRQHandler              			/* Radio IRQs RFBUSY interrupt through EXTI           */
-  .word	AES_IRQHandler                       			/* AES global interrupt                               */
-  .word	RNG_IRQHandler                       			/* RNG interrupt                                      */
-  .word	PKA_IRQHandler                       			/* PKA interrupt                                      */
-  .word	DMA2_Channel1_IRQHandler             			/* DMA2 channel 1 interrupt                           */
-  .word	DMA2_Channel2_IRQHandler             			/* DMA2 channel 2 interrupt                           */
-  .word	DMA2_Channel3_IRQHandler             			/* DMA2 channel 3 interrupt                           */
-  .word	DMA2_Channel4_IRQHandler             			/* DMA2 channel 4 interrupt                           */
-  .word	DMA2_Channel5_IRQHandler             			/* DMA2 channel 5 interrupt                           */
-  .word	DMA2_Channel6_IRQHandler             			/* DMA2 channel 6 interrupt                           */
-  .word	DMA2_Channel7_IRQHandler             			/* DMA2 channel 7 interrupt                           */
-  .word	DMAMUX1_OVR_IRQHandler               			/* DMAMUX overrun interrupt                           */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-	.weak	NMI_Handler
-	.thumb_set NMI_Handler,Default_Handler
-
-	.weak	HardFault_Handler
-	.thumb_set HardFault_Handler,Default_Handler
-
-	.weak	MemManage_Handler
-	.thumb_set MemManage_Handler,Default_Handler
-
-	.weak	BusFault_Handler
-	.thumb_set BusFault_Handler,Default_Handler
-
-	.weak	UsageFault_Handler
-	.thumb_set UsageFault_Handler,Default_Handler
-
-	.weak	SVC_Handler
-	.thumb_set SVC_Handler,Default_Handler
-
-	.weak	DebugMon_Handler
-	.thumb_set DebugMon_Handler,Default_Handler
-
-	.weak	PendSV_Handler
-	.thumb_set PendSV_Handler,Default_Handler
-
-	.weak	SysTick_Handler
-	.thumb_set SysTick_Handler,Default_Handler
-
-	.weak	WWDG_IRQHandler
-	.thumb_set WWDG_IRQHandler,Default_Handler
-
-	.weak	PVD_PVM_IRQHandler
-	.thumb_set PVD_PVM_IRQHandler,Default_Handler
-
-	.weak	TAMP_STAMP_LSECSS_SSRU_IRQHandler
-	.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
-
-	.weak	RTC_WKUP_IRQHandler
-	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-	.weak	FLASH_IRQHandler
-	.thumb_set FLASH_IRQHandler,Default_Handler
-
-	.weak	RCC_IRQHandler
-	.thumb_set RCC_IRQHandler,Default_Handler
-
-	.weak	EXTI0_IRQHandler
-	.thumb_set EXTI0_IRQHandler,Default_Handler
-
-	.weak	EXTI1_IRQHandler
-	.thumb_set EXTI1_IRQHandler,Default_Handler
-
-	.weak	EXTI2_IRQHandler
-	.thumb_set EXTI2_IRQHandler,Default_Handler
-
-	.weak	EXTI3_IRQHandler
-	.thumb_set EXTI3_IRQHandler,Default_Handler
-
-	.weak	EXTI4_IRQHandler
-	.thumb_set EXTI4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel1_IRQHandler
-	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel2_IRQHandler
-	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel3_IRQHandler
-	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel4_IRQHandler
-	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel5_IRQHandler
-	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel6_IRQHandler
-	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel7_IRQHandler
-	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-	.weak	ADC_IRQHandler
-	.thumb_set ADC_IRQHandler,Default_Handler
-
-	.weak	DAC_IRQHandler
-	.thumb_set DAC_IRQHandler,Default_Handler
-
-	.weak	COMP_IRQHandler
-	.thumb_set COMP_IRQHandler,Default_Handler
-
-	.weak	EXTI9_5_IRQHandler
-	.thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-	.weak	TIM1_BRK_IRQHandler
-	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-	.weak	TIM1_UP_IRQHandler
-	.thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-	.weak	TIM1_TRG_COM_IRQHandler
-	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-	.weak	TIM1_CC_IRQHandler
-	.thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-	.weak	TIM2_IRQHandler
-	.thumb_set TIM2_IRQHandler,Default_Handler
-
-	.weak	TIM16_IRQHandler
-	.thumb_set TIM16_IRQHandler,Default_Handler
-
-	.weak	TIM17_IRQHandler
-	.thumb_set TIM17_IRQHandler,Default_Handler
-
-	.weak	I2C1_EV_IRQHandler
-	.thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-	.weak	I2C1_ER_IRQHandler
-	.thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-	.weak	I2C2_EV_IRQHandler
-	.thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-	.weak	I2C2_ER_IRQHandler
-	.thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-	.weak	SPI1_IRQHandler
-	.thumb_set SPI1_IRQHandler,Default_Handler
-
-	.weak	SPI2_IRQHandler
-	.thumb_set SPI2_IRQHandler,Default_Handler
-
-	.weak	USART1_IRQHandler
-	.thumb_set USART1_IRQHandler,Default_Handler
-
-	.weak	USART2_IRQHandler
-	.thumb_set USART2_IRQHandler,Default_Handler
-
-	.weak	LPUART1_IRQHandler
-	.thumb_set LPUART1_IRQHandler,Default_Handler
-
-	.weak	LPTIM1_IRQHandler
-	.thumb_set LPTIM1_IRQHandler,Default_Handler
-
-	.weak	LPTIM2_IRQHandler
-	.thumb_set LPTIM2_IRQHandler,Default_Handler
-
-	.weak	EXTI15_10_IRQHandler
-	.thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-	.weak	RTC_Alarm_IRQHandler
-	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-	.weak	LPTIM3_IRQHandler
-	.thumb_set LPTIM3_IRQHandler,Default_Handler
-
-	.weak	SUBGHZSPI_IRQHandler
-	.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
-
-	.weak	HSEM_IRQHandler
-	.thumb_set HSEM_IRQHandler,Default_Handler
-
-	.weak	I2C3_EV_IRQHandler
-	.thumb_set I2C3_EV_IRQHandler,Default_Handler
-
-	.weak	I2C3_ER_IRQHandler
-	.thumb_set I2C3_ER_IRQHandler,Default_Handler
-
-	.weak	SUBGHZ_Radio_IRQHandler
-	.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
-
-	.weak	AES_IRQHandler
-	.thumb_set AES_IRQHandler,Default_Handler
-
-	.weak	RNG_IRQHandler
-	.thumb_set RNG_IRQHandler,Default_Handler
-
-	.weak	PKA_IRQHandler
-	.thumb_set PKA_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel1_IRQHandler
-	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel2_IRQHandler
-	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel3_IRQHandler
-	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel4_IRQHandler
-	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel5_IRQHandler
-	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel6_IRQHandler
-	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel7_IRQHandler
-	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
-
-	.weak	DMAMUX1_OVR_IRQHandler
-	.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-
-	.weak	SystemInit
-
-/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/gcc/startup_stm32wle5xx.s

@@ -1,426 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32wle5xx.s
-  * @author    MCD Application Team
-  * @brief     STM32WLE5xx devices vector table for GCC toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address,
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M4 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2020(-2021) STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-.syntax unified
-.cpu cortex-m4
-.fpu softvfp
-.thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Call the clock system initialization function.*/
-  bl  SystemInit
-
-/* Copy the data segment initializers from flash to SRAM */
-  ldr r0, =_sdata
-  ldr r1, =_edata
-  ldr r2, =_sidata
-  movs r3, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r4, [r2, r3]
-  str r4, [r0, r3]
-  adds r3, r3, #4
-
-LoopCopyDataInit:
-  adds r4, r0, r3
-  cmp r4, r1
-  bcc CopyDataInit
-
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
-  ldr r4, =_ebss
-  movs r3, #0
-  b LoopFillZerobss
-
-FillZerobss:
-  str  r3, [r2]
-  adds r2, r2, #4
-
-LoopFillZerobss:
-  cmp r2, r4
-  bcc FillZerobss
-
-/* Call static constructors */
-  bl __libc_init_array
-/* Call the application's entry point.*/
-  bl entry
-
-LoopForever:
-    b LoopForever
-
-  .size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-  .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-
-/******************************************************************************
-*
-* The STM32WLE5xx vector table.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-  .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word	MemManage_Handler
-  .word	BusFault_Handler
-  .word	UsageFault_Handler
-  .word	0
-  .word	0
-  .word	0
-  .word	0
-  .word	SVC_Handler
-  .word	DebugMon_Handler
-  .word	0
-  .word	PendSV_Handler
-  .word	SysTick_Handler
-  .word	WWDG_IRQHandler                      			/* Window Watchdog interrupt                          */
-  .word	PVD_PVM_IRQHandler                   			/* PVD and PVM interrupt through EXTI                 */
-  .word	TAMP_STAMP_LSECSS_SSRU_IRQHandler    			/* RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU int.*/
-  .word	RTC_WKUP_IRQHandler                  			/* RTC wakeup interrupt through EXTI[19]              */
-  .word	FLASH_IRQHandler                     			/* Flash memory global interrupt and Flash memory ECC */
-  .word	RCC_IRQHandler                       			/* RCC global interrupt                               */
-  .word	EXTI0_IRQHandler                     			/* EXTI line 0 interrupt                              */
-  .word	EXTI1_IRQHandler                     			/* EXTI line 1 interrupt                              */
-  .word	EXTI2_IRQHandler                     			/* EXTI line 2 interrupt                              */
-  .word	EXTI3_IRQHandler                     			/* EXTI line 3 interrupt                              */
-  .word	EXTI4_IRQHandler                     			/* EXTI line 4 interrupt                              */
-  .word	DMA1_Channel1_IRQHandler             			/* DMA1 channel 1 interrupt                           */
-  .word	DMA1_Channel2_IRQHandler             			/* DMA1 channel 2 interrupt                           */
-  .word	DMA1_Channel3_IRQHandler             			/* DMA1 channel 3 interrupt                           */
-  .word	DMA1_Channel4_IRQHandler             			/* DMA1 channel 4 interrupt                           */
-  .word	DMA1_Channel5_IRQHandler             			/* DMA1 channel 5 interrupt                           */
-  .word	DMA1_Channel6_IRQHandler             			/* DMA1 channel 6 interrupt                           */
-  .word	DMA1_Channel7_IRQHandler             			/* DMA1 channel 7 interrupt                           */
-  .word	ADC_IRQHandler                       			/* ADC interrupt                                      */
-  .word	DAC_IRQHandler                       			/* DAC interrupt                                      */
-  .word	0                                    			/* Reserved                                           */
-  .word	COMP_IRQHandler                      			/* COMP1 and COMP2 interrupt through EXTI             */
-  .word	EXTI9_5_IRQHandler                   			/* EXTI line 9_5 interrupt                            */
-  .word	TIM1_BRK_IRQHandler                  			/* Timer 1 break interrupt                            */
-  .word	TIM1_UP_IRQHandler                   			/* Timer 1 Update                                     */
-  .word	TIM1_TRG_COM_IRQHandler              			/* Timer 1 trigger and communication                  */
-  .word	TIM1_CC_IRQHandler                   			/* Timer 1 capture compare interrupt                  */
-  .word	TIM2_IRQHandler                      			/* TIM2 global interrupt                              */
-  .word	TIM16_IRQHandler                     			/* Timer 16 global interrupt                          */
-  .word	TIM17_IRQHandler                     			/* Timer 17 global interrupt                          */
-  .word	I2C1_EV_IRQHandler                   			/* I2C1 event interrupt                               */
-  .word	I2C1_ER_IRQHandler                   			/* I2C1 event interrupt                               */
-  .word	I2C2_EV_IRQHandler                   			/* I2C2 error interrupt                               */
-  .word	I2C2_ER_IRQHandler                   			/* I2C2 error interrupt                               */
-  .word	SPI1_IRQHandler                      			/* SPI1 global interrupt                              */
-  .word	SPI2_IRQHandler                      			/* SPI2 global interrupt                              */
-  .word	USART1_IRQHandler                    			/* USART1 global interrupt                            */
-  .word	USART2_IRQHandler                    			/* USART2 global interrupt                            */
-  .word	LPUART1_IRQHandler                   			/* LPUART1 global interrupt                           */
-  .word	LPTIM1_IRQHandler                    			/* LPtimer 1 global interrupt                         */
-  .word	LPTIM2_IRQHandler                    			/* LPtimer 2 global interrupt                         */
-  .word	EXTI15_10_IRQHandler                 			/* EXTI line 15_10] interrupt through EXTI            */
-  .word	RTC_Alarm_IRQHandler                 			/* RTC Alarms A & B interrupt                         */
-  .word	LPTIM3_IRQHandler                    			/* LPtimer 3 global interrupt                         */
-  .word	SUBGHZSPI_IRQHandler                 			/* SUBGHZSPI global interrupt                         */
-  .word	0                                    			/* Reserved                                           */
-  .word	0                                    			/* Reserved                                           */
-  .word	HSEM_IRQHandler                      			/* Semaphore interrupt 0 to CPU1                      */
-  .word	I2C3_EV_IRQHandler                   			/* I2C3 event interrupt                               */
-  .word	I2C3_ER_IRQHandler                   			/* I2C3 error interrupt                               */
-  .word	SUBGHZ_Radio_IRQHandler              			/* Radio IRQs RFBUSY interrupt through EXTI           */
-  .word	AES_IRQHandler                       			/* AES global interrupt                               */
-  .word	RNG_IRQHandler                       			/* RNG interrupt                                      */
-  .word	PKA_IRQHandler                       			/* PKA interrupt                                      */
-  .word	DMA2_Channel1_IRQHandler             			/* DMA2 channel 1 interrupt                           */
-  .word	DMA2_Channel2_IRQHandler             			/* DMA2 channel 2 interrupt                           */
-  .word	DMA2_Channel3_IRQHandler             			/* DMA2 channel 3 interrupt                           */
-  .word	DMA2_Channel4_IRQHandler             			/* DMA2 channel 4 interrupt                           */
-  .word	DMA2_Channel5_IRQHandler             			/* DMA2 channel 5 interrupt                           */
-  .word	DMA2_Channel6_IRQHandler             			/* DMA2 channel 6 interrupt                           */
-  .word	DMA2_Channel7_IRQHandler             			/* DMA2 channel 7 interrupt                           */
-  .word	DMAMUX1_OVR_IRQHandler               			/* DMAMUX overrun interrupt                           */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-	.weak	NMI_Handler
-	.thumb_set NMI_Handler,Default_Handler
-
-	.weak	HardFault_Handler
-	.thumb_set HardFault_Handler,Default_Handler
-
-	.weak	MemManage_Handler
-	.thumb_set MemManage_Handler,Default_Handler
-
-	.weak	BusFault_Handler
-	.thumb_set BusFault_Handler,Default_Handler
-
-	.weak	UsageFault_Handler
-	.thumb_set UsageFault_Handler,Default_Handler
-
-	.weak	SVC_Handler
-	.thumb_set SVC_Handler,Default_Handler
-
-	.weak	DebugMon_Handler
-	.thumb_set DebugMon_Handler,Default_Handler
-
-	.weak	PendSV_Handler
-	.thumb_set PendSV_Handler,Default_Handler
-
-	.weak	SysTick_Handler
-	.thumb_set SysTick_Handler,Default_Handler
-
-	.weak	WWDG_IRQHandler
-	.thumb_set WWDG_IRQHandler,Default_Handler
-
-	.weak	PVD_PVM_IRQHandler
-	.thumb_set PVD_PVM_IRQHandler,Default_Handler
-
-	.weak	TAMP_STAMP_LSECSS_SSRU_IRQHandler
-	.thumb_set TAMP_STAMP_LSECSS_SSRU_IRQHandler,Default_Handler
-
-	.weak	RTC_WKUP_IRQHandler
-	.thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-	.weak	FLASH_IRQHandler
-	.thumb_set FLASH_IRQHandler,Default_Handler
-
-	.weak	RCC_IRQHandler
-	.thumb_set RCC_IRQHandler,Default_Handler
-
-	.weak	EXTI0_IRQHandler
-	.thumb_set EXTI0_IRQHandler,Default_Handler
-
-	.weak	EXTI1_IRQHandler
-	.thumb_set EXTI1_IRQHandler,Default_Handler
-
-	.weak	EXTI2_IRQHandler
-	.thumb_set EXTI2_IRQHandler,Default_Handler
-
-	.weak	EXTI3_IRQHandler
-	.thumb_set EXTI3_IRQHandler,Default_Handler
-
-	.weak	EXTI4_IRQHandler
-	.thumb_set EXTI4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel1_IRQHandler
-	.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel2_IRQHandler
-	.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel3_IRQHandler
-	.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel4_IRQHandler
-	.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel5_IRQHandler
-	.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel6_IRQHandler
-	.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-	.weak	DMA1_Channel7_IRQHandler
-	.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-	.weak	ADC_IRQHandler
-	.thumb_set ADC_IRQHandler,Default_Handler
-
-	.weak	DAC_IRQHandler
-	.thumb_set DAC_IRQHandler,Default_Handler
-
-	.weak	COMP_IRQHandler
-	.thumb_set COMP_IRQHandler,Default_Handler
-
-	.weak	EXTI9_5_IRQHandler
-	.thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-	.weak	TIM1_BRK_IRQHandler
-	.thumb_set TIM1_BRK_IRQHandler,Default_Handler
-
-	.weak	TIM1_UP_IRQHandler
-	.thumb_set TIM1_UP_IRQHandler,Default_Handler
-
-	.weak	TIM1_TRG_COM_IRQHandler
-	.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
-
-	.weak	TIM1_CC_IRQHandler
-	.thumb_set TIM1_CC_IRQHandler,Default_Handler
-
-	.weak	TIM2_IRQHandler
-	.thumb_set TIM2_IRQHandler,Default_Handler
-
-	.weak	TIM16_IRQHandler
-	.thumb_set TIM16_IRQHandler,Default_Handler
-
-	.weak	TIM17_IRQHandler
-	.thumb_set TIM17_IRQHandler,Default_Handler
-
-	.weak	I2C1_EV_IRQHandler
-	.thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-	.weak	I2C1_ER_IRQHandler
-	.thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-	.weak	I2C2_EV_IRQHandler
-	.thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-	.weak	I2C2_ER_IRQHandler
-	.thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-	.weak	SPI1_IRQHandler
-	.thumb_set SPI1_IRQHandler,Default_Handler
-
-	.weak	SPI2_IRQHandler
-	.thumb_set SPI2_IRQHandler,Default_Handler
-
-	.weak	USART1_IRQHandler
-	.thumb_set USART1_IRQHandler,Default_Handler
-
-	.weak	USART2_IRQHandler
-	.thumb_set USART2_IRQHandler,Default_Handler
-
-	.weak	LPUART1_IRQHandler
-	.thumb_set LPUART1_IRQHandler,Default_Handler
-
-	.weak	LPTIM1_IRQHandler
-	.thumb_set LPTIM1_IRQHandler,Default_Handler
-
-	.weak	LPTIM2_IRQHandler
-	.thumb_set LPTIM2_IRQHandler,Default_Handler
-
-	.weak	EXTI15_10_IRQHandler
-	.thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-	.weak	RTC_Alarm_IRQHandler
-	.thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-	.weak	LPTIM3_IRQHandler
-	.thumb_set LPTIM3_IRQHandler,Default_Handler
-
-	.weak	SUBGHZSPI_IRQHandler
-	.thumb_set SUBGHZSPI_IRQHandler,Default_Handler
-
-	.weak	HSEM_IRQHandler
-	.thumb_set HSEM_IRQHandler,Default_Handler
-
-	.weak	I2C3_EV_IRQHandler
-	.thumb_set I2C3_EV_IRQHandler,Default_Handler
-
-	.weak	I2C3_ER_IRQHandler
-	.thumb_set I2C3_ER_IRQHandler,Default_Handler
-
-	.weak	SUBGHZ_Radio_IRQHandler
-	.thumb_set SUBGHZ_Radio_IRQHandler,Default_Handler
-
-	.weak	AES_IRQHandler
-	.thumb_set AES_IRQHandler,Default_Handler
-
-	.weak	RNG_IRQHandler
-	.thumb_set RNG_IRQHandler,Default_Handler
-
-	.weak	PKA_IRQHandler
-	.thumb_set PKA_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel1_IRQHandler
-	.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel2_IRQHandler
-	.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel3_IRQHandler
-	.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel4_IRQHandler
-	.thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel5_IRQHandler
-	.thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel6_IRQHandler
-	.thumb_set DMA2_Channel6_IRQHandler,Default_Handler
-
-	.weak	DMA2_Channel7_IRQHandler
-	.thumb_set DMA2_Channel7_IRQHandler,Default_Handler
-
-	.weak	DMAMUX1_OVR_IRQHandler
-	.thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
-
-	.weak	SystemInit
-
-/************************ (C) COPYRIGHT STMicroelectonics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm0plus.icf

@@ -1,40 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08020000;
-
-/*-Memory Regions-*/
-/***** FLASH part dedicated to M0+ *****/
-define symbol __ICFEDIT_region_ROM_start__    = 0x08020000;
-define symbol __ICFEDIT_region_ROM_end__      = 0x0803FFFF;
-/***** Non-backup SRAM1 dedicated to M0+ *****/
-define symbol __ICFEDIT_region_RAM_start__    = 0x20004000;
-define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
-/***** Backup SRAM2 dedicated to M0+ *****/
-define symbol __ICFEDIT_region_RAM2_start__   = 0x2000C000;
-define symbol __ICFEDIT_region_RAM2_end__     = 0x2000FFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-define region RAM2_region     = mem:[from __ICFEDIT_region_RAM2_start__  to __ICFEDIT_region_RAM2_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
-place in RAM2_region  { };

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_flash_cm4.icf

@@ -1,40 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-
-/*-Memory Regions-*/
-/***** FLASH part dedicated to M4 *****/
-define symbol __ICFEDIT_region_ROM_start__    = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__      = 0x0801FFFF;
-/***** Non-backup SRAM1 dedicated to M4 *****/
-define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
-/***** Backup SRAM2 dedicated to M4 *****/
-define symbol __ICFEDIT_region_RAM2_start__   = 0x20008000;
-define symbol __ICFEDIT_region_RAM2_end__     = 0x2000BFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-define region RAM2_region     = mem:[from __ICFEDIT_region_RAM2_start__  to __ICFEDIT_region_RAM2_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
-place in RAM2_region  { };

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_sram_cm0plus.icf

@@ -1,35 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x2000C000;
-
-/*-Memory Regions-*/
-/***** Non-backup SRAM1 dedicated to M0+ code *****/
-define symbol __ICFEDIT_region_ROM_start__ = 0x2000C000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x2000FFFF;
-/***** Backup SRAM2 dedicated to M0+ data *****/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20004000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl54xx_sram_cm4.icf

@@ -1,34 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20008000;
-/*-Memory Regions-*/
-/***** Non-backup SRAM1 dedicated to M4 code *****/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20008000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x2000BFFF;
-/***** Backup SRAM2 dedicated to M4 data *****/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm0plus.icf

@@ -1,40 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08020000;
-
-/*-Memory Regions-*/
-/***** FLASH part dedicated to M0+ *****/
-define symbol __ICFEDIT_region_ROM_start__    = 0x08020000;
-define symbol __ICFEDIT_region_ROM_end__      = 0x0803FFFF;
-/***** SRAM1 dedicated to M0+ *****/
-define symbol __ICFEDIT_region_RAM_start__    = 0x20004000;
-define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
-/***** SRAM2 dedicated to M0+ *****/
-define symbol __ICFEDIT_region_RAM2_start__   = 0x2000C000;
-define symbol __ICFEDIT_region_RAM2_end__     = 0x2000FFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-define region RAM2_region     = mem:[from __ICFEDIT_region_RAM2_start__  to __ICFEDIT_region_RAM2_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
-place in RAM2_region  { };

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_flash_cm4.icf

@@ -1,40 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-
-/*-Memory Regions-*/
-/***** FLASH part dedicated to M4 *****/
-define symbol __ICFEDIT_region_ROM_start__    = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__      = 0x0801FFFF;
-/***** Non-backup SRAM1 dedicated to M4 *****/
-define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__      = 0x20003FFF;
-/***** Backup SRAM2 dedicated to M4 *****/
-define symbol __ICFEDIT_region_RAM2_start__   = 0x20008000;
-define symbol __ICFEDIT_region_RAM2_end__     = 0x2000BFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-define region RAM2_region     = mem:[from __ICFEDIT_region_RAM2_start__  to __ICFEDIT_region_RAM2_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
-place in RAM2_region  { };

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm0plus.icf

@@ -1,35 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x2000C000;
-
-/*-Memory Regions-*/
-/***** Non-backup SRAM1 dedicated to M0+ code *****/
-define symbol __ICFEDIT_region_ROM_start__ = 0x2000C000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x2000FFFF;
-/***** Backup SRAM2 dedicated to M0+ data *****/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20004000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wl55xx_sram_cm4.icf

@@ -1,35 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20008000;
-
-/*-Memory Regions-*/
-/***** Non-backup SRAM1 dedicated to M4 code *****/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20008000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x2000BFFF;
-/***** Backup SRAM2 dedicated to M4 data *****/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_flash.icf

@@ -1,40 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-
-/*-Memory Regions-*/
-/***** FLASH *****/
-define symbol __ICFEDIT_region_ROM_start__    = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__      = 0x0803FFFF;
-/***** Non-backup SRAM1 *****/
-define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
-/***** Backup SRAM2 *****/
-define symbol __ICFEDIT_region_RAM2_start__   = 0x20008000;
-define symbol __ICFEDIT_region_RAM2_end__     = 0x2000FFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-define region RAM2_region     = mem:[from __ICFEDIT_region_RAM2_start__  to __ICFEDIT_region_RAM2_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
-place in RAM2_region  { };

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle4xx_sram.icf

@@ -1,35 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-
-/*-Memory Regions-*/
-/***** Non-backup SRAM1 dedicated to code *****/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x20007FFF;
-/***** Backup SRAM2 dedicated to data *****/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20008000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2000FFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_flash.icf

@@ -1,40 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x08000000;
-
-/*-Memory Regions-*/
-/***** FLASH *****/
-define symbol __ICFEDIT_region_ROM_start__    = 0x08000000;
-define symbol __ICFEDIT_region_ROM_end__      = 0x0803FFFF;
-/***** Non-backup SRAM1 *****/
-define symbol __ICFEDIT_region_RAM_start__    = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__      = 0x20007FFF;
-/***** Backup SRAM2 *****/
-define symbol __ICFEDIT_region_RAM2_start__   = 0x20008000;
-define symbol __ICFEDIT_region_RAM2_end__     = 0x2000FFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-define region RAM2_region     = mem:[from __ICFEDIT_region_RAM2_start__  to __ICFEDIT_region_RAM2_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };
-place in RAM2_region  { };

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/linker/stm32wle5xx_sram.icf

@@ -1,35 +0,0 @@
-/*###ICF### Section handled by ICF editor, don't touch! ****/
-/*-Editor annotation file-*/
-/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
-/*-Specials-*/
-define symbol __ICFEDIT_intvec_start__ = 0x20000000;
-
-/*-Memory Regions-*/
-/***** Non-backup SRAM1 dedicated to code *****/
-define symbol __ICFEDIT_region_ROM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_ROM_end__   = 0x20007FFF;
-/***** Backup SRAM2 dedicated to data *****/
-define symbol __ICFEDIT_region_RAM_start__ = 0x20008000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2000FFFF;
-
-/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x400;
-define symbol __ICFEDIT_size_heap__ = 0x000;
-/**** End of ICF editor section. ###ICF###*/
-
-
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
-define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
-
-define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
-define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
-
-initialize by copy { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite,
-                        block CSTACK, block HEAP };

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wl54xx_cm0plus.s

@@ -1,316 +0,0 @@
-;********************************************************************************
-;* File Name          : startup_stm32wl54xx_cm0plus.s
-;* Author             : MCD Application Team
-;* Description        : MO+ core vector table of the STM32WLxxxx devices for the
-;*                      IAR (EWARM) toolchain.
-;*
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR
-;*                        address.
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2020(2021) STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler                     ; Reset Handler
-
-        DCD     NMI_Handler                       ; NMI Handler
-        DCD     HardFault_Handler                 ; Hard Fault Handler
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     SVC_Handler                       ; SVCall Handler
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     PendSV_Handler                    ; PendSV Handler
-        DCD     SysTick_Handler                   ; SysTick Handler
-
-        ; External Interrupts
-        DCD     TZIC_ILA_IRQHandler               ; TZIC ILA Interrupt
-        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
-        DCD     RTC_LSECSS_IRQHandler             ; RTC Wakeup, Tamper, TimeStamp, RTC Alarms (A & B) and RTC SSRU Interrupts and LSECSS Interrupts
-        DCD     RCC_FLASH_C1SEV_IRQHandler        ; RCC and FLASH and CPU1 M4 SEV Interrupt
-        DCD     EXTI1_0_IRQHandler                ; EXTI Line 1:0 Interrupt
-        DCD     EXTI3_2_IRQHandler                ; EXTI Line 3:2 Interrupt
-        DCD     EXTI15_4_IRQHandler               ; EXTI Line 15:4 interrupt
-        DCD     ADC_COMP_DAC_IRQHandler           ; ADC, COMP1, COMP2, DAC Interrupt
-        DCD     DMA1_Channel1_2_3_IRQHandler      ; DMA1 Channel 1 to 3 Interrupt
-        DCD     DMA1_Channel4_5_6_7_IRQHandler    ; DMA1 Channels 4,5,6,7 Interrupt 
-        DCD     DMA2_DMAMUX1_OVR_IRQHandler       ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts          
-
-        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Global Interrupt
-        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Global Interrupt
-        DCD     LPTIM3_IRQHandler                 ; LPTIM3 Global Interrupt
-
-        DCD     TIM1_IRQHandler                   ; TIM1 Global Interrupt
-        DCD     TIM2_IRQHandler                     ; TIM2 Global Interrupt
-        DCD     TIM16_IRQHandler                    ; TIM16 Global Interrupt
-        DCD     TIM17_IRQHandler                    ; TIM17 Global Interrupt
-        DCD     IPCC_C2_RX_C2_TX_IRQHandler         ; IPCC RX Occupied and TX Free Interrupt Interrupt
-        DCD     HSEM_IRQHandler                     ; Semaphore Interrupt
-        DCD     RNG_IRQHandler                      ; RNG Interrupt
-        DCD     AES_PKA_IRQHandler                  ; AES and PKA Interrupt
-        DCD     I2C1_IRQHandler                     ; I2C1 Event and Error Interrupt
-        DCD     I2C2_IRQHandler                     ; I2C2 Event and Error Interrupt
-        DCD     I2C3_IRQHandler                     ; I2C3 Event and Error Interrupt
-        DCD     SPI1_IRQHandler                     ; SPI1 Interrupt
-        DCD     SPI2_IRQHandler                     ; SPI2 Interrupt
-        DCD     USART1_IRQHandler                   ; USART1 Interrupt
-        DCD     USART2_IRQHandler                   ; USART2 Interrupt
-        DCD     LPUART1_IRQHandler                  ; LPUART1 Interrupt
-        DCD     SUBGHZSPI_IRQHandler                ; SUBGHZSPI Interrupt
-        DCD     SUBGHZ_Radio_IRQHandler             ; SUBGHZ Radio Interrupt
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK TZIC_ILA_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TZIC_ILA_IRQHandler
-        B TZIC_ILA_IRQHandler
-
-        PUBWEAK PVD_PVM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_PVM_IRQHandler
-        B PVD_PVM_IRQHandler
-
-        PUBWEAK RTC_LSECSS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_LSECSS_IRQHandler
-        B RTC_LSECSS_IRQHandler
-
-        PUBWEAK RCC_FLASH_C1SEV_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_FLASH_C1SEV_IRQHandler
-        B RCC_FLASH_C1SEV_IRQHandler
-
-        PUBWEAK EXTI1_0_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_0_IRQHandler
-        B EXTI1_0_IRQHandler
-
-        PUBWEAK EXTI3_2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_2_IRQHandler
-        B EXTI3_2_IRQHandler
-
-        PUBWEAK EXTI15_4_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_4_IRQHandler
-        B EXTI15_4_IRQHandler
-
-        PUBWEAK ADC_COMP_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC_COMP_DAC_IRQHandler
-        B ADC_COMP_DAC_IRQHandler
-
-        PUBWEAK DMA1_Channel1_2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_2_3_IRQHandler
-        B DMA1_Channel1_2_3_IRQHandler
-
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-
-        PUBWEAK DMA2_DMAMUX1_OVR_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_DMAMUX1_OVR_IRQHandler
-        B DMA2_DMAMUX1_OVR_IRQHandler
-
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-
-        PUBWEAK LPTIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM2_IRQHandler
-        B LPTIM2_IRQHandler
-
-        PUBWEAK LPTIM3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM3_IRQHandler
-        B LPTIM3_IRQHandler
-
-        PUBWEAK TIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_IRQHandler
-        B TIM1_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM16_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
-        B TIM16_IRQHandler
-
-        PUBWEAK TIM17_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
-        B TIM17_IRQHandler
-
-        PUBWEAK IPCC_C2_RX_C2_TX_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-IPCC_C2_RX_C2_TX_IRQHandler
-        B IPCC_C2_RX_C2_TX_IRQHandler
-
-        PUBWEAK HSEM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HSEM_IRQHandler
-        B HSEM_IRQHandler
-
-        PUBWEAK RNG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_IRQHandler
-        B RNG_IRQHandler
-
-        PUBWEAK AES_PKA_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-AES_PKA_IRQHandler
-        B AES_PKA_IRQHandler
-
-        PUBWEAK LCD_802_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LCD_802_1_IRQHandler
-        B LCD_802_1_IRQHandler
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-
-        PUBWEAK I2C3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_IRQHandler
-        B I2C3_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-
-        PUBWEAK SUBGHZSPI_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SUBGHZSPI_IRQHandler
-        B SUBGHZSPI_IRQHandler
-
-        PUBWEAK SUBGHZ_Radio_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SUBGHZ_Radio_IRQHandler
-        B SUBGHZ_Radio_IRQHandler
-
-        END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wl54xx_cm4.s

@@ -1,509 +0,0 @@
-;********************************************************************************
-;* File Name          : startup_stm32wl54xx_cm4.s
-;* Author             : MCD Application Team
-;* Description        : M4 core vector table of the STM32WLxxxx devices for the
-;*                      IAR (EWARM) toolchain.
-;*
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR
-;*                        address.
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2020(2021) STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler                     ; Reset Handler
-
-        DCD     NMI_Handler                       ; NMI Handler
-        DCD     HardFault_Handler                 ; Hard Fault Handler
-        DCD     MemManage_Handler                 ; MPU Fault Handler
-        DCD     BusFault_Handler                  ; Bus Fault Handler
-        DCD     UsageFault_Handler                ; Usage Fault Handler
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     SVC_Handler                       ; SVCall Handler
-        DCD     DebugMon_Handler                  ; Debug Monitor Handler
-        DCD     0                                 ; Reserved
-        DCD     PendSV_Handler                    ; PendSV Handler
-        DCD     SysTick_Handler                   ; SysTick Handler
-
-        ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
-        DCD     TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
-        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
-        DCD     RCC_IRQHandler                    ; RCC Interrupt
-        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
-        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
-        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
-        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrupt
-        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
-        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
-        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
-        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
-        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
-        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
-        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
-        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
-        DCD     ADC_IRQHandler                    ; ADC Interrupt
-        DCD     DAC_IRQHandler                    ; DAC Interrupt
-        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
-        DCD     COMP_IRQHandler                   ; COMP1 and COMP2 Interrupts
-        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
-        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
-        DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupt
-        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Communication Interrupts
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
-        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
-        DCD     TIM16_IRQHandler                  ; TIM16 Global Interrupt
-        DCD     TIM17_IRQHandler                  ; TIM17 Global Interrupt
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event Interrupt
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error Interrupt
-        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
-        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
-        DCD     USART1_IRQHandler                 ; USART1 Interrupt
-        DCD     USART2_IRQHandler                 ; USART2 Interrupt
-        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
-        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Global Interrupt
-        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Global Interrupt
-        DCD     EXTI15_10_IRQHandler              ; EXTI Lines [15:10] Interrupt
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
-        DCD     LPTIM3_IRQHandler                 ; LPTIM3 Global Interrupt
-        DCD     SUBGHZSPI_IRQHandler              ; SUBGHZSPI Interrupt
-        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
-        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
-        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
-        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
-        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
-        DCD     SUBGHZ_Radio_IRQHandler           ; SUBGHZ Radio Interrupt
-        DCD     AES_IRQHandler                    ; AES Interrupt
-        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
-        DCD     PKA_IRQHandler                    ; PKA Interrupt
-        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
-        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
-        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
-        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
-        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
-        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
-        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
-        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_PVM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_PVM_IRQHandler
-        B PVD_PVM_IRQHandler
-
-        PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TAMP_STAMP_LSECSS_SSRU_IRQHandler
-        B TAMP_STAMP_LSECSS_SSRU_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC_IRQHandler
-        B ADC_IRQHandler
-
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-
-        PUBWEAK C2SEV_PWR_C2H_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-C2SEV_PWR_C2H_IRQHandler
-        B C2SEV_PWR_C2H_IRQHandler
-
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_IRQHandler
-        B TIM1_BRK_IRQHandler
-
-        PUBWEAK TIM1_UP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_UP_IRQHandler
-        B TIM1_UP_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_TRG_COM_IRQHandler
-        B TIM1_TRG_COM_IRQHandler
-
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM16_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
-        B TIM16_IRQHandler
-
-        PUBWEAK TIM17_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
-        B TIM17_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-
-        PUBWEAK LPTIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM2_IRQHandler
-        B LPTIM2_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK LPTIM3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM3_IRQHandler
-        B LPTIM3_IRQHandler
-
-        PUBWEAK SUBGHZSPI_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SUBGHZSPI_IRQHandler
-        B SUBGHZSPI_IRQHandler
-
-        PUBWEAK IPCC_C1_RX_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-IPCC_C1_RX_IRQHandler
-        B IPCC_C1_RX_IRQHandler
-
-        PUBWEAK IPCC_C1_TX_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-IPCC_C1_TX_IRQHandler
-        B IPCC_C1_TX_IRQHandler
-
-        PUBWEAK HSEM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HSEM_IRQHandler
-        B HSEM_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_EV_IRQHandler
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_ER_IRQHandler
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK SUBGHZ_Radio_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SUBGHZ_Radio_IRQHandler
-        B SUBGHZ_Radio_IRQHandler
-
-        PUBWEAK AES_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-AES_IRQHandler
-        B AES_IRQHandler
-
-        PUBWEAK RNG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_IRQHandler
-        B RNG_IRQHandler
-
-        PUBWEAK PKA_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PKA_IRQHandler
-        B PKA_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-        PUBWEAK DMA2_Channel6_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel6_IRQHandler
-        B DMA2_Channel6_IRQHandler
-
-        PUBWEAK DMA2_Channel7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel7_IRQHandler
-        B DMA2_Channel7_IRQHandler
-
-        PUBWEAK DMAMUX1_OVR_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMAMUX1_OVR_IRQHandler
-        B DMAMUX1_OVR_IRQHandler
-
-        END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wl55xx_cm0plus.s

@@ -1,316 +0,0 @@
-;********************************************************************************
-;* File Name          : startup_stm32wl55xx_cm0plus.s
-;* Author             : MCD Application Team
-;* Description        : MO+ core vector table of the STM32WLxxxx devices for the
-;*                      IAR (EWARM) toolchain.
-;*
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR
-;*                        address.
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2020(2021) STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler                     ; Reset Handler
-
-        DCD     NMI_Handler                       ; NMI Handler
-        DCD     HardFault_Handler                 ; Hard Fault Handler
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     SVC_Handler                       ; SVCall Handler
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     PendSV_Handler                    ; PendSV Handler
-        DCD     SysTick_Handler                   ; SysTick Handler
-
-        ; External Interrupts
-        DCD     TZIC_ILA_IRQHandler               ; TZIC ILA Interrupt
-        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
-        DCD     RTC_LSECSS_IRQHandler             ; RTC Wakeup, Tamper, TimeStamp, RTC Alarms (A & B) and RTC SSRU Interrupts and LSECSS Interrupts
-        DCD     RCC_FLASH_C1SEV_IRQHandler        ; RCC and FLASH and CPU1 M4 SEV Interrupt
-        DCD     EXTI1_0_IRQHandler                ; EXTI Line 1:0 Interrupt
-        DCD     EXTI3_2_IRQHandler                ; EXTI Line 3:2 Interrupt
-        DCD     EXTI15_4_IRQHandler               ; EXTI Line 15:4 interrupt
-        DCD     ADC_COMP_DAC_IRQHandler           ; ADC, COMP1, COMP2, DAC Interrupt
-        DCD     DMA1_Channel1_2_3_IRQHandler      ; DMA1 Channel 1 to 3 Interrupt
-        DCD     DMA1_Channel4_5_6_7_IRQHandler    ; DMA1 Channels 4,5,6,7 Interrupt 
-        DCD     DMA2_DMAMUX1_OVR_IRQHandler       ; DMA2 Channels[1..7] and DMAMUX Overrun Interrupts          
-
-        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Global Interrupt
-        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Global Interrupt
-        DCD     LPTIM3_IRQHandler                 ; LPTIM3 Global Interrupt
-
-        DCD     TIM1_IRQHandler                   ; TIM1 Global Interrupt
-        DCD     TIM2_IRQHandler                     ; TIM2 Global Interrupt
-        DCD     TIM16_IRQHandler                    ; TIM16 Global Interrupt
-        DCD     TIM17_IRQHandler                    ; TIM17 Global Interrupt
-        DCD     IPCC_C2_RX_C2_TX_IRQHandler         ; IPCC RX Occupied and TX Free Interrupt Interrupt
-        DCD     HSEM_IRQHandler                     ; Semaphore Interrupt
-        DCD     RNG_IRQHandler                      ; RNG Interrupt
-        DCD     AES_PKA_IRQHandler                  ; AES and PKA Interrupt
-        DCD     I2C1_IRQHandler                     ; I2C1 Event and Error Interrupt
-        DCD     I2C2_IRQHandler                     ; I2C2 Event and Error Interrupt
-        DCD     I2C3_IRQHandler                     ; I2C3 Event and Error Interrupt
-        DCD     SPI1_IRQHandler                     ; SPI1 Interrupt
-        DCD     SPI2_IRQHandler                     ; SPI2 Interrupt
-        DCD     USART1_IRQHandler                   ; USART1 Interrupt
-        DCD     USART2_IRQHandler                   ; USART2 Interrupt
-        DCD     LPUART1_IRQHandler                  ; LPUART1 Interrupt
-        DCD     SUBGHZSPI_IRQHandler                ; SUBGHZSPI Interrupt
-        DCD     SUBGHZ_Radio_IRQHandler             ; SUBGHZ Radio Interrupt
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK TZIC_ILA_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TZIC_ILA_IRQHandler
-        B TZIC_ILA_IRQHandler
-
-        PUBWEAK PVD_PVM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_PVM_IRQHandler
-        B PVD_PVM_IRQHandler
-
-        PUBWEAK RTC_LSECSS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_LSECSS_IRQHandler
-        B RTC_LSECSS_IRQHandler
-
-        PUBWEAK RCC_FLASH_C1SEV_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_FLASH_C1SEV_IRQHandler
-        B RCC_FLASH_C1SEV_IRQHandler
-
-        PUBWEAK EXTI1_0_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_0_IRQHandler
-        B EXTI1_0_IRQHandler
-
-        PUBWEAK EXTI3_2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_2_IRQHandler
-        B EXTI3_2_IRQHandler
-
-        PUBWEAK EXTI15_4_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_4_IRQHandler
-        B EXTI15_4_IRQHandler
-
-        PUBWEAK ADC_COMP_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC_COMP_DAC_IRQHandler
-        B ADC_COMP_DAC_IRQHandler
-
-        PUBWEAK DMA1_Channel1_2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_2_3_IRQHandler
-        B DMA1_Channel1_2_3_IRQHandler
-
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-
-        PUBWEAK DMA2_DMAMUX1_OVR_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_DMAMUX1_OVR_IRQHandler
-        B DMA2_DMAMUX1_OVR_IRQHandler
-
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-
-        PUBWEAK LPTIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM2_IRQHandler
-        B LPTIM2_IRQHandler
-
-        PUBWEAK LPTIM3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM3_IRQHandler
-        B LPTIM3_IRQHandler
-
-        PUBWEAK TIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_IRQHandler
-        B TIM1_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM16_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
-        B TIM16_IRQHandler
-
-        PUBWEAK TIM17_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
-        B TIM17_IRQHandler
-
-        PUBWEAK IPCC_C2_RX_C2_TX_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-IPCC_C2_RX_C2_TX_IRQHandler
-        B IPCC_C2_RX_C2_TX_IRQHandler
-
-        PUBWEAK HSEM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HSEM_IRQHandler
-        B HSEM_IRQHandler
-
-        PUBWEAK RNG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_IRQHandler
-        B RNG_IRQHandler
-
-        PUBWEAK AES_PKA_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-AES_PKA_IRQHandler
-        B AES_PKA_IRQHandler
-
-        PUBWEAK LCD_802_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LCD_802_1_IRQHandler
-        B LCD_802_1_IRQHandler
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-
-        PUBWEAK I2C3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_IRQHandler
-        B I2C3_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-
-        PUBWEAK SUBGHZSPI_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SUBGHZSPI_IRQHandler
-        B SUBGHZSPI_IRQHandler
-
-        PUBWEAK SUBGHZ_Radio_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SUBGHZ_Radio_IRQHandler
-        B SUBGHZ_Radio_IRQHandler
-
-        END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wl55xx_cm4.s

@@ -1,509 +0,0 @@
-;********************************************************************************
-;* File Name          : startup_stm32wl55xx_cm4.s
-;* Author             : MCD Application Team
-;* Description        : M4 core vector table of the STM32WLxxxx devices for the
-;*                      IAR (EWARM) toolchain.
-;*
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR
-;*                        address.
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2020(2021) STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler                     ; Reset Handler
-
-        DCD     NMI_Handler                       ; NMI Handler
-        DCD     HardFault_Handler                 ; Hard Fault Handler
-        DCD     MemManage_Handler                 ; MPU Fault Handler
-        DCD     BusFault_Handler                  ; Bus Fault Handler
-        DCD     UsageFault_Handler                ; Usage Fault Handler
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     SVC_Handler                       ; SVCall Handler
-        DCD     DebugMon_Handler                  ; Debug Monitor Handler
-        DCD     0                                 ; Reserved
-        DCD     PendSV_Handler                    ; PendSV Handler
-        DCD     SysTick_Handler                   ; SysTick Handler
-
-        ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
-        DCD     TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
-        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
-        DCD     RCC_IRQHandler                    ; RCC Interrupt
-        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
-        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
-        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
-        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrupt
-        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
-        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
-        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
-        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
-        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
-        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
-        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
-        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
-        DCD     ADC_IRQHandler                    ; ADC Interrupt
-        DCD     DAC_IRQHandler                    ; DAC Interrupt
-        DCD     C2SEV_PWR_C2H_IRQHandler          ; CPU M0+ SEV Interrupt
-        DCD     COMP_IRQHandler                   ; COMP1 and COMP2 Interrupts
-        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
-        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
-        DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupt
-        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Communication Interrupts
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
-        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
-        DCD     TIM16_IRQHandler                  ; TIM16 Global Interrupt
-        DCD     TIM17_IRQHandler                  ; TIM17 Global Interrupt
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event Interrupt
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error Interrupt
-        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
-        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
-        DCD     USART1_IRQHandler                 ; USART1 Interrupt
-        DCD     USART2_IRQHandler                 ; USART2 Interrupt
-        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
-        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Global Interrupt
-        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Global Interrupt
-        DCD     EXTI15_10_IRQHandler              ; EXTI Lines [15:10] Interrupt
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
-        DCD     LPTIM3_IRQHandler                 ; LPTIM3 Global Interrupt
-        DCD     SUBGHZSPI_IRQHandler              ; SUBGHZSPI Interrupt
-        DCD     IPCC_C1_RX_IRQHandler             ; IPCC CPU1 RX occupied interrupt
-        DCD     IPCC_C1_TX_IRQHandler             ; IPCC CPU1 RX free interrupt
-        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
-        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
-        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
-        DCD     SUBGHZ_Radio_IRQHandler           ; SUBGHZ Radio Interrupt
-        DCD     AES_IRQHandler                    ; AES Interrupt
-        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
-        DCD     PKA_IRQHandler                    ; PKA Interrupt
-        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
-        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
-        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
-        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
-        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
-        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
-        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
-        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_PVM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_PVM_IRQHandler
-        B PVD_PVM_IRQHandler
-
-        PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TAMP_STAMP_LSECSS_SSRU_IRQHandler
-        B TAMP_STAMP_LSECSS_SSRU_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC_IRQHandler
-        B ADC_IRQHandler
-
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-
-        PUBWEAK C2SEV_PWR_C2H_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-C2SEV_PWR_C2H_IRQHandler
-        B C2SEV_PWR_C2H_IRQHandler
-
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_IRQHandler
-        B TIM1_BRK_IRQHandler
-
-        PUBWEAK TIM1_UP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_UP_IRQHandler
-        B TIM1_UP_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_TRG_COM_IRQHandler
-        B TIM1_TRG_COM_IRQHandler
-
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM16_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
-        B TIM16_IRQHandler
-
-        PUBWEAK TIM17_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
-        B TIM17_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-
-        PUBWEAK LPTIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM2_IRQHandler
-        B LPTIM2_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK LPTIM3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM3_IRQHandler
-        B LPTIM3_IRQHandler
-
-        PUBWEAK SUBGHZSPI_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SUBGHZSPI_IRQHandler
-        B SUBGHZSPI_IRQHandler
-
-        PUBWEAK IPCC_C1_RX_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-IPCC_C1_RX_IRQHandler
-        B IPCC_C1_RX_IRQHandler
-
-        PUBWEAK IPCC_C1_TX_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-IPCC_C1_TX_IRQHandler
-        B IPCC_C1_TX_IRQHandler
-
-        PUBWEAK HSEM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HSEM_IRQHandler
-        B HSEM_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_EV_IRQHandler
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_ER_IRQHandler
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK SUBGHZ_Radio_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SUBGHZ_Radio_IRQHandler
-        B SUBGHZ_Radio_IRQHandler
-
-        PUBWEAK AES_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-AES_IRQHandler
-        B AES_IRQHandler
-
-        PUBWEAK RNG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_IRQHandler
-        B RNG_IRQHandler
-
-        PUBWEAK PKA_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PKA_IRQHandler
-        B PKA_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-        PUBWEAK DMA2_Channel6_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel6_IRQHandler
-        B DMA2_Channel6_IRQHandler
-
-        PUBWEAK DMA2_Channel7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel7_IRQHandler
-        B DMA2_Channel7_IRQHandler
-
-        PUBWEAK DMAMUX1_OVR_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMAMUX1_OVR_IRQHandler
-        B DMAMUX1_OVR_IRQHandler
-
-        END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wle4xx.s

@@ -1,494 +0,0 @@
-;********************************************************************************
-;* File Name          : startup_stm32wle4xx.s
-;* Author             : MCD Application Team
-;* Description        : M4 core vector table of the STM32WLxxxx devices for the
-;*                      IAR (EWARM) toolchain.
-;*
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR
-;*                        address.
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2020(2021) STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler                     ; Reset Handler
-
-        DCD     NMI_Handler                       ; NMI Handler
-        DCD     HardFault_Handler                 ; Hard Fault Handler
-        DCD     MemManage_Handler                 ; MPU Fault Handler
-        DCD     BusFault_Handler                  ; Bus Fault Handler
-        DCD     UsageFault_Handler                ; Usage Fault Handler
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     SVC_Handler                       ; SVCall Handler
-        DCD     DebugMon_Handler                  ; Debug Monitor Handler
-        DCD     0                                 ; Reserved
-        DCD     PendSV_Handler                    ; PendSV Handler
-        DCD     SysTick_Handler                   ; SysTick Handler
-
-        ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
-        DCD     TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
-        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
-        DCD     RCC_IRQHandler                    ; RCC Interrupt
-        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
-        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
-        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
-        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrupt
-        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
-        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
-        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
-        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
-        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
-        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
-        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
-        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
-        DCD     ADC_IRQHandler                    ; ADC Interrupt
-        DCD     DAC_IRQHandler                    ; DAC Interrupt
-        DCD     0                                 ; Reserved
-        DCD     COMP_IRQHandler                   ; COMP1 and COMP2 Interrupts
-        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
-        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
-        DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupt
-        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Communication Interrupts
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
-        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
-        DCD     TIM16_IRQHandler                  ; TIM16 Global Interrupt
-        DCD     TIM17_IRQHandler                  ; TIM17 Global Interrupt
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event Interrupt
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error Interrupt
-        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
-        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
-        DCD     USART1_IRQHandler                 ; USART1 Interrupt
-        DCD     USART2_IRQHandler                 ; USART2 Interrupt
-        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
-        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Global Interrupt
-        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Global Interrupt
-        DCD     EXTI15_10_IRQHandler              ; EXTI Lines [15:10] Interrupt
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
-        DCD     LPTIM3_IRQHandler                 ; LPTIM3 Global Interrupt
-        DCD     SUBGHZSPI_IRQHandler              ; SUBGHZSPI Interrupt
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
-        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
-        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
-        DCD     SUBGHZ_Radio_IRQHandler           ; SUBGHZ Radio Interrupt
-        DCD     AES_IRQHandler                    ; AES Interrupt
-        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
-        DCD     PKA_IRQHandler                    ; PKA Interrupt
-        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
-        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
-        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
-        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
-        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
-        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
-        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
-        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_PVM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_PVM_IRQHandler
-        B PVD_PVM_IRQHandler
-
-        PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TAMP_STAMP_LSECSS_SSRU_IRQHandler
-        B TAMP_STAMP_LSECSS_SSRU_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC_IRQHandler
-        B ADC_IRQHandler
-
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_IRQHandler
-        B TIM1_BRK_IRQHandler
-
-        PUBWEAK TIM1_UP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_UP_IRQHandler
-        B TIM1_UP_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_TRG_COM_IRQHandler
-        B TIM1_TRG_COM_IRQHandler
-
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM16_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
-        B TIM16_IRQHandler
-
-        PUBWEAK TIM17_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
-        B TIM17_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-
-        PUBWEAK LPTIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM2_IRQHandler
-        B LPTIM2_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK LPTIM3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM3_IRQHandler
-        B LPTIM3_IRQHandler
-
-        PUBWEAK SUBGHZSPI_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SUBGHZSPI_IRQHandler
-        B SUBGHZSPI_IRQHandler
-
-        PUBWEAK HSEM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HSEM_IRQHandler
-        B HSEM_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_EV_IRQHandler
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_ER_IRQHandler
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK SUBGHZ_Radio_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SUBGHZ_Radio_IRQHandler
-        B SUBGHZ_Radio_IRQHandler
-
-        PUBWEAK AES_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-AES_IRQHandler
-        B AES_IRQHandler
-
-        PUBWEAK RNG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_IRQHandler
-        B RNG_IRQHandler
-
-        PUBWEAK PKA_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PKA_IRQHandler
-        B PKA_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-        PUBWEAK DMA2_Channel6_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel6_IRQHandler
-        B DMA2_Channel6_IRQHandler
-
-        PUBWEAK DMA2_Channel7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel7_IRQHandler
-        B DMA2_Channel7_IRQHandler
-
-        PUBWEAK DMAMUX1_OVR_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMAMUX1_OVR_IRQHandler
-        B DMAMUX1_OVR_IRQHandler
-
-        END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/iar/startup_stm32wle5xx.s

@@ -1,494 +0,0 @@
-;********************************************************************************
-;* File Name          : startup_stm32wle5xx.s
-;* Author             : MCD Application Team
-;* Description        : M4 core vector table of the STM32WLxxxx devices for the
-;*                      IAR (EWARM) toolchain.
-;*
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR
-;*                        address.
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M4 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* Copyright (c) 2020(2021) STMicroelectronics.
-;* All rights reserved.
-;*
-;* This software is licensed under terms that can be found in the LICENSE file
-;* in the root directory of this software component.
-;* If no LICENSE file comes with this software, it is provided AS-IS.
-;
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler                     ; Reset Handler
-
-        DCD     NMI_Handler                       ; NMI Handler
-        DCD     HardFault_Handler                 ; Hard Fault Handler
-        DCD     MemManage_Handler                 ; MPU Fault Handler
-        DCD     BusFault_Handler                  ; Bus Fault Handler
-        DCD     UsageFault_Handler                ; Usage Fault Handler
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     SVC_Handler                       ; SVCall Handler
-        DCD     DebugMon_Handler                  ; Debug Monitor Handler
-        DCD     0                                 ; Reserved
-        DCD     PendSV_Handler                    ; PendSV Handler
-        DCD     SysTick_Handler                   ; SysTick Handler
-
-        ; External Interrupts
-        DCD     WWDG_IRQHandler                   ; Window WatchDog
-        DCD     PVD_PVM_IRQHandler                ; PVD and PVM Interrupt
-        DCD     TAMP_STAMP_LSECSS_SSRU_IRQHandler ; RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts
-        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup Interrupt
-        DCD     FLASH_IRQHandler                  ; FLASH global Interrupt
-        DCD     RCC_IRQHandler                    ; RCC Interrupt
-        DCD     EXTI0_IRQHandler                  ; EXTI Line 0 Interrupt
-        DCD     EXTI1_IRQHandler                  ; EXTI Line 1 Interrupt
-        DCD     EXTI2_IRQHandler                  ; EXTI Line 2 Interrupt
-        DCD     EXTI3_IRQHandler                  ; EXTI Line 3 Interrupt
-        DCD     EXTI4_IRQHandler                  ; EXTI Line 4 Interrupt
-        DCD     DMA1_Channel1_IRQHandler          ; DMA1 Channel 1 Interrupt
-        DCD     DMA1_Channel2_IRQHandler          ; DMA1 Channel 2 Interrupt
-        DCD     DMA1_Channel3_IRQHandler          ; DMA1 Channel 3 Interrupt
-        DCD     DMA1_Channel4_IRQHandler          ; DMA1 Channel 4 Interrupt
-        DCD     DMA1_Channel5_IRQHandler          ; DMA1 Channel 5 Interrupt
-        DCD     DMA1_Channel6_IRQHandler          ; DMA1 Channel 6 Interrupt
-        DCD     DMA1_Channel7_IRQHandler          ; DMA1 Channel 7 Interrupt
-        DCD     ADC_IRQHandler                    ; ADC Interrupt
-        DCD     DAC_IRQHandler                    ; DAC Interrupt
-        DCD     0                                 ; Reserved
-        DCD     COMP_IRQHandler                   ; COMP1 and COMP2 Interrupts
-        DCD     EXTI9_5_IRQHandler                ; EXTI Lines [9:5] Interrupt
-        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break Interrupt
-        DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupt
-        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Communication Interrupts
-        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare Interrupt
-        DCD     TIM2_IRQHandler                   ; TIM2 Global Interrupt
-        DCD     TIM16_IRQHandler                  ; TIM16 Global Interrupt
-        DCD     TIM17_IRQHandler                  ; TIM17 Global Interrupt
-        DCD     I2C1_EV_IRQHandler                ; I2C1 Event Interrupt
-        DCD     I2C1_ER_IRQHandler                ; I2C1 Error Interrupt
-        DCD     I2C2_EV_IRQHandler                ; I2C2 Event Interrupt
-        DCD     I2C2_ER_IRQHandler                ; I2C2 Error Interrupt
-        DCD     SPI1_IRQHandler                   ; SPI1 Interrupt
-        DCD     SPI2_IRQHandler                   ; SPI2 Interrupt
-        DCD     USART1_IRQHandler                 ; USART1 Interrupt
-        DCD     USART2_IRQHandler                 ; USART2 Interrupt
-        DCD     LPUART1_IRQHandler                ; LPUART1 Interrupt
-        DCD     LPTIM1_IRQHandler                 ; LPTIM1 Global Interrupt
-        DCD     LPTIM2_IRQHandler                 ; LPTIM2 Global Interrupt
-        DCD     EXTI15_10_IRQHandler              ; EXTI Lines [15:10] Interrupt
-        DCD     RTC_Alarm_IRQHandler              ; RTC Alarms (A and B) Interrupt
-        DCD     LPTIM3_IRQHandler                 ; LPTIM3 Global Interrupt
-        DCD     SUBGHZSPI_IRQHandler              ; SUBGHZSPI Interrupt
-        DCD     0                                 ; Reserved
-        DCD     0                                 ; Reserved
-        DCD     HSEM_IRQHandler                   ; HSEM0 Interrupt
-        DCD     I2C3_EV_IRQHandler                ; I2C3 Event Interrupt
-        DCD     I2C3_ER_IRQHandler                ; I2C3 Error Interrupt
-        DCD     SUBGHZ_Radio_IRQHandler           ; SUBGHZ Radio Interrupt
-        DCD     AES_IRQHandler                    ; AES Interrupt
-        DCD     RNG_IRQHandler                    ; RNG1 Interrupt
-        DCD     PKA_IRQHandler                    ; PKA Interrupt
-        DCD     DMA2_Channel1_IRQHandler          ; DMA2 Channel 1 Interrupt
-        DCD     DMA2_Channel2_IRQHandler          ; DMA2 Channel 2 Interrupt
-        DCD     DMA2_Channel3_IRQHandler          ; DMA2 Channel 3 Interrupt
-        DCD     DMA2_Channel4_IRQHandler          ; DMA2 Channel 4 Interrupt
-        DCD     DMA2_Channel5_IRQHandler          ; DMA2 Channel 5 Interrupt
-        DCD     DMA2_Channel6_IRQHandler          ; DMA2 Channel 6 Interrupt
-        DCD     DMA2_Channel7_IRQHandler          ; DMA2 Channel 7 Interrupt
-        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX overrun Interrupt
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-MemManage_Handler
-        B MemManage_Handler
-
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-BusFault_Handler
-        B BusFault_Handler
-
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-UsageFault_Handler
-        B UsageFault_Handler
-
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-
-        PUBWEAK PVD_PVM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_PVM_IRQHandler
-        B PVD_PVM_IRQHandler
-
-        PUBWEAK TAMP_STAMP_LSECSS_SSRU_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TAMP_STAMP_LSECSS_SSRU_IRQHandler
-        B TAMP_STAMP_LSECSS_SSRU_IRQHandler
-
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-
-        PUBWEAK ADC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC_IRQHandler
-        B ADC_IRQHandler
-
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-
-        PUBWEAK TIM1_BRK_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_IRQHandler
-        B TIM1_BRK_IRQHandler
-
-        PUBWEAK TIM1_UP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_UP_IRQHandler
-        B TIM1_UP_IRQHandler
-
-        PUBWEAK TIM1_TRG_COM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_TRG_COM_IRQHandler
-        B TIM1_TRG_COM_IRQHandler
-
-        PUBWEAK TIM1_CC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
-        B TIM1_CC_IRQHandler
-
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-
-        PUBWEAK TIM16_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
-        B TIM16_IRQHandler
-
-        PUBWEAK TIM17_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
-        B TIM17_IRQHandler
-
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-
-        PUBWEAK LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPUART1_IRQHandler
-        B LPUART1_IRQHandler
-
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-
-        PUBWEAK LPTIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM2_IRQHandler
-        B LPTIM2_IRQHandler
-
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-
-        PUBWEAK LPTIM3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM3_IRQHandler
-        B LPTIM3_IRQHandler
-
-        PUBWEAK SUBGHZSPI_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SUBGHZSPI_IRQHandler
-        B SUBGHZSPI_IRQHandler
-
-        PUBWEAK HSEM_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HSEM_IRQHandler
-        B HSEM_IRQHandler
-
-        PUBWEAK I2C3_EV_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_EV_IRQHandler
-        B I2C3_EV_IRQHandler
-
-        PUBWEAK I2C3_ER_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_ER_IRQHandler
-        B I2C3_ER_IRQHandler
-
-        PUBWEAK SUBGHZ_Radio_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SUBGHZ_Radio_IRQHandler
-        B SUBGHZ_Radio_IRQHandler
-
-        PUBWEAK AES_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-AES_IRQHandler
-        B AES_IRQHandler
-
-        PUBWEAK RNG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_IRQHandler
-        B RNG_IRQHandler
-
-        PUBWEAK PKA_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PKA_IRQHandler
-        B PKA_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-        PUBWEAK DMA2_Channel6_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel6_IRQHandler
-        B DMA2_Channel6_IRQHandler
-
-        PUBWEAK DMA2_Channel7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA2_Channel7_IRQHandler
-        B DMA2_Channel7_IRQHandler
-
-        PUBWEAK DMAMUX1_OVR_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMAMUX1_OVR_IRQHandler
-        B DMAMUX1_OVR_IRQHandler
-
-        END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

bsp/stm32/libraries/STM32WLxx_HAL/CMSIS/Device/ST/STM32WLxx/Source/Templates/system_stm32wlxx.c

@@ -1,359 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32wlxx.c
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex Device Peripheral Access Layer System Source File
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2020(-2021) STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  *   This file provides two functions and one global variable to be called from
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32wlxx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick
-  *                                  timer or configure other parameters.
-  *
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  *   After each device reset the MSI (4 MHz) is used as system clock source.
-  *   Then SystemInit() function is called, in "startup_stm32wlxx.s" file, to
-  *   configure the system clock before to branch to main program.
-  *
-  *   This file configures the system clock as follows:
-  *=============================================================================
-  *-----------------------------------------------------------------------------
-  *        System Clock source                    | MSI
-  *-----------------------------------------------------------------------------
-  *        SYSCLK(Hz)                             | 4000000
-  *-----------------------------------------------------------------------------
-  *        HCLK(Hz)                               | 4000000
-  *-----------------------------------------------------------------------------
-  *        AHB Prescaler                          | 1
-  *-----------------------------------------------------------------------------
-  *        APB1 Prescaler                         | 1
-  *-----------------------------------------------------------------------------
-  *        APB2 Prescaler                         | 1
-  *-----------------------------------------------------------------------------
-  *        PLL_M                                  | 1
-  *-----------------------------------------------------------------------------
-  *        PLL_N                                  | 8
-  *-----------------------------------------------------------------------------
-  *        PLL_P                                  | 7
-  *-----------------------------------------------------------------------------
-  *        PLL_Q                                  | 2
-  *-----------------------------------------------------------------------------
-  *        PLL_R                                  | 2
-  *-----------------------------------------------------------------------------
-  *        PLLSAI1_P                              | NA
-  *-----------------------------------------------------------------------------
-  *        PLLSAI1_Q                              | NA
-  *-----------------------------------------------------------------------------
-  *        PLLSAI1_R                              | NA
-  *-----------------------------------------------------------------------------
-  *        Require 48MHz for USB OTG FS,          | Disabled
-  *        SDIO and RNG clock                     |
-  *-----------------------------------------------------------------------------
-  *=============================================================================
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32WLxx_system
-  * @{
-  */
-
-/** @addtogroup stm32WLxx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32wlxx.h"
-
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    (32000000UL) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-   #define MSI_VALUE    (4000000UL) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    (16000000UL) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  (32000UL)       /*!< Value of LSI in Hz*/
-#endif /* LSI_VALUE */
-
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    (32768UL)    /*!< Value of LSE in Hz*/
-#endif /* LSE_VALUE */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32WLxx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32WLxx_System_Private_Defines
-  * @{
-  */
-
-/* Note: Following vector table addresses must be defined in line with linker
-         configuration. */
-/*!< Uncomment the following line if you need to relocate CPU1 CM4 and/or CPU2
-     CM0+ vector table anywhere in Sram or Flash. Else vector table will be kept
-     at address 0x00 which correspond to automatic remap of boot address selected */
-/* #define USER_VECT_TAB_ADDRESS */
-#if defined(USER_VECT_TAB_ADDRESS)
-#ifdef CORE_CM0PLUS
- /*!< Uncomment this line for user vector table remap in Sram else user remap
-      will be done in Flash. */
-/* #define VECT_TAB_SRAM */
-#if defined(VECT_TAB_SRAM)
-#define VECT_TAB_BASE_ADDRESS   SRAM2_BASE      /*!< Vector Table base address field.
-                                                     This value must be a multiple of 0x100. */
-#define VECT_TAB_OFFSET         0x00008000U     /*!< Vector Table base offset field.
-                                                     This value must be a multiple of 0x100. */
-#else
-#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
-                                                     This value must be a multiple of 0x100. */
-#define VECT_TAB_OFFSET         0x00020000U        /*!< Vector Table base offset field.
-                                                     This value must be a multiple of 0x100. */
-#endif
-#else /* CORE_CM4 */
- /*!< Uncomment this line for user vector table remap in Sram else user remap
-      will be done in Flash. */
-/* #define VECT_TAB_SRAM */
-#if defined(VECT_TAB_SRAM)
-#define VECT_TAB_BASE_ADDRESS   SRAM1_BASE      /*!< Vector Table base address field.
-                                                     This value must be a multiple of 0x200. */
-#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
-                                                     This value must be a multiple of 0x200. */
-#else
-#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
-                                                     This value must be a multiple of 0x200. */
-#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
-                                                     This value must be a multiple of 0x200. */
-#endif
-#endif
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32WLxx_System_Private_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32WLxx_System_Private_Variables
-  * @{
-  */
-  /* The SystemCoreClock variable is updated in three ways:
-      1) from within HAL_Init()
-      2) by calling CMSIS function SystemCoreClockUpdate()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-  */
-  uint32_t SystemCoreClock  = 4000000UL; /*CPU1: M4 on MSI clock after startup (4MHz)*/
-
-  const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
-
-  const uint32_t APBPrescTable[8UL]  = {0UL, 0UL, 0UL, 0UL, 1UL, 2UL, 3UL, 4UL};
-
-  const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
-    4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32WLxx_System_Private_FunctionPrototypes
-  * @{
-  */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32WLxx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
-#if defined(USER_VECT_TAB_ADDRESS)
-  /* Configure the Vector Table location add offset address ------------------*/
-  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
-#endif
-
-  /* FPU settings ------------------------------------------------------------*/
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
-#endif
-}
-
-/**
-  * @brief  Update SystemCoreClock variable according to Clock Register Values.
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
-  *           constant and the selected clock source:
-  *
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
-  *
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
-  *
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
-  *
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
-  *             or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
-  *
-  *         (*) MSI_VALUE is a constant defined in stm32wlxx_hal.h file (default value
-  *             4 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.
-  *
-  *         (**) HSI_VALUE is a constant defined in stm32wlxx_hal_conf.h file (default value
-  *              16 MHz) but the real value may vary depending on the variations
-  *              in voltage and temperature.
-  *
-  *         (***) HSE_VALUE is a constant defined in stm32wlxx_hal_conf.h file (default value
-  *              32 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  *
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate(void)
-{
-  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
-
- /* Get MSI Range frequency--------------------------------------------------*/
-
-   /* Get MSI Range frequency--------------------------------------------------*/
-   if((RCC->CR & RCC_CR_MSIRGSEL) == 0U)
-   { /* MSISRANGE from RCC_CSR applies */
-     msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U;
-   }
-   else
-   { /* MSIRANGE from RCC_CR applies */
-     msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U;
-   }
-   /*MSI frequency range in HZ*/
-   msirange = MSIRangeTable[msirange];
-
-
-  /*SystemCoreClock=HAL_RCC_GetSysClockFreq();*/
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (RCC->CFGR & RCC_CFGR_SWS)
-  {
-    case 0x00:   /* MSI used as system clock source */
-      SystemCoreClock = msirange;
-      break;
-
-    case 0x04:  /* HSI used as system clock source */
-      /* HSI used as system clock source */
-        SystemCoreClock = HSI_VALUE;
-      break;
-
-    case 0x08:  /* HSE used as system clock source */
-      SystemCoreClock = HSE_VALUE;
-      break;
-
-    case 0x0C: /* PLL used as system clock  source */
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
-         SYSCLK = PLL_VCO / PLLR
-         */
-      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
-      pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
-
-      switch (pllsource)
-      {
-        case 0x02:  /* HSI used as PLL clock source */
-          pllvco = (HSI_VALUE / pllm);
-          break;
-
-        case 0x03:  /* HSE used as PLL clock source */
-          pllvco = (HSE_VALUE / pllm);
-          break;
-
-        default:    /* MSI used as PLL clock source */
-          pllvco = (msirange / pllm);
-          break;
-      }
-
-      pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
-      pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
-
-      SystemCoreClock = pllvco/pllr;
-      break;
-
-    default:
-      SystemCoreClock = msirange;
-      break;
-  }
-
-  /* Compute HCLK clock frequency --------------------------------------------*/
-#if defined(DUAL_CORE) &&  defined(CORE_CM0PLUS)
-  /* Get HCLK2 prescaler */
-  tmp = AHBPrescTable[((RCC->EXTCFGR & RCC_EXTCFGR_C2HPRE) >> RCC_EXTCFGR_C2HPRE_Pos)];
-#else
-  /* Get HCLK1 prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
-#endif
-
-  /* Core clock frequency */
-  SystemCoreClock = SystemCoreClock / tmp;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/SConscript

@@ -1,77 +0,0 @@
-import rtconfig
-from building import *
-
-# get current directory
-cwd = GetCurrentDir()
-
-# The set of source files associated with this SConscript file.
-
-src = Split('''
-CMSIS/Device/ST/STM32WLxx/Source/Templates/system_stm32wlxx.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_comp.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_crc_ex.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cryp.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cryp_ex.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rng.c
-STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c
-''')
-
-if GetDepend(['RT_USING_SERIAL']) or GetDepend(['RT_USING_NANO', 'RT_USING_CONSOLE']):
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c']
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c']
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_usart.c']
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_usart_ex.c']
-
-if GetDepend(['RT_USING_I2C']):
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_i2c.c']
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_i2c_ex.c']
-
-if GetDepend(['RT_USING_SPI']):
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_spi.c']
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_spi_ex.c']
-
-if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM']):
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_lptim.c']
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.c']
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.c']
-
-if GetDepend(['RT_USING_ADC']):
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c']
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c']
-
-if GetDepend(['BSP_USING_ONCHIP_RTC']):
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c']
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c']
-
-if GetDepend(['RT_USING_WDT']):
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_iwdg.c']
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_wwdg.c']
-
-if GetDepend(['RT_USING_PM']):
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_lptim.c']
-
-if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c']
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c']
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ramfunc.c']
-
-if GetDepend(['BSP_USING_SUBGHZ']):
-    src += ['STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c']
-
-path = [cwd + '/STM32WLxx_HAL_Driver/Inc',
-    cwd + '/CMSIS/Device/ST/STM32WLxx/Include']
-
-CPPDEFINES = ['USE_HAL_DRIVER']
-group = DefineGroup('STM32_HAL', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
-
-Return('group')

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

@@ -1,3830 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_hal_legacy.h
-  * @author  MCD Application Team
-  * @brief   This file contains aliases definition for the STM32Cube HAL constants
-  *          macros and functions maintained for legacy purpose.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32_HAL_LEGACY
-#define STM32_HAL_LEGACY
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
-#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
-#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
-#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
-#if defined(STM32U5)
-#define CRYP_DATATYPE_32B               CRYP_NO_SWAP
-#define CRYP_DATATYPE_16B               CRYP_HALFWORD_SWAP
-#define CRYP_DATATYPE_8B                CRYP_BYTE_SWAP
-#define CRYP_DATATYPE_1B                CRYP_BIT_SWAP
-#define CRYP_CCF_CLEAR                  CRYP_CLEAR_CCF
-#define CRYP_ERR_CLEAR                  CRYP_CLEAR_RWEIF
-#endif /* STM32U5 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
-#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
-#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
-#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
-#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
-#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
-#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
-#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
-#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
-#define REGULAR_GROUP                   ADC_REGULAR_GROUP
-#define INJECTED_GROUP                  ADC_INJECTED_GROUP
-#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
-#define AWD_EVENT                       ADC_AWD_EVENT
-#define AWD1_EVENT                      ADC_AWD1_EVENT
-#define AWD2_EVENT                      ADC_AWD2_EVENT
-#define AWD3_EVENT                      ADC_AWD3_EVENT
-#define OVR_EVENT                       ADC_OVR_EVENT
-#define JQOVF_EVENT                     ADC_JQOVF_EVENT
-#define ALL_CHANNELS                    ADC_ALL_CHANNELS
-#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
-#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
-#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
-#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
-#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
-#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
-#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
-#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
-#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
-#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
-#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
-#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
-#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
-#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
-#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
-#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
-#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
-#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
-#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
-
-#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
-#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
-#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
-#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
-#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
-#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
-
-#if defined(STM32H7)
-#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
-#endif /* STM32H7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
-#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
-#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
-#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
-#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
-#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
-#if defined(STM32L0)
-#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
-#endif
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
-#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32L0) || defined(STM32L4)
-#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-
-#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
-#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
-#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
-#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
-#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
-#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
-
-#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
-#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
-#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
-#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
-#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
-#if defined(STM32L0)
-/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
-/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
-/* to the second dedicated IO (only for COMP2).                               */
-#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
-#else
-#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
-#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
-#endif
-#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
-#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
-
-#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
-#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
-
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
-/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
-#if defined(COMP_CSR_LOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
-#elif defined(COMP_CSR_COMP1LOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
-#elif defined(COMP_CSR_COMPxLOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
-#endif
-
-#if defined(STM32L4)
-#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
-#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
-#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
-#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
-#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
-#endif
-
-#if defined(STM32L0)
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
-#else
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
-#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
-#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
-#endif
-
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Aliases CRC API aliases
-  * @{
-  */
-#if defined(STM32WL) || defined(STM32WB) || defined(STM32L5) || defined(STM32L4)
-#else
-#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */
-#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
-#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
-#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC_WAVE_NONE                                   0x00000000U
-#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
-#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
-#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
-#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
-#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
-
-#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
-#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
-#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
-#endif
-
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
-#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
-#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
-#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
-#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
-#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
-#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
-#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
-#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
-#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
-#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
-
-#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
-#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
-#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
-
-#if defined(STM32L4)
-
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
-#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
-#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
-
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
-#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
-#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
-#endif
-
-#endif /* STM32L4 */
-
-#if defined(STM32G0)
-#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
-#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM
-#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM
-
-#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM
-#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM
-#endif
-
-#if defined(STM32H7)
-
-#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
-
-#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
-#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
-
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
-#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
-
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
-
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
-#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
-#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
-#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
-#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
-
-#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
-#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
-
-#endif /* STM32H7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
-#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
-#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
-#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
-#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
-#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
-#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
-#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
-#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
-#define OBEX_PCROP                    OPTIONBYTE_PCROP
-#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
-#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
-#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
-#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
-#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
-#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
-#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
-#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
-#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
-#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
-#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
-#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
-#define PAGESIZE                      FLASH_PAGE_SIZE
-#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
-#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
-#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
-#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
-#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
-#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
-#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
-#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
-#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
-#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
-#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
-#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
-#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
-#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
-#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
-#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
-#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
-#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
-#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
-#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
-#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
-#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
-#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
-#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
-#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
-#define OB_WDG_SW                     OB_IWDG_SW
-#define OB_WDG_HW                     OB_IWDG_HW
-#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
-#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
-#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
-#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
-#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
-#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
-#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
-#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
-#if defined(STM32G0)
-#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
-#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
-#else
-#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
-#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
-#endif
-#if defined(STM32H7)
-#define FLASH_FLAG_SNECCE_BANK1RR     FLASH_FLAG_SNECCERR_BANK1
-#define FLASH_FLAG_DBECCE_BANK1RR     FLASH_FLAG_DBECCERR_BANK1
-#define FLASH_FLAG_STRBER_BANK1R      FLASH_FLAG_STRBERR_BANK1
-#define FLASH_FLAG_SNECCE_BANK2RR     FLASH_FLAG_SNECCERR_BANK2
-#define FLASH_FLAG_DBECCE_BANK2RR     FLASH_FLAG_DBECCERR_BANK2
-#define FLASH_FLAG_STRBER_BANK2R      FLASH_FLAG_STRBERR_BANK2
-#define FLASH_FLAG_WDW                FLASH_FLAG_WBNE
-#define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL
-#endif /* STM32H7 */
-#if defined(STM32U5)
-#define OB_USER_nRST_STOP             OB_USER_NRST_STOP
-#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
-#define OB_USER_nRST_SHDW             OB_USER_NRST_SHDW
-#define OB_USER_nSWBOOT0              OB_USER_NSWBOOT0
-#define OB_USER_nBOOT0                OB_USER_NBOOT0
-#define OB_nBOOT0_RESET               OB_NBOOT0_RESET
-#define OB_nBOOT0_SET                 OB_NBOOT0_SET
-#endif /* STM32U5 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#if defined(STM32H7)
-#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
-#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
-#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
-#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
-#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
-#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
-#endif /* STM32H7 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
-#if defined(STM32G4)
-
-#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
-#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
-#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
-#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
-#endif /* STM32G4 */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
-  * @{
-  */
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
-#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
-#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
-#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
-#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
-#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
-/**
-  * @}
-  */
-
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
-#define GET_GPIO_INDEX                            GPIO_GET_INDEX
-
-#if defined(STM32F4)
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
-#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
-#endif
-
-#if defined(STM32F7)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32L4)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32H7)
-#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
-#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
-#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
-#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
-#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
-#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
-
-#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
-    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
-#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
-#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
-#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
-#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
-#endif /* STM32H7 */
-
-#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
-#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
-#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
-
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB)
-#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
-#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
-#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
-#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/
-
-#if defined(STM32L1)
-#define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
-#define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
-#define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
-#define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L1 */
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
-#define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
-#define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
-#define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F0 || STM32F3 || STM32F1 */
-
-#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
-/**
-  * @}
-  */
-
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-
-#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
-#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
-#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
-#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
-#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
-#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
-
-#if defined(STM32G4)
-#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
-#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
-#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
-#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
-#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A
-#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B
-#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
-#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
-#endif /* STM32G4 */
-
-#if defined(STM32H7)
-#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
-
-#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
-#endif /* STM32H7 */
-
-#if defined(STM32F3)
-/** @brief Constants defining available sources associated to external events.
-  */
-#define HRTIM_EVENTSRC_1              (0x00000000U)
-#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
-#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
-#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
-
-/** @brief Constants defining the DLL calibration periods (in micro seconds)
-  */
-#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
-#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
-#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
-#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
-
-#endif /* STM32F3 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
-#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
-#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
-#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
-#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
-#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
-#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
-#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
-#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
-#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
-#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
-#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
-#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
-
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
-
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/* The following 3 definition have also been present in a temporary version of lptim.h */
-/* They need to be renamed also to the right name, just in case */
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-#if defined(STM32U5)
-#define LPTIM_ISR_CC1        LPTIM_ISR_CC1IF
-#define LPTIM_ISR_CC2        LPTIM_ISR_CC2IF
-#endif /* STM32U5 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
-#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
-#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
-#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
-
-#define NAND_AddressTypedef             NAND_AddressTypeDef
-
-#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
-#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
-#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
-#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
-#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
-#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
-#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
-#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
-#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
-
-#define __NOR_WRITE                    NOR_WRITE
-#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
-/**
-  * @}
-  */
-
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
-#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
-#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
-#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
-
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
-
-#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
-#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
-
-#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
-#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
-
-#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
-#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
-#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
-#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
-#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
-#endif
-
-#if defined(STM32L4) || defined(STM32L5)
-#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALPOWER
-#elif defined(STM32G4)
-#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALSPEED
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
-
-#if defined(STM32H7)
-#define I2S_IT_TXE               I2S_IT_TXP
-#define I2S_IT_RXNE              I2S_IT_RXP
-
-#define I2S_FLAG_TXE             I2S_FLAG_TXP
-#define I2S_FLAG_RXNE            I2S_FLAG_RXP
-#endif
-
-#if defined(STM32F7)
-#define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA                       ATA_DATA
-#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
-#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
-#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
-#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
-#define CF_CARD_HEAD                  ATA_CARD_HEAD
-#define CF_STATUS_CMD                 ATA_STATUS_CMD
-#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
-#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
-#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
-#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
-
-#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
-#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
-#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
-#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
-#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define FORMAT_BIN                  RTC_FORMAT_BIN
-#define FORMAT_BCD                  RTC_FORMAT_BCD
-
-#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
-
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
-
-#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
-
-#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
-#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
-#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
-
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
-#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
-#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
-
-#if defined(STM32H7)
-#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
-#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
-
-#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
-#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
-#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
-#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL
-#endif /* STM32H7 */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
-#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
-
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-
-#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
-#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
-
-#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
-#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
-#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
-#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
-#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
-#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
-#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
-#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
-#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
-#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
-#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
-#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
-#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
-
-#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
-#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
-
-#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
-#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
-
-#if defined(STM32H7)
-
-#define SPI_FLAG_TXE                    SPI_FLAG_TXP
-#define SPI_FLAG_RXNE                   SPI_FLAG_RXP
-
-#define SPI_IT_TXE                      SPI_IT_TXP
-#define SPI_IT_RXNE                     SPI_IT_RXP
-
-#define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
-#define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
-#define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
-#define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
-
-#endif /* STM32H7 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
-#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
-
-#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
-#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
-#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
-#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
-#define TIM_DMABase_SR                   TIM_DMABASE_SR
-#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
-#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
-#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
-#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
-#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
-#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
-#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
-#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
-#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
-#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
-#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
-#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
-#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
-#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
-#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
-#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
-#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
-#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
-#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
-#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
-#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
-#define TIM_DMABase_OR                   TIM_DMABASE_OR
-
-#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
-#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
-#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
-#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
-#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
-#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
-#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
-#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
-#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
-
-#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
-#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
-#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
-#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
-#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
-#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
-#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
-#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
-#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
-#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
-#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
-#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
-#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
-#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
-#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
-#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
-#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
-#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
-
-#if defined(STM32L0)
-#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
-#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
-#endif
-
-#if defined(STM32F3)
-#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
-#endif
-
-#if defined(STM32H7)
-#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
-#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
-#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
-#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
-#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
-#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
-#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
-#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
-#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
-#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
-#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
-#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
-#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
-#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
-#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
-#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
-#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
-
-#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
-#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
-
-#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
-#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
-#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
-#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
-
-#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
-#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
-#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
-#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
-
-#define __DIV_LPUART                    UART_DIV_LPUART
-
-#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
-#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
-#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
-
-#define USARTNACK_ENABLED               USART_NACK_ENABLE
-#define USARTNACK_DISABLED              USART_NACK_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CFR_BASE                    WWDG_CFR_BASE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
-#define CAN_IT_RQCP0                CAN_IT_TME
-#define CAN_IT_RQCP1                CAN_IT_TME
-#define CAN_IT_RQCP2                CAN_IT_TME
-#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
-#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
-#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define VLAN_TAG                ETH_VLAN_TAG
-#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
-#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
-#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
-#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
-#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
-#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
-#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
-
-#define ETH_MMCCR              0x00000100U
-#define ETH_MMCRIR             0x00000104U
-#define ETH_MMCTIR             0x00000108U
-#define ETH_MMCRIMR            0x0000010CU
-#define ETH_MMCTIMR            0x00000110U
-#define ETH_MMCTGFSCCR         0x0000014CU
-#define ETH_MMCTGFMSCCR        0x00000150U
-#define ETH_MMCTGFCR           0x00000168U
-#define ETH_MMCRFCECR          0x00000194U
-#define ETH_MMCRFAECR          0x00000198U
-#define ETH_MMCRGUFCR          0x000001C4U
-
-#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
-#if defined(STM32F1)
-#else
-#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
-#define DCMI_IT_OVF             DCMI_IT_OVR
-#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
-#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
-
-#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
-#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
-#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
-
-/**
-  * @}
-  */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
-  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
-  || defined(STM32H7)
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
-#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
-#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
-#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
-
-#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
-#define CM_RGB888               DMA2D_INPUT_RGB888
-#define CM_RGB565               DMA2D_INPUT_RGB565
-#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
-#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
-#define CM_L8                   DMA2D_INPUT_L8
-#define CM_AL44                 DMA2D_INPUT_AL44
-#define CM_AL88                 DMA2D_INPUT_AL88
-#define CM_L4                   DMA2D_INPUT_L4
-#define CM_A8                   DMA2D_INPUT_A8
-#define CM_A4                   DMA2D_INPUT_A4
-/**
-  * @}
-  */
-#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
-  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
-  || defined(STM32H7) || defined(STM32U5)
-/** @defgroup DMA2D_Aliases DMA2D API Aliases
-  * @{
-  */
-#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
-                                                                        for compatibility with legacy code */
-/**
-  * @}
-  */
-
-#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 || STM32U5 */
-
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
-/**
-  * @}
-  */
-
-#if !defined(STM32F2)
-/** @defgroup HASH_alias HASH API alias
-  * @{
-  */
-#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< Redirection for compatibility with legacy code */
-/**
-  *
-  * @}
-  */
-#endif /* STM32F2 */
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
-#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
-#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
-
-/*HASH Algorithm Selection*/
-
-#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
-#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
-#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
-#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
-
-#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
-#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
-
-#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
-#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
-
-#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
-
-#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
-#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
-#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
-#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
-
-#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
-#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
-#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
-#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
-
-#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
-#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
-#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
-#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
-
-#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
-#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
-#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
-#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
-
-#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
-                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-#if defined(STM32L0)
-#else
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#endif
-#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
-                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
-#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
-#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
-#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
-#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
-#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
-#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
-#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
-#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
-#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
-#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
-#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
-
-/**
-  * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
-#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
-#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
-
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
-                                                                 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
-#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
-#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
-#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
-#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
-#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
-#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
-#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
-#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-
-#if defined(STM32F4)
-#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
-#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
-#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
-#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
-#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
-#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
-#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
-#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
-#endif /* STM32F4 */
-/**
-  * @}
- */
-
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
-  * @{
-  */
-
-#if defined(STM32G0)
-#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
-#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
-#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
-#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
-#endif
-#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
-#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
-#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
-#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
-#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
-#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
-#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
-#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
-#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
-#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
-#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
-#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
-#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
-#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
-#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
-#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
-
-#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
-#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
-#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
-#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
-#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
-#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
-#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
-
-#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
-#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
-#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
-#define CR_PMODE_BB                                   CR_VOS_BB
-
-#define DBP_BitNumber                                 DBP_BIT_NUMBER
-#define PVDE_BitNumber                                PVDE_BIT_NUMBER
-#define PMODE_BitNumber                               PMODE_BIT_NUMBER
-#define EWUP_BitNumber                                EWUP_BIT_NUMBER
-#define FPDS_BitNumber                                FPDS_BIT_NUMBER
-#define ODEN_BitNumber                                ODEN_BIT_NUMBER
-#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
-#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
-#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
-#define BRE_BitNumber                                 BRE_BIT_NUMBER
-
-#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
-
-/**
-  * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
-#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
-#define HAL_TIM_DMAError                                TIM_DMAError
-#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
-#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
-#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
-#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
-#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
-#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
-#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
-#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
-#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
-#define HAL_LTDC_Relaod           HAL_LTDC_Reload
-#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
-#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define AES_IT_CC                      CRYP_IT_CC
-#define AES_IT_ERR                     CRYP_IT_ERR
-#define AES_FLAG_CCF                   CRYP_FLAG_CCF
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
-#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
-#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
-#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
-#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
-#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
-#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
-#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
-#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
-#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
-#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
-#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
-#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
-
-#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
-#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
-#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
-#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
-#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
-#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
-#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
-#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
-#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
-#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
-
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
-#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
-#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
-#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
-#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
-#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
-#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
-#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
-#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
-#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
-#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
-#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
-#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
-#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
-
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
-#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
-#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
-#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
-#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
-#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
-
-#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
-#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
-#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
-#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
-#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
-
-#define __HAL_ADC_SQR1                                   ADC_SQR1
-#define __HAL_ADC_SMPR1                                  ADC_SMPR1
-#define __HAL_ADC_SMPR2                                  ADC_SMPR2
-#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
-#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
-#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
-#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
-#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
-#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
-#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
-#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
-#define __HAL_ADC_JSQR                                   ADC_JSQR
-
-#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
-#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
-#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
-#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
-#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
-#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
-#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
-#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
-#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
-
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
-
-
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#if defined(STM32H7)
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
-#else
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
-#endif /* STM32H7 */
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined(STM32F3)
-#define COMP_START                                       __HAL_COMP_ENABLE
-#define COMP_STOP                                        __HAL_COMP_DISABLE
-#define COMP_LOCK                                        __HAL_COMP_LOCK
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
-#else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-
-#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
-
-#if defined(STM32L0) || defined(STM32L4)
-/* Note: On these STM32 families, the only argument of this macro             */
-/*       is COMP_FLAG_LOCK.                                                   */
-/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
-/*       argument.                                                            */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
-#endif
-/**
-  * @}
-  */
-
-#if defined(STM32L0) || defined(STM32L4)
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-/**
-  * @}
-  */
-#endif
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
-                           ((WAVE) == DAC_WAVE_NOISE)|| \
-                           ((WAVE) == DAC_WAVE_TRIANGLE))
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_WRPAREA          IS_OB_WRPAREA
-#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
-#define IS_TYPEERASE        IS_FLASH_TYPEERASE
-#define IS_NBSECTORS        IS_FLASH_NBSECTORS
-#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
-#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
-#if defined(STM32F1)
-#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
-#else
-#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
-#endif /* STM32F1 */
-#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
-#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
-#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
-#define __HAL_I2C_SPEED                 I2C_SPEED
-#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
-#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
-#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
-#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
-#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
-#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
-#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
-#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
-#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
-
-#if defined(STM32H7)
-#define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
-#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
-
-#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
-#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
-#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
-#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
-
-#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
-
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
-#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
-#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
-#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
-#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
-#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
-#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
-#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
-#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
-#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
-#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
-#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
-#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
-#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
-#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
-#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
-#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
-#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
-
-#if defined (STM32F4)
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
-#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
-#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
-#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
-#endif /* STM32F4 */
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
-  * @{
-  */
-
-#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
-#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
-
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
-                                         )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-
-#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
-#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
-#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
-#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
-#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
-#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
-#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
-#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
-#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
-#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
-#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
-#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
-#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
-#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
-#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
-#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
-#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
-#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
-#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
-
-#if defined(STM32WB)
-#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
-#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
-#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
-#define QSPI_IRQHandler QUADSPI_IRQHandler
-#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
-
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
-#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
-#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
-#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
-#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
-#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
-#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
-#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
-#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
-#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
-
-#if defined(STM32H7)
-#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
-#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
-
-#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
-#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
-
-
-#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
-#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
-#endif
-
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
-
-#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
-#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
-#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
-#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
-#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
-#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
-#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
-#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
-#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
-#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
-#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
-#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
-
-#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
-#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
-#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
-#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
-#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
-#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
-#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
-#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
-#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
-#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
-#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
-#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
-#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
-#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
-#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
-#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
-#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
-#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
-#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
-#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
-#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
-#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
-#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
-#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
-#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
-#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
-#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
-#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
-#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
-#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
-#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
-#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
-#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
-#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
-#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
-#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
-#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
-#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
-#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
-#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
-#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
-#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
-#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
-#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
-#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
-#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
-#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
-#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
-#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
-#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
-#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
-#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
-#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
-#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
-#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
-#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
-#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
-#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
-#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
-#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
-#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
-#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
-#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
-#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
-#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
-#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
-#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
-#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
-#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
-#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
-#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
-#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
-#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
-#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
-#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
-#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
-#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
-#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
-#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
-#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
-#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
-#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
-#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
-
-/* alias define maintained for legacy */
-#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
-#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
-#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
-#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
-#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
-#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
-#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
-#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
-#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
-#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
-#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
-#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
-#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
-#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
-#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
-#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
-#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
-#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
-#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
-
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
-#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
-#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
-#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
-#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
-#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
-#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
-#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
-#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
-#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
-#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
-#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
-#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
-#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
-#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
-#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
-#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
-#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
-#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
-
-#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
-#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
-#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
-#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
-#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
-#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
-#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
-#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
-#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
-#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
-#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
-#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
-#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
-#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
-#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
-#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
-#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
-#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
-#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
-#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
-#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
-#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
-#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
-#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
-#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
-#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
-#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
-#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
-#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
-#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
-#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
-#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
-#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
-#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
-#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
-#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
-#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
-#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
-#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
-#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
-#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
-#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
-#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
-#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
-#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
-#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
-#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
-#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
-#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
-#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
-#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
-#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
-#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
-#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
-#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
-#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
-#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
-#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
-#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
-#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
-#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
-#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
-#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
-#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
-#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
-#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
-#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
-#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
-#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
-#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
-#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
-#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
-#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
-#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
-#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
-#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
-#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
-#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
-#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
-#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
-#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
-#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
-#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
-#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
-#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
-#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
-#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
-#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
-#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
-#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
-#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
-#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
-#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
-#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
-#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
-#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
-#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
-#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
-#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
-#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
-#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
-#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
-#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
-#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
-#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
-#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
-#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
-#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
-#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
-#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
-#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
-#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
-#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
-#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
-
-#if defined(STM32L1)
-#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
-#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
-#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
-#endif /* STM32L1 */
-
-#if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
-#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
-#define Sdmmc1ClockSelection               SdioClockSelection
-#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
-#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
-#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
-#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
-#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
-#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
-#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
-#define SdioClockSelection                 Sdmmc1ClockSelection
-#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
-#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
-#endif
-
-#if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
-#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
-#endif
-
-#if defined(STM32H7)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
-
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
-#endif
-
-#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
-#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
-
-#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
-
-#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
-#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
-
-#define RCC_IT_HSI14                RCC_IT_HSI14RDY
-
-#define RCC_IT_CSSLSE               RCC_IT_LSECSS
-#define RCC_IT_CSSHSE               RCC_IT_CSS
-
-#define RCC_PLLMUL_3                RCC_PLL_MUL3
-#define RCC_PLLMUL_4                RCC_PLL_MUL4
-#define RCC_PLLMUL_6                RCC_PLL_MUL6
-#define RCC_PLLMUL_8                RCC_PLL_MUL8
-#define RCC_PLLMUL_12               RCC_PLL_MUL12
-#define RCC_PLLMUL_16               RCC_PLL_MUL16
-#define RCC_PLLMUL_24               RCC_PLL_MUL24
-#define RCC_PLLMUL_32               RCC_PLL_MUL32
-#define RCC_PLLMUL_48               RCC_PLL_MUL48
-
-#define RCC_PLLDIV_2                RCC_PLL_DIV2
-#define RCC_PLLDIV_3                RCC_PLL_DIV3
-#define RCC_PLLDIV_4                RCC_PLL_DIV4
-
-#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
-#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
-#define RCC_MCO_NODIV               RCC_MCODIV_1
-#define RCC_MCO_DIV1                RCC_MCODIV_1
-#define RCC_MCO_DIV2                RCC_MCODIV_2
-#define RCC_MCO_DIV4                RCC_MCODIV_4
-#define RCC_MCO_DIV8                RCC_MCODIV_8
-#define RCC_MCO_DIV16               RCC_MCODIV_16
-#define RCC_MCO_DIV32               RCC_MCODIV_32
-#define RCC_MCO_DIV64               RCC_MCODIV_64
-#define RCC_MCO_DIV128              RCC_MCODIV_128
-#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
-#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
-#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
-#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
-#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
-#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
-#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
-#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
-#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
-
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
-#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
-#else
-#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
-#endif
-
-#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
-#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
-#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
-#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
-#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
-#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
-
-#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
-#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
-#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
-#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
-#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
-#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
-#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
-#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
-#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
-#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
-#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
-#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
-#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
-#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
-#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
-#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
-#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
-#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
-#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
-#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
-#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
-#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
-#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
-#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
-#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
-#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
-#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
-#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
-#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
-#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
-#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
-
-#define CR_HSION_BB            RCC_CR_HSION_BB
-#define CR_CSSON_BB            RCC_CR_CSSON_BB
-#define CR_PLLON_BB            RCC_CR_PLLON_BB
-#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
-#define CR_MSION_BB            RCC_CR_MSION_BB
-#define CSR_LSION_BB           RCC_CSR_LSION_BB
-#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
-#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
-#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
-#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
-#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
-#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
-#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
-#define CR_HSEON_BB            RCC_CR_HSEON_BB
-#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
-#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
-#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
-
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
-
-#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
-
-#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
-#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
-
-#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
-#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
-#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
-#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
-#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
-#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
-
-#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
-#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
-#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
-#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
-#define DfsdmClockSelection         Dfsdm1ClockSelection
-#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
-#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
-#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
-#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
-#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
-#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
-
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
-#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
-#if defined(STM32U5)
-#define MSIKPLLModeSEL  RCC_MSIKPLL_MODE_SEL
-#define MSISPLLModeSEL  RCC_MSISPLL_MODE_SEL
-#define __HAL_RCC_AHB21_CLK_DISABLE           __HAL_RCC_AHB2_1_CLK_DISABLE
-#define __HAL_RCC_AHB22_CLK_DISABLE           __HAL_RCC_AHB2_2_CLK_DISABLE
-#define __HAL_RCC_AHB1_CLK_Disable_Clear      __HAL_RCC_AHB1_CLK_ENABLE
-#define __HAL_RCC_AHB21_CLK_Disable_Clear     __HAL_RCC_AHB2_1_CLK_ENABLE
-#define __HAL_RCC_AHB22_CLK_Disable_Clear     __HAL_RCC_AHB2_2_CLK_ENABLE
-#define __HAL_RCC_AHB3_CLK_Disable_Clear      __HAL_RCC_AHB3_CLK_ENABLE
-#define __HAL_RCC_APB1_CLK_Disable_Clear      __HAL_RCC_APB1_CLK_ENABLE
-#define __HAL_RCC_APB2_CLK_Disable_Clear      __HAL_RCC_APB2_CLK_ENABLE
-#define __HAL_RCC_APB3_CLK_Disable_Clear      __HAL_RCC_APB3_CLK_ENABLE
-#define IS_RCC_MSIPLLModeSelection            IS_RCC_MSIPLLMODE_SELECT
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
-#else
-#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
-#endif
-#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
-#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
-
-#if defined (STM32F1)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
-
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
-
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
-
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
-
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
-                                                       (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
-                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#endif   /* STM32F1 */
-
-#define IS_ALARM                                  IS_RTC_ALARM
-#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
-#define IS_TAMPER                                 IS_RTC_TAMPER
-#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
-#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
-#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
-#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
-#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
-#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
-#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
-#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
-#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
-
-#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
-#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
-#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
-
-#define eMMC_HIGH_VOLTAGE_RANGE     EMMC_HIGH_VOLTAGE_RANGE
-#define eMMC_DUAL_VOLTAGE_RANGE     EMMC_DUAL_VOLTAGE_RANGE
-#define eMMC_LOW_VOLTAGE_RANGE      EMMC_LOW_VOLTAGE_RANGE
-
-#if defined(STM32F4) || defined(STM32F2)
-#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
-#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
-#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
-#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
-#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
-#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
-#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
-#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
-#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
-#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
-#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
-#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
-#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
-#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
-#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
-#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
-#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
-#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
-#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
-#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
-/* alias CMSIS */
-#define  SDMMC1_IRQn                SDIO_IRQn
-#define  SDMMC1_IRQHandler          SDIO_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
-#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
-#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
-#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
-#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
-#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
-#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
-#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
-#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
-#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
-#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
-#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
-#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
-#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
-#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
-#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
-#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
-#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
-#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
-#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
-/* alias CMSIS for compatibilities */
-#define  SDIO_IRQn                  SDMMC1_IRQn
-#define  SDIO_IRQHandler            SDMMC1_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
-#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
-#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
-#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
-#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
-#endif
-
-#if defined(STM32H7) || defined(STM32L5)
-#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
-#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
-#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
-#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
-#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
-
-#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
-#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
-
-#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
-#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
-#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
-#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
-#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
-#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
-#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
-#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
-#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
-#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
-#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
-#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
-#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
-
-#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
-
-#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
-#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
-#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
-#define __USART_ENABLE                  __HAL_USART_ENABLE
-#define __USART_DISABLE                 __HAL_USART_DISABLE
-
-#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
-#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
-#define USART_OVERSAMPLING_16               0x00000000U
-#define USART_OVERSAMPLING_8                USART_CR1_OVER8
-
-#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
-                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))
-#endif /* STM32F0 || STM32F3 || STM32F7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
-
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
-#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
-
-#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
-
-#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
-#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
-
-#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
-
-#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
-#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
-#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
-#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
-#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
-#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
-#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
-#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
-#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
-#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
-#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
-#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
-
-#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
-#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-
-#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
-#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
-#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_LTDC_LAYER LTDC_LAYER
-#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
-#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
-#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
-#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
-#define SAI_STREOMODE                     SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
-#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
-#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
-#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
-#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
-#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
-#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
-#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
-#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined(STM32H7)
-#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
-#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
-#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
-#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
-#endif /* STM32L4 || STM32F4 || STM32F7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32_HAL_LEGACY */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32_assert_template.h

@@ -1,57 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32_assert.h
-  * @author  MCD Application Team
-  * @brief   STM32 assert template file.
-  *          This file should be copied to the application folder and renamed
-  *          to stm32_assert.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_ASSERT_H
-#define __STM32_ASSERT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Includes ------------------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32_ASSERT_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h

@@ -1,796 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal.h
-  * @author  MCD Application Team
-  * @brief   This file contains all the functions prototypes for the HAL
-  *          module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32WLxx_HAL_H
-#define __STM32WLxx_HAL_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_conf.h"
-#include "stm32wlxx_ll_system.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup HAL HAL
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup HAL_Exported_Structures HAL Exported Structures
-  * @{
-  */
-
-/** @defgroup HAL_TICK_FREQ Tick Frequency
-  * @{
-  */
-typedef enum
-{
-  HAL_TICK_FREQ_10HZ         = 100U,
-  HAL_TICK_FREQ_100HZ        = 10U,
-  HAL_TICK_FREQ_1KHZ         = 1U,
-  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
-} HAL_TickFreqTypeDef;
-/**
-  * @}
-  */
-
-#if defined(DUAL_CORE)
-/** @defgroup HAL_SYSCFG_IM HAL SYSCFG Interrupt Mask
-  * @{
-  */
-/**
-  * @brief SYSCFG Interrupt Mask structure definition
-  */
-typedef struct
-{
-  uint32_t InterruptMask1;      /*!< The SYSCFG Interrupt Mask to be configured.
-                                     This parameter can be a combination of @ref SYSCFG_IM_GRP1 */
-  uint32_t InterruptMask2;      /*!< The SYSCFG Interrupt Mask to be configured.
-                                     This parameter can be a combination of @ref SYSCFG_IM_GRP2 */
-} SYSCFG_InterruptTypeDef;
-/**
-  * @}
-  */
-#endif
-
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup HAL_Exported_Constants HAL Exported Constants
-  * @{
-  */
-
-/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
-  * @{
-  */
-
-/** @defgroup SYSCFG_BootMode BOOT Mode
-  * @{
-  */
-#define SYSCFG_BOOT_MAINFLASH           LL_SYSCFG_REMAP_FLASH           /*!< Main Flash memory mapped at 0x00000000   */
-#define SYSCFG_BOOT_SYSTEMFLASH         LL_SYSCFG_REMAP_SYSTEMFLASH     /*!< System Flash memory mapped at 0x00000000 */
-#define SYSCFG_BOOT_SRAM                LL_SYSCFG_REMAP_SRAM            /*!< SRAM1 mapped at 0x00000000               */
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31)
-  * @{
-  */
-#define SYSCFG_SRAM2WRP_PAGE0           LL_SYSCFG_SRAM2WRP_PAGE0        /*!< SRAM2 Write protection page 0  */
-#define SYSCFG_SRAM2WRP_PAGE1           LL_SYSCFG_SRAM2WRP_PAGE1        /*!< SRAM2 Write protection page 1  */
-#define SYSCFG_SRAM2WRP_PAGE2           LL_SYSCFG_SRAM2WRP_PAGE2        /*!< SRAM2 Write protection page 2  */
-#define SYSCFG_SRAM2WRP_PAGE3           LL_SYSCFG_SRAM2WRP_PAGE3        /*!< SRAM2 Write protection page 3  */
-#define SYSCFG_SRAM2WRP_PAGE4           LL_SYSCFG_SRAM2WRP_PAGE4        /*!< SRAM2 Write protection page 4  */
-#define SYSCFG_SRAM2WRP_PAGE5           LL_SYSCFG_SRAM2WRP_PAGE5        /*!< SRAM2 Write protection page 5  */
-#define SYSCFG_SRAM2WRP_PAGE6           LL_SYSCFG_SRAM2WRP_PAGE6        /*!< SRAM2 Write protection page 6  */
-#define SYSCFG_SRAM2WRP_PAGE7           LL_SYSCFG_SRAM2WRP_PAGE7        /*!< SRAM2 Write protection page 7  */
-#define SYSCFG_SRAM2WRP_PAGE8           LL_SYSCFG_SRAM2WRP_PAGE8        /*!< SRAM2 Write protection page 8  */
-#define SYSCFG_SRAM2WRP_PAGE9           LL_SYSCFG_SRAM2WRP_PAGE9        /*!< SRAM2 Write protection page 9  */
-#define SYSCFG_SRAM2WRP_PAGE10          LL_SYSCFG_SRAM2WRP_PAGE10       /*!< SRAM2 Write protection page 10 */
-#define SYSCFG_SRAM2WRP_PAGE11          LL_SYSCFG_SRAM2WRP_PAGE11       /*!< SRAM2 Write protection page 11 */
-#define SYSCFG_SRAM2WRP_PAGE12          LL_SYSCFG_SRAM2WRP_PAGE12       /*!< SRAM2 Write protection page 12 */
-#define SYSCFG_SRAM2WRP_PAGE13          LL_SYSCFG_SRAM2WRP_PAGE13       /*!< SRAM2 Write protection page 13 */
-#define SYSCFG_SRAM2WRP_PAGE14          LL_SYSCFG_SRAM2WRP_PAGE14       /*!< SRAM2 Write protection page 14 */
-#define SYSCFG_SRAM2WRP_PAGE15          LL_SYSCFG_SRAM2WRP_PAGE15       /*!< SRAM2 Write protection page 15 */
-#define SYSCFG_SRAM2WRP_PAGE16          LL_SYSCFG_SRAM2WRP_PAGE16       /*!< SRAM2 Write protection page 16 */
-#define SYSCFG_SRAM2WRP_PAGE17          LL_SYSCFG_SRAM2WRP_PAGE17       /*!< SRAM2 Write protection page 17 */
-#define SYSCFG_SRAM2WRP_PAGE18          LL_SYSCFG_SRAM2WRP_PAGE18       /*!< SRAM2 Write protection page 18 */
-#define SYSCFG_SRAM2WRP_PAGE19          LL_SYSCFG_SRAM2WRP_PAGE19       /*!< SRAM2 Write protection page 19 */
-#define SYSCFG_SRAM2WRP_PAGE20          LL_SYSCFG_SRAM2WRP_PAGE20       /*!< SRAM2 Write protection page 20 */
-#define SYSCFG_SRAM2WRP_PAGE21          LL_SYSCFG_SRAM2WRP_PAGE21       /*!< SRAM2 Write protection page 21 */
-#define SYSCFG_SRAM2WRP_PAGE22          LL_SYSCFG_SRAM2WRP_PAGE22       /*!< SRAM2 Write protection page 22 */
-#define SYSCFG_SRAM2WRP_PAGE23          LL_SYSCFG_SRAM2WRP_PAGE23       /*!< SRAM2 Write protection page 23 */
-#define SYSCFG_SRAM2WRP_PAGE24          LL_SYSCFG_SRAM2WRP_PAGE24       /*!< SRAM2 Write protection page 24 */
-#define SYSCFG_SRAM2WRP_PAGE25          LL_SYSCFG_SRAM2WRP_PAGE25       /*!< SRAM2 Write protection page 25 */
-#define SYSCFG_SRAM2WRP_PAGE26          LL_SYSCFG_SRAM2WRP_PAGE26       /*!< SRAM2 Write protection page 26 */
-#define SYSCFG_SRAM2WRP_PAGE27          LL_SYSCFG_SRAM2WRP_PAGE27       /*!< SRAM2 Write protection page 27 */
-#define SYSCFG_SRAM2WRP_PAGE28          LL_SYSCFG_SRAM2WRP_PAGE28       /*!< SRAM2 Write protection page 28 */
-#define SYSCFG_SRAM2WRP_PAGE29          LL_SYSCFG_SRAM2WRP_PAGE29       /*!< SRAM2 Write protection page 29 */
-#define SYSCFG_SRAM2WRP_PAGE30          LL_SYSCFG_SRAM2WRP_PAGE30       /*!< SRAM2 Write protection page 30 */
-#define SYSCFG_SRAM2WRP_PAGE31          LL_SYSCFG_SRAM2WRP_PAGE31       /*!< SRAM2 Write protection page 31 */
-
-/**
-  * @}
-  */
-
-#if defined(VREFBUF)
-/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
-  * @{
-  */
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE0   LL_VREFBUF_VOLTAGE_SCALE0       /*!< Voltage reference scale 0 (VREF_OUT1) */
-#define SYSCFG_VREFBUF_VOLTAGE_SCALE1   LL_VREFBUF_VOLTAGE_SCALE1       /*!< Voltage reference scale 1 (VREF_OUT2) */
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
-  * @{
-  */
-#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE   0x00000000U             /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
-#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE    VREFBUF_CSR_HIZ         /*!< VREF_plus pin is high impedance */
-
-/**
-  * @}
-  */
-#endif /* VREFBUF */
-
-/** @defgroup SYSCFG_SRAM_flags_definition SRAM Flags
-  * @{
-  */
-
-#define SYSCFG_FLAG_SRAM2_PE            SYSCFG_CFGR2_SPF                /*!< SRAM2 parity error */
-#define SYSCFG_FLAG_SRAM_BUSY           SYSCFG_SCSR_SRAMBSY             /*!< SRAM1 or SRAM2 erase operation is ongoing */
-#define SYSCFG_FLAG_PKASRAM_BUSY        SYSCFG_SCSR_PKASRAMBSY          /*!< PKA SRAM busy by erase operation */
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
-  * @{
-  */
-
-/** @brief  Fast-mode Plus driving capability on a specific GPIO
-  */
-#define SYSCFG_FASTMODEPLUS_PB6         SYSCFG_CFGR1_I2C_PB6_FMP        /*!< Enable Fast-mode Plus on PB6 */
-#define SYSCFG_FASTMODEPLUS_PB7         SYSCFG_CFGR1_I2C_PB7_FMP        /*!< Enable Fast-mode Plus on PB7 */
-#define SYSCFG_FASTMODEPLUS_PB8         SYSCFG_CFGR1_I2C_PB8_FMP        /*!< Enable Fast-mode Plus on PB8 */
-#define SYSCFG_FASTMODEPLUS_PB9         SYSCFG_CFGR1_I2C_PB9_FMP        /*!< Enable Fast-mode Plus on PB9 */
-
-/**
- * @}
- */
-
-#if defined(DUAL_CORE)
-/** @defgroup SYSCFG_IM_GRP1 SYSCFG INTERRUPT MASK GROUP1
-  * @{
-  */
-
-#define HAL_SYSCFG_GRP1_RESERVED                0x00U                              /*!< Define user to differentiate Group1 to Group 2                */
-
-#if defined(CORE_CM0PLUS)
-/** @brief  Interrupt mask related to CPU2 NVIC
-  */
-#define HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS  (LL_C2_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS | HAL_SYSCFG_GRP1_RESERVED)  /*!< Enabling of interrupt from RTC TimeStamp, RTC Tampers
-                                                                                                                              and LSE Clock Security System to CPU2               */
-#define HAL_SYSCFG_GRP1_RTCALARM                (LL_C2_SYSCFG_GRP1_RTCALARM        | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC Alarms to CPU2                 */
-#define HAL_SYSCFG_GRP1_RTCSSRU                 (LL_C2_SYSCFG_GRP1_RTCSSRU         | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC SSRU to CPU2                   */
-#define HAL_SYSCFG_GRP1_RTCWKUP                 (LL_C2_SYSCFG_GRP1_RTCWKUP         | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC Wakeup to CPU2                 */
-#define HAL_SYSCFG_GRP1_RCC                     (LL_C2_SYSCFG_GRP1_RCC             | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RCC to CPU2                        */
-#define HAL_SYSCFG_GRP1_FLASH                   (LL_C2_SYSCFG_GRP1_FLASH           | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from FLASH to CPU2                      */
-#define HAL_SYSCFG_GRP1_PKA                     (LL_C2_SYSCFG_GRP1_PKA             | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from PKA to CPU2                        */
-#define HAL_SYSCFG_GRP1_AES                     (LL_C2_SYSCFG_GRP1_AES             | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from AES to CPU2                        */
-#define HAL_SYSCFG_GRP1_COMP                    (LL_C2_SYSCFG_GRP1_COMP            | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from Comparator to CPU2                 */
-#define HAL_SYSCFG_GRP1_ADC                     (LL_C2_SYSCFG_GRP1_ADC             | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from Analog Digital Converter to CPU2   */
-#define HAL_SYSCFG_GRP1_DAC                     (LL_C2_SYSCFG_GRP1_DAC             | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from Digital Analog Converter to CPU2   */
-
-#define HAL_SYSCFG_GRP1_EXTI0                   (LL_C2_SYSCFG_GRP1_EXTI0           | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 0 to CPU2  */
-#define HAL_SYSCFG_GRP1_EXTI1                   (LL_C2_SYSCFG_GRP1_EXTI1           | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 1 to CPU2  */
-#define HAL_SYSCFG_GRP1_EXTI2                   (LL_C2_SYSCFG_GRP1_EXTI2           | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 2 to CPU2  */
-#define HAL_SYSCFG_GRP1_EXTI3                   (LL_C2_SYSCFG_GRP1_EXTI3           | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 3 to CPU2  */
-#define HAL_SYSCFG_GRP1_EXTI4                   (LL_C2_SYSCFG_GRP1_EXTI4           | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 4 to CPU2  */
-#define HAL_SYSCFG_GRP1_EXTI5                   (LL_C2_SYSCFG_GRP1_EXTI5           | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 5 to CPU2  */
-#define HAL_SYSCFG_GRP1_EXTI6                   (LL_C2_SYSCFG_GRP1_EXTI6           | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 6 to CPU2  */
-#define HAL_SYSCFG_GRP1_EXTI7                   (LL_C2_SYSCFG_GRP1_EXTI7           | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 7 to CPU2  */
-#define HAL_SYSCFG_GRP1_EXTI8                   (LL_C2_SYSCFG_GRP1_EXTI8           | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 8 to CPU2  */
-#define HAL_SYSCFG_GRP1_EXTI9                   (LL_C2_SYSCFG_GRP1_EXTI9           | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 9 to CPU2  */
-#define HAL_SYSCFG_GRP1_EXTI10                  (LL_C2_SYSCFG_GRP1_EXTI10          | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 10 to CPU2 */
-#define HAL_SYSCFG_GRP1_EXTI11                  (LL_C2_SYSCFG_GRP1_EXTI11          | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 11 to CPU2 */
-#define HAL_SYSCFG_GRP1_EXTI12                  (LL_C2_SYSCFG_GRP1_EXTI12          | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 12 to CPU2 */
-#define HAL_SYSCFG_GRP1_EXTI13                  (LL_C2_SYSCFG_GRP1_EXTI13          | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 13 to CPU2 */
-#define HAL_SYSCFG_GRP1_EXTI14                  (LL_C2_SYSCFG_GRP1_EXTI14          | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 14 to CPU2 */
-#define HAL_SYSCFG_GRP1_EXTI15                  (LL_C2_SYSCFG_GRP1_EXTI15          | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 15 to CPU2 */
-
-#else
-
-/** @brief  Interrupt mask related to CPU1 NVIC
-  */
-#define HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS      (LL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTCSTAMPTAMPLSECSS to CPU1         */
-#define HAL_SYSCFG_GRP1_RTCSSRU                 (LL_SYSCFG_GRP1_RTCSSRU            | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from RTC SSRU to CPU1                   */
-#define HAL_SYSCFG_GRP1_EXTI5                   (LL_SYSCFG_GRP1_EXTI5              | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 5 to CPU1  */
-#define HAL_SYSCFG_GRP1_EXTI6                   (LL_SYSCFG_GRP1_EXTI6              | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 6 to CPU1  */
-#define HAL_SYSCFG_GRP1_EXTI7                   (LL_SYSCFG_GRP1_EXTI7              | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 7 to CPU1  */
-#define HAL_SYSCFG_GRP1_EXTI8                   (LL_SYSCFG_GRP1_EXTI8              | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 8 to CPU1  */
-#define HAL_SYSCFG_GRP1_EXTI9                   (LL_SYSCFG_GRP1_EXTI9              | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 9 to CPU1  */
-#define HAL_SYSCFG_GRP1_EXTI10                  (LL_SYSCFG_GRP1_EXTI10             | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 10 to CPU1 */
-#define HAL_SYSCFG_GRP1_EXTI11                  (LL_SYSCFG_GRP1_EXTI11             | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 11 to CPU1 */
-#define HAL_SYSCFG_GRP1_EXTI12                  (LL_SYSCFG_GRP1_EXTI12             | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 12 to CPU1 */
-#define HAL_SYSCFG_GRP1_EXTI13                  (LL_SYSCFG_GRP1_EXTI13             | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 13 to CPU1 */
-#define HAL_SYSCFG_GRP1_EXTI14                  (LL_SYSCFG_GRP1_EXTI14             | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 14 to CPU1 */
-#define HAL_SYSCFG_GRP1_EXTI15                  (LL_SYSCFG_GRP1_EXTI15             | HAL_SYSCFG_GRP1_RESERVED) /*!< Enabling of interrupt from External Interrupt Line 15 to CPU1 */
-
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_IM_GRP2 SYSCFG INTERRUPT MASK GROUP2
-  * @{
-  */
-
-#define HAL_SYSCFG_GRP2_RESERVED                0x80U                              /*!< Define user to differentiate Group1 to Group 2                */
-
-#if defined(CORE_CM0PLUS)
-/** @brief  Interrupt mask related to CPU2 NVIC
-  */
-#define HAL_SYSCFG_GRP2_DMA1CH1                 (LL_C2_SYSCFG_GRP2_DMA1CH1         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 1 to CPU2             */
-#define HAL_SYSCFG_GRP2_DMA1CH2                 (LL_C2_SYSCFG_GRP2_DMA1CH2         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 2 to CPU2             */
-#define HAL_SYSCFG_GRP2_DMA1CH3                 (LL_C2_SYSCFG_GRP2_DMA1CH3         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 3 to CPU2             */
-#define HAL_SYSCFG_GRP2_DMA1CH4                 (LL_C2_SYSCFG_GRP2_DMA1CH4         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 4 to CPU2             */
-#define HAL_SYSCFG_GRP2_DMA1CH5                 (LL_C2_SYSCFG_GRP2_DMA1CH5         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 5 to CPU2             */
-#define HAL_SYSCFG_GRP2_DMA1CH6                 (LL_C2_SYSCFG_GRP2_DMA1CH6         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 6 to CPU2             */
-#define HAL_SYSCFG_GRP2_DMA1CH7                 (LL_C2_SYSCFG_GRP2_DMA1CH7         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA1 Channel 7 to CPU2             */
-
-#define HAL_SYSCFG_GRP2_DMA2CH1                 (LL_C2_SYSCFG_GRP2_DMA2CH1         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 1 to CPU2             */
-#define HAL_SYSCFG_GRP2_DMA2CH2                 (LL_C2_SYSCFG_GRP2_DMA2CH2         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 2 to CPU2             */
-#define HAL_SYSCFG_GRP2_DMA2CH3                 (LL_C2_SYSCFG_GRP2_DMA2CH3         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 3 to CPU2             */
-#define HAL_SYSCFG_GRP2_DMA2CH4                 (LL_C2_SYSCFG_GRP2_DMA2CH4         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 4 to CPU2             */
-#define HAL_SYSCFG_GRP2_DMA2CH5                 (LL_C2_SYSCFG_GRP2_DMA2CH5         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 5 to CPU2             */
-#define HAL_SYSCFG_GRP2_DMA2CH6                 (LL_C2_SYSCFG_GRP2_DMA2CH6         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 6 to CPU2             */
-#define HAL_SYSCFG_GRP2_DMA2CH7                 (LL_C2_SYSCFG_GRP2_DMA2CH7         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMA2 Channel 7 to CPU2             */
-
-#define HAL_SYSCFG_GRP2_DMAMUX1                 (LL_C2_SYSCFG_GRP2_DMAMUX1         | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from DMAMUX1 to CPU2                    */
-
-#define HAL_SYSCFG_GRP2_PVM3                    (LL_C2_SYSCFG_GRP2_PVM3            | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU2 */
-#define HAL_SYSCFG_GRP2_PVD                     (LL_C2_SYSCFG_GRP2_PVD             | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Detector to CPU2     */
-
-#else
-
-/** @brief  Interrupt mask related to CPU1 NVIC
-  */
-#define HAL_SYSCFG_GRP2_PVM3                    (LL_SYSCFG_GRP2_PVM3               | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Monitoring 3 to CPU1 */
-#define HAL_SYSCFG_GRP2_PVD                     (LL_SYSCFG_GRP2_PVD                | HAL_SYSCFG_GRP2_RESERVED) /*!< Enabling of interrupt from Power Voltage Detector to CPU1     */
-
-#endif
-/**
-  * @}
-  */
-#endif /* DUAL_CORE */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup HAL_Exported_Macros HAL Exported Macros
-  * @{
-  */
-
-/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
-  * @{
-  */
-
-/** @brief  Freeze and Unfreeze Peripherals in Debug mode
-  */
-
-/** @defgroup DBGMCU_APBx_GRPx_STOP_IP DBGMCU CPU1 APBx GRPx STOP IP
-  * @{
-  */
-#if defined(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM2()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM2()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP)
-#endif
-
-#if defined(LL_DBGMCU_APB1_GRP1_RTC_STOP)
-#define __HAL_DBGMCU_FREEZE_RTC()               LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
-#define __HAL_DBGMCU_UNFREEZE_RTC()             LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP)
-#endif
-
-#if defined(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
-#define __HAL_DBGMCU_FREEZE_WWDG()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_WWDG()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP)
-#endif
-
-#if defined(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
-#define __HAL_DBGMCU_FREEZE_IWDG()              LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
-#define __HAL_DBGMCU_UNFREEZE_IWDG()            LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP)
-#endif
-
-#if defined(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()      LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()    LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP)
-#endif
-
-#if defined(LL_DBGMCU_APB1_GRP1_I2C2_STOP)
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()      LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()    LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C2_STOP)
-#endif
-
-#if defined(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
-#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()      LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
-#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()    LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP)
-#endif
-
-#if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
-#define __HAL_DBGMCU_FREEZE_LPTIM1()            LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_LPTIM1()          LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP)
-#endif
-
-#if defined(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
-#define __HAL_DBGMCU_FREEZE_LPTIM2()            LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
-#define __HAL_DBGMCU_UNFREEZE_LPTIM2()          LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP)
-#endif
-
-#if defined(LL_DBGMCU_APB1_GRP2_LPTIM3_STOP)
-#define __HAL_DBGMCU_FREEZE_LPTIM3()            LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM3_STOP)
-#define __HAL_DBGMCU_UNFREEZE_LPTIM3()          LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM3_STOP)
-#endif
-
-#if defined(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM1()              LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM1()            LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP)
-#endif
-
-#if defined(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM16()             LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM16()           LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP)
-#endif
-
-#if defined(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
-#define __HAL_DBGMCU_FREEZE_TIM17()             LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
-#define __HAL_DBGMCU_UNFREEZE_TIM17()           LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP)
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup DBGMCU_C2_APBx_GRPx_STOP_IP DBGMCU CPU2 APBx GRPx STOP IP
-  * @{
-  */
-#if defined(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
-#define __HAL_C2_DBGMCU_FREEZE_TIM2()           LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
-#define __HAL_C2_DBGMCU_UNFREEZE_TIM2()         LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP)
-#endif
-
-#if defined(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
-#define __HAL_C2_DBGMCU_FREEZE_RTC()            LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
-#define __HAL_C2_DBGMCU_UNFREEZE_RTC()          LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP)
-#endif
-
-#if defined(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
-#define __HAL_C2_DBGMCU_FREEZE_IWDG()           LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
-#define __HAL_C2_DBGMCU_UNFREEZE_IWDG()         LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP)
-#endif
-
-#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
-#define __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT()   LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
-#define __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP)
-#endif
-
-#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP)
-#define __HAL_C2_DBGMCU_FREEZE_I2C2_TIMEOUT()   LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP)
-#define __HAL_C2_DBGMCU_UNFREEZE_I2C2_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C2_STOP)
-#endif
-
-#if defined(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
-#define __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT()   LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
-#define __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP)
-#endif
-
-#if defined(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
-#define __HAL_C2_DBGMCU_FREEZE_LPTIM1()         LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
-#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM1()       LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP)
-#endif
-
-#if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
-#define __HAL_C2_DBGMCU_FREEZE_LPTIM2()         LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
-#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM2()       LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP)
-#endif
-
-#if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP)
-#define __HAL_C2_DBGMCU_FREEZE_LPTIM3()         LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP)
-#define __HAL_C2_DBGMCU_UNFREEZE_LPTIM3()       LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM3_STOP)
-#endif
-
-#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
-#define __HAL_C2_DBGMCU_FREEZE_TIM1()           LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
-#define __HAL_C2_DBGMCU_UNFREEZE_TIM1()         LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP)
-#endif
-
-#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
-#define __HAL_C2_DBGMCU_FREEZE_TIM16()          LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
-#define __HAL_C2_DBGMCU_UNFREEZE_TIM16()        LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP)
-#endif
-
-#if defined(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
-#define __HAL_C2_DBGMCU_FREEZE_TIM17()          LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
-#define __HAL_C2_DBGMCU_UNFREEZE_TIM17()        LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP)
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
-  * @{
-  */
-
-/** @brief  Main Flash memory mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FLASH()        LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH)
-
-/** @brief  System Flash memory mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()  LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SYSTEMFLASH)
-
-/** @brief  Embedded SRAM mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_SRAM()         LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM)
-
-/**
-  * @brief  Return the boot mode as configured by user.
-  * @retval The boot mode as configured by user. The returned value can be one
-  *         of the following values:
-  *           @arg @ref SYSCFG_BOOT_MAINFLASH
-  *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH
-  *           @arg @ref SYSCFG_BOOT_SRAM
-  */
-#define __HAL_SYSCFG_GET_BOOT_MODE()            LL_SYSCFG_GetRemapMemory()
-
-/** @brief  SRAM2 page 0 to 31 write protection enable macro
-  * @param  __SRAM2WRP__  This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP
-  * @note   Write protection can only be disabled by a system reset
-  */
-/* Legacy define */
-#define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE      __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
-#define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__)    do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
-                                                                LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__);\
-                                                            }while(0)
-
-/** @brief  SRAM2 page write protection unlock prior to erase
-  * @note   Writing a wrong key reactivates the write protection
-  */
-#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK()         LL_SYSCFG_UnlockSRAM2WRP()
-
-/** @brief  SRAM2 erase
-  * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM_BUSY) may be used to check end of erase
-  */
-#define __HAL_SYSCFG_SRAM2_ERASE()              LL_SYSCFG_EnableSRAM2Erase()
-
-/** @brief  SYSCFG Break ECC lock.
-  *         Enable and lock the connection of Flash ECC error connection to TIM1/16/17 Break input.
-  * @note   The selected configuration is locked and can be unlocked only by system reset.
-  */
-#define __HAL_SYSCFG_BREAK_ECC_LOCK()           LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_ECC)
-
-/** @brief  SYSCFG Break Cortex-M4 Lockup lock.
-  *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/16/17 Break input.
-  * @note   The selected configuration is locked and can be unlocked only by system reset.
-  */
-#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()        LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP)
-
-/** @brief  SYSCFG Break PVD lock.
-  *         Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
-  * @note   The selected configuration is locked and can be unlocked only by system reset.
-  */
-#define __HAL_SYSCFG_BREAK_PVD_LOCK()           LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD)
-
-/** @brief  SYSCFG Break SRAM2 parity lock.
-  *         Enable and lock the SRAM2 parity error signal connection to TIM1/16/17 Break input.
-  * @note   The selected configuration is locked and can be unlocked by system reset.
-  */
-#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK()   LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_SRAM2_PARITY)
-
-/** @brief  Check SYSCFG flag is set or not.
-  * @param  __FLAG__  specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg @ref SYSCFG_FLAG_SRAM2_PE      SRAM2 Parity Error Flag
-  *            @arg @ref SYSCFG_FLAG_SRAM_BUSY     SRAM2 Erase Ongoing
-  *            @arg @ref SYSCFG_FLAG_PKASRAM_BUSY  PKA SRAM Erase Ongoing
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SYSCFG_GET_FLAG(__FLAG__)         ((((((__FLAG__) == SYSCFG_FLAG_SRAM2_PE)? SYSCFG->CFGR2 : SYSCFG->SCSR) & (__FLAG__))!= 0) ? 1 : 0)
-
-/** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.
-  */
-#define __HAL_SYSCFG_CLEAR_FLAG()               LL_SYSCFG_ClearFlag_SP()
-
-/** @brief  Fast mode Plus driving capability enable/disable macros
-  * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO
-  */
-#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
-                                                                LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__);           \
-                                                               }while(0)
-
-#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \
-                                                                LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__);          \
-                                                               }while(0)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup HAL_Private_Macros HAL Private Macros
-  * @{
-  */
-
-/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
-  * @{
-  */
-
-#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)               (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
-
-#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)      (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
-                                                         ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
-
-#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)     (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
-                                                         ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
-
-#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)           (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
-
-#define IS_SYSCFG_FASTMODEPLUS(__PIN__)                 ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6)  == SYSCFG_FASTMODEPLUS_PB6)  || \
-                                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7)  == SYSCFG_FASTMODEPLUS_PB7)  || \
-                                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8)  == SYSCFG_FASTMODEPLUS_PB8)  || \
-                                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9)  == SYSCFG_FASTMODEPLUS_PB9))
-
-
-#if defined(DUAL_CORE)
-#if defined(CORE_CM0PLUS)
-#define IS_SYSCFG_IM_GRP1(__VALUE__)                    ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP1_RESERVED)                                                     && \
-                                                        ((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS)  == HAL_SYSCFG_GRP1_RTCSTAMP_RTCTAMP_LSECSS)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_RTCALARM               )  == HAL_SYSCFG_GRP1_RTCALARM               )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU                )  == HAL_SYSCFG_GRP1_RTCSSRU                )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_RTCWKUP                )  == HAL_SYSCFG_GRP1_RTCWKUP                )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_RCC                    )  == HAL_SYSCFG_GRP1_RCC                    )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_FLASH                  )  == HAL_SYSCFG_GRP1_FLASH                  )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_PKA                    )  == HAL_SYSCFG_GRP1_PKA                    )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_AES                    )  == HAL_SYSCFG_GRP1_AES                    )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_COMP                   )  == HAL_SYSCFG_GRP1_COMP                   )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_ADC                    )  == HAL_SYSCFG_GRP1_ADC                    )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_DAC                    )  == HAL_SYSCFG_GRP1_DAC                    )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI0                  )  == HAL_SYSCFG_GRP1_EXTI0                  )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI1                  )  == HAL_SYSCFG_GRP1_EXTI1                  )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI2                  )  == HAL_SYSCFG_GRP1_EXTI2                  )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI3                  )  == HAL_SYSCFG_GRP1_EXTI3                  )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI4                  )  == HAL_SYSCFG_GRP1_EXTI4                  )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5                  )  == HAL_SYSCFG_GRP1_EXTI5                  )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6                  )  == HAL_SYSCFG_GRP1_EXTI6                  )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7                  )  == HAL_SYSCFG_GRP1_EXTI7                  )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8                  )  == HAL_SYSCFG_GRP1_EXTI8                  )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9                  )  == HAL_SYSCFG_GRP1_EXTI9                  )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10                 )  == HAL_SYSCFG_GRP1_EXTI10                 )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11                 )  == HAL_SYSCFG_GRP1_EXTI11                 )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12                 )  == HAL_SYSCFG_GRP1_EXTI12                 )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13                 )  == HAL_SYSCFG_GRP1_EXTI13                 )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14                 )  == HAL_SYSCFG_GRP1_EXTI14                 )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15                 )  == HAL_SYSCFG_GRP1_EXTI15                 )))
-
-#define IS_SYSCFG_IM_GRP2(__VALUE__)                    ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP2_RESERVED)                    && \
-                                                        ((((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH1)  == HAL_SYSCFG_GRP2_DMA1CH1)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH2)  == HAL_SYSCFG_GRP2_DMA1CH2)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH3)  == HAL_SYSCFG_GRP2_DMA1CH3)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH4)  == HAL_SYSCFG_GRP2_DMA1CH4)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH5)  == HAL_SYSCFG_GRP2_DMA1CH5)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH6)  == HAL_SYSCFG_GRP2_DMA1CH6)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_DMA1CH7)  == HAL_SYSCFG_GRP2_DMA1CH7)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH1)  == HAL_SYSCFG_GRP2_DMA2CH1)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH2)  == HAL_SYSCFG_GRP2_DMA2CH2)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH3)  == HAL_SYSCFG_GRP2_DMA2CH3)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH4)  == HAL_SYSCFG_GRP2_DMA2CH4)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH5)  == HAL_SYSCFG_GRP2_DMA2CH5)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH6)  == HAL_SYSCFG_GRP2_DMA2CH6)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_DMA2CH7)  == HAL_SYSCFG_GRP2_DMA2CH7)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_DMAMUX1)  == HAL_SYSCFG_GRP2_DMAMUX1)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_PVM3   )  == HAL_SYSCFG_GRP2_PVM3   )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_PVD    )  == HAL_SYSCFG_GRP2_PVD    )))
-
-#else /* !CORE_CM0PLUS */
-
-#define IS_SYSCFG_IM_GRP1(__VALUE__)                    ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP1_RESERVED)                                          && \
-                                                        ((((__VALUE__) & HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS)  == HAL_SYSCFG_GRP1_RTCSTAMPTAMPLSECSS)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_RTCSSRU           )  == HAL_SYSCFG_GRP1_RTCSSRU           )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI5             )  == HAL_SYSCFG_GRP1_EXTI5             )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI6             )  == HAL_SYSCFG_GRP1_EXTI6             )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI7             )  == HAL_SYSCFG_GRP1_EXTI7             )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI8             )  == HAL_SYSCFG_GRP1_EXTI8             )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI9             )  == HAL_SYSCFG_GRP1_EXTI9             )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI10            )  == HAL_SYSCFG_GRP1_EXTI10            )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI11            )  == HAL_SYSCFG_GRP1_EXTI11            )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI12            )  == HAL_SYSCFG_GRP1_EXTI12            )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI13            )  == HAL_SYSCFG_GRP1_EXTI13            )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI14            )  == HAL_SYSCFG_GRP1_EXTI14            )  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP1_EXTI15            )  == HAL_SYSCFG_GRP1_EXTI15            )))
-
-#define IS_SYSCFG_IM_GRP2(__VALUE__)                    ((((__VALUE__) & 0x80U) == HAL_SYSCFG_GRP2_RESERVED)              && \
-                                                        ((((__VALUE__) & HAL_SYSCFG_GRP2_PVM3)  == HAL_SYSCFG_GRP2_PVM3)  || \
-                                                         (((__VALUE__) & HAL_SYSCFG_GRP2_PVD )  == HAL_SYSCFG_GRP2_PVD )))
-
-#endif /* CORE_CM0PLUS */
-#endif /* DUAL_CORE */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Private_Macros HAL Private Macros
-  * @{
-  */
-#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
-                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
-                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Functions HAL Exported Functions
-  * @{
-  */
-
-/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions
-  * @{
-  */
-
-/* Initialization and Configuration functions  ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void HAL_MspInit(void);
-void HAL_MspDeInit(void);
-
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
-
-/**
-  * @}
-  */
-
-/* Exported variables ---------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Variables
-  * @{
-  */
-extern __IO uint32_t uwTick;
-extern uint32_t uwTickPrio;
-extern HAL_TickFreqTypeDef uwTickFreq;
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(uint32_t Delay);
-uint32_t HAL_GetTick(void);
-uint32_t HAL_GetTickPrio(void);
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
-HAL_TickFreqTypeDef HAL_GetTickFreq(void);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-uint32_t HAL_GetUIDw0(void);
-uint32_t HAL_GetUIDw1(void);
-uint32_t HAL_GetUIDw2(void);
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
-  * @{
-  */
-
-/* DBGMCU Peripheral Control functions  *****************************************/
-void HAL_DBGMCU_EnableDBGSleepMode(void);
-void HAL_DBGMCU_DisableDBGSleepMode(void);
-void HAL_DBGMCU_EnableDBGStopMode(void);
-void HAL_DBGMCU_DisableDBGStopMode(void);
-void HAL_DBGMCU_EnableDBGStandbyMode(void);
-void HAL_DBGMCU_DisableDBGStandbyMode(void);
-/**
-  * @}
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group4 HAL System Configuration functions
-  * @{
-  */
-
-/* SYSCFG Control functions  ****************************************************/
-void HAL_SYSCFG_SRAM2Erase(void);
-
-void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
-void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
-void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
-HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
-void HAL_SYSCFG_DisableVREFBUF(void);
-
-void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
-void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
-
-#if defined(DUAL_CORE)
-void HAL_SYSCFG_EnableIT(SYSCFG_InterruptTypeDef *Interrupt);
-void HAL_SYSCFG_DisableIT(SYSCFG_InterruptTypeDef *Interrupt);
-#endif
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32WLxx_HAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h

@@ -1,1716 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_adc.h
-  * @author  MCD Application Team
-  * @brief   Header file of ADC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_ADC_H
-#define STM32WLxx_HAL_ADC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/* Include low level driver */
-#include "stm32wlxx_ll_adc.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADC_Exported_Types ADC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  ADC group regular oversampling structure definition
-  */
-typedef struct
-{
-  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
-                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
-
-  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
-                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
-
-  uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
-                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
-
-} ADC_OversamplingTypeDef;
-
-/**
-  * @brief  Structure definition of ADC instance and ADC group regular.
-  * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
-  *            ScanConvMode, EOCSelection, LowPowerAutoWait.
-  *          - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
-  *            ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
-  * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled
-  *          - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular.
-  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
-  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter
-  *         (which fulfills the ADC state condition) on the fly).
-  */
-typedef struct
-{
-  uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
-                                       This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
-                                       Note: The ADC clock configuration is common to all ADC instances.
-                                       Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
-                                             if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
-                                             must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
-                                       Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
-                                       Note: This parameter can be modified only if all ADC instances are disabled. */
-
-  uint32_t Resolution;            /*!< Configure the ADC resolution.
-                                       This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
-
-  uint32_t DataAlign;             /*!< Specify ADC data alignment in conversion data register (right or left).
-                                       Refer to reference manual for alignments formats versus resolutions.
-                                       This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
-
-  uint32_t ScanConvMode;          /*!< Configure the sequencer of ADC group regular.
-                                       On this STM32 series, ADC group regular sequencer both modes "fully configurable" or "not fully configurable" are
-                                       available:
-                                        - sequencer configured to fully configurable:
-                                          sequencer length and each rank affectation to a channel are configurable.
-                                           - Sequence length: Set number of ranks in the scan sequence.
-                                           - Sequence direction: Unless specified in parameters, sequencer
-                                             scan direction is forward (from rank 1 to rank n).
-                                        - sequencer configured to not fully configurable:
-                                          sequencer length and each rank affectation to a channel are fixed by channel HW number.
-                                           - Sequence length: Number of ranks in the scan sequence is
-                                             defined by number of channels set in the sequence,
-                                             rank of each channel is fixed by channel HW number.
-                                             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
-                                           - Sequence direction: Unless specified in parameters, sequencer
-                                             scan direction is forward (from lowest channel number to
-                                             highest channel number).
-                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
-                                       Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices):
-                                       If only 1 channel is set: Conversion is performed in single mode.
-                                       If several channels are set:  Conversions are performed in sequence mode.
-                                       This parameter can be a value of @ref ADC_Scan_mode */
-
-  uint32_t EOCSelection;          /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
-                                       This parameter can be a value of @ref ADC_EOCSelection. */
-
-  FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
-                                       conversion (for ADC group regular) has been retrieved by user software,
-                                       using function HAL_ADC_GetValue().
-                                       This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
-                                       for low frequency applications.
-                                       This parameter can be set to ENABLE or DISABLE.
-                                       Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
-                                             Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
-                                             Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
-                                             use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */
-
-  FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
-                                       This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
-                                       This parameter can be set to ENABLE or DISABLE. */
-
-  FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
-                                       after the first ADC conversion start trigger occurred (software start or external trigger).
-                                       This parameter can be set to ENABLE or DISABLE. */
-
-  uint32_t NbrOfConversion;       /*!< Specify the number of ranks that will be converted within the regular group sequencer.
-                                       This parameter is dependent on ScanConvMode:
-                                        - sequencer configured to fully configurable:
-                                          Number of ranks in the scan sequence is configurable using this parameter.
-                                          Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
-                                                Afterwards, when all needed sequencer ranks are set, parameter 'NbrOfConversion' can be updated without modifying configuration of sequencer ranks
-                                                (sequencer ranks above 'NbrOfConversion' are discarded).
-                                        - sequencer configured to not fully configurable:
-                                          Number of ranks in the scan sequence is defined by number of channels set in the sequence. This parameter is discarded.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8.
-                                       Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
-
-  FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
-                                       (main sequence subdivided in successive parts).
-                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
-                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
-                                       This parameter can be set to ENABLE or DISABLE.
-                                       Note: On this STM32 series, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */
-
-  uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion start.
-                                       If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
-                                       This parameter can be a value of @ref ADC_regular_external_trigger_source.
-                                       Caution: external trigger source is common to all ADC instances. */
-
-  uint32_t ExternalTrigConvEdge;  /*!< Select the external event edge used to trigger ADC group regular conversion start.
-                                       If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
-                                       This parameter can be a value of @ref ADC_regular_external_trigger_edge */
-
-  FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
-                                       or in continuous mode (DMA transfer unlimited, whatever number of conversions).
-                                       This parameter can be set to ENABLE or DISABLE.
-                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
-
-  uint32_t Overrun;               /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
-                                       This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
-                                       Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
-                                       end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
-                                       HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
-                                       Note: Error reporting with respect to the conversion mode:
-                                             - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
-                                               overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
-                                             - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
-
-  uint32_t SamplingTimeCommon1;   /*!< Set sampling time common to a group of channels.
-                                       Unit: ADC clock cycles
-                                       Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
-                                       Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
-                                       This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
-                                       Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
-                                             sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
-                                             Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
-
-  uint32_t SamplingTimeCommon2;   /*!< Set sampling time common to a group of channels, second common setting possible.
-                                       Unit: ADC clock cycles
-                                       Conversion time is the addition of sampling time and processing time (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
-                                       Note: On this STM32 family, two different sampling time settings are available, each channel can use one of these two settings. On some other STM32 devices, this parameter in channel wise and is located into ADC channel initialization structure.
-                                       This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
-                                       Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
-                                             sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
-                                             Refer to device datasheet for timings values, parameters TS_vrefint, TS_vbat, TS_temp (values rough order: few tens of microseconds). */
-
-  FunctionalState OversamplingMode;       /*!< Specify whether the oversampling feature is enabled or disabled.
-                                               This parameter can be set to ENABLE or DISABLE.
-                                               Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
-
-  ADC_OversamplingTypeDef Oversampling;   /*!< Specify the Oversampling parameters.
-                                               Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
-
-  uint32_t TriggerFrequencyMode;  /*!< Set ADC trigger frequency mode.
-                                       This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ.
-                                       Note: ADC trigger frequency mode must be set to low frequency when
-                                             a duration is exceeded before ADC conversion start trigger event
-                                             (between ADC enable and ADC conversion start trigger event
-                                             or between two ADC conversion start trigger event).
-                                             Duration value: Refer to device datasheet, parameter "tIdle".
-                                       Note: When ADC trigger frequency mode is set to low frequency,
-                                             some rearm cycles are inserted before performing ADC conversion
-                                             start, inducing a delay of 2 ADC clock cycles. */
-
-} ADC_InitTypeDef;
-
-/**
-  * @brief  Structure definition of ADC channel for regular group
-  * @note   The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled or enabled without conversion on going on regular group.
-  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
-  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
-  *         on the fly).
-  */
-typedef struct
-{
-  uint32_t Channel;                /*!< Specify the channel to configure into ADC regular group.
-                                        This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
-                                        Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
-
-  uint32_t Rank;                   /*!< Add or remove the channel from ADC regular group sequencer and specify its conversion rank.
-                                        This parameter is dependent on ScanConvMode:
-                                        - sequencer configured to fully configurable:
-                                          Channels ordering into each rank of scan sequence:
-                                          whatever channel can be placed into whatever rank.
-                                        - sequencer configured to not fully configurable:
-                                          rank of each channel is fixed by channel HW number.
-                                          (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
-                                          Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
-                                        This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */
-
-  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
-                                        Unit: ADC clock cycles
-                                        Conversion time is the addition of sampling time and processing time
-                                        (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
-                                        This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON
-                                        Note: On this STM32 family, two different sampling time settings are available (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), each channel can use one of these two settings.
-
-                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
-                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
-                                              Refer to device datasheet for timings values. */
-
-} ADC_ChannelConfTypeDef;
-
-/**
-  * @brief  Structure definition of ADC analog watchdog
-  * @note   The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular.
-  *          - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular.
-  */
-typedef struct
-{
-  uint32_t WatchdogNumber;    /*!< Select which ADC analog watchdog is monitoring the selected channel.
-                                   For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
-                                   For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
-                                   This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
-
-  uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all/none channels.
-                                   For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC group regular.
-                                   For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure.
-                                   This parameter can be a value of @ref ADC_analog_watchdog_mode. */
-
-  uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.
-                                   For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
-                                   For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
-                                   This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
-
-  FunctionalState ITMode;     /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
-                                   This parameter can be set to ENABLE or DISABLE */
-
-  uint32_t HighThreshold;     /*!< Configure the ADC analog watchdog High threshold value.
-                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
-                                   between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
-                                   Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
-                                         the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
-                                   Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
-                                         impacted: the comparison of analog watchdog thresholds is done on
-                                         oversampling final computation (after ratio and shift application):
-                                         ADC data register bitfield [15:4] (12 most significant bits). */
-
-  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value.
-                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
-                                   between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
-                                   Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
-                                         the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
-                                   Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
-                                         impacted: the comparison of analog watchdog thresholds is done on
-                                         oversampling final computation (after ratio and shift application):
-                                         ADC data register bitfield [15:4] (12 most significant bits). */
-} ADC_AnalogWDGConfTypeDef;
-
-/** @defgroup ADC_States ADC States
-  * @{
-  */
-
-/**
-  * @brief  HAL ADC state machine: ADC states definition (bitfields)
-  * @note   ADC state machine is managed by bitfields, state must be compared
-  *         with bit by bit.
-  *         For example:
-  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
-  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
-  */
-/* States of ADC global scope */
-#define HAL_ADC_STATE_RESET             (0x00000000UL)   /*!< ADC not yet initialized or disabled */
-#define HAL_ADC_STATE_READY             (0x00000001UL)   /*!< ADC peripheral ready for use */
-#define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002UL)   /*!< ADC is busy due to an internal process (initialization, calibration) */
-#define HAL_ADC_STATE_TIMEOUT           (0x00000004UL)   /*!< TimeOut occurrence */
-
-/* States of ADC errors */
-#define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010UL)   /*!< Internal error occurrence */
-#define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020UL)   /*!< Configuration error occurrence */
-#define HAL_ADC_STATE_ERROR_DMA         (0x00000040UL)   /*!< DMA error occurrence */
-
-/* States of ADC group regular */
-#define HAL_ADC_STATE_REG_BUSY          (0x00000100UL)   /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
-                                                              external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
-#define HAL_ADC_STATE_REG_EOC           (0x00000200UL)   /*!< Conversion data available on group regular */
-#define HAL_ADC_STATE_REG_OVR           (0x00000400UL)   /*!< Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP         (0x00000800UL)   /*!< Not available on this STM32 series: End Of Sampling flag raised  */
-
-/* States of ADC group injected */
-#define HAL_ADC_STATE_INJ_BUSY          (0x00001000UL)  /*!< Not available on this STM32 series: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
-                                                             external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available))*/
-#define HAL_ADC_STATE_INJ_EOC           (0x00002000UL)  /*!< Not available on this STM32 series: Conversion data available on group injected */
-#define HAL_ADC_STATE_INJ_JQOVF         (0x00004000UL)  /*!< Not available on this STM32 series: Injected queue overflow occurrence */
-
-/* States of ADC analog watchdogs */
-#define HAL_ADC_STATE_AWD1              (0x00010000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 1 */
-#define HAL_ADC_STATE_AWD2              (0x00020000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 2 */
-#define HAL_ADC_STATE_AWD3              (0x00040000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 3 */
-
-/* States of ADC multi-mode */
-#define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000UL)   /*!< Not available on this STM32 series: ADC in multimode slave state, controlled by another ADC master (when feature available) */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  ADC handle Structure definition
-  */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-typedef struct __ADC_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-{
-  ADC_TypeDef                   *Instance;              /*!< Register base address */
-  ADC_InitTypeDef               Init;                   /*!< ADC initialization parameters and regular conversions setting */
-  DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
-  HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
-  __IO uint32_t                 State;                  /*!< ADC communication state (bitmap of ADC states) */
-  __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
-
-  uint32_t                      ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks setting, used in mode "fully configurable" (refer to parameter 'ScanConvMode') */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
-  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */
-  void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
-  void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
-  void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 2 callback */
-  void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 3 callback */
-  void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc);         /*!< ADC end of sampling callback */
-  void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
-  void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-} ADC_HandleTypeDef;
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL ADC Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
-  HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
-  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
-  HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
-  HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID   = 0x06U,  /*!< ADC analog watchdog 2 callback ID */
-  HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID   = 0x07U,  /*!< ADC analog watchdog 3 callback ID */
-  HAL_ADC_END_OF_SAMPLING_CB_ID         = 0x08U,  /*!< ADC end of sampling callback ID */
-  HAL_ADC_MSPINIT_CB_ID                 = 0x09U,  /*!< ADC Msp Init callback ID          */
-  HAL_ADC_MSPDEINIT_CB_ID               = 0x0AU   /*!< ADC Msp DeInit callback ID        */
-} HAL_ADC_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL ADC Callback pointer definition
-  */
-typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
-
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants ADC Exported Constants
-  * @{
-  */
-
-/** @defgroup ADC_Error_Code ADC Error Code
-  * @{
-  */
-#define HAL_ADC_ERROR_NONE              (0x00U)   /*!< No error                                    */
-#define HAL_ADC_ERROR_INTERNAL          (0x01U)   /*!< ADC peripheral internal error (problem of clocking,
-                                                       enable/disable, erroneous state, ...)       */
-#define HAL_ADC_ERROR_OVR               (0x02U)   /*!< Overrun error                               */
-#define HAL_ADC_ERROR_DMA               (0x04U)   /*!< DMA transfer error                          */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-#define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
-  * @{
-  */
-#define ADC_CLOCK_SYNC_PCLK_DIV1           (LL_ADC_CLOCK_SYNC_PCLK_DIV1)  /*!< ADC synchronous clock derived from AHB clock without prescaler. This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) */
-#define ADC_CLOCK_SYNC_PCLK_DIV2           (LL_ADC_CLOCK_SYNC_PCLK_DIV2)  /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
-#define ADC_CLOCK_SYNC_PCLK_DIV4           (LL_ADC_CLOCK_SYNC_PCLK_DIV4)  /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
-
-#define ADC_CLOCK_ASYNC_DIV1               (LL_ADC_CLOCK_ASYNC_DIV1)      /*!< ADC asynchronous clock without prescaler */
-#define ADC_CLOCK_ASYNC_DIV2               (LL_ADC_CLOCK_ASYNC_DIV2)      /*!< ADC asynchronous clock with prescaler division by 2   */
-#define ADC_CLOCK_ASYNC_DIV4               (LL_ADC_CLOCK_ASYNC_DIV4)      /*!< ADC asynchronous clock with prescaler division by 4   */
-#define ADC_CLOCK_ASYNC_DIV6               (LL_ADC_CLOCK_ASYNC_DIV6)      /*!< ADC asynchronous clock with prescaler division by 6   */
-#define ADC_CLOCK_ASYNC_DIV8               (LL_ADC_CLOCK_ASYNC_DIV8)      /*!< ADC asynchronous clock with prescaler division by 8   */
-#define ADC_CLOCK_ASYNC_DIV10              (LL_ADC_CLOCK_ASYNC_DIV10)     /*!< ADC asynchronous clock with prescaler division by 10  */
-#define ADC_CLOCK_ASYNC_DIV12              (LL_ADC_CLOCK_ASYNC_DIV12)     /*!< ADC asynchronous clock with prescaler division by 12  */
-#define ADC_CLOCK_ASYNC_DIV16              (LL_ADC_CLOCK_ASYNC_DIV16)     /*!< ADC asynchronous clock with prescaler division by 16  */
-#define ADC_CLOCK_ASYNC_DIV32              (LL_ADC_CLOCK_ASYNC_DIV32)     /*!< ADC asynchronous clock with prescaler division by 32  */
-#define ADC_CLOCK_ASYNC_DIV64              (LL_ADC_CLOCK_ASYNC_DIV64)     /*!< ADC asynchronous clock with prescaler division by 64  */
-#define ADC_CLOCK_ASYNC_DIV128             (LL_ADC_CLOCK_ASYNC_DIV128)    /*!< ADC asynchronous clock with prescaler division by 128 */
-#define ADC_CLOCK_ASYNC_DIV256             (LL_ADC_CLOCK_ASYNC_DIV256)    /*!< ADC asynchronous clock with prescaler division by 256 */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_HAL_EC_RESOLUTION  ADC instance - Resolution
-  * @{
-  */
-#define ADC_RESOLUTION_12B                 (LL_ADC_RESOLUTION_12B)  /*!< ADC resolution 12 bits */
-#define ADC_RESOLUTION_10B                 (LL_ADC_RESOLUTION_10B)  /*!< ADC resolution 10 bits */
-#define ADC_RESOLUTION_8B                  (LL_ADC_RESOLUTION_8B)   /*!< ADC resolution  8 bits */
-#define ADC_RESOLUTION_6B                  (LL_ADC_RESOLUTION_6B)   /*!< ADC resolution  6 bits */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
-  * @{
-  */
-#define ADC_DATAALIGN_RIGHT                (LL_ADC_DATA_ALIGN_RIGHT)      /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
-#define ADC_DATAALIGN_LEFT                 (LL_ADC_DATA_ALIGN_LEFT)       /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Scan_mode ADC sequencer scan mode
-  * @{
-  */
-/* Note: On this STM32 family, ADC group regular sequencer both modes         */
-/*       "fully configurable" or "not fully configurable" are                 */
-/*       available.                                                           */
-/*       Scan mode values must be compatible with other STM32 devices having  */
-/*       a configurable sequencer.                                            */
-/*       Scan direction setting values are defined by taking in account       */
-/*       already defined values for other STM32 devices:                      */
-/*         ADC_SCAN_DISABLE         (0x00000000UL)                            */
-/*         ADC_SCAN_ENABLE          (0x00000001UL)                            */
-/*       Sequencer fully configurable with only rank 1 enabled is considered  */
-/*       as default setting equivalent to scan enable.                        */
-/*       In case of migration from another STM32 device, the user will be     */
-/*       warned of change of setting choices with assert check.               */
-#define ADC_SCAN_DISABLE                  (0x00000000UL)                               /*!< Sequencer set to fully configurable: only the rank 1 is enabled (no scan sequence on several ranks) */
-#define ADC_SCAN_ENABLE                   (ADC_CFGR1_CHSELRMOD)                        /*!< Sequencer set to fully configurable: sequencer length and each rank affectation to a channel are configurable. */
-
-#define ADC_SCAN_SEQ_FIXED                (ADC_SCAN_SEQ_FIXED_INT)                     /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */
-#define ADC_SCAN_SEQ_FIXED_BACKWARD       (ADC_SCAN_SEQ_FIXED_INT | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */
-
-#define ADC_SCAN_DIRECTION_FORWARD        (ADC_SCAN_SEQ_FIXED)                   /* For compatibility with other STM32 devices */
-#define ADC_SCAN_DIRECTION_BACKWARD       (ADC_SCAN_SEQ_FIXED_BACKWARD)          /* For compatibility with other STM32 devices */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
-  * @{
-  */
-/* ADC group regular trigger sources for all ADC instances */
-#define ADC_SOFTWARE_START            (LL_ADC_REG_TRIG_SOFTWARE)                 /*!< ADC group regular conversion trigger internal: SW start. */
-#define ADC_EXTERNALTRIG_T1_TRGO2     (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)           /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T1_CC4       (LL_ADC_REG_TRIG_EXT_TIM1_CH4)             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T2_TRGO      (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T2_CC4       (LL_ADC_REG_TRIG_EXT_TIM2_CH4)             /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define ADC_EXTERNALTRIG_T2_CC3       (LL_ADC_REG_TRIG_EXT_TIM2_CH3)             /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
-#define ADC_EXTERNALTRIG_EXT_IT11     (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)          /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
-  * @{
-  */
-#define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000UL)                      /*!< Regular conversions hardware trigger detection disabled */
-#define ADC_EXTERNALTRIGCONVEDGE_RISING         (LL_ADC_REG_TRIG_EXT_RISING)        /*!< ADC group regular conversion trigger polarity set to rising edge */
-#define ADC_EXTERNALTRIGCONVEDGE_FALLING        (LL_ADC_REG_TRIG_EXT_FALLING)       /*!< ADC group regular conversion trigger polarity set to falling edge */
-#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
-  * @{
-  */
-#define ADC_EOC_SINGLE_CONV         (ADC_ISR_EOC)                 /*!< End of unitary conversion flag  */
-#define ADC_EOC_SEQ_CONV            (ADC_ISR_EOS)                 /*!< End of sequence conversions flag    */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
-  * @{
-  */
-#define ADC_OVR_DATA_PRESERVED             (LL_ADC_REG_OVR_DATA_PRESERVED)    /*!< ADC group regular behavior in case of overrun: data preserved */
-#define ADC_OVR_DATA_OVERWRITTEN           (LL_ADC_REG_OVR_DATA_OVERWRITTEN)  /*!< ADC group regular behavior in case of overrun: data overwritten */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
-  * @{
-  */
-#define ADC_RANK_CHANNEL_NUMBER            (0x00000001U)  /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
-#define ADC_RANK_NONE                      (0x00000002U)  /*!< Setting relevant if parameter "ScanConvMode" is set to sequencer not fully configurable: Disable the selected rank (selected channel) from sequencer */
-
-#define ADC_REGULAR_RANK_1                 (LL_ADC_REG_RANK_1)  /*!< ADC group regular sequencer rank 1 */
-#define ADC_REGULAR_RANK_2                 (LL_ADC_REG_RANK_2)  /*!< ADC group regular sequencer rank 2 */
-#define ADC_REGULAR_RANK_3                 (LL_ADC_REG_RANK_3)  /*!< ADC group regular sequencer rank 3 */
-#define ADC_REGULAR_RANK_4                 (LL_ADC_REG_RANK_4)  /*!< ADC group regular sequencer rank 4 */
-#define ADC_REGULAR_RANK_5                 (LL_ADC_REG_RANK_5)  /*!< ADC group regular sequencer rank 5 */
-#define ADC_REGULAR_RANK_6                 (LL_ADC_REG_RANK_6)  /*!< ADC group regular sequencer rank 6 */
-#define ADC_REGULAR_RANK_7                 (LL_ADC_REG_RANK_7)  /*!< ADC group regular sequencer rank 7 */
-#define ADC_REGULAR_RANK_8                 (LL_ADC_REG_RANK_8)  /*!< ADC group regular sequencer rank 8 */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON  ADC instance - Sampling time common to a group of channels
-  * @{
-  */
-#define ADC_SAMPLINGTIME_COMMON_1          (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of channels: sampling time nb 1 */
-#define ADC_SAMPLINGTIME_COMMON_2          (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of channels: sampling time nb 2 */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
-  * @{
-  */
-#define ADC_SAMPLETIME_1CYCLE_5            (LL_ADC_SAMPLINGTIME_1CYCLE_5)     /*!< Sampling time 1.5 ADC clock cycle */
-#define ADC_SAMPLETIME_3CYCLES_5           (LL_ADC_SAMPLINGTIME_3CYCLES_5)    /*!< Sampling time 3.5 ADC clock cycles */
-#define ADC_SAMPLETIME_7CYCLES_5           (LL_ADC_SAMPLINGTIME_7CYCLES_5)    /*!< Sampling time 7.5 ADC clock cycles */
-#define ADC_SAMPLETIME_12CYCLES_5          (LL_ADC_SAMPLINGTIME_12CYCLES_5)   /*!< Sampling time 12.5 ADC clock cycles */
-#define ADC_SAMPLETIME_19CYCLES_5          (LL_ADC_SAMPLINGTIME_19CYCLES_5)   /*!< Sampling time 19.5 ADC clock cycles */
-#define ADC_SAMPLETIME_39CYCLES_5          (LL_ADC_SAMPLINGTIME_39CYCLES_5)   /*!< Sampling time 39.5 ADC clock cycles */
-#define ADC_SAMPLETIME_79CYCLES_5          (LL_ADC_SAMPLINGTIME_79CYCLES_5)   /*!< Sampling time 79.5 ADC clock cycles */
-#define ADC_SAMPLETIME_160CYCLES_5         (LL_ADC_SAMPLINGTIME_160CYCLES_5)  /*!< Sampling time 160.5 ADC clock cycles */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_HAL_EC_CHANNEL  ADC instance - Channel number
-  * @{
-  */
-#define ADC_CHANNEL_0                      (LL_ADC_CHANNEL_0)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */
-#define ADC_CHANNEL_1                      (LL_ADC_CHANNEL_1)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */
-#define ADC_CHANNEL_2                      (LL_ADC_CHANNEL_2)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */
-#define ADC_CHANNEL_3                      (LL_ADC_CHANNEL_3)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */
-#define ADC_CHANNEL_4                      (LL_ADC_CHANNEL_4)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */
-#define ADC_CHANNEL_5                      (LL_ADC_CHANNEL_5)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */
-#define ADC_CHANNEL_6                      (LL_ADC_CHANNEL_6)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */
-#define ADC_CHANNEL_7                      (LL_ADC_CHANNEL_7)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */
-#define ADC_CHANNEL_8                      (LL_ADC_CHANNEL_8)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */
-#define ADC_CHANNEL_9                      (LL_ADC_CHANNEL_9)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */
-#define ADC_CHANNEL_10                     (LL_ADC_CHANNEL_10)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
-#define ADC_CHANNEL_11                     (LL_ADC_CHANNEL_11)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
-#define ADC_CHANNEL_12                     (LL_ADC_CHANNEL_12)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
-#define ADC_CHANNEL_13                     (LL_ADC_CHANNEL_13)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
-#define ADC_CHANNEL_14                     (LL_ADC_CHANNEL_14)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
-#define ADC_CHANNEL_15                     (LL_ADC_CHANNEL_15)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
-#define ADC_CHANNEL_16                     (LL_ADC_CHANNEL_16)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
-#define ADC_CHANNEL_17                     (LL_ADC_CHANNEL_17)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
-#define ADC_CHANNEL_VREFINT                (LL_ADC_CHANNEL_VREFINT)         /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */
-#define ADC_CHANNEL_TEMPSENSOR             (LL_ADC_CHANNEL_TEMPSENSOR)      /*!< ADC internal channel connected to Temperature sensor. */
-#define ADC_CHANNEL_VBAT                   (LL_ADC_CHANNEL_VBAT)            /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */
-#define ADC_CHANNEL_DACCH1                 (LL_ADC_CHANNEL_DACCH1)          /*!< ADC internal channel connected to DAC channel 1. */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
-  * @{
-  */
-#define ADC_ANALOGWATCHDOG_1               (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
-#define ADC_ANALOGWATCHDOG_2               (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
-#define ADC_ANALOGWATCHDOG_3               (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
-  * @{
-  */
-#define ADC_ANALOGWATCHDOG_NONE                 (0x00000000UL)                                          /*!< No analog watchdog selected                                             */
-#define ADC_ANALOGWATCHDOG_SINGLE_REG           (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN)                  /*!< Analog watchdog applied to a regular group single channel               */
-#define ADC_ANALOGWATCHDOG_ALL_REG              (ADC_CFGR1_AWD1EN)                                      /*!< Analog watchdog applied to regular group all channels                   */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_HAL_EC_OVS_RATIO  Oversampling - Ratio
-  * @{
-  */
-#define ADC_OVERSAMPLING_RATIO_2           (LL_ADC_OVS_RATIO_2)   /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_4           (LL_ADC_OVS_RATIO_4)   /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_8           (LL_ADC_OVS_RATIO_8)   /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_16          (LL_ADC_OVS_RATIO_16)  /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_32          (LL_ADC_OVS_RATIO_32)  /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_64          (LL_ADC_OVS_RATIO_64)  /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_128         (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_256         (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_HAL_EC_OVS_SHIFT  Oversampling - Data shift
-  * @{
-  */
-#define ADC_RIGHTBITSHIFT_NONE             (LL_ADC_OVS_SHIFT_NONE)    /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_1                (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_2                (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_3                (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_4                (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_5                (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_6                (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_7                (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
-#define ADC_RIGHTBITSHIFT_8                (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
-  * @{
-  */
-#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER   (LL_ADC_OVS_REG_CONT)          /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
-#define ADC_TRIGGEREDMODE_MULTI_TRIGGER    (LL_ADC_OVS_REG_DISCONT)       /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ  ADC group regular - Trigger frequency mode
-  * @{
-  */
-#define ADC_TRIGGER_FREQ_HIGH              (LL_ADC_TRIGGER_FREQ_HIGH) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
-#define ADC_TRIGGER_FREQ_LOW               (LL_ADC_TRIGGER_FREQ_LOW)  /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Event_type ADC Event type
-  * @{
-  */
-#define ADC_EOSMP_EVENT          (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
-#define ADC_AWD1_EVENT           (ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
-#define ADC_AWD2_EVENT           (ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
-#define ADC_AWD3_EVENT           (ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
-#define ADC_OVR_EVENT            (ADC_FLAG_OVR)   /*!< ADC overrun event */
-/**
-  * @}
-  */
-#define ADC_AWD_EVENT            ADC_AWD1_EVENT      /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
-
-/** @defgroup ADC_interrupts_definition ADC interrupts definition
-  * @{
-  */
-#define ADC_IT_RDY           ADC_IER_ADRDYIE    /*!< ADC Ready interrupt source */
-#define ADC_IT_CCRDY         ADC_IER_CCRDYIE    /*!< ADC channel configuration ready interrupt source */
-#define ADC_IT_EOSMP         ADC_IER_EOSMPIE    /*!< ADC End of sampling interrupt source */
-#define ADC_IT_EOC           ADC_IER_EOCIE      /*!< ADC End of regular conversion interrupt source */
-#define ADC_IT_EOS           ADC_IER_EOSIE      /*!< ADC End of regular sequence of conversions interrupt source */
-#define ADC_IT_OVR           ADC_IER_OVRIE      /*!< ADC overrun interrupt source */
-#define ADC_IT_AWD1          ADC_IER_AWD1IE     /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
-#define ADC_IT_AWD2          ADC_IER_AWD2IE     /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
-#define ADC_IT_AWD3          ADC_IER_AWD3IE     /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_flags_definition ADC flags definition
-  * @{
-  */
-#define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready flag */
-#define ADC_FLAG_CCRDY         ADC_ISR_CCRDY    /*!< ADC channel configuration ready flag */
-#define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
-#define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
-#define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */
-#define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
-#define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag */
-#define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag */
-#define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Macros ADC Private Macros
-  * @{
-  */
-/* Macro reserved for internal HAL driver usage, not intended to be used in   */
-/* code of final user.                                                        */
-
-/**
-  * @brief Test if conversion trigger of regular group is software start
-  *        or external trigger.
-  * @param __HANDLE__ ADC handle
-  * @retval SET (software start) or RESET (external trigger)
-  */
-#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
-  (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL)
-
-/**
-  * @brief Return resolution bits in CFGR1 register RES[1:0] field.
-  * @param __HANDLE__ ADC handle
-  * @retval Value of bitfield RES in CFGR1 register.
-  */
-#define ADC_GET_RESOLUTION(__HANDLE__)                                         \
-  (LL_ADC_GetResolution((__HANDLE__)->Instance))
-
-/**
-  * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
-  * @param __HANDLE__ ADC handle
-  * @retval None
-  */
-#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-
-/**
-  * @brief Simultaneously clear and set specific bits of the handle State.
-  * @note  ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
-  *        the first parameter is the ADC handle State, the second parameter is the
-  *        bit field to clear, the third and last parameter is the bit field to set.
-  * @retval None
-  */
-#define ADC_STATE_CLR_SET MODIFY_REG
-
-/**
-  * @brief Enable ADC discontinuous conversion mode for regular group
-  * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
-  * @retval None
-  */
-#define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_)                 \
-  ((_REG_DISCONTINUOUS_MODE_) << 16U)
-
-/**
-  * @brief Enable the ADC auto off mode.
-  * @param _AUTOOFF_ Auto off bit enable or disable.
-  * @retval None
-  */
-#define ADC_CFGR1_AUTOOFF(_AUTOOFF_)                                           \
-  ((_AUTOOFF_) << 15U)
-
-/**
-  * @brief Enable the ADC auto delay mode.
-  * @param _AUTOWAIT_ Auto delay bit enable or disable.
-  * @retval None
-  */
-#define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_)                                         \
-  ((_AUTOWAIT_) << 14U)
-
-/**
-  * @brief Enable ADC continuous conversion mode.
-  * @param _CONTINUOUS_MODE_ Continuous mode.
-  * @retval None
-  */
-#define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_)                                \
-  ((_CONTINUOUS_MODE_) << 13U)
-
-/**
-  * @brief Enable ADC overrun mode.
-  * @param _OVERRUN_MODE_ Overrun mode.
-  * @retval Overrun bit setting to be programmed into CFGR register
-  */
-/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant                   */
-/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it    */
-/* as the default case to be compliant with other STM32 devices.              */
-#define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_)                                      \
-  ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED)                             \
-    )? (ADC_CFGR1_OVRMOD) : (0x00000000UL)                                     \
-  )
-
-/**
-  * @brief Set ADC scan mode with differentiation of sequencer setting
-  *        fixed or configurable
-  * @param _SCAN_MODE_ Scan conversion mode.
-  * @retval None
-  */
-/* Note: Scan mode set using this macro (instead of parameter direct set)     */
-/*       due to different modes on other STM32 devices:                       */
-/*       if scan mode is disabled, sequencer is set to fully configurable     */
-/*       with setting of only rank 1 enabled afterwards.                      */
-#define ADC_SCAN_SEQ_MODE(_SCAN_MODE_)                                         \
-  ( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL                           \
-    )?                                                                         \
-    ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT))                                \
-    :                                                                          \
-    (ADC_CFGR1_CHSELRMOD)                                                      \
-  )
-
-/**
-  * @brief Enable the ADC DMA continuous request.
-  * @param _DMACONTREQ_MODE_: DMA continuous request mode.
-  * @retval None
-  */
-#define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_)                                \
-  ((_DMACONTREQ_MODE_) << 1U)
-
-/**
-  * @brief Shift the AWD threshold in function of the selected ADC resolution.
-  *        Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
-  *        If resolution 12 bits, no shift.
-  *        If resolution 10 bits, shift of 2 ranks on the left.
-  *        If resolution 8 bits, shift of 4 ranks on the left.
-  *        If resolution 6 bits, shift of 6 ranks on the left.
-  *        therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
-  * @param __HANDLE__ ADC handle
-  * @param _Threshold_ Value to be shifted
-  * @retval None
-  */
-#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_)            \
-  ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
-
-#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1  )   ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2  )   ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4  )   ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6  )   ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8  )   ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 )   ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 )   ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 )   ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 )   ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 )   ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 )  ||\
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
-
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
-                                       ((RESOLUTION) == ADC_RESOLUTION_10B) || \
-                                       ((RESOLUTION) == ADC_RESOLUTION_8B)  || \
-                                       ((RESOLUTION) == ADC_RESOLUTION_6B)    )
-
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
-                                  ((ALIGN) == ADC_DATAALIGN_LEFT)    )
-
-#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE)            || \
-                                     ((SCAN_MODE) == ADC_SCAN_ENABLE)             || \
-                                     ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED)          || \
-                                     ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD)   )
-
-#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
-                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
-                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
-                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
-
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIG_T2_CC4)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIG_T2_CC3)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \
-                                 ((REGTRIG) == ADC_SOFTWARE_START)          )
-
-#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV)    || \
-                                             ((EOC_SELECTION) == ADC_EOC_SEQ_CONV))
-
-#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED)  || \
-                             ((OVR) == ADC_OVR_DATA_OVERWRITTEN)  )
-
-#define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \
-                                             ((RANK) == ADC_RANK_NONE)             )
-
-#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \
-                                   ((RANK) == ADC_REGULAR_RANK_2 ) || \
-                                   ((RANK) == ADC_REGULAR_RANK_3 ) || \
-                                   ((RANK) == ADC_REGULAR_RANK_4 ) || \
-                                   ((RANK) == ADC_REGULAR_RANK_5 ) || \
-                                   ((RANK) == ADC_REGULAR_RANK_6 ) || \
-                                   ((RANK) == ADC_REGULAR_RANK_7 ) || \
-                                   ((RANK) == ADC_REGULAR_RANK_8 )   )
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_16)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_17)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
-                                 ((CHANNEL) == ADC_CHANNEL_VREFINT)     || \
-                                 ((CHANNEL) == ADC_CHANNEL_VBAT)        || \
-                                 ((CHANNEL) == ADC_CHANNEL_DACCH1)        )
-
-#define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \
-                                                           ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2)   )
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
-                                  ((TIME) == ADC_SAMPLETIME_3CYCLES_5)   || \
-                                  ((TIME) == ADC_SAMPLETIME_7CYCLES_5)   || \
-                                  ((TIME) == ADC_SAMPLETIME_12CYCLES_5)  || \
-                                  ((TIME) == ADC_SAMPLETIME_19CYCLES_5)  || \
-                                  ((TIME) == ADC_SAMPLETIME_39CYCLES_5)  || \
-                                  ((TIME) == ADC_SAMPLETIME_79CYCLES_5)  || \
-                                  ((TIME) == ADC_SAMPLETIME_160CYCLES_5)   )
-
-#define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \
-                                                 ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \
-                                                 ((WATCHDOG) == ADC_ANALOGWATCHDOG_3)   )
-
-#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)            )
-
-#define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \
-                                           ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW)    )
-
-#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_EOSMP_EVENT) || \
-                                  ((EVENT) == ADC_AWD1_EVENT)  || \
-                                  ((EVENT) == ADC_AWD2_EVENT)  || \
-                                  ((EVENT) == ADC_AWD3_EVENT)  || \
-                                  ((EVENT) == ADC_OVR_EVENT)     )
-
-/**
-  * @brief Verify that a given value is aligned with the ADC resolution range.
-  * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
-  * @param __ADC_VALUE__ value checked against the resolution.
-  * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
-  */
-#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
-  ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
-
-/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
-  * @{
-  */
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL))
-/**
-  * @}
-  */
-
-
-/* Private constants ---------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Constants ADC Private Constants
-  * @{
-  */
-
-/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
-#define ADC_FLAG_POSTCONV_ALL    (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
-
-#define ADC_SCAN_SEQ_FIXED_INT  0x80000000U  /* Internal definition to differentiate sequencer setting fixed or configurable */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Macros ADC Exported Macros
-  * @{
-  */
-/* Macro for internal HAL driver usage, and possibly can be used into code of */
-/* final user.                                                                */
-
-/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
-  * @{
-  */
-
-/** @brief  Reset ADC handle state.
-  * @param __HANDLE__ ADC handle
-  * @retval None
-  */
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
-  do{                                                                          \
-    (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \
-    (__HANDLE__)->MspInitCallback = NULL;                                      \
-    (__HANDLE__)->MspDeInitCallback = NULL;                                    \
-  } while(0)
-#else
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
-  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-
-/**
-  * @brief Enable ADC interrupt.
-  * @param __HANDLE__ ADC handle
-  * @param __INTERRUPT__ ADC Interrupt
-  *        This parameter can be one of the following values:
-  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
-  *            @arg @ref ADC_IT_CCRDY  ADC channel configuration ready interrupt source
-  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
-  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
-  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
-  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
-  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
-  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
-  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
-  * @retval None
-  */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
-  (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
-
-/**
-  * @brief Disable ADC interrupt.
-  * @param __HANDLE__ ADC handle
-  * @param __INTERRUPT__ ADC Interrupt
-  *        This parameter can be one of the following values:
-  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
-  *            @arg @ref ADC_IT_CCRDY  ADC channel configuration ready interrupt source
-  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
-  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
-  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
-  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
-  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
-  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
-  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
-  * @retval None
-  */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
-  (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
-  * @param __HANDLE__ ADC handle
-  * @param __INTERRUPT__ ADC interrupt source to check
-  *          This parameter can be one of the following values:
-  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
-  *            @arg @ref ADC_IT_CCRDY  ADC channel configuration ready interrupt source
-  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
-  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
-  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
-  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
-  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
-  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
-  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
-  * @retval State of interruption (SET or RESET)
-  */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
-  (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief Check whether the specified ADC flag is set or not.
-  * @param __HANDLE__ ADC handle
-  * @param __FLAG__ ADC flag
-  *        This parameter can be one of the following values:
-  *            @arg @ref ADC_FLAG_RDY    ADC Ready flag
-  *            @arg @ref ADC_FLAG_CCRDY  ADC channel configuration ready flag
-  *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
-  *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
-  *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
-  *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
-  *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
-  *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
-  *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
-  * @retval State of flag (TRUE or FALSE).
-  */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
-  ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief Clear the specified ADC flag.
-  * @param __HANDLE__ ADC handle
-  * @param __FLAG__ ADC flag
-  *        This parameter can be one of the following values:
-  *            @arg @ref ADC_FLAG_RDY    ADC Ready flag
-  *            @arg @ref ADC_FLAG_CCRDY  ADC channel configuration ready flag
-  *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
-  *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
-  *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
-  *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
-  *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
-  *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
-  *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
-  * @retval None
-  */
-/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
-  (((__HANDLE__)->Instance->ISR) = (__FLAG__))
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to get ADC channel number in decimal format
-  *         from literals ADC_CHANNEL_x.
-  * @note   Example:
-  *           __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
-  *           will return decimal number "4".
-  * @note   The input can be a value from functions where a channel
-  *         number is returned, either defined with number
-  *         or with bitfield (only one bit must be set).
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref ADC_CHANNEL_0
-  *         @arg @ref ADC_CHANNEL_1
-  *         @arg @ref ADC_CHANNEL_2
-  *         @arg @ref ADC_CHANNEL_3
-  *         @arg @ref ADC_CHANNEL_4
-  *         @arg @ref ADC_CHANNEL_5
-  *         @arg @ref ADC_CHANNEL_6
-  *         @arg @ref ADC_CHANNEL_7
-  *         @arg @ref ADC_CHANNEL_8
-  *         @arg @ref ADC_CHANNEL_9
-  *         @arg @ref ADC_CHANNEL_10
-  *         @arg @ref ADC_CHANNEL_11
-  *         @arg @ref ADC_CHANNEL_12
-  *         @arg @ref ADC_CHANNEL_13
-  *         @arg @ref ADC_CHANNEL_14
-  *         @arg @ref ADC_CHANNEL_15         (1)
-  *         @arg @ref ADC_CHANNEL_16         (1)
-  *         @arg @ref ADC_CHANNEL_17         (1)
-  *         @arg @ref ADC_CHANNEL_VREFINT
-  *         @arg @ref ADC_CHANNEL_TEMPSENSOR
-  *         @arg @ref ADC_CHANNEL_VBAT
-  *
-  *         (1) On STM32WL, parameter can be set in ADC group sequencer
-  *             only if sequencer is set in mode "not fully configurable",
-  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
-  * @retval Value between Min_Data=0 and Max_Data=18
-  */
-#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                           \
-  __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
-
-/**
-  * @brief  Helper macro to get ADC channel in literal format ADC_CHANNEL_x
-  *         from number in decimal format.
-  * @note   Example:
-  *           __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
-  *           will return a data equivalent to "ADC_CHANNEL_4".
-  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref ADC_CHANNEL_0
-  *         @arg @ref ADC_CHANNEL_1
-  *         @arg @ref ADC_CHANNEL_2
-  *         @arg @ref ADC_CHANNEL_3
-  *         @arg @ref ADC_CHANNEL_4
-  *         @arg @ref ADC_CHANNEL_5
-  *         @arg @ref ADC_CHANNEL_6
-  *         @arg @ref ADC_CHANNEL_7
-  *         @arg @ref ADC_CHANNEL_8
-  *         @arg @ref ADC_CHANNEL_9
-  *         @arg @ref ADC_CHANNEL_10
-  *         @arg @ref ADC_CHANNEL_11
-  *         @arg @ref ADC_CHANNEL_12
-  *         @arg @ref ADC_CHANNEL_13
-  *         @arg @ref ADC_CHANNEL_14
-  *         @arg @ref ADC_CHANNEL_15         (1)
-  *         @arg @ref ADC_CHANNEL_16         (1)
-  *         @arg @ref ADC_CHANNEL_17         (1)
-  *         @arg @ref ADC_CHANNEL_VREFINT    (2)
-  *         @arg @ref ADC_CHANNEL_TEMPSENSOR (2)
-  *         @arg @ref ADC_CHANNEL_VBAT       (2)
-  *
-  *         (1) On STM32WL, parameter can be set in ADC group sequencer
-  *             only if sequencer is set in mode "not fully configurable",
-  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
-  *         (2) For ADC channel read back from ADC register,
-  *             comparison with internal channel parameter to be done
-  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
-  */
-#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                        \
-  __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
-
-/**
-  * @brief  Helper macro to determine whether the selected channel
-  *         corresponds to literal definitions of driver.
-  * @note   The different literal definitions of ADC channels are:
-  *         - ADC internal channel:
-  *           ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
-  *         - ADC external channel (channel connected to a GPIO pin):
-  *           ADC_CHANNEL_1, ADC_CHANNEL_2, ...
-  * @note   The channel parameter must be a value defined from literal
-  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
-  *         ADC_CHANNEL_TEMPSENSOR, ...),
-  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
-  *         must not be a value from functions where a channel number is
-  *         returned from ADC registers,
-  *         because internal and external channels share the same channel
-  *         number in ADC registers. The differentiation is made only with
-  *         parameters definitions of driver.
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref ADC_CHANNEL_0
-  *         @arg @ref ADC_CHANNEL_1
-  *         @arg @ref ADC_CHANNEL_2
-  *         @arg @ref ADC_CHANNEL_3
-  *         @arg @ref ADC_CHANNEL_4
-  *         @arg @ref ADC_CHANNEL_5
-  *         @arg @ref ADC_CHANNEL_6
-  *         @arg @ref ADC_CHANNEL_7
-  *         @arg @ref ADC_CHANNEL_8
-  *         @arg @ref ADC_CHANNEL_9
-  *         @arg @ref ADC_CHANNEL_10
-  *         @arg @ref ADC_CHANNEL_11
-  *         @arg @ref ADC_CHANNEL_12
-  *         @arg @ref ADC_CHANNEL_13
-  *         @arg @ref ADC_CHANNEL_14
-  *         @arg @ref ADC_CHANNEL_15         (1)
-  *         @arg @ref ADC_CHANNEL_16         (1)
-  *         @arg @ref ADC_CHANNEL_17         (1)
-  *         @arg @ref ADC_CHANNEL_VREFINT
-  *         @arg @ref ADC_CHANNEL_TEMPSENSOR
-  *         @arg @ref ADC_CHANNEL_VBAT
-  *
-  *         (1) On STM32WL, parameter can be set in ADC group sequencer
-  *             only if sequencer is set in mode "not fully configurable",
-  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
-  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
-  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
-  */
-#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                             \
-  __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
-
-/**
-  * @brief  Helper macro to convert a channel defined from parameter
-  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
-  *         ADC_CHANNEL_TEMPSENSOR, ...),
-  *         to its equivalent parameter definition of a ADC external channel
-  *         (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
-  * @note   The channel parameter can be, additionally to a value
-  *         defined from parameter definition of a ADC internal channel
-  *         (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
-  *         a value defined from parameter definition of
-  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
-  *         or a value from functions where a channel number is returned
-  *         from ADC registers.
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref ADC_CHANNEL_0
-  *         @arg @ref ADC_CHANNEL_1
-  *         @arg @ref ADC_CHANNEL_2
-  *         @arg @ref ADC_CHANNEL_3
-  *         @arg @ref ADC_CHANNEL_4
-  *         @arg @ref ADC_CHANNEL_5
-  *         @arg @ref ADC_CHANNEL_6
-  *         @arg @ref ADC_CHANNEL_7
-  *         @arg @ref ADC_CHANNEL_8
-  *         @arg @ref ADC_CHANNEL_9
-  *         @arg @ref ADC_CHANNEL_10
-  *         @arg @ref ADC_CHANNEL_11
-  *         @arg @ref ADC_CHANNEL_12
-  *         @arg @ref ADC_CHANNEL_13
-  *         @arg @ref ADC_CHANNEL_14
-  *         @arg @ref ADC_CHANNEL_15         (1)
-  *         @arg @ref ADC_CHANNEL_16         (1)
-  *         @arg @ref ADC_CHANNEL_17         (1)
-  *         @arg @ref ADC_CHANNEL_VREFINT
-  *         @arg @ref ADC_CHANNEL_TEMPSENSOR
-  *         @arg @ref ADC_CHANNEL_VBAT
-  *
-  *         (1) On STM32WL, parameter can be set in ADC group sequencer
-  *             only if sequencer is set in mode "not fully configurable",
-  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref ADC_CHANNEL_0
-  *         @arg @ref ADC_CHANNEL_1
-  *         @arg @ref ADC_CHANNEL_2
-  *         @arg @ref ADC_CHANNEL_3
-  *         @arg @ref ADC_CHANNEL_4
-  *         @arg @ref ADC_CHANNEL_5
-  *         @arg @ref ADC_CHANNEL_6
-  *         @arg @ref ADC_CHANNEL_7
-  *         @arg @ref ADC_CHANNEL_8
-  *         @arg @ref ADC_CHANNEL_9
-  *         @arg @ref ADC_CHANNEL_10
-  *         @arg @ref ADC_CHANNEL_11
-  *         @arg @ref ADC_CHANNEL_12
-  *         @arg @ref ADC_CHANNEL_13
-  *         @arg @ref ADC_CHANNEL_14
-  *         @arg @ref ADC_CHANNEL_15
-  *         @arg @ref ADC_CHANNEL_16
-  *         @arg @ref ADC_CHANNEL_17
-  */
-#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                    \
-  __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
-
-/**
-  * @brief  Helper macro to determine whether the internal channel
-  *         selected is available on the ADC instance selected.
-  * @note   The channel parameter must be a value defined from parameter
-  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
-  *         ADC_CHANNEL_TEMPSENSOR, ...),
-  *         must not be a value defined from parameter definition of
-  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
-  *         or a value from functions where a channel number is
-  *         returned from ADC registers,
-  *         because internal and external channels share the same channel
-  *         number in ADC registers. The differentiation is made only with
-  *         parameters definitions of driver.
-  * @param  __ADC_INSTANCE__ ADC instance
-  * @param  __CHANNEL__ This parameter can be one of the following values:
-  *         @arg @ref ADC_CHANNEL_VREFINT
-  *         @arg @ref ADC_CHANNEL_TEMPSENSOR
-  *         @arg @ref ADC_CHANNEL_VBAT
-  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
-  *         Value "1" if the internal channel selected is available on the ADC instance selected.
-  */
-#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
-  __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
-
-/**
-  * @brief  Helper macro to select the ADC common instance
-  *         to which is belonging the selected ADC instance.
-  * @note   ADC common register instance can be used for:
-  *         - Set parameters common to several ADC instances
-  *         - Multimode (for devices with several ADC instances)
-  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
-  * @param  __ADCx__ ADC instance
-  * @retval ADC common register instance
-  */
-#define __HAL_ADC_COMMON_INSTANCE(__ADCx__)                                    \
-  __LL_ADC_COMMON_INSTANCE((__ADCx__))
-
-/**
-  * @brief  Helper macro to check if all ADC instances sharing the same
-  *         ADC common instance are disabled.
-  * @note   This check is required by functions with setting conditioned to
-  *         ADC state:
-  *         All ADC instances of the ADC common group must be disabled.
-  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
-  * @note   On devices with only 1 ADC common instance, parameter of this macro
-  *         is useless and can be ignored (parameter kept for compatibility
-  *         with devices featuring several ADC common instances).
-  * @param  __ADCXY_COMMON__ ADC common instance
-  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
-  * @retval Value "0" if all ADC instances sharing the same ADC common instance
-  *         are disabled.
-  *         Value "1" if at least one ADC instance sharing the same ADC common instance
-  *         is enabled.
-  */
-#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
-  __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
-
-/**
-  * @brief  Helper macro to define the ADC conversion data full-scale digital
-  *         value corresponding to the selected ADC resolution.
-  * @note   ADC conversion data full-scale corresponds to voltage range
-  *         determined by analog voltage references Vref+ and Vref-
-  *         (refer to reference manual).
-  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref ADC_RESOLUTION_12B
-  *         @arg @ref ADC_RESOLUTION_10B
-  *         @arg @ref ADC_RESOLUTION_8B
-  *         @arg @ref ADC_RESOLUTION_6B
-  * @retval ADC conversion data full-scale digital value
-  */
-#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
-  __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
-
-/**
-  * @brief  Helper macro to convert the ADC conversion data from
-  *         a resolution to another resolution.
-  * @param  __DATA__ ADC conversion data to be converted
-  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
-  *         This parameter can be one of the following values:
-  *         @arg @ref ADC_RESOLUTION_12B
-  *         @arg @ref ADC_RESOLUTION_10B
-  *         @arg @ref ADC_RESOLUTION_8B
-  *         @arg @ref ADC_RESOLUTION_6B
-  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
-  *         This parameter can be one of the following values:
-  *         @arg @ref ADC_RESOLUTION_12B
-  *         @arg @ref ADC_RESOLUTION_10B
-  *         @arg @ref ADC_RESOLUTION_8B
-  *         @arg @ref ADC_RESOLUTION_6B
-  * @retval ADC conversion data to the requested resolution
-  */
-#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
-                                          __ADC_RESOLUTION_CURRENT__,\
-                                          __ADC_RESOLUTION_TARGET__) \
-__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
-                                 (__ADC_RESOLUTION_CURRENT__),\
-                                 (__ADC_RESOLUTION_TARGET__))
-
-/**
-  * @brief  Helper macro to calculate the voltage (unit: mVolt)
-  *         corresponding to a ADC conversion data (unit: digital value).
-  * @note   Analog reference voltage (Vref+) must be either known from
-  *         user board environment or can be calculated using ADC measurement
-  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
-  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
-  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
-  *                       (unit: digital value).
-  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref ADC_RESOLUTION_12B
-  *         @arg @ref ADC_RESOLUTION_10B
-  *         @arg @ref ADC_RESOLUTION_8B
-  *         @arg @ref ADC_RESOLUTION_6B
-  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
-  */
-#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
-                                       __ADC_DATA__,\
-                                       __ADC_RESOLUTION__) \
-__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
-                              (__ADC_DATA__),\
-                              (__ADC_RESOLUTION__))
-
-/**
-  * @brief  Helper macro to calculate analog reference voltage (Vref+)
-  *         (unit: mVolt) from ADC conversion data of internal voltage
-  *         reference VrefInt.
-  * @note   Computation is using VrefInt calibration value
-  *         stored in system memory for each device during production.
-  * @note   This voltage depends on user board environment: voltage level
-  *         connected to pin Vref+.
-  *         On devices with small package, the pin Vref+ is not present
-  *         and internally bonded to pin Vdda.
-  * @note   On this STM32 series, calibration data of internal voltage reference
-  *         VrefInt corresponds to a resolution of 12 bits,
-  *         this is the recommended ADC resolution to convert voltage of
-  *         internal voltage reference VrefInt.
-  *         Otherwise, this macro performs the processing to scale
-  *         ADC conversion data to 12 bits.
-  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
-  *         of internal voltage reference VrefInt (unit: digital value).
-  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
-  *         @arg @ref ADC_RESOLUTION_12B
-  *         @arg @ref ADC_RESOLUTION_10B
-  *         @arg @ref ADC_RESOLUTION_8B
-  *         @arg @ref ADC_RESOLUTION_6B
-  * @retval Analog reference voltage (unit: mV)
-  */
-#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
-                                          __ADC_RESOLUTION__) \
-__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
-                                 (__ADC_RESOLUTION__))
-
-/**
-  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
-  *         from ADC conversion data of internal temperature sensor.
-  * @note   Computation is using temperature sensor calibration values
-  *         stored in system memory for each device during production.
-  * @note   Calculation formula:
-  *           Temperature = ((TS_ADC_DATA - TS_CAL1)
-  *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
-  *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
-  *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
-  *                Avg_Slope = (TS_CAL2 - TS_CAL1)
-  *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
-  *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
-  *                            TEMP_DEGC_CAL1 (calibrated in factory)
-  *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
-  *                            TEMP_DEGC_CAL2 (calibrated in factory)
-  *         Caution: Calculation relevancy under reserve that calibration
-  *                  parameters are correct (address and data).
-  *                  To calculate temperature using temperature sensor
-  *                  datasheet typical values (generic values less, therefore
-  *                  less accurate than calibrated values),
-  *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
-  * @note   As calculation input, the analog reference voltage (Vref+) must be
-  *         defined as it impacts the ADC LSB equivalent voltage.
-  * @note   Analog reference voltage (Vref+) must be either known from
-  *         user board environment or can be calculated using ADC measurement
-  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
-  * @note   On this STM32 series, calibration data of temperature sensor
-  *         corresponds to a resolution of 12 bits,
-  *         this is the recommended ADC resolution to convert voltage of
-  *         temperature sensor.
-  *         Otherwise, this macro performs the processing to scale
-  *         ADC conversion data to 12 bits.
-  * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
-  * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
-  *                                 temperature sensor (unit: digital value).
-  * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
-  *                                 sensor voltage has been measured.
-  *         This parameter can be one of the following values:
-  *         @arg @ref ADC_RESOLUTION_12B
-  *         @arg @ref ADC_RESOLUTION_10B
-  *         @arg @ref ADC_RESOLUTION_8B
-  *         @arg @ref ADC_RESOLUTION_6B
-  * @retval Temperature (unit: degree Celsius)
-  */
-#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
-                                   __TEMPSENSOR_ADC_DATA__,\
-                                   __ADC_RESOLUTION__) \
-__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
-                          (__TEMPSENSOR_ADC_DATA__),\
-                          (__ADC_RESOLUTION__))
-
-/**
-  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
-  *         from ADC conversion data of internal temperature sensor.
-  * @note   Computation is using temperature sensor typical values
-  *         (refer to device datasheet).
-  * @note   Calculation formula:
-  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
-  *                         / Avg_Slope + CALx_TEMP
-  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
-  *                                   (unit: digital value)
-  *                Avg_Slope        = temperature sensor slope
-  *                                   (unit: uV/Degree Celsius)
-  *                TS_TYP_CALx_VOLT = temperature sensor digital value at
-  *                                   temperature CALx_TEMP (unit: mV)
-  *         Caution: Calculation relevancy under reserve the temperature sensor
-  *                  of the current device has characteristics in line with
-  *                  datasheet typical values.
-  *                  If temperature sensor calibration values are available on
-  *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
-  *                  temperature calculation will be more accurate using
-  *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
-  * @note   As calculation input, the analog reference voltage (Vref+) must be
-  *         defined as it impacts the ADC LSB equivalent voltage.
-  * @note   Analog reference voltage (Vref+) must be either known from
-  *         user board environment or can be calculated using ADC measurement
-  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
-  * @note   ADC measurement data must correspond to a resolution of 12bits
-  *         (full scale digital value 4095). If not the case, the data must be
-  *         preliminarily rescaled to an equivalent resolution of 12 bits.
-  * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
-  *                                       On STM32WL, refer to device datasheet parameter "Avg_Slope".
-  * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
-  *                                       On STM32WL, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
-  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
-  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
-  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
-  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
-  *         This parameter can be one of the following values:
-  *         @arg @ref ADC_RESOLUTION_12B
-  *         @arg @ref ADC_RESOLUTION_10B
-  *         @arg @ref ADC_RESOLUTION_8B
-  *         @arg @ref ADC_RESOLUTION_6B
-  * @retval Temperature (unit: degree Celsius)
-  */
-#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
-                                              __TEMPSENSOR_TYP_CALX_V__,\
-                                              __TEMPSENSOR_CALX_TEMP__,\
-                                              __VREFANALOG_VOLTAGE__,\
-                                              __TEMPSENSOR_ADC_DATA__,\
-                                              __ADC_RESOLUTION__) \
-__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
-                                     (__TEMPSENSOR_TYP_CALX_V__),\
-                                     (__TEMPSENSOR_CALX_TEMP__),\
-                                     (__VREFANALOG_VOLTAGE__),\
-                                     (__TEMPSENSOR_ADC_DATA__),\
-                                     (__ADC_RESOLUTION__))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Include ADC HAL Extended module */
-#include "stm32wlxx_hal_adc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group1
-  * @brief    Initialization and Configuration functions
-  * @{
-  */
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void                    HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
-void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
-
-#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
-                                           pADC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group2
-  * @brief    IO operation functions
-  * @{
-  */
-/* IO operation functions  *****************************************************/
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
-HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
-
-/* Non-blocking mode: DMA */
-HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
-HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
-void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
-void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
-void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
-void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
-void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief    Peripheral Control functions
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig);
-HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig);
-
-/**
-  * @}
-  */
-
-/* Peripheral State functions *************************************************/
-/** @addtogroup ADC_Exported_Functions_Group4
-  * @{
-  */
-uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
-uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32WLxx_HAL_ADC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h

@@ -1,189 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_adc_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of ADC HAL extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_ADC_EX_H
-#define STM32WLxx_HAL_ADC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADCEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup ADC_HAL_EC_GROUPS  ADC instance - Groups
-  * @{
-  */
-#define ADC_REGULAR_GROUP                  (LL_ADC_GROUP_REGULAR)           /*!< ADC group regular (available on all STM32 devices) */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
-  * @{
-  */
-/* Macro reserved for internal HAL driver usage, not intended to be used in   */
-/* code of final user.                                                        */
-
-/**
-  * @brief Check whether or not ADC is independent.
-  * @param __HANDLE__ ADC handle.
-  * @note  When multimode feature is not available, the macro always returns SET.
-  * @retval SET (ADC is independent) or RESET (ADC is not).
-  */
-#define ADC_IS_INDEPENDENT(__HANDLE__)   (SET)
-
-
-/**
-  * @brief Calibration factor size verification (7 bits maximum).
-  * @param __CALIBRATION_FACTOR__ Calibration factor value.
-  * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
-  */
-#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
-
-/**
-  * @brief Verify the ADC oversampling ratio.
-  * @param __RATIO__ programmed ADC oversampling ratio.
-  * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
-  */
-#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__)      (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
-                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
-                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
-                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
-                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
-                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
-                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
-                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
-
-/**
-  * @brief Verify the ADC oversampling shift.
-  * @param __SHIFT__ programmed ADC oversampling shift.
-  * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
-  */
-#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)        (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
-                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))
-
-/**
-  * @brief Verify the ADC oversampling triggered mode.
-  * @param __MODE__ programmed ADC oversampling triggered mode.
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
-                                                      ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
-
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADCEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup ADCEx_Exported_Functions_Group1
-  * @{
-  */
-/* IO operation functions *****************************************************/
-
-/* ADC calibration */
-HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc);
-uint32_t                HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc);
-HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
-void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
-void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
-void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
-void                    HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc);
-
-/**
-  * @}
-  */
-
-/** @addtogroup ADCEx_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_ADC_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_comp.h

@@ -1,730 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_comp.h
-  * @author  MCD Application Team
-  * @brief   Header file of COMP HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_COMP_H
-#define STM32WLxx_HAL_COMP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-#include "stm32wlxx_ll_exti.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-
-/** @addtogroup COMP
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup COMP_Exported_Types COMP Exported Types
-  * @{
-  */
-
-/**
-  * @brief  COMP Init structure definition
-  */
-typedef struct
-{
-
-  uint32_t WindowMode;         /*!< Set window mode of a pair of comparators instances
-                                    (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
-                                    Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
-                                    This parameter can be a value of @ref COMP_WindowMode */
-
-  uint32_t Mode;               /*!< Set comparator operating mode to adjust power and speed.
-                                    Note: For the characteristics of comparator power modes
-                                          (propagation delay and power consumption), refer to device datasheet.
-                                    This parameter can be a value of @ref COMP_PowerMode */
-
-  uint32_t InputPlus;          /*!< Set comparator input plus (non-inverting input).
-                                    This parameter can be a value of @ref COMP_InputPlus */
-
-  uint32_t InputMinus;         /*!< Set comparator input minus (inverting input).
-                                    This parameter can be a value of @ref COMP_InputMinus */
-
-  uint32_t Hysteresis;         /*!< Set comparator hysteresis mode of the input minus.
-                                    This parameter can be a value of @ref COMP_Hysteresis */
-
-  uint32_t OutputPol;          /*!< Set comparator output polarity.
-                                    This parameter can be a value of @ref COMP_OutputPolarity */
-
-  uint32_t BlankingSrce;       /*!< Set comparator blanking source.
-                                    This parameter can be a value of @ref COMP_BlankingSrce */
-
-  uint32_t TriggerMode;        /*!< Set the comparator output triggering External Interrupt Line (EXTI).
-                                    This parameter can be a value of @ref COMP_EXTI_TriggerMode */
-
-} COMP_InitTypeDef;
-
-/**
-  * @brief  HAL COMP state machine: HAL COMP states definition
-  */
-#define COMP_STATE_BITFIELD_LOCK  (0x10U)
-typedef enum
-{
-  HAL_COMP_STATE_RESET             = 0x00U,                                             /*!< COMP not yet initialized                             */
-  HAL_COMP_STATE_RESET_LOCKED      = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
-  HAL_COMP_STATE_READY             = 0x01U,                                             /*!< COMP initialized and ready for use                   */
-  HAL_COMP_STATE_READY_LOCKED      = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked         */
-  HAL_COMP_STATE_BUSY              = 0x02U,                                             /*!< COMP is running                                      */
-  HAL_COMP_STATE_BUSY_LOCKED       = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)   /*!< COMP is running and configuration is locked          */
-} HAL_COMP_StateTypeDef;
-
-/**
-  * @brief  COMP Handle Structure definition
-  */
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-typedef struct __COMP_HandleTypeDef
-#else
-typedef struct
-#endif
-{
-  COMP_TypeDef       *Instance;       /*!< Register base address    */
-  COMP_InitTypeDef   Init;            /*!< COMP required parameters */
-  HAL_LockTypeDef    Lock;            /*!< Locking object           */
-  __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
-  __IO uint32_t      ErrorCode;       /*!< COMP error code */
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-  void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP trigger callback */
-  void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP Msp Init callback */
-  void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-} COMP_HandleTypeDef;
-
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL COMP Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_COMP_TRIGGER_CB_ID                = 0x00U,  /*!< COMP trigger callback ID */
-  HAL_COMP_MSPINIT_CB_ID                = 0x01U,  /*!< COMP Msp Init callback ID */
-  HAL_COMP_MSPDEINIT_CB_ID              = 0x02U   /*!< COMP Msp DeInit callback ID */
-} HAL_COMP_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL COMP Callback pointer definition
-  */
-typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
-
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup COMP_Exported_Constants COMP Exported Constants
-  * @{
-  */
-
-/** @defgroup COMP_Error_Code COMP Error Code
-  * @{
-  */
-#define HAL_COMP_ERROR_NONE             (0x00UL)  /*!< No error */
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)  /*!< Invalid Callback error */
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_WindowMode COMP Window Mode
-  * @{
-  */
-#define COMP_WINDOWMODE_DISABLE                 (0x00000000UL)         /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
-#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE)     /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_PowerMode COMP power mode
-  * @{
-  */
-/* Note: For the characteristics of comparator power modes                    */
-/*       (propagation delay and power consumption),                           */
-/*       refer to device datasheet.                                           */
-#define COMP_POWERMODE_HIGHSPEED       (0x00000000UL)         /*!< High Speed */
-#define COMP_POWERMODE_MEDIUMSPEED     (COMP_CSR_PWRMODE_0)   /*!< Medium Speed */
-#define COMP_POWERMODE_ULTRALOWPOWER   (COMP_CSR_PWRMODE)     /*!< Ultra-low power mode */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
-  * @{
-  */
-#define COMP_INPUT_PLUS_IO1            (0x00000000UL)         /*!< Comparator input plus connected to IO1 (pin PB4 for COMP1, pin PB4 for COMP2) */
-#define COMP_INPUT_PLUS_IO2            (COMP_CSR_INPSEL_0)    /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PB1 for COMP2) */
-#define COMP_INPUT_PLUS_IO3            (COMP_CSR_INPSEL_1)    /*!< Comparator input plus connected to IO3 (not applicable for COMP1, pin PA15 for COMP2) */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_InputMinus COMP input minus (inverting input)
-  * @{
-  */
-#define COMP_INPUT_MINUS_1_4VREFINT    (                                                            COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt */
-#define COMP_INPUT_MINUS_1_2VREFINT    (                                        COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt */
-#define COMP_INPUT_MINUS_3_4VREFINT    (                    COMP_CSR_INMSEL_1                     | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt */
-#define COMP_INPUT_MINUS_VREFINT       (                    COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN                 )        /*!< Comparator input minus connected to VrefInt */
-#define COMP_INPUT_MINUS_DAC_CH1       (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC channel 1 (DAC_OUT1) */
-#define COMP_INPUT_MINUS_IO1           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    )                                           /*!< Comparator input minus connected to IO1 (pin PB3 for COMP1, pin PB3 for COMP2) */
-#define COMP_INPUT_MINUS_IO2           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to IO2 (pin PA10 for COMP1, pin PB2 for COMP2) */
-#define COMP_INPUT_MINUS_IO3           (                     COMP_CSR_INMESEL_0 | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO3 (pin PA11 for COMP1, pin PA10 for COMP2) */
-#define COMP_INPUT_MINUS_IO4           (COMP_CSR_INMESEL_1                      | COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO4 (pin PA15 for COMP1, pin PA11 for COMP2) */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Hysteresis COMP hysteresis
-  * @{
-  */
-#define COMP_HYSTERESIS_NONE           (0x00000000UL)                       /*!< No hysteresis */
-#define COMP_HYSTERESIS_LOW            (                  COMP_CSR_HYST_0)  /*!< Hysteresis level low */
-#define COMP_HYSTERESIS_MEDIUM         (COMP_CSR_HYST_1                  )  /*!< Hysteresis level medium */
-#define COMP_HYSTERESIS_HIGH           (COMP_CSR_HYST_1 | COMP_CSR_HYST_0)  /*!< Hysteresis level high */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_OutputPolarity COMP output Polarity
-  * @{
-  */
-#define COMP_OUTPUTPOL_NONINVERTED     (0x00000000UL)         /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
-#define COMP_OUTPUTPOL_INVERTED        (COMP_CSR_POLARITY)    /*!< COMP output level is inverted     (comparator output is low  when the input plus is at a higher voltage than the input minus) */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_BlankingSrce  COMP blanking source
-  * @{
-  */
-#define COMP_BLANKINGSRC_NONE            (0x00000000UL)          /*!<Comparator output without blanking */
-/* Note: Output blanking source common to all COMP instances */
-#define COMP_BLANKINGSRC_TIM1_OC5        (COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2) */
-#define COMP_BLANKINGSRC_TIM2_OC3        (COMP_CSR_BLANKING_1)   /*!< Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2) */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_OutputLevel COMP Output Level
-  * @{
-  */
-/* Note: Comparator output level values are fixed to "0" and "1",             */
-/* corresponding COMP register bit is managed by HAL function to match        */
-/* with these values (independently of bit position in register).             */
-
-/* When output polarity is not inverted, comparator output is low when
-   the input plus is at a lower voltage than the input minus */
-#define COMP_OUTPUT_LEVEL_LOW              (0x00000000UL)
-/* When output polarity is not inverted, comparator output is high when
-   the input plus is at a higher voltage than the input minus */
-#define COMP_OUTPUT_LEVEL_HIGH             (0x00000001UL)
-/**
-  * @}
-  */
-
-/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
-  * @{
-  */
-#define COMP_TRIGGERMODE_NONE                 (0x00000000UL)                                            /*!< Comparator output triggering no External Interrupt Line */
-#define COMP_TRIGGERMODE_IT_RISING            (COMP_EXTI_IT | COMP_EXTI_RISING)                         /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
-#define COMP_TRIGGERMODE_IT_FALLING           (COMP_EXTI_IT | COMP_EXTI_FALLING)                        /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
-#define COMP_TRIGGERMODE_IT_RISING_FALLING    (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)     /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
-#define COMP_TRIGGERMODE_EVENT_RISING         (COMP_EXTI_EVENT | COMP_EXTI_RISING)                      /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
-#define COMP_TRIGGERMODE_EVENT_FALLING        (COMP_EXTI_EVENT | COMP_EXTI_FALLING)                     /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
-#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)  /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup COMP_Exported_Macros COMP Exported Macros
-  * @{
-  */
-
-/** @defgroup COMP_Handle_Management  COMP Handle Management
-  * @{
-  */
-
-/** @brief  Reset COMP handle state.
-  * @param  __HANDLE__  COMP handle
-  * @retval None
-  */
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{                                                  \
-                                                      (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
-                                                      (__HANDLE__)->MspInitCallback = NULL;            \
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                    } while(0)
-#else
-#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
-#endif
-
-/**
-  * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
-  * @param __HANDLE__ COMP handle
-  * @retval None
-  */
-#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
-
-/**
-  * @brief  Enable the specified comparator.
-  * @param  __HANDLE__  COMP handle
-  * @retval None
-  */
-#define __HAL_COMP_ENABLE(__HANDLE__)              SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
-
-/**
-  * @brief  Disable the specified comparator.
-  * @param  __HANDLE__  COMP handle
-  * @retval None
-  */
-#define __HAL_COMP_DISABLE(__HANDLE__)             CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
-
-/**
-  * @brief  Lock the specified comparator configuration.
-  * @note   Using this macro induce HAL COMP handle state machine being no
-  *         more in line with COMP instance state.
-  *         To keep HAL COMP handle state machine updated, it is recommended
-  *         to use function "HAL_COMP_Lock')".
-  * @param  __HANDLE__  COMP handle
-  * @retval None
-  */
-#define __HAL_COMP_LOCK(__HANDLE__)                SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
-
-/**
-  * @brief  Check whether the specified comparator is locked.
-  * @param  __HANDLE__  COMP handle
-  * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
-  */
-#define __HAL_COMP_IS_LOCKED(__HANDLE__)           (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Exti_Management  COMP external interrupt line management
-  * @{
-  */
-
-/**
-  * @brief  Enable the COMP1 EXTI line rising edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Disable the COMP1 EXTI line rising edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Enable the COMP1 EXTI line falling edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Disable the COMP1 EXTI line falling edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
-                                                               LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
-                                                               LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
-                                                             } while(0)
-
-/**
-  * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
-                                                               LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
-                                                               LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
-                                                             } while(0)
-
-/**
-  * @brief  Enable the COMP1 EXTI line in interrupt mode.
-  * @retval None
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             LL_C2_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
-#else
-#define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
-#endif
-
-/**
-  * @brief  Disable the COMP1 EXTI line in interrupt mode.
-  * @retval None
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            LL_C2_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
-#else
-#define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
-#endif
-
-/**
-  * @brief  Generate a software interrupt on the COMP1 EXTI line.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Enable the COMP1 EXTI line in event mode.
-  * @retval None
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()          LL_C2_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
-#else
-#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
-#endif
-
-/**
-  * @brief  Disable the COMP1 EXTI line in event mode.
-  * @retval None
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()         LL_C2_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
-#else
-#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
-#endif
-
-/**
-  * @brief  Check whether the COMP1 EXTI line flag is set.
-  * @retval RESET or SET
-  */
-#define __HAL_COMP_COMP1_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Clear the COMP1 EXTI flag.
-  * @retval None
-  */
-#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)
-
-/**
-  * @brief  Enable the COMP2 EXTI line rising edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Disable the COMP2 EXTI line rising edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Enable the COMP2 EXTI line falling edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Disable the COMP2 EXTI line falling edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
-                                                               LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
-                                                               LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
-                                                             } while(0)
-
-/**
-  * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
-  * @retval None
-  */                                         
-#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
-                                                               LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
-                                                               LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
-                                                             } while(0)
-
-/**
-  * @brief  Enable the COMP2 EXTI line in interrupt mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Disable the COMP2 EXTI line in interrupt mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Generate a software interrupt on the COMP2 EXTI line.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Enable the COMP2 EXTI line in event mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Disable the COMP2 EXTI line in event mode.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Check whether the COMP2 EXTI line flag is set.
-  * @retval RESET or SET
-  */
-#define __HAL_COMP_COMP2_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)
-
-/**
-  * @brief  Clear the COMP2 EXTI flag.
-  * @retval None
-  */
-#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Private types -------------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup COMP_Private_Constants COMP Private Constants
-  * @{
-  */
-
-/** @defgroup COMP_ExtiLine COMP EXTI Lines
-  * @{
-  */
-#define COMP_EXTI_LINE_COMP1           (LL_EXTI_LINE_21)  /*!< EXTI line 21 connected to COMP1 output */
-#define COMP_EXTI_LINE_COMP2           (LL_EXTI_LINE_22)  /*!< EXTI line 22 connected to COMP2 output */
-/**
-  * @}
-  */
-
-/** @defgroup COMP_ExtiLine COMP EXTI Lines
-  * @{
-  */
-#define COMP_EXTI_IT                        (0x00000001UL)  /*!< EXTI line event with interruption */
-#define COMP_EXTI_EVENT                     (0x00000002UL)  /*!< EXTI line event only (without interruption) */
-#define COMP_EXTI_RISING                    (0x00000010UL)  /*!< EXTI line event on rising edge */
-#define COMP_EXTI_FALLING                   (0x00000020UL)  /*!< EXTI line event on falling edge */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup COMP_Private_Macros COMP Private Macros
-  * @{
-  */
-
-/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
-  * @{
-  */
-/**
-  * @brief  Get the specified EXTI line for a comparator instance.
-  * @param  __INSTANCE__  specifies the COMP instance.
-  * @retval value of @ref COMP_ExtiLine
-  */
-#define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1  \
-                                             : COMP_EXTI_LINE_COMP2)
-/**
-  * @}
-  */
-
-/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters
-  * @{
-  */
-#define IS_COMP_WINDOWMODE(__WINDOWMODE__)  (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \
-                                             ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )
-
-#define IS_COMP_POWERMODE(__POWERMODE__)    (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \
-                                             ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
-                                             ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )
-
-#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) ((__COMP_INSTANCE__ == COMP1)                     \
-                                                               ? (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) ||  \
-                                                                  ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2)   ) \
-                                                               :                                                \
-                                                               (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) ||    \
-                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) ||    \
-                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO3)   )   \
-                                                              )
-
-/* Note: On this STM32 series, comparator input minus parameters are          */
-/*       the same on all COMP instances.                                      */
-/*       However, comparator instance kept as macro parameter for             */
-/*       compatibility with other STM32 families.                             */
-#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
-                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
-                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
-                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
-                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC_CH1)     || \
-                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
-                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         || \
-                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO3)         || \
-                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO4))
-
-#define IS_COMP_HYSTERESIS(__HYSTERESIS__)  (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
-                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
-                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
-                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
-
-#define IS_COMP_OUTPUTPOL(__POL__)          (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
-                                             ((__POL__) == COMP_OUTPUTPOL_INVERTED))
-
-#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)                    \
-  (   ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)               \
-   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5)           \
-   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3)           \
-  )
-
-/* Note: Output blanking source common to all COMP instances */
-/*       Macro kept for compatibility with other STM32 series */
-#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)  \
-   (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__))
-
-
-#define IS_COMP_TRIGGERMODE(__MODE__)       (((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
-                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
-                                             ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
-                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
-                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
-                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
-                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
-
-#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
-                                                ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup COMP_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup COMP_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
-void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
-void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
-
-#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
-                                            pCOMP_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* IO operation functions  *****************************************************/
-/** @addtogroup COMP_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
-void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup COMP_Exported_Functions_Group3
-  * @{
-  */
-HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
-uint32_t          HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
-/* Callback in interrupt mode */
-void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
-/**
-  * @}
-  */
-
-/* Peripheral State functions  **************************************************/
-/** @addtogroup COMP_Exported_Functions_Group4
-  * @{
-  */
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
-uint32_t              HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_COMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_conf_template.h

@@ -1,340 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_conf.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration file.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_CONF_H
-#define STM32WLxx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_COMP_MODULE_ENABLED
-#define HAL_CRC_MODULE_ENABLED
-#define HAL_CRYP_MODULE_ENABLED
-#define HAL_DAC_MODULE_ENABLED
-#define HAL_GTZC_MODULE_ENABLED
-#define HAL_HSEM_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
-#define HAL_IPCC_MODULE_ENABLED
-#define HAL_IRDA_MODULE_ENABLED
-#define HAL_IWDG_MODULE_ENABLED
-#define HAL_LPTIM_MODULE_ENABLED
-#define HAL_PKA_MODULE_ENABLED
-#define HAL_RNG_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-#define HAL_SMARTCARD_MODULE_ENABLED
-#define HAL_SMBUS_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_SUBGHZ_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-#define HAL_USART_MODULE_ENABLED
-#define HAL_WWDG_MODULE_ENABLED
-#define HAL_EXTI_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-
-/* ########################## Register Callbacks selection ############################## */
-/**
-  * @brief This is the list of modules where register callback can be used
-  */
-#define USE_HAL_ADC_REGISTER_CALLBACKS         0u
-#define USE_HAL_COMP_REGISTER_CALLBACKS        0u
-#define USE_HAL_CRYP_REGISTER_CALLBACKS        0u
-#define USE_HAL_DAC_REGISTER_CALLBACKS         0u
-#define USE_HAL_I2C_REGISTER_CALLBACKS         0u
-#define USE_HAL_I2S_REGISTER_CALLBACKS         0u
-#define USE_HAL_IRDA_REGISTER_CALLBACKS        0u
-#define USE_HAL_LPTIM_REGISTER_CALLBACKS       0u
-#define USE_HAL_PKA_REGISTER_CALLBACKS         0u
-#define USE_HAL_RNG_REGISTER_CALLBACKS         0u
-#define USE_HAL_RTC_REGISTER_CALLBACKS         0u
-#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0u
-#define USE_HAL_SMBUS_REGISTER_CALLBACKS       0u
-#define USE_HAL_SPI_REGISTER_CALLBACKS         0u
-#define USE_HAL_SUBGHZ_REGISTER_CALLBACKS      0u
-#define USE_HAL_TIM_REGISTER_CALLBACKS         0u
-#define USE_HAL_UART_REGISTER_CALLBACKS        0u
-#define USE_HAL_USART_REGISTER_CALLBACKS       0u
-#define USE_HAL_WWDG_REGISTER_CALLBACKS        0u
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-
-#if !defined (HSE_VALUE)
-#define HSE_VALUE                           32000000UL  /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (HSE_STARTUP_TIMEOUT)
-#define HSE_STARTUP_TIMEOUT                 100UL       /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal Multiple Speed oscillator (MSI) default value.
-  *        This value is the default MSI range value after Reset.
-  */
-#if !defined  (MSI_VALUE)
-#define MSI_VALUE                           4000000UL   /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-#define HSI_VALUE                           16000000UL  /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined (LSI_VALUE)
-#define LSI_VALUE                           32000UL     /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                                  /*!< Value of the Internal Low Speed oscillator in Hz
-                                                        The real value may vary depending on the variations
-                                                        in voltage and temperature. */
-
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined (LSE_VALUE)
-#define LSE_VALUE                           32768UL     /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-/**
-  * @brief Internal Multiple Speed oscillator (HSI48) default value.
-  *        This value is the default HSI48 range value after Reset.
-  */
-#if !defined (HSI48_VALUE)
-#define HSI48_VALUE                         48000000UL  /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI48_VALUE */
-
-#if !defined (LSE_STARTUP_TIMEOUT)
-#define LSE_STARTUP_TIMEOUT                 5000UL      /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE                          3300U                             /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY                  ((1uL <<__NVIC_PRIO_BITS) - 1uL)  /*!< tick interrupt priority (lowest by default) */
-#define  USE_RTOS                           0U
-#define  PREFETCH_ENABLE                    0U
-#define  INSTRUCTION_CACHE_ENABLE           1U
-#define  DATA_CACHE_ENABLE                  1U
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1 */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
- * Activated: CRC code is present inside driver
- * Deactivated: CRC code cleaned from driver
- */
-
-#define USE_SPI_CRC                         1U
-
-/* ################## CRYP peripheral configuration ########################## */
-
-#define USE_HAL_CRYP_SUSPEND_RESUME         1U
-
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32wlxx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32wlxx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32wlxx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32wlxx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32wlxx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32wlxx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32wlxx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32wlxx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32wlxx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32wlxx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_GTZC_MODULE_ENABLED
-  #include "stm32wlxx_hal_gtzc.h"
-#endif /* HAL_GTZC_MODULE_ENABLED */
-
-#ifdef HAL_HSEM_MODULE_ENABLED
-  #include "stm32wlxx_hal_hsem.h"
-#endif /* HAL_HSEM_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-  #include "stm32wlxx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
-  #include "stm32wlxx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IPCC_MODULE_ENABLED
-  #include "stm32wlxx_hal_ipcc.h"
-#endif /* HAL_IPCC_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
-  #include "stm32wlxx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
-  #include "stm32wlxx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
-  #include "stm32wlxx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_PKA_MODULE_ENABLED
-  #include "stm32wlxx_hal_pka.h"
-#endif /* HAL_PKA_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-  #include "stm32wlxx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32wlxx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
-  #include "stm32wlxx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-  #include "stm32wlxx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-  #include "stm32wlxx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
-  #include "stm32wlxx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
-  #include "stm32wlxx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_SUBGHZ_MODULE_ENABLED
-  #include "stm32wlxx_hal_subghz.h"
-#endif /* HAL_SUBGHZ_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-  #include "stm32wlxx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
-  #include "stm32wlxx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
-  #include "stm32wlxx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
-  #include "stm32wlxx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_CONF_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h

@@ -1,466 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_cortex.h
-  * @author  MCD Application Team
-  * @brief   Header file of CORTEX HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32WLxx_HAL_CORTEX_H
-#define __STM32WLxx_HAL_CORTEX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CORTEX CORTEX
-  * @brief CORTEX HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
-  * @brief  MPU Region initialization structure
-  * @{
-  */
-typedef struct
-{
-  uint8_t    Enable;             /*!< Specifies the status of the region.
-                                      This parameter can be a value of @ref CORTEX_MPU_Region_Enable                */
-  uint8_t    Number;             /*!< Specifies the number of the region to protect.
-                                      This parameter can be a value of @ref CORTEX_MPU_Region_Number                */
-  uint32_t   BaseAddress;        /*!< Specifies the base address of the region to protect.
-                                                                                                                    */
-  uint8_t    Size;               /*!< Specifies the size of the region to protect.
-                                      This parameter can be a value of @ref CORTEX_MPU_Region_Size                  */
-  uint8_t    SubRegionDisable;   /*!< Specifies the number of the subregion protection to disable.
-                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF   */
-  uint8_t    TypeExtField;       /*!< Specifies the TEX field level.
-                                      This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                   */
-  uint8_t    AccessPermission;   /*!< Specifies the region access permission type.
-                                      This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
-  uint8_t    DisableExec;        /*!< Specifies the instruction access status.
-                                      This parameter can be a value of @ref CORTEX_MPU_Instruction_Access           */
-  uint8_t    IsShareable;        /*!< Specifies the shareability status of the protected region.
-                                      This parameter can be a value of @ref CORTEX_MPU_Access_Shareable             */
-  uint8_t    IsCacheable;        /*!< Specifies the cacheable status of the region protected.
-                                      This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable             */
-  uint8_t    IsBufferable;       /*!< Specifies the bufferable status of the protected region.
-                                      This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable            */
-} MPU_Region_InitTypeDef;
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
-  * @{
-  */
-#ifdef CORE_CM0PLUS
-#else
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
-  * @{
-  */
-#define NVIC_PRIORITYGROUP_0         (0x00000007U) /*!< 0 bit  for pre-emption priority,
-                                                                 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1         (0x00000006U) /*!< 1 bit  for pre-emption priority,
-                                                                 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2         (0x00000005U) /*!< 2 bits for pre-emption priority,
-                                                                 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3         (0x00000004U) /*!< 3 bits for pre-emption priority,
-                                                                 1 bit  for subpriority */
-#define NVIC_PRIORITYGROUP_4         (0x00000003U) /*!< 4 bits for pre-emption priority,
-                                                                 0 bit  for subpriority */
-/**
-  * @}
-  */
-#endif /* CORE_CM0PLUS */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
-  * @{
-  */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8       0x00000000U
-#define SYSTICK_CLKSOURCE_HCLK            0x00000004U
-
-/**
-  * @}
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
-  * @{
-  */
-#define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
-#define  MPU_HARDFAULT_NMI                (MPU_CTRL_HFNMIENA_Msk)
-#define  MPU_PRIVILEGED_DEFAULT           (MPU_CTRL_PRIVDEFENA_Msk)
-#define  MPU_HFNMI_PRIVDEF                (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
-  * @{
-  */
-#define  MPU_REGION_ENABLE           ((uint8_t)0x01)
-#define  MPU_REGION_DISABLE          ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
-  * @{
-  */
-#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
-#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
-  * @{
-  */
-#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
-  * @{
-  */
-#define  MPU_ACCESS_CACHEABLE        ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_CACHEABLE    ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
-  * @{
-  */
-#define  MPU_ACCESS_BUFFERABLE       ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_BUFFERABLE   ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
-  * @{
-  */
-#define  MPU_TEX_LEVEL0              ((uint8_t)0x00)
-#define  MPU_TEX_LEVEL1              ((uint8_t)0x01)
-#define  MPU_TEX_LEVEL2              ((uint8_t)0x02)
-#define  MPU_TEX_LEVEL4              ((uint8_t)0x04)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#else
-#define   MPU_REGION_SIZE_32B        ((uint8_t)0x04)
-#define   MPU_REGION_SIZE_64B        ((uint8_t)0x05)
-#define   MPU_REGION_SIZE_128B       ((uint8_t)0x06)
-#endif
-#define   MPU_REGION_SIZE_256B       ((uint8_t)0x07)
-#define   MPU_REGION_SIZE_512B       ((uint8_t)0x08)
-#define   MPU_REGION_SIZE_1KB        ((uint8_t)0x09)
-#define   MPU_REGION_SIZE_2KB        ((uint8_t)0x0A)
-#define   MPU_REGION_SIZE_4KB        ((uint8_t)0x0B)
-#define   MPU_REGION_SIZE_8KB        ((uint8_t)0x0C)
-#define   MPU_REGION_SIZE_16KB       ((uint8_t)0x0D)
-#define   MPU_REGION_SIZE_32KB       ((uint8_t)0x0E)
-#define   MPU_REGION_SIZE_64KB       ((uint8_t)0x0F)
-#define   MPU_REGION_SIZE_128KB      ((uint8_t)0x10)
-#define   MPU_REGION_SIZE_256KB      ((uint8_t)0x11)
-#define   MPU_REGION_SIZE_512KB      ((uint8_t)0x12)
-#define   MPU_REGION_SIZE_1MB        ((uint8_t)0x13)
-#define   MPU_REGION_SIZE_2MB        ((uint8_t)0x14)
-#define   MPU_REGION_SIZE_4MB        ((uint8_t)0x15)
-#define   MPU_REGION_SIZE_8MB        ((uint8_t)0x16)
-#define   MPU_REGION_SIZE_16MB       ((uint8_t)0x17)
-#define   MPU_REGION_SIZE_32MB       ((uint8_t)0x18)
-#define   MPU_REGION_SIZE_64MB       ((uint8_t)0x19)
-#define   MPU_REGION_SIZE_128MB      ((uint8_t)0x1A)
-#define   MPU_REGION_SIZE_256MB      ((uint8_t)0x1B)
-#define   MPU_REGION_SIZE_512MB      ((uint8_t)0x1C)
-#define   MPU_REGION_SIZE_1GB        ((uint8_t)0x1D)
-#define   MPU_REGION_SIZE_2GB        ((uint8_t)0x1E)
-#define   MPU_REGION_SIZE_4GB        ((uint8_t)0x1F)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
-  * @{
-  */
-#define  MPU_REGION_NO_ACCESS        ((uint8_t)0x00)
-#define  MPU_REGION_PRIV_RW          ((uint8_t)0x01)
-#define  MPU_REGION_PRIV_RW_URO      ((uint8_t)0x02)
-#define  MPU_REGION_FULL_ACCESS      ((uint8_t)0x03)
-#define  MPU_REGION_PRIV_RO          ((uint8_t)0x05)
-#define  MPU_REGION_PRIV_RO_URO      ((uint8_t)0x06)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
-  * @{
-  */
-#define  MPU_REGION_NUMBER0          ((uint8_t)0x00)
-#define  MPU_REGION_NUMBER1          ((uint8_t)0x01)
-#define  MPU_REGION_NUMBER2          ((uint8_t)0x02)
-#define  MPU_REGION_NUMBER3          ((uint8_t)0x03)
-#define  MPU_REGION_NUMBER4          ((uint8_t)0x04)
-#define  MPU_REGION_NUMBER5          ((uint8_t)0x05)
-#define  MPU_REGION_NUMBER6          ((uint8_t)0x06)
-#define  MPU_REGION_NUMBER7          ((uint8_t)0x07)
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
-  * @{
-  */
-
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
-  * @brief    Initialization and Configuration functions
-  * @{
-  */
-/* Initialization and Configuration functions *****************************/
-#ifdef CORE_CM0PLUS
-#else
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-#endif /* CORE_CM0PLUS */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
-  * @brief   Cortex control functions
-  * @{
-  */
-/* Peripheral Control functions *************************************************/
-#ifdef CORE_CM0PLUS
-uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn);
-#else
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority);
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-#endif /* CORE_CM0PLUS */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void HAL_SYSTICK_IRQHandler(void);
-void HAL_SYSTICK_Callback(void);
-
-#if (__MPU_PRESENT == 1U)
-void HAL_MPU_Enable(uint32_t MPU_Control);
-void HAL_MPU_Disable(void);
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
-  * @{
-  */
-#ifdef CORE_CM0PLUS
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)     ((PRIORITY) < 0x4U)
-#else
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
-#endif /* CORE_CM0PLUS */
-
-#define IS_NVIC_DEVICE_IRQ(IRQ)                   ((IRQ) > SysTick_IRQn)
-
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
-                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-
-#if (__MPU_PRESENT == 1)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
-                                     ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
-                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
-                                           ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
-                                ((TYPE) == MPU_TEX_LEVEL1)  || \
-                                ((TYPE) == MPU_TEX_LEVEL2)  || \
-                                ((TYPE) == MPU_TEX_LEVEL4))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
-                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER7))
-
-#if defined(CORE_CM0PLUS)
-#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_256B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4GB))
-#else
-#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4GB))
-#endif
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)      ((SUBREGION) < (uint16_t)0x00FFU)
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32WLxx_HAL_CORTEX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_crc.h

@@ -1,344 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_crc.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_CRC_H
-#define STM32WLxx_HAL_CRC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CRC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CRC_Exported_Types CRC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  CRC HAL State Structure definition
-  */
-typedef enum
-{
-  HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */
-  HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */
-  HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */
-  HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */
-  HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */
-} HAL_CRC_StateTypeDef;
-
-/**
-  * @brief CRC Init Structure definition
-  */
-typedef struct
-{
-  uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
-                                            If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
-                                            X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
-                                            In that case, there is no need to set GeneratingPolynomial field.
-                                            If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */
-
-  uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
-                                           If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
-                                           0xFFFFFFFF value. In that case, there is no need to set InitValue field.
-                                           If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set. */
-
-  uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
-                                           respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
-                                           e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
-                                           No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.   */
-
-  uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
-                                           Value can be either one of
-                                           @arg @ref CRC_POLYLENGTH_32B                  (32-bit CRC),
-                                           @arg @ref CRC_POLYLENGTH_16B                  (16-bit CRC),
-                                           @arg @ref CRC_POLYLENGTH_8B                   (8-bit CRC),
-                                           @arg @ref CRC_POLYLENGTH_7B                   (7-bit CRC). */
-
-  uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
-                                           is set to DEFAULT_INIT_VALUE_ENABLE.   */
-
-  uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
-                                           Can be either one of the following values
-                                           @arg @ref CRC_INPUTDATA_INVERSION_NONE       no input data inversion
-                                           @arg @ref CRC_INPUTDATA_INVERSION_BYTE       byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
-                                           @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD   halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
-                                           @arg @ref CRC_INPUTDATA_INVERSION_WORD       word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
-
-  uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
-                                            Can be either
-                                            @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion,
-                                            @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted into 0x22CC4488 */
-} CRC_InitTypeDef;
-
-/**
-  * @brief  CRC Handle Structure definition
-  */
-typedef struct
-{
-  CRC_TypeDef                 *Instance;   /*!< Register base address        */
-
-  CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */
-
-  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */
-
-  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */
-
-  uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
-                                            Can be either
-                                            @arg @ref CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes (8-bit data)
-                                            @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of half-words (16-bit data)
-                                            @arg @ref CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words (32-bit data)
-
-                                           Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
-                                           must occur if InputBufferFormat is not one of the three values listed above  */
-} CRC_HandleTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Constants CRC Exported Constants
-  * @{
-  */
-
-/** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial
-  * @{
-  */
-#define DEFAULT_CRC32_POLY      0x04C11DB7U  /*!<  X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Default_InitValue    Default CRC computation initialization value
-  * @{
-  */
-#define DEFAULT_CRC_INITVALUE   0xFFFFFFFFU  /*!< Initial CRC default value */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used
-  * @{
-  */
-#define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00U)  /*!< Enable default generating polynomial 0x04C11DB7  */
-#define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01U)  /*!< Disable default generating polynomial 0x04C11DB7 */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used
-  * @{
-  */
-#define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00U) /*!< Enable initial CRC default value  */
-#define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01U) /*!< Disable initial CRC default value */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
-  * @{
-  */
-#define CRC_POLYLENGTH_32B                  0x00000000U        /*!< Resort to a 32-bit long generating polynomial */
-#define CRC_POLYLENGTH_16B                  CRC_CR_POLYSIZE_0  /*!< Resort to a 16-bit long generating polynomial */
-#define CRC_POLYLENGTH_8B                   CRC_CR_POLYSIZE_1  /*!< Resort to a 8-bit long generating polynomial  */
-#define CRC_POLYLENGTH_7B                   CRC_CR_POLYSIZE    /*!< Resort to a 7-bit long generating polynomial  */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
-  * @{
-  */
-#define HAL_CRC_LENGTH_32B     32U          /*!< 32-bit long CRC */
-#define HAL_CRC_LENGTH_16B     16U          /*!< 16-bit long CRC */
-#define HAL_CRC_LENGTH_8B       8U          /*!< 8-bit long CRC  */
-#define HAL_CRC_LENGTH_7B       7U          /*!< 7-bit long CRC  */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
-  * @{
-  */
-/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
- * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
- * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
- * the CRC APIs to provide a correct result */
-#define CRC_INPUTDATA_FORMAT_UNDEFINED             0x00000000U  /*!< Undefined input data format    */
-#define CRC_INPUTDATA_FORMAT_BYTES                 0x00000001U  /*!< Input data in byte format      */
-#define CRC_INPUTDATA_FORMAT_HALFWORDS             0x00000002U  /*!< Input data in half-word format */
-#define CRC_INPUTDATA_FORMAT_WORDS                 0x00000003U  /*!< Input data in word format      */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Aliases CRC API aliases
-  * @{
-  */
-#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */
-#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CRC_Exported_Macros CRC Exported Macros
-  * @{
-  */
-
-/** @brief Reset CRC handle state.
-  * @param  __HANDLE__ CRC handle.
-  * @retval None
-  */
-#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
-
-/**
-  * @brief  Reset CRC Data Register.
-  * @param  __HANDLE__ CRC handle
-  * @retval None
-  */
-#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
-
-/**
-  * @brief  Set CRC INIT non-default value
-  * @param  __HANDLE__ CRC handle
-  * @param  __INIT__ 32-bit initial value
-  * @retval None
-  */
-#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
-
-/**
-  * @brief Store data in the Independent Data (ID) register.
-  * @param __HANDLE__ CRC handle
-  * @param __VALUE__  Value to be stored in the ID register
-  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
-  * @retval None
-  */
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
-
-/**
-  * @brief Return the data stored in the Independent Data (ID) register.
-  * @param __HANDLE__ CRC handle
-  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits
-  * @retval Value of the ID register
-  */
-#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
-/**
-  * @}
-  */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup  CRC_Private_Macros CRC Private Macros
-  * @{
-  */
-
-#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
-                                        ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
-
-
-#define IS_DEFAULT_INIT_VALUE(VALUE)  (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
-                                       ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
-
-#define IS_CRC_POL_LENGTH(LENGTH)     (((LENGTH) == CRC_POLYLENGTH_32B) || \
-                                       ((LENGTH) == CRC_POLYLENGTH_16B) || \
-                                       ((LENGTH) == CRC_POLYLENGTH_8B)  || \
-                                       ((LENGTH) == CRC_POLYLENGTH_7B))
-
-#define IS_CRC_INPUTDATA_FORMAT(FORMAT)           (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES)     || \
-                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
-                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
-
-/**
-  * @}
-  */
-
-/* Include CRC HAL Extended module */
-#include "stm32wlxx_hal_crc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRC_Exported_Functions CRC Exported Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
-HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
-void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions ***********************************************/
-/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
-  * @{
-  */
-uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-/**
-  * @}
-  */
-
-/* Peripheral State and Error functions ***************************************/
-/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
-  * @{
-  */
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_crc_ex.h

@@ -1,153 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_crc_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRC HAL extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_CRC_EX_H
-#define STM32WLxx_HAL_CRC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CRCEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
-  * @{
-  */
-#define CRC_INPUTDATA_INVERSION_NONE               0x00000000U     /*!< No input data inversion            */
-#define CRC_INPUTDATA_INVERSION_BYTE               CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion     */
-#define CRC_INPUTDATA_INVERSION_HALFWORD           CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
-#define CRC_INPUTDATA_INVERSION_WORD               CRC_CR_REV_IN   /*!< Word-wise input data inversion     */
-/**
-  * @}
-  */
-
-/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
-  * @{
-  */
-#define CRC_OUTPUTDATA_INVERSION_DISABLE         0x00000000U       /*!< No output data inversion       */
-#define CRC_OUTPUTDATA_INVERSION_ENABLE          CRC_CR_REV_OUT    /*!< Bit-wise output data inversion */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Set CRC output reversal
-  * @param  __HANDLE__ CRC handle
-  * @retval None
-  */
-#define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
-
-/**
-  * @brief  Unset CRC output reversal
-  * @param  __HANDLE__ CRC handle
-  * @retval None
-  */
-#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
-
-/**
-  * @brief  Set CRC non-default polynomial
-  * @param  __HANDLE__ CRC handle
-  * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
-  * @retval None
-  */
-#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
-  * @{
-  */
-
-#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE)     || \
-                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE)     || \
-                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
-                                                   ((MODE) == CRC_INPUTDATA_INVERSION_WORD))
-
-#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
-                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup CRCEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CRCEx_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
-HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
-HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_CRC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cryp.h

@@ -1,648 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_cryp.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRYP HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_CRYP_H
-#define STM32WLxx_HAL_CRYP_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-
-
-/** @defgroup CRYP CRYP
-  * @brief CRYP HAL module driver.
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Types CRYP Exported Types
-  * @{
-  */
-
-/**
-  * @brief CRYP Init Structure definition
-  */
-
-typedef struct
-{
-  uint32_t DataType;                   /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
-                                        This parameter can be a value of @ref CRYP_Data_Type */
-  uint32_t KeySize;                    /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
-                                        128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
-  uint32_t *pKey;                      /*!< The key used for encryption/decryption */
-  uint32_t *pInitVect;                 /*!< The initialization vector used also as initialization
-                                         counter in CTR mode */
-  uint32_t Algorithm;                  /*!<  DES/ TDES Algorithm ECB/CBC
-                                        AES Algorithm ECB/CBC/CTR/GCM or CCM
-                                        This parameter can be a value of @ref CRYP_Algorithm_Mode */
-  uint32_t *Header;                    /*!< used only in AES GCM and CCM Algorithm for authentication,
-                                        GCM : also known as Additional Authentication Data
-                                        CCM : named B1 composed of the associated data length and Associated Data. */
-  uint32_t HeaderSize;                 /*!< The size of header buffer */
-  uint32_t *B0;                        /*!< B0 is first authentication block used only  in AES CCM mode */
-  uint32_t DataWidthUnit;              /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
-  uint32_t HeaderWidthUnit;            /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
-  uint32_t KeyIVConfigSkip;            /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
-                                           Vector only once and to skip configuration for consecutive processings.
-                                           This parameter can be a value of @ref CRYP_Configuration_Skip */
-
-} CRYP_ConfigTypeDef;
-
-
-/**
-  * @brief  CRYP State Structure definition
-  */
-
-typedef enum
-{
-  HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */
-  HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */
-  HAL_CRYP_STATE_BUSY              = 0x02U,  /*!< CRYP BUSY, internal processing is ongoing  */
-#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
-  HAL_CRYP_STATE_SUSPENDED         = 0x03U,   /*!< CRYP suspended                        */
-#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
-} HAL_CRYP_STATETypeDef;
-
-#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
-/**
-  * @brief HAL CRYP mode suspend definitions
-  */
-typedef enum
-{
-  HAL_CRYP_SUSPEND_NONE            = 0x00U,    /*!< CRYP processing suspension not requested */
-  HAL_CRYP_SUSPEND                 = 0x01U     /*!< CRYP processing suspension requested     */
-}HAL_SuspendTypeDef;
-#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
-
-/**
-  * @brief  CRYP handle Structure definition
-  */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
-typedef struct __CRYP_HandleTypeDef
-#else
-typedef struct
-#endif
-{
-  AES_TypeDef                       *Instance;        /*!< AES Register base address */
-
-  CRYP_ConfigTypeDef                Init;             /*!< CRYP required parameters */
-
-  FunctionalState                   AutoKeyDerivation;   /*!< Used only in TinyAES to allow to bypass or not key write-up before decryption.
-                                                         This parameter can be a value of ENABLE/DISABLE */
-
-  uint32_t                          *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
-  uint32_t                          *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
-  __IO uint16_t                     CrypHeaderCount;  /*!< Counter of header data in words */
-
-  __IO uint16_t                     CrypInCount;      /*!< Counter of input data in words */
-
-  __IO uint16_t                     CrypOutCount;     /*!< Counter of output data in words */
-
-  uint16_t                          Size;             /*!< Length of input data */
-
-  uint32_t                          Phase;            /*!< CRYP peripheral phase */
-
-  DMA_HandleTypeDef                 *hdmain;          /*!< CRYP In DMA handle parameters */
-
-  DMA_HandleTypeDef                 *hdmaout;         /*!< CRYP Out DMA handle parameters */
-
-  HAL_LockTypeDef                   Lock;             /*!< CRYP locking object */
-
-  __IO  HAL_CRYP_STATETypeDef       State;            /*!< CRYP peripheral state */
-
-  __IO uint32_t                     ErrorCode;        /*!< CRYP peripheral error code */
-
-  uint32_t                          KeyIVConfig;      /*!< CRYP peripheral Key and IV configuration flag, used when
-                                                           configuration can be skipped */
-
-  uint32_t                          SizesSum;         /*!< Sum of successive payloads lengths (in bytes), stored
-                                                           for a single signature computation after several
-                                                           messages processing */
-
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
-  void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);      /*!< CRYP Input FIFO transfer completed callback  */
-  void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);     /*!< CRYP Output FIFO transfer completed callback */
-  void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp);       /*!< CRYP Error callback */
-
-  void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp);    /*!< CRYP Msp Init callback  */
-  void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp);  /*!< CRYP Msp DeInit callback  */
-
-#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
-
-#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
-
-  __IO HAL_SuspendTypeDef     SuspendRequest;          /*!< CRYP peripheral suspension request flag */
-
-  CRYP_ConfigTypeDef          Init_saved;              /*!< copy of CRYP required parameters when processing is suspended */
-
-  uint32_t                    *pCrypInBuffPtr_saved;   /*!< copy of CRYP input pointer when processing is suspended */
-
-  uint32_t                    *pCrypOutBuffPtr_saved;  /*!< copy of CRYP output pointer when processing is suspended */
-
-  uint32_t                    CrypInCount_saved;       /*!< copy of CRYP input data counter when processing is suspended */
-
-  uint32_t                    CrypOutCount_saved;      /*!< copy of CRYP output data counter when processing is suspended */
-
-  uint32_t                    Phase_saved;             /*!< copy of CRYP authentication phase when processing is suspended */
-
-  __IO HAL_CRYP_STATETypeDef  State_saved;             /*!< copy of CRYP peripheral state when processing is suspended */
-
-  uint32_t                    IV_saved[4];             /*!< copy of Initialisation Vector registers */
-
-  uint32_t                    SUSPxR_saved[8];         /*!< copy of suspension registers */
-
-  uint32_t                    CR_saved;                /*!< copy of CRYP control register  when processing is suspended*/
-
-  uint32_t                    Key_saved[8];            /*!< copy of key registers */
-
-  uint16_t                    Size_saved;              /*!< copy of input buffer size */
-
-  uint16_t                    CrypHeaderCount_saved;   /*!< copy of CRYP header data counter when processing is suspended */
-
-  uint32_t                    SizesSum_saved;          /*!< copy of SizesSum when processing is suspended */
-
-  uint32_t                    ResumingFlag;            /*!< resumption flag to bypass steps already carried out */
-
-  FunctionalState             AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */
-
-#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
-
-} CRYP_HandleTypeDef;
-
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
-/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
-  * @brief  HAL CRYP Callback ID enumeration definition
-  * @{
-  */
-typedef enum
-{
-  HAL_CRYP_MSPINIT_CB_ID           = 0x00U,    /*!< CRYP MspInit callback ID                        */
-  HAL_CRYP_MSPDEINIT_CB_ID         = 0x01U,     /*!< CRYP MspDeInit callback ID                      */
-  HAL_CRYP_INPUT_COMPLETE_CB_ID    = 0x02U,    /*!< CRYP Input FIFO transfer completed callback ID  */
-  HAL_CRYP_OUTPUT_COMPLETE_CB_ID   = 0x03U,    /*!< CRYP Output FIFO transfer completed callback ID */
-  HAL_CRYP_ERROR_CB_ID             = 0x04U,    /*!< CRYP Error callback ID                          */
-} HAL_CRYP_CallbackIDTypeDef;
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
-  * @brief  HAL CRYP Callback pointer definition
-  * @{
-  */
-
-typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< pointer to a common CRYP callback function */
-
-/**
-  * @}
-  */
-
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
-  * @{
-  */
-
-/** @defgroup CRYP_Error_Definition   CRYP Error Definition
-  * @{
-  */
-#define HAL_CRYP_ERROR_NONE              0x00000000U  /*!< No error        */
-#define HAL_CRYP_ERROR_WRITE             0x00000001U  /*!< Write error     */
-#define HAL_CRYP_ERROR_READ              0x00000002U  /*!< Read error      */
-#define HAL_CRYP_ERROR_DMA               0x00000004U  /*!< DMA error       */
-#define HAL_CRYP_ERROR_BUSY              0x00000008U  /*!< Busy flag error */
-#define HAL_CRYP_ERROR_TIMEOUT           0x00000010U  /*!< Timeout error */
-#define HAL_CRYP_ERROR_NOT_SUPPORTED     0x00000020U  /*!< Not supported mode */
-#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U  /*!< Sequence are not respected only for GCM or CCM */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
-#define  HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)    /*!< Invalid Callback error  */
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
-  * @{
-  */
-
-#define CRYP_DATAWIDTHUNIT_WORD   0x00000000U  /*!< By default, size unit is word */
-#define CRYP_DATAWIDTHUNIT_BYTE   0x00000001U  /*!< By default, size unit is byte */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
-  * @{
-  */
-
-#define CRYP_HEADERWIDTHUNIT_WORD   0x00000000U  /*!< By default, header size unit is word */
-#define CRYP_HEADERWIDTHUNIT_BYTE   0x00000001U  /*!< By default, header size unit is byte */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
-  * @{
-  */
-
-#define CRYP_AES_ECB            0x00000000U                       /*!< Electronic codebook chaining algorithm                   */
-#define CRYP_AES_CBC            AES_CR_CHMOD_0                    /*!< Cipher block chaining algorithm                          */
-#define CRYP_AES_CTR            AES_CR_CHMOD_1                    /*!< Counter mode chaining algorithm                          */
-#define CRYP_AES_GCM_GMAC       (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
-#define CRYP_AES_CCM            AES_CR_CHMOD_2                    /*!< Counter with Cipher Mode                                 */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Key_Size CRYP Key Size
-  * @{
-  */
-
-#define CRYP_KEYSIZE_128B         0x00000000U          /*!< 128-bit long key */
-#define CRYP_KEYSIZE_256B         AES_CR_KEYSIZE       /*!< 256-bit long key */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Data_Type CRYP Data Type
-  * @{
-  */
-
-#define CRYP_DATATYPE_32B         0x00000000U  /*!< 32-bit data type (no swapping)        */
-#define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0       /*!< 16-bit data type (half-word swapping) */
-#define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1       /*!< 8-bit data type (byte swapping)       */
-#define CRYP_DATATYPE_1B          AES_CR_DATATYPE         /*!< 1-bit data type (bit swapping)        */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Interrupt  CRYP Interrupt
-  * @{
-  */
-
-#define CRYP_IT_CCFIE     AES_CR_CCFIE /*!< Computation Complete interrupt enable */
-#define CRYP_IT_ERRIE     AES_CR_ERRIE /*!< Error interrupt enable                */
-#define CRYP_IT_WRERR     AES_SR_WRERR  /*!< Write Error           */
-#define CRYP_IT_RDERR     AES_SR_RDERR  /*!< Read Error            */
-#define CRYP_IT_CCF       AES_SR_CCF    /*!< Computation completed */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Flags CRYP Flags
-  * @{
-  */
-
-/* status flags */
-#define CRYP_FLAG_BUSY    AES_SR_BUSY   /*!< GCM process suspension forbidden */
-#define CRYP_FLAG_WRERR   AES_SR_WRERR  /*!< Write Error                      */
-#define CRYP_FLAG_RDERR   AES_SR_RDERR  /*!< Read error                       */
-#define CRYP_FLAG_CCF     AES_SR_CCF    /*!< Computation completed            */
-/* clearing flags */
-#define CRYP_CCF_CLEAR    AES_CR_CCFC   /*!< Computation Complete Flag Clear */
-#define CRYP_ERR_CLEAR    AES_CR_ERRC   /*!< Error Flag Clear  */
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
-  * @{
-  */
-
-#define CRYP_KEYIVCONFIG_ALWAYS        0x00000000U            /*!< Peripheral Key and IV configuration to do systematically */
-#define CRYP_KEYIVCONFIG_ONCE          0x00000001U            /*!< Peripheral Key and IV configuration to do only once      */
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
-  * @{
-  */
-
-/** @brief Reset CRYP handle state
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @retval None
-  */
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
-#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
-                                                      (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
-                                                      (__HANDLE__)->MspInitCallback = NULL;\
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
-                                                     }while(0U)
-#else
-#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Enable/Disable the CRYP peripheral.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @retval None
-  */
-
-#define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  AES_CR_EN)
-#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~AES_CR_EN)
-
-
-/** @brief  Check whether the specified CRYP status flag is set or not.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values for TinyAES:
-  *            @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
-  *            @arg @ref CRYP_IT_WRERR Write Error
-  *            @arg @ref CRYP_IT_RDERR Read Error
-  *            @arg @ref CRYP_IT_CCF Computation Complete
-  *         This parameter can be one of the following values for CRYP:
-  *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
-  *                                 or a key preparation (for AES decryption).
-  *            @arg CRYP_FLAG_IFEM: Input FIFO is empty
-  *            @arg CRYP_FLAG_IFNF: Input FIFO is not full
-  *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
-  *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty
-  *            @arg CRYP_FLAG_OFFU: Output FIFO is full
-  *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
- * @retval The state of __FLAG__ (TRUE or FALSE).
-  */
-
-#define CRYP_FLAG_MASK  0x0000001FU
-#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the CRYP pending status flag.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __FLAG__ specifies the flag to clear.
-  *         This parameter can be one of the following values:
-  *            @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
-  *            @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
-  * @retval None
-  */
-
-#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
-
-
-/** @brief  Check whether the specified CRYP interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param __INTERRUPT__ CRYP interrupt source to check
-  *         This parameter can be one of the following values for TinyAES:
-  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
-  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
-  * @retval State of interruption (TRUE or FALSE).
-  */
-
-#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief  Check whether the specified CRYP interrupt is set or not.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __INTERRUPT__ specifies the interrupt to check.
-  *         This parameter can be one of the following values for TinyAES:
-  *            @arg @ref CRYP_IT_WRERR Write Error
-  *            @arg @ref CRYP_IT_RDERR Read Error
-  *            @arg @ref CRYP_IT_CCF  Computation Complete
-  *         This parameter can be one of the following values for CRYP:
-  *            @arg CRYP_IT_INI: Input FIFO service masked interrupt status
-  *            @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
-  * @retval The state of __INTERRUPT__ (TRUE or FALSE).
-  */
-
-#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Enable the CRYP interrupt.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __INTERRUPT__ CRYP Interrupt.
-  *         This parameter can be one of the following values for TinyAES:
-  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
-  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
-  *         This parameter can be one of the following values for CRYP:
-  *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
-  *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
-  * @retval None
-  */
-
-#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the CRYP interrupt.
-  * @param  __HANDLE__ specifies the CRYP handle.
-  * @param  __INTERRUPT__ CRYP Interrupt.
-  *         This parameter can be one of the following values for TinyAES:
-  *            @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
-  *            @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
-  *         This parameter can be one of the following values for CRYP:
-  *            @ CRYP_IT_INI : Input FIFO service interrupt mask.
-  *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
-  * @retval None
-  */
-
-#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-
-/**
-  * @}
-  */
-
-/* Include CRYP HAL Extended module */
-#include "stm32wlxx_hal_cryp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
-  * @{
-  */
-
-/** @addtogroup CRYP_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
-HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
-#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
-#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
-void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
-#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
-/**
-  * @}
-  */
-
-/** @addtogroup CRYP_Exported_Functions_Group2
-  * @{
-  */
-
-/* encryption/decryption ***********************************/
-HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup CRYP_Exported_Functions_Group3
-  * @{
-  */
-/* Interrupt Handler functions  **********************************************/
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
-void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
-uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup CRYP_Private_Macros CRYP Private Macros
-  * @{
-  */
-
-/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
-  * @{
-  */
-
-#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB)      || \
-                                      ((ALGORITHM)  == CRYP_AES_CBC)     || \
-                                      ((ALGORITHM)  == CRYP_AES_CTR)     || \
-                                      ((ALGORITHM)  == CRYP_AES_GCM_GMAC)|| \
-                                      ((ALGORITHM)  == CRYP_AES_CCM))
-
-
-#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B)   || \
-                                 ((KEYSIZE) == CRYP_KEYSIZE_256B))
-
-#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
-                                   ((DATATYPE) == CRYP_DATATYPE_16B) || \
-                                   ((DATATYPE) == CRYP_DATATYPE_8B)  || \
-                                   ((DATATYPE) == CRYP_DATATYPE_1B))
-
-#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
-                             ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
-
-#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE)                                             \
-       (((((ALGO) == CRYP_AES_CTR)) &&                                             \
-            ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U))           || \
-             (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U))))        || \
-         (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC)                  || \
-          ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Constants CRYP Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup CRYP_Private_Defines CRYP Private Defines
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Variables CRYP Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRYP_Private_Functions CRYP Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_CRYP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cryp_ex.h

@@ -1,133 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_cryp_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of CRYPEx HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_CRYP_EX_H
-#define STM32WLxx_HAL_CRYP_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-
-
-/** @defgroup CRYPEx CRYPEx
-  * @brief CRYP Extension HAL module driver.
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
-  * @{
-  */
-
-/**
- * @}
- */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
-  * @{
-  */
-
-/** @addtogroup CRYPEx_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
-
-/**
-  * @}
-  */
-
-/** @addtogroup CRYPEx_Exported_Functions_Group2
-  * @{
-  */
-void  HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
-void  HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_CRYP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dac.h

@@ -1,507 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_dac.h
-  * @author  MCD Application Team
-  * @brief   Header file of DAC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_DAC_H
-#define STM32WLxx_HAL_DAC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-#if defined(DAC)
-
-/** @addtogroup DAC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Types DAC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
-  HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
-  HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
-  HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
-  HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
-
-} HAL_DAC_StateTypeDef;
-
-/**
-  * @brief  DAC handle Structure definition
-  */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-typedef struct __DAC_HandleTypeDef
-#else
-typedef struct
-#endif
-{
-  DAC_TypeDef                 *Instance;     /*!< Register base address             */
-
-  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
-
-  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
-
-  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
-
-  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
-
-  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  void (* ConvCpltCallbackCh1)            (struct __DAC_HandleTypeDef *hdac);
-  void (* ConvHalfCpltCallbackCh1)        (struct __DAC_HandleTypeDef *hdac);
-  void (* ErrorCallbackCh1)               (struct __DAC_HandleTypeDef *hdac);
-  void (* DMAUnderrunCallbackCh1)         (struct __DAC_HandleTypeDef *hdac);
-
-  void (* MspInitCallback)                (struct __DAC_HandleTypeDef *hdac);
-  void (* MspDeInitCallback )             (struct __DAC_HandleTypeDef *hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-} DAC_HandleTypeDef;
-
-/**
-  * @brief   DAC Configuration sample and hold Channel structure definition
-  */
-typedef struct
-{
-  uint32_t DAC_SampleTime ;          /*!< Specifies the Sample time for the selected channel.
-                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
-                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
-
-  uint32_t DAC_HoldTime ;            /*!< Specifies the hold time for the selected channel
-                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
-                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
-
-  uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel
-                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
-                                          This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
-} DAC_SampleAndHoldConfTypeDef;
-
-/**
-  * @brief   DAC Configuration regular Channel structure definition
-  */
-typedef struct
-{
-  uint32_t DAC_SampleAndHold;            /*!< Specifies whether the DAC mode.
-                                              This parameter can be a value of @ref DAC_SampleAndHold */
-
-  uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
-                                              This parameter can be a value of @ref DAC_trigger_selection */
-
-  uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                               This parameter can be a value of @ref DAC_output_buffer */
-
-  uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
-                                              This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
-
-  uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode
-                                              This parameter must be a value of @ref DAC_UserTrimming
-                                              DAC_UserTrimming is either factory or user trimming */
-
-  uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value
-                                               i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
-                                               This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
-  DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */
-
-} DAC_ChannelConfTypeDef;
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL DAC Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_DAC_CH1_COMPLETE_CB_ID                 = 0x00U,  /*!< DAC CH1 Complete Callback ID      */
-  HAL_DAC_CH1_HALF_COMPLETE_CB_ID            = 0x01U,  /*!< DAC CH1 half Complete Callback ID */
-  HAL_DAC_CH1_ERROR_ID                       = 0x02U,  /*!< DAC CH1 error Callback ID         */
-  HAL_DAC_CH1_UNDERRUN_CB_ID                 = 0x03U,  /*!< DAC CH1 underrun Callback ID      */
-  HAL_DAC_MSPINIT_CB_ID                      = 0x08U,  /*!< DAC MspInit Callback ID           */
-  HAL_DAC_MSPDEINIT_CB_ID                    = 0x09U,  /*!< DAC MspDeInit Callback ID         */
-  HAL_DAC_ALL_CB_ID                          = 0x0AU   /*!< DAC All ID                        */
-} HAL_DAC_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL DAC Callback pointer definition
-  */
-typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants DAC Exported Constants
-  * @{
-  */
-
-/** @defgroup DAC_Error_Code DAC Error Code
-  * @{
-  */
-#define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DMA underrun error   */
-#define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
-#define  HAL_DAC_ERROR_TIMEOUT           0x08U    /*!< Timeout error                     */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-#define HAL_DAC_ERROR_INVALID_CALLBACK   0x10U    /*!< Invalid callback error            */
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_trigger_selection DAC trigger selection
-  * @{
-  */
-#define DAC_TRIGGER_NONE       (0x00000000UL)                                                    /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
-#define DAC_TRIGGER_SOFTWARE   (DAC_CR_TEN1)                                                     /*!< Conversion started by software trigger for DAC channel */
-#define DAC_TRIGGER_T1_TRGO    (DAC_CR_TSEL1_0 | DAC_CR_TEN1)                                    /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T2_TRGO    (DAC_CR_TSEL1_1 | DAC_CR_TEN1)                                    /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)  /*!< LPTIM1_OUT selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)                   /*!< LPTIM2_OUT selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)  /*!< LPTIM3_OUT selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9    (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)  /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_output_buffer DAC output buffer
-  * @{
-  */
-#define DAC_OUTPUTBUFFER_ENABLE            0x00000000U
-#define DAC_OUTPUTBUFFER_DISABLE           (DAC_MCR_MODE1_1)
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Channel_selection DAC Channel selection
-  * @{
-  */
-#define DAC_CHANNEL_1                      0x00000000U
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data_alignment DAC data alignment
-  * @{
-  */
-#define DAC_ALIGN_12B_R                    0x00000000U
-#define DAC_ALIGN_12B_L                    0x00000004U
-#define DAC_ALIGN_8B_R                     0x00000008U
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_flags_definition DAC flags definition
-  * @{
-  */
-#define DAC_FLAG_DMAUDR1                   (DAC_SR_DMAUDR1)
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_IT_definition  DAC IT definition
-  * @{
-  */
-#define DAC_IT_DMAUDR1                   (DAC_SR_DMAUDR1)
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
-  * @{
-  */
-#define DAC_CHIPCONNECT_DISABLE    (0x00000000UL)
-#define DAC_CHIPCONNECT_ENABLE     (DAC_MCR_MODE1_0)
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_UserTrimming DAC User Trimming
-  * @{
-  */
-#define DAC_TRIMMING_FACTORY        (0x00000000UL)        /*!< Factory trimming */
-#define DAC_TRIMMING_USER           (0x00000001UL)        /*!< User trimming */
-/**
-  * @}
-  */
-
-/** @defgroup DAC_SampleAndHold DAC power mode
-  * @{
-  */
-#define DAC_SAMPLEANDHOLD_DISABLE     (0x00000000UL)
-#define DAC_SAMPLEANDHOLD_ENABLE      (DAC_MCR_MODE1_2)
-
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Macros DAC Exported Macros
-  * @{
-  */
-
-/** @brief Reset DAC handle state.
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @retval None
-  */
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
-                                                      (__HANDLE__)->State             = HAL_DAC_STATE_RESET; \
-                                                      (__HANDLE__)->MspInitCallback   = NULL;                \
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;                \
-                                                     } while(0)
-#else
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/** @brief Enable the DAC channel.
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __DAC_Channel__ specifies the DAC channel
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
-  ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
-
-/** @brief Disable the DAC channel.
-  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __DAC_Channel__ specifies the DAC channel.
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
-  ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
-
-/** @brief Set DHR12R1 alignment.
-  * @param  __ALIGNMENT__ specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
-
-
-/** @brief  Set DHR12RD alignment.
-  * @param  __ALIGNMENT__ specifies the DAC alignment
-  * @retval None
-  */
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
-
-/** @brief Enable the DAC interrupt.
-  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __INTERRUPT__ specifies the DAC interrupt.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-
-/** @brief Disable the DAC interrupt.
-  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __INTERRUPT__ specifies the DAC interrupt.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-
-/** @brief  Check whether the specified DAC interrupt source is enabled or not.
-  * @param __HANDLE__ DAC handle
-  * @param __INTERRUPT__ DAC interrupt source to check
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
-  * @retval State of interruption (SET or RESET)
-  */
-#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief  Get the selected DAC's flag status.
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __FLAG__ specifies the DAC flag to get.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
-  * @retval None
-  */
-#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the DAC's flag.
-  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __FLAG__ specifies the DAC flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
-  * @retval None
-  */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Macros DAC Private Macros
-  * @{
-  */
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
-                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-
-#define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1)
-
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
-                             ((ALIGN) == DAC_ALIGN_12B_L) || \
-                             ((ALIGN) == DAC_ALIGN_8B_R))
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
-
-#define IS_DAC_REFRESHTIME(TIME)   ((TIME) <= 0x000000FFUL)
-
-/**
-  * @}
-  */
-
-/* Include DAC HAL Extended module */
-#include "stm32wlxx_hal_dac_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DAC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
-                                    uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
-
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
-
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-
-#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-/* DAC callback registering/unregistering */
-HAL_StatusTypeDef     HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
-                                               pDAC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
-
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Private_Functions DAC Private Functions
-  * @{
-  */
-void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DAC */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /*STM32WLxx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dac_ex.h

@@ -1,205 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_dac_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of DAC HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_DAC_EX_H
-#define STM32WLxx_HAL_DAC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-#if defined(DAC)
-
-/** @addtogroup DACEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
-  * @brief  HAL State structures definition
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
-  * @{
-  */
-
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
-  * @{
-  */
-#define DAC_LFSRUNMASK_BIT0                0x00000000UL                                                        /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0             (                                                   DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0             (                                  DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0             (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0             (                 DAC_CR_MAMP1_2                                  ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0             (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0             (DAC_CR_MAMP1_3                                                   ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0             (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1            0x00000000UL                                                        /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3            (                                                   DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7            (                                  DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15           (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31           (                 DAC_CR_MAMP1_2                                  ) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63           (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511          (DAC_CR_MAMP1_3                                                   ) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023         (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup DACEx_Private_Macros DACEx Private Macros
-  * @{
-  */
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \
-                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE)   || \
-                                 ((TRIGGER) == DAC_TRIGGER_T1_TRGO)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
-                                 ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
-                                 ((TRIGGER) == DAC_TRIGGER_LPTIM3_OUT) || \
-                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9))
-
-#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
-
-#define IS_DAC_HOLDTIME(TIME)   ((TIME) <= 0x000003FFU)
-
-#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
-                                    ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
-
-#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
-
-#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
-
-#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
-                                         ((CONNECT) == DAC_CHIPCONNECT_ENABLE))
-
-#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
-                                   ((TRIMMING) == DAC_TRIMMING_USER))
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/* Extended features functions ***********************************************/
-
-/** @addtogroup DACEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DACEx_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup DACEx_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-
-HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
-                                            uint32_t NewTrimmingValue);
-uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DAC */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*STM32WLxx_HAL_DAC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h

@@ -1,212 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_def.h
-  * @author  MCD Application Team
-  * @brief   This file contains HAL common defines, enumeration, macros and
-  *          structures definitions.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32WLxx_HAL_DEF
-#define __STM32WLxx_HAL_DEF
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx.h"
-#include "Legacy/stm32_hal_legacy.h"   /* Aliases file for old names compatibility */
-#include <stddef.h>
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
-  * @brief  HAL Status structures definition
-  */
-typedef enum
-{
-  HAL_OK       = 0x00,
-  HAL_ERROR    = 0x01,
-  HAL_BUSY     = 0x02,
-  HAL_TIMEOUT  = 0x03
-} HAL_StatusTypeDef;
-
-/**
-  * @brief  HAL Lock structures definition
-  */
-typedef enum
-{
-  HAL_UNLOCKED = 0x00,
-  HAL_LOCKED   = 0x01
-} HAL_LockTypeDef;
-
-/* Exported macros -----------------------------------------------------------*/
-
-#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
-
-#define HAL_MAX_DELAY      0xFFFFFFFFU
-
-#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
-#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
-                        do{                                                      \
-                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
-                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
-                          } while(0)
-                         
-/** @brief Reset the Handle's State field.
-  * @param __HANDLE__ specifies the Peripheral Handle.
-  * @note  This macro can be used for the following purpose: 
-  *          - When the Handle is declared as local variable; before passing it as parameter
-  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
-  *            to set to 0 the Handle's "State" field.
-  *            Otherwise, "State" field may have any random value and the first time the function 
-  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
-  *            (i.e. HAL_PPP_MspInit() will not be executed).
-  *          - When there is a need to reconfigure the low level hardware: instead of calling
-  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
-  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
-  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
-  * @retval None
-  */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
-
-#if (USE_RTOS == 1)
-  /* Reserved for future use */
-  #error " USE_RTOS should be 0 in the current HAL release "
-#else
-  #define __HAL_LOCK(__HANDLE__)                                           \
-                                do{                                        \
-                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
-                                    {                                      \
-                                       return HAL_BUSY;                    \
-                                    }                                      \
-                                    else                                   \
-                                    {                                      \
-                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
-                                    }                                      \
-                                  }while (0)
-
-  #define __HAL_UNLOCK(__HANDLE__)                                          \
-                                  do{                                       \
-                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
-                                    }while (0)
-#endif /* USE_RTOS */
-
-
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
-  #ifndef __weak
-    #define __weak  __attribute__((weak))
-  #endif
-  #ifndef __packed
-    #define __packed  __attribute__((packed))
-  #endif
-#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
-  #ifndef __weak
-    #define __weak   __attribute__((weak))
-  #endif /* __weak */
-  #ifndef __packed
-    #define __packed __attribute__((__packed__))
-  #endif /* __packed */
-#endif /* __GNUC__ */
-
-
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
-  #ifndef __ALIGN_BEGIN
-    #define __ALIGN_BEGIN
-  #endif
-  #ifndef __ALIGN_END
-    #define __ALIGN_END      __attribute__ ((aligned (4)))
-  #endif
-#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
-  #ifndef __ALIGN_END
-    #define __ALIGN_END    __attribute__ ((aligned (4)))
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN
-    #define __ALIGN_BEGIN
-  #endif /* __ALIGN_BEGIN */
-#else
-  #ifndef __ALIGN_END
-    #define __ALIGN_END
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN
-    #if defined   (__CC_ARM)      /* ARM Compiler V5 */
-      #define __ALIGN_BEGIN    __align(4)
-    #elif defined (__ICCARM__)    /* IAR Compiler */
-      #define __ALIGN_BEGIN
-    #endif /* __CC_ARM */
-  #endif /* __ALIGN_BEGIN */
-#endif /* __GNUC__ */
-
-/**
-  * @brief  __RAM_FUNC definition
-  */
-#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-/* ARM Compiler V4/V5 and V6
-   --------------------------
-   RAM functions are defined using the toolchain options.
-   Functions that are executed in RAM should reside in a separate source module.
-   Using the 'Options for File' dialog you can simply change the 'Code / Const'
-   area of a module to a memory space in physical RAM.
-   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
-   dialog.
-*/
-#define __RAM_FUNC
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-   RAM functions are defined using a specific toolchain keyword "__ramfunc".
-*/
-#define __RAM_FUNC __ramfunc
-
-#elif defined   (  __GNUC__  )
-/* GNU Compiler
-   ------------
-  RAM functions are defined using a specific toolchain attribute
-   "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC __attribute__((section(".RamFunc")))
-
-#endif
-
-/** 
-  * @brief  __NOINLINE definition
-  */ 
-#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined   (  __GNUC__  )
-/* ARM V4/V5 and V6 & GNU Compiler
-   ------------------------------- 
-*/
-#define __NOINLINE __attribute__ ( (noinline) )  
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-*/
-#define __NOINLINE _Pragma("optimize = no_inline")
-
-#endif
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32WLxx_HAL_DEF */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h

@@ -1,686 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_dma.h
-  * @author  MCD Application Team
-  * @brief   Header file of DMA HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_DMA_H
-#define STM32WLxx_HAL_DMA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-#include "stm32wlxx_ll_dma.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMA_Exported_Types DMA Exported Types
-  * @{
-  */
-
-/**
-  * @brief  DMA Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Request;               /*!< Specifies the request selected for the specified channel.
-                                       This parameter can be a value of @ref DMA_request */
-
-  uint32_t Direction;             /*!< Specifies if the data will be transferred from memory to peripheral,
-                                       from memory to memory or from peripheral to memory.
-                                       This parameter can be a value of @ref DMA_Data_transfer_direction */
-
-  uint32_t PeriphInc;             /*!< Specifies whether the Peripheral address register should be incremented or not.
-                                       This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-
-  uint32_t MemInc;                /*!< Specifies whether the memory address register should be incremented or not.
-                                       This parameter can be a value of @ref DMA_Memory_incremented_mode */
-
-  uint32_t PeriphDataAlignment;   /*!< Specifies the Peripheral data width.
-                                       This parameter can be a value of @ref DMA_Peripheral_data_size */
-
-  uint32_t MemDataAlignment;      /*!< Specifies the Memory data width.
-                                       This parameter can be a value of @ref DMA_Memory_data_size */
-
-  uint32_t Mode;                  /*!< Specifies the operation mode of the DMAy Channelx.
-                                       This parameter can be a value of @ref DMA_mode
-                                       @note The circular buffer mode cannot be used if the memory-to-memory
-                                             data transfer is configured on the selected Channel */
-
-  uint32_t Priority;              /*!< Specifies the software priority for the DMAy Channelx.
-                                       This parameter can be a value of @ref DMA_Priority_level */
-} DMA_InitTypeDef;
-
-/**
-  * @brief  HAL DMA State structures definition
-  */
-typedef enum
-{
-  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled    */
-  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use      */
-  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing                 */
-  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                      */
-} HAL_DMA_StateTypeDef;
-
-/**
-  * @brief  HAL DMA Error Code structure definition
-  */
-typedef enum
-{
-  HAL_DMA_FULL_TRANSFER           = 0x00U,  /*!< Full transfer     */
-  HAL_DMA_HALF_TRANSFER           = 0x01U   /*!< Half Transfer     */
-} HAL_DMA_LevelCompleteTypeDef;
-
-/**
-  * @brief  HAL DMA Callback ID structure definition
-  */
-typedef enum
-{
-  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,  /*!< Full transfer    */
-  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,  /*!< Half transfer    */
-  HAL_DMA_XFER_ERROR_CB_ID         = 0x02U,  /*!< Error            */
-  HAL_DMA_XFER_ABORT_CB_ID         = 0x03U,  /*!< Abort            */
-  HAL_DMA_XFER_ALL_CB_ID           = 0x04U   /*!< All              */
-
-} HAL_DMA_CallbackIDTypeDef;
-
-/**
-  * @brief  DMA handle Structure definition
-  */
-typedef struct __DMA_HandleTypeDef
-{
-  DMA_Channel_TypeDef             *Instance;                          /*!< Register base address                 */
-
-  DMA_InitTypeDef                 Init;                               /*!< DMA communication parameters          */
-
-  HAL_LockTypeDef                 Lock;                               /*!< DMA locking object                    */
-
-  __IO HAL_DMA_StateTypeDef       State;                              /*!< DMA transfer state                    */
-
-  void   *Parent;                                                     /*!< Parent object state                   */
-
-  void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma);        /*!< DMA transfer complete callback        */
-
-  void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma);    /*!< DMA Half transfer complete callback   */
-
-  void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma);       /*!< DMA transfer error callback           */
-
-  void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma);       /*!< DMA transfer abort callback           */
-
-  __IO uint32_t                   ErrorCode;                          /*!< DMA Error code                        */
-
-  DMA_TypeDef            *DmaBaseAddress;                             /*!< DMA Channel Base Address              */
-
-  uint32_t                        ChannelIndex;                       /*!< DMA Channel Index                     */
-
-  DMAMUX_Channel_TypeDef           *DMAmuxChannel;                    /*!< Register base address                 */
-
-  DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;              /*!< DMAMUX Channels Status Base Address   */
-
-  uint32_t                         DMAmuxChannelStatusMask;           /*!< DMAMUX Channel Status Mask            */
-
-  DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                 /*!< DMAMUX request generator Base Address */
-
-  DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;           /*!< DMAMUX request generator Address      */
-
-  uint32_t                         DMAmuxRequestGenStatusMask;        /*!< DMAMUX request generator Status mask  */
-} DMA_HandleTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
-  * @{
-  */
-
-/** @defgroup DMA_Error_Code DMA Error Code
-  * @{
-  */
-#define HAL_DMA_ERROR_NONE           0x00000000U       /*!< No error                                */
-#define HAL_DMA_ERROR_TE             0x00000001U       /*!< Transfer error                          */
-#define HAL_DMA_ERROR_NO_XFER        0x00000004U       /*!< Abort requested with no Xfer ongoing    */
-#define HAL_DMA_ERROR_TIMEOUT        0x00000020U       /*!< Timeout error                           */
-#define HAL_DMA_ERROR_PARAM          0x00000040U       /*!< Parameter error                         */
-#define HAL_DMA_ERROR_BUSY           0x00000080U       /*!< DMA Busy error                          */
-#define HAL_DMA_ERROR_NOT_SUPPORTED  0x00000100U       /*!< Not supported mode                      */
-#define HAL_DMA_ERROR_SYNC           0x00000200U       /*!< DMAMUX sync overrun error               */
-#define HAL_DMA_ERROR_REQGEN         0x00000400U       /*!< DMAMUX request generator overrun error  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_request DMA request
-  * @{
-  */
-#define DMA_REQUEST_MEM2MEM          LL_DMAMUX_REQ_MEM2MEM        /*!< memory to memory transfer  */
-#define DMA_REQUEST_GENERATOR0       LL_DMAMUX_REQ_GENERATOR0     /*!< DMAMUX request generator 0 */
-#define DMA_REQUEST_GENERATOR1       LL_DMAMUX_REQ_GENERATOR1     /*!< DMAMUX request generator 1 */
-#define DMA_REQUEST_GENERATOR2       LL_DMAMUX_REQ_GENERATOR2     /*!< DMAMUX request generator 2 */
-#define DMA_REQUEST_GENERATOR3       LL_DMAMUX_REQ_GENERATOR3     /*!< DMAMUX request generator 3 */
-#define DMA_REQUEST_ADC              LL_DMAMUX_REQ_ADC            /*!< DMAMUX ADC request         */
-#define DMA_REQUEST_DAC_OUT1         LL_DMAMUX_REQ_DAC_OUT1       /*!< DMAMUX DAC OUT request     */
-#define DMA_REQUEST_SPI1_RX          LL_DMAMUX_REQ_SPI1_RX        /*!< DMAMUX SPI1 RX request     */
-#define DMA_REQUEST_SPI1_TX          LL_DMAMUX_REQ_SPI1_TX        /*!< DMAMUX SPI1 TX request     */
-#define DMA_REQUEST_SPI2_RX          LL_DMAMUX_REQ_SPI2_RX        /*!< DMAMUX SPI2 RX request     */
-#define DMA_REQUEST_SPI2_TX          LL_DMAMUX_REQ_SPI2_TX        /*!< DMAMUX SPI2 TX request     */
-#define DMA_REQUEST_I2C1_RX          LL_DMAMUX_REQ_I2C1_RX        /*!< DMAMUX I2C1 RX request     */
-#define DMA_REQUEST_I2C1_TX          LL_DMAMUX_REQ_I2C1_TX        /*!< DMAMUX I2C1 TX request     */
-#define DMA_REQUEST_I2C2_RX          LL_DMAMUX_REQ_I2C2_RX        /*!< DMAMUX I2C2 RX request     */
-#define DMA_REQUEST_I2C2_TX          LL_DMAMUX_REQ_I2C2_TX        /*!< DMAMUX I2C2 TX request     */
-#define DMA_REQUEST_I2C3_RX          LL_DMAMUX_REQ_I2C3_RX        /*!< DMAMUX I2C3 RX request     */
-#define DMA_REQUEST_I2C3_TX          LL_DMAMUX_REQ_I2C3_TX        /*!< DMAMUX I2C3 TX request     */
-#define DMA_REQUEST_USART1_RX        LL_DMAMUX_REQ_USART1_RX      /*!< DMAMUX USART1 RX request   */
-#define DMA_REQUEST_USART1_TX        LL_DMAMUX_REQ_USART1_TX      /*!< DMAMUX USART1 TX request   */
-#define DMA_REQUEST_USART2_RX        LL_DMAMUX_REQ_USART2_RX      /*!< DMAMUX USART2 RX request   */
-#define DMA_REQUEST_USART2_TX        LL_DMAMUX_REQ_USART2_TX      /*!< DMAMUX USART2 TX request   */
-#define DMA_REQUEST_LPUART1_RX       LL_DMAMUX_REQ_LPUART1_RX     /*!< DMAMUX LPUART1 RX request  */
-#define DMA_REQUEST_LPUART1_TX       LL_DMAMUX_REQ_LPUART1_TX     /*!< DMAMUX LPUART1 TX request  */
-#define DMA_REQUEST_TIM1_CH1         LL_DMAMUX_REQ_TIM1_CH1       /*!< DMAMUX TIM1 CH1 request    */
-#define DMA_REQUEST_TIM1_CH2         LL_DMAMUX_REQ_TIM1_CH2       /*!< DMAMUX TIM1 CH2 request    */
-#define DMA_REQUEST_TIM1_CH3         LL_DMAMUX_REQ_TIM1_CH3       /*!< DMAMUX TIM1 CH3 request    */
-#define DMA_REQUEST_TIM1_CH4         LL_DMAMUX_REQ_TIM1_CH4       /*!< DMAMUX TIM1 CH4 request    */
-#define DMA_REQUEST_TIM1_UP          LL_DMAMUX_REQ_TIM1_UP        /*!< DMAMUX TIM1 UP request     */
-#define DMA_REQUEST_TIM1_TRIG        LL_DMAMUX_REQ_TIM1_TRIG      /*!< DMAMUX TIM1 TRIG request   */
-#define DMA_REQUEST_TIM1_COM         LL_DMAMUX_REQ_TIM1_COM       /*!< DMAMUX TIM1 COM request    */
-#define DMA_REQUEST_TIM2_CH1         LL_DMAMUX_REQ_TIM2_CH1       /*!< DMAMUX TIM2 CH1 request    */
-#define DMA_REQUEST_TIM2_CH2         LL_DMAMUX_REQ_TIM2_CH2       /*!< DMAMUX TIM2 CH2 request    */
-#define DMA_REQUEST_TIM2_CH3         LL_DMAMUX_REQ_TIM2_CH3       /*!< DMAMUX TIM2 CH3 request    */
-#define DMA_REQUEST_TIM2_CH4         LL_DMAMUX_REQ_TIM2_CH4       /*!< DMAMUX TIM2 CH4 request    */
-#define DMA_REQUEST_TIM2_UP          LL_DMAMUX_REQ_TIM2_UP        /*!< DMAMUX TIM2 UP request     */
-#define DMA_REQUEST_TIM16_CH1        LL_DMAMUX_REQ_TIM16_CH1      /*!< DMAMUX TIM16 CH1 request   */
-#define DMA_REQUEST_TIM16_UP         LL_DMAMUX_REQ_TIM16_UP       /*!< DMAMUX TIM16 UP request    */
-#define DMA_REQUEST_TIM17_CH1        LL_DMAMUX_REQ_TIM17_CH1      /*!< DMAMUX TIM17 CH1 request   */
-#define DMA_REQUEST_TIM17_UP         LL_DMAMUX_REQ_TIM17_UP       /*!< DMAMUX TIM17 UP request    */
-#define DMA_REQUEST_AES_IN           LL_DMAMUX_REQ_AES_IN         /*!< DMAMUX AES_IN request      */
-#define DMA_REQUEST_AES_OUT          LL_DMAMUX_REQ_AES_OUT        /*!< DMAMUX AES_OUT request     */
-#define DMA_REQUEST_SUBGHZSPI_RX     LL_DMAMUX_REQ_SUBGHZSPI_RX   /*!< DMAMUX SUBGHZSPI RX request*/
-#define DMA_REQUEST_SUBGHZSPI_TX     LL_DMAMUX_REQ_SUBGHZSPI_TX   /*!< DMAMUX SUBGHZSPI TX request*/
-
-#define DMA_MAX_REQUEST              LL_DMAMUX_MAX_REQ
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
-  * @{
-  */
-#define DMA_PERIPH_TO_MEMORY         LL_DMA_DIRECTION_PERIPH_TO_MEMORY  /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH         LL_DMA_DIRECTION_MEMORY_TO_PERIPH  /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY         LL_DMA_DIRECTION_MEMORY_TO_MEMORY  /*!< Memory to memory direction     */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
-  * @{
-  */
-#define DMA_PINC_ENABLE              LL_DMA_PERIPH_INCREMENT            /*!< Peripheral increment mode Enable  */
-#define DMA_PINC_DISABLE             LL_DMA_PERIPH_NOINCREMENT          /*!< Peripheral increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
-  * @{
-  */
-#define DMA_MINC_ENABLE              LL_DMA_MEMORY_INCREMENT            /*!< Memory increment mode Enable  */
-#define DMA_MINC_DISABLE             LL_DMA_MEMORY_NOINCREMENT          /*!< Memory increment mode Disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
-  * @{
-  */
-#define DMA_PDATAALIGN_BYTE          LL_DMA_PDATAALIGN_BYTE             /*!< Peripheral data alignment : Byte     */
-#define DMA_PDATAALIGN_HALFWORD      LL_DMA_PDATAALIGN_HALFWORD         /*!< Peripheral data alignment : HalfWord */
-#define DMA_PDATAALIGN_WORD          LL_DMA_PDATAALIGN_WORD             /*!< Peripheral data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
-  * @{
-  */
-#define DMA_MDATAALIGN_BYTE          LL_DMA_MDATAALIGN_BYTE             /*!< Memory data alignment : Byte     */
-#define DMA_MDATAALIGN_HALFWORD      LL_DMA_MDATAALIGN_HALFWORD         /*!< Memory data alignment : HalfWord */
-#define DMA_MDATAALIGN_WORD          LL_DMA_MDATAALIGN_WORD             /*!< Memory data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_mode DMA mode
-  * @{
-  */
-#define DMA_NORMAL                   LL_DMA_MODE_NORMAL                 /*!< Normal mode    */
-#define DMA_CIRCULAR                 LL_DMA_MODE_CIRCULAR               /*!< Circular mode  */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Priority_level DMA Priority level
-  * @{
-  */
-#define DMA_PRIORITY_LOW             LL_DMA_PRIORITY_LOW                /*!< Priority level : Low       */
-#define DMA_PRIORITY_MEDIUM          LL_DMA_PRIORITY_MEDIUM             /*!< Priority level : Medium    */
-#define DMA_PRIORITY_HIGH            LL_DMA_PRIORITY_HIGH               /*!< Priority level : High      */
-#define DMA_PRIORITY_VERY_HIGH       LL_DMA_PRIORITY_VERYHIGH           /*!< Priority level : Very_High */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
-  * @{
-  */
-#define DMA_IT_TC                    DMA_CCR_TCIE                       /*!< Transfer Complete interrupt      */
-#define DMA_IT_HT                    DMA_CCR_HTIE                       /*!< Half Transfer Complete interrupt */
-#define DMA_IT_TE                    DMA_CCR_TEIE                       /*!< Transfer Error interrupt         */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
-  * @{
-  */
-
-#define DMA_FLAG_GI1                 DMA_ISR_GIF1                       /*!< Global Interrupt flag for Channel 1  */
-#define DMA_FLAG_TC1                 DMA_ISR_TCIF1                      /*!< Transfer Complete flag for Channel 1 */
-#define DMA_FLAG_HT1                 DMA_ISR_HTIF1                      /*!< Half Transfer flag for Channel 1     */
-#define DMA_FLAG_TE1                 DMA_ISR_TEIF1                      /*!< Transfer Error flag for Channel 1    */
-#define DMA_FLAG_GI2                 DMA_ISR_GIF2                       /*!< Global Interrupt flag for Channel 2  */
-#define DMA_FLAG_TC2                 DMA_ISR_TCIF2                      /*!< Transfer Complete flag for Channel 2 */
-#define DMA_FLAG_HT2                 DMA_ISR_HTIF2                      /*!< Half Transfer flag for Channel 2     */
-#define DMA_FLAG_TE2                 DMA_ISR_TEIF2                      /*!< Transfer Error flag for Channel 2    */
-#define DMA_FLAG_GI3                 DMA_ISR_GIF3                       /*!< Global Interrupt flag for Channel 3  */
-#define DMA_FLAG_TC3                 DMA_ISR_TCIF3                      /*!< Transfer Complete flag for Channel 3 */
-#define DMA_FLAG_HT3                 DMA_ISR_HTIF3                      /*!< Half Transfer flag for Channel 3     */
-#define DMA_FLAG_TE3                 DMA_ISR_TEIF3                      /*!< Transfer Error flag for Channel 3    */
-#define DMA_FLAG_GI4                 DMA_ISR_GIF4                       /*!< Global Interrupt flag for Channel 4  */
-#define DMA_FLAG_TC4                 DMA_ISR_TCIF4                      /*!< Transfer Complete flag for Channel 4 */
-#define DMA_FLAG_HT4                 DMA_ISR_HTIF4                      /*!< Half Transfer flag for Channel 4     */
-#define DMA_FLAG_TE4                 DMA_ISR_TEIF4                      /*!< Transfer Error flag for Channel 4    */
-#define DMA_FLAG_GI5                 DMA_ISR_GIF5                       /*!< Global Interrupt flag for Channel 5  */
-#define DMA_FLAG_TC5                 DMA_ISR_TCIF5                      /*!< Transfer Complete flag for Channel 5 */
-#define DMA_FLAG_HT5                 DMA_ISR_HTIF5                      /*!< Half Transfer flag for Channel 5     */
-#define DMA_FLAG_TE5                 DMA_ISR_TEIF5                      /*!< Transfer Error for Channel 5         */
-#define DMA_FLAG_GI6                 DMA_ISR_GIF6                       /*!< Global Interrupt flag for Channel 6  */
-#define DMA_FLAG_TC6                 DMA_ISR_TCIF6                      /*!< Transfer Complete flag for Channel 6 */
-#define DMA_FLAG_HT6                 DMA_ISR_HTIF6                      /*!< Half Transfer flag for Channel 6     */
-#define DMA_FLAG_TE6                 DMA_ISR_TEIF6                      /*!< Transfer Error flag for Channel 6    */
-#define DMA_FLAG_GI7                 DMA_ISR_GIF7                       /*!< Global Interrupt flag for Channel 7  */
-#define DMA_FLAG_TC7                 DMA_ISR_TCIF7                      /*!< Transfer Complete flag for Channel 7 */
-#define DMA_FLAG_HT7                 DMA_ISR_HTIF7                      /*!< Half Transfer flag for Channel 7     */
-#define DMA_FLAG_TE7                 DMA_ISR_TEIF7                      /*!< Transfer Error flag for Channel 7    */
-/**
-  * @}
-  */
-
-#if defined(DMA_CCR_SECM) && defined(DMA_CCR_PRIV)
-/** @defgroup DMA_Channel_Attributes DMA Channel Attributes
-  * @brief DMA channel secure or non-secure and privileged or non-privileged attributes
-  * @note Secure and non-secure attributes are only available from secure when the system
-  *       implements the security (ESE=1)
-  * @{
-  */
-
-#define DMA_CHANNEL_ATTR_PRIV_MASK         (DMA_CCR_PRIV >> 16U)
-#define DMA_CHANNEL_ATTR_SEC_MASK          (DMA_CCR_SECM >> 16U)
-#if defined (CORE_CM0PLUS)
-#define DMA_CHANNEL_ATTR_SEC_SRC_MASK      (DMA_CCR_SSEC >> 16U)
-#define DMA_CHANNEL_ATTR_SEC_DEST_MASK     (DMA_CCR_DSEC >> 16U)
-#endif /* CORE_CM0PLUS */
-
-#define DMA_CHANNEL_PRIV          (DMA_CHANNEL_ATTR_PRIV_MASK | DMA_CCR_PRIV)     /*!< Channel is privileged             */
-#define DMA_CHANNEL_NPRIV         (DMA_CHANNEL_ATTR_PRIV_MASK)                    /*!< Channel is unprivileged           */
-#define DMA_CHANNEL_SEC           (DMA_CHANNEL_ATTR_SEC_MASK | DMA_CCR_SECM)      /*!< Channel is secure                 */
-#define DMA_CHANNEL_NSEC          (DMA_CHANNEL_ATTR_SEC_MASK)                     /*!< Channel is non-secure             */
-#if defined (CORE_CM0PLUS)
-#define DMA_CHANNEL_SRC_SEC       (DMA_CHANNEL_ATTR_SEC_SRC_MASK | DMA_CCR_SSEC)  /*!< Channel source is secure          */
-#define DMA_CHANNEL_SRC_NSEC      (DMA_CHANNEL_ATTR_SEC_SRC_MASK)                 /*!< Channel source is non-secure      */
-#define DMA_CHANNEL_DEST_SEC      (DMA_CHANNEL_ATTR_SEC_DEST_MASK | DMA_CCR_DSEC) /*!< Channel destination is secure     */
-#define DMA_CHANNEL_DEST_NSEC     (DMA_CHANNEL_ATTR_SEC_DEST_MASK)                /*!< Channel destination is non-secure */
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-#endif /* DMA_SECURE_SWITCH */
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup DMA_Exported_Macros DMA Exported Macros
-  * @{
-  */
-
-/** @brief  Reset DMA handle state
-  * @param __HANDLE__ DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
-  * @brief  Enable the specified DMA Channel.
-  * @param __HANDLE__ DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
-
-/**
-  * @brief  Disable the specified DMA Channel.
-  * @param __HANDLE__ DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
-
-/**
-  * @brief  Return the current DMA Channel transfer complete flag.
-  * @param __HANDLE__ DMA handle
-  * @retval The specified transfer complete flag index.
-  */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
-   DMA_FLAG_TC7)
-
-/**
-  * @brief  Return the current DMA Channel half transfer complete flag.
-  * @param __HANDLE__ DMA handle
-  * @retval The specified half transfer complete flag index.
-  */
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
-   DMA_FLAG_HT7)
-
-/**
-  * @brief  Return the current DMA Channel transfer error flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
-   DMA_FLAG_TE7)
-
-/**
-  * @brief  Return the current DMA Channel Global interrupt flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_GI1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_GI1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_GI2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_GI2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_GI3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_GI3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_GI4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_GI4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_GI5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_GI5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_GI6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_GI6 :\
-   DMA_FLAG_GI7)
-
-/**
-  * @brief  Get the DMA Channel pending flags.
-  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__ Get the specified flag.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *            @arg DMA_FLAG_GIx:  Global interrupt flag
-  *         Where x can be 1 to max Channel supported by the product to select the DMA Channel flag.
-  * @retval The state of FLAG (SET or RESET).
-  */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
- (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
-
-/**
-  * @brief  Clear the DMA Channel pending flags.
-  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *            @arg DMA_FLAG_GIx:  Global interrupt flag
-  *         Where x can be 1 to max Channel supported by the product to select the DMA Channel flag.
-  * @retval None
-  */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
- (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
-
-/**
-  * @brief  Enable the specified DMA Channel interrupts.
-  * @param  __HANDLE__ DMA handle
-  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified DMA Channel interrupts.
-  * @param  __HANDLE__ DMA handle
-  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified DMA Channel interrupt is enabled or disabled.
-  * @param  __HANDLE__ DMA handle
-  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval The state of DMA_IT (SET or RESET).
-  */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
-
-/**
-  * @brief  Returns the number of remaining data units in the current DMA Channel transfer.
-  * @param  __HANDLE__ DMA handle
-  * @retval The number of remaining data units in the current DMA Channel transfer.
-  */
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
-
-/**
-  * @}
-  */
-
-/* Include DMA HAL Extension module */
-#include "stm32wlxx_hal_dma_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DMA_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-#if defined(DMA_CCR_SECM) && defined(DMA_CCR_PRIV)
-/** @addtogroup DMA_Exported_Functions_Group4
-  * @{
-  */
-/* DMA Attributes functions ********************************************/
-HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t ChannelAttributes);
-HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t *ChannelAttributes);
-/**
-  * @}
-  */
-
-#endif /* DMA_SECURE_SWITCH */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Macros DMA Private Macros
-  * @{
-  */
-
-#define IS_DMA_DIRECTION(DIRECTION)             (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
-                                                 ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
-                                                 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
-
-#define IS_DMA_BUFFER_SIZE(SIZE)                (((SIZE) >= 0x1U) && ((SIZE) < DMA_CNDTR_NDT))
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE)      (((STATE) == DMA_PINC_ENABLE) || \
-                                                 ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE)          (((STATE) == DMA_MINC_ENABLE)  || \
-                                                 ((STATE) == DMA_MINC_DISABLE))
-
-#define IS_DMA_ALL_REQUEST(REQUEST)             ((REQUEST) <= DMA_MAX_REQUEST)
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE)       (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
-                                                 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
-                                                 ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE)           (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
-                                                 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
-                                                 ((SIZE) == DMA_MDATAALIGN_WORD ))
-
-#define IS_DMA_MODE(MODE)                       (((MODE) == DMA_NORMAL )  || \
-                                                 ((MODE) == DMA_CIRCULAR))
-
-#define IS_DMA_PRIORITY(PRIORITY)               (((PRIORITY) == DMA_PRIORITY_LOW )   || \
-                                                 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
-                                                 ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
-                                                 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
-
-#if defined(DMA_CCR_SECM) && defined(DMA_CCR_PRIV)
-#if defined (CORE_CM0PLUS)
-#define IS_DMA_ATTRIBUTES(ATTRIBUTE)            ((((ATTRIBUTE) & (~(0x001E001EU))) == 0U) && (((ATTRIBUTE) & 0x0000001EU) != 0U))
-#else
-#define IS_DMA_ATTRIBUTES(ATTRIBUTE)            ((((ATTRIBUTE) & (~(0x00100010U))) == 0U) && (((ATTRIBUTE) & 0x00000010U) != 0U))
-#endif /* CORE_CM0PLUS */
-#endif /* DMA_SECURE_SWITCH */
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h

@@ -1,268 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_dma_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of DMA HAL extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_DMA_EX_H
-#define STM32WLxx_HAL_DMA_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-#include "stm32wlxx_ll_dmamux.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DMAEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
-  * @{
-  */
-
-/**
-  * @brief  HAL DMAMUX Synchronization configuration structure definition
-  */
-typedef struct
-{
-  uint32_t SyncSignalID;        /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
-                                  This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
-
-  uint32_t SyncPolarity;        /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
-                                  This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
-
-  FunctionalState SyncEnable;   /*!< Specifies if the synchronization shall be enabled or disabled
-                                  This parameter can take the value ENABLE or DISABLE */
-
-  FunctionalState EventEnable;  /*!< Specifies if an event shall be generated once the RequestNumber is reached.
-                                  This parameter can take the value ENABLE or DISABLE */
-
-  uint32_t RequestNumber;       /*!< Specifies the number of DMA request that will be authorized after a sync event
-                                  This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
-
-
-} HAL_DMA_MuxSyncConfigTypeDef;
-
-
-/**
-  * @brief  HAL DMAMUX request generator parameters structure definition
-  */
-typedef struct
-{
-  uint32_t SignalID;            /*!< Specifies the ID of the signal used for DMAMUX request generator
-                                  This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
-
-  uint32_t Polarity;            /*!< Specifies the polarity of the signal on which the request is generated.
-                                  This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
-
-  uint32_t RequestNumber;       /*!< Specifies the number of DMA request that will be generated after a signal event
-                                  This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
-
-} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
-  * @{
-  */
-
-/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
-  * @{
-  */
-#define HAL_DMAMUX1_SYNC_EXTI0            LL_DMAMUX_SYNC_EXTI_LINE0      /*!< Synchronization signal from EXTI Line0  */
-#define HAL_DMAMUX1_SYNC_EXTI1            LL_DMAMUX_SYNC_EXTI_LINE1      /*!< Synchronization signal from EXTI Line1  */
-#define HAL_DMAMUX1_SYNC_EXTI2            LL_DMAMUX_SYNC_EXTI_LINE2      /*!< Synchronization signal from EXTI Line2  */
-#define HAL_DMAMUX1_SYNC_EXTI3            LL_DMAMUX_SYNC_EXTI_LINE3      /*!< Synchronization signal from EXTI Line3  */
-#define HAL_DMAMUX1_SYNC_EXTI4            LL_DMAMUX_SYNC_EXTI_LINE4      /*!< Synchronization signal from EXTI Line4  */
-#define HAL_DMAMUX1_SYNC_EXTI5            LL_DMAMUX_SYNC_EXTI_LINE5      /*!< Synchronization signal from EXTI Line5  */
-#define HAL_DMAMUX1_SYNC_EXTI6            LL_DMAMUX_SYNC_EXTI_LINE6      /*!< Synchronization signal from EXTI Line6  */
-#define HAL_DMAMUX1_SYNC_EXTI7            LL_DMAMUX_SYNC_EXTI_LINE7      /*!< Synchronization signal from EXTI Line7  */
-#define HAL_DMAMUX1_SYNC_EXTI8            LL_DMAMUX_SYNC_EXTI_LINE8      /*!< Synchronization signal from EXTI Line8  */
-#define HAL_DMAMUX1_SYNC_EXTI9            LL_DMAMUX_SYNC_EXTI_LINE9      /*!< Synchronization signal from EXTI Line9  */
-#define HAL_DMAMUX1_SYNC_EXTI10           LL_DMAMUX_SYNC_EXTI_LINE10     /*!< Synchronization signal from EXTI Line10 */
-#define HAL_DMAMUX1_SYNC_EXTI11           LL_DMAMUX_SYNC_EXTI_LINE11     /*!< Synchronization signal from EXTI Line11 */
-#define HAL_DMAMUX1_SYNC_EXTI12           LL_DMAMUX_SYNC_EXTI_LINE12     /*!< Synchronization signal from EXTI Line12 */
-#define HAL_DMAMUX1_SYNC_EXTI13           LL_DMAMUX_SYNC_EXTI_LINE13     /*!< Synchronization signal from EXTI Line13 */
-#define HAL_DMAMUX1_SYNC_EXTI14           LL_DMAMUX_SYNC_EXTI_LINE14     /*!< Synchronization signal from EXTI Line14 */
-#define HAL_DMAMUX1_SYNC_EXTI15           LL_DMAMUX_SYNC_EXTI_LINE15     /*!< Synchronization signal from EXTI Line15 */
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT  LL_DMAMUX_SYNC_DMAMUX_CH0      /*!< Synchronization signal from DMAMUX channel0 Event */
-#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT  LL_DMAMUX_SYNC_DMAMUX_CH1      /*!< Synchronization signal from DMAMUX channel1 Event */
-#define HAL_DMAMUX1_SYNC_LPTIM1_OUT       LL_DMAMUX_SYNC_LPTIM1_OUT      /*!< Synchronization signal from LPTIM1 Output */
-#define HAL_DMAMUX1_SYNC_LPTIM2_OUT       LL_DMAMUX_SYNC_LPTIM2_OUT      /*!< Synchronization signal from LPTIM2 Output */
-#define HAL_DMAMUX1_SYNC_LPTIM3_OUT       LL_DMAMUX_SYNC_LPTIM3_OUT      /*!< Synchronization signal from LPTIM3 Output */
-
-#define HAL_DMAMUX1_MAX_SYNC              HAL_DMAMUX1_SYNC_LPTIM3_OUT
-/**
-  * @}
-  */
-
-/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
-  * @{
-  */
-#define HAL_DMAMUX_SYNC_NO_EVENT          LL_DMAMUX_SYNC_NO_EVENT               /*!< block synchronization events                       */
-#define HAL_DMAMUX_SYNC_RISING            LL_DMAMUX_SYNC_POL_RISING             /*!< synchronize with rising edge events                */
-#define HAL_DMAMUX_SYNC_FALLING           LL_DMAMUX_SYNC_POL_FALLING            /*!< synchronize with falling edge events               */
-#define HAL_DMAMUX_SYNC_RISING_FALLING    LL_DMAMUX_SYNC_POL_RISING_FALLING     /*!< synchronize with rising and falling edge events    */
-
-/**
-  * @}
-  */
-
-/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
-  * @{
-  */
-#define HAL_DMAMUX1_REQ_GEN_EXTI0            LL_DMAMUX_REQ_GEN_EXTI_LINE0   /*!< Request signal generation from EXTI Line0  */
-#define HAL_DMAMUX1_REQ_GEN_EXTI1            LL_DMAMUX_REQ_GEN_EXTI_LINE1   /*!< Request signal generation from EXTI Line1  */
-#define HAL_DMAMUX1_REQ_GEN_EXTI2            LL_DMAMUX_REQ_GEN_EXTI_LINE2   /*!< Request signal generation from EXTI Line2  */
-#define HAL_DMAMUX1_REQ_GEN_EXTI3            LL_DMAMUX_REQ_GEN_EXTI_LINE3   /*!< Request signal generation from EXTI Line3  */
-#define HAL_DMAMUX1_REQ_GEN_EXTI4            LL_DMAMUX_REQ_GEN_EXTI_LINE4   /*!< Request signal generation from EXTI Line4  */
-#define HAL_DMAMUX1_REQ_GEN_EXTI5            LL_DMAMUX_REQ_GEN_EXTI_LINE5   /*!< Request signal generation from EXTI Line5  */
-#define HAL_DMAMUX1_REQ_GEN_EXTI6            LL_DMAMUX_REQ_GEN_EXTI_LINE6   /*!< Request signal generation from EXTI Line6  */
-#define HAL_DMAMUX1_REQ_GEN_EXTI7            LL_DMAMUX_REQ_GEN_EXTI_LINE7   /*!< Request signal generation from EXTI Line7  */
-#define HAL_DMAMUX1_REQ_GEN_EXTI8            LL_DMAMUX_REQ_GEN_EXTI_LINE8   /*!< Request signal generation from EXTI Line8  */
-#define HAL_DMAMUX1_REQ_GEN_EXTI9            LL_DMAMUX_REQ_GEN_EXTI_LINE9   /*!< Request signal generation from EXTI Line9  */
-#define HAL_DMAMUX1_REQ_GEN_EXTI10           LL_DMAMUX_REQ_GEN_EXTI_LINE10  /*!< Request signal generation from EXTI Line10 */
-#define HAL_DMAMUX1_REQ_GEN_EXTI11           LL_DMAMUX_REQ_GEN_EXTI_LINE11  /*!< Request signal generation from EXTI Line11 */
-#define HAL_DMAMUX1_REQ_GEN_EXTI12           LL_DMAMUX_REQ_GEN_EXTI_LINE12  /*!< Request signal generation from EXTI Line12 */
-#define HAL_DMAMUX1_REQ_GEN_EXTI13           LL_DMAMUX_REQ_GEN_EXTI_LINE13  /*!< Request signal generation from EXTI Line13 */
-#define HAL_DMAMUX1_REQ_GEN_EXTI14           LL_DMAMUX_REQ_GEN_EXTI_LINE14  /*!< Request signal generation from EXTI Line14 */
-#define HAL_DMAMUX1_REQ_GEN_EXTI15           LL_DMAMUX_REQ_GEN_EXTI_LINE15  /*!< Request signal generation from EXTI Line15 */
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT  LL_DMAMUX_REQ_GEN_DMAMUX_CH0   /*!< Request signal generation from DMAMUX channel0 Event */
-#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT  LL_DMAMUX_REQ_GEN_DMAMUX_CH1   /*!< Request signal generation from DMAMUX channel1 Event */
-#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT       LL_DMAMUX_REQ_GEN_LPTIM1_OUT   /*!< Request signal generation from LPTIM1 Output */
-#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT       LL_DMAMUX_REQ_GEN_LPTIM2_OUT   /*!< Request signal generation from LPTIM2 Output */
-#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT       LL_DMAMUX_REQ_GEN_LPTIM3_OUT   /*!< Request signal generation from LPTIM3 Output */
-
-#define HAL_DMAMUX1_MAX_REQ_GEN              HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
-/**
-  * @}
-  */
-
-/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
-  * @{
-  */
-#define HAL_DMAMUX_REQ_GEN_NO_EVENT       LL_DMAMUX_REQ_GEN_NO_EVENT            /*!< block request generator events                     */
-#define HAL_DMAMUX_REQ_GEN_RISING         LL_DMAMUX_REQ_GEN_POL_RISING          /*!< generate request on rising edge events             */
-#define HAL_DMAMUX_REQ_GEN_FALLING        LL_DMAMUX_REQ_GEN_POL_FALLING         /*!< generate request on falling edge events            */
-#define HAL_DMAMUX_REQ_GEN_RISING_FALLING LL_DMAMUX_REQ_GEN_POL_RISING_FALLING  /*!< generate request on rising and falling edge events */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMAEx_Exported_Functions
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-/** @addtogroup DMAEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* ------------------------- REQUEST -----------------------------------------*/
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
-                                                      HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
-HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
-/* -------------------------------------------------------------------------- */
-
-/* ------------------------- SYNCHRO -----------------------------------------*/
-HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
-/* -------------------------------------------------------------------------- */
-
-void              HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
-  * @brief    DMAEx private macros
- * @{
- */
-
-#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID)             (((SIGNAL_ID) == HAL_DMAMUX1_SYNC_EXTI0) || \
-                                                         (((SIGNAL_ID) >= HAL_DMAMUX1_SYNC_EXTI1) && \
-                                                          ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_SYNC)))
-
-#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER)   (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
-
-#define IS_DMAMUX_SYNC_POLARITY(POLARITY)               (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
-                                                         ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \
-                                                         ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \
-                                                         ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
-
-#define IS_DMAMUX_SYNC_STATE(SYNC)                      (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))
-
-#define IS_DMAMUX_SYNC_EVENT(EVENT)                     (((EVENT) == DISABLE)   || \
-                                                         ((EVENT) == ENABLE))
-
-#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID)      (((SIGNAL_ID) == HAL_DMAMUX1_REQ_GEN_EXTI0) || \
-                                                         (((SIGNAL_ID) >= HAL_DMAMUX1_REQ_GEN_EXTI1) && \
-                                                          ((SIGNAL_ID) <= HAL_DMAMUX1_MAX_REQ_GEN)))
-
-#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
-
-#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY)        (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT)|| \
-                                                         ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)  || \
-                                                         ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
-                                                         ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_DMA_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h

@@ -1,330 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_exti.h
-  * @author  MCD Application Team
-  * @brief   Header file of EXTI HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics. 
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the 
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_EXTI_H
-#define STM32WLxx_HAL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup EXTI EXTI
-  * @brief EXTI HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Types EXTI Exported Types
-  * @{
-  */
-typedef enum
-{
-  HAL_EXTI_COMMON_CB_ID          = 0x00U,
-} EXTI_CallbackIDTypeDef;
-
-
-/**
-  * @brief  EXTI Handle structure definition
-  */
-typedef struct
-{
-  uint32_t Line;                    /*!<  Exti line number */
-  void (* PendingCallback)(void);   /*!<  Exti pending callback */
-} EXTI_HandleTypeDef;
-
-/**
-  * @brief  EXTI Configuration structure definition
-  */
-typedef struct
-{
-  uint32_t Line;      /*!< The Exti line to be configured. This parameter
-                           can be a value of @ref EXTI_Line */
-  uint32_t Mode;      /*!< The Exit Mode to be configured for a core.
-                           This parameter can be a combination of @ref EXTI_Mode */
-  uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter
-                           can be a value of @ref EXTI_Trigger */
-  uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.
-                           This parameter is only possible for line 0 to 15. It
-                           can be a value of @ref EXTI_GPIOSel */
-} EXTI_ConfigTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
-  * @{
-  */
-
-/** @defgroup EXTI_Line  EXTI Line
-  * @{
-  */
-#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x00u)
-#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x01u)
-#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x02u)
-#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x03u)
-#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x04u)
-#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x05u)
-#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x06u)
-#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x07u)
-#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x08u)
-#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x09u)
-#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x0Au)
-#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x0Bu)
-#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x0Cu)
-#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x0Du)
-#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x0Eu)
-#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | 0x0Fu)
-#define EXTI_LINE_16                        (EXTI_CONFIG   |              EXTI_REG1 | 0x10u)
-#define EXTI_LINE_17                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | 0x11u)
-#define EXTI_LINE_18                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | 0x12u)
-#define EXTI_LINE_19                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | 0x13u)
-#define EXTI_LINE_20                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | 0x14u)
-#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | 0x15u)
-#define EXTI_LINE_22                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | 0x16u)
-#define EXTI_LINE_23                        (EXTI_DIRECT   |              EXTI_REG1 | 0x17u)
-#define EXTI_LINE_24                        (EXTI_DIRECT   |              EXTI_REG1 | 0x18u)
-#define EXTI_LINE_25                        (EXTI_DIRECT   |              EXTI_REG1 | 0x19u)
-#define EXTI_LINE_26                        (EXTI_DIRECT   |              EXTI_REG1 | 0x1Au)
-#define EXTI_LINE_27                        (EXTI_DIRECT   |              EXTI_REG1 | 0x1Bu)
-#define EXTI_LINE_28                        (EXTI_DIRECT   |              EXTI_REG1 | 0x1Cu)
-#define EXTI_LINE_29                        (EXTI_DIRECT   |              EXTI_REG1 | 0x1Du)
-#define EXTI_LINE_30                        (EXTI_DIRECT   |              EXTI_REG1 | 0x1Eu)
-#define EXTI_LINE_31                        (EXTI_DIRECT   |              EXTI_REG1 | 0x1Fu)
-#define EXTI_LINE_32                        (EXTI_RESERVED |              EXTI_REG2 | 0x00u)
-#define EXTI_LINE_33                        (EXTI_RESERVED |              EXTI_REG2 | 0x01u)
-#define EXTI_LINE_34                        (EXTI_CONFIG   |              EXTI_REG2 | 0x02u)
-#define EXTI_LINE_35                        (EXTI_RESERVED |              EXTI_REG2 | 0x03u)
-#if defined (DUAL_CORE)
-#define EXTI_LINE_36                        (EXTI_DIRECT   |              EXTI_REG2 | 0x04u)
-#define EXTI_LINE_37                        (EXTI_DIRECT   |              EXTI_REG2 | 0x05u)
-#else
-#define EXTI_LINE_36                        (EXTI_RESERVED |              EXTI_REG2 | 0x04u)
-#define EXTI_LINE_37                        (EXTI_RESERVED |              EXTI_REG2 | 0x05u)
-#endif
-#define EXTI_LINE_38                        (EXTI_DIRECT   |              EXTI_REG2 | 0x06u)
-#if defined (DUAL_CORE)
-#define EXTI_LINE_39                        (EXTI_DIRECT   |              EXTI_REG2 | 0x07u)
-#define EXTI_LINE_40                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | 0x08u)
-#define EXTI_LINE_41                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | 0x09u)
-#else
-#define EXTI_LINE_39                        (EXTI_RESERVED |              EXTI_REG2 | 0x07u)
-#define EXTI_LINE_40                        (EXTI_RESERVED |              EXTI_REG2 | 0x08u)
-#define EXTI_LINE_41                        (EXTI_RESERVED |              EXTI_REG2 | 0x09u)
-#endif
-#define EXTI_LINE_42                        (EXTI_DIRECT   |              EXTI_REG2 | 0x0Au)
-#define EXTI_LINE_43                        (EXTI_DIRECT   |              EXTI_REG2 | 0x0Bu)
-#define EXTI_LINE_44                        (EXTI_DIRECT   |              EXTI_REG2 | 0x0Cu)
-#define EXTI_LINE_45                        (EXTI_CONFIG   |              EXTI_REG2 | 0x0Du)
-#define EXTI_LINE_46                        (EXTI_DIRECT   |              EXTI_REG2 | 0x0Eu)
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Mode  EXTI Mode
-  * @{
-  */
-#define EXTI_MODE_NONE                      0x00000000u
-#define EXTI_MODE_INTERRUPT                 0x00000001u
-#define EXTI_MODE_EVENT                     0x00000002u
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Trigger  EXTI Trigger
-  * @{
-  */
-#define EXTI_TRIGGER_NONE                   0x00000000u
-#define EXTI_TRIGGER_RISING                 0x00000001u
-#define EXTI_TRIGGER_FALLING                0x00000002u
-#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
-  * @brief
-  * @{
-  */
-#define EXTI_GPIOA                          0x00000000u
-#define EXTI_GPIOB                          0x00000001u
-#define EXTI_GPIOC                          0x00000002u
-#define EXTI_GPIOH                          0x00000007u
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants --------------------------------------------------------*/
-/** @defgroup EXTI_Private_Constants EXTI Private Constants
-  * @{
-  */
-/**
-  * @brief  EXTI Line property definition
-  */
-#define EXTI_PROPERTY_SHIFT                 24u
-#define EXTI_DIRECT                         (0x01uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
-#define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
-
-/**
-  * @brief  EXTI Event presence definition
-  */
-#define EXTI_EVENT_PRESENCE_SHIFT           28u
-#define EXTI_EVENT_PRESENCE_MASK           (0x01uL << EXTI_EVENT_PRESENCE_SHIFT)
-#define EXTI_EVENT                          EXTI_EVENT_PRESENCE_MASK
-
-/**
-  * @brief  EXTI Register and bit usage
-  */
-#define EXTI_REG_SHIFT                      16u
-#define EXTI_REG1                           (0x00uL << EXTI_REG_SHIFT)
-#define EXTI_REG2                           (0x01uL << EXTI_REG_SHIFT)
-#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2)
-#define EXTI_PIN_MASK                       0x0000001Fu
-
-/**
-  * @brief  EXTI Mask for interrupt & event mode
-  */
-#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
-
-/**
-  * @brief  EXTI Mask for trigger possibilities
-  */
-#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-
-/**
-  * @brief  EXTI Line number
-  */
-#define EXTI_LINE_NB                        47uL
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup EXTI_Private_Macros EXTI Private Macros
-  * @{
-  */
-#define IS_EXTI_LINE(__EXTI_LINE__)          ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00u) && \
-                                        ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT)   || \
-                                         (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)   || \
-                                         (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))    && \
-                                         (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \
-                                         (((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
-
-#define IS_EXTI_MODE(__EXTI_LINE__)          ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
-                                         (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
-
-#define IS_EXTI_TRIGGER(__EXTI_LINE__)       (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u)
-
-#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__)  ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
-
-#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__)   (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
-
-#define IS_EXTI_EVENT_PRESENT(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_EVENT) != 0x00u)
-
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
-                                         ((__PORT__) == EXTI_GPIOB) || \
-                                         ((__PORT__) == EXTI_GPIOC) || \
-                                         ((__PORT__) == EXTI_GPIOH))
-
-#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16u)
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
-  * @brief    EXTI Exported Functions
-  * @{
-  */
-
-/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
-  * @brief    Configuration functions
-  * @{
-  */
-/* Configuration functions ****************************************************/
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
-  * @brief    IO operation functions
-  * @{
-  */
-/* IO operation functions *****************************************************/
-void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
-uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_EXTI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h

@@ -1,1012 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_flash.h
-  * @author  MCD Application Team
-  * @brief   Header file of FLASH HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_FLASH_H
-#define STM32WLxx_HAL_FLASH_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
-  * @{
-  */
-
-/**
-  * @brief  FLASH Erase structure definition
-  */
-typedef struct
-{
-  uint32_t TypeErase;   /*!< Mass erase or page erase.
-                             This parameter can be a value of @ref FLASH_TYPE_ERASE */
-  uint32_t Page;        /*!< Initial Flash page to erase when page erase is enabled
-                             This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */
-  uint32_t NbPages;     /*!< Number of pages to be erased.
-                             This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)*/
-} FLASH_EraseInitTypeDef;
-
-/**
-  * @brief  FLASH Option Bytes Program structure definition
-  */
-typedef struct
-{
-  uint32_t OptionType;             /*!< Option byte to be configured.
-                                        This parameter can be a combination of the values of @ref FLASH_OB_TYPE */
-  uint32_t WRPArea;                 /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
-                                        Only one WRP area could be programmed at the same time.
-                                        This parameter can be value of @ref FLASH_OB_WRP_AREA */
-  uint32_t WRPStartOffset;         /*!< Write protection start offset (used for OPTIONBYTE_WRP).
-                                        This parameter must be a value between 0 and (max number of pages - 1) */
-  uint32_t WRPEndOffset;           /*!< Write protection end offset (used for OPTIONBYTE_WRP).
-                                        This parameter must be a value between WRPStartOffset and (max number of pages - 1) */
-  uint32_t RDPLevel;               /*!< Set the read protection level (used for OPTIONBYTE_RDP).
-                                        This parameter can be a value of @ref FLASH_OB_READ_PROTECTION */
-  uint32_t UserType;               /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
-                                        This parameter can be a combination of @ref FLASH_OB_USER_TYPE */
-#if defined(DUAL_CORE) /* Comment duplicated for Document generation */
-  uint32_t UserConfig;             /*!< Value of the user option byte (used for OPTIONBYTE_USER).
-                                        This parameter can be a combination of the values of
-                                            @ref FLASH_OB_USER_BOR_LEVEL
-                                            @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
-                                            @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
-                                            @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
-                                            @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nBOOT1,
-                                            @ref FLASH_OB_USER_SRAM2_PE, @ref FLASH_OB_USER_SRAM_RST,
-                                            @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
-                                            @ref FLASH_OB_USER_BOOT_LOCK, @ref FLASH_OB_USER_C2BOOT_LOCK */
-#else
-  uint32_t UserConfig;             /*!< Value of the user option byte (used for OPTIONBYTE_USER).
-                                        This parameter can be a combination of the values of
-                                            @ref FLASH_OB_USER_BOR_LEVEL
-                                            @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
-                                            @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
-                                            @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
-                                            @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_nBOOT1,
-                                            @ref FLASH_OB_USER_SRAM2_PE, @ref FLASH_OB_USER_SRAM_RST,
-                                            @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0,
-                                            @ref FLASH_OB_USER_BOOT_LOCK */
-#endif
-  uint32_t PCROPConfig;            /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
-                                        This parameter must be a combination of values of @ref FLASH_OB_PCROP_ZONE
-                                        and @ref FLASH_OB_PCROP_RDP */
-  uint32_t PCROP1AStartAddr;       /*!< PCROP Zone A Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
-                                        to protect. Make sure this parameter is multiple of PCROP granularity */
-  uint32_t PCROP1AEndAddr;         /*!< PCROP Zone A End address (used for OPTIONBYTE_PCROP). It represents first address of end block
-                                        to protect. Make sure this parameter is multiple of PCROP granularity */
-  uint32_t PCROP1BStartAddr;       /*!< PCROP Zone B Start address (used for OPTIONBYTE_PCROP). It represents first address of start block
-                                        to protect. Make sure this parameter is multiple of PCROP granularity */
-  uint32_t PCROP1BEndAddr;         /*!< PCROP Zone B End address (used for OPTIONBYTE_PCROP). It represents first address of end block
-                                        to protect. Make sure this parameter is multiple of PCROP granularity */
-#if defined(DUAL_CORE)
-  uint32_t SecureFlashStartAddr;   /*!< Secure Flash start address (used for OPTIONBYTE_SECURE_MODE).
-                                        This parameter must be a value between begin and end of Flash bank
-                                        => Contains the start address of the first 2kB page of the secure Flash area */
-  uint32_t SecureSRAM2StartAddr;   /*!< Secure Backup SRAM2 start address (used for OPTIONBYTE_SECURE_MODE).
-                                        This parameter must be aligned on 1kB boundary */
-  uint32_t SecureSRAM1StartAddr;   /*!< Secure non-Backup SRAM1 start address (used for OPTIONBYTE_SECURE_MODE)
-                                        This parameter must be aligned on 1kB boundary */
-  uint32_t HideProtectionStartAddr;/*!< Hide Protection area start address (used for OPTIONBYTE_SECURE_MODE)
-                                        This parameter must be aligned on 2kB boundary */
-  uint32_t SecureMode;             /*!< Secure mode activated or deactivated.
-                                        This parameter can be a value of @ref FLASH_OB_SECURITY_MODE */
-  uint32_t SUBGHZSPISecureAccess;  /*!< Sub-GHz radio SPI security access enabled or disabled (used for OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS).
-                                        This parameter can be a value of @ref FLASH_OB_SUBGHZSPI_SECURE_ACCESS */
-  uint32_t C2DebugAccessMode;      /*!< CPU2 debug access enabled or disabled (used for OPTIONBYTE_C2_DEBUG_ACCESS).
-                                        This parameter can be a value of @ref FLASH_OB_C2_DEBUG_ACCESS */
-  uint32_t C2BootRegion;           /*!< CPU2 Secure Boot memory region(used for OPTIONBYTE_C2_BOOT_VECT).
-                                        This parameter can be a value of @ref FLASH_OB_C2_BOOT_REGION */
-  uint32_t C2SecureBootVectAddr;   /*!< CPU2 Secure Boot reset vector (used for OPTIONBYTE_C2_BOOT_VECT).
-                                        This parameter contains the CPU2 boot reset start address within
-                                        the selected memory region. Make sure this parameter is word aligned. */
-  uint32_t IPCCdataBufAddr;        /*!< IPCC mailbox data buffer base address (used for OPTIONBYTE_IPCC_BUF_ADDR).
-                                        This parameter contains the IPCC mailbox data buffer start address area
-                                        in SRAM1 or SRAM2. Make sure this parameter is double-word aligned. */
-#endif /* DUAL_CORE */
-} FLASH_OBProgramInitTypeDef;
-
-/**
-* @brief  FLASH handle Structure definition
-*/
-typedef struct
-{
-  HAL_LockTypeDef   Lock;              /* FLASH locking object */
-  uint32_t          ErrorCode;         /* FLASH error code */
-  uint32_t          ProcedureOnGoing;  /* Internal variable to indicate which procedure is ongoing or not in IT context */
-  uint32_t          Address;           /* Internal variable to save address selected for program in IT context */
-  uint32_t          Page;              /* Internal variable to define the current page which is erasing in IT context */
-  uint32_t          NbPagesToErase;    /* Internal variable to save the remaining pages to erase in IT context */
-} FLASH_ProcessTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
-  * @{
-  */
-
-/** @defgroup FLASH_KEYS FLASH Keys
-  * @{
-  */
-#define FLASH_KEY1                      0x45670123U  /*!< Flash key1 */
-#define FLASH_KEY2                      0xCDEF89ABU  /*!< Flash key2: used with FLASH_KEY1
-                                                          to unlock the FLASH registers access */
-
-#define FLASH_OPTKEY1                   0x08192A3BU  /*!< Flash option byte key1 */
-#define FLASH_OPTKEY2                   0x4C5D6E7FU  /*!< Flash option byte key2: used with FLASH_OPTKEY1
-                                                          to allow option bytes operations */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_LATENCY FLASH Latency
-  * @{
-  */
-#define FLASH_LATENCY_0                 0x00000000U         /*!< FLASH Zero wait state */
-#define FLASH_LATENCY_1                 FLASH_ACR_LATENCY_0 /*!< FLASH One wait state */
-#define FLASH_LATENCY_2                 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_FLAGS FLASH Flags Definition
-  * @{
-  */
-#ifdef CORE_CM0PLUS
-#define FLASH_FLAG_EOP                  FLASH_C2SR_EOP      /*!< CPU2 FLASH End of operation flag */
-#define FLASH_FLAG_OPERR                FLASH_C2SR_OPERR    /*!< CPU2 FLASH Operation error flag */
-#define FLASH_FLAG_PROGERR              FLASH_C2SR_PROGERR  /*!< CPU2 FLASH Programming error flag */
-#define FLASH_FLAG_WRPERR               FLASH_C2SR_WRPERR   /*!< CPU2 FLASH Write protection error flag */
-#define FLASH_FLAG_PGAERR               FLASH_C2SR_PGAERR   /*!< CPU2 FLASH Programming alignment error flag */
-#define FLASH_FLAG_SIZERR               FLASH_C2SR_SIZERR   /*!< CPU2 FLASH Size error flag  */
-#define FLASH_FLAG_PGSERR               FLASH_C2SR_PGSERR   /*!< CPU2 FLASH Programming sequence error flag */
-#define FLASH_FLAG_MISERR               FLASH_C2SR_MISERR   /*!< CPU2 FLASH Fast programming data miss error flag */
-#define FLASH_FLAG_FASTERR              FLASH_C2SR_FASTERR  /*!< CPU2 FLASH Fast programming error flag */
-#define FLASH_FLAG_OPTNV                FLASH_C2SR_OPTNV    /*!< CPU2 FLASH User Option OPTVAL indication */
-#define FLASH_FLAG_RDERR                FLASH_C2SR_RDERR    /*!< CPU2 FLASH PCROP read error flag */
-#define FLASH_FLAG_OPTVERR              FLASH_SR_OPTVERR    /*!< FLASH Option validity error flag  */
-#define FLASH_FLAG_BSY                  FLASH_C2SR_BSY      /*!< CPU2 FLASH Busy flag */
-#define FLASH_FLAG_CFGBSY               FLASH_C2SR_CFGBSY   /*!< CPU2 FLASH Programming/erase configuration busy */
-#define FLASH_FLAG_PESD                 FLASH_C2SR_PESD     /*!< CPU2 FLASH Programming/erase operation suspended */
-#else
-#define FLASH_FLAG_EOP                  FLASH_SR_EOP      /*!< FLASH End of operation flag */
-#define FLASH_FLAG_OPERR                FLASH_SR_OPERR    /*!< FLASH Operation error flag */
-#define FLASH_FLAG_PROGERR              FLASH_SR_PROGERR  /*!< FLASH Programming error flag */
-#define FLASH_FLAG_WRPERR               FLASH_SR_WRPERR   /*!< FLASH Write protection error flag */
-#define FLASH_FLAG_PGAERR               FLASH_SR_PGAERR   /*!< FLASH Programming alignment error flag */
-#define FLASH_FLAG_SIZERR               FLASH_SR_SIZERR   /*!< FLASH Size error flag  */
-#define FLASH_FLAG_PGSERR               FLASH_SR_PGSERR   /*!< FLASH Programming sequence error flag */
-#define FLASH_FLAG_MISERR               FLASH_SR_MISERR   /*!< FLASH Fast programming data miss error flag */
-#define FLASH_FLAG_FASTERR              FLASH_SR_FASTERR  /*!< FLASH Fast programming error flag */
-#define FLASH_FLAG_OPTNV                FLASH_SR_OPTNV    /*!< FLASH User Option OPTVAL indication */
-#define FLASH_FLAG_RDERR                FLASH_SR_RDERR    /*!< FLASH PCROP read error flag */
-#define FLASH_FLAG_OPTVERR              FLASH_SR_OPTVERR  /*!< FLASH Option validity error flag  */
-#define FLASH_FLAG_BSY                  FLASH_SR_BSY      /*!< FLASH Busy flag */
-#define FLASH_FLAG_CFGBSY               FLASH_SR_CFGBSY   /*!< FLASH Programming/erase configuration busy */
-#define FLASH_FLAG_PESD                 FLASH_SR_PESD     /*!< FLASH Programming/erase operation suspended */
-#endif
-
-#define FLASH_FLAG_SR_ERRORS            (FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
-                                         FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \
-                                         FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \
-                                         FLASH_FLAG_OPTVERR)  /*!< All SR error flags */
-
-#define FLASH_FLAG_ECCC                 FLASH_ECCR_ECCC   /*!< FLASH ECC correction */
-#define FLASH_FLAG_ECCD                 FLASH_ECCR_ECCD   /*!< FLASH ECC detection */
-
-#define FLASH_FLAG_ECCR_ERRORS          (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
-
-#define FLASH_FLAG_ALL_ERRORS           (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
-
-/** @defgroup FLASH_INTERRUPT_DEFINITION FLASH Interrupts Definition
-  * @brief FLASH Interrupt definition
-  * @{
-  */
-#define FLASH_IT_EOP                    FLASH_CR_EOPIE     /*!< End of FLASH Operation Interrupt source */
-#define FLASH_IT_OPERR                  FLASH_CR_ERRIE     /*!< Error Interrupt source */
-#define FLASH_IT_RDERR                  FLASH_CR_RDERRIE   /*!< PCROP Read Error Interrupt source */
-#define FLASH_IT_ECCC                   (FLASH_ECCR_ECCCIE >> FLASH_ECCR_ECCCIE_Pos)  /*!< ECC Correction Interrupt source */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_ERROR FLASH Error
-  * @{
-  */
-#define HAL_FLASH_ERROR_NONE            0x00000000U
-#define HAL_FLASH_ERROR_OP              FLASH_FLAG_OPERR
-#define HAL_FLASH_ERROR_PROG            FLASH_FLAG_PROGERR
-#define HAL_FLASH_ERROR_WRP             FLASH_FLAG_WRPERR
-#define HAL_FLASH_ERROR_PGA             FLASH_FLAG_PGAERR
-#define HAL_FLASH_ERROR_SIZ             FLASH_FLAG_SIZERR
-#define HAL_FLASH_ERROR_PGS             FLASH_FLAG_PGSERR
-#define HAL_FLASH_ERROR_MIS             FLASH_FLAG_MISERR
-#define HAL_FLASH_ERROR_FAST            FLASH_FLAG_FASTERR
-#define HAL_FLASH_ERROR_RD              FLASH_FLAG_RDERR
-#define HAL_FLASH_ERROR_OPTV            FLASH_FLAG_OPTVERR
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_TYPE_ERASE FLASH Erase Type
-  * @{
-  */
-#define FLASH_TYPEERASE_PAGES           FLASH_CR_PER  /*!< Pages erase only*/
-#define FLASH_TYPEERASE_MASSERASE       FLASH_CR_MER  /*!< Flash mass erase activation*/
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_TYPE_PROGRAM FLASH Program Type
-  * @{
-  */
-#define FLASH_TYPEPROGRAM_DOUBLEWORD    FLASH_CR_PG     /*!< Program a double-word (64-bit) at a specified address.*/
-#define FLASH_TYPEPROGRAM_FAST          FLASH_CR_FSTPG  /*!< Fast program a 32 double-word (64-bit) row at a specified address.
-                                                             And another 32 double-word (64-bit) row will be programmed */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_TYPE FLASH Option Bytes Type
-  * @{
-  */
-#define OPTIONBYTE_WRP                  0x00000001U  /*!< WRP option byte configuration             */
-#define OPTIONBYTE_RDP                  0x00000002U  /*!< RDP option byte configuration             */
-#define OPTIONBYTE_USER                 0x00000004U  /*!< User option byte configuration            */
-#define OPTIONBYTE_PCROP                0x00000008U  /*!< PCROP option byte configuration           */
-#if defined(DUAL_CORE)
-#define OPTIONBYTE_IPCC_BUF_ADDR        0x00000010U  /*!< IPCC mailbox buffer address configuration */
-#define OPTIONBYTE_C2_BOOT_VECT         0x00000100U  /*!< CPU2 Secure Boot reset vector             */
-#define OPTIONBYTE_SECURE_MODE          0x00000200U  /*!< Secure mode on activated or not           */
-#define OPTIONBYTE_C2_DEBUG_ACCESS      0x00000400U  /*!< CPU2 debug access enabled or disabled     */
-#define OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS  0x00000800U  /*!< Sub-GHz radio SPI security access enabled or disabled  */
-
-#define OPTIONBYTE_ALL                  (OPTIONBYTE_WRP   | OPTIONBYTE_RDP           | OPTIONBYTE_USER         | \
-                                         OPTIONBYTE_PCROP | OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | \
-                                         OPTIONBYTE_SECURE_MODE | OPTIONBYTE_C2_DEBUG_ACCESS | OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS) /*!< All option byte configuration */
-#else
-
-#define OPTIONBYTE_ALL                  (OPTIONBYTE_WRP   | OPTIONBYTE_RDP           | OPTIONBYTE_USER         | \
-                                         OPTIONBYTE_PCROP) /*!< All option byte configuration */
-#endif /* DUAL_CORE */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_WRP_AREA FLASH WRP Area
-  * @{
-  */
-#define OB_WRPAREA_BANK1_AREAA          0x00000000U  /*!< Flash Area A */
-#define OB_WRPAREA_BANK1_AREAB          0x00000001U  /*!< Flash Area B */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_READ_PROTECTION FLASH Option Bytes Read Protection
-  * @{
-  */
-#define OB_RDP_LEVEL_0                  0x000000AAU
-#define OB_RDP_LEVEL_1                  0x000000BBU
-#define OB_RDP_LEVEL_2                  0x000000CCU  /*!< Warning: When enabling read protection level 2
-                                                          it's no more possible to go back to level 1 or 0 */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_TYPE FLASH Option Bytes User Type
-  * @{
-  */
-#define OB_USER_BOR_LEV                 FLASH_OPTR_BOR_LEV    /*!< BOR reset Level */
-#define OB_USER_nRST_STOP               FLASH_OPTR_nRST_STOP  /*!< Reset generated when entering the stop mode */
-#define OB_USER_nRST_STDBY              FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */
-#define OB_USER_nRST_SHDW               FLASH_OPTR_nRST_SHDW  /*!< Reset generated when entering the shutdown mode */
-#define OB_USER_IWDG_SW                 FLASH_OPTR_IWDG_SW    /*!< Independent watchdog selection */
-#define OB_USER_IWDG_STOP               FLASH_OPTR_IWDG_STOP  /*!< Independent watchdog counter freeze in stop mode */
-#define OB_USER_IWDG_STDBY              FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */
-#define OB_USER_WWDG_SW                 FLASH_OPTR_WWDG_SW    /*!< Window watchdog selection */
-#define OB_USER_nBOOT1                  FLASH_OPTR_nBOOT1     /*!< Boot configuration */
-#define OB_USER_SRAM2_PE                FLASH_OPTR_SRAM2_PE   /*!< SRAM2 parity check enable     */
-#define OB_USER_SRAM_RST                FLASH_OPTR_SRAM_RST   /*!< SRAM1 and SRAM2 erase when system reset */
-#define OB_USER_nSWBOOT0                FLASH_OPTR_nSWBOOT0   /*!< Software BOOT0 */
-#define OB_USER_nBOOT0                  FLASH_OPTR_nBOOT0     /*!< nBOOT0 option bit */
-#define OB_USER_BOOT_LOCK               FLASH_OPTR_BOOT_LOCK  /*!< CPU1 Boot Lock enable option bit */
-#if defined(DUAL_CORE)
-#define OB_USER_C2BOOT_LOCK             FLASH_OPTR_C2BOOT_LOCK /*!< CPU2 Boot Lock enable option bit */
-#endif
-
-#if defined(DUAL_CORE)
-#define OB_USER_ALL                     (OB_USER_BOR_LEV    | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \
-                                         OB_USER_nRST_SHDW  | OB_USER_IWDG_SW   | OB_USER_IWDG_STOP  | \
-                                         OB_USER_IWDG_STDBY | OB_USER_WWDG_SW   | OB_USER_nBOOT1     | \
-                                         OB_USER_SRAM2_PE   | OB_USER_SRAM_RST  | OB_USER_nSWBOOT0   | \
-                                         OB_USER_nBOOT0     | OB_USER_BOOT_LOCK | OB_USER_C2BOOT_LOCK)   /*!< all option bits */
-#else
-#define OB_USER_ALL                     (OB_USER_BOR_LEV    | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \
-                                         OB_USER_nRST_SHDW  | OB_USER_IWDG_SW   | OB_USER_IWDG_STOP  | \
-                                         OB_USER_IWDG_STDBY | OB_USER_WWDG_SW   | OB_USER_nBOOT1     | \
-                                         OB_USER_SRAM2_PE   | OB_USER_SRAM_RST  | OB_USER_nSWBOOT0   | \
-                                         OB_USER_nBOOT0     | OB_USER_BOOT_LOCK)   /*!< all option bits */
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
-  * @{
-  */
-#define OB_BOR_LEVEL_0                  0x00000000U                                   /*!< Reset level threshold is around 1.7V */
-#define OB_BOR_LEVEL_1                  FLASH_OPTR_BOR_LEV_0                          /*!< Reset level threshold is around 2.0V */
-#define OB_BOR_LEVEL_2                  FLASH_OPTR_BOR_LEV_1                          /*!< Reset level threshold is around 2.2V */
-#define OB_BOR_LEVEL_3                  (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.5V */
-#define OB_BOR_LEVEL_4                  FLASH_OPTR_BOR_LEV_2                          /*!< Reset level threshold is around 2.8V */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
-  * @{
-  */
-#define OB_STOP_RST                     0x00000000U           /*!< Reset generated when entering the stop mode    */
-#define OB_STOP_NORST                   FLASH_OPTR_nRST_STOP  /*!< No reset generated when entering the stop mode */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
-  * @{
-  */
-#define OB_STANDBY_RST                  0x00000000U           /*!< Reset generated when entering the standby mode    */
-#define OB_STANDBY_NORST                FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
-  * @{
-  */
-#define OB_SHUTDOWN_RST                 0x00000000U           /*!< Reset generated when entering the shutdown mode    */
-#define OB_SHUTDOWN_NORST               FLASH_OPTR_nRST_SHDW  /*!< No reset generated when entering the shutdown mode */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
-  * @{
-  */
-#define OB_IWDG_HW                      0x00000000U         /*!< Hardware independent watchdog */
-#define OB_IWDG_SW                      FLASH_OPTR_IWDG_SW  /*!< Software independent watchdog */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
-  * @{
-  */
-#define OB_IWDG_STOP_FREEZE             0x00000000U           /*!< Independent watchdog counter is frozen in Stop mode  */
-#define OB_IWDG_STOP_RUN                FLASH_OPTR_IWDG_STOP  /*!< Independent watchdog counter is running in Stop mode */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
-  * @{
-  */
-#define OB_IWDG_STDBY_FREEZE            0x00000000U            /*!< Independent watchdog counter is frozen in Standby mode  */
-#define OB_IWDG_STDBY_RUN               FLASH_OPTR_IWDG_STDBY  /*!< Independent watchdog counter is running in Standby mode */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
-  * @{
-  */
-#define OB_WWDG_HW                      0x00000000U         /*!< Hardware window watchdog */
-#define OB_WWDG_SW                      FLASH_OPTR_WWDG_SW  /*!< Software window watchdog */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes SRAM2 parity check
-  * @{
-  */
-#define OB_SRAM2_PARITY_ENABLE          0x00000000U          /*!< SRAM2 parity check enable  */
-#define OB_SRAM2_PARITY_DISABLE         FLASH_OPTR_SRAM2_PE  /*!< SRAM2 parity check disable */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_SRAM_RST FLASH Option Bytes SRAM1 and SRAM2 erase when system reset
-  * @{
-  */
-#define OB_SRAM_RST_ERASE               0x00000000U         /*!< SRAM2 and SRAM1 erased when a system reset        */
-#define OB_SRAM_RST_NOT_ERASE           FLASH_OPTR_SRAM_RST /*!< SRAM2 and SRAM1 is not erased when a system reset */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
-  * @{
-  */
-#define OB_BOOT1_RESET                  0x00000000U        /*!< nBOOT1 = 0 */
-#define OB_BOOT1_SET                    FLASH_OPTR_nBOOT1  /*!< nBOOT1 = 1 */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
-  * @{
-  */
-#define OB_BOOT0_FROM_OB                0x00000000U          /*!< BOOT0 taken from the option bit nBOOT0 */
-#define OB_BOOT0_FROM_PIN               FLASH_OPTR_nSWBOOT0  /*!< BOOT0 taken from PH3/BOOT0 pin         */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
-  * @{
-  */
-#define OB_BOOT0_RESET                  0x00000000U        /*!< nBOOT0 = 0 */
-#define OB_BOOT0_SET                    FLASH_OPTR_nBOOT0  /*!< nBOOT0 = 1 */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_USER_BOOT_LOCK FLASH Option Bytes CPU1 Boot Lock option bit
-  * @{
-  */
-#define OB_BOOT_LOCK_DISABLE            0x00000000U           /*!< BOOT_LOCK = 0 */
-#define OB_BOOT_LOCK_ENABLE             FLASH_OPTR_BOOT_LOCK  /*!< BOOT_LOCK = 1 */
-/**
-  * @}
-  */
-
-#if defined(DUAL_CORE)
-/** @defgroup FLASH_OB_USER_C2BOOT_LOCK FLASH Option Bytes CPU2 Boot Lock option bit
-  * @{
-  */
-#define OB_C2BOOT_LOCK_DISABLE          0x00000000U             /*!< C2BOOT_LOCK = 0 */
-#define OB_C2BOOT_LOCK_ENABLE           FLASH_OPTR_C2BOOT_LOCK  /*!< C2BOOT_LOCK = 1 */
-/**
-  * @}
-  */
-#endif /* DUAL_CORE */
-
-/** @defgroup FLASH_OB_PCROP_ZONE FLASH PCROP ZONE
-  * @{
-  */
-#define OB_PCROP_ZONE_A                 0x00000001U  /*!< PCROP Zone A */
-#define OB_PCROP_ZONE_B                 0x00000002U  /*!< PCROP Zone B */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
-  * @{
-  */
-#define OB_PCROP_RDP_NOT_ERASE          0x00000000U                /*!< PCROP area is not erased when the RDP level
-                                                                        is decreased from Level 1 to Level 0 */
-#define OB_PCROP_RDP_ERASE              FLASH_PCROP1AER_PCROP_RDP  /*!< PCROP area is erased when the RDP level is
-                                                                        decreased from Level 1 to Level 0 (full mass erase) */
-/**
-  * @}
-  */
-
-#if defined(DUAL_CORE)
-/** @defgroup FLASH_OB_SECURITY_MODE Option Bytes FLASH Secure mode
-  * @{
-  */
-#define OB_SECURE_SYSTEM_AND_FLASH_ENABLE       0x00000001U     /*!< Flash and System secure area enabled  */
-#define OB_SECURE_HIDE_PROTECTION_ENABLE        0x00000002U     /*!< Hide Protection area enabled          */
-#define OB_SECURE_SRAM1_ENABLE                  0x00000004U     /*!< SRAM1 area enabled                    */
-#define OB_SECURE_SRAM2_ENABLE                  0x00000008U     /*!< SRAM2 area enabled                    */
-#define OB_SECURE_SYSTEM_AND_FLASH_DISABLE      0x00000010U     /*!< Flash and System secure area disabled */
-#define OB_SECURE_HIDE_PROTECTION_DISABLE       0x00000020U     /*!< Hide Protection area disabled         */
-#define OB_SECURE_SRAM1_DISABLE                 0x00000040U     /*!< SRAM1 area disabled                   */
-#define OB_SECURE_SRAM2_DISABLE                 0x00000080U     /*!< SRAM2 area disabled                   */
-#define OB_SECURE_SYSTEM_AND_ALL_AREAS_ENABLE   (OB_SECURE_SYSTEM_AND_FLASH_ENABLE | OB_SECURE_HIDE_PROTECTION_ENABLE | \
-                                                 OB_SECURE_SRAM1_ENABLE            | OB_SECURE_SRAM2_ENABLE)               /*!< All System in Secure mode : Security enabled on all areas */
-#define OB_SECURE_SYSTEM_AND_ALL_AREAS_DISABLE  (OB_SECURE_SYSTEM_AND_FLASH_DISABLE | OB_SECURE_HIDE_PROTECTION_DISABLE | \
-                                                 OB_SECURE_SRAM1_DISABLE            | OB_SECURE_SRAM2_DISABLE)               /*!< Unsecure mode: Security disabled      */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_SUBGHZSPI_SECURE_ACCESS Option Bytes Sub-GHz radio SPI Secure Access
-  * @{
-  */
-#define OB_SUBGHZSPI_SECURE_ACCESS_DISABLE      FLASH_SFR_SUBGHZSPISD  /*!< Sub-GHz radio SPI Secure access disabled  */
-#define OB_SUBGHZSPI_SECURE_ACCESS_ENABLE       0x00000000U       /*!< Sub-GHz radio SPI Secure access enabled   */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_C2_DEBUG_ACCESS Option Bytes CPU2 Debug Access
-  * @{
-  */
-#define OB_C2_DEBUG_ACCESS_DISABLE         FLASH_SFR_DDS /*!< CPU2 debug access disabled   */
-#define OB_C2_DEBUG_ACCESS_ENABLE          0x00000000U   /*!< CPU2 debug access enabled (when also enabled by FLASH_ACR2_C2SWDBGEN) */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_OB_C2_BOOT_REGION CPU2 Option Bytes Reset Boot Vector
-  * @{
-  */
-#define OB_C2_BOOT_FROM_SRAM               0x00000000U        /*!< CPU2 boot from SRAM1 or SRAM2 */
-#define OB_C2_BOOT_FROM_FLASH              FLASH_SRRVR_C2OPT  /*!< CPU2 boot from Flash          */
-/**
-  * @}
-  */
-#endif /* DUAL_CORE */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
-  *  @brief macros to control FLASH features
-  *  @{
-  */
-
-/**
-  * @brief  Set the FLASH Latency.
-  * @param __LATENCY__ FLASH Latency
-  *         This parameter can be one of the following values :
-  *     @arg @ref FLASH_LATENCY_0 FLASH Zero wait state
-  *     @arg @ref FLASH_LATENCY_1 FLASH One wait state
-  *     @arg @ref FLASH_LATENCY_2 FLASH Two wait states
-  * @retval None
-  */
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__)    MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
-
-/**
-  * @brief  Get the FLASH Latency.
-  * @retval FLASH Latency
-  *         Returned value can be one of the following values :
-  *     @arg @ref FLASH_LATENCY_0 FLASH Zero wait state
-  *     @arg @ref FLASH_LATENCY_1 FLASH One wait state
-  *     @arg @ref FLASH_LATENCY_2 FLASH Two wait states
-  */
-#define __HAL_FLASH_GET_LATENCY()               READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
-
-/**
-  * @brief  Enable the FLASH prefetch buffer.
-  * @retval None
-  */
-#ifdef CORE_CM0PLUS
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    SET_BIT(FLASH->C2ACR, FLASH_C2ACR_PRFTEN)
-#else
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
-#endif
-
-/**
-  * @brief  Disable the FLASH prefetch buffer.
-  * @retval None
-  */
-#ifdef CORE_CM0PLUS
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_PRFTEN)
-#else
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
-#endif
-
-/**
-  * @brief  Enable the FLASH instruction cache.
-  * @retval none
-  */
-#ifdef CORE_CM0PLUS
-#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  SET_BIT(FLASH->C2ACR, FLASH_C2ACR_ICEN)
-#else
-#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
-#endif
-
-/**
-  * @brief  Disable the FLASH instruction cache.
-  * @retval none
-  */
-#ifdef CORE_CM0PLUS
-#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_ICEN)
-#else
-#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
-#endif
-
-/**
-  * @brief  Enable the FLASH data cache.
-  * @retval none
-  */
-#ifdef CORE_CM0PLUS
-#else
-#define __HAL_FLASH_DATA_CACHE_ENABLE()         SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
-#endif
-
-/**
-  * @brief  Disable the FLASH data cache.
-  * @retval none
-  */
-#ifdef CORE_CM0PLUS
-#else
-#define __HAL_FLASH_DATA_CACHE_DISABLE()        CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
-#endif
-
-/**
-  * @brief  Reset the FLASH instruction Cache.
-  * @note   This function must be used only when the Instruction Cache is disabled.
-  * @retval None
-  */
-#ifdef CORE_CM0PLUS
-#define __HAL_FLASH_INSTRUCTION_CACHE_RESET()   do { SET_BIT(FLASH->C2ACR, FLASH_C2ACR_ICRST);   \
-                                                     CLEAR_BIT(FLASH->C2ACR, FLASH_C2ACR_ICRST); \
-                                                   } while (0)
-#else
-#define __HAL_FLASH_INSTRUCTION_CACHE_RESET()   do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \
-                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
-                                                   } while (0)
-#endif
-
-/**
-  * @brief  Reset the FLASH data Cache.
-  * @note   This function must be used only when the data Cache is disabled.
-  * @retval None
-  */
-#ifdef CORE_CM0PLUS
-#else
-#define __HAL_FLASH_DATA_CACHE_RESET()          do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);   \
-                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
-                                                   } while (0)
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
- *  @brief macros to handle FLASH interrupts
- * @{
- */
-
-/**
-  * @brief  Enable the specified FLASH interrupt.
-  * @param __INTERRUPT__ FLASH interrupt
-  *         This parameter can be any combination of the following values:
-  *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
-  *     @arg @ref FLASH_IT_OPERR Error Interrupt
-  *     @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt
-  *     @arg @ref FLASH_IT_ECCC ECC Correction Interrupt
-  * @retval none
-  */
-#ifdef CORE_CM0PLUS
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\
-                                                     if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->C2CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
-                                                   } while(0)
-#else
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\
-                                                     if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
-                                                   } while(0)
-#endif
-
-/**
-  * @brief  Disable the specified FLASH interrupt.
-  * @param __INTERRUPT__ FLASH interrupt
-  *         This parameter can be any combination of the following values:
-  *     @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt
-  *     @arg @ref FLASH_IT_OPERR Error Interrupt
-  *     @arg @ref FLASH_IT_RDERR PCROP Read Error Interrupt
-  *     @arg @ref FLASH_IT_ECCC ECC Correction Interrupt
-  * @retval none
-  */
-#ifdef CORE_CM0PLUS
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\
-                                                     if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->C2CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
-                                                   } while(0)
-#else
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCCIE); }\
-                                                     if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
-                                                   } while(0)
-#endif
-
-/**
-  * @brief  Check whether the specified FLASH flag is set or not.
-  * @param __FLAG__ specifies the FLASH flag to check.
-  *   This parameter can be one of the following values:
-  *     @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
-  *     @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag
-  *     @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag
-  *     @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag
-  *     @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag
-  *     @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
-  *     @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag
-  *     @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
-  *     @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag
-  *     @arg @ref FLASH_FLAG_OPTNV FLASH User Option OPTVAL indication
-  *     @arg @ref FLASH_FLAG_RDERR FLASH PCROP read  error flag
-  *     @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
-  *     @arg @ref FLASH_FLAG_BSY FLASH write/erase operations in progress flag
-  *     @arg @ref FLASH_FLAG_CFGBSY Programming/erase configuration busy
-  *     @arg @ref FLASH_FLAG_PESD FLASH Programming/erase operation suspended
-  *     @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected
-  *     @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected
-  * @retval The new state of FLASH_FLAG (SET or RESET).
-  */
-#ifdef CORE_CM0PLUS
-#define __HAL_FLASH_GET_FLAG(__FLAG__)          ((((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) ? \
-                                                 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__))  : \
-                                                 ((((__FLAG__) & FLASH_FLAG_OPTVERR) != 0U) ? \
-                                                  (READ_BIT(FLASH->SR,   (__FLAG__)) == (__FLAG__))  : \
-                                                  (READ_BIT(FLASH->C2SR,   (__FLAG__)) == (__FLAG__))))
-#else
-#define __HAL_FLASH_GET_FLAG(__FLAG__)          ((((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) ? \
-                                                 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__))  : \
-                                                 (READ_BIT(FLASH->SR,   (__FLAG__)) == (__FLAG__)))
-#endif
-/**
-  * @brief  Clear the FLASH's pending flags.
-  * @param __FLAG__ specifies the FLASH flags to clear.
-  *   This parameter can be any combination of the following values:
-  *     @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag
-  *     @arg @ref FLASH_FLAG_OPERR FLASH Operation error flag
-  *     @arg @ref FLASH_FLAG_PROGERR FLASH Programming error flag
-  *     @arg @ref FLASH_FLAG_WRPERR FLASH Write protection error flag
-  *     @arg @ref FLASH_FLAG_PGAERR FLASH Programming alignment error flag
-  *     @arg @ref FLASH_FLAG_SIZERR FLASH Size error flag
-  *     @arg @ref FLASH_FLAG_PGSERR FLASH Programming sequence error flag
-  *     @arg @ref FLASH_FLAG_MISERR FLASH Fast programming data miss error flag
-  *     @arg @ref FLASH_FLAG_FASTERR FLASH Fast programming error flag
-  *     @arg @ref FLASH_FLAG_RDERR FLASH PCROP read  error flag
-  *     @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
-  *     @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected
-  *     @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected
-  *     @arg @ref FLASH_FLAG_SR_ERRORS FLASH All SR errors flags
-  *     @arg @ref FLASH_FLAG_ECCR_ERRORS FLASH All ECCR errors flags
-  *     @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags
-  * @retval None
-  */
-#ifdef CORE_CM0PLUS
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        do { if(((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS))); }\
-                                                     if(((__FLAG__) & FLASH_FLAG_OPTVERR) != 0U) { SET_BIT(FLASH->SR, FLASH_FLAG_OPTVERR); }\
-                                                     if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->C2SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
-                                                   } while(0)
-#else
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        do { if(((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS))); }\
-                                                     if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
-                                                   } while(0)
-#endif
-/**
-  * @}
-  */
-
-/* Include FLASH HAL Extended module */
-#include "stm32wlxx_hal_flash_ex.h"
-/* Exported variables --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Variables FLASH Exported Variables
-  * @{
-  */
-extern FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_Exported_Functions
-  * @{
-  */
-
-/* Program operation functions  ***********************************************/
-/** @addtogroup FLASH_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef  HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-HAL_StatusTypeDef  HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-/* FLASH IRQ handler method */
-void               HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */
-void               HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void               HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  **********************************************/
-/** @addtogroup FLASH_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef  HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef  HAL_FLASH_Lock(void);
-/* Option bytes control */
-HAL_StatusTypeDef  HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef  HAL_FLASH_OB_Lock(void);
-HAL_StatusTypeDef  HAL_FLASH_OB_Launch(void);
-/**
-  * @}
-  */
-
-/* Peripheral State functions  ************************************************/
-/** @addtogroup FLASH_Exported_Functions_Group3
-  * @{
-  */
-uint32_t HAL_FLASH_GetError(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types --------------------------------------------------------*/
-/** @defgroup FLASH_Private_types FLASH Private Types
-  * @{
-  */
-HAL_StatusTypeDef  FLASH_WaitForLastOperation(uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Private constants --------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
-  * @{
-  */
-#define FLASH_END_ADDR                          (FLASH_BASE + FLASH_SIZE - 1U)
-
-#define FLASH_BANK_SIZE                         FLASH_SIZE   /*!< FLASH Bank Size */
-#define FLASH_PAGE_SIZE                         0x00000800U  /*!< FLASH Page Size, 2 KBytes */
-#define FLASH_PAGE_NB                           128U
-#define FLASH_TIMEOUT_VALUE                     1000U        /*!< FLASH Execution Timeout, 1 s */
-
-#define FLASH_PCROP_GRANULARITY_OFFSET          10U                                        /*!< FLASH Code Readout Protection granularity offset */
-#define FLASH_PCROP_GRANULARITY                 (1UL << FLASH_PCROP_GRANULARITY_OFFSET)    /*!< FLASH Code Readout Protection granularity, 1 KBytes */
-
-#define FLASH_TYPENONE                          0x00000000U                                /*!< No Programmation Procedure On Going */
-
-/** @defgroup SRAM_MEMORY_SIZE  SRAM memory size
-  * @{
-  */
-#define SRAM_SECURE_PAGE_GRANULARITY_OFFSET     10U                                      /*!< Secure SRAM1 and SRAM2 Protection granularity offset */
-#define SRAM_SECURE_PAGE_GRANULARITY            (1UL << FLASH_PCROP_GRANULARITY_OFFSET)  /*!< Secure SRAM1 and SRAM2 Protection granularity, 1KBytes */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
- *  @{
- */
-#define IS_FLASH_MAIN_MEM_ADDRESS(__VALUE__)        (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL)))
-
-#define IS_FLASH_FAST_PROGRAM_ADDRESS(__VALUE__)    (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL))
-
-#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__)   (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL))
-
-#define IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__)     (((__VALUE__) >= OTP_AREA_BASE) && ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL))
-
-#define IS_FLASH_PROGRAM_ADDRESS(__VALUE__)         (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) || IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__))
-
-#define IS_FLASH_PAGE(__VALUE__)                    ((__VALUE__) < FLASH_PAGE_NB)
-
-#define IS_ADDR_ALIGNED_64BITS(__VALUE__)           (((__VALUE__) & 0x7U) == (0x00UL))
-
-#define IS_FLASH_TYPEERASE(__VALUE__)               (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \
-                                                     ((__VALUE__) == FLASH_TYPEERASE_MASSERASE))
-
-#define IS_FLASH_TYPEPROGRAM(__VALUE__)             (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
-                                                     ((__VALUE__) == FLASH_TYPEPROGRAM_FAST))
-
-#if defined(DUAL_CORE)
-#define IS_OB_SFSA_START_ADDR(__VALUE__)            (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~0x7FFU) == (__VALUE__)))
-#define IS_OB_HDPSA_START_ADDR(__VALUE__)           IS_OB_SFSA_START_ADDR(__VALUE__)
-#define IS_OB_SBRSA_START_ADDR(__VALUE__)           (((__VALUE__) >= SRAM2_BASE) && ((__VALUE__) <= (SRAM2_BASE + SRAM2_SIZE)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
-#define IS_OB_SNBRSA_START_ADDR(__VALUE__)          (((__VALUE__) >= SRAM1_BASE) && ((__VALUE__) <= (SRAM1_BASE + SRAM1_SIZE)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
-
-#define IS_OB_SECURE_MODE(__VALUE__)                ( (((__VALUE__) &  (OB_SECURE_SYSTEM_AND_ALL_AREAS_ENABLE | OB_SECURE_SYSTEM_AND_ALL_AREAS_DISABLE)) != 0U)  && \
-                                                      (((__VALUE__) & ~(OB_SECURE_SYSTEM_AND_ALL_AREAS_ENABLE | OB_SECURE_SYSTEM_AND_ALL_AREAS_DISABLE)) == 0U)  && \
-                                                      (((__VALUE__) &  (OB_SECURE_SYSTEM_AND_FLASH_ENABLE     | OB_SECURE_SYSTEM_AND_FLASH_DISABLE))     != (OB_SECURE_SYSTEM_AND_FLASH_ENABLE | OB_SECURE_SYSTEM_AND_FLASH_DISABLE)) && \
-                                                      (((__VALUE__) &  (OB_SECURE_HIDE_PROTECTION_ENABLE      | OB_SECURE_HIDE_PROTECTION_DISABLE))      != (OB_SECURE_HIDE_PROTECTION_ENABLE  | OB_SECURE_HIDE_PROTECTION_DISABLE))  && \
-                                                      (((__VALUE__) &  (OB_SECURE_SRAM1_ENABLE                | OB_SECURE_SRAM1_DISABLE))                != (OB_SECURE_SRAM1_ENABLE            | OB_SECURE_SRAM1_DISABLE))            && \
-                                                      (((__VALUE__) &  (OB_SECURE_SRAM2_ENABLE                | OB_SECURE_SRAM2_DISABLE))                != (OB_SECURE_SRAM2_ENABLE            | OB_SECURE_SRAM2_DISABLE)) )
-#endif /* DUAL_CORE */
-
-#if defined(DUAL_CORE)
-#define IS_OPTIONBYTE(__VALUE__)                    ((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \
-                                                              OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | OPTIONBYTE_SECURE_MODE | \
-                                                              OPTIONBYTE_C2_DEBUG_ACCESS | OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS))
-
-#else
-
-#define IS_OPTIONBYTE(__VALUE__)                    ((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP))
-#endif /* DUAL_CORE */
-
-#define IS_OB_WRPAREA(__VALUE__)                    (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) || ((__VALUE__) == OB_WRPAREA_BANK1_AREAB))
-
-#define IS_OB_RDP_LEVEL(__VALUE__)                  (((__VALUE__) == OB_RDP_LEVEL_0)   ||\
-                                                     ((__VALUE__) == OB_RDP_LEVEL_1)   ||\
-                                                     ((__VALUE__) == OB_RDP_LEVEL_2))
-
-#define IS_OB_USER_TYPE(__VALUE__)                  ((((__VALUE__) & OB_USER_ALL) != 0U) && \
-                                                     (((__VALUE__) & ~OB_USER_ALL) == 0U))
-
-#define IS_OB_USER_CONFIG(__TYPE__, __VALUE__)      ((((__TYPE__) & OB_USER_BOR_LEV) == OB_USER_BOR_LEV) \
-                                                      ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_0) || \
-                                                         (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_1) || \
-                                                         (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_2) || \
-                                                         (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_3) || \
-                                                         (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_4)) \
-                                                      : ((~(__TYPE__) & (__VALUE__)) == 0U))
-
-#define IS_OB_USER_BOR_LEVEL(__VALUE__)             (((__VALUE__) == OB_BOR_LEVEL_0) || ((__VALUE__) == OB_BOR_LEVEL_1) || \
-                                                     ((__VALUE__) == OB_BOR_LEVEL_2) || ((__VALUE__) == OB_BOR_LEVEL_3) || \
-                                                     ((__VALUE__) == OB_BOR_LEVEL_4))
-
-#define IS_OB_PCROP_CONFIG(__VALUE__)               (((__VALUE__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U)
-
-#if defined(DUAL_CORE)
-#define IS_OB_IPCC_BUF_ADDR(__VALUE__)              (IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__))
-
-#define IS_OB_BOOT_VECTOR_ADDR(__VALUE__)           (IS_OB_SFSA_START_ADDR(__VALUE__) || IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__))
-#define IS_OB_BOOT_REGION(__VALUE__)                (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) || ((__VALUE__) == OB_C2_BOOT_FROM_SRAM))
-
-#define IS_OB_SUBGHZSPI_SECURE_ACCESS(__VALUE__)         (((__VALUE__) == OB_SUBGHZSPI_SECURE_ACCESS_ENABLE) || ((__VALUE__) == OB_SUBGHZSPI_SECURE_ACCESS_DISABLE))
-
-#define IS_OB_C2_DEBUG_MODE(__VALUE__)              (((__VALUE__) == OB_C2_DEBUG_ACCESS_ENABLE) || ((__VALUE__) == OB_C2_DEBUG_ACCESS_DISABLE))
-#endif /* DUAL_CORE */
-
-#define IS_FLASH_LATENCY(__VALUE__)                 (((__VALUE__) == FLASH_LATENCY_0) || \
-                                                     ((__VALUE__) == FLASH_LATENCY_1) || \
-                                                     ((__VALUE__) == FLASH_LATENCY_2))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_FLASH_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h

@@ -1,133 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_flash_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of FLASH HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                       opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_FLASH_EX_H
-#define STM32WLxx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASHEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
-  * @{
-  */
-/** @defgroup FLASHEx_EMPTY_CHECK FLASHEx Empty Check
-  * @{
-  */
-#define FLASH_PROG_NOT_EMPTY            0x00000000U     /*!< 1st location in Flash is programmed */
-#define FLASH_PROG_EMPTY                FLASH_ACR_EMPTY /*!< 1st location in Flash is empty      */
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_PRIV_MODE_CFG FLASHEx privilege mode configuration
-  * @{
-  */
-#define FLASH_PRIV_GRANTED              0x00000000U         /*!< access to Flash registers is granted                        */
-#define FLASH_PRIV_DENIED               FLASH_ACR2_PRIVMODE /*!< access to Flash registers is denied to non-privilege access */
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASHEx_Exported_Functions
-  * @{
-  */
-
-/* Extended Program operation functions  *************************************/
-/** @addtogroup FLASHEx_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-uint32_t          HAL_FLASHEx_FlashEmptyCheck(void);
-void              HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty);
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-void              HAL_FLASHEx_SuspendOperation(void);
-void              HAL_FLASHEx_AllowOperation(void);
-uint32_t          HAL_FLASHEx_IsOperationSuspended(void);
-#if defined(DUAL_CORE)
-void              HAL_FLASHEx_DisableC2Debug(void);
-void              HAL_FLASHEx_EnableC2Debug(void);
-void              HAL_FLASHEx_EnableSecHideProtection(void);
-void              HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode);
-uint32_t          HAL_FLASHEx_GetPrivMode(void);
-#endif /* DUAL_CORE */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
-  *  @{
-  */
-#define IS_FLASH_EMPTY_CHECK(__VALUE__)         (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY))
-
-#define IS_FLASH_CFGPRIVMODE(__VALUE__)         (((__VALUE__) == FLASH_PRIV_GRANTED) || ((__VALUE__) == FLASH_PRIV_DENIED))
-/**
-  * @}
-  */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
-  * @{
-  */
-void              FLASH_PageErase(uint32_t Page);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_FLASH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h

@@ -1,326 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_gpio.h
-  * @author  MCD Application Team
-  * @brief   Header file of GPIO HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_GPIO_H
-#define STM32WLxx_HAL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIO GPIO
-  * @brief GPIO HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
-  * @{
-  */
-/**
-  * @brief   GPIO Init structure definition
-  */
-typedef struct
-{
-  uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
-                           This parameter can be any value of @ref GPIO_pins */
-
-  uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref GPIO_mode */
-
-  uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
-                           This parameter can be a value of @ref GPIO_pull */
-
-  uint32_t Speed;      /*!< Specifies the speed for the selected pins.
-                           This parameter can be a value of @ref GPIO_speed */
-
-  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
-                            This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
-} GPIO_InitTypeDef;
-
-/**
-  * @brief  GPIO Bit SET and Bit RESET enumeration
-  */
-typedef enum
-{
-  GPIO_PIN_RESET = 0U,
-  GPIO_PIN_SET
-} GPIO_PinState;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
-  * @{
-  */
-/** @defgroup GPIO_pins GPIO pins
-  * @{
-  */
-#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
-#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
-#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
-#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
-#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
-#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
-#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
-#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
-#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
-#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
-#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
-#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
-#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
-#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
-#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
-#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
-#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
-
-#define GPIO_PIN_MASK              (0x0000FFFFu) /* PIN mask for assert test */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_mode GPIO mode
-  * @brief GPIO Configuration Mode
-  *        Elements values convention: 0x00WX00YZ
-  *           - W  : EXTI trigger detection on 3 bits
-  *           - X  : EXTI mode (IT or Event) on 2 bits
-  *           - Y  : Output type (Push Pull or Open Drain) on 1 bit
-  *           - Z  : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
-  * @{
-  */
-#define GPIO_MODE_INPUT                 MODE_INPUT                                                  /*!< Input Floating Mode                                                */
-#define GPIO_MODE_OUTPUT_PP             (MODE_OUTPUT | OUTPUT_PP)                                   /*!< Output Push Pull Mode                                              */
-#define GPIO_MODE_OUTPUT_OD             (MODE_OUTPUT | OUTPUT_OD)                                   /*!< Output Open Drain Mode                                             */
-#define GPIO_MODE_AF_PP                 (MODE_AF | OUTPUT_PP)                                       /*!< Alternate Function Push Pull Mode                                  */
-#define GPIO_MODE_AF_OD                 (MODE_AF | OUTPUT_OD)                                       /*!< Alternate Function Open Drain Mode                                 */
-#define GPIO_MODE_ANALOG                MODE_ANALOG                                                 /*!< Analog Mode                                                        */
-#define GPIO_MODE_IT_RISING             (MODE_INPUT | EXTI_IT | TRIGGER_RISING)                     /*!< External Interrupt Mode with Rising edge trigger detection         */
-#define GPIO_MODE_IT_FALLING            (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)                    /*!< External Interrupt Mode with Falling edge trigger detection        */
-#define GPIO_MODE_IT_RISING_FALLING     (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define GPIO_MODE_EVT_RISING            (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)                    /*!< External Event Mode with Rising edge trigger detection             */
-#define GPIO_MODE_EVT_FALLING           (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)                   /*!< External Event Mode with Falling edge trigger detection            */
-#define GPIO_MODE_EVT_RISING_FALLING    (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)  /*!< External Event Mode with Rising/Falling edge trigger detection     */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_speed GPIO speed
-  * @brief GPIO Output Maximum frequency
-  * @{
-  */
-#define GPIO_SPEED_FREQ_LOW             0x00000000u  /*!< Low speed       */
-#define GPIO_SPEED_FREQ_MEDIUM          0x00000001u  /*!< Medium speed    */
-#define GPIO_SPEED_FREQ_HIGH            0x00000002u  /*!< High speed      */
-#define GPIO_SPEED_FREQ_VERY_HIGH       0x00000003u  /*!< Very high speed */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_pull GPIO pull
-  * @brief GPIO Pull-Up or Pull-Down Activation
-  * @{
-  */
-#define GPIO_NOPULL                     0x00000000u   /*!< No Pull-up or Pull-down activation  */
-#define GPIO_PULLUP                     0x00000001u   /*!< Pull-up activation                  */
-#define GPIO_PULLDOWN                   0x00000002u   /*!< Pull-down activation                */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Check whether the specified EXTI line flag is set or not.
-  * @param __EXTI_LINE__ specifies the EXTI line flag to check.
-  *         This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__)       (EXTI->PR1 & (__EXTI_LINE__))
-
-/**
-  * @brief  Clear the EXTI's line pending flags.
-  * @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
-  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__)     (EXTI->PR1 = (__EXTI_LINE__))
-
-/**
-  * @brief  Check whether the specified EXTI line is asserted or not.
-  * @param __EXTI_LINE__ specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)         (EXTI->PR1 & (__EXTI_LINE__))
-
-/**
-  * @brief  Clear the EXTI's line pending bits.
-  * @param __EXTI_LINE__ specifies the EXTI lines to clear.
-  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)       (EXTI->PR1 = (__EXTI_LINE__))
-
-/**
-  * @brief  Generate a Software interrupt on selected EXTI line.
-  * @param __EXTI_LINE__ specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__)  (EXTI->SWIER1 |= (__EXTI_LINE__))
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Constants GPIO Private Constants
-  * @{
-  */
-#define GPIO_MODE_Pos                           0u
-#define GPIO_MODE                               (0x3uL << GPIO_MODE_Pos)
-#define MODE_INPUT                              (0x0uL << GPIO_MODE_Pos)
-#define MODE_OUTPUT                             (0x1uL << GPIO_MODE_Pos)
-#define MODE_AF                                 (0x2uL << GPIO_MODE_Pos)
-#define MODE_ANALOG                             (0x3uL << GPIO_MODE_Pos)
-#define OUTPUT_TYPE_Pos                         4u
-#define OUTPUT_TYPE                             (0x1uL << OUTPUT_TYPE_Pos)
-#define OUTPUT_PP                               (0x0uL << OUTPUT_TYPE_Pos)
-#define OUTPUT_OD                               (0x1uL << OUTPUT_TYPE_Pos)
-#define EXTI_MODE_Pos                           16u
-#define EXTI_MODE                               (0x3uL << EXTI_MODE_Pos)
-#define EXTI_IT                                 (0x1uL << EXTI_MODE_Pos)
-#define EXTI_EVT                                (0x2uL << EXTI_MODE_Pos)
-#define TRIGGER_MODE_Pos                         20u
-#define TRIGGER_MODE                            (0x7uL << TRIGGER_MODE_Pos)
-#define TRIGGER_RISING                          (0x1uL << TRIGGER_MODE_Pos)
-#define TRIGGER_FALLING                         (0x2uL << TRIGGER_MODE_Pos)
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Private_Macros GPIO Private Macros
-  * @{
-  */
-#define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-
-#define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
-                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
-
-#define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\
-                                     ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
-                                     ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
-                                     ((__MODE__) == GPIO_MODE_AF_PP)              ||\
-                                     ((__MODE__) == GPIO_MODE_AF_OD)              ||\
-                                     ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
-                                     ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
-                                     ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
-                                     ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
-                                     ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
-                                     ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
-                                     ((__MODE__) == GPIO_MODE_ANALOG))
-
-#define IS_GPIO_SPEED(__SPEED__)    (((__SPEED__) == GPIO_SPEED_FREQ_LOW)       ||\
-                                     ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM)    ||\
-                                     ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)      ||\
-                                     ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
-
-#define IS_GPIO_PULL(__PULL__)      (((__PULL__) == GPIO_NOPULL)   ||\
-                                     ((__PULL__) == GPIO_PULLUP)   || \
-                                     ((__PULL__) == GPIO_PULLDOWN))
-/**
-  * @}
-  */
-
-/* Include GPIO HAL Extended module */
-#include "stm32wlxx_hal_gpio_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
-  *  @brief    GPIO Exported Functions
-  * @{
-  */
-
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions *****************************/
-void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
-  *  @brief    IO operation functions
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void              HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void              HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
-void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h

@@ -1,184 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_gpio_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of GPIO HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_GPIO_EX_H
-#define STM32WLxx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIOEx GPIOEx
-  * @brief GPIO Extended HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
-  * @{
-  */
-
-/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
-  * @{
-  */
-
-/**
-  * @brief   AF 0 selection
-  */
-#define GPIO_AF0_MCO                        ((uint8_t)0x00)  /*!< MCO Alternate Function mapping       */
-#define GPIO_AF0_LSCO                       ((uint8_t)0x00)  /*!< LSCO Alternate Function mapping      */
-#define GPIO_AF0_JTAG                       ((uint8_t)0x00)  /*!< JTAG Alternate Function mapping      */
-#define GPIO_AF0_SWD                        ((uint8_t)0x00)  /*!< SWD Alternate Function mapping       */
-#define GPIO_AF0_RTC                        ((uint8_t)0x00)  /*!< RCT_OUT Alternate Function mapping   */
-
-/**
-  * @brief   AF 1 selection
- */
-#define GPIO_AF1_LPTIM1                     ((uint8_t)0x01)  /*!< LPTIM3 Alternate Function mapping    */
-#define GPIO_AF1_TIM1                       ((uint8_t)0x01)  /*!< TIM1 Alternate Function mapping      */
-#define GPIO_AF1_TIM2                       ((uint8_t)0x01)  /*!< TIM2 Alternate Function mapping      */
-
-/**
-  * @brief   AF 2 selection
-  */
-#define GPIO_AF2_TIM2                       ((uint8_t)0x02)  /*!< TIM2 Alternate Function mapping      */
-#define GPIO_AF2_TIM1                       ((uint8_t)0x02)  /*!< TIM1 Alternate Function mapping      */
-
-/**
-  * @brief   AF 3 selection
-  */
-#define GPIO_AF3_SPI2                       ((uint8_t)0x03)  /*!< SPI2 Alternate Function mapping      */
-#define GPIO_AF3_LPTIM3                     ((uint8_t)0x03)  /*!< LPTIM3 Alternate Function mapping    */
-#define GPIO_AF3_TIM1                       ((uint8_t)0x03)  /*!< TIM1 Alternate Function mapping      */
-
-/**
-  * @brief   AF 4 selection
-  */
-#define GPIO_AF4_I2C1                       ((uint8_t)0x04)  /*!< I2C1 Alternate Function mapping      */
-#define GPIO_AF4_I2C2                       ((uint8_t)0x04)  /*!< I2C1 Alternate Function mapping      */
-#define GPIO_AF4_I2C3                       ((uint8_t)0x04)  /*!< I2C3 Alternate Function mapping      */
-
-/**
-  * @brief   AF 5 selection
-  */
-#define GPIO_AF5_SPI1                       ((uint8_t)0x05)  /*!< SPI1 Alternate Function mapping      */
-#define GPIO_AF5_SPI2                       ((uint8_t)0x05)  /*!< SPI2 Alternate Function mapping      */
-
-/**
-  * @brief   AF 6 selection
-  */
-#define GPIO_AF6_RF_BUSY                    ((uint8_t)0x06)  /*!< RF_BUSY Alternate Function mapping   */
-
-/**
-  * @brief  AF 7 selection
-  */
-#define GPIO_AF7_USART1                     ((uint8_t)0x07) /*!< USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2                     ((uint8_t)0x07) /*!< USART1 Alternate Function mapping     */
-
-/**
-  * @brief  AF 8 selection
-  */
-#define GPIO_AF8_LPUART1                    ((uint8_t)0x08) /*!< LPUART1 Alternate Function mapping    */
-#define GPIO_AF8_IR                         ((uint8_t)0x08) /*!< IR Alternate Function mapping         */
-
-/**
-  * @brief  AF 12 selection
-  */
-#define GPIO_AF12_COMP1                     ((uint8_t)0x0C)  /*!< COMP1 Alternate Function mapping     */
-#define GPIO_AF12_COMP2                     ((uint8_t)0x0C)  /*!< COMP2 Alternate Function mapping     */
-#define GPIO_AF12_TIM1                      ((uint8_t)0x0C)  /*!< TIM1 Alternate Function mapping      */
-
-/**
-  * @brief  AF 13 selection
-  */
-#define GPIO_AF13_DEBUG_PWR                 ((uint8_t)0x0D) /*!< Debug PWR Alternate Function mapping       */
-#define GPIO_AF13_DEBUG_RF                  ((uint8_t)0x0D) /*!< Debug RF Alternate Function mapping        */
-#define GPIO_AF13_DEBUG_SUBGHZSPI           ((uint8_t)0x0D) /*!< Debug SUBGHZSPI Alternate Function mapping */
-
-/**
-  * @brief  AF 14 selection
-  */
-#define GPIO_AF14_LPTIM2                    ((uint8_t)0x0E) /*!< LPTIM2 Alternate Function mapping     */
-#define GPIO_AF14_TIM2                      ((uint8_t)0x0E) /*!< TIM2 Alternate Function mapping       */
-#define GPIO_AF14_TIM16                     ((uint8_t)0x0E) /*!< TIM16 Alternate Function mapping      */
-#define GPIO_AF14_TIM17                     ((uint8_t)0x0E) /*!< TIM17 Alternate Function mapping      */
-
-/**
-  * @brief  AF 15 selection
-  */
-
-#define GPIO_AF15_EVENTOUT                  ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping   */
-
-#define IS_GPIO_AF(AF)                      ((AF) <= (uint8_t)0x0F)
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
-  * @{
-  */
-
-/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
-  * @{
-  */
-
-#define GPIO_GET_INDEX(__GPIOx__)           (((__GPIOx__) == (GPIOA))? 0uL :\
-                                             ((__GPIOx__) == (GPIOB))? 1uL :\
-                                             ((__GPIOx__) == (GPIOC))? 2uL : 7uL)
-
-/**
-  * @}
- */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_GPIO_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gtzc.h

@@ -1,325 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_gtzc.h
-  * @author  MCD Application Team
-  * @brief   Header file of GTZC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_GTZC_H
-#define STM32WLxx_HAL_GTZC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-#if defined(GTZC_TZSC)
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup GTZC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup GTZC_Exported_Types GTZC Exported Types
-  * @{
-  */
-/**
-  * @brief  GTZC TZSC MPCWM structure
-  */
-typedef struct
-{
-  uint32_t AreaId; /*!< Area identifier field. It can be a value of @ref 
-                        GTZC_MPCWM_AreaId */
-  uint32_t Length; /*!< length of the unprivileged area starting from selected
-                        memory base address. It must be aligned on 2kB for Flash
-                        areas and 1kB for Sram ones. */
-} MPCWM_ConfigTypeDef;
-/**
-  * @}
-  */
-
-
-/* Private constants --------------------------------------------------------*/
-/** @defgroup GTZC_Private_Constants GTZC Private Constants
-  * @{
-  */
-/**
-  * @brief  GTZC structure definitions for IP identifier parameter (PeriphId)
-  *         used in HAL_GTZC_TZSC_ConfigPeriphAttributes and 
-  *         HAL_GTZC_TZSC_GetConfigPeriphAttributes functions and also in all
-  *        HAL_GTZC_TZIC related functions bitmap:
-  *         bits[31:28] Field "register". Define the register an IP belongs to.
-  *                     Each bit is dedicated to a single register.
-  *         bit[5]      Field "all Ips". If this bit is set then the PeriphId
-  *                     targets all Ips within register.
-  *         bits[4:0]   Field "bit position". Define the bit position within
-  *                     the register dedicated to the IP, value from 0 to 31.
-  */
-#define GTZC_PERIPH_REG_Pos                 (28U)
-#define GTZC_PERIPH_REG_Msk                 (0xFUL << GTZC_PERIPH_REG_Pos)        /*0 xF0000000 */
-#define GTZC_PERIPH_REG1                    (0x0UL << GTZC_PERIPH_REG_Pos)
-#define GTZC_PERIPH_ALLPERIPH_Pos           (5U)
-#define GTZC_PERIPH_ALLPERIPH_Msk           (0x1UL << GTZC_PERIPH_ALLPERIPH_Pos)  /* 0x00000020 */
-#define GTZC_PERIPH_BITPOS_Pos              (0U)
-#define GTZC_PERIPH_BITPOS_Msk              (0x1FUL << GTZC_PERIPH_BITPOS_Pos)    /* 0x0000001F */
-
-/**
-  * @brief GTZC TZSC MPCWM Watermark granularity depending on area
-  */
-#define GTZC_TZSC_MPCWM_GRANULARITY_FLASH_OFFSET  11U
-#define GTZC_TZSC_MPCWM_GRANULARITY_FLASH         (1UL << GTZC_TZSC_MPCWM_GRANULARITY_FLASH_OFFSET)  /* 2 kB */
-#define GTZC_TZSC_MPCWM_GRANULARITY_SRAM1_OFFSET  10U
-#define GTZC_TZSC_MPCWM_GRANULARITY_SRAM1         (1UL << GTZC_TZSC_MPCWM_GRANULARITY_SRAM1_OFFSET)  /* 1 kB */
-#define GTZC_TZSC_MPCWM_GRANULARITY_SRAM2_OFFSET  10U
-#define GTZC_TZSC_MPCWM_GRANULARITY_SRAM2         (1UL << GTZC_TZSC_MPCWM_GRANULARITY_SRAM2_OFFSET)  /* 1 kB */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup GTZC_Exported_Constants GTZC Exported Constants
-  * @{
-  */
-
-/** @defgroup GTZC_TZSC_Peripheral_Attribute GTZC TZSC Peripheral Attribute
-  *           bitmap: bit0 : Sec Attr (0 = Ns, 1 = Sec)
-  *                   bit1 : PrivAttr (0 = NonPriv, 1 = Priv)
-  * @{
-  */
-#define GTZC_TZSC_ATTRIBUTE_NSEC            0x00U
-#define GTZC_TZSC_ATTRIBUTE_SEC             0x01U
-#define GTZC_TZSC_ATTRIBUTE_NPRIV           0x00U
-#define GTZC_TZSC_ATTRIBUTE_PRIV            0x02U
-/**
-  * @}
-  */
-
-/** @defgroup GTZC_Peripheral_Identification GTZC Peripheral Identification
-  *           user-oriented definition for each IP identifier parameter (PeriphId)
-  *           used in HAL_GTZC_TZSC_ConfigPeriphAttributes and HAL_GTZC_TZSC_GetConfigPeriphAttributes
-  *           functions and also in all HAL_GTZC_TZIC relative functions.
-  * @note     user can also select all IPs using specific define
-  * @note     that two maximum values are also defined here:
-  *           - max number of securable AHB/APB peripherals or masters (used in
-  *           TZSC sub-block)
-  *           - max number of securable and security-aware AHB/APB peripherals
-  *           or masters (used in TZIC sub-block)
-  * @{
-  */
-#define GTZC_PERIPH_TZIC                    (GTZC_PERIPH_REG1 | GTZC_CFGR1_TZIC_Pos)
-#define GTZC_PERIPH_TZSC                    (GTZC_PERIPH_REG1 | GTZC_CFGR1_TZSC_Pos)
-#define GTZC_PERIPH_AES                     (GTZC_PERIPH_REG1 | GTZC_CFGR1_AES_Pos)
-#define GTZC_PERIPH_RNG                     (GTZC_PERIPH_REG1 | GTZC_CFGR1_RNG_Pos)
-#define GTZC_PERIPH_SUBGHZSPI               (GTZC_PERIPH_REG1 | GTZC_CFGR1_SUBGHZSPI_Pos)
-#define GTZC_PERIPH_PWR                     (GTZC_PERIPH_REG1 | GTZC_CFGR1_PWR_Pos)
-#define GTZC_PERIPH_FLASHIF                 (GTZC_PERIPH_REG1 | GTZC_CFGR1_FLASHIF_Pos)
-#define GTZC_PERIPH_DMA1                    (GTZC_PERIPH_REG1 | GTZC_CFGR1_DMA1_Pos)
-#define GTZC_PERIPH_DMA2                    (GTZC_PERIPH_REG1 | GTZC_CFGR1_DMA2_Pos)
-#define GTZC_PERIPH_DMAMUX                  (GTZC_PERIPH_REG1 | GTZC_CFGR1_DMAMUX_Pos)
-#define GTZC_PERIPH_FLASH                   (GTZC_PERIPH_REG1 | GTZC_CFGR1_FLASH_Pos)
-#define GTZC_PERIPH_SRAM1                   (GTZC_PERIPH_REG1 | GTZC_CFGR1_SRAM1_Pos)
-#define GTZC_PERIPH_SRAM2                   (GTZC_PERIPH_REG1 | GTZC_CFGR1_SRAM2_Pos)
-#define GTZC_PERIPH_PKA                     (GTZC_PERIPH_REG1 | GTZC_CFGR1_PKA_Pos)
-#define GTZC_PERIPH_TZIC_MAX                GTZC_PERIPH_PKA
-#define GTZC_PERIPH_ALL                     GTZC_PERIPH_ALLPERIPH_Msk
-
-
-/* Note that two maximum values are also defined here:
- * - max number of securable peripherals
- *   (used in TZSC sub-block)
- * - max number of securable and security-aware peripherals or masters
- *   (used in TZIC sub-block)
- */
-#define GTZC_TZSC_PERIPH_NUMBER             4U
-#define GTZC_TZIC_PERIPH_NUMBER             (GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_PKA + 1U))
-
-/**
-  * @}
-  */
-
-/** @defgroup GTZC_TZSC_Lock  GTZC TZSC Lock
-  * @{
-  */
-#define GTZC_TZSC_LOCK_OFF                  (0U)
-#define GTZC_TZSC_LOCK_ON                   (1U)
-/**
-  * @}
-  */
-
-/** @defgroup GTZC_MPCWM_AreaId GTZC MPCWM area identifier values
-  * @{
-  */
-#define GTZC_TZSC_MPCWM_AREAID_UNPRIV              (0U)
-#define GTZC_TZSC_MPCWM_AREAID_UNPRIV_WRITABLE     (1U)
-/**
-  * @}
-  */
-
-
-/** @defgroup GTZC_TZIC_ILA_Pending GTZC TZIC ILA Pending
-  * @{
-  */
-#define GTZC_TZIC_NO_ILA_EVENT              (0U)
-#define GTZC_TZIC_ILA_EVENT_PENDING         (1U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GTZC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup GTZC_Exported_Functions_Group1
-  * @{
-  */
-/* TZSC Initialization and Configuration functions ****************************/
-HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, uint32_t PeriphAttributes);
-HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, uint32_t *PeriphAttributes);
-/**
-  * @}
-  */
-
-/** @addtogroup GTZC_Exported_Functions_Group2
-  * @{
-  */
-/* MPCWM Initialization and Configuration functions ***************************/
-HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc);
-HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc);
-/**
-  * @}
-  */
-
-/** @addtogroup GTZC_Exported_Functions_Group3
-  * @{
-  */
-/* TZSC and TZSC-MPCWM Lock functions *****************************************/
-uint32_t          HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSCx);
-#if defined(CORE_CM0PLUS)
-void              HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSCx);
-/**
-  * @}
-  */
-
-/** @addtogroup GTZC_Exported_Functions_Group4
-  * @{
-  */
-/* TZIC Initialization and Configuration functions ****************************/
-HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId);
-HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId);
-HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *Flag);
-HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId);
-/**
-  * @}
-  */
-
-/** @addtogroup GTZC_Exported_Functions_Group5
-  * @{
-  */
-void              HAL_GTZC_IRQHandler(void);
-void              HAL_GTZC_TZIC_Callback(uint32_t PeriphId);
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Private macro ------------------------------------------------------------*/
-/** @defgroup GTZC_Private_Macros GTZC Private Macros
-  * @{
-  */
-/**
-  * @brief  GTZC private macros usable to retrieve information to access register
-  *         for a specific PeriphId
-  */
-#define GTZC_GET_REG_INDEX(__PERIPHERAL__)    (((__PERIPHERAL__) & GTZC_PERIPH_REG_Msk) >> GTZC_PERIPH_REG_Pos)
-#define GTZC_GET_PERIPH_POS(__PERIPHERAL__)   ((__PERIPHERAL__) & GTZC_PERIPH_BITPOS_Msk)
-
-/**
-  * @brief  GTZC private macro to get array index of a specific PeriphId
-  *         in case of GTZC_PERIPH_ALL usage in the two following functions:
-  *         HAL_GTZC_TZSC_ConfigPeriphAttributes and HAL_GTZC_TZSC_GetConfigPeriphAttributes
-  */
-#define GTZC_GET_ARRAY_INDEX(__PERIPHERAL__)  ((GTZC_GET_REG_INDEX(__PERIPHERAL__) * 32U) + GTZC_GET_PERIPH_POS(__PERIPHERAL__))
-
-
-/**
-  * @brief  GTZC private macros to check function input parameters
-  */
-#define IS_GTZC_ATTRIBUTE(__ATTRIBUTES__)   (((__ATTRIBUTES__) & ~(GTZC_TZSC_ATTRIBUTE_SEC | GTZC_TZSC_ATTRIBUTE_PRIV)) == 0x00u)
-
-#define IS_GTZC_TZSC_PERIPHERAL(__PERIPHERAL__)  (((__PERIPHERAL__) == GTZC_PERIPH_AES) || ((__PERIPHERAL__) == GTZC_PERIPH_RNG) || \
-                                                  ((__PERIPHERAL__) == GTZC_PERIPH_SUBGHZSPI) || ((__PERIPHERAL__) == GTZC_PERIPH_PKA) ||\
-                                                  ((__PERIPHERAL__) == GTZC_PERIPH_ALL))
-
-#define IS_GTZC_TZIC_PERIPHERAL(__PERIPHERAL__)  (((((__PERIPHERAL__) & ~(GTZC_PERIPH_REG_Pos | GTZC_PERIPH_BITPOS_Msk)) == 0x00u) && \
-                                                  ((GTZC_GET_ARRAY_INDEX(__PERIPHERAL__) <= GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_TZIC_MAX)))) || \
-                                                  ((__PERIPHERAL__) == GTZC_PERIPH_ALLPERIPH_Msk))
-
-#define IS_GTZC_MPCWM_MEMORY_BASEADDRESS(__BASE_ADDRESS__)   (((__BASE_ADDRESS__) == FLASH_BASE) || \
-                                                              ((__BASE_ADDRESS__) == SRAM1_BASE) || \
-                                                              ((__BASE_ADDRESS__) == SRAM2_BASE))
-
-#define IS_GTZC_MPCWM_FLASH_AREAID(__AREAID__)  (((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV) || \
-                                                 ((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV_WRITABLE))
-
-#define IS_GTZC_MPCWM_SRAM1_AREAID(__AREAID__)  ((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV)
-
-#define IS_GTZC_MPCWM_SRAM2_AREAID(__AREAID__)  ((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV)
-
-#define IS_GTZC_MPCWM_FLASH_LENGTH(__LENGTH__)  ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_FLASH) == 0x00u) && \
-                                                  ((__LENGTH__) <= FLASH_SIZE))
-
-#define IS_GTZC_MPCWM_SRAM1_LENGTH(__LENGTH__)  ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_SRAM1) == 0x00u) && \
-                                                  ((__LENGTH__) <= SRAM1_SIZE))
-
-#define IS_GTZC_MPCWM_SRAM2_LENGTH(__LENGTH__)  ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_SRAM2) == 0x00u) && \
-                                                  ((__LENGTH__) <= SRAM2_SIZE))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* GTZC_TZSC */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_GTZC_H */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_hsem.h

@@ -1,210 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_hsem.h
-  * @author  MCD Application Team
-  * @brief   Header file of HSEM HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_HSEM_H
-#define STM32WLxx_HAL_HSEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-   * @{
-   */
-
-/** @addtogroup HSEM
-   * @{
-   */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup HSEM_Exported_Macros HSEM Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  SemID to mask helper Macro.
-  * @param  __SEMID__: semaphore ID from 0 to 15
-  * @retval Semaphore Mask.
-  */
-#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
-
-/**
-  * @brief  Enables the specified HSEM interrupts.
-  * @param  __SEM_MASK__: semaphores Mask
-  * @retval None.
-  */
-#if defined(DUAL_CORE)
-#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
-                                            (HSEM->C1IER |= (__SEM_MASK__)) : \
-                                            (HSEM->C2IER |= (__SEM_MASK__)))
-#else
-#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
-#endif /* DUAL_CORE */
-/**
-  * @brief  Disables the specified HSEM interrupts.
-  * @param  __SEM_MASK__: semaphores Mask
-  * @retval None.
-  */
-#if defined(DUAL_CORE)
-#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
-                                             (HSEM->C1IER &= ~(__SEM_MASK__)) :       \
-                                             (HSEM->C2IER &= ~(__SEM_MASK__)))
-#else
-#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
-#endif /* DUAL_CORE */
-
-/**
-  * @brief  Checks whether interrupt has occurred or not for semaphores specified by a mask.
-  * @param  __SEM_MASK__: semaphores Mask
-  * @retval semaphores Mask : Semaphores where an interrupt occurred.
-  */
-#if defined(DUAL_CORE)
-#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
-                                         ((__SEM_MASK__) & HSEM->C1MISR) :        \
-                                         ((__SEM_MASK__) & HSEM->C2MISR1))
-#else
-#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
-#endif /* DUAL_CORE */
-
-/**
-  * @brief  Get the semaphores release status flags.
-  * @param  __SEM_MASK__: semaphores Mask
-  * @retval semaphores Mask : Semaphores where Release flags rise.
-  */
-#if defined(DUAL_CORE)
-#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
-                                           (__SEM_MASK__) & HSEM->C1ISR :           \
-                                           (__SEM_MASK__) & HSEM->C2ISR)
-#else
-#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
-#endif /* DUAL_CORE */
-
-/**
-  * @brief  Clears the HSEM Interrupt flags.
-  * @param  __SEM_MASK__: semaphores Mask
-  * @retval None.
-  */
-#if defined(DUAL_CORE)
-#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \
-                                             (HSEM->C1ICR |= (__SEM_MASK__)) :        \
-                                             (HSEM->C2ICR |= (__SEM_MASK__)))
-#else
-#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
-#endif /* DUAL_CORE */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
-  * @{
-  */
-
-/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
-  * @brief    HSEM Take and Release functions
-  * @{
-  */
-
-/* HSEM semaphore take (lock) using 2-Step  method ****************************/
-HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
-/* HSEM semaphore fast take (lock) using 1-Step  method ***********************/
-HAL_StatusTypeDef  HAL_HSEM_FastTake(uint32_t SemID);
-/* HSEM Check semaphore state Taken or not   **********************************/
-uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
-/* HSEM Release  **************************************************************/
-void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
-/* HSEM Release All************************************************************/
-void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);
-
-/**
-  * @}
-  */
-
-/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
-  * @brief    HSEM Set and Get Key functions.
-  * @{
-  */
-/* HSEM Set Clear Key *********************************************************/
-void  HAL_HSEM_SetClearKey(uint32_t Key);
-/* HSEM Get Clear Key *********************************************************/
-uint32_t HAL_HSEM_GetClearKey(void);
-/**
-  * @}
-  */
-
-/** @addtogroup HSEM_Exported_Functions_Group3
-  * @brief   HSEM Notification functions
-  * @{
-  */
-/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
-void HAL_HSEM_ActivateNotification(uint32_t SemMask);
-/* HSEM Deactivate HSEM Notification (When a semaphore is released)  ****************/
-void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
-/* HSEM Free Callback (When a semaphore is released)  *******************************/
-void HAL_HSEM_FreeCallback(uint32_t SemMask);
-/* HSEM IRQ Handler  **********************************************************/
-void HAL_HSEM_IRQHandler(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup HSEM_Private_Macros HSEM Private Macros
-  * @{
-  */
-
-#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
-
-#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
-
-#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
-
-#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \
-                                    ((__COREID__) == HSEM_CPU2_COREID))
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_HSEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2c.h

@@ -1,838 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_i2c.h
-  * @author  MCD Application Team
-  * @brief   Header file of I2C HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_I2C_H
-#define STM32WLxx_HAL_I2C_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2C
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Types I2C Exported Types
-  * @{
-  */
-
-/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
-  * @brief  I2C Configuration Structure definition
-  * @{
-  */
-typedef struct
-{
-  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
-                                     This parameter calculated by referring to I2C initialization section
-                                     in Reference manual */
-
-  uint32_t OwnAddress1;         /*!< Specifies the first device own address.
-                                     This parameter can be a 7-bit or 10-bit address. */
-
-  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
-                                     This parameter can be a value of @ref I2C_ADDRESSING_MODE */
-
-  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
-                                     This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
-
-  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
-                                     This parameter can be a 7-bit address. */
-
-  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing
-                                     mode is selected.
-                                     This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
-
-  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
-                                     This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
-
-  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
-                                     This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
-
-} I2C_InitTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_state_structure_definition HAL state structure definition
-  * @brief  HAL State structure definition
-  * @note  HAL I2C State value coding follow below described bitmap :\n
-  *          b7-b6  Error information\n
-  *             00 : No Error\n
-  *             01 : Abort (Abort user request on going)\n
-  *             10 : Timeout\n
-  *             11 : Error\n
-  *          b5     Peripheral initialization status\n
-  *             0  : Reset (peripheral not initialized)\n
-  *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
-  *          b4     (not used)\n
-  *             x  : Should be set to 0\n
-  *          b3\n
-  *             0  : Ready or Busy (No Listen mode ongoing)\n
-  *             1  : Listen (peripheral in Address Listen Mode)\n
-  *          b2     Intrinsic process state\n
-  *             0  : Ready\n
-  *             1  : Busy (peripheral busy with some configuration or internal operations)\n
-  *          b1     Rx state\n
-  *             0  : Ready (no Rx operation ongoing)\n
-  *             1  : Busy (Rx operation ongoing)\n
-  *          b0     Tx state\n
-  *             0  : Ready (no Tx operation ongoing)\n
-  *             1  : Busy (Tx operation ongoing)
-  * @{
-  */
-typedef enum
-{
-  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */
-  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */
-  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */
-  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */
-  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */
-  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */
-  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission
-                                                 process is ongoing                         */
-  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception
-                                                 process is ongoing                         */
-  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */
-  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */
-  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */
-
-} HAL_I2C_StateTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_mode_structure_definition HAL mode structure definition
-  * @brief  HAL Mode structure definition
-  * @note  HAL I2C Mode value coding follow below described bitmap :\n
-  *          b7     (not used)\n
-  *             x  : Should be set to 0\n
-  *          b6\n
-  *             0  : None\n
-  *             1  : Memory (HAL I2C communication is in Memory Mode)\n
-  *          b5\n
-  *             0  : None\n
-  *             1  : Slave (HAL I2C communication is in Slave Mode)\n
-  *          b4\n
-  *             0  : None\n
-  *             1  : Master (HAL I2C communication is in Master Mode)\n
-  *          b3-b2-b1-b0  (not used)\n
-  *             xxxx : Should be set to 0000
-  * @{
-  */
-typedef enum
-{
-  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */
-  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */
-  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */
-  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */
-
-} HAL_I2C_ModeTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Error_Code_definition I2C Error Code definition
-  * @brief  I2C Error Code definition
-  * @{
-  */
-#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */
-#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */
-#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */
-#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */
-#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */
-#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */
-#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
-#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */
-#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-#define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */
-/**
-  * @}
-  */
-
-/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
-  * @brief  I2C handle Structure definition
-  * @{
-  */
-typedef struct __I2C_HandleTypeDef
-{
-  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */
-
-  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */
-
-  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */
-
-  uint16_t                   XferSize;       /*!< I2C transfer size                         */
-
-  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */
-
-  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can
-                                                  be a value of @ref I2C_XFEROPTIONS */
-
-  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */
-
-  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
-  /*!< I2C transfer IRQ handler function pointer */
-
-  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */
-
-  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */
-
-  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */
-
-  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */
-
-  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */
-
-  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */
-
-  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Master Tx Transfer completed callback */
-  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Master Rx Transfer completed callback */
-  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Slave Tx Transfer completed callback  */
-  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Slave Rx Transfer completed callback  */
-  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Listen Complete callback              */
-  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Memory Tx Transfer completed callback */
-  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Memory Rx Transfer completed callback */
-  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Error callback                        */
-  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Abort callback                        */
-
-  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
-  /*!< I2C Slave Address Match callback */
-
-  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Msp Init callback                     */
-  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
-  /*!< I2C Msp DeInit callback                   */
-
-#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */
-} I2C_HandleTypeDef;
-
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL I2C Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */
-  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */
-  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */
-  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */
-  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */
-  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */
-  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */
-  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */
-  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */
-
-  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */
-  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */
-
-} HAL_I2C_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL I2C Callback pointer definition
-  */
-typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
-/*!< pointer to an I2C callback function */
-typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
-                                          uint16_t AddrMatchCode);
-/*!< pointer to an I2C Address Match callback function */
-
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
-  * @{
-  */
-
-/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options
-  * @{
-  */
-#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
-#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
-#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
-#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
-#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
-#define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)
-
-/* List of XferOptions in usage of :
- * 1- Restart condition in all use cases (direction change or not)
- */
-#define  I2C_OTHER_FRAME                (0x000000AAU)
-#define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
-  * @{
-  */
-#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)
-#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLE         (0x00000000U)
-#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
-/**
-  * @}
-  */
-
-/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
-  * @{
-  */
-#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)
-#define I2C_OA2_MASK01                  ((uint8_t)0x01U)
-#define I2C_OA2_MASK02                  ((uint8_t)0x02U)
-#define I2C_OA2_MASK03                  ((uint8_t)0x03U)
-#define I2C_OA2_MASK04                  ((uint8_t)0x04U)
-#define I2C_OA2_MASK05                  ((uint8_t)0x05U)
-#define I2C_OA2_MASK06                  ((uint8_t)0x06U)
-#define I2C_OA2_MASK07                  ((uint8_t)0x07U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
-  * @{
-  */
-#define I2C_GENERALCALL_DISABLE         (0x00000000U)
-#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
-/**
-  * @}
-  */
-
-/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
-  * @{
-  */
-#define I2C_NOSTRETCH_DISABLE           (0x00000000U)
-#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
-/**
-  * @}
-  */
-
-/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
-  * @{
-  */
-#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)
-#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
-  * @{
-  */
-#define I2C_DIRECTION_TRANSMIT          (0x00000000U)
-#define I2C_DIRECTION_RECEIVE           (0x00000001U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
-  * @{
-  */
-#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
-#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
-#define  I2C_SOFTEND_MODE               (0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
-  * @{
-  */
-#define  I2C_NO_STARTSTOP               (0x00000000U)
-#define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)
-#define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
-#define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
-  * @brief I2C Interrupt definition
-  *        Elements values convention: 0xXXXXXXXX
-  *           - XXXXXXXX  : Interrupt control mask
-  * @{
-  */
-#define I2C_IT_ERRI                     I2C_CR1_ERRIE
-#define I2C_IT_TCI                      I2C_CR1_TCIE
-#define I2C_IT_STOPI                    I2C_CR1_STOPIE
-#define I2C_IT_NACKI                    I2C_CR1_NACKIE
-#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
-#define I2C_IT_RXI                      I2C_CR1_RXIE
-#define I2C_IT_TXI                      I2C_CR1_TXIE
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Flag_definition I2C Flag definition
-  * @{
-  */
-#define I2C_FLAG_TXE                    I2C_ISR_TXE
-#define I2C_FLAG_TXIS                   I2C_ISR_TXIS
-#define I2C_FLAG_RXNE                   I2C_ISR_RXNE
-#define I2C_FLAG_ADDR                   I2C_ISR_ADDR
-#define I2C_FLAG_AF                     I2C_ISR_NACKF
-#define I2C_FLAG_STOPF                  I2C_ISR_STOPF
-#define I2C_FLAG_TC                     I2C_ISR_TC
-#define I2C_FLAG_TCR                    I2C_ISR_TCR
-#define I2C_FLAG_BERR                   I2C_ISR_BERR
-#define I2C_FLAG_ARLO                   I2C_ISR_ARLO
-#define I2C_FLAG_OVR                    I2C_ISR_OVR
-#define I2C_FLAG_PECERR                 I2C_ISR_PECERR
-#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
-#define I2C_FLAG_ALERT                  I2C_ISR_ALERT
-#define I2C_FLAG_BUSY                   I2C_ISR_BUSY
-#define I2C_FLAG_DIR                    I2C_ISR_DIR
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Macros I2C Exported Macros
-  * @{
-  */
-
-/** @brief Reset I2C handle state.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                             \
-                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;  \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;       \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;     \
-                                                                  } while(0)
-#else
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-
-/** @brief  Enable the specified I2C interrupt.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable.
-  *        This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable
-  *
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
-
-/** @brief  Disable the specified I2C interrupt.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to disable.
-  *        This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable
-  *
-  * @retval None
-  */
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
-
-/** @brief  Check whether the specified I2C interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
-  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
-  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
-  *            @arg @ref I2C_IT_RXI   RX interrupt enable
-  *            @arg @ref I2C_IT_TXI   TX interrupt enable
-  *
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & \
-                                                                   (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified I2C flag is set or not.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
-  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
-  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
-  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
-  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
-  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
-  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
-  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
-  *            @arg @ref I2C_FLAG_BERR    Bus error
-  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
-  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
-  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
-  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
-  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
-  *            @arg @ref I2C_FLAG_BUSY    Bus busy
-  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
-  *
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define I2C_FLAG_MASK  (0x0001FFFFU)
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
-                                                    (__FLAG__)) == (__FLAG__)) ? SET : RESET)
-
-/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
-  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
-  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
-  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
-  *            @arg @ref I2C_FLAG_BERR    Bus error
-  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
-  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
-  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
-  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
-  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
-  *
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
-                                                    ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
-                                                    ((__HANDLE__)->Instance->ICR = (__FLAG__)))
-
-/** @brief  Enable the specified I2C peripheral.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE(__HANDLE__)                         (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief  Disable the specified I2C peripheral.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_DISABLE(__HANDLE__)                        (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
-  * @param  __HANDLE__ specifies the I2C Handle.
-  * @retval None
-  */
-#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
-/**
-  * @}
-  */
-
-/* Include I2C HAL Extended module */
-#include "stm32wlxx_hal_i2c_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-/* Initialization and de-initialization functions******************************/
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
-                                           pI2C_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
-#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-/* IO operation functions  ****************************************************/
-/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                          uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                         uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                         uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                        uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                    uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                   uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
-                                        uint32_t Timeout);
-
-/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                             uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                            uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                      uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                                 uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                                uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                                uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                               uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
-
-/******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                              uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                             uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                        uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
-                                       uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                                  uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
-                                                 uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                                 uint32_t XferOptions);
-HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
-                                                uint32_t XferOptions);
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
-  * @{
-  */
-/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-
-/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
-  * @{
-  */
-/* Peripheral State, Mode and Error functions  *********************************/
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
-uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Macro I2C Private Macros
-  * @{
-  */
-
-#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
-                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))
-
-#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
-                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
-
-#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
-                                         ((MASK) == I2C_OA2_MASK01) || \
-                                         ((MASK) == I2C_OA2_MASK02) || \
-                                         ((MASK) == I2C_OA2_MASK03) || \
-                                         ((MASK) == I2C_OA2_MASK04) || \
-                                         ((MASK) == I2C_OA2_MASK05) || \
-                                         ((MASK) == I2C_OA2_MASK06) || \
-                                         ((MASK) == I2C_OA2_MASK07))
-
-#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
-                                         ((CALL) == I2C_GENERALCALL_ENABLE))
-
-#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
-                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))
-
-#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
-                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-
-#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
-                                         ((MODE) == I2C_AUTOEND_MODE) || \
-                                         ((MODE) == I2C_SOFTEND_MODE))
-
-#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
-                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
-                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
-                                         ((REQUEST) == I2C_NO_STARTSTOP))
-
-#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
-                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
-                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
-                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
-                                                   ((REQUEST) == I2C_LAST_FRAME)           || \
-                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \
-                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
-
-#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \
-                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
-
-#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= \
-                                                   (uint32_t)~((uint32_t)(I2C_CR2_SADD   | I2C_CR2_HEAD10R | \
-                                                                          I2C_CR2_NBYTES | I2C_CR2_RELOAD  | \
-                                                                          I2C_CR2_RD_WRN)))
-
-#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
-                                                              >> 16U))
-#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
-                                                             >> 16U))
-#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
-#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)
-
-#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
-                                                                         (uint16_t)(0xFF00U))) >> 8U)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
-
-#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
-                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
-                                                                 (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
-                                                                (~I2C_CR2_RD_WRN)) : \
-                                                     (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
-                                                                 (I2C_CR2_ADD10) | (I2C_CR2_START)) & \
-                                                                (~I2C_CR2_RD_WRN)))
-
-#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
-                                                    ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
-#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
-/**
-  * @}
-  */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-/* Private functions are defined in stm32wlxx_hal_i2c.c file */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32WLxx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2c_ex.h

@@ -1,170 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_i2c_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of I2C HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_I2C_EX_H
-#define STM32WLxx_HAL_I2C_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2CEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
-  * @{
-  */
-#define I2C_ANALOGFILTER_ENABLE         0x00000000U
-#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
-/**
-  * @}
-  */
-
-/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
-  * @{
-  */
-#define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
-#define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
-#define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
-#define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
-#define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
-#define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
-#define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
-  * @{
-  */
-
-/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
-HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
-/**
-  * @}
-  */
-
-/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-
-/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
-  * @{
-  */
-void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
-void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
-  * @{
-  */
-#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
-                                         ((FILTER) == I2C_ANALOGFILTER_DISABLE))
-
-#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)
-
-#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6))  == I2C_FASTMODEPLUS_PB6)     || \
-                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7))  == I2C_FASTMODEPLUS_PB7)     || \
-                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8))  == I2C_FASTMODEPLUS_PB8)     || \
-                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9))  == I2C_FASTMODEPLUS_PB9)     || \
-                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)    || \
-                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)    || \
-                                         (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
-/**
-  * @}
-  */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
-  * @{
-  */
-/* Private functions are defined in stm32wlxx_hal_i2c_ex.c file */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_I2C_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2s.h

@@ -1,554 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_i2s.h
-  * @author  MCD Application Team
-  * @brief   Header file of I2S HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_I2S_H
-#define STM32WLxx_HAL_I2S_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2S
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Types I2S Exported Types
-  * @{
-  */
-
-/**
-  * @brief I2S Init structure definition
-  */
-typedef struct
-{
-  uint32_t Mode;                /*!< Specifies the I2S operating mode.
-                                     This parameter can be a value of @ref I2S_Mode */
-
-  uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Standard */
-
-  uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Data_Format */
-
-  uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.
-                                     This parameter can be a value of @ref I2S_MCLK_Output */
-
-  uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.
-                                     This parameter can be a value of @ref I2S_Audio_Frequency */
-
-  uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.
-                                     This parameter can be a value of @ref I2S_Clock_Polarity */
-} I2S_InitTypeDef;
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_I2S_STATE_RESET      = 0x00U,  /*!< I2S not yet initialized or disabled                */
-  HAL_I2S_STATE_READY      = 0x01U,  /*!< I2S initialized and ready for use                  */
-  HAL_I2S_STATE_BUSY       = 0x02U,  /*!< I2S internal process is ongoing                    */
-  HAL_I2S_STATE_BUSY_TX    = 0x03U,  /*!< Data Transmission process is ongoing               */
-  HAL_I2S_STATE_BUSY_RX    = 0x04U,  /*!< Data Reception process is ongoing                  */
-  HAL_I2S_STATE_TIMEOUT    = 0x06U,  /*!< I2S timeout state                                  */
-  HAL_I2S_STATE_ERROR      = 0x07U   /*!< I2S error state                                    */
-} HAL_I2S_StateTypeDef;
-
-/**
-  * @brief I2S handle Structure definition
-  */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
-typedef struct __I2S_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-{
-  SPI_TypeDef                *Instance;    /*!< I2S registers base address */
-
-  I2S_InitTypeDef            Init;         /*!< I2S communication parameters */
-
-  uint16_t                   *pTxBuffPtr;  /*!< Pointer to I2S Tx transfer buffer */
-
-  __IO uint16_t              TxXferSize;   /*!< I2S Tx transfer size */
-
-  __IO uint16_t              TxXferCount;  /*!< I2S Tx transfer Counter */
-
-  uint16_t                   *pRxBuffPtr;  /*!< Pointer to I2S Rx transfer buffer */
-
-  __IO uint16_t              RxXferSize;   /*!< I2S Rx transfer size */
-
-  __IO uint16_t              RxXferCount;  /*!< I2S Rx transfer counter
-                                              (This field is initialized at the
-                                               same value as transfer size at the
-                                               beginning of the transfer and
-                                               decremented when a sample is received
-                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */
-  DMA_HandleTypeDef          *hdmatx;      /*!< I2S Tx DMA handle parameters */
-
-  DMA_HandleTypeDef          *hdmarx;      /*!< I2S Rx DMA handle parameters */
-
-  __IO HAL_LockTypeDef       Lock;         /*!< I2S locking object */
-
-  __IO HAL_I2S_StateTypeDef  State;        /*!< I2S communication state */
-
-  __IO uint32_t              ErrorCode;    /*!< I2S Error code
-                                                This parameter can be a value of @ref I2S_Error */
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-  void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Tx Completed callback          */
-  void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Rx Completed callback          */
-  void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Tx Half Completed callback     */
-  void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Rx Half Completed callback     */
-  void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s);              /*!< I2S Error callback                 */
-  void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s);            /*!< I2S Msp Init callback              */
-  void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s);          /*!< I2S Msp DeInit callback            */
-
-#endif  /* USE_HAL_I2S_REGISTER_CALLBACKS */
-} I2S_HandleTypeDef;
-
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  HAL I2S Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_I2S_TX_COMPLETE_CB_ID             = 0x00U,    /*!< I2S Tx Completed callback ID         */
-  HAL_I2S_RX_COMPLETE_CB_ID             = 0x01U,    /*!< I2S Rx Completed callback ID         */
-  HAL_I2S_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< I2S Tx Half Completed callback ID    */
-  HAL_I2S_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< I2S Rx Half Completed callback ID    */
-  HAL_I2S_ERROR_CB_ID                   = 0x06U,    /*!< I2S Error callback ID                */
-  HAL_I2S_MSPINIT_CB_ID                 = 0x07U,    /*!< I2S Msp Init callback ID             */
-  HAL_I2S_MSPDEINIT_CB_ID               = 0x08U     /*!< I2S Msp DeInit callback ID           */
-
-} HAL_I2S_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL I2S Callback pointer definition
-  */
-typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
-
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Constants I2S Exported Constants
-  * @{
-  */
-/** @defgroup I2S_Error I2S Error
-  * @{
-  */
-#define HAL_I2S_ERROR_NONE               (0x00000000U)  /*!< No error                    */
-#define HAL_I2S_ERROR_TIMEOUT            (0x00000001U)  /*!< Timeout error               */
-#define HAL_I2S_ERROR_OVR                (0x00000002U)  /*!< OVR error                   */
-#define HAL_I2S_ERROR_UDR                (0x00000004U)  /*!< UDR error                   */
-#define HAL_I2S_ERROR_DMA                (0x00000008U)  /*!< DMA transfer error          */
-#define HAL_I2S_ERROR_PRESCALER          (0x00000010U)  /*!< Prescaler Calculation error */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-#define HAL_I2S_ERROR_INVALID_CALLBACK   (0x00000020U)  /*!< Invalid Callback error      */
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-#define HAL_I2S_ERROR_BUSY_LINE_RX       (0x00000040U)  /*!< Busy Rx Line error          */
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Mode I2S Mode
-  * @{
-  */
-#define I2S_MODE_SLAVE_TX                (0x00000000U)
-#define I2S_MODE_SLAVE_RX                (SPI_I2SCFGR_I2SCFG_0)
-#define I2S_MODE_MASTER_TX               (SPI_I2SCFGR_I2SCFG_1)
-#define I2S_MODE_MASTER_RX               ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Standard I2S Standard
-  * @{
-  */
-#define I2S_STANDARD_PHILIPS             (0x00000000U)
-#define I2S_STANDARD_MSB                 (SPI_I2SCFGR_I2SSTD_0)
-#define I2S_STANDARD_LSB                 (SPI_I2SCFGR_I2SSTD_1)
-#define I2S_STANDARD_PCM_SHORT           ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
-#define I2S_STANDARD_PCM_LONG            ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Data_Format I2S Data Format
-  * @{
-  */
-#define I2S_DATAFORMAT_16B               (0x00000000U)
-#define I2S_DATAFORMAT_16B_EXTENDED      (SPI_I2SCFGR_CHLEN)
-#define I2S_DATAFORMAT_24B               ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
-#define I2S_DATAFORMAT_32B               ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_MCLK_Output I2S MCLK Output
-  * @{
-  */
-#define I2S_MCLKOUTPUT_ENABLE            (SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE           (0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
-  * @{
-  */
-#define I2S_AUDIOFREQ_192K               (192000U)
-#define I2S_AUDIOFREQ_96K                (96000U)
-#define I2S_AUDIOFREQ_48K                (48000U)
-#define I2S_AUDIOFREQ_44K                (44100U)
-#define I2S_AUDIOFREQ_32K                (32000U)
-#define I2S_AUDIOFREQ_22K                (22050U)
-#define I2S_AUDIOFREQ_16K                (16000U)
-#define I2S_AUDIOFREQ_11K                (11025U)
-#define I2S_AUDIOFREQ_8K                 (8000U)
-#define I2S_AUDIOFREQ_DEFAULT            (2U)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
-  * @{
-  */
-#define I2S_CPOL_LOW                     (0x00000000U)
-#define I2S_CPOL_HIGH                    (SPI_I2SCFGR_CKPOL)
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
-  * @{
-  */
-#define I2S_IT_TXE                       SPI_CR2_TXEIE
-#define I2S_IT_RXNE                      SPI_CR2_RXNEIE
-#define I2S_IT_ERR                       SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Flags_Definition I2S Flags Definition
-  * @{
-  */
-#define I2S_FLAG_TXE                     SPI_SR_TXE
-#define I2S_FLAG_RXNE                    SPI_SR_RXNE
-
-#define I2S_FLAG_UDR                     SPI_SR_UDR
-#define I2S_FLAG_OVR                     SPI_SR_OVR
-#define I2S_FLAG_FRE                     SPI_SR_FRE
-
-#define I2S_FLAG_CHSIDE                  SPI_SR_CHSIDE
-#define I2S_FLAG_BSY                     SPI_SR_BSY
-
-#define I2S_FLAG_MASK                   (SPI_SR_RXNE\
-                                         | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup I2S_Exported_macros I2S Exported Macros
-  * @{
-  */
-
-/** @brief  Reset I2S handle state
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
-                                                                    (__HANDLE__)->State = HAL_I2S_STATE_RESET;       \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                                  } while(0)
-#else
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-
-/** @brief  Enable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief  Disable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief  Enable the specified I2S interrupts.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-
-/** @brief  Disable the specified I2S interrupts.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-
-/** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
-  * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
-                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks whether the specified I2S flag is set or not.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
-  *            @arg I2S_FLAG_UDR: Underrun flag
-  *            @arg I2S_FLAG_OVR: Overrun flag
-  *            @arg I2S_FLAG_FRE: Frame error flag
-  *            @arg I2S_FLAG_CHSIDE: Channel Side flag
-  *            @arg I2S_FLAG_BSY: Busy flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the I2S OVR pending flag.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
-                                                __IO uint32_t tmpreg_ovr = 0x00U; \
-                                                tmpreg_ovr = (__HANDLE__)->Instance->DR; \
-                                                tmpreg_ovr = (__HANDLE__)->Instance->SR; \
-                                                UNUSED(tmpreg_ovr); \
-                                              }while(0U)
-/** @brief Clears the I2S UDR pending flag.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
-                                                __IO uint32_t tmpreg_udr = 0x00U;\
-                                                tmpreg_udr = ((__HANDLE__)->Instance->SR);\
-                                                UNUSED(tmpreg_udr); \
-                                              }while(0U)
-/** @brief Flush the I2S DR Register.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__)  do{\
-                                                __IO uint32_t tmpreg_dr = 0x00U;\
-                                                tmpreg_dr = ((__HANDLE__)->Instance->DR);\
-                                                UNUSED(tmpreg_dr); \
-                                              }while(0U)
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
-                                           pI2S_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions  ***************************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
-void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control and State functions  ************************************/
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup I2S_Private_Macros I2S Private Macros
-  * @{
-  */
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __SR__  copy of I2S SR register.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
-  *            @arg I2S_FLAG_UDR: Underrun error flag
-  *            @arg I2S_FLAG_OVR: Overrun flag
-  *            @arg I2S_FLAG_CHSIDE: Channel side flag
-  *            @arg I2S_FLAG_BSY: Busy flag
-  * @retval SET or RESET.
-  */
-#define I2S_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__)\
-                                                    & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI Interrupt is set or not.
-  * @param  __CR2__  copy of I2S CR2 register.
-  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval SET or RESET.
-  */
-#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__)      ((((__CR2__)\
-                                                            & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks if I2S Mode parameter is in allowed range.
-  * @param  __MODE__ specifies the I2S Mode.
-  *         This parameter can be a value of @ref I2S_Mode
-  * @retval None
-  */
-#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX)  || \
-                               ((__MODE__) == I2S_MODE_SLAVE_RX)  || \
-                               ((__MODE__) == I2S_MODE_MASTER_TX) || \
-                               ((__MODE__) == I2S_MODE_MASTER_RX))
-
-#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS)   || \
-                                       ((__STANDARD__) == I2S_STANDARD_MSB)       || \
-                                       ((__STANDARD__) == I2S_STANDARD_LSB)       || \
-                                       ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
-                                       ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
-
-#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B)          || \
-                                        ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
-                                        ((__FORMAT__) == I2S_DATAFORMAT_24B)          || \
-                                        ((__FORMAT__) == I2S_DATAFORMAT_32B))
-
-#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
-                                        ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
-
-#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K)    && \
-                                      ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
-                                     ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
-
-/** @brief  Checks if I2S Serial clock steady state parameter is in allowed range.
-  * @param  __CPOL__ specifies the I2S serial clock steady state.
-  *         This parameter can be a value of @ref I2S_Clock_Polarity
-  * @retval None
-  */
-#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
-                               ((__CPOL__) == I2S_CPOL_HIGH))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_I2S_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_ipcc.h

@@ -1,292 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_ipcc.h
-  * @author  MCD Application Team
-  * @brief   Header file of Mailbox HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_IPCC_H
-#define STM32WLxx_HAL_IPCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-#if defined(IPCC)
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup IPCC IPCC
-  * @brief IPCC HAL module driver
-  * @{
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup IPCC_Exported_Constants IPCC Exported Constants
-  * @{
-  */
-
-/** @defgroup IPCC_Channel IPCC Channel
-  * @{
-  */
-#define IPCC_CHANNEL_1 0x00000000U
-#define IPCC_CHANNEL_2 0x00000001U
-#define IPCC_CHANNEL_3 0x00000002U
-#define IPCC_CHANNEL_4 0x00000003U
-#define IPCC_CHANNEL_5 0x00000004U
-#define IPCC_CHANNEL_6 0x00000005U
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IPCC_Exported_Types IPCC Exported Types
-  * @{
-  */
-
-/**
-  * @brief HAL IPCC State structures definition
-  */
-typedef enum
-{
-  HAL_IPCC_STATE_RESET             = 0x00U,  /*!< IPCC not yet initialized or disabled  */
-  HAL_IPCC_STATE_READY             = 0x01U,  /*!< IPCC initialized and ready for use    */
-  HAL_IPCC_STATE_BUSY              = 0x02U   /*!< IPCC internal processing is ongoing   */
-} HAL_IPCC_StateTypeDef;
-
-/**
-  * @brief  IPCC channel direction structure definition
-  */
-typedef enum
-{
-  IPCC_CHANNEL_DIR_TX  = 0x00U,  /*!< Channel direction Tx is used by an MCU to transmit */
-  IPCC_CHANNEL_DIR_RX  = 0x01U   /*!< Channel direction Rx is used by an MCU to receive */
-} IPCC_CHANNELDirTypeDef;
-
-/**
-  * @brief  IPCC channel status structure definition
-  */
-typedef enum
-{
-  IPCC_CHANNEL_STATUS_FREE       = 0x00U,  /*!< Means that a new msg can be posted on that channel */
-  IPCC_CHANNEL_STATUS_OCCUPIED   = 0x01U   /*!< An MCU has posted a msg the other MCU hasn't retrieved */
-} IPCC_CHANNELStatusTypeDef;
-
-/**
-  * @brief  IPCC handle structure definition
-  */
-typedef struct __IPCC_HandleTypeDef
-{
-  IPCC_TypeDef                   *Instance;     /*!< IPCC registers base address */
-  void (* ChannelCallbackRx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);                            /*!< Rx Callback registration table */
-  void (* ChannelCallbackTx[IPCC_CHANNEL_NUMBER])(struct __IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);                            /*!< Tx Callback registration table */
-  uint32_t                       callbackRequest; /*!< Store information about callback notification by channel */
-  __IO HAL_IPCC_StateTypeDef      State;         /*!< IPCC State: initialized or not */
-} IPCC_HandleTypeDef;
-
-/**
-  * @brief  IPCC callback typedef
-  */
-typedef void ChannelCb(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup IPCC_Exported_Macros IPCC Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Enable the specified interrupt.
-  * @param  __HANDLE__ specifies the IPCC Handle
-  * @param  __CHDIRECTION__ specifies the channels Direction
-  *          This parameter can be one of the following values:
-  *            @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
-  *            @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_IPCC_ENABLE_IT(__HANDLE__, __CHDIRECTION__) \
-            (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
-                ((__HANDLE__)->Instance->C2CR |= IPCC_C2CR_RXOIE) : \
-                ((__HANDLE__)->Instance->C2CR |= IPCC_C2CR_TXFIE))
-#else
-#define __HAL_IPCC_ENABLE_IT(__HANDLE__, __CHDIRECTION__) \
-            (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
-                ((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_RXOIE) : \
-                ((__HANDLE__)->Instance->C1CR |= IPCC_C1CR_TXFIE))
-#endif
-
-/**
-  * @brief  Disable the specified interrupt.
-  * @param  __HANDLE__ specifies the IPCC Handle
-  * @param  __CHDIRECTION__ specifies the channels Direction
-  *          This parameter can be one of the following values:
-  *            @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
-  *            @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_IPCC_DISABLE_IT(__HANDLE__, __CHDIRECTION__) \
-            (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
-                ((__HANDLE__)->Instance->C2CR &= ~IPCC_C2CR_RXOIE) : \
-                ((__HANDLE__)->Instance->C2CR &= ~IPCC_C2CR_TXFIE))
-#else
-#define __HAL_IPCC_DISABLE_IT(__HANDLE__, __CHDIRECTION__) \
-            (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
-                ((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_RXOIE) : \
-                ((__HANDLE__)->Instance->C1CR &= ~IPCC_C1CR_TXFIE))
-#endif
-
-/**
-  * @brief  Mask the specified interrupt.
-  * @param  __HANDLE__ specifies the IPCC Handle
-  * @param  __CHDIRECTION__ specifies the channels Direction
-  *          This parameter can be one of the following values:
-  *            @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
-  *            @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
-  * @param  __CHINDEX__ specifies the channels number:
-  *         This parameter can be one of the following values:
-  *            @arg IPCC_CHANNEL_1: IPCC Channel 1
-  *            @arg IPCC_CHANNEL_2: IPCC Channel 2
-  *            @arg IPCC_CHANNEL_3: IPCC Channel 3
-  *            @arg IPCC_CHANNEL_4: IPCC Channel 4
-  *            @arg IPCC_CHANNEL_5: IPCC Channel 5
-  *            @arg IPCC_CHANNEL_6: IPCC Channel 6
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_IPCC_MASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
-            (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
-                ((__HANDLE__)->Instance->C2MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
-                ((__HANDLE__)->Instance->C2MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
-#else
-#define __HAL_IPCC_MASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
-            (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
-                ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
-                ((__HANDLE__)->Instance->C1MR |= (IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
-#endif
-
-/**
-  * @brief  Unmask the specified interrupt.
-  * @param  __HANDLE__ specifies the IPCC Handle
-  * @param  __CHDIRECTION__ specifies the channels Direction
-  *          This parameter can be one of the following values:
-  *            @arg @ref IPCC_CHANNEL_DIR_TX Transmit channel free interrupt enable
-  *            @arg @ref IPCC_CHANNEL_DIR_RX Receive channel occupied interrupt enable
-  * @param  __CHINDEX__ specifies the channels number:
-  *         This parameter can be one of the following values:
-  *            @arg IPCC_CHANNEL_1: IPCC Channel 1
-  *            @arg IPCC_CHANNEL_2: IPCC Channel 2
-  *            @arg IPCC_CHANNEL_3: IPCC Channel 3
-  *            @arg IPCC_CHANNEL_4: IPCC Channel 4
-  *            @arg IPCC_CHANNEL_5: IPCC Channel 5
-  *            @arg IPCC_CHANNEL_6: IPCC Channel 6
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_IPCC_UNMASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
-            (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
-                ((__HANDLE__)->Instance->C2MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
-                ((__HANDLE__)->Instance->C2MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
-#else
-#define __HAL_IPCC_UNMASK_CHANNEL_IT(__HANDLE__, __CHDIRECTION__, __CHINDEX__) \
-            (((__CHDIRECTION__) == IPCC_CHANNEL_DIR_RX) ? \
-                ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1OM_Msk << (__CHINDEX__))) : \
-                ((__HANDLE__)->Instance->C1MR &= ~(IPCC_C1MR_CH1FM_Msk << (__CHINDEX__))))
-#endif
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup IPCC_Exported_Functions IPCC Exported Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions *******************************/
-/** @defgroup IPCC_Exported_Functions_Group1 Initialization and deinitialization functions
- *  @{
- */
-HAL_StatusTypeDef HAL_IPCC_Init(IPCC_HandleTypeDef *hipcc);
-HAL_StatusTypeDef HAL_IPCC_DeInit(IPCC_HandleTypeDef *hipcc);
-void HAL_IPCC_MspInit(IPCC_HandleTypeDef *hipcc);
-void HAL_IPCC_MspDeInit(IPCC_HandleTypeDef *hipcc);
-/**
-  * @}
-  */
-
-/** @defgroup IPCC_Exported_Functions_Group2 Communication functions
- *  @{
- */
-/* IO operation functions  *****************************************************/
-HAL_StatusTypeDef HAL_IPCC_ActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir, ChannelCb cb);
-HAL_StatusTypeDef HAL_IPCC_DeActivateNotification(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
-IPCC_CHANNELStatusTypeDef HAL_IPCC_GetChannelStatus(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
-HAL_StatusTypeDef HAL_IPCC_NotifyCPU(IPCC_HandleTypeDef const *const hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
-/**
-  * @}
-  */
-
-/** @defgroup IPCC_Exported_Functions_Group3 Peripheral State and Error functions
- *  @{
- */
-/* Peripheral State and Error functions ****************************************/
-HAL_IPCC_StateTypeDef HAL_IPCC_GetState(IPCC_HandleTypeDef const *const hipcc);
-/**
-  * @}
-  */
-
-/** @defgroup IPCC_IRQ_Handler_and_Callbacks Peripheral IRQ Handler and Callbacks
- *  @{
- */
-/* IRQHandler and Callbacks used in non blocking modes  ************************/
-void HAL_IPCC_TX_IRQHandler(IPCC_HandleTypeDef   *const hipcc);
-void HAL_IPCC_RX_IRQHandler(IPCC_HandleTypeDef *const hipcc);
-void HAL_IPCC_TxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
-void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_CHANNELDirTypeDef ChannelDir);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* IPCC */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_IPCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_irda.h

@@ -1,882 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_irda.h
-  * @author  MCD Application Team
-  * @brief   Header file of IRDA HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_IRDA_H
-#define STM32WLxx_HAL_IRDA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup IRDA
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Types IRDA Exported Types
-  * @{
-  */
-
-/**
-  * @brief IRDA Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
-                                           The baud rate register is computed using the following formula:
-                                              Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate)))
-                                           where usart_ker_ckpres is the IRDA input clock divided by a prescaler */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref IRDAEx_Word_Length */
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref IRDA_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
-
-  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref IRDA_Transfer_Mode */
-
-  uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock
-                                           to achieve low-power frequency.
-                                           @note Prescaler value 0 is forbidden */
-
-  uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.
-                                           This parameter can be a value of @ref IRDA_Low_Power */
-
-  uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the IRDA clock source.
-                                           This parameter can be a value of @ref IRDA_ClockPrescaler. */
-
-} IRDA_InitTypeDef;
-
-/**
-  * @brief HAL IRDA State definition
-  * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).
-  *        - gState contains IRDA state information related to global Handle management
-  *          and also information related to Tx operations.
-  *          gState value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : (Not Used)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized. HAL IRDA Init function already called)
-  *          b4-b3  (not used)
-  *             xx : Should be set to 00
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (Peripheral busy with some configuration or internal operations)
-  *          b1     (not used)
-  *             x  : Should be set to 0
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  *        - RxState contains information related to Rx operations.
-  *          RxState value coding follow below described bitmap :
-  *          b7-b6  (not used)
-  *             xx : Should be set to 00
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized)
-  *          b4-b2  (not used)
-  *            xxx : Should be set to 000
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     (not used)
-  *             x  : Should be set to 0.
-  */
-typedef uint32_t HAL_IRDA_StateTypeDef;
-
-/**
-  * @brief IRDA clock sources definition
-  */
-typedef enum
-{
-  IRDA_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source         */
-  IRDA_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source         */
-  IRDA_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source           */
-  IRDA_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source        */
-  IRDA_CLOCKSOURCE_LSE        = 0x10U,    /*!< LSE clock source           */
-  IRDA_CLOCKSOURCE_UNDEFINED  = 0x20U     /*!< Undefined clock source     */
-} IRDA_ClockSourceTypeDef;
-
-/**
-  * @brief  IRDA handle Structure definition
-  */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-typedef struct __IRDA_HandleTypeDef
-#else
-typedef struct
-#endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-{
-  USART_TypeDef            *Instance;        /*!< USART registers base address       */
-
-  IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */
-
-  uint8_t                  *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */
-
-  uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */
-
-  __IO uint16_t            TxXferCount;      /*!< IRDA Tx Transfer Counter           */
-
-  uint8_t                  *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */
-
-  uint16_t                 RxXferSize;       /*!< IRDA Rx Transfer size              */
-
-  __IO uint16_t            RxXferCount;      /*!< IRDA Rx Transfer Counter           */
-
-  uint16_t                 Mask;             /*!< USART RX RDR register mask         */
-
-  DMA_HandleTypeDef        *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */
-
-  DMA_HandleTypeDef        *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */
-
-  HAL_LockTypeDef          Lock;             /*!< Locking object                     */
-
-  __IO HAL_IRDA_StateTypeDef    gState;      /*!< IRDA state information related to global Handle management
-                                                  and also related to Tx operations.
-                                                  This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
-  __IO HAL_IRDA_StateTypeDef    RxState;     /*!< IRDA state information related to Rx operations.
-                                                  This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
-
-  __IO uint32_t            ErrorCode;        /*!< IRDA Error code                    */
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-  void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Tx Half Complete Callback        */
-
-  void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Tx Complete Callback             */
-
-  void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Rx Half Complete Callback        */
-
-  void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Rx Complete Callback             */
-
-  void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda);             /*!< IRDA Error Callback                   */
-
-  void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Abort Complete Callback          */
-
-  void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
-
-  void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda);  /*!< IRDA Abort Receive Complete Callback  */
-
-
-  void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda);           /*!< IRDA Msp Init callback                */
-
-  void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Msp DeInit callback              */
-#endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-} IRDA_HandleTypeDef;
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL IRDA Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_IRDA_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< IRDA Tx Half Complete Callback ID        */
-  HAL_IRDA_TX_COMPLETE_CB_ID             = 0x01U,    /*!< IRDA Tx Complete Callback ID             */
-  HAL_IRDA_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< IRDA Rx Half Complete Callback ID        */
-  HAL_IRDA_RX_COMPLETE_CB_ID             = 0x03U,    /*!< IRDA Rx Complete Callback ID             */
-  HAL_IRDA_ERROR_CB_ID                   = 0x04U,    /*!< IRDA Error Callback ID                   */
-  HAL_IRDA_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< IRDA Abort Complete Callback ID          */
-  HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< IRDA Abort Transmit Complete Callback ID */
-  HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< IRDA Abort Receive Complete Callback ID  */
-
-  HAL_IRDA_MSPINIT_CB_ID                 = 0x08U,    /*!< IRDA MspInit callback ID                 */
-  HAL_IRDA_MSPDEINIT_CB_ID               = 0x09U     /*!< IRDA MspDeInit callback ID               */
-
-} HAL_IRDA_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL IRDA Callback pointer definition
-  */
-typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer to an IRDA callback function */
-
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
-  * @{
-  */
-
-/** @defgroup IRDA_State_Definition IRDA State Code Definition
-  * @{
-  */
-#define HAL_IRDA_STATE_RESET                0x00000000U   /*!< Peripheral is not initialized
-                                                               Value is allowed for gState and RxState */
-#define HAL_IRDA_STATE_READY                0x00000020U   /*!< Peripheral Initialized and ready for use
-                                                               Value is allowed for gState and RxState */
-#define HAL_IRDA_STATE_BUSY                 0x00000024U   /*!< An internal process is ongoing
-                                                               Value is allowed for gState only */
-#define HAL_IRDA_STATE_BUSY_TX              0x00000021U   /*!< Data Transmission process is ongoing
-                                                               Value is allowed for gState only */
-#define HAL_IRDA_STATE_BUSY_RX              0x00000022U   /*!< Data Reception process is ongoing
-                                                               Value is allowed for RxState only */
-#define HAL_IRDA_STATE_BUSY_TX_RX           0x00000023U   /*!< Data Transmission and Reception process is ongoing
-                                                               Not to be used for neither gState nor RxState.
-                                                               Value is result of combination (Or) between gState and RxState values */
-#define HAL_IRDA_STATE_TIMEOUT              0x000000A0U   /*!< Timeout state
-                                                               Value is allowed for gState only */
-#define HAL_IRDA_STATE_ERROR                0x000000E0U   /*!< Error
-                                                               Value is allowed for gState only */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
-  * @{
-  */
-#define HAL_IRDA_ERROR_NONE                 ((uint32_t)0x00000000U)          /*!< No error                */
-#define HAL_IRDA_ERROR_PE                   ((uint32_t)0x00000001U)          /*!< Parity error            */
-#define HAL_IRDA_ERROR_NE                   ((uint32_t)0x00000002U)          /*!< Noise error             */
-#define HAL_IRDA_ERROR_FE                   ((uint32_t)0x00000004U)          /*!< frame error             */
-#define HAL_IRDA_ERROR_ORE                  ((uint32_t)0x00000008U)          /*!< Overrun error           */
-#define HAL_IRDA_ERROR_DMA                  ((uint32_t)0x00000010U)          /*!< DMA transfer error      */
-#define HAL_IRDA_ERROR_BUSY                 ((uint32_t)0x00000020U)          /*!< Busy Error              */
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-#define HAL_IRDA_ERROR_INVALID_CALLBACK     ((uint32_t)0x00000040U)          /*!< Invalid Callback error  */
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Parity IRDA Parity
-  * @{
-  */
-#define IRDA_PARITY_NONE                    0x00000000U                      /*!< No parity   */
-#define IRDA_PARITY_EVEN                    USART_CR1_PCE                    /*!< Even parity */
-#define IRDA_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
-  * @{
-  */
-#define IRDA_MODE_RX                        USART_CR1_RE                   /*!< RX mode        */
-#define IRDA_MODE_TX                        USART_CR1_TE                   /*!< TX mode        */
-#define IRDA_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)   /*!< RX and TX mode */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Low_Power IRDA Low Power
-  * @{
-  */
-#define IRDA_POWERMODE_NORMAL               0x00000000U       /*!< IRDA normal power mode */
-#define IRDA_POWERMODE_LOWPOWER             USART_CR3_IRLP    /*!< IRDA low power mode    */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
-  * @{
-  */
-#define IRDA_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
-#define IRDA_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
-#define IRDA_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
-#define IRDA_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
-#define IRDA_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
-#define IRDA_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
-#define IRDA_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
-#define IRDA_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
-#define IRDA_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
-#define IRDA_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
-#define IRDA_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
-#define IRDA_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_State IRDA State
-  * @{
-  */
-#define IRDA_STATE_DISABLE                  0x00000000U     /*!< IRDA disabled  */
-#define IRDA_STATE_ENABLE                   USART_CR1_UE    /*!< IRDA enabled   */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Mode IRDA Mode
-  * @{
-  */
-#define IRDA_MODE_DISABLE                   0x00000000U      /*!< Associated UART disabled in IRDA mode */
-#define IRDA_MODE_ENABLE                    USART_CR3_IREN   /*!< Associated UART enabled in IRDA mode  */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
-  * @{
-  */
-#define IRDA_ONE_BIT_SAMPLE_DISABLE         0x00000000U       /*!< One-bit sampling disabled */
-#define IRDA_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT  /*!< One-bit sampling enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
-  * @{
-  */
-#define IRDA_DMA_TX_DISABLE                 0x00000000U       /*!< IRDA DMA TX disabled */
-#define IRDA_DMA_TX_ENABLE                  USART_CR3_DMAT    /*!< IRDA DMA TX enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
-  * @{
-  */
-#define IRDA_DMA_RX_DISABLE                 0x00000000U       /*!< IRDA DMA RX disabled */
-#define IRDA_DMA_RX_ENABLE                  USART_CR3_DMAR    /*!< IRDA DMA RX enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
-  * @{
-  */
-#define IRDA_AUTOBAUD_REQUEST            USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
-#define IRDA_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
-#define IRDA_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Flags IRDA Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the ISR register
-  * @{
-  */
-#define IRDA_FLAG_REACK                     USART_ISR_REACK         /*!< IRDA receive enable acknowledge flag      */
-#define IRDA_FLAG_TEACK                     USART_ISR_TEACK         /*!< IRDA transmit enable acknowledge flag     */
-#define IRDA_FLAG_BUSY                      USART_ISR_BUSY          /*!< IRDA busy flag                            */
-#define IRDA_FLAG_ABRF                      USART_ISR_ABRF          /*!< IRDA auto Baud rate flag                  */
-#define IRDA_FLAG_ABRE                      USART_ISR_ABRE          /*!< IRDA auto Baud rate error                 */
-#define IRDA_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< IRDA transmit data register empty         */
-#define IRDA_FLAG_TC                        USART_ISR_TC            /*!< IRDA transmission complete                */
-#define IRDA_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< IRDA read data register not empty         */
-#define IRDA_FLAG_ORE                       USART_ISR_ORE           /*!< IRDA overrun error                        */
-#define IRDA_FLAG_NE                        USART_ISR_NE            /*!< IRDA noise error                          */
-#define IRDA_FLAG_FE                        USART_ISR_FE            /*!< IRDA frame error                          */
-#define IRDA_FLAG_PE                        USART_ISR_PE            /*!< IRDA parity error                         */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
-  *        Elements values convention: 0000ZZZZ0XXYYYYYb
-  *           - YYYYY  : Interrupt source position in the XX register (5bits)
-  *           - XX  : Interrupt source register (2bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  *           - ZZZZ  : Flag position in the ISR register(4bits)
-  * @{
-  */
-#define IRDA_IT_PE                          0x0028U     /*!< IRDA Parity error interruption                 */
-#define IRDA_IT_TXE                         0x0727U     /*!< IRDA Transmit data register empty interruption */
-#define IRDA_IT_TC                          0x0626U     /*!< IRDA Transmission complete interruption        */
-#define IRDA_IT_RXNE                        0x0525U     /*!< IRDA Read data register not empty interruption */
-#define IRDA_IT_IDLE                        0x0424U     /*!< IRDA Idle interruption                         */
-
-/*       Elements values convention: 000000000XXYYYYYb
-             - YYYYY  : Interrupt source position in the XX register (5bits)
-             - XX  : Interrupt source register (2bits)
-                   - 01: CR1 register
-                   - 10: CR2 register
-                   - 11: CR3 register */
-#define IRDA_IT_ERR                         0x0060U       /*!< IRDA Error interruption        */
-
-/*       Elements values convention: 0000ZZZZ00000000b
-             - ZZZZ  : Flag position in the ISR register(4bits) */
-#define IRDA_IT_ORE                         0x0300U      /*!< IRDA Overrun error interruption */
-#define IRDA_IT_NE                          0x0200U      /*!< IRDA Noise error interruption   */
-#define IRDA_IT_FE                          0x0100U      /*!< IRDA Frame error interruption   */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
-  * @{
-  */
-#define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */
-#define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */
-#define IRDA_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag  */
-#define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */
-#define IRDA_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */
-#define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
-  * @{
-  */
-#define IRDA_IT_MASK  0x001FU  /*!< IRDA Interruptions flags mask  */
-#define IRDA_CR_MASK  0x00E0U  /*!< IRDA control register mask     */
-#define IRDA_CR_POS   5U       /*!< IRDA control register position */
-#define IRDA_ISR_MASK 0x1F00U  /*!< IRDA ISR register mask         */
-#define IRDA_ISR_POS  8U       /*!< IRDA ISR register position     */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
-  * @{
-  */
-
-/** @brief  Reset IRDA handle state.
-  * @param  __HANDLE__ IRDA handle.
-  * @retval None
-  */
-#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
-                                                       (__HANDLE__)->MspInitCallback = NULL;             \
-                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
-                                                     } while(0U)
-#else
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \
-                                                     } while(0U)
-#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS  */
-
-/** @brief  Flush the IRDA DR register.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
-  do{                                                                    \
-    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
-    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
-  } while(0U)
-
-/** @brief  Clear the specified IRDA pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref IRDA_CLEAR_PEF
-  *            @arg @ref IRDA_CLEAR_FEF
-  *            @arg @ref IRDA_CLEAR_NEF
-  *            @arg @ref IRDA_CLEAR_OREF
-  *            @arg @ref IRDA_CLEAR_TCF
-  *            @arg @ref IRDA_CLEAR_IDLEF
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief  Clear the IRDA PE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
-
-
-/** @brief  Clear the IRDA FE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
-
-/** @brief  Clear the IRDA NE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
-
-/** @brief  Clear the IRDA ORE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
-
-/** @brief  Clear the IRDA IDLE pending flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
-
-/** @brief  Check whether the specified IRDA flag is set or not.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
-  *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
-  *            @arg @ref IRDA_FLAG_BUSY  Busy flag
-  *            @arg @ref IRDA_FLAG_ABRF  Auto Baud rate detection flag
-  *            @arg @ref IRDA_FLAG_ABRE  Auto Baud rate detection error flag
-  *            @arg @ref IRDA_FLAG_TXE   Transmit data register empty flag
-  *            @arg @ref IRDA_FLAG_TC    Transmission Complete flag
-  *            @arg @ref IRDA_FLAG_RXNE  Receive data register not empty flag
-  *            @arg @ref IRDA_FLAG_ORE   OverRun Error flag
-  *            @arg @ref IRDA_FLAG_NE    Noise Error flag
-  *            @arg @ref IRDA_FLAG_FE    Framing Error flag
-  *            @arg @ref IRDA_FLAG_PE    Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-
-/** @brief  Enable the specified IRDA interrupt.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
-  *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
-  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
-  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
-  *            @arg @ref IRDA_IT_PE   Parity Error interrupt
-  *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
-                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
-                                                           ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
-
-/** @brief  Disable the specified IRDA interrupt.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
-  *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
-  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
-  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
-  *            @arg @ref IRDA_IT_PE   Parity Error interrupt
-  *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
-                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
-                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
-
-
-/** @brief  Check whether the specified IRDA interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
-  *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
-  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
-  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
-  *            @arg @ref IRDA_IT_ORE OverRun Error interrupt
-  *            @arg @ref IRDA_IT_NE Noise Error interrupt
-  *            @arg @ref IRDA_IT_FE Framing Error interrupt
-  *            @arg @ref IRDA_IT_PE Parity Error interrupt
-  * @retval The new state of __IT__ (SET or RESET).
-  */
-#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
-                                                        & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
-
-/** @brief  Check whether the specified IRDA interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
-  *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
-  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
-  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt
-  *            @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
-  *            @arg @ref IRDA_IT_PE Parity Error interrupt
-  * @retval The new state of __IT__ (SET or RESET).
-  */
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
-                                                                (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
-                                                                 (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
-
-/** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
-  *                       to clear the corresponding interrupt
-  *          This parameter can be one of the following values:
-  *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
-  *            @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
-  *            @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
-  *            @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
-  *            @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
-
-
-/** @brief  Set a specific IRDA request flag.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __REQ__ specifies the request flag to set
-  *          This parameter can be one of the following values:
-  *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
-  *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
-  *            @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
-  * @retval None
-  */
-#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-
-/** @brief  Enable the IRDA one bit sample method.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief  Disable the IRDA one bit sample method.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
-                                                       &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
-
-/** @brief  Enable UART/USART associated to IRDA Handle.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
-
-/** @brief  Disable UART/USART associated to IRDA Handle.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None
-  */
-#define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup IRDA_Private_Macros
-  * @{
-  */
-
-/** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
-  * @param  __BAUDRATE__ specifies the IRDA Baudrate set by the user.
-  * @retval True or False
-  */
-#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
-
-/** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
-  * @param  __PRESCALER__ specifies the IRDA prescaler value set by the user.
-  * @retval True or False
-  */
-#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
-
-/** @brief Ensure that IRDA frame parity is valid.
-  * @param __PARITY__ IRDA frame parity.
-  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
-  */
-#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
-                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \
-                                    ((__PARITY__) == IRDA_PARITY_ODD))
-
-/** @brief Ensure that IRDA communication mode is valid.
-  * @param __MODE__ IRDA communication mode.
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
-                                        & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
-
-/** @brief Ensure that IRDA power mode is valid.
-  * @param __MODE__ IRDA power mode.
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
-                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))
-
-/** @brief Ensure that IRDA clock Prescaler is valid.
-  * @param __CLOCKPRESCALER__ IRDA clock Prescaler value.
-  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
-  */
-#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
-                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2)   || \
-                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4)   || \
-                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6)   || \
-                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8)   || \
-                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10)  || \
-                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12)  || \
-                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16)  || \
-                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32)  || \
-                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64)  || \
-                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
-                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
-
-/** @brief Ensure that IRDA state is valid.
-  * @param __STATE__ IRDA state mode.
-  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
-  */
-#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
-                                  ((__STATE__) == IRDA_STATE_ENABLE))
-
-/** @brief Ensure that IRDA associated UART/USART mode is valid.
-  * @param __MODE__ IRDA associated UART/USART mode.
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
-                                 ((__MODE__) == IRDA_MODE_ENABLE))
-
-/** @brief Ensure that IRDA sampling rate is valid.
-  * @param __ONEBIT__ IRDA sampling rate.
-  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
-  */
-#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
-                                                 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
-
-/** @brief Ensure that IRDA DMA TX mode is valid.
-  * @param __DMATX__ IRDA DMA TX mode.
-  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
-  */
-#define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
-                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))
-
-/** @brief Ensure that IRDA DMA RX mode is valid.
-  * @param __DMARX__ IRDA DMA RX mode.
-  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
-  */
-#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
-                                   ((__DMARX__) == IRDA_DMA_RX_ENABLE))
-
-/** @brief Ensure that IRDA request is valid.
-  * @param __PARAM__ IRDA request.
-  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
-  */
-#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
-                                              ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
-                                              ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
-/**
-  * @}
-  */
-
-/* Include IRDA HAL Extended module */
-#include "stm32wlxx_hal_irda_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
-  * @{
-  */
-
-/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
-
-#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
-                                            pIRDA_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
-
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
-
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  ************************************************/
-
-/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
-  * @{
-  */
-
-/* Peripheral State and Error functions ***************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_IRDA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_irda_ex.h

@@ -1,196 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_irda_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of IRDA HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_IRDA_EX_H
-#define STM32WLxx_HAL_IRDA_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup IRDAEx IRDAEx
-  * @brief IRDA Extended HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup IRDAEx_Word_Length IRDAEx Word Length
-  * @{
-  */
-#define IRDA_WORDLENGTH_7B                  USART_CR1_M1   /*!< 7-bit long frame */
-#define IRDA_WORDLENGTH_8B                  0x00000000U    /*!< 8-bit long frame */
-#define IRDA_WORDLENGTH_9B                  USART_CR1_M0   /*!< 9-bit long frame */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
-  * @{
-  */
-
-/** @brief  Report the IRDA clock source.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __CLOCKSOURCE__ output variable.
-  * @retval IRDA clocking source, written in __CLOCKSOURCE__.
-  */
-#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)        \
-  do {                                                         \
-    if((__HANDLE__)->Instance == USART1)                       \
-    {                                                          \
-      switch(__HAL_RCC_GET_USART1_SOURCE())                    \
-      {                                                        \
-        case RCC_USART1CLKSOURCE_PCLK2:                        \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2;          \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
-          break;                                               \
-        default:                                               \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
-          break;                                               \
-      }                                                        \
-    }                                                          \
-    else if((__HANDLE__)->Instance == USART2)                  \
-    {                                                          \
-      switch(__HAL_RCC_GET_USART2_SOURCE())                    \
-      {                                                        \
-        case RCC_USART2CLKSOURCE_PCLK1:                        \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1;          \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;            \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK;         \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;            \
-          break;                                               \
-        default:                                               \
-          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;      \
-          break;                                               \
-      }                                                        \
-    }                                                          \
-    else                                                      \
-    {                                                         \
-      (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \
-    }                                                         \
-  } while(0U)
-
-/** @brief  Compute the mask to apply to retrieve the received data
-  *         according to the word length and to the parity bits activation.
-  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
-  */
-#define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
-  do {                                                                \
-    if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)          \
-    {                                                                 \
-      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x01FFU ;                                \
-      }                                                               \
-      else                                                            \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x00FFU ;                                \
-      }                                                               \
-    }                                                                 \
-    else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)     \
-    {                                                                 \
-      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x00FFU ;                                \
-      }                                                               \
-      else                                                            \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x007FU ;                                \
-      }                                                               \
-    }                                                                 \
-    else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)     \
-    {                                                                 \
-      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x007FU ;                                \
-      }                                                               \
-      else                                                            \
-      {                                                               \
-        (__HANDLE__)->Mask = 0x003FU ;                                \
-      }                                                               \
-    }                                                                 \
-    else                                                              \
-    {                                                                 \
-      (__HANDLE__)->Mask = 0x0000U;                                   \
-    }                                                                 \
-  } while(0U)
-
-/** @brief Ensure that IRDA frame length is valid.
-  * @param __LENGTH__ IRDA frame length.
-  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
-  */
-#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
-                                         ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
-                                         ((__LENGTH__) == IRDA_WORDLENGTH_9B))
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_IRDA_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_iwdg.h

@@ -1,240 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_iwdg.h
-  * @author  MCD Application Team
-  * @brief   Header file of IWDG HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_IWDG_H
-#define STM32WLxx_HAL_IWDG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup IWDG IWDG
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Types IWDG Exported Types
-  * @{
-  */
-
-/**
-  * @brief  IWDG Init structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.
-                            This parameter can be a value of @ref IWDG_Prescaler */
-
-  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-
-  uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-
-} IWDG_InitTypeDef;
-
-/**
-  * @brief  IWDG Handle Structure definition
-  */
-typedef struct
-{
-  IWDG_TypeDef                 *Instance;  /*!< Register base address    */
-
-  IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
-} IWDG_HandleTypeDef;
-
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
-  * @{
-  */
-
-/** @defgroup IWDG_Prescaler IWDG Prescaler
-  * @{
-  */
-#define IWDG_PRESCALER_4                0x00000000u                                     /*!< IWDG prescaler set to 4   */
-#define IWDG_PRESCALER_8                IWDG_PR_PR_0                                    /*!< IWDG prescaler set to 8   */
-#define IWDG_PRESCALER_16               IWDG_PR_PR_1                                    /*!< IWDG prescaler set to 16  */
-#define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 32  */
-#define IWDG_PRESCALER_64               IWDG_PR_PR_2                                    /*!< IWDG prescaler set to 64  */
-#define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)                   /*!< IWDG prescaler set to 256 */
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Window_option IWDG Window option
-  * @{
-  */
-#define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Enable the IWDG peripheral.
-  * @param  __HANDLE__  IWDG handle
-  * @retval None
-  */
-#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
-
-/**
-  * @brief  Reload IWDG counter with value defined in the reload register
-  *         (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
-  * @param  __HANDLE__  IWDG handle
-  * @retval None
-  */
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions
-  * @{
-  */
-
-/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
-  * @{
-  */
-/* Initialization/Start functions  ********************************************/
-HAL_StatusTypeDef     HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef     HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup IWDG_Private_Constants IWDG Private Constants
-  * @{
-  */
-
-/**
-  * @brief  IWDG Key Register BitMask
-  */
-#define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */
-#define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */
-#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */
-#define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup IWDG_Private_Macros IWDG Private Macros
-  * @{
-  */
-
-/**
-  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
-  * @param  __HANDLE__  IWDG handle
-  * @retval None
-  */
-#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
-
-/**
-  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
-  * @param  __HANDLE__  IWDG handle
-  * @retval None
-  */
-#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
-
-/**
-  * @brief  Check IWDG prescaler value.
-  * @param  __PRESCALER__  IWDG prescaler value
-  * @retval None
-  */
-#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
-                                               ((__PRESCALER__) == IWDG_PRESCALER_256))
-
-/**
-  * @brief  Check IWDG reload value.
-  * @param  __RELOAD__  IWDG reload value
-  * @retval None
-  */
-#define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)
-
-/**
-  * @brief  Check IWDG window value.
-  * @param  __WINDOW__  IWDG window value
-  * @retval None
-  */
-#define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_lptim.h

@@ -1,889 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_lptim.h
-  * @author  MCD Application Team
-  * @brief   Header file of LPTIM HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_LPTIM_H
-#define STM32WLxx_HAL_LPTIM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3)
-
-/** @addtogroup LPTIM
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
-  * @{
-  */
-#define LPTIM_EXTI_LINE_LPTIM1  EXTI_IMR1_IM29  /*!< External interrupt line 29 Connected to the LPTIM1 EXTI Line */
-#define LPTIM_EXTI_LINE_LPTIM2  EXTI_IMR1_IM30  /*!< External interrupt line 30 Connected to the LPTIM2 EXTI Line */
-#define LPTIM_EXTI_LINE_LPTIM3  EXTI_IMR1_IM31  /*!< External interrupt line 31 Connected to the LPTIM3 EXTI Line */
-
-/**
-  * @brief  LPTIM Clock configuration definition
-  */
-typedef struct
-{
-  uint32_t Source;         /*!< Selects the clock source.
-                           This parameter can be a value of @ref LPTIM_Clock_Source   */
-
-  uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.
-                           This parameter can be a value of @ref LPTIM_Clock_Prescaler */
-
-} LPTIM_ClockConfigTypeDef;
-
-/**
-  * @brief  LPTIM Clock configuration definition
-  */
-typedef struct
-{
-  uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit
-                           if the ULPTIM input is selected.
-                           Note: This parameter is used only when Ultra low power clock source is used.
-                           Note: If the polarity is configured on 'both edges', an auxiliary clock
-                           (one of the Low power oscillator) must be active.
-                           This parameter can be a value of @ref LPTIM_Clock_Polarity */
-
-  uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.
-                           Note: This parameter is used only when Ultra low power clock source is used.
-                           This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
-
-} LPTIM_ULPClockConfigTypeDef;
-
-/**
-  * @brief  LPTIM Trigger configuration definition
-  */
-typedef struct
-{
-  uint32_t Source;        /*!< Selects the Trigger source.
-                          This parameter can be a value of @ref LPTIM_Trigger_Source */
-
-  uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.
-                          Note: This parameter is used only when an external trigger is used.
-                          This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
-
-  uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.
-                          Note: This parameter is used only when an external trigger is used.
-                          This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */
-} LPTIM_TriggerConfigTypeDef;
-
-/**
-  * @brief  LPTIM Initialization Structure definition
-  */
-typedef struct
-{
-  LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */
-
-  LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */
-
-  LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */
-
-  uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.
-                                                    This parameter can be a value of @ref LPTIM_Output_Polarity */
-
-  uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autoreload and the compare
-                                                    values is done immediately or after the end of current period.
-                                                    This parameter can be a value of @ref LPTIM_Updating_Mode */
-
-  uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event
-                                                    or each external event.
-                                                    This parameter can be a value of @ref LPTIM_Counter_Source */
-
-  uint32_t                     Input1Source;        /*!< Specifies source selected for input1 (GPIO or comparator output).
-                                                    This parameter can be a value of @ref LPTIM_Input1_Source */
-
-  uint32_t                     Input2Source;        /*!< Specifies source selected for input2 (GPIO or comparator output).
-                                                    Note: This parameter is used only for encoder feature so is used only
-                                                    for LPTIM1 instance.
-                                                    This parameter can be a value of @ref LPTIM_Input2_Source */
-
-  uint32_t                     RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
-                                                    reaches zero, an update event is generated and counting restarts
-                                                    from the RCR value (N).
-                                                    Note: When using repetition counter the UpdateMode field must be set to
-                                                          LPTIM_UPDATE_ENDOFPERIOD otherwise unpredictable behavior may occur.
-                                                    This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
-} LPTIM_InitTypeDef;
-
-/**
-  * @brief  HAL LPTIM State structure definition
-  */
-typedef enum
-{
-  HAL_LPTIM_STATE_RESET            = 0x00U,    /*!< Peripheral not yet initialized or disabled  */
-  HAL_LPTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use    */
-  HAL_LPTIM_STATE_BUSY             = 0x02U,    /*!< An internal process is ongoing              */
-  HAL_LPTIM_STATE_TIMEOUT          = 0x03U,    /*!< Timeout state                               */
-  HAL_LPTIM_STATE_ERROR            = 0x04U     /*!< Internal Process is ongoing                 */
-} HAL_LPTIM_StateTypeDef;
-
-/**
-  * @brief  LPTIM handle Structure definition
-  */
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-typedef struct __LPTIM_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-{
-  LPTIM_TypeDef                 *Instance;         /*!< Register base address     */
-
-  LPTIM_InitTypeDef              Init;             /*!< LPTIM required parameters */
-
-  HAL_StatusTypeDef              Status;           /*!< LPTIM peripheral status   */
-
-  HAL_LockTypeDef                Lock;             /*!< LPTIM locking object      */
-
-  __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */
-
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-  void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< LPTIM Base Msp Init Callback                 */
-  void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);          /*!< LPTIM Base Msp DeInit Callback               */
-  void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare match Callback                       */
-  void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload match Callback                   */
-  void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< External trigger event detection Callback    */
-  void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare register write complete Callback     */
-  void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload register write complete Callback */
-  void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim);        /*!< Up-counting direction change Callback        */
-  void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim);      /*!< Down-counting direction change Callback      */
-  void (* UpdateEventCallback)(struct __LPTIM_HandleTypeDef *hlptim);        /*!< Update event detection Callback              */
-  void (* RepCounterWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Repetition counter register write complete Callback */
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-} LPTIM_HandleTypeDef;
-
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL LPTIM Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_LPTIM_MSPINIT_CB_ID          = 0x00U,    /*!< LPTIM Base Msp Init Callback ID                  */
-  HAL_LPTIM_MSPDEINIT_CB_ID        = 0x01U,    /*!< LPTIM Base Msp DeInit Callback ID                */
-  HAL_LPTIM_COMPARE_MATCH_CB_ID    = 0x02U,    /*!< Compare match Callback ID                        */
-  HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,    /*!< Auto-reload match Callback ID                    */
-  HAL_LPTIM_TRIGGER_CB_ID          = 0x04U,    /*!< External trigger event detection Callback ID     */
-  HAL_LPTIM_COMPARE_WRITE_CB_ID    = 0x05U,    /*!< Compare register write complete Callback ID      */
-  HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U,    /*!< Auto-reload register write complete Callback ID  */
-  HAL_LPTIM_DIRECTION_UP_CB_ID     = 0x07U,    /*!< Up-counting direction change Callback ID         */
-  HAL_LPTIM_DIRECTION_DOWN_CB_ID   = 0x08U,    /*!< Down-counting direction change Callback ID       */
-  HAL_LPTIM_UPDATE_EVENT_CB_ID      = 0x09U,   /*!< Update event detection Callback ID               */
-  HAL_LPTIM_REP_COUNTER_WRITE_CB_ID = 0x0AU,   /*!< Repetition counter register write complete Callback ID */
-} HAL_LPTIM_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL TIM Callback pointer definition
-  */
-typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< pointer to the LPTIM callback function */
-
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
-  * @{
-  */
-
-/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
-  * @{
-  */
-#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        0x00000000U
-#define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
-  * @{
-  */
-#define LPTIM_PRESCALER_DIV1                    0x00000000U
-#define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0
-#define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1
-#define LPTIM_PRESCALER_DIV8                    (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
-#define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2
-#define LPTIM_PRESCALER_DIV32                   (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
-#define LPTIM_PRESCALER_DIV64                   (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
-#define LPTIM_PRESCALER_DIV128                  LPTIM_CFGR_PRESC
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
-  * @{
-  */
-
-#define LPTIM_OUTPUTPOLARITY_HIGH               0x00000000U
-#define LPTIM_OUTPUTPOLARITY_LOW                LPTIM_CFGR_WAVPOL
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
-  * @{
-  */
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION  0x00000000U
-#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_CKFLT_0
-#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_CKFLT_1
-#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_CKFLT
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
-  * @{
-  */
-#define LPTIM_CLOCKPOLARITY_RISING              0x00000000U
-#define LPTIM_CLOCKPOLARITY_FALLING             LPTIM_CFGR_CKPOL_0
-#define LPTIM_CLOCKPOLARITY_RISING_FALLING      LPTIM_CFGR_CKPOL_1
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
-  * @{
-  */
-#define LPTIM_TRIGSOURCE_SOFTWARE               0x0000FFFFU
-#define LPTIM_TRIGSOURCE_0                      0x00000000U
-#define LPTIM_TRIGSOURCE_1                      LPTIM_CFGR_TRIGSEL_0
-#define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1
-#define LPTIM_TRIGSOURCE_3                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
-#define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2
-#define LPTIM_TRIGSOURCE_5                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
-#define LPTIM_TRIGSOURCE_6                      (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
-#define LPTIM_TRIGSOURCE_7                      LPTIM_CFGR_TRIGSEL
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
-  * @{
-  */
-#define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0
-#define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1
-#define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
-  * @{
-  */
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  0x00000000U
-#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0
-#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1
-#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
-  * @{
-  */
-
-#define LPTIM_UPDATE_IMMEDIATE                  0x00000000U
-#define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
-  * @{
-  */
-
-#define LPTIM_COUNTERSOURCE_INTERNAL            0x00000000U
-#define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
-  * @{
-  */
-
-#define LPTIM_INPUT1SOURCE_GPIO          0x00000000U   /*!< For LPTIM1, LPTIM2 and LPTIM3 */
-#define LPTIM_INPUT1SOURCE_COMP1         LPTIM_OR_OR_0 /*!< For LPTIM1, LPTIM2 and LPTIM3 */
-#define LPTIM_INPUT1SOURCE_COMP2         LPTIM_OR_OR_1 /*!< For LPTIM2 and LPTIM3 */
-#define LPTIM_INPUT1SOURCE_COMP1_COMP2   LPTIM_OR_OR   /*!< For LPTIM2 and LPTIM3 */
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
-  * @{
-  */
-
-#define LPTIM_INPUT2SOURCE_GPIO         0x00000000U                    /*!< For LPTIM1 */
-#define LPTIM_INPUT2SOURCE_COMP2        LPTIM_OR_OR_1                  /*!< For LPTIM1 */
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
-  * @{
-  */
-
-#define LPTIM_FLAG_REPOK                         LPTIM_ISR_REPOK
-#define LPTIM_FLAG_UPDATE                        LPTIM_ISR_UE
-#define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN
-#define LPTIM_FLAG_UP                            LPTIM_ISR_UP
-#define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK
-#define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK
-#define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG
-#define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM
-#define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM
-/**
-  * @}
-  */
-
-/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
-  * @{
-  */
-#define LPTIM_IT_REPOK                           LPTIM_IER_REPOKIE
-#define LPTIM_IT_UPDATE                          LPTIM_IER_UEIE
-#define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE
-#define LPTIM_IT_UP                              LPTIM_IER_UPIE
-#define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE
-#define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE
-#define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE
-#define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE
-#define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
-  * @{
-  */
-
-/** @brief Reset LPTIM handle state.
-  * @param  __HANDLE__ LPTIM handle
-  * @retval None
-  */
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                          \
-                                                        (__HANDLE__)->State             = HAL_LPTIM_STATE_RESET; \
-                                                        (__HANDLE__)->MspInitCallback   = NULL;                  \
-                                                        (__HANDLE__)->MspDeInitCallback = NULL;                  \
-                                                      } while(0)
-#else
-#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Enable the LPTIM peripheral.
-  * @param  __HANDLE__ LPTIM handle
-  * @retval None
-  */
-#define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
-
-/**
-  * @brief  Disable the LPTIM peripheral.
-  * @param  __HANDLE__ LPTIM handle
-  * @note   The following sequence is required to solve LPTIM disable HW limitation.
-  *         Please check Errata Sheet ES0335 for more details under "MCU may remain
-  *         stuck in LPTIM interrupt when entering Stop mode" section.
-  * @note   Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
-  *         check for TIMEOUT.
-  * @retval None
-  */
-#define __HAL_LPTIM_DISABLE(__HANDLE__)   LPTIM_Disable(__HANDLE__)
-
-/**
-  * @brief  Start the LPTIM peripheral in Continuous mode.
-  * @param  __HANDLE__ LPTIM handle
-  * @retval None
-  */
-#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)
-/**
-  * @brief  Start the LPTIM peripheral in single mode.
-  * @param  __HANDLE__ LPTIM handle
-  * @retval None
-  */
-#define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)
-
-/**
-  * @brief  Reset the LPTIM Counter register in synchronous mode.
-  * @param  __HANDLE__ LPTIM handle
-  * @retval None
-  */
-#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_COUNTRST)
-
-/**
-  * @brief  Reset after read of the LPTIM Counter register in asynchronous mode.
-  * @param  __HANDLE__ LPTIM handle
-  * @retval None
-  */
-#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_RSTARE)
-
-/**
-  * @brief  Write the passed parameter in the Autoreload register.
-  * @param  __HANDLE__ LPTIM handle
-  * @param  __VALUE__ Autoreload value
-  * @retval None
-  * @note   The ARR register can only be modified when the LPTIM instance is enabled.
-  */
-#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
-
-/**
-  * @brief  Write the passed parameter in the Compare register.
-  * @param  __HANDLE__ LPTIM handle
-  * @param  __VALUE__ Compare value
-  * @retval None
-  * @note   The CMP register can only be modified when the LPTIM instance is enabled.
-  */
-#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))
-
-/**
-  * @brief  Write the passed parameter in the Repetition register.
-  * @param  __HANDLE__ LPTIM handle
-  * @param  __VALUE__ Repetition value
-  * @retval None
-  */
-#define __HAL_LPTIM_REPETITIONCOUNTER_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->RCR =  (__VALUE__))
-
-/**
-  * @brief  Return the current Repetition value.
-  * @param  __HANDLE__ LPTIM handle
-  * @retval Repetition register value
-  * @note   The RCR register can only be modified when the LPTIM instance is enabled.
-  */
-#define __HAL_LPTIM_REPETITIONCOUNTER_GET(__HANDLE__)  ((__HANDLE__)->Instance->RCR)
-
-/**
-  * @brief  Check whether the specified LPTIM flag is set or not.
-  * @param  __HANDLE__ LPTIM handle
-  * @param  __FLAG__ LPTIM flag to check
-  *            This parameter can be a value of:
-  *            @arg LPTIM_FLAG_REPOK   : Repetition register update OK Flag.
-  *            @arg LPTIM_FLAG_UPDATE  : Update event Flag.
-  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
-  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
-  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
-  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
-  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
-  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
-  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
-  * @retval The state of the specified flag (SET or RESET).
-  */
-#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clear the specified LPTIM flag.
-  * @param  __HANDLE__ LPTIM handle.
-  * @param  __FLAG__ LPTIM flag to clear.
-  *            This parameter can be a value of:
-  *            @arg LPTIM_FLAG_REPOK   : Repetition register update OK Flag.
-  *            @arg LPTIM_FLAG_UPDATE  : Update event Flag.
-  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.
-  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.
-  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.
-  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.
-  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
-  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.
-  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.
-  * @retval None.
-  */
-#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ICR  = (__FLAG__))
-
-/**
-  * @brief  Enable the specified LPTIM interrupt.
-  * @param  __HANDLE__ LPTIM handle.
-  * @param  __INTERRUPT__ LPTIM interrupt to set.
-  *            This parameter can be a value of:
-  *            @arg LPTIM_IT_REPOK   : Repetition register update OK Interrupt.
-  *            @arg LPTIM_IT_UPDATE  : Update event register Interrupt.
-  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
-  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
-  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
-  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
-  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
-  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
-  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
-  * @retval None.
-  * @note   The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
-  */
-#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified LPTIM interrupt.
-  * @param  __HANDLE__ LPTIM handle.
-  * @param  __INTERRUPT__ LPTIM interrupt to set.
-  *            This parameter can be a value of:
-  *            @arg LPTIM_IT_REPOK   : Repetition register update OK Interrupt.
-  *            @arg LPTIM_IT_UPDATE  : Update event register Interrupt.
-  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
-  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
-  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
-  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
-  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
-  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
-  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
-  * @retval None.
-  * @note   The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
-  */
-#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))
-
-/**
-  * @brief  Check whether the specified LPTIM interrupt source is enabled or not.
-  * @param  __HANDLE__ LPTIM handle.
-  * @param  __INTERRUPT__ LPTIM interrupt to check.
-  *            This parameter can be a value of:
-  *            @arg LPTIM_IT_REPOK   : Repetition register update OK Interrupt.
-  *            @arg LPTIM_IT_UPDATE  : Update event register Interrupt.
-  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.
-  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.
-  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.
-  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.
-  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
-  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
-  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
-  * @retval Interrupt status.
-  */
-
-#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \
-                                                                (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-#if defined(CORE_CM0PLUS)
-#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT()            (EXTI->C2IMR1 |= \
-                                                        LPTIM_EXTI_LINE_LPTIM1)
-#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT()           (EXTI->C2IMR1 &= \
-                                                        ~(LPTIM_EXTI_LINE_LPTIM1))
-
-#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT()            (EXTI->C2IMR1 |= \
-                                                        LPTIM_EXTI_LINE_LPTIM2)
-#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT()           (EXTI->C2IMR1 &= \
-                                                        ~(LPTIM_EXTI_LINE_LPTIM2))
-
-#define __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT()            (EXTI->C2IMR1 |= \
-                                                        LPTIM_EXTI_LINE_LPTIM3)
-#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT()           (EXTI->C2IMR1 &= \
-                                                        ~(LPTIM_EXTI_LINE_LPTIM3))
-#else
-#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT()            (EXTI->IMR1 |= \
-                                                        LPTIM_EXTI_LINE_LPTIM1)
-#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT()           (EXTI->IMR1 &= \
-                                                        ~(LPTIM_EXTI_LINE_LPTIM1))
-
-#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT()            (EXTI->IMR1 |= \
-                                                        LPTIM_EXTI_LINE_LPTIM2)
-#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT()           (EXTI->IMR1 &= \
-                                                        ~(LPTIM_EXTI_LINE_LPTIM2))
-
-#define __HAL_LPTIM_LPTIM3_EXTI_ENABLE_IT()            (EXTI->IMR1 |= \
-                                                        LPTIM_EXTI_LINE_LPTIM3)
-#define __HAL_LPTIM_LPTIM3_EXTI_DISABLE_IT()           (EXTI->IMR1 &= \
-                                                        ~(LPTIM_EXTI_LINE_LPTIM3))
-#endif
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
-  * @{
-  */
-
-/** @addtogroup LPTIM_Exported_Functions_Group1
-  *  @brief    Initialization and Configuration functions.
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
-HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
-
-/* MSP functions  *************************************************************/
-void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
-/**
-  * @}
-  */
-
-/** @addtogroup LPTIM_Exported_Functions_Group2
-  *  @brief   Start-Stop operation functions.
-  * @{
-  */
-/* Start/Stop operation functions  *********************************************/
-/* ################################# PWM Mode ################################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################# One Pulse Mode ##############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################## Set once Mode ##############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
-HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################### Encoder Mode ##############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
-HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################# Time out  Mode ##############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
-HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-
-/* ############################## Counter Mode ###############################*/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
-HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
-HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
-/**
-  * @}
-  */
-
-/** @addtogroup LPTIM_Exported_Functions_Group3
-  *  @brief  Read operation functions.
-  * @{
-  */
-/* Reading operation functions ************************************************/
-uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
-uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
-uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
-/**
-  * @}
-  */
-
-/** @addtogroup LPTIM_Exported_Functions_Group4
-  *  @brief  LPTIM IRQ handler and callback functions.
-  * @{
-  */
-/* LPTIM IRQ functions  *******************************************************/
-void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
-
-/* CallBack functions  ********************************************************/
-void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_UpdateEventCallback(LPTIM_HandleTypeDef *hlptim);
-void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
-                                             pLPTIM_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup LPTIM_Group5
-  *  @brief   Peripheral State functions.
-  * @{
-  */
-/* Peripheral State functions  ************************************************/
-HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Types LPTIM Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
-  * @{
-  */
-
-#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)       (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
-                                                 ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
-
-
-#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \
-                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \
-                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \
-                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \
-                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \
-                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \
-                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \
-                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))
-
-#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)
-
-#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)  (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
-                                                 ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
-
-#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
-                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \
-                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \
-                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
-
-#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)   (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \
-                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
-                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
-
-#define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
-                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_7))
-
-#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \
-                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \
-                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
-
-#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
-                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \
-                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \
-                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))
-
-#define IS_LPTIM_UPDATE_MODE(__MODE__)          (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
-                                                 ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
-
-#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)     (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
-                                                 ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
-
-#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)     ((__AUTORELOAD__) <= 0x0000FFFFUL)
-
-#define IS_LPTIM_COMPARE(__COMPARE__)           ((__COMPARE__) <= 0x0000FFFFUL)
-
-#define IS_LPTIM_PERIOD(__PERIOD__)             ((__PERIOD__) <= 0x0000FFFFUL)
-
-#define IS_LPTIM_PULSE(__PULSE__)               ((__PULSE__) <= 0x0000FFFFUL)
-
-#define IS_LPTIM_REPETITION(__REPETITION__)     ((__REPETITION__) <= 0x000000FFUL)
-
-#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)    \
-  ((((__INSTANCE__) == LPTIM1) &&                           \
-    (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||           \
-     ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))           \
-   ||                                                       \
-   (((__INSTANCE__) == LPTIM2) &&                           \
-    (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||           \
-     ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||          \
-     ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||          \
-     ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2)))     \
-   ||                                                       \
-   (((__INSTANCE__) == LPTIM3) &&                           \
-    (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO)  ||          \
-     ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||          \
-     ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||          \
-     ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))))
-
-#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)  \
-  (((__INSTANCE__) == LPTIM1) &&                          \
-   (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||          \
-    ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
-  * @{
-  */
-void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* LPTIM1 || LPTIM2  || LPTIM3 */
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_LPTIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pka.h

@@ -1,567 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_pka.h
-  * @author  MCD Application Team
-  * @brief   Header file of PKA HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_PKA_H
-#define STM32WLxx_HAL_PKA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
- * @{
- */
-
-#if defined(PKA) && defined(HAL_PKA_MODULE_ENABLED)
-
-/** @addtogroup PKA
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup PKA_Exported_Types PKA Exported Types
- * @{
- */
-
-/** @defgroup HAL_state_structure_definition HAL state structure definition
-  * @brief  HAL State structures definition
-  * @{
-  */
-typedef enum
-{
-  HAL_PKA_STATE_RESET   = 0x00U,  /*!< PKA not yet initialized or disabled  */
-  HAL_PKA_STATE_READY   = 0x01U,  /*!< PKA initialized and ready for use    */
-  HAL_PKA_STATE_BUSY    = 0x02U,  /*!< PKA internal processing is ongoing   */
-  HAL_PKA_STATE_ERROR   = 0x03U,  /*!< PKA error state                      */
-}
-HAL_PKA_StateTypeDef;
-
-/**
-  * @}
-  */
-
-#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
-/** @defgroup HAL_callback_id HAL callback ID enumeration
-  * @{
-  */
-typedef enum
-{
-  HAL_PKA_OPERATION_COMPLETE_CB_ID      = 0x00U,    /*!< PKA End of operation callback ID  */
-  HAL_PKA_ERROR_CB_ID                   = 0x01U,    /*!< PKA Error callback ID             */
-  HAL_PKA_MSPINIT_CB_ID                 = 0x02U,    /*!< PKA Msp Init callback ID          */
-  HAL_PKA_MSPDEINIT_CB_ID               = 0x03U     /*!< PKA Msp DeInit callback ID        */
-} HAL_PKA_CallbackIDTypeDef;
-
-/**
-  * @}
-  */
-
-#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
-
-/** @defgroup PKA_Error_Code_definition PKA Error Code definition
-  * @brief  PKA Error Code definition
-  * @{
-  */
-#define HAL_PKA_ERROR_NONE      (0x00000000U)
-#define HAL_PKA_ERROR_ADDRERR   (0x00000001U)
-#define HAL_PKA_ERROR_RAMERR    (0x00000002U)
-#define HAL_PKA_ERROR_TIMEOUT   (0x00000004U)
-#define HAL_PKA_ERROR_OPERATION (0x00000008U)
-#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
-#define HAL_PKA_ERROR_INVALID_CALLBACK  (0x00000010U)    /*!< Invalid Callback error */
-#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup PKA_handle_Structure_definition PKA handle Structure definition
-  * @brief  PKA handle Structure definition
-  * @{
-  */
-#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
-typedef struct __PKA_HandleTypeDef
-#else
-typedef struct
-#endif  /* USE_HAL_PKA_REGISTER_CALLBACKS */
-{
-  PKA_TypeDef                   *Instance;              /*!< Register base address */
-  __IO HAL_PKA_StateTypeDef     State;                  /*!< PKA state */
-  __IO uint32_t                 ErrorCode;              /*!< PKA Error code */
-#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
-  void (* OperationCpltCallback)(struct __PKA_HandleTypeDef *hpka); /*!< PKA End of operation callback */
-  void (* ErrorCallback)(struct __PKA_HandleTypeDef *hpka);         /*!< PKA Error callback            */
-  void (* MspInitCallback)(struct __PKA_HandleTypeDef *hpka);       /*!< PKA Msp Init callback         */
-  void (* MspDeInitCallback)(struct __PKA_HandleTypeDef *hpka);     /*!< PKA Msp DeInit callback       */
-#endif  /* USE_HAL_PKA_REGISTER_CALLBACKS */
-} PKA_HandleTypeDef;
-/**
-  * @}
-  */
-
-#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
-/** @defgroup PKA_Callback_definition PKA Callback pointer definition
-  * @brief  PKA Callback pointer definition
-  * @{
-  */
-typedef  void (*pPKA_CallbackTypeDef)(PKA_HandleTypeDef *hpka); /*!< Pointer to a PKA callback function */
-/**
-  * @}
-  */
-#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
-/** @defgroup PKA_Operation PKA operation structure definition
-  * @brief  Input and output data definition
-  * @{
-  */
-typedef struct
-{
-  uint32_t scalarMulSize;              /*!< Number of element in scalarMul array */
-  uint32_t modulusSize;                /*!< Number of element in modulus, coefA, pointX and pointY arrays */
-  uint32_t coefSign;                   /*!< Curve coefficient a sign */
-  const uint8_t *coefA;                /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
-  const uint8_t *modulus;              /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
-  const uint8_t *pointX;               /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
-  const uint8_t *pointY;               /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
-  const uint8_t *scalarMul;            /*!< Pointer to scalar multiplier k   (Array of scalarMulSize elements) */
-  const uint32_t *pMontgomeryParam;    /*!< Pointer to Montgomery parameter  (Array of modulusSize/4 elements) */
-} PKA_ECCMulFastModeInTypeDef;
-
-typedef struct
-{
-  uint32_t scalarMulSize;              /*!< Number of element in scalarMul array */
-  uint32_t modulusSize;                /*!< Number of element in modulus, coefA, pointX and pointY arrays */
-  uint32_t coefSign;                   /*!< Curve coefficient a sign */
-  const uint8_t *coefA;                /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
-  const uint8_t *modulus;              /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
-  const uint8_t *pointX;               /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
-  const uint8_t *pointY;               /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
-  const uint8_t *scalarMul;            /*!< Pointer to scalar multiplier k   (Array of scalarMulSize elements) */
-} PKA_ECCMulInTypeDef;
-
-typedef struct
-{
-  uint32_t modulusSize;                /*!< Number of element in coefA, coefB, modulus, pointX and pointY arrays */
-  uint32_t coefSign;                   /*!< Curve coefficient a sign */
-  const uint8_t *coefA;                /*!< Pointer to curve coefficient |a| (Array of modulusSize elements) */
-  const uint8_t *coefB;                /*!< Pointer to curve coefficient b   (Array of modulusSize elements) */
-  const uint8_t *modulus;              /*!< Pointer to curve modulus value p (Array of modulusSize elements) */
-  const uint8_t *pointX;               /*!< Pointer to point P coordinate xP (Array of modulusSize elements) */
-  const uint8_t *pointY;               /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
-} PKA_PointCheckInTypeDef;
-
-typedef struct
-{
-  uint32_t size;                       /*!< Number of element in popA array */
-  const uint8_t *pOpDp;                /*!< Pointer to operand dP   (Array of size/2 elements) */
-  const uint8_t *pOpDq;                /*!< Pointer to operand dQ   (Array of size/2 elements) */
-  const uint8_t *pOpQinv;              /*!< Pointer to operand qinv (Array of size/2 elements) */
-  const uint8_t *pPrimeP;              /*!< Pointer to prime p      (Array of size/2 elements) */
-  const uint8_t *pPrimeQ;              /*!< Pointer to prime Q      (Array of size/2 elements) */
-  const uint8_t *popA;                 /*!< Pointer to operand A    (Array of size elements) */
-} PKA_RSACRTExpInTypeDef;
-
-typedef struct
-{
-  uint32_t primeOrderSize;             /*!< Number of element in primeOrder array */
-  uint32_t modulusSize;                /*!< Number of element in modulus array */
-  uint32_t coefSign;                   /*!< Curve coefficient a sign */
-  const uint8_t *coef;                 /*!< Pointer to curve coefficient |a|     (Array of modulusSize elements) */
-  const uint8_t *modulus;              /*!< Pointer to curve modulus value p     (Array of modulusSize elements) */
-  const uint8_t *basePointX;           /*!< Pointer to curve base point xG       (Array of modulusSize elements) */
-  const uint8_t *basePointY;           /*!< Pointer to curve base point yG       (Array of modulusSize elements) */
-  const uint8_t *pPubKeyCurvePtX;      /*!< Pointer to public-key curve point xQ (Array of modulusSize elements) */
-  const uint8_t *pPubKeyCurvePtY;      /*!< Pointer to public-key curve point yQ (Array of modulusSize elements) */
-  const uint8_t *RSign;                /*!< Pointer to signature part r          (Array of primeOrderSize elements) */
-  const uint8_t *SSign;                /*!< Pointer to signature part s          (Array of primeOrderSize elements) */
-  const uint8_t *hash;                 /*!< Pointer to hash of the message e     (Array of primeOrderSize elements) */
-  const uint8_t *primeOrder;           /*!< Pointer to order of the curve n      (Array of primeOrderSize elements) */
-} PKA_ECDSAVerifInTypeDef;
-
-typedef struct
-{
-  uint32_t primeOrderSize;             /*!< Number of element in primeOrder array */
-  uint32_t modulusSize;                /*!< Number of element in modulus array */
-  uint32_t coefSign;                   /*!< Curve coefficient a sign */
-  const uint8_t *coef;                 /*!< Pointer to curve coefficient |a|     (Array of modulusSize elements) */
-  const uint8_t *modulus;              /*!< Pointer to curve modulus value p     (Array of modulusSize elements) */
-  const uint8_t *integer;              /*!< Pointer to random integer k          (Array of primeOrderSize elements) */
-  const uint8_t *basePointX;           /*!< Pointer to curve base point xG       (Array of modulusSize elements) */
-  const uint8_t *basePointY;           /*!< Pointer to curve base point yG       (Array of modulusSize elements) */
-  const uint8_t *hash;                 /*!< Pointer to hash of the message       (Array of primeOrderSize elements) */
-  const uint8_t *privateKey;           /*!< Pointer to private key d             (Array of primeOrderSize elements) */
-  const uint8_t *primeOrder;           /*!< Pointer to order of the curve n      (Array of primeOrderSize elements) */
-} PKA_ECDSASignInTypeDef;
-
-typedef struct
-{
-  uint8_t *RSign;                      /*!< Pointer to signature part r          (Array of modulusSize elements) */
-  uint8_t *SSign;                      /*!< Pointer to signature part s          (Array of modulusSize elements) */
-} PKA_ECDSASignOutTypeDef;
-
-typedef struct
-{
-  uint8_t *ptX;                        /*!< Pointer to point P coordinate xP     (Array of modulusSize elements) */
-  uint8_t *ptY;                        /*!< Pointer to point P coordinate yP     (Array of modulusSize elements) */
-} PKA_ECDSASignOutExtParamTypeDef, PKA_ECCMulOutTypeDef;
-
-
-typedef struct
-{
-  uint32_t expSize;                    /*!< Number of element in pExp array */
-  uint32_t OpSize;                     /*!< Number of element in pOp1 and pMod arrays */
-  const uint8_t *pExp;                 /*!< Pointer to Exponent             (Array of expSize elements) */
-  const uint8_t *pOp1;                 /*!< Pointer to Operand              (Array of OpSize elements) */
-  const uint8_t *pMod;                 /*!< Pointer to modulus              (Array of OpSize elements) */
-} PKA_ModExpInTypeDef;
-
-
-typedef struct
-{
-  uint32_t expSize;                    /*!< Number of element in pExp and pMontgomeryParam arrays */
-  uint32_t OpSize;                     /*!< Number of element in pOp1 and pMod arrays */
-  const uint8_t *pExp;                 /*!< Pointer to Exponent             (Array of expSize elements) */
-  const uint8_t *pOp1;                 /*!< Pointer to Operand              (Array of OpSize elements) */
-  const uint8_t *pMod;                 /*!< Pointer to modulus              (Array of OpSize elements) */
-  const uint32_t *pMontgomeryParam;    /*!< Pointer to Montgomery parameter (Array of expSize/4 elements) */
-} PKA_ModExpFastModeInTypeDef;
-
-typedef struct
-{
-  uint32_t size;                       /*!< Number of element in pOp1 array */
-  const uint8_t *pOp1;                 /*!< Pointer to Operand (Array of size elements) */
-} PKA_MontgomeryParamInTypeDef;
-
-typedef struct
-{
-  uint32_t size;                       /*!< Number of element in pOp1 and pOp2 arrays */
-  const uint32_t *pOp1;                /*!< Pointer to Operand 1 (Array of size elements) */
-  const uint32_t *pOp2;                /*!< Pointer to Operand 2 (Array of size elements) */
-} PKA_AddInTypeDef, PKA_SubInTypeDef, PKA_MulInTypeDef, PKA_CmpInTypeDef;
-
-typedef struct
-{
-  uint32_t size;                       /*!< Number of element in pOp1 array */
-  const uint32_t *pOp1;                /*!< Pointer to Operand 1       (Array of size elements) */
-  const uint8_t *pMod;                 /*!< Pointer to modulus value n (Array of size*4 elements) */
-} PKA_ModInvInTypeDef;
-
-typedef struct
-{
-  uint32_t OpSize;                     /*!< Number of element in pOp1 array */
-  uint32_t modSize;                    /*!< Number of element in pMod array */
-  const uint32_t *pOp1;                /*!< Pointer to Operand 1       (Array of OpSize elements) */
-  const uint8_t *pMod;                 /*!< Pointer to modulus value n (Array of modSize elements) */
-} PKA_ModRedInTypeDef;
-
-typedef struct
-{
-  uint32_t size;                       /*!< Number of element in pOp1 and pOp2 arrays */
-  const uint32_t *pOp1;                /*!< Pointer to Operand 1 (Array of size elements) */
-  const uint32_t *pOp2;                /*!< Pointer to Operand 2 (Array of size elements) */
-  const uint8_t  *pOp3;                /*!< Pointer to Operand 3 (Array of size*4 elements) */
-} PKA_ModAddInTypeDef, PKA_ModSubInTypeDef, PKA_MontgomeryMulInTypeDef;
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PKA_Exported_Constants PKA Exported Constants
-  * @{
-  */
-
-/** @defgroup PKA_Mode PKA mode
-  * @{
-  */
-#define PKA_MODE_MONTGOMERY_PARAM                 (0x00000001U)
-#define PKA_MODE_MODULAR_EXP                      (0x00000000U)
-#define PKA_MODE_MODULAR_EXP_FAST_MODE            (0x00000002U)
-#define PKA_MODE_ECC_MUL                          (0x00000020U)
-#define PKA_MODE_ECC_MUL_FAST_MODE                (0x00000022U)
-#define PKA_MODE_ECDSA_SIGNATURE                  (0x00000024U)
-#define PKA_MODE_ECDSA_VERIFICATION               (0x00000026U)
-#define PKA_MODE_POINT_CHECK                      (0x00000028U)
-#define PKA_MODE_RSA_CRT_EXP                      (0x00000007U)
-#define PKA_MODE_MODULAR_INV                      (0x00000008U)
-#define PKA_MODE_ARITHMETIC_ADD                   (0x00000009U)
-#define PKA_MODE_ARITHMETIC_SUB                   (0x0000000AU)
-#define PKA_MODE_ARITHMETIC_MUL                   (0x0000000BU)
-#define PKA_MODE_COMPARISON                       (0x0000000CU)
-#define PKA_MODE_MODULAR_RED                      (0x0000000DU)
-#define PKA_MODE_MODULAR_ADD                      (0x0000000EU)
-#define PKA_MODE_MODULAR_SUB                      (0x0000000FU)
-#define PKA_MODE_MONTGOMERY_MUL                   (0x00000010U)
-/**
-  * @}
-  */
-
-/** @defgroup PKA_Interrupt_configuration_definition PKA Interrupt configuration definition
-  * @brief PKA Interrupt definition
-  * @{
-  */
-#define PKA_IT_PROCEND                            PKA_CR_PROCENDIE
-#define PKA_IT_ADDRERR                            PKA_CR_ADDRERRIE
-#define PKA_IT_RAMERR                             PKA_CR_RAMERRIE
-
-/**
-  * @}
-  */
-
-/** @defgroup PKA_Flag_definition PKA Flag definition
-  * @{
-  */
-#define PKA_FLAG_PROCEND                          PKA_SR_PROCENDF
-#define PKA_FLAG_ADDRERR                          PKA_SR_ADDRERRF
-#define PKA_FLAG_RAMERR                           PKA_SR_RAMERRF
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup PKA_Exported_Macros PKA Exported Macros
-  * @{
-  */
-
-/** @brief  Reset PKA handle state.
-  * @param  __HANDLE__ specifies the PKA Handle
-  * @retval None
-  */
-#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
-#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \
-                                                                    (__HANDLE__)->State = HAL_PKA_STATE_RESET;       \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                                  } while(0)
-#else
-#define __HAL_PKA_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_PKA_STATE_RESET)
-#endif
-
-/** @brief  Enable the specified PKA interrupt.
-  * @param  __HANDLE__ specifies the PKA Handle
-  * @param  __INTERRUPT__ specifies the interrupt source to enable.
-  *        This parameter can be one of the following values:
-  *            @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
-  *            @arg @ref PKA_IT_ADDRERR Address error interrupt enable
-  *            @arg @ref PKA_IT_RAMERR RAM error interrupt enable
-  * @retval None
-  */
-#define __HAL_PKA_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/** @brief  Disable the specified PKA interrupt.
-  * @param  __HANDLE__ specifies the PKA Handle
-  * @param  __INTERRUPT__ specifies the interrupt source to disable.
-  *        This parameter can be one of the following values:
-  *            @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
-  *            @arg @ref PKA_IT_ADDRERR Address error interrupt enable
-  *            @arg @ref PKA_IT_RAMERR RAM error interrupt enable
-  * @retval None
-  */
-#define __HAL_PKA_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= (~(__INTERRUPT__)))
-
-/** @brief  Check whether the specified PKA interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the PKA Handle
-  * @param  __INTERRUPT__ specifies the PKA interrupt source to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref PKA_IT_PROCEND End Of Operation interrupt enable
-  *            @arg @ref PKA_IT_ADDRERR Address error interrupt enable
-  *            @arg @ref PKA_IT_RAMERR RAM error interrupt enable
-  * @retval The new state of __INTERRUPT__ (SET or RESET)
-  */
-#define __HAL_PKA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified PKA flag is set or not.
-  * @param  __HANDLE__ specifies the PKA Handle
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref PKA_FLAG_PROCEND End Of Operation
-  *            @arg @ref PKA_FLAG_ADDRERR Address error
-  *            @arg @ref PKA_FLAG_RAMERR RAM error
-  * @retval The new state of __FLAG__ (SET or RESET)
-  */
-#define __HAL_PKA_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
-
-/** @brief  Clear the PKA pending flags which are cleared by writing 1 in a specific bit.
-  * @param  __HANDLE__ specifies the PKA Handle
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref PKA_FLAG_PROCEND End Of Operation
-  *            @arg @ref PKA_FLAG_ADDRERR Address error
-  *            @arg @ref PKA_FLAG_RAMERR RAM error
-  * @retval None
-  */
-#define __HAL_PKA_CLEAR_FLAG(__HANDLE__, __FLAG__)              ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
-
-/** @brief  Enable the specified PKA peripheral.
-  * @param  __HANDLE__ specifies the PKA Handle
-  * @retval None
-  */
-#define __HAL_PKA_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR,  PKA_CR_EN))
-
-/** @brief  Disable the specified PKA peripheral.
-  * @param  __HANDLE__ specifies the PKA Handle
-  * @retval None
-  */
-#define __HAL_PKA_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR, PKA_CR_EN))
-
-/** @brief  Start a PKA operation.
-  * @param  __HANDLE__ specifies the PKA Handle
-  * @retval None
-  */
-#define __HAL_PKA_START(__HANDLE__)                             (SET_BIT((__HANDLE__)->Instance->CR,  PKA_CR_START))
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PKA_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup PKA_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_PKA_Init(PKA_HandleTypeDef *hpka);
-HAL_StatusTypeDef HAL_PKA_DeInit(PKA_HandleTypeDef *hpka);
-void              HAL_PKA_MspInit(PKA_HandleTypeDef *hpka);
-void              HAL_PKA_MspDeInit(PKA_HandleTypeDef *hpka);
-
-#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_PKA_RegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID, pPKA_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup PKA_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-/* High Level Functions *******************************************************/
-HAL_StatusTypeDef HAL_PKA_ModExp(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_ModExp_IT(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in);
-HAL_StatusTypeDef HAL_PKA_ModExpFastMode(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef *in);
-void HAL_PKA_ModExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes);
-
-HAL_StatusTypeDef HAL_PKA_ECDSASign(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in);
-void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt);
-
-HAL_StatusTypeDef HAL_PKA_ECDSAVerif(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_ECDSAVerif_IT(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in);
-uint32_t HAL_PKA_ECDSAVerif_IsValidSignature(PKA_HandleTypeDef const *const hpka);
-
-HAL_StatusTypeDef HAL_PKA_RSACRTExp(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_RSACRTExp_IT(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in);
-void HAL_PKA_RSACRTExp_GetResult(PKA_HandleTypeDef *hpka, uint8_t *pRes);
-
-HAL_StatusTypeDef HAL_PKA_PointCheck(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in);
-uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka);
-
-HAL_StatusTypeDef HAL_PKA_ECCMul(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in);
-HAL_StatusTypeDef HAL_PKA_ECCMulFastMode(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_ECCMulFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef *in);
-void HAL_PKA_ECCMul_GetResult(PKA_HandleTypeDef *hpka, PKA_ECCMulOutTypeDef *out);
-
-HAL_StatusTypeDef HAL_PKA_Add(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_Add_IT(PKA_HandleTypeDef *hpka, PKA_AddInTypeDef *in);
-HAL_StatusTypeDef HAL_PKA_Sub(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_Sub_IT(PKA_HandleTypeDef *hpka, PKA_SubInTypeDef *in);
-HAL_StatusTypeDef HAL_PKA_Cmp(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_Cmp_IT(PKA_HandleTypeDef *hpka, PKA_CmpInTypeDef *in);
-HAL_StatusTypeDef HAL_PKA_Mul(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_Mul_IT(PKA_HandleTypeDef *hpka, PKA_MulInTypeDef *in);
-HAL_StatusTypeDef HAL_PKA_ModAdd(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_ModAdd_IT(PKA_HandleTypeDef *hpka, PKA_ModAddInTypeDef *in);
-HAL_StatusTypeDef HAL_PKA_ModSub(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_ModSub_IT(PKA_HandleTypeDef *hpka, PKA_ModSubInTypeDef *in);
-HAL_StatusTypeDef HAL_PKA_ModInv(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_ModInv_IT(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in);
-HAL_StatusTypeDef HAL_PKA_ModRed(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_ModRed_IT(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in);
-HAL_StatusTypeDef HAL_PKA_MontgomeryMul(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_MontgomeryMul_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryMulInTypeDef *in);
-void HAL_PKA_Arithmetic_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
-
-HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in, uint32_t Timeout);
-HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in);
-void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
-
-
-HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka);
-void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka);
-void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka);
-void HAL_PKA_ErrorCallback(PKA_HandleTypeDef *hpka);
-void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka);
-/**
-  * @}
-  */
-
-/** @addtogroup PKA_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka);
-uint32_t             HAL_PKA_GetError(PKA_HandleTypeDef *hpka);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(PKA) && defined(HAL_PKA_MODULE_ENABLED) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_PKA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h

@@ -1,585 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_pwr.h
-  * @author  MCD Application Team
-  * @brief   Header file of PWR HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_PWR_H
-#define STM32WLxx_HAL_PWR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/* Include low level driver */
-#include "stm32wlxx_ll_pwr.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWR PWR
-  * @brief PWR HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup PWR_Exported_Types PWR Exported Types
-  * @{
-  */
-
-/**
-  * @brief  PWR PVD configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PVDLevel;       /*!< PVDLevel: Specifies the PVD detection level.
-                                This parameter can be a value of @ref PWR_PVD_detection_level. */
-
-  uint32_t Mode;           /*!< Mode: Specifies the operating mode for the selected pins.
-                                This parameter can be a value of @ref PWR_PVD_Mode. */
-} PWR_PVDTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
-  * @{
-  */
-
-/** @defgroup PWR_PVD_detection_level  Power Voltage Detector Level selection
-  * @note     Refer datasheet for selection voltage value
-  * @{
-  */
-#define PWR_PVDLEVEL_0                      (0x00000000UL)                                   /*!< PVD threshold around 2.0 V */
-#define PWR_PVDLEVEL_1                      (                                PWR_CR2_PLS_0)  /*!< PVD threshold around 2.2 V */
-#define PWR_PVDLEVEL_2                      (                PWR_CR2_PLS_1                )  /*!< PVD threshold around 2.4 V */
-#define PWR_PVDLEVEL_3                      (                PWR_CR2_PLS_1 | PWR_CR2_PLS_0)  /*!< PVD threshold around 2.5 V */
-#define PWR_PVDLEVEL_4                      (PWR_CR2_PLS_2                                )  /*!< PVD threshold around 2.6 V */
-#define PWR_PVDLEVEL_5                      (PWR_CR2_PLS_2                 | PWR_CR2_PLS_0)  /*!< PVD threshold around 2.8 V */
-#define PWR_PVDLEVEL_6                      (PWR_CR2_PLS_2 | PWR_CR2_PLS_1                )  /*!< PVD threshold around 2.9 V */
-#define PWR_PVDLEVEL_7                      (PWR_CR2_PLS_2 | PWR_CR2_PLS_1 | PWR_CR2_PLS_0)  /*!< External input analog voltage (compared internally to VREFINT) */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_PVD_Mode  PWR PVD interrupt and event mode
-  * @{
-  */
-/* Note: On STM32WL series, power PVD event is not available on EXTI lines     */
-/*       (only interruption is available through EXTI line 16).               */
-#define PWR_PVD_MODE_NORMAL                 (0x00000000UL)                          /*!< PVD in polling mode (PVD flag update without interruption) */
-
-#define PWR_PVD_MODE_IT_RISING              (PVD_MODE_IT | PVD_RISING_EDGE)         /*!< PVD in interrupt mode with rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING             (PVD_MODE_IT | PVD_FALLING_EDGE)        /*!< PVD in interrupt mode with falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING      (PVD_MODE_IT | PVD_RISING_FALLING_EDGE) /*!< PVD in interrupt mode with rising/falling edge trigger detection */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Low_Power_Mode_Selection  PWR Low Power Mode Selection
-  * @{
-  */
-#ifdef CORE_CM0PLUS
-#define PWR_LOWPOWERMODE_STOP0              (0x00000000UL)                        /*!< Stop 0: Stop mode with main regulator */
-#define PWR_LOWPOWERMODE_STOP1              (PWR_C2CR1_LPMS_0)                    /*!< Stop 1: Stop mode with low power regulator */
-#define PWR_LOWPOWERMODE_STOP2              (PWR_C2CR1_LPMS_1)                    /*!< Stop 2: Stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)*/
-#define PWR_LOWPOWERMODE_STANDBY            (PWR_C2CR1_LPMS_0 | PWR_C2CR1_LPMS_1) /*!< Standby mode */
-#define PWR_LOWPOWERMODE_SHUTDOWN           (PWR_C2CR1_LPMS_2 | PWR_C2CR1_LPMS_1 | PWR_C2CR1_LPMS_0) /*!< Shutdown mode */
-#else
-#define PWR_LOWPOWERMODE_STOP0              (0x00000000UL)                        /*!< Stop 0: Stop mode with main regulator */
-#define PWR_LOWPOWERMODE_STOP1              (PWR_CR1_LPMS_0)                      /*!< Stop 1: Stop mode with low power regulator */
-#define PWR_LOWPOWERMODE_STOP2              (PWR_CR1_LPMS_1)                      /*!< Stop 2: Stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)*/
-#define PWR_LOWPOWERMODE_STANDBY            (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)     /*!< Standby mode */
-#define PWR_LOWPOWERMODE_SHUTDOWN           (PWR_CR1_LPMS_2 | PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0) /*!< Shutdown mode */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode  PWR regulator mode
-  * @{
-  */
-#define PWR_MAINREGULATOR_ON                (0x00000000UL)              /*!< Regulator in main mode      */
-#define PWR_LOWPOWERREGULATOR_ON            (PWR_CR1_LPR)               /*!< Regulator in low-power mode */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_SLEEP_mode_entry  PWR SLEEP mode entry
-  * @{
-  */
-#define PWR_SLEEPENTRY_WFI                  ((uint8_t)0x01)         /*!< Wait For Interruption instruction to enter Sleep mode */
-#define PWR_SLEEPENTRY_WFE                  ((uint8_t)0x02)         /*!< Wait For Event instruction to enter Sleep mode        */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_STOP_mode_entry  PWR STOP mode entry
-  * @{
-  */
-#define PWR_STOPENTRY_WFI                   ((uint8_t)0x01)         /*!< Wait For Interruption instruction to enter Stop mode */
-#define PWR_STOPENTRY_WFE                   ((uint8_t)0x02)         /*!< Wait For Event instruction to enter Stop mode        */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PWR_Private_Constants PWR Private Constants
-  * @{
-  */
-
-/** @defgroup PWR_PVD_EXTI_LINE  PWR PVD external interrupt line
-  * @{
-  */
-#define PWR_EXTI_LINE_PVD                   (LL_EXTI_LINE_16)   /*!< External interrupt line 16 Connected to the PWR PVD */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
-  * @{
-  */
-/* Note: On STM32WL series, power PVD event is not available on EXTI lines     */
-/*       (only interruption is available through EXTI line 16).               */
-#define PVD_MODE_IT                         (0x00010000UL)  /*!< Mask for interruption yielded by PVD threshold crossing */
-#define PVD_RISING_EDGE                     (0x00000001UL)  /*!< Mask for rising edge set as PVD trigger                 */
-#define PVD_FALLING_EDGE                    (0x00000002UL)  /*!< Mask for falling edge set as PVD trigger                */
-#define PVD_RISING_FALLING_EDGE             (0x00000003UL)  /*!< Mask for rising and falling edges set as PVD trigger    */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macros  PWR Exported Macros
-  * @{
-  */
-#if defined(DUAL_CORE)
-/** @brief  Check whether or not a specific PWR flag is set.
-  * @param __FLAG__ specifies the flag to check.
-  *           This parameter can be one of the following values:
-  *
-  *            /--------------------------------SR1-------------------------------/
-  *            @arg @ref PWR_FLAG_WUF1  Wake Up Flag 1. Indicates that a wakeup event
-  *                                     was received from the WKUP pin 1.
-  *            @arg @ref PWR_FLAG_WUF2  Wake Up Flag 2. Indicates that a wakeup event
-  *                                     was received from the WKUP pin 2.
-  *            @arg @ref PWR_FLAG_WUF3  Wake Up Flag 3. Indicates that a wakeup event
-  *                                     was received from the WKUP pin 3.
-  *
-  *            @arg @ref PWR_FLAG_WPVD      Wakeup PVD flag
-  *
-  *            @arg @ref PWR_FLAG_HOLDC2I   CPU2 on-Hold Interrupt Flag
-  *            @arg @ref PWR_FLAG_WUFI      Wake-Up Flag Internal. Set when a wakeup is detected on
-  *                                         the internal wakeup line.
-  *
-  *            @arg @ref PWR_FLAG_WRFBUSY   Wake-up radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software)
-  *
-  *            /--------------------------------SR2-------------------------------/
-  *            @arg @ref PWR_FLAG_LDORDY   Main LDO ready flag
-  *            @arg @ref PWR_FLAG_SMPSRDY  SMPS ready Flag
-  *
-  *            @arg @ref PWR_FLAG_REGLPS Low-power Regulator 1 started: Indicates whether the regulator
-  *                                      is ready after a power-on reset or a Standby/Shutdown.
-  *            @arg @ref PWR_FLAG_REGLPF Low-power Regulator 1 flag: Indicates whether the
-  *                                      regulator 1 is in main mode or is in low-power mode.
-  *
-  *            @arg @ref PWR_FLAG_REGMRS Low-power regulator (main regulator or low-power regulator used) flag.
-  *
-  *            @arg @ref PWR_FLAG_FLASHRDY Flash ready flag
-  *
-  *            @arg @ref PWR_FLAG_VOSF   Voltage Scaling Flag. Indicates whether the regulator is ready
-  *                                      in the selected voltage range or is still changing to the required voltage level.
-  *            @arg @ref PWR_FLAG_PVDO   Power Voltage Detector Output. Indicates whether VDD voltage is below
-  *                                      or above the selected PVD threshold.
-  *
-  *            @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
-  *                                     is below or above PVM3 threshold.
-  *
-  *            @arg @ref PWR_FLAG_RFEOL Indicate whether supply voltage is below radio operating level (radio "end of life").
-  *
-  *            @arg @ref PWR_FLAG_RFBUSYS  Radio busy signal flag (current status).
-  *            @arg @ref PWR_FLAG_RFBUSYMS Radio busy masked signal flag (current status).
-  *
-  *            @arg @ref PWR_FLAG_C2BOOTS  CPU2 boot request source information flag.
-  *
-  *            /----------------------------EXTSCR--------------------------/
-  *            @arg @ref PWR_FLAG_STOP      System Stop 0 or Stop1 Flag for CPU1.
-  *            @arg @ref PWR_FLAG_STOP2     System Stop 2 Flag for CPU1.
-  *            @arg @ref PWR_FLAG_SB        System Standby Flag for CPU1.
-  *
-  *            @arg @ref PWR_FLAG_C2STOP    System Stop 0 or Stop1 Flag for CPU2.
-  *            @arg @ref PWR_FLAG_C2STOP2   System Stop 2 Flag for CPU2.
-  *            @arg @ref PWR_FLAG_C2SB      System Standby Flag for CPU2.
-  *
-  *            @arg @ref PWR_FLAG_C1DEEPSLEEP       CPU1 DeepSleep Flag.
-  *            @arg @ref PWR_FLAG_C2DEEPSLEEP       CPU2 DeepSleep Flag.
-  *
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#else
-/** @brief  Check whether or not a specific PWR flag is set.
-  * @param __FLAG__ specifies the flag to check.
-  *           This parameter can be one of the following values:
-  *
-  *            /--------------------------------SR1-------------------------------/
-  *            @arg @ref PWR_FLAG_WUF1  Wake Up Flag 1. Indicates that a wakeup event
-  *                                     was received from the WKUP pin 1.
-  *            @arg @ref PWR_FLAG_WUF2  Wake Up Flag 2. Indicates that a wakeup event
-  *                                     was received from the WKUP pin 2.
-  *            @arg @ref PWR_FLAG_WUF3  Wake Up Flag 3. Indicates that a wakeup event
-  *                                     was received from the WKUP pin 3.
-  *
-  *            @arg @ref PWR_FLAG_WPVD      Wakeup PVD flag
-  *
-  *            @arg @ref PWR_FLAG_WUFI      Wake-Up Flag Internal. Set when a wakeup is detected on
-  *                                         the internal wakeup line.
-  *
-  *            @arg @ref PWR_FLAG_WRFBUSY   Wake-up radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software)
-  *
-  *            /--------------------------------SR2-------------------------------/
-  *            @arg @ref PWR_FLAG_LDORDY   Main LDO ready flag
-  *            @arg @ref PWR_FLAG_SMPSRDY  SMPS ready Flag
-  *
-  *            @arg @ref PWR_FLAG_REGLPS Low-power Regulator 1 started: Indicates whether the regulator
-  *                                      is ready after a power-on reset or a Standby/Shutdown.
-  *            @arg @ref PWR_FLAG_REGLPF Low-power Regulator 1 flag: Indicates whether the
-  *                                      regulator 1 is in main mode or is in low-power mode.
-  *
-  *            @arg @ref PWR_FLAG_REGMRS Low-power regulator (main regulator or low-power regulator used) flag.
-  *
-  *            @arg @ref PWR_FLAG_FLASHRDY Flash ready flag
-  *
-  *            @arg @ref PWR_FLAG_VOSF   Voltage Scaling Flag. Indicates whether the regulator is ready
-  *                                      in the selected voltage range or is still changing to the required voltage level.
-  *            @arg @ref PWR_FLAG_PVDO   Power Voltage Detector Output. Indicates whether VDD voltage is below
-  *                                      or above the selected PVD threshold.
-  *
-  *            @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
-  *                                     is below or above PVM3 threshold.
-  *
-  *            @arg @ref PWR_FLAG_RFEOL Indicate whether supply voltage is below radio operating level (radio "end of life").
-  *
-  *            @arg @ref PWR_FLAG_RFBUSYS  Radio busy signal flag (current status).
-  *            @arg @ref PWR_FLAG_RFBUSYMS Radio busy masked signal flag (current status).
-  *
-  *            /----------------------------EXTSCR--------------------------/
-  *            @arg @ref PWR_FLAG_STOP      System Stop 0 or Stop1 Flag for CPU1.
-  *            @arg @ref PWR_FLAG_STOP2     System Stop 2 Flag for CPU1.
-  *            @arg @ref PWR_FLAG_SB        System Standby Flag for CPU1.
-  *
-  *            @arg @ref PWR_FLAG_C1DEEPSLEEP       CPU1 DeepSleep Flag.
-  *
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#endif
-#define __HAL_PWR_GET_FLAG(__FLAG__)  ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR1) ?   \
-                                       (                                                          \
-                                        PWR->SR1 & (1UL << ((__FLAG__) & 31UL))                   \
-                                       )                                                          \
-                                       :                                                          \
-                                       (                                                          \
-                                        (((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR2) ? \
-                                        (                                                        \
-                                         PWR->SR2 & (1UL << ((__FLAG__) & 31UL))                 \
-                                        )                                                        \
-                                        :                                                        \
-                                        (                                                        \
-                                         PWR->EXTSCR & (1UL << ((__FLAG__) & 31UL))              \
-                                        )                                                        \
-                                       )                                                          \
-                                      )
-
-#if defined(DUAL_CORE)
-/** @brief  Clear a specific PWR flag.
-  * @note   Clearing of flags {PWR_FLAG_STOP, PWR_FLAG_STOP2, PWR_FLAG_SB}
-  *         and flags {PWR_FLAG_C2STOP, PWR_FLAG_C2SB} are grouped:
-  *         clearing of one flag also clears the other ones.
-  * @param __FLAG__ specifies the flag to clear.
-  *          This parameter can be one of the following values:
-  *
-  *            /--------------------------------SCR (SRR)------------------------------/
-  *            @arg @ref PWR_FLAG_WU    Wake Up Flag of all pins.
-  *            @arg @ref PWR_FLAG_WUF1  Wake Up Flag 1. Indicates that a wakeup event
-  *                                     was received from the WKUP pin 1.
-  *            @arg @ref PWR_FLAG_WUF2  Wake Up Flag 2. Indicates that a wakeup event
-  *                                     was received from the WKUP pin 2.
-  *            @arg @ref PWR_FLAG_WUF3  Wake Up Flag 3. Indicates that a wakeup event
-  *                                     was received from the WKUP pin 3.
-  *
-  *            @arg @ref PWR_FLAG_WPVD      Wakeup PVD flag
-  *
-  *            @arg @ref PWR_FLAG_HOLDC2I   CPU2 on-Hold Interrupt Flag
-  *
-  *            @arg @ref PWR_FLAG_WRFBUSY   Wake-up radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software)
-  *
-  *            /----------------------------EXTSCR--------------------------/
-  *            @arg @ref PWR_FLAG_LPMODES   System Standby Flag for CPU1.
-  *            @arg @ref PWR_FLAG_C2LPMODES System Standby Flag for CPU2.
-  *
-  * @retval None
-  */
-#else
-/** @brief  Clear a specific PWR flag.
-  * @note   Clearing of flags {PWR_FLAG_STOP, PWR_FLAG_STOP2, PWR_FLAG_SB}
-  *         are grouped:
-  *         clearing of one flag also clears the other ones.
-  * @param __FLAG__ specifies the flag to clear.
-  *          This parameter can be one of the following values:
-  *
-  *            /--------------------------------SCR (SRR)------------------------------/
-  *            @arg @ref PWR_FLAG_WU    Wake Up Flag of all pins.
-  *            @arg @ref PWR_FLAG_WUF1  Wake Up Flag 1. Indicates that a wakeup event
-  *                                     was received from the WKUP pin 1.
-  *            @arg @ref PWR_FLAG_WUF2  Wake Up Flag 2. Indicates that a wakeup event
-  *                                     was received from the WKUP pin 2.
-  *            @arg @ref PWR_FLAG_WUF3  Wake Up Flag 3. Indicates that a wakeup event
-  *                                     was received from the WKUP pin 3.
-  *
-  *            @arg @ref PWR_FLAG_WPVD      Wakeup PVD flag
-  *
-  *            @arg @ref PWR_FLAG_WRFBUSY   Wake-up radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software)
-  *
-  *            /----------------------------EXTSCR--------------------------/
-  *            @arg @ref PWR_FLAG_LPMODES   System Standby Flag for CPU1.
-  *
-  * @retval None
-  */
-#endif
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__)   ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_EXTSCR) ?                                  \
-                                          (                                                                                            \
-                                           PWR->EXTSCR = (1UL << (((__FLAG__) & PWR_FLAG_EXTSCR_CLR_MASK) >> PWR_FLAG_EXTSCR_CLR_POS)) \
-                                          )                                                                                            \
-                                          :                                                                                            \
-                                          (                                                                                            \
-                                           (((__FLAG__)) == PWR_FLAG_WU) ?                                                             \
-                                           (PWR->SCR = PWR_SCR_CWUF) :                                                                 \
-                                           (PWR->SCR = (1UL << ((__FLAG__) & 31UL)))                                                   \
-                                          )                                                                                            \
-                                         )
-
-/**
-  * @brief Enable the PVD Extended Interrupt line.
-  * @retval None
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT()      LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)
-#else
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT()      LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD)
-#endif
-
-/**
-  * @brief Disable the PVD Extended Interrupt line.
-  * @retval None
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT()     LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)
-#else
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT()     LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD)
-#endif
-
-/* Note: On STM32WL series, power PVD event is not available on EXTI lines     */
-/*       (only interruption is available through EXTI line 16).               */
-
-/**
-  * @brief Enable the PVD Extended Interrupt Rising Trigger.
-  * @note  PVD flag polarity is inverted compared to EXTI line, therefore
-  *        EXTI rising and falling logic edges are inverted versus PVD voltage edges.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableFallingTrig_0_31(PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising Trigger.
-  * @note  PVD flag polarity is inverted compared to EXTI line, therefore
-  *        EXTI rising and falling logic edges are inverted versus PVD voltage edges.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableFallingTrig_0_31(PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Enable the PVD Extended Interrupt Falling Trigger.
-  * @note  PVD flag polarity is inverted compared to EXTI line, therefore
-  *        EXTI rising and falling logic edges are inverted versus PVD voltage edges.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableRisingTrig_0_31(PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Falling Trigger.
-  * @note  PVD flag polarity is inverted compared to EXTI line, therefore
-  *        EXTI rising and falling logic edges are inverted versus PVD voltage edges.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableRisingTrig_0_31(PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief  Enable the PVD Extended Interrupt Rising & Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()  \
-  do {                                                   \
-    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
-    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
-  } while(0)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \
-  do {                                                    \
-    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
-    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
-  } while(0)
-
-/**
-  * @brief  Generate a Software interrupt on selected EXTI line.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT()  LL_EXTI_GenerateSWI_0_31(PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Check whether or not the PVD EXTI interrupt flag is set.
-  * @retval EXTI PVD Line Status.
-  */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG()       LL_EXTI_ReadFlag_0_31(PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Clear the PVD EXTI interrupt flag.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()     LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVD)
-
-/**
-  * @}
-  */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup PWR_Private_Macros  PWR Private Macros
-  * @{
-  */
-#define IS_PWR_PVD_LEVEL(__LEVEL__) (((__LEVEL__) == PWR_PVDLEVEL_0) || ((__LEVEL__) == PWR_PVDLEVEL_1)|| \
-                                     ((__LEVEL__) == PWR_PVDLEVEL_2) || ((__LEVEL__) == PWR_PVDLEVEL_3)|| \
-                                     ((__LEVEL__) == PWR_PVDLEVEL_4) || ((__LEVEL__) == PWR_PVDLEVEL_5)|| \
-                                     ((__LEVEL__) == PWR_PVDLEVEL_6) || ((__LEVEL__) == PWR_PVDLEVEL_7))
-
-#define IS_PWR_PVD_MODE(__MODE__)  (((__MODE__) == PWR_PVD_MODE_NORMAL)              ||\
-                                    ((__MODE__) == PWR_PVD_MODE_IT_RISING)           ||\
-                                    ((__MODE__) == PWR_PVD_MODE_IT_FALLING)          ||\
-                                    ((__MODE__) == PWR_PVD_MODE_IT_RISING_FALLING))
-
-#define IS_PWR_REGULATOR(__REGULATOR__)           (((__REGULATOR__) == PWR_MAINREGULATOR_ON)    || \
-                                                   ((__REGULATOR__) == PWR_LOWPOWERREGULATOR_ON))
-
-#define IS_PWR_SLEEP_ENTRY(__ENTRY__)             (((__ENTRY__) == PWR_SLEEPENTRY_WFI) || \
-                                                   ((__ENTRY__) == PWR_SLEEPENTRY_WFE))
-
-#define IS_PWR_STOP_ENTRY(__ENTRY__)              (((__ENTRY__) == PWR_STOPENTRY_WFI) || \
-                                                   ((__ENTRY__) == PWR_STOPENTRY_WFE))
-/**
-  * @}
-  */
-
-/* Include PWR HAL Extended module */
-#include "stm32wlxx_hal_pwr_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PWR_Exported_Functions  PWR Exported Functions
-  * @{
-  */
-
-/** @defgroup PWR_Exported_Functions_Group1  Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions *******************************/
-void              HAL_PWR_DeInit(void);
-
-void              HAL_PWR_EnableBkUpAccess(void);
-void              HAL_PWR_DisableBkUpAccess(void);
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Exported_Functions_Group2  Peripheral Control functions
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-void              HAL_PWR_EnablePVD(void);
-void              HAL_PWR_DisablePVD(void);
-
-/* WakeUp pins configuration functions ****************************************/
-void              HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
-void              HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes configuration functions ************************************/
-void              HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void              HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void              HAL_PWR_EnterSTANDBYMode(void);
-
-void              HAL_PWR_EnableSleepOnExit(void);
-void              HAL_PWR_DisableSleepOnExit(void);
-
-void              HAL_PWR_EnableSEVOnPend(void);
-void              HAL_PWR_DisableSEVOnPend(void);
-
-void              HAL_PWR_PVDCallback(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32WLxx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h

@@ -1,654 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_pwr_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of PWR HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_PWR_EX_H
-#define STM32WLxx_HAL_PWR_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWREx PWREx
-  * @brief PWR Extended HAL module driver
-  * @{
-  */
-
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
-  * @{
-  */
-
-/**
-  * @brief  PWR PVM configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold.
-                           This parameter can be a value of @ref PWREx_PVM_Type.
-                           @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V.
-                           */
-  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref PWREx_PVM_Mode. */
-} PWR_PVMTypeDef;
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PWREx_Private_Constants PWR Extended Private Constants
-  * @{
-  */
-#define PWR_WUP_POLARITY_SHIFT                  0x05   /*!< Internal constant used to retrieve wakeup pin polarity */
-
-/** @defgroup PWR_FLAG_REG PWR flag register
-  * @{
-  */
-#define PWR_FLAG_REG_SR1         (0x20UL)   /* Bitfield to indicate PWR flag located in register PWR_SR1 */
-#define PWR_FLAG_REG_SR2         (0x40UL)   /* Bitfield to indicate PWR flag located in register PWR_SR2 */
-#define PWR_FLAG_REG_EXTSCR      (0x60UL)   /* Bitfield to indicate PWR flag located in register PWR_EXTSCR */
-#define PWR_FLAG_REG_MASK_POS    (5UL)      /* Bitfield mask position to indicate PWR flag location in PWR register */
-#define PWR_FLAG_REG_MASK        (PWR_FLAG_REG_SR1 | PWR_FLAG_REG_SR2 | PWR_FLAG_REG_EXTSCR)   /* Bitfield mask to indicate PWR flag location in PWR register */
-#define PWR_FLAG_EXTSCR_CLR_POS  (16UL)     /* Bitfield for register PWR_EXTSCR clearable bits positions: position of bitfield in flag literals */
-#if defined(DUAL_CORE)
-#define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos | PWR_EXTSCR_C2CSSF_Pos) << PWR_FLAG_EXTSCR_CLR_POS)  /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */
-#else
-#define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos) << PWR_FLAG_EXTSCR_CLR_POS)  /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask
-  * @{
-  */
-/* Note: On STM32WL series, power PVD event is not available on EXTI lines     */
-/*       (only interruption is available through EXTI line 16).               */
-#define PVM_MODE_IT                         (0x00010000UL)  /*!< Mask for interruption yielded by PVM threshold crossing */
-#define PVM_RISING_EDGE                     (0x00000001UL)  /*!< Mask for rising edge set as PVM trigger */
-#define PVM_FALLING_EDGE                    (0x00000002UL)  /*!< Mask for falling edge set as PVM trigger */
-#define PVM_RISING_FALLING_EDGE             (0x00000003UL)  /*!< Mask for rising and falling edges set as PVM trigger */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Constants  PWR Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup PWREx_WakeUp_Pins  PWR wake-up pins
-  * @{
-  */
-#define PWR_WAKEUP_PIN1_HIGH                PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
-#define PWR_WAKEUP_PIN2_HIGH                PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
-#define PWR_WAKEUP_PIN3_HIGH                PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
-
-#define PWR_WAKEUP_PIN1_LOW                 ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
-#define PWR_WAKEUP_PIN2_LOW                 ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
-#define PWR_WAKEUP_PIN3_LOW                 ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
-/**
-  * @}
-  */
-
-/* Literals kept for legacy purpose */
-#define PWR_WAKEUP_PIN1                     PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
-#define PWR_WAKEUP_PIN2                     PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
-#define PWR_WAKEUP_PIN3                     PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
-
-/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
-  * @{
-  */
-#define PWR_PVM_3                           PWR_CR2_PVME3  /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_PVM_Mode  PWR PVM interrupt and event mode
-  * @{
-  */
-/* Note: On STM32WL series, power PVM event is not available on EXTI lines     */
-/*       (only interruption is available through EXTI line 34).               */
-#define PWR_PVM_MODE_NORMAL                 (0x00000000UL)                              /*!< basic mode is used */
-
-#define PWR_PVM_MODE_IT_RISING              (PVM_MODE_IT | PVM_RISING_EDGE)             /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVM_MODE_IT_FALLING             (PVM_MODE_IT | PVM_FALLING_EDGE)            /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVM_MODE_IT_RISING_FALLING      (PVM_MODE_IT | PVM_RISING_FALLING_EDGE)     /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_Flash_PowerDown  Flash Power Down modes
-  * @{
-  */
-#define PWR_FLASHPD_LPRUN                   PWR_CR1_FPDR     /*!< Enable Flash power down in low power run mode */
-#define PWR_FLASHPD_LPSLEEP                 PWR_CR1_FPDS     /*!< Enable Flash power down in low power sleep mode */
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_Regulator_Voltage_Scale  PWR Regulator voltage scale
-  * @{
-  */
-#define PWR_REGULATOR_VOLTAGE_SCALE1        PWR_CR1_VOS_0     /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */
-#define PWR_REGULATOR_VOLTAGE_SCALE2        PWR_CR1_VOS_1     /*!< Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz */
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
-  * @{
-  */
-#define PWR_BATTERY_CHARGING_RESISTOR_5     (0x00000000UL)         /*!< VBAT charging through a 5 kOhms resistor   */
-#define PWR_BATTERY_CHARGING_RESISTOR_1_5   PWR_CR4_VBRS           /*!< VBAT charging through a 1.5 kOhms resistor */
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
-  * @{
-  */
-#define PWR_BATTERY_CHARGING_DISABLE        (0x00000000UL)
-#define PWR_BATTERY_CHARGING_ENABLE         PWR_CR4_VBE
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
-  * @{
-  */
-#define PWR_GPIO_BIT_0                      PWR_PUCRB_PB0    /*!< GPIO port I/O pin 0  */
-#define PWR_GPIO_BIT_1                      PWR_PUCRB_PB1    /*!< GPIO port I/O pin 1  */
-#define PWR_GPIO_BIT_2                      PWR_PUCRB_PB2    /*!< GPIO port I/O pin 2  */
-#define PWR_GPIO_BIT_3                      PWR_PUCRB_PB3    /*!< GPIO port I/O pin 3  */
-#define PWR_GPIO_BIT_4                      PWR_PUCRB_PB4    /*!< GPIO port I/O pin 4  */
-#define PWR_GPIO_BIT_5                      PWR_PUCRB_PB5    /*!< GPIO port I/O pin 5  */
-#define PWR_GPIO_BIT_6                      PWR_PUCRB_PB6    /*!< GPIO port I/O pin 6  */
-#define PWR_GPIO_BIT_7                      PWR_PUCRB_PB7    /*!< GPIO port I/O pin 7  */
-#define PWR_GPIO_BIT_8                      PWR_PUCRB_PB8    /*!< GPIO port I/O pin 8  */
-#define PWR_GPIO_BIT_9                      PWR_PUCRB_PB9    /*!< GPIO port I/O pin 9  */
-#define PWR_GPIO_BIT_10                     PWR_PUCRB_PB10   /*!< GPIO port I/O pin 10 */
-#define PWR_GPIO_BIT_11                     PWR_PUCRB_PB11   /*!< GPIO port I/O pin 11 */
-#define PWR_GPIO_BIT_12                     PWR_PUCRB_PB12   /*!< GPIO port I/O pin 12 */
-#define PWR_GPIO_BIT_13                     PWR_PUCRB_PB13   /*!< GPIO port I/O pin 14 */
-#define PWR_GPIO_BIT_14                     PWR_PDCRB_PB14   /*!< GPIO port I/O pin 14 */
-#define PWR_GPIO_BIT_15                     PWR_PUCRB_PB15   /*!< GPIO port I/O pin 15 */
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_GPIO GPIO port
-  * @{
-  */
-#define PWR_GPIO_A                          (0x00000000UL)      /*!< GPIO port A */
-#define PWR_GPIO_B                          (0x00000001UL)      /*!< GPIO port B */
-#define PWR_GPIO_C                          (0x00000002UL)      /*!< GPIO port C */
-#define PWR_GPIO_H                          (0x00000007UL)      /*!< GPIO port H */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_EC_EOL_OPERATING_MODES Monitoring of supply voltage for radio operating level (radio End Of Life)
-  * @{
-  */
-#define PWR_RADIO_EOL_DISABLE               (0x00000000UL)    /*!< Monitoring of supply voltage for radio operating level (radio End Of Life) disable */
-#define PWR_RADIO_EOL_ENABLE                (PWR_CR5_RFEOLEN) /*!< Monitoring of supply voltage for radio operating level (radio End Of Life) enable */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_EC_SMPS_OPERATING_MODES SMPS Step down converter operating modes
-  * @{
-  */
-#define PWR_SMPS_BYPASS                     (0x00000000UL)    /*!< SMPS step down in bypass mode  */
-#define PWR_SMPS_STEP_DOWN                  (PWR_CR5_SMPSEN)  /*!< SMPS step down in step down mode if system low power mode is run, LP run or stop0. If system low power mode is stop1, stop2, standby, shutdown, then SMPS is forced in mode open to preserve energy stored in decoupling capacitor as long as possible. Note: In case of a board without SMPS coil mounted, SMPS should not be activated. */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_EC_RADIO_BUSY_POLARITY Radio busy signal polarity
-  * @{
-  */
-#define PWR_RADIO_BUSY_POLARITY_RISING      (0x00000000UL)     /*!< Radio busy signal polarity to rising edge (detection on high level). */
-#define PWR_RADIO_BUSY_POLARITY_FALLING     (PWR_CR4_WRFBUSYP) /*!< Radio busy signal polarity to falling edge (detection on low level). */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_EC_RADIO_BUSY_TRIGGER Radio busy trigger
-  * @{
-  */
-#define PWR_RADIO_BUSY_TRIGGER_NONE         (0x00000000UL)     /*!< Radio busy trigger action: no wake-up from low-power mode and no interruption sent to the selected CPU. */
-#define PWR_RADIO_BUSY_TRIGGER_WU_IT        (PWR_CR3_EWRFBUSY) /*!< Radio busy trigger action: wake-up from low-power mode Standby and interruption sent to the selected CPU. */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_EC_RADIO_IRQ_TRIGGER Radio IRQ trigger
-  * @{
-  */
-#define PWR_RADIO_IRQ_TRIGGER_NONE          (0x00000000UL)     /*!< Radio IRQ trigger action: no wake-up from low-power mode and no interruption sent to the selected CPU. */
-#define PWR_RADIO_IRQ_TRIGGER_WU_IT         (PWR_CR3_EWRFIRQ)  /*!< Radio IRQ trigger action: wake-up from low-power mode Standby and interruption sent to the selected CPU. */
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_Flag  PWR Status Flags
-  *        Elements values convention: 0000 0000 0XXY YYYYb
-  *           - Y YYYY  : Flag position in the XX register (5 bits)
-  *           - XX  : Status register (2 bits)
-  *                 - 01: SR1 register
-  *                 - 10: SR2 register
-  *                 - 11: EXTSCR register
-  * @{
-  */
-/*--------------------------------SR1-------------------------------*/
-#define PWR_FLAG_WUF1                       (PWR_FLAG_REG_SR1 | PWR_SR1_WUF1_Pos)        /*!< Wakeup event on wakeup pin 1 */
-#define PWR_FLAG_WUF2                       (PWR_FLAG_REG_SR1 | PWR_SR1_WUF2_Pos)        /*!< Wakeup event on wakeup pin 2 */
-#define PWR_FLAG_WUF3                       (PWR_FLAG_REG_SR1 | PWR_SR1_WUF3_Pos)        /*!< Wakeup event on wakeup pin 3 */
-#define PWR_FLAG_WU                         (PWR_FLAG_REG_SR1 | PWR_SR1_WUF)             /*!< Encompass wakeup event on all wakeup pins */
-#define PWR_FLAG_WPVD                       (PWR_FLAG_REG_SR1 | PWR_SR1_WPVDF_Pos)       /*!< Wakeup PVD flag */
-#define PWR_FLAG_HOLDC2I                    (PWR_FLAG_REG_SR1 | PWR_SR1_C2HF_Pos)        /*!< CPU2 on-Hold Interrupt Flag */
-#define PWR_FLAG_WUFI                       (PWR_FLAG_REG_SR1 | PWR_SR1_WUFI_Pos)        /*!< Wakeup on internal wakeup line */
-#define PWR_FLAG_WRFBUSY                    (PWR_FLAG_REG_SR1 | PWR_SR1_WRFBUSYF_Pos)    /*!< Wakeup radio busy flag (triggered status: wake-up event or interruption occurred at least once. Can be cleared by software) */
-/*--------------------------------SR2-------------------------------*/
-#define PWR_FLAG_LDORDY                     (PWR_FLAG_REG_SR2 | PWR_SR2_LDORDY_Pos)      /*!< Main LDO ready flag */
-#define PWR_FLAG_SMPSRDY                    (PWR_FLAG_REG_SR2 | PWR_SR2_SMPSRDY_Pos)     /*!< SMPS ready Flag */
-#define PWR_FLAG_REGLPS                     (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPS_Pos)      /*!< Low-power regulator started and ready flag */
-#define PWR_FLAG_REGLPF                     (PWR_FLAG_REG_SR2 | PWR_SR2_REGLPF_Pos)      /*!< Low-power regulator (main regulator or low-power regulator used) flag */
-#define PWR_FLAG_REGMRS                     (PWR_FLAG_REG_SR2 | PWR_SR2_REGMRS_Pos)      /*!< Main regulator supply from LDO or SMPS or directly from VDD */
-#define PWR_FLAG_FLASHRDY                   (PWR_FLAG_REG_SR2 | PWR_SR2_FLASHRDY_Pos)    /*!< Flash ready flag */
-#define PWR_FLAG_VOSF                       (PWR_FLAG_REG_SR2 | PWR_SR2_VOSF_Pos)        /*!< Voltage scaling flag */
-#define PWR_FLAG_PVDO                       (PWR_FLAG_REG_SR2 | PWR_SR2_PVDO_Pos)        /*!< Power Voltage Detector output flag */
-#define PWR_FLAG_PVMO3                      (PWR_FLAG_REG_SR2 | PWR_SR2_PVMO3_Pos)       /*!< Power Voltage Monitoring 3 output flag */
-#define PWR_FLAG_RFEOL                      (PWR_FLAG_REG_SR2 | PWR_SR2_RFEOLF_Pos)      /*!< Power Voltage Monitoring Radio end of life flag */
-#define PWR_FLAG_RFBUSYS                    (PWR_FLAG_REG_SR2 | PWR_SR2_RFBUSYS_Pos)     /*!< Radio busy signal flag (current status) */
-#define PWR_FLAG_RFBUSYMS                   (PWR_FLAG_REG_SR2 | PWR_SR2_RFBUSYMS_Pos)    /*!< Radio busy masked signal flag (current status) */
-#define PWR_FLAG_C2BOOTS                    (PWR_FLAG_REG_SR2 | PWR_SR2_C2BOOTS_Pos)     /*!< CPU2 boot request source information flag */
-/*------------------------------EXTSCR------------------------------*/
-#define PWR_FLAG_SB                         (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1SBF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS))    /*!< System Standby flag for CPU1 */
-#define PWR_FLAG_STOP2                      (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1STOP2F_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop 2 flag for CPU1 */
-#define PWR_FLAG_STOP                       (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C1STOPF_Pos | (PWR_EXTSCR_C1CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS))  /*!< System Stop 0 or Stop 1 flag for CPU1 */
-#if defined(DUAL_CORE)
-#define PWR_FLAG_C2SB                       (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2SBF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS))    /*!< System Standby flag for CPU2 */
-#define PWR_FLAG_C2STOP2                    (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2STOP2F_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop 2 flag for CPU2 */
-#define PWR_FLAG_C2STOP                     (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2STOPF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS))  /*!< System Stop 0 or Stop 1 flag for CPU2 */
-#endif
-
-#define PWR_FLAG_LPMODES                    (PWR_FLAG_SB)                       /*!< System flag encompassing all low-powers flags (Stop0, 1, 2 and Standby) for CPU1, used when clearing flags */
-#if defined(DUAL_CORE)
-#define PWR_FLAG_C2LPMODES                  (PWR_FLAG_C2SB)                     /*!< System flag encompassing all low-powers flags (Stop0, 1, 2 and Standby) for CPU2, used when clearing flags */
-#endif
-
-#define PWR_FLAG_C1DEEPSLEEP                (PWR_EXTSCR_C1DS_Pos | PWR_FLAG_REG_EXTSCR)     /*!< CPU1 DeepSleep Flag */
-#if defined(DUAL_CORE)
-#define PWR_FLAG_C2DEEPSLEEP                (PWR_EXTSCR_C2DS_Pos | PWR_FLAG_REG_EXTSCR)     /*!< CPU2 DeepSleep Flag */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_Core_Select PWREx Core definition
-  * @{
-  */
-#define PWR_CORE_CPU1                       (0x00000000UL)
-#if defined(DUAL_CORE)
-#define PWR_CORE_CPU2                       (0x00000001UL)
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
-  * @{
-  */
-#define PWR_EXTI_LINE_PVM3                  (LL_EXTI_LINE_34)  /*!< External interrupt line 34 connected to PVM3 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
- * @{
- */
-
-/**
-  * @brief Enable the PVM3 Extended Interrupt line.
-  * @retval None
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_PWR_PVM3_EXTI_ENABLE_IT()     LL_C2_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)
-#else
-#define __HAL_PWR_PVM3_EXTI_ENABLE_IT()     LL_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3)
-#endif
-
-/**
-  * @brief Disable the PVM3 Extended Interrupt line.
-  * @retval None
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_PWR_PVM3_EXTI_DISABLE_IT()    LL_C2_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)
-#else
-#define __HAL_PWR_PVM3_EXTI_DISABLE_IT()    LL_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3)
-#endif
-
-/**
-  * @brief Enable the PVM3 Event line.
-  * @retval None
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT()  LL_C2_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)
-#else
-#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT()  LL_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3)
-#endif
-
-/**
-  * @brief Disable the PVM3 Event line.
-  * @retval None
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT()   LL_C2_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)
-#else
-#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT()   LL_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3)
-#endif
-
-/**
-  * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
-  * @note  PVM3 flag polarity is inverted compared to EXTI line, therefore
-  *        EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE()   LL_EXTI_EnableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)
-
-/**
-  * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
-  * @note  PVM3 flag polarity is inverted compared to EXTI line, therefore
-  *        EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE()  LL_EXTI_DisableFallingTrig_32_63(PWR_EXTI_LINE_PVM3)
-
-/**
-  * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
-  * @note  PVM3 flag polarity is inverted compared to EXTI line, therefore
-  *        EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)
-
-
-/**
-  * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
-  * @note  PVM3 flag polarity is inverted compared to EXTI line, therefore
-  *        EXTI rising and falling logic edges are inverted versus PVM3 voltage edges.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableRisingTrig_32_63(PWR_EXTI_LINE_PVM3)
-
-/**
-  * @brief  PVM3 EXTI line configuration: set rising & falling edge trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()  \
-  do {                                                    \
-    __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \
-    __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \
-  } while(0)
-
-/**
-  * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()  \
-  do {                                                     \
-    __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();             \
-    __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();            \
-  } while(0)
-
-/**
-  * @brief  Generate a Software interrupt on selected EXTI line.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_32_63(PWR_EXTI_LINE_PVM3)
-
-/**
-  * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
-  * @retval EXTI PVM3 Line Status.
-  */
-#define __HAL_PWR_PVM3_EXTI_GET_FLAG()      LL_EXTI_ReadFlag_32_63(PWR_EXTI_LINE_PVM3)
-
-/**
-  * @brief Clear the PVM3 EXTI flag.
-  * @retval None
-  */
-#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG()    LL_EXTI_ClearFlag_32_63(PWR_EXTI_LINE_PVM3)
-
-
-/**
-  * @brief Configure the main internal regulator output voltage.
-  * @param __REGULATOR__ specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption.
-  *          This parameter can be one of the following values:
-  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1  Regulator voltage output range 1 mode,
-  *                                                typical output voltage at 1.2 V,
-  *                                                system frequency up to 64 MHz.
-  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2  Regulator voltage output range 2 mode,
-  *                                                typical output voltage at 1.0 V,
-  *                                                system frequency up to 16 MHz.
-  * @note  This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
-  *        whether or not VOSF flag is cleared when moving from range 2 to range 1. User
-  *        may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.
-  * @retval None
-  */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
-                                                            __IO uint32_t tmpreg;                               \
-                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
-                                                            /* Delay after an RCC peripheral clock enabling */  \
-                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
-                                                            UNUSED(tmpreg);                                     \
-                                                          } while(0)
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros
-  * @{
-  */
-
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
-                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
-                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
-                                ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
-                                ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
-                                ((PIN) == PWR_WAKEUP_PIN3_LOW))
-
-#define IS_PWR_PVM_TYPE(__TYPE__) (((__TYPE__) == PWR_PVM_3))
-
-#define IS_PWR_PVM_MODE(__MODE__) (((__MODE__) == PWR_PVM_MODE_NORMAL)              ||\
-                                   ((__MODE__) == PWR_PVM_MODE_IT_RISING)           ||\
-                                   ((__MODE__) == PWR_PVM_MODE_IT_FALLING)          ||\
-                                   ((__MODE__) == PWR_PVM_MODE_IT_RISING_FALLING))
-
-#define IS_PWR_FLASH_POWERDOWN(__MODE__)    ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) != 0x00UL) && \
-                                             (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) == 0x00UL))
-
-#define IS_PWR_VOLTAGE_SCALING_RANGE(__RANGE__) (((__RANGE__) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
-                                                 ((__RANGE__) == PWR_REGULATOR_VOLTAGE_SCALE2))
-
-#define IS_PWR_BATTERY_RESISTOR_SELECT(__RESISTOR__) (((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
-                                                      ((__RESISTOR__) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
-
-#define IS_PWR_BATTERY_CHARGING(__CHARGING__) (((__CHARGING__) == PWR_BATTERY_CHARGING_DISABLE) ||\
-                                               ((__CHARGING__) == PWR_BATTERY_CHARGING_ENABLE))
-
-#define IS_PWR_GPIO_BIT_NUMBER(__BIT_NUMBER__) (((__BIT_NUMBER__) & GPIO_PIN_MASK) != (uint32_t)0x00)
-
-#define IS_PWR_GPIO(__GPIO__) (((__GPIO__) == PWR_GPIO_A) ||\
-                               ((__GPIO__) == PWR_GPIO_B) ||\
-                               ((__GPIO__) == PWR_GPIO_C) ||\
-                               ((__GPIO__) == PWR_GPIO_H))
-
-#define IS_PWR_SMPS_MODE(__SMPS_MODE__) (((__SMPS_MODE__) == PWR_SMPS_BYPASS)    ||\
-                                         ((__SMPS_MODE__) == PWR_SMPS_STEP_DOWN))
-
-#define IS_RADIO_BUSY_POLARITY(__RADIO_BUSY_POLARITY__) (((__RADIO_BUSY_POLARITY__) == PWR_RADIO_BUSY_POLARITY_RISING)  ||\
-                                                         ((__RADIO_BUSY_POLARITY__) == PWR_RADIO_BUSY_POLARITY_FALLING))
-
-#define IS_PWR_RADIO_BUSY_TRIGGER(__RADIO_BUSY_TRIGGER__) (((__RADIO_BUSY_TRIGGER__) == PWR_RADIO_BUSY_TRIGGER_NONE)  ||\
-                                                           ((__RADIO_BUSY_TRIGGER__) == PWR_RADIO_BUSY_TRIGGER_WU_IT))
-
-#define IS_RADIO_IRQ_TRIGGER(__RADIO_IRQ_TRIGGER__) (((__RADIO_IRQ_TRIGGER__) == PWR_RADIO_IRQ_TRIGGER_NONE)  ||\
-                                                     ((__RADIO_IRQ_TRIGGER__) == PWR_RADIO_IRQ_TRIGGER_WU_IT))
-
-#if defined(DUAL_CORE)
-#define IS_PWR_CORE(__CPU__)  (((__CPU__) == PWR_CORE_CPU1) || ((__CPU__) == PWR_CORE_CPU2))
-#else
-#define IS_PWR_CORE(__CPU__)  (((__CPU__) == PWR_CORE_CPU1))
-#endif
-
-#if defined(DUAL_CORE)
-#define IS_PWR_CORE_HOLD_RELEASE(__CPU__)  ((__CPU__) == PWR_CORE_CPU2)
-#endif
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
-  * @{
-  */
-
-/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions
-  * @{
-  */
-
-
-/* Peripheral Control functions  **********************************************/
-uint32_t          HAL_PWREx_GetVoltageRange(void);
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
-
-void              HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
-void              HAL_PWREx_DisableBatteryCharging(void);
-
-void              HAL_PWREx_EnableInternalWakeUpLine(void);
-void              HAL_PWREx_DisableInternalWakeUpLine(void);
-
-void              HAL_PWREx_SetRadioBusyPolarity(uint32_t RadioBusyPolarity);
-void              HAL_PWREx_SetRadioBusyTrigger(uint32_t RadioBusyTrigger);
-void              HAL_PWREx_SetRadioIRQTrigger(uint32_t RadioIRQTrigger);
-
-void              HAL_PWREx_EnableHOLDC2IT(void);
-void              HAL_PWREx_DisableHOLDC2IT(void);
-
-void              HAL_PWREx_HoldCore(uint32_t CPU);
-void              HAL_PWREx_ReleaseCore(uint32_t CPU);
-
-#ifdef CORE_CM0PLUS
-void              HAL_PWREx_EnableWakeUp_ILAC(void);
-void              HAL_PWREx_DisableWakeUp_ILAC(void);
-uint32_t          HAL_PWREx_IsEnabledWakeUp_ILAC(void);
-#endif
-
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
-HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
-HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
-void              HAL_PWREx_EnablePullUpPullDownConfig(void);
-void              HAL_PWREx_DisablePullUpPullDownConfig(void);
-
-void              HAL_PWREx_EnableSRAMRetention(void);
-void              HAL_PWREx_DisableSRAMRetention(void);
-
-void              HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode);
-void              HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode);
-
-void              HAL_PWREx_EnableWPVD(void);
-void              HAL_PWREx_DisableWPVD(void);
-void              HAL_PWREx_EnableBORPVD_ULP(void);
-void              HAL_PWREx_DisableBORPVD_ULP(void);
-
-void              HAL_PWREx_EnablePVM3(void);
-void              HAL_PWREx_DisablePVM3(void);
-
-HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
-
-void              HAL_PWREx_SetRadioEOL(uint32_t RadioEOL);
-void              HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode);
-uint32_t          HAL_PWREx_SMPS_GetEffectiveMode(void);
-
-/* Low Power modes configuration functions ************************************/
-void              HAL_PWREx_EnableLowPowerRunMode(void);
-HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
-
-void              HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
-void              HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
-void              HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
-void              HAL_PWREx_EnterSHUTDOWNMode(void);
-
-void              HAL_PWREx_PVD_PVM_IRQHandler(void);
-
-void              HAL_PWREx_PVM3Callback(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32WLxx_HAL_PWR_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h

@@ -1,2403 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_rcc.h
-  * @author  MCD Application Team
-  * @brief   Header file of RCC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_RCC_H
-#define STM32WLxx_HAL_RCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-#include "stm32wlxx_ll_rcc.h"
-#include "stm32wlxx_ll_bus.h"
-
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCC
-  * @{
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RCC_Private_Constants
-  * @{
-  */
-/* Defines used for Flags */
-#define CR_REG_INDEX              1U
-#define BDCR_REG_INDEX            2U
-#define CSR_REG_INDEX             3U
-#define REG_INDEX_POS             5U
-
-#define RCC_FLAG_MASK             0x1FU
-
-/* Defines Oscillator Masks */
-#define RCC_OSCILLATORTYPE_ALL          (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE)  /*!< All Oscillator to configure */
-
-/** @defgroup RCC_Timeout_Value Timeout Values
-  * @{
-  */
-#define RCC_DBP_TIMEOUT_VALUE          2U                   /*!< 2 ms (minimum Tick + 1)  */
-#define RCC_LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT  /*!< LSE timeout in ms        */
-#define PLL_TIMEOUT_VALUE              10U                 /*!< 10 ms (minimum Tick + 1)  */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Reset_Flag Reset Flag
-  * @{
-  */
-#define RCC_RESET_FLAG_OBL             RCC_CSR_OBLRSTF    /*!< Option Byte Loader reset flag */
-#define RCC_RESET_FLAG_PIN             RCC_CSR_PINRSTF    /*!< PIN reset flag */
-#define RCC_RESET_FLAG_PWR             RCC_CSR_BORRSTF    /*!< BOR or POR/PDR reset flag */
-#define RCC_RESET_FLAG_SW              RCC_CSR_SFTRSTF    /*!< Software Reset flag */
-#define RCC_RESET_FLAG_IWDG            RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */
-#define RCC_RESET_FLAG_WWDG            RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */
-#define RCC_RESET_FLAG_LPWR            RCC_CSR_LPWRRSTF   /*!< Low power reset flag */
-#define RCC_RESET_FLAG_ALL             (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \
-                                        RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \
-                                        RCC_RESET_FLAG_LPWR)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCC_Private_Macros
-  * @{
-  */
-
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)  (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
-                                                (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U))
-
-
-#define IS_RCC_HSE(__HSE__)  (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
-                              ((__HSE__) == RCC_HSE_BYPASS_PWR))
-
-#define IS_RCC_HSEDIV(__HSEDIV__)  (((__HSEDIV__) == RCC_HSE_DIV1) || ((__HSEDIV__) == RCC_HSE_DIV2))
-
-#define IS_RCC_LSE(__LSE__)  (((__LSE__) == RCC_LSE_OFF)                                              || \
-                              ((__LSE__) == RCC_LSE_ON)     || ((__LSE__) == RCC_LSE_ON_RTC_ONLY)     || \
-                              ((__LSE__) == RCC_LSE_BYPASS) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY))
-
-#define IS_RCC_HSI(__HSI__)  (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-
-#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)127U)
-
-#define IS_RCC_LSI(__LSI__)  (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
-
-#define IS_RCC_LSIDIV(__LSIDIV__)  (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128))
-
-#define IS_RCC_MSI(__MSI__)  (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
-
-#define IS_RCC_MSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)255U)
-
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
-                             ((__PLL__) == RCC_PLL_ON))
-
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
-                                      ((__SOURCE__) == RCC_PLLSOURCE_MSI)  || \
-                                      ((__SOURCE__) == RCC_PLLSOURCE_HSI)  || \
-                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))
-
-#define IS_RCC_PLLM_VALUE(__VALUE__) (((__VALUE__) == RCC_PLLM_DIV1)  || \
-                                      ((__VALUE__) == RCC_PLLM_DIV2)  || \
-                                      ((__VALUE__) == RCC_PLLM_DIV3)  || \
-                                      ((__VALUE__) == RCC_PLLM_DIV4)  || \
-                                      ((__VALUE__) == RCC_PLLM_DIV5)  || \
-                                      ((__VALUE__) == RCC_PLLM_DIV6)  || \
-                                      ((__VALUE__) == RCC_PLLM_DIV7)  || \
-                                      ((__VALUE__) == RCC_PLLM_DIV8))
-
-#define IS_RCC_PLLN_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
-
-#define IS_RCC_PLLP_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))
-
-#define IS_RCC_PLLQ_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))
-
-#define IS_RCC_PLLR_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))
-
-#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_1)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_2)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_3)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_4)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_5)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_6)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_7)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_8)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_9)  || \
-                                           ((__RANGE__) == RCC_MSIRANGE_10) || \
-                                           ((__RANGE__) == RCC_MSIRANGE_11))
-
-#if defined(DUAL_CORE)
-#define IS_RCC_CLOCKTYPE(__CLK__)   ((1U <= (__CLK__)) && ((__CLK__) <= (RCC_CLOCKTYPE_SYSCLK | \
-                                                                         RCC_CLOCKTYPE_HCLK   | \
-                                                                         RCC_CLOCKTYPE_PCLK1  | \
-                                                                         RCC_CLOCKTYPE_PCLK2  | \
-                                                                         RCC_CLOCKTYPE_HCLK2  | \
-                                                                         RCC_CLOCKTYPE_HCLK3)))
-#else
-#define IS_RCC_CLOCKTYPE(__CLK__)   ((1U <= (__CLK__)) && ((__CLK__) <= (RCC_CLOCKTYPE_SYSCLK | \
-                                                                         RCC_CLOCKTYPE_HCLK   | \
-                                                                         RCC_CLOCKTYPE_PCLK1  | \
-                                                                         RCC_CLOCKTYPE_PCLK2  | \
-                                                                         RCC_CLOCKTYPE_HCLK3)))
-#endif /* DUAL_CORE */
-
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
-
-#define IS_RCC_HCLKx(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1)   || ((__HCLK__) == RCC_SYSCLK_DIV2)   || \
-                                ((__HCLK__) == RCC_SYSCLK_DIV3)   || ((__HCLK__) == RCC_SYSCLK_DIV4)   || \
-                                ((__HCLK__) == RCC_SYSCLK_DIV5)   || ((__HCLK__) == RCC_SYSCLK_DIV6)   || \
-                                ((__HCLK__) == RCC_SYSCLK_DIV8)   || ((__HCLK__) == RCC_SYSCLK_DIV10)  || \
-                                ((__HCLK__) == RCC_SYSCLK_DIV16)  || ((__HCLK__) == RCC_SYSCLK_DIV32)  || \
-                                ((__HCLK__) == RCC_SYSCLK_DIV64)  || ((__HCLK__) == RCC_SYSCLK_DIV128) || \
-                                ((__HCLK__) == RCC_SYSCLK_DIV256) || ((__HCLK__) == RCC_SYSCLK_DIV512))
-
-#define IS_RCC_PCLKx(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
-                                ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
-                                ((__PCLK__) == RCC_HCLK_DIV16))
-
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE)  || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI)  || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
-
-#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO1))
-
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK)  || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_MSI)     || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSI)     || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_HSE)     || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK)  || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSI)     || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_LSE)     || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLPCLK) || \
-                                       ((__SOURCE__) == RCC_MCO1SOURCE_PLLQCLK))
-
-#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
-                                ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
-                                ((__DIV__) == RCC_MCODIV_16))
-
-
-#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) || \
-                                             ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI))
-/**
-  * @}
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RCC_Exported_Types RCC Exported Types
-  * @{
-  */
-
-
-/**
-  * @brief  RCC PLL configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PLLState;   /*!< The new state of the PLL.
-                            This parameter must be a value of @ref RCC_PLL_Config                                 */
-
-  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
-                            This parameter must be a value of @ref RCC_PLL_Clock_Source                           */
-
-  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
-                            This parameter must be a value of @ref RCC_PLLM_Clock_Divider                         */
-
-  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
-                            This parameter must be a number between Min_Data = 6 and Max_Data = 127                */
-
-  uint32_t PLLP;       /*!< PLLP: Division factor for ADC clock.
-                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider                         */
-
-  uint32_t PLLQ;       /*!< PLLQ: Division factor for I2S2 and RNG clock.
-                            This parameter must be a value of @ref RCC_PLLQ_Clock_Divider                         */
-
-  uint32_t PLLR;       /*!< PLLR: Division for the main system clock.
-                            User has to set the PLLR parameter correctly to not exceed max frequency 48 MHZ.
-                            This parameter must be a value of @ref RCC_PLLR_Clock_Divider                         */
-
-} RCC_PLLInitTypeDef;
-
-/**
-  * @brief  RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition
-  */
-typedef struct
-{
-  uint32_t OscillatorType;       /*!< The oscillators to be configured.
-                                      This parameter can be a combination of @ref RCC_Oscillator_Type             */
-
-  uint32_t HSEState;             /*!< The new state of the HSE.
-                                      This parameter can be a value of @ref RCC_HSE_Config                        */
-
-  uint32_t HSEDiv;               /*!< The division factor of the HSE.
-                                      This parameter can be a value of @ref RCC_HSE_Div                           */
-
-  uint32_t LSEState;             /*!< The new state of the LSE.
-                                      This parameter can be a value of @ref RCC_LSE_Config                        */
-
-  uint32_t HSIState;             /*!< The new state of the HSI.
-                                      This parameter can be a value of @ref RCC_HSI_Config                        */
-
-  uint32_t HSICalibrationValue;  /*!< The calibration trimming value (default is @ref RCC_HSICALIBRATION_DEFAULT).
-                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
-
-  uint32_t LSIState;             /*!< The new state of the LSI.
-                                      This parameter can be a value of @ref RCC_LSI_Config                        */
-
-  uint32_t LSIDiv;               /*!< The division factor of the LSI.
-                                      This parameter can be a value of @ref RCC_LSI_Div                           */
-
-  uint32_t MSIState;             /*!< The new state of the MSI.
-                                      This parameter can be a value of @ref RCC_MSI_Config */
-
-  uint32_t MSICalibrationValue;  /*!< The calibration trimming value (default is @ref RCC_MSICALIBRATION_DEFAULT).
-                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-
-  uint32_t MSIClockRange;        /*!< The MSI frequency range.
-                                      This parameter can be a value of @ref RCC_MSI_Clock_Range                   */
-
-  RCC_PLLInitTypeDef PLL;        /*!< Main PLL structure parameters                                               */
-
-} RCC_OscInitTypeDef;
-
-/**
-  * @brief  RCC System, AHB and APB buses clock configuration structure definition
-  */
-typedef struct
-{
-  uint32_t ClockType;             /*!< The clock to be configured.
-                                       This parameter can be a combination of @ref RCC_System_Clock_Type          */
-
-  uint32_t SYSCLKSource;          /*!< The clock source used as system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_System_Clock_Source              */
-
-  uint32_t AHBCLKDivider;         /*!< The AHBx clock (HCLK1) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_AHBx_Clock_Source                */
-
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APBx_Clock_Source                */
-
-  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APBx_Clock_Source                */
-
-#if defined(DUAL_CORE)
-  uint32_t AHBCLK2Divider;        /*!< The AHB clock (HCLK2) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_AHBx_Clock_Source                */
-
-#endif /* DUAL_CORE */
-  uint32_t AHBCLK3Divider;        /*!< The AHB shared clock (HCLK3) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_AHBx_Clock_Source                */
-
-} RCC_ClkInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
-  * @{
-  */
-
-/** @defgroup RCC_Oscillator_Type Oscillator Type
-  * @{
-  */
-#define RCC_OSCILLATORTYPE_NONE        0x00000000U  /*!< Oscillator configuration unchanged  */
-#define RCC_OSCILLATORTYPE_HSE         0x00000001U  /*!< HSE to configure                    */
-#define RCC_OSCILLATORTYPE_HSI         0x00000002U  /*!< HSI to configure                    */
-#define RCC_OSCILLATORTYPE_LSE         0x00000004U  /*!< LSE to configure                    */
-#define RCC_OSCILLATORTYPE_LSI         0x00000008U  /*!< LSI to configure                    */
-#define RCC_OSCILLATORTYPE_MSI         0x00000020U  /*!< MSI to configure                    */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Config HSE Config
-  * @{
-  */
-#define RCC_HSE_OFF                    0x00000000U                                    /*!< HSE clock deactivation                    */
-#define RCC_HSE_ON                     RCC_CR_HSEON                                   /*!< HSE clock activation                      */
-#define RCC_HSE_BYPASS_PWR             ((uint32_t)(RCC_CR_HSEBYPPWR | RCC_CR_HSEON))  /*!< TCXO external clock source for HSE clock  */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Div HSE Div
-  * @{
-  */
-#define RCC_HSE_DIV1                   0x00000000U    /*!< HSE clock not divided    */
-#define RCC_HSE_DIV2                   RCC_CR_HSEPRE  /*!< HSE clock divided by 2    */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Config LSE Config
-  * @{
-  */
-#define RCC_LSE_OFF                    0U                                                                  /*!< LSE clock deactivation                             */
-#define RCC_LSE_ON_RTC_ONLY            RCC_BDCR_LSEON                                                      /*!< LSE clock activation for RTC only                  */
-#define RCC_LSE_ON                     ((uint32_t)(RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON))                    /*!< LSE clock activation for RTC and other peripherals */
-#define RCC_LSE_BYPASS_RTC_ONLY        ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))                      /*!< External clock source for LSE clock                */
-#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON))  /*!< External clock source for LSE clock                */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSI_Config HSI Config
-  * @{
-  */
-#define RCC_HSI_OFF                    0x00000000U   /*!< HSI clock deactivation */
-#define RCC_HSI_ON                     RCC_CR_HSION  /*!< HSI clock activation   */
-
-#define RCC_HSICALIBRATION_DEFAULT     64U           /*!< Default HSI calibration trimming value */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Config LSI Config
-  * @{
-  */
-#define RCC_LSI_OFF                    0x00000000U    /*!< LSI clock deactivation */
-#define RCC_LSI_ON                     RCC_CSR_LSION  /*!< LSI clock activation   */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Div LSI Div
-  * @{
-  */
-#define RCC_LSI_DIV1                   LL_RCC_LSI_PREDIV_1    /*!< LSI clock not divided    */
-#define RCC_LSI_DIV128                 LL_RCC_LSI_PREDIV_128  /*!< LSI clock divided by 128 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MSI_Config MSI Config
-  * @{
-  */
-#define RCC_MSI_OFF                    0x00000000U   /*!< MSI clock deactivation */
-#define RCC_MSI_ON                     RCC_CR_MSION  /*!< MSI clock activation   */
-
-#define RCC_MSICALIBRATION_DEFAULT     0U            /*!< Default MSI calibration trimming value */
-/**
-  * @}
-  */
-
-
-/** @defgroup RCC_PLL_Config PLL Config
-  * @{
-  */
-#define RCC_PLL_NONE                   0x00000000U  /*!< PLL configuration unchanged */
-#define RCC_PLL_OFF                    0x00000001U  /*!< PLL deactivation            */
-#define RCC_PLL_ON                     0x00000002U  /*!< PLL activation              */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider
-  * @{
-  */
-#define RCC_PLLM_DIV1                  LL_RCC_PLLM_DIV_1  /*!< PLLM division factor = 1  */
-#define RCC_PLLM_DIV2                  LL_RCC_PLLM_DIV_2  /*!< PLLM division factor = 2  */
-#define RCC_PLLM_DIV3                  LL_RCC_PLLM_DIV_3  /*!< PLLM division factor = 3  */
-#define RCC_PLLM_DIV4                  LL_RCC_PLLM_DIV_4  /*!< PLLM division factor = 4  */
-#define RCC_PLLM_DIV5                  LL_RCC_PLLM_DIV_5  /*!< PLLM division factor = 5  */
-#define RCC_PLLM_DIV6                  LL_RCC_PLLM_DIV_6  /*!< PLLM division factor = 6  */
-#define RCC_PLLM_DIV7                  LL_RCC_PLLM_DIV_7  /*!< PLLM division factor = 7  */
-#define RCC_PLLM_DIV8                  LL_RCC_PLLM_DIV_8  /*!< PLLM division factor = 8  */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
-  * @{
-  */
-#define RCC_PLLP_DIV2                  LL_RCC_PLLP_DIV_2   /*!< PLLP division factor = 2  */
-#define RCC_PLLP_DIV3                  LL_RCC_PLLP_DIV_3   /*!< PLLP division factor = 3  */
-#define RCC_PLLP_DIV4                  LL_RCC_PLLP_DIV_4   /*!< PLLP division factor = 4  */
-#define RCC_PLLP_DIV5                  LL_RCC_PLLP_DIV_5   /*!< PLLP division factor = 5  */
-#define RCC_PLLP_DIV6                  LL_RCC_PLLP_DIV_6   /*!< PLLP division factor = 6  */
-#define RCC_PLLP_DIV7                  LL_RCC_PLLP_DIV_7   /*!< PLLP division factor = 7  */
-#define RCC_PLLP_DIV8                  LL_RCC_PLLP_DIV_8   /*!< PLLP division factor = 8  */
-#define RCC_PLLP_DIV9                  LL_RCC_PLLP_DIV_9   /*!< PLLP division factor = 9  */
-#define RCC_PLLP_DIV10                 LL_RCC_PLLP_DIV_10  /*!< PLLP division factor = 10 */
-#define RCC_PLLP_DIV11                 LL_RCC_PLLP_DIV_11  /*!< PLLP division factor = 11 */
-#define RCC_PLLP_DIV12                 LL_RCC_PLLP_DIV_12  /*!< PLLP division factor = 12 */
-#define RCC_PLLP_DIV13                 LL_RCC_PLLP_DIV_13  /*!< PLLP division factor = 13 */
-#define RCC_PLLP_DIV14                 LL_RCC_PLLP_DIV_14  /*!< PLLP division factor = 14 */
-#define RCC_PLLP_DIV15                 LL_RCC_PLLP_DIV_15  /*!< PLLP division factor = 15 */
-#define RCC_PLLP_DIV16                 LL_RCC_PLLP_DIV_16  /*!< PLLP division factor = 16 */
-#define RCC_PLLP_DIV17                 LL_RCC_PLLP_DIV_17  /*!< PLLP division factor = 17 */
-#define RCC_PLLP_DIV18                 LL_RCC_PLLP_DIV_18  /*!< PLLP division factor = 18 */
-#define RCC_PLLP_DIV19                 LL_RCC_PLLP_DIV_19  /*!< PLLP division factor = 19 */
-#define RCC_PLLP_DIV20                 LL_RCC_PLLP_DIV_20  /*!< PLLP division factor = 20 */
-#define RCC_PLLP_DIV21                 LL_RCC_PLLP_DIV_21  /*!< PLLP division factor = 21 */
-#define RCC_PLLP_DIV22                 LL_RCC_PLLP_DIV_22  /*!< PLLP division factor = 22 */
-#define RCC_PLLP_DIV23                 LL_RCC_PLLP_DIV_23  /*!< PLLP division factor = 23 */
-#define RCC_PLLP_DIV24                 LL_RCC_PLLP_DIV_24  /*!< PLLP division factor = 24 */
-#define RCC_PLLP_DIV25                 LL_RCC_PLLP_DIV_25  /*!< PLLP division factor = 25 */
-#define RCC_PLLP_DIV26                 LL_RCC_PLLP_DIV_26  /*!< PLLP division factor = 26 */
-#define RCC_PLLP_DIV27                 LL_RCC_PLLP_DIV_27  /*!< PLLP division factor = 27 */
-#define RCC_PLLP_DIV28                 LL_RCC_PLLP_DIV_28  /*!< PLLP division factor = 28 */
-#define RCC_PLLP_DIV29                 LL_RCC_PLLP_DIV_29  /*!< PLLP division factor = 29 */
-#define RCC_PLLP_DIV30                 LL_RCC_PLLP_DIV_30  /*!< PLLP division factor = 30 */
-#define RCC_PLLP_DIV31                 LL_RCC_PLLP_DIV_31  /*!< PLLP division factor = 31 */
-#define RCC_PLLP_DIV32                 LL_RCC_PLLP_DIV_32  /*!< PLLP division factor = 32 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
-  * @{
-  */
-#define RCC_PLLQ_DIV2                  LL_RCC_PLLQ_DIV_2  /*!< PLLQ division factor = 2 */
-#define RCC_PLLQ_DIV3                  LL_RCC_PLLQ_DIV_3  /*!< PLLQ division factor = 3 */
-#define RCC_PLLQ_DIV4                  LL_RCC_PLLQ_DIV_4  /*!< PLLQ division factor = 4 */
-#define RCC_PLLQ_DIV5                  LL_RCC_PLLQ_DIV_5  /*!< PLLQ division factor = 5 */
-#define RCC_PLLQ_DIV6                  LL_RCC_PLLQ_DIV_6  /*!< PLLQ division factor = 6 */
-#define RCC_PLLQ_DIV7                  LL_RCC_PLLQ_DIV_7  /*!< PLLQ division factor = 7 */
-#define RCC_PLLQ_DIV8                  LL_RCC_PLLQ_DIV_8  /*!< PLLQ division factor = 8 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
-  * @{
-  */
-#define RCC_PLLR_DIV2                  LL_RCC_PLLR_DIV_2  /*!< PLLR division factor = 2 */
-#define RCC_PLLR_DIV3                  LL_RCC_PLLR_DIV_3  /*!< PLLR division factor = 3 */
-#define RCC_PLLR_DIV4                  LL_RCC_PLLR_DIV_4  /*!< PLLR division factor = 4 */
-#define RCC_PLLR_DIV5                  LL_RCC_PLLR_DIV_5  /*!< PLLR division factor = 5 */
-#define RCC_PLLR_DIV6                  LL_RCC_PLLR_DIV_6  /*!< PLLR division factor = 6 */
-#define RCC_PLLR_DIV7                  LL_RCC_PLLR_DIV_7  /*!< PLLR division factor = 7 */
-#define RCC_PLLR_DIV8                  LL_RCC_PLLR_DIV_8  /*!< PLLR division factor = 8 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
-  * @{
-  */
-#define RCC_PLLSOURCE_NONE             LL_RCC_PLLSOURCE_NONE  /*!< No clock selected as PLL entry clock source  */
-#define RCC_PLLSOURCE_MSI              LL_RCC_PLLSOURCE_MSI   /*!< MSI clock selected as PLL entry clock source */
-#define RCC_PLLSOURCE_HSI              LL_RCC_PLLSOURCE_HSI   /*!< HSI clock selected as PLL entry clock source */
-#define RCC_PLLSOURCE_HSE              LL_RCC_PLLSOURCE_HSE   /*!< HSE clock selected as PLL entry clock source */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
-  * @{
-  */
-#define RCC_PLL_SYSCLK                 RCC_PLLCFGR_PLLREN  /*!< PLLCLK selected from main PLL     */
-#define RCC_PLL_I2S2CLK                RCC_PLLCFGR_PLLQEN  /*!< PLLI2S2CLK selected from main PLL */
-#define RCC_PLL_RNGCLK                 RCC_PLLCFGR_PLLQEN  /*!< PLLRNGCLK selected from main PLL  */
-#define RCC_PLL_ADCCLK                 RCC_PLLCFGR_PLLPEN  /*!< PLLADCCLK selected from main PLL  */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MSI_Clock_Range MSI Clock Range
-  * @{
-  */
-#define RCC_MSIRANGE_0                 LL_RCC_MSIRANGE_0   /*!< MSI = 100 KHz  */
-#define RCC_MSIRANGE_1                 LL_RCC_MSIRANGE_1   /*!< MSI = 200 KHz  */
-#define RCC_MSIRANGE_2                 LL_RCC_MSIRANGE_2   /*!< MSI = 400 KHz  */
-#define RCC_MSIRANGE_3                 LL_RCC_MSIRANGE_3   /*!< MSI = 800 KHz  */
-#define RCC_MSIRANGE_4                 LL_RCC_MSIRANGE_4   /*!< MSI = 1 MHz    */
-#define RCC_MSIRANGE_5                 LL_RCC_MSIRANGE_5   /*!< MSI = 2 MHz    */
-#define RCC_MSIRANGE_6                 LL_RCC_MSIRANGE_6   /*!< MSI = 4 MHz    */
-#define RCC_MSIRANGE_7                 LL_RCC_MSIRANGE_7   /*!< MSI = 8 MHz    */
-#define RCC_MSIRANGE_8                 LL_RCC_MSIRANGE_8   /*!< MSI = 16 MHz   */
-#define RCC_MSIRANGE_9                 LL_RCC_MSIRANGE_9   /*!< MSI = 24 MHz   */
-#define RCC_MSIRANGE_10                LL_RCC_MSIRANGE_10  /*!< MSI = 32 MHz   */
-#define RCC_MSIRANGE_11                LL_RCC_MSIRANGE_11  /*!< MSI = 48 MHz   */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Type System Clock Type
-  * @{
-  */
-#define RCC_CLOCKTYPE_SYSCLK           0x00000001U  /*!< SYSCLK to configure */
-#define RCC_CLOCKTYPE_HCLK             0x00000002U  /*!< HCLK to configure   */
-#define RCC_CLOCKTYPE_PCLK1            0x00000004U  /*!< PCLK1 to configure  */
-#define RCC_CLOCKTYPE_PCLK2            0x00000008U  /*!< PCLK2 to configure  */
-#if defined(DUAL_CORE)
-#define RCC_CLOCKTYPE_HCLK2            0x00000020U  /*!< HCLK2 to configure  */
-#endif /* DUAL_CORE */
-#define RCC_CLOCKTYPE_HCLK3            0x00000040U  /*!< HCLK3 to configure  */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Source System Clock Source
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_MSI           LL_RCC_SYS_CLKSOURCE_MSI  /*!< MSI selected as system clock */
-#define RCC_SYSCLKSOURCE_HSI           LL_RCC_SYS_CLKSOURCE_HSI  /*!< HSI selected as system clock */
-#define RCC_SYSCLKSOURCE_HSE           LL_RCC_SYS_CLKSOURCE_HSE  /*!< HSE selected as system clock */
-#define RCC_SYSCLKSOURCE_PLLCLK        LL_RCC_SYS_CLKSOURCE_PLL  /*!< PLL selected as system clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_STATUS_MSI    LL_RCC_SYS_CLKSOURCE_STATUS_MSI  /*!< MSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSI    LL_RCC_SYS_CLKSOURCE_STATUS_HSI  /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE    LL_RCC_SYS_CLKSOURCE_STATUS_HSE  /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK LL_RCC_SYS_CLKSOURCE_STATUS_PLL  /*!< PLL used as system clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHBx_Clock_Source AHB Clock Source
-  * @{
-  */
-#define RCC_SYSCLK_DIV1                LL_RCC_SYSCLK_DIV_1    /*!< SYSCLK not divided    */
-#define RCC_SYSCLK_DIV2                LL_RCC_SYSCLK_DIV_2    /*!< SYSCLK divided by 2   */
-#define RCC_SYSCLK_DIV3                LL_RCC_SYSCLK_DIV_3    /*!< SYSCLK divided by 3   */
-#define RCC_SYSCLK_DIV4                LL_RCC_SYSCLK_DIV_4    /*!< SYSCLK divided by 4   */
-#define RCC_SYSCLK_DIV5                LL_RCC_SYSCLK_DIV_5    /*!< SYSCLK divided by 5   */
-#define RCC_SYSCLK_DIV6                LL_RCC_SYSCLK_DIV_6    /*!< SYSCLK divided by 6   */
-#define RCC_SYSCLK_DIV8                LL_RCC_SYSCLK_DIV_8    /*!< SYSCLK divided by 8   */
-#define RCC_SYSCLK_DIV10               LL_RCC_SYSCLK_DIV_10   /*!< SYSCLK divided by 10  */
-#define RCC_SYSCLK_DIV16               LL_RCC_SYSCLK_DIV_16   /*!< SYSCLK divided by 16  */
-#define RCC_SYSCLK_DIV32               LL_RCC_SYSCLK_DIV_32   /*!< SYSCLK divided by 32  */
-#define RCC_SYSCLK_DIV64               LL_RCC_SYSCLK_DIV_64   /*!< SYSCLK divided by 64  */
-#define RCC_SYSCLK_DIV128              LL_RCC_SYSCLK_DIV_128  /*!< SYSCLK divided by 128 */
-#define RCC_SYSCLK_DIV256              LL_RCC_SYSCLK_DIV_256  /*!< SYSCLK divided by 256 */
-#define RCC_SYSCLK_DIV512              LL_RCC_SYSCLK_DIV_512  /*!< SYSCLK divided by 512 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APBx_Clock_Source APB1 Clock Source
-  * @{
-  */
-#define RCC_HCLK_DIV1                  LL_RCC_APB1_DIV_1   /*!< HCLK not divided   */
-#define RCC_HCLK_DIV2                  LL_RCC_APB1_DIV_2   /*!< HCLK divided by 2  */
-#define RCC_HCLK_DIV4                  LL_RCC_APB1_DIV_4   /*!< HCLK divided by 4  */
-#define RCC_HCLK_DIV8                  LL_RCC_APB1_DIV_8   /*!< HCLK divided by 8  */
-#define RCC_HCLK_DIV16                 LL_RCC_APB1_DIV_16  /*!< HCLK divided by 16 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
-  * @{
-  */
-#define RCC_RTCCLKSOURCE_NONE           LL_RCC_RTC_CLKSOURCE_NONE       /*!< No clock used as RTC clock                           */
-#define RCC_RTCCLKSOURCE_LSE            LL_RCC_RTC_CLKSOURCE_LSE        /*!< LSE oscillator clock used as RTC clock               */
-#define RCC_RTCCLKSOURCE_LSI            LL_RCC_RTC_CLKSOURCE_LSI        /*!< LSI oscillator clock used as RTC clock               */
-#define RCC_RTCCLKSOURCE_HSE_DIV32      LL_RCC_RTC_CLKSOURCE_HSE_DIV32  /*!< HSE oscillator clock divided by 32 used as RTC clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO_Index MCO Index
-  * @{
-  */
-#define RCC_MCO1                       0x00000000U  /*!< MCO1 index                                         */
-#define RCC_MCO                        RCC_MCO1     /*!< MCO to be compliant with other families with 1 MCO */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
-  * @{
-  */
-#define RCC_MCO1SOURCE_NOCLOCK         LL_RCC_MCO1SOURCE_NOCLOCK  /*!< MCO1 output disabled, no clock on MCO1          */
-#define RCC_MCO1SOURCE_SYSCLK          LL_RCC_MCO1SOURCE_SYSCLK   /*!< SYSCLK selected as MCO1 source                  */
-#define RCC_MCO1SOURCE_MSI             LL_RCC_MCO1SOURCE_MSI      /*!< MSI selected as MCO1 source                     */
-#define RCC_MCO1SOURCE_HSI             LL_RCC_MCO1SOURCE_HSI      /*!< HSI selected as MCO1 source                     */
-#define RCC_MCO1SOURCE_HSE             LL_RCC_MCO1SOURCE_HSE      /*!< HSE after stabilization selected as MCO1 source */
-#define RCC_MCO1SOURCE_PLLCLK          LL_RCC_MCO1SOURCE_PLLCLK   /*!< Main PLLRCLK selected as MCO1 source            */
-#define RCC_MCO1SOURCE_LSI             LL_RCC_MCO1SOURCE_LSI      /*!< LSI selected as MCO1 source                     */
-#define RCC_MCO1SOURCE_LSE             LL_RCC_MCO1SOURCE_LSE      /*!< LSE selected as MCO1 source                     */
-#define RCC_MCO1SOURCE_PLLPCLK         LL_RCC_MCO1SOURCE_PLLPCLK  /*!< Main PLLPCLK selected as MCO1 source            */
-#define RCC_MCO1SOURCE_PLLQCLK         LL_RCC_MCO1SOURCE_PLLQCLK  /*!< Main PLLQCLK selected as MCO1 source            */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
-  * @{
-  */
-#define RCC_MCODIV_1                   LL_RCC_MCO1_DIV_1    /*!< MCO not divided */
-#define RCC_MCODIV_2                   LL_RCC_MCO1_DIV_2    /*!< MCO divided by 2 */
-#define RCC_MCODIV_4                   LL_RCC_MCO1_DIV_4    /*!< MCO divided by 4 */
-#define RCC_MCODIV_8                   LL_RCC_MCO1_DIV_8    /*!< MCO divided by 8 */
-#define RCC_MCODIV_16                  LL_RCC_MCO1_DIV_16  /*!< MCO divided by 16 */
-/**
-  * @}
-  */
-
-
-/** @defgroup RCC_Interrupt Interrupts
-  * @{
-  */
-#define RCC_IT_LSIRDY                  LL_RCC_CIFR_LSIRDYF   /*!< LSI Ready Interrupt flag                 */
-#define RCC_IT_LSERDY                  LL_RCC_CIFR_LSERDYF   /*!< LSE Ready Interrupt flag                 */
-#define RCC_IT_MSIRDY                  LL_RCC_CIFR_MSIRDYF   /*!< MSI Ready Interrupt flag                 */
-#define RCC_IT_HSIRDY                  LL_RCC_CIFR_HSIRDYF   /*!< HSI Ready Interrupt flag                 */
-#define RCC_IT_HSERDY                  LL_RCC_CIFR_HSERDYF   /*!< HSE Ready Interrupt flag                 */
-#define RCC_IT_PLLRDY                  LL_RCC_CIFR_PLLRDYF   /*!< PLL Ready Interrupt flag                 */
-#define RCC_IT_HSECSS                  LL_RCC_CIFR_CSSF      /*!< HSE Clock Security System Interrupt flag */
-#define RCC_IT_LSECSS                  LL_RCC_CIFR_LSECSSF   /*!< LSE Clock Security System Interrupt flag */
-/**
-  * @}
-  */
-
-
-/** @defgroup RCC_Flag Flags
-  *        Elements values convention: XXXYYYYYb
-  *           - YYYYY  : Flag position in the register
-  *           - XXX  : Register index
-  *                 - 001: CR register
-  *                 - 010: BDCR register
-  *                 - 011: CSR register
-  * @{
-  */
-/* Flags in the CR register */
-#define RCC_FLAG_MSIRDY                ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_MSIRDY_Pos)         /*!< MSI Ready flag                                   */
-#define RCC_FLAG_HSIRDY                ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_HSIRDY_Pos)         /*!< HSI Ready flag                                   */
-#define RCC_FLAG_HSIKERDY              ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_HSIKERDY_Pos)       /*!< HSI Ready flag                                   */
-#define RCC_FLAG_HSERDY                ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_HSERDY_Pos)         /*!< HSE Ready flag                                   */
-#define RCC_FLAG_PLLRDY                ((CR_REG_INDEX << REG_INDEX_POS) | RCC_CR_PLLRDY_Pos)         /*!< PLL Ready flag                                   */
-
-/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY                ((BDCR_REG_INDEX << REG_INDEX_POS) | RCC_BDCR_LSERDY_Pos)     /*!< LSE Ready flag                                   */
-#define RCC_FLAG_LSECSSD               ((BDCR_REG_INDEX << REG_INDEX_POS) | RCC_BDCR_LSECSSD_Pos)    /*!< LSE Clock Security System failure detection flag */
-#define RCC_FLAG_LSESYSRDY             ((BDCR_REG_INDEX << REG_INDEX_POS) | RCC_BDCR_LSESYSRDY_Pos)  /*!< LSE system clock ready flag                      */
-
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY                ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_LSIRDY_Pos)       /*!< LSI Ready flag                                   */
-#define RCC_FLAG_RFRST                 ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_RFRSTF_Pos)       /*!< Sub-GHz radio reset flag                         */
-#define RCC_FLAG_RFILARSTF             ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_RFILARSTF_Pos)    /*!< Sub-GHz radio illegal command flag               */
-#define RCC_FLAG_OBLRST                ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_OBLRSTF_Pos)      /*!< Option Byte Loader reset flag                    */
-#define RCC_FLAG_PINRST                ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_PINRSTF_Pos)      /*!< Pin reset flag (NRST pin)                        */
-#define RCC_FLAG_BORRST                ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_BORRSTF_Pos)      /*!< BOR reset flag                                   */
-#define RCC_FLAG_SFTRST                ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_SFTRSTF_Pos)      /*!< Software Reset flag                              */
-#define RCC_FLAG_IWDGRST               ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_IWDGRSTF_Pos)     /*!< Watchdog reset flag                              */
-#define RCC_FLAG_WWDGRST               ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_WWDGRSTF_Pos)     /*!< Window watchdog reset flag                       */
-#define RCC_FLAG_LPWRRST               ((CSR_REG_INDEX << REG_INDEX_POS) | RCC_CSR_LPWRRSTF_Pos)     /*!< Low-Power reset flag                             */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSEDrive_Config LSE Drive Configuration
-  * @{
-  */
-#define RCC_LSEDRIVE_LOW                 LL_RCC_LSEDRIVE_LOW         /*!< LSE low drive capability         */
-#define RCC_LSEDRIVE_MEDIUMLOW           LL_RCC_LSEDRIVE_MEDIUMLOW   /*!< LSE medium low drive capability  */
-#define RCC_LSEDRIVE_MEDIUMHIGH          LL_RCC_LSEDRIVE_MEDIUMHIGH  /*!< LSE medium high drive capability */
-#define RCC_LSEDRIVE_HIGH                LL_RCC_LSEDRIVE_HIGH        /*!< LSE high drive capability        */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock
-  * @{
-  */
-#define RCC_STOP_WAKEUPCLOCK_MSI       LL_RCC_STOP_WAKEUPCLOCK_MSI  /*!< MSI selected after wake-up from STOP */
-#define RCC_STOP_WAKEUPCLOCK_HSI       LL_RCC_STOP_WAKEUPCLOCK_HSI  /*!< HSI selected after wake-up from STOP */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
-  * @{
-  */
-
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_DMA1_CLK_ENABLE()                 LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)
-#define __HAL_RCC_DMA2_CLK_ENABLE()                 LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)
-#define __HAL_RCC_DMAMUX1_CLK_ENABLE()              LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
-#define __HAL_RCC_CRC_CLK_ENABLE()                  LL_C2_AHB1_GRP1_EnableClock(LL_C2_AHB1_GRP1_PERIPH_CRC)
-
-#define __HAL_RCC_DMA1_CLK_DISABLE()                LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)
-#define __HAL_RCC_DMA2_CLK_DISABLE()                LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)
-#define __HAL_RCC_DMAMUX1_CLK_DISABLE()             LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
-#define __HAL_RCC_CRC_CLK_DISABLE()                 LL_C2_AHB1_GRP1_DisableClock(LL_C2_AHB1_GRP1_PERIPH_CRC)
-#else
-#define __HAL_RCC_DMA1_CLK_ENABLE()                 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1)
-#define __HAL_RCC_DMA2_CLK_ENABLE()                 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA2)
-#define __HAL_RCC_DMAMUX1_CLK_ENABLE()              LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)
-#define __HAL_RCC_CRC_CLK_ENABLE()                  LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_CRC)
-
-#define __HAL_RCC_DMA1_CLK_DISABLE()                LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA1)
-#define __HAL_RCC_DMA2_CLK_DISABLE()                LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMA2)
-#define __HAL_RCC_DMAMUX1_CLK_DISABLE()             LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)
-#define __HAL_RCC_CRC_CLK_DISABLE()                 LL_AHB1_GRP1_DisableClock(LL_AHB1_GRP1_PERIPH_CRC)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_GPIOA_CLK_ENABLE()                LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
-#define __HAL_RCC_GPIOB_CLK_ENABLE()                LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
-#define __HAL_RCC_GPIOC_CLK_ENABLE()                LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
-#define __HAL_RCC_GPIOH_CLK_ENABLE()                LL_C2_AHB2_GRP1_EnableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
-
-#define __HAL_RCC_GPIOA_CLK_DISABLE()               LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
-#define __HAL_RCC_GPIOB_CLK_DISABLE()               LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
-#define __HAL_RCC_GPIOC_CLK_DISABLE()               LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
-#define __HAL_RCC_GPIOH_CLK_DISABLE()               LL_C2_AHB2_GRP1_DisableClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
-#else
-#define __HAL_RCC_GPIOA_CLK_ENABLE()                LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA)
-#define __HAL_RCC_GPIOB_CLK_ENABLE()                LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB)
-#define __HAL_RCC_GPIOC_CLK_ENABLE()                LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOC)
-#define __HAL_RCC_GPIOH_CLK_ENABLE()                LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOH)
-
-#define __HAL_RCC_GPIOA_CLK_DISABLE()               LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOA)
-#define __HAL_RCC_GPIOB_CLK_DISABLE()               LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOB)
-#define __HAL_RCC_GPIOC_CLK_DISABLE()               LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOC)
-#define __HAL_RCC_GPIOH_CLK_DISABLE()               LL_AHB2_GRP1_DisableClock(LL_AHB2_GRP1_PERIPH_GPIOH)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_PKA_CLK_ENABLE()                  LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_PKA)
-#define __HAL_RCC_AES_CLK_ENABLE()                  LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_AES)
-#define __HAL_RCC_RNG_CLK_ENABLE()                  LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_RNG)
-#define __HAL_RCC_HSEM_CLK_ENABLE()                 LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)
-#define __HAL_RCC_IPCC_CLK_ENABLE()                 LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)
-#define __HAL_RCC_FLASH_CLK_ENABLE()                LL_C2_AHB3_GRP1_EnableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)
-
-#define __HAL_RCC_PKA_CLK_DISABLE()                 LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_PKA)
-#define __HAL_RCC_AES_CLK_DISABLE()                 LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_AES)
-#define __HAL_RCC_RNG_CLK_DISABLE()                 LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_RNG)
-#define __HAL_RCC_HSEM_CLK_DISABLE()                LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)
-#define __HAL_RCC_IPCC_CLK_DISABLE()                LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)
-#define __HAL_RCC_FLASH_CLK_DISABLE()               LL_C2_AHB3_GRP1_DisableClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)
-#else
-#define __HAL_RCC_PKA_CLK_ENABLE()                  LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_PKA)
-#define __HAL_RCC_AES_CLK_ENABLE()                  LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_AES)
-#define __HAL_RCC_RNG_CLK_ENABLE()                  LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_RNG)
-#define __HAL_RCC_HSEM_CLK_ENABLE()                 LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_HSEM)
-#define __HAL_RCC_IPCC_CLK_ENABLE()                 LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC)
-#define __HAL_RCC_FLASH_CLK_ENABLE()                LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_FLASH)
-
-#define __HAL_RCC_PKA_CLK_DISABLE()                 LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_PKA)
-#define __HAL_RCC_AES_CLK_DISABLE()                 LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_AES)
-#define __HAL_RCC_RNG_CLK_DISABLE()                 LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_RNG)
-#define __HAL_RCC_HSEM_CLK_DISABLE()                LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_HSEM)
-#define __HAL_RCC_IPCC_CLK_DISABLE()                LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_IPCC)
-#define __HAL_RCC_FLASH_CLK_DISABLE()               LL_AHB3_GRP1_DisableClock(LL_AHB3_GRP1_PERIPH_FLASH)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_TIM2_CLK_ENABLE()                 LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_TIM2)
-#define __HAL_RCC_RTCAPB_CLK_ENABLE()               LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
-#define __HAL_RCC_SPI2_CLK_ENABLE()                 LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_SPI2)
-#define __HAL_RCC_USART2_CLK_ENABLE()               LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_USART2)
-#define __HAL_RCC_I2C1_CLK_ENABLE()                 LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C1)
-#define __HAL_RCC_I2C2_CLK_ENABLE()                 LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C2)
-#define __HAL_RCC_I2C3_CLK_ENABLE()                 LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_I2C3)
-#define __HAL_RCC_DAC_CLK_ENABLE()                  LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_DAC)
-#define __HAL_RCC_LPTIM1_CLK_ENABLE()               LL_C2_APB1_GRP1_EnableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
-
-#define __HAL_RCC_LPTIM2_CLK_ENABLE()               LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
-#define __HAL_RCC_LPTIM3_CLK_ENABLE()               LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM3)
-#define __HAL_RCC_LPUART1_CLK_ENABLE()              LL_C2_APB1_GRP2_EnableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)
-
-#define __HAL_RCC_TIM2_CLK_DISABLE()                LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_TIM2)
-#define __HAL_RCC_RTCAPB_CLK_DISABLE()              LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
-#define __HAL_RCC_SPI2_CLK_DISABLE()                LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_SPI2)
-#define __HAL_RCC_USART2_CLK_DISABLE()              LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_USART2)
-#define __HAL_RCC_I2C1_CLK_DISABLE()                LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C1)
-#define __HAL_RCC_I2C2_CLK_DISABLE()                LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C2)
-#define __HAL_RCC_I2C3_CLK_DISABLE()                LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_I2C3)
-#define __HAL_RCC_DAC_CLK_DISABLE()                 LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_DAC)
-#define __HAL_RCC_LPTIM1_CLK_DISABLE()              LL_C2_APB1_GRP1_DisableClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
-
-#define __HAL_RCC_LPTIM2_CLK_DISABLE()              LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
-#define __HAL_RCC_LPTIM3_CLK_DISABLE()              LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPTIM3)
-#define __HAL_RCC_LPUART1_CLK_DISABLE()             LL_C2_APB1_GRP2_DisableClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)
-#else
-#define __HAL_RCC_TIM2_CLK_ENABLE()                 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2)
-#define __HAL_RCC_RTCAPB_CLK_ENABLE()               LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB)
-#define __HAL_RCC_SPI2_CLK_ENABLE()                 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_SPI2)
-#define __HAL_RCC_USART2_CLK_ENABLE()               LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2)
-#define __HAL_RCC_I2C1_CLK_ENABLE()                 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C1)
-#define __HAL_RCC_I2C2_CLK_ENABLE()                 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C2)
-#define __HAL_RCC_I2C3_CLK_ENABLE()                 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_I2C3)
-#define __HAL_RCC_DAC_CLK_ENABLE()                  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DAC)
-#define __HAL_RCC_LPTIM1_CLK_ENABLE()               LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1)
-
-#define __HAL_RCC_LPTIM2_CLK_ENABLE()               LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM2)
-#define __HAL_RCC_LPTIM3_CLK_ENABLE()               LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPTIM3)
-#define __HAL_RCC_LPUART1_CLK_ENABLE()              LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_LPUART1)
-
-#define __HAL_RCC_TIM2_CLK_DISABLE()                LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2)
-#define __HAL_RCC_RTCAPB_CLK_DISABLE()              LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_RTCAPB)
-#define __HAL_RCC_SPI2_CLK_DISABLE()                LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_SPI2)
-#define __HAL_RCC_USART2_CLK_DISABLE()              LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_USART2)
-#define __HAL_RCC_I2C1_CLK_DISABLE()                LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C1)
-#define __HAL_RCC_I2C2_CLK_DISABLE()                LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C2)
-#define __HAL_RCC_I2C3_CLK_DISABLE()                LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_I2C3)
-#define __HAL_RCC_DAC_CLK_DISABLE()                 LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_DAC)
-#define __HAL_RCC_LPTIM1_CLK_DISABLE()              LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1)
-
-#define __HAL_RCC_LPTIM2_CLK_DISABLE()              LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPTIM2)
-#define __HAL_RCC_LPTIM3_CLK_DISABLE()              LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPTIM3)
-#define __HAL_RCC_LPUART1_CLK_DISABLE()             LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_LPUART1)
-#endif /* CORE_CM0PLUS */
-
-#define __HAL_RCC_WWDG_CLK_ENABLE()                 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_WWDG)
-
-#define __HAL_RCC_WWDG_CLK_DISABLE()                LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_WWDG)
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_ADC_CLK_ENABLE()                  LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_ADC)
-#define __HAL_RCC_TIM1_CLK_ENABLE()                 LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
-#define __HAL_RCC_SPI1_CLK_ENABLE()                 LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
-#define __HAL_RCC_USART1_CLK_ENABLE()               LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_USART1)
-#define __HAL_RCC_TIM16_CLK_ENABLE()                LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM16)
-#define __HAL_RCC_TIM17_CLK_ENABLE()                LL_C2_APB2_GRP1_EnableClock(LL_C2_APB2_GRP1_PERIPH_TIM17)
-
-#define __HAL_RCC_ADC_CLK_DISABLE()                 LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_ADC)
-#define __HAL_RCC_TIM1_CLK_DISABLE()                LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
-#define __HAL_RCC_SPI1_CLK_DISABLE()                LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
-#define __HAL_RCC_USART1_CLK_DISABLE()              LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_USART1)
-#define __HAL_RCC_TIM16_CLK_DISABLE()               LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM16)
-#define __HAL_RCC_TIM17_CLK_DISABLE()               LL_C2_APB2_GRP1_DisableClock(LL_C2_APB2_GRP1_PERIPH_TIM17)
-#else
-#define __HAL_RCC_ADC_CLK_ENABLE()                  LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC)
-#define __HAL_RCC_TIM1_CLK_ENABLE()                 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM1)
-#define __HAL_RCC_SPI1_CLK_ENABLE()                 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1)
-#define __HAL_RCC_USART1_CLK_ENABLE()               LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1)
-#define __HAL_RCC_TIM16_CLK_ENABLE()                LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM16)
-#define __HAL_RCC_TIM17_CLK_ENABLE()                LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_TIM17)
-
-#define __HAL_RCC_ADC_CLK_DISABLE()                 LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_ADC)
-#define __HAL_RCC_TIM1_CLK_DISABLE()                LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM1)
-#define __HAL_RCC_SPI1_CLK_DISABLE()                LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_SPI1)
-#define __HAL_RCC_USART1_CLK_DISABLE()              LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_USART1)
-#define __HAL_RCC_TIM16_CLK_DISABLE()               LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM16)
-#define __HAL_RCC_TIM17_CLK_DISABLE()               LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_TIM17)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-
-/** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the APB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_SUBGHZSPI_CLK_ENABLE()            LL_C2_APB3_GRP1_EnableClock(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI)
-
-#define __HAL_RCC_SUBGHZSPI_CLK_DISABLE()           LL_C2_APB3_GRP1_DisableClock(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI)
-#else
-#define __HAL_RCC_SUBGHZSPI_CLK_ENABLE()            LL_APB3_GRP1_EnableClock(LL_APB3_GRP1_PERIPH_SUBGHZSPI)
-
-#define __HAL_RCC_SUBGHZSPI_CLK_DISABLE()           LL_APB3_GRP1_DisableClock(LL_APB3_GRP1_PERIPH_SUBGHZSPI)
-#endif /* CORE_CM0PLUS */
-
-
-/* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */
-#define __HAL_RCC_SUBGHZ_CLK_ENABLE()               __HAL_RCC_SUBGHZSPI_CLK_ENABLE()
-#define __HAL_RCC_SUBGHZ_CLK_DISABLE()              __HAL_RCC_SUBGHZSPI_CLK_DISABLE()
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the AHB1 peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED()             LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA1)
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED()             LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMA2)
-#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED()          LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()              LL_C2_AHB1_GRP1_IsEnabledClock(LL_C2_AHB1_GRP1_PERIPH_CRC)
-#else
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED()             LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA1)
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED()             LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMA2)
-#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED()          LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_DMAMUX1)
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()              LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_CRC)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the AHB2 peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()            LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()            LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()            LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
-#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()            LL_C2_AHB2_GRP1_IsEnabledClock(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
-#else
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()            LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOA)
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()            LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOB)
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()            LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOC)
-#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()            LL_AHB2_GRP1_IsEnabledClock(LL_AHB2_GRP1_PERIPH_GPIOH)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the AHB3 peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_PKA_IS_CLK_ENABLED()              LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_PKA)
-#define __HAL_RCC_AES_IS_CLK_ENABLED()              LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_AES)
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()              LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_RNG)
-#define __HAL_RCC_HSEM_IS_CLK_ENABLED()             LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_HSEM)
-#define __HAL_RCC_IPCC_IS_CLK_ENABLED()             LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_IPCC)
-#define __HAL_RCC_FLASH_IS_CLK_ENABLED()            LL_C2_AHB3_GRP1_IsEnabledClock(LL_C2_AHB3_GRP1_PERIPH_FLASH)
-#else
-#define __HAL_RCC_PKA_IS_CLK_ENABLED()              LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_PKA)
-#define __HAL_RCC_AES_IS_CLK_ENABLED()              LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_AES)
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()              LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_RNG)
-#define __HAL_RCC_HSEM_IS_CLK_ENABLED()             LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_HSEM)
-#define __HAL_RCC_IPCC_IS_CLK_ENABLED()             LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_IPCC)
-#define __HAL_RCC_FLASH_IS_CLK_ENABLED()            LL_AHB3_GRP1_IsEnabledClock(LL_AHB3_GRP1_PERIPH_FLASH)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the APB1 peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()             LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_TIM2)
-#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()           LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED()             LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_SPI2)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED()           LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_USART2)
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED()             LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C1)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED()             LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C2)
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()             LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_I2C3)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()              LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_DAC)
-#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()           LL_C2_APB1_GRP1_IsEnabledClock(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
-
-#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()           LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
-#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED()           LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPTIM3)
-#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()          LL_C2_APB1_GRP2_IsEnabledClock(LL_C2_APB1_GRP2_PERIPH_LPUART1)
-#else
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()             LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_TIM2)
-#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()           LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_RTCAPB)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED()             LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_SPI2)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED()           LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_USART2)
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED()             LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C1)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED()             LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C2)
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()             LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_I2C3)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()              LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_DAC)
-#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()           LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_LPTIM1)
-
-#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()           LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM2)
-#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED()           LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPTIM3)
-#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()          LL_APB1_GRP2_IsEnabledClock(LL_APB1_GRP2_PERIPH_LPUART1)
-#endif /* CORE_CM0PLUS */
-
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED()             LL_APB1_GRP1_IsEnabledClock(LL_APB1_GRP1_PERIPH_WWDG)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the APB2 peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_ADC_IS_CLK_ENABLED()              LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_ADC)
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED()             LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM1)
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED()             LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_SPI1)
-#define __HAL_RCC_USART1_IS_CLK_ENABLED()           LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_USART1)
-#define __HAL_RCC_TIM16_IS_CLK_ENABLED()            LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM16)
-#define __HAL_RCC_TIM17_IS_CLK_ENABLED()            LL_C2_APB2_GRP1_IsEnabledClock(LL_C2_APB2_GRP1_PERIPH_TIM17)
-#else
-#define __HAL_RCC_ADC_IS_CLK_ENABLED()              LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_ADC)
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED()             LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM1)
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED()             LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_SPI1)
-#define __HAL_RCC_USART1_IS_CLK_ENABLED()           LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_USART1)
-#define __HAL_RCC_TIM16_IS_CLK_ENABLED()            LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM16)
-#define __HAL_RCC_TIM17_IS_CLK_ENABLED()            LL_APB2_GRP1_IsEnabledClock(LL_APB2_GRP1_PERIPH_TIM17)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB3_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status
-  * @brief  Check whether the APB3 peripheral clock is enabled or not.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_SUBGHZSPI_IS_CLK_ENABLED()        LL_C2_APB3_GRP1_IsEnabledClock(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI)
-#else
-#define __HAL_RCC_SUBGHZSPI_IS_CLK_ENABLED()        LL_APB3_GRP1_IsEnabledClock(LL_APB3_GRP1_PERIPH_SUBGHZSPI)
-#endif /* CORE_CM0PLUS */
-
-/* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */
-#define __HAL_RCC_SUBGHZ_IS_CLK_ENABLED()           __HAL_RCC_SUBGHZSPI_IS_CLK_ENABLED()
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB1_FORCE_RESET()                LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_ALL)
-#define __HAL_RCC_DMA1_FORCE_RESET()                LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1)
-#define __HAL_RCC_DMA2_FORCE_RESET()                LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2)
-#define __HAL_RCC_DMAMUX1_FORCE_RESET()             LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMAMUX1)
-#define __HAL_RCC_CRC_FORCE_RESET()                 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC)
-
-#define __HAL_RCC_AHB1_RELEASE_RESET()              LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ALL)
-#define __HAL_RCC_DMA1_RELEASE_RESET()              LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1)
-#define __HAL_RCC_DMA2_RELEASE_RESET()              LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2)
-#define __HAL_RCC_DMAMUX1_RELEASE_RESET()           LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMAMUX1)
-#define __HAL_RCC_CRC_RELEASE_RESET()               LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()                LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ALL)
-#define __HAL_RCC_GPIOA_FORCE_RESET()               LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA)
-#define __HAL_RCC_GPIOB_FORCE_RESET()               LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB)
-#define __HAL_RCC_GPIOC_FORCE_RESET()               LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC)
-#define __HAL_RCC_GPIOH_FORCE_RESET()               LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH)
-
-#define __HAL_RCC_AHB2_RELEASE_RESET()              LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ALL)
-#define __HAL_RCC_GPIOA_RELEASE_RESET()             LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA)
-#define __HAL_RCC_GPIOB_RELEASE_RESET()             LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB)
-#define __HAL_RCC_GPIOC_RELEASE_RESET()             LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC)
-#define __HAL_RCC_GPIOH_RELEASE_RESET()             LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */
-#if defined (DUAL_CORE)
-#define __HAL_RCC_IPCC_FORCE_RESET()                LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_IPCC)
-#define __HAL_RCC_IPCC_RELEASE_RESET()              LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_IPCC)
-#endif /* DUAL_CORE */
-
-#define __HAL_RCC_AHB3_FORCE_RESET()                LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_ALL)
-#define __HAL_RCC_PKA_FORCE_RESET()                 LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_PKA)
-#define __HAL_RCC_AES_FORCE_RESET()                 LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_AES)
-#define __HAL_RCC_RNG_FORCE_RESET()                 LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_RNG)
-#define __HAL_RCC_HSEM_FORCE_RESET()                LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_HSEM)
-#define __HAL_RCC_FLASH_FORCE_RESET()               LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_FLASH)
-
-#define __HAL_RCC_AHB3_RELEASE_RESET()              LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_ALL)
-#define __HAL_RCC_PKA_RELEASE_RESET()               LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_PKA)
-#define __HAL_RCC_AES_RELEASE_RESET()               LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_AES)
-#define __HAL_RCC_RNG_RELEASE_RESET()               LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_RNG)
-#define __HAL_RCC_HSEM_RELEASE_RESET()              LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_HSEM)
-#define __HAL_RCC_FLASH_RELEASE_RESET()             LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_FLASH)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB1L_FORCE_RESET()               LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_ALL)
-#define __HAL_RCC_TIM2_FORCE_RESET()                LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2)
-#define __HAL_RCC_SPI2_FORCE_RESET()                LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2)
-#define __HAL_RCC_USART2_FORCE_RESET()              LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2)
-#define __HAL_RCC_I2C1_FORCE_RESET()                LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1)
-#define __HAL_RCC_I2C2_FORCE_RESET()                LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2)
-#define __HAL_RCC_I2C3_FORCE_RESET()                LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3)
-#define __HAL_RCC_DAC_FORCE_RESET()                 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC)
-#define __HAL_RCC_LPTIM1_FORCE_RESET()              LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1)
-
-#define __HAL_RCC_APB1H_FORCE_RESET()               LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ALL)
-#define __HAL_RCC_LPUART1_FORCE_RESET()             LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPUART1)
-#define __HAL_RCC_LPTIM2_FORCE_RESET()              LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2)
-#define __HAL_RCC_LPTIM3_FORCE_RESET()              LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM3)
-
-#define __HAL_RCC_APB1_FORCE_RESET() do {                                \
-                                           __HAL_RCC_APB1L_FORCE_RESET();\
-                                           __HAL_RCC_APB1H_FORCE_RESET();\
-                                        } while(0U)
-
-#define __HAL_RCC_APB1L_RELEASE_RESET()             LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_ALL)
-#define __HAL_RCC_TIM2_RELEASE_RESET()              LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2)
-#define __HAL_RCC_USART2_RELEASE_RESET()            LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2)
-#define __HAL_RCC_SPI2_RELEASE_RESET()              LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2)
-#define __HAL_RCC_I2C1_RELEASE_RESET()              LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1)
-#define __HAL_RCC_I2C2_RELEASE_RESET()              LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2)
-#define __HAL_RCC_I2C3_RELEASE_RESET()              LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3)
-#define __HAL_RCC_DAC_RELEASE_RESET()               LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC)
-#define __HAL_RCC_LPTIM1_RELEASE_RESET()            LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1)
-
-#define __HAL_RCC_APB1H_RELEASE_RESET()             LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ALL)
-#define __HAL_RCC_LPUART1_RELEASE_RESET()           LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPUART1)
-#define __HAL_RCC_LPTIM2_RELEASE_RESET()            LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2)
-#define __HAL_RCC_LPTIM3_RELEASE_RESET()            LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM3)
-
-#define __HAL_RCC_APB1_RELEASE_RESET() do {                                \
-                                            __HAL_RCC_APB1L_RELEASE_RESET();\
-                                            __HAL_RCC_APB1H_RELEASE_RESET();\
-                                          } while(0U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB2_FORCE_RESET()                LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ALL)
-#define __HAL_RCC_ADC_FORCE_RESET()                 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC)
-#define __HAL_RCC_TIM1_FORCE_RESET()                LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1)
-#define __HAL_RCC_SPI1_FORCE_RESET()                LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1)
-#define __HAL_RCC_USART1_FORCE_RESET()              LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1)
-#define __HAL_RCC_TIM16_FORCE_RESET()               LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16)
-#define __HAL_RCC_TIM17_FORCE_RESET()               LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17)
-
-#define __HAL_RCC_APB2_RELEASE_RESET()              LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ALL)
-#define __HAL_RCC_ADC_RELEASE_RESET()               LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC)
-#define __HAL_RCC_TIM1_RELEASE_RESET()              LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1)
-#define __HAL_RCC_SPI1_RELEASE_RESET()              LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1)
-#define __HAL_RCC_USART1_RELEASE_RESET()            LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1)
-#define __HAL_RCC_TIM16_RELEASE_RESET()             LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16)
-#define __HAL_RCC_TIM17_RELEASE_RESET()             LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset
-  * @brief  Force or release APB3 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB3_FORCE_RESET()                LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_ALL)
-#define __HAL_RCC_SUBGHZSPI_FORCE_RESET()           LL_APB3_GRP1_ForceReset(LL_APB3_GRP1_PERIPH_SUBGHZSPI)
-
-#define __HAL_RCC_APB3_RELEASE_RESET()              LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_ALL)
-#define __HAL_RCC_SUBGHZSPI_RELEASE_RESET()         LL_APB3_GRP1_ReleaseReset(LL_APB3_GRP1_PERIPH_SUBGHZSPI)
-
-/* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */
-#define __HAL_RCC_SUBGHZ_FORCE_RESET()              __HAL_RCC_SUBGHZSPI_FORCE_RESET()
-#define __HAL_RCC_SUBGHZ_RELEASE_RESET()            __HAL_RCC_SUBGHZSPI_RELEASE_RESET()
-/**
-  * @}
-  */
-
-/** @defgroup RCC_SUBGHZ_Force_Release_Reset SUBGHZ Radio Force Release Reset
-  * @brief  Force or release SUBGHZ Radio reset.
-  * @{
-  */
-#define __HAL_RCC_SUBGHZ_RADIO_FORCE_RESET()              SET_BIT(RCC->CSR, RCC_CSR_RFRST)
-
-#define __HAL_RCC_SUBGHZ_RADIO_RELEASE_RESET()            CLEAR_BIT(RCC->CSR, RCC_CSR_RFRST)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()           LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1)
-#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()           LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2)
-#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE()        LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()            LL_C2_AHB1_GRP1_EnableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC)
-
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()          LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA1)
-#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()          LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMA2)
-#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE()       LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_DMAMUX1)
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()           LL_C2_AHB1_GRP1_DisableClockSleep(LL_C2_AHB1_GRP1_PERIPH_CRC)
-#else
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()           LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1)
-#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()           LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2)
-#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE()        LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1)
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()            LL_AHB1_GRP1_EnableClockSleep(LL_AHB1_GRP1_PERIPH_CRC)
-
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()          LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA1)
-#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()          LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMA2)
-#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE()       LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1)
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()           LL_AHB1_GRP1_DisableClockSleep(LL_AHB1_GRP1_PERIPH_CRC)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()          LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()          LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()          LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()          LL_C2_AHB2_GRP1_EnableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()         LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()         LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()         LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()         LL_C2_AHB2_GRP1_DisableClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
-#else
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()          LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA)
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()          LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB)
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()          LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC)
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()          LL_AHB2_GRP1_EnableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()         LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA)
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()         LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB)
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()         LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC)
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()         LL_AHB2_GRP1_DisableClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE()            LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA)
-#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()            LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES)
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()            LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG)
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()          LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM1)
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()          LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2)
-#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()          LL_C2_AHB3_GRP1_EnableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH)
-
-#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE()           LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_PKA)
-#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()           LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_AES)
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()           LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_RNG)
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()         LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM1)
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()         LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_SRAM2)
-#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()         LL_C2_AHB3_GRP1_DisableClockSleep(LL_C2_AHB3_GRP1_PERIPH_FLASH)
-#else
-#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE()            LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_PKA)
-#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()            LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_AES)
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()            LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_RNG)
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()          LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM1)
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()          LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2)
-#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()          LL_AHB3_GRP1_EnableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH)
-
-#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE()           LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_PKA)
-#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()           LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_AES)
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()           LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_RNG)
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()         LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM1)
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()         LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2)
-#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()         LL_AHB3_GRP1_DisableClockSleep(LL_AHB3_GRP1_PERIPH_FLASH)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()           LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2)
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()         LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()           LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2)
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()         LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_USART2)
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()           LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1)
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()           LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C2)
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()           LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3)
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()            LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_DAC)
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()         LL_C2_APB1_GRP1_EnableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
-
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()        LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1)
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()         LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
-#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE()         LL_C2_APB1_GRP2_EnableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM3)
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()          LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2)
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()        LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()        LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_USART2)
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()          LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2)
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()          LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1)
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()          LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C2)
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()          LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3)
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()          LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_DAC)
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()        LL_C2_APB1_GRP1_DisableClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
-
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()       LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1)
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()        LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
-#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE()        LL_C2_APB1_GRP2_DisableClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM3)
-#else
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()           LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_TIM2)
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()         LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB)
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()           LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_SPI2)
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()         LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_USART2)
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()           LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C1)
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()           LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C2)
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()           LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_I2C3)
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()            LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_DAC)
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()         LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1)
-
-#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()        LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1)
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()         LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2)
-#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE()         LL_APB1_GRP2_EnableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM3)
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()          LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_TIM2)
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()        LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB)
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()        LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_USART2)
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()          LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_SPI2)
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()          LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C1)
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()          LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C2)
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()          LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_I2C3)
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()           LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_DAC)
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()        LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1)
-
-#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()       LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPUART1)
-#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()        LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2)
-#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE()        LL_APB1_GRP2_DisableClockSleep(LL_APB1_GRP2_PERIPH_LPTIM3)
-#endif /* CORE_CM0PLUS */
-
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()           LL_APB1_GRP1_EnableClockSleep(LL_APB1_GRP1_PERIPH_WWDG)
-
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()          LL_APB1_GRP1_DisableClockSleep(LL_APB1_GRP1_PERIPH_WWDG)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE()            LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC)
-#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()           LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()           LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()         LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)
-#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()          LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16)
-#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()          LL_C2_APB2_GRP1_EnableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17)
-
-#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE()           LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC)
-#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()          LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()          LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()        LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)
-#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()         LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16)
-#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()         LL_C2_APB2_GRP1_DisableClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17)
-#else
-#define __HAL_RCC_ADC_CLK_SLEEP_ENABLE()            LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_ADC)
-#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()           LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM1)
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()           LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_SPI1)
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()         LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_USART1)
-#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()          LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM16)
-#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()          LL_APB2_GRP1_EnableClockSleep(LL_APB2_GRP1_PERIPH_TIM17)
-
-#define __HAL_RCC_ADC_CLK_SLEEP_DISABLE()           LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_ADC)
-#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()          LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM1)
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()          LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_SPI1)
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()        LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_USART1)
-#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()         LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM16)
-#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()         LL_APB2_GRP1_DisableClockSleep(LL_APB2_GRP1_PERIPH_TIM17)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable
-  * @brief  Enable or disable the APB3 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_SUBGHZSPI_CLK_SLEEP_ENABLE()      LL_C2_APB3_GRP1_EnableClockSleep(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI)
-
-#define __HAL_RCC_SUBGHZSPI_CLK_SLEEP_DISABLE()     LL_C2_APB3_GRP1_DisableClockSleep(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI)
-#else
-#define __HAL_RCC_SUBGHZSPI_CLK_SLEEP_ENABLE()      LL_APB3_GRP1_EnableClockSleep(LL_APB3_GRP1_PERIPH_SUBGHZSPI)
-
-#define __HAL_RCC_SUBGHZSPI_CLK_SLEEP_DISABLE()     LL_APB3_GRP1_DisableClockSleep(LL_APB3_GRP1_PERIPH_SUBGHZSPI)
-#endif /* CORE_CM0PLUS */
-
-/* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */
-#define __HAL_RCC_SUBGHZ_CLK_SLEEP_ENABLE()         __HAL_RCC_SUBGHZSPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_SUBGHZ_CLK_SLEEP_DISABLE()        __HAL_RCC_SUBGHZSPI_CLK_SLEEP_DISABLE()
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()       LL_C2_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMA1)
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()       LL_C2_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMA2)
-#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED()    LL_C2_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1)
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()        LL_C2_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_CRC)
-#else
-#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()       LL_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMA1)
-#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()       LL_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMA2)
-#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED()    LL_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_DMAMUX1)
-#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()        LL_AHB1_GRP1_IsEnabledClockSleep(LL_AHB1_GRP1_PERIPH_CRC)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()      LL_C2_AHB2_GRP1_IsEnabledClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOA)
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()      LL_C2_AHB2_GRP1_IsEnabledClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOB)
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()      LL_C2_AHB2_GRP1_IsEnabledClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOC)
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()      LL_C2_AHB2_GRP1_IsEnabledClockSleep(LL_C2_AHB2_GRP1_PERIPH_GPIOH)
-#else
-#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()      LL_AHB2_GRP1_IsEnabledClockSleep(LL_AHB2_GRP1_PERIPH_GPIOA)
-#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()      LL_AHB2_GRP1_IsEnabledClockSleep(LL_AHB2_GRP1_PERIPH_GPIOB)
-#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()      LL_AHB2_GRP1_IsEnabledClockSleep(LL_AHB2_GRP1_PERIPH_GPIOC)
-#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()      LL_AHB2_GRP1_IsEnabledClockSleep(LL_AHB2_GRP1_PERIPH_GPIOH)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED()        LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_PKA)
-#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()        LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_AES)
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()        LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_RNG)
-#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()      LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_SRAM1)
-#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()      LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2)
-#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()      LL_C2_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_FLASH)
-#else
-#define __HAL_RCC_PKA_IS_CLK_SLEEP_ENABLED()        LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_PKA)
-#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()        LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_AES)
-#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()        LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_RNG)
-#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED()      LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_SRAM1)
-#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED()      LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_SRAM2)
-#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()      LL_AHB3_GRP1_IsEnabledClockSleep(LL_AHB3_GRP1_PERIPH_FLASH)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()       LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_TIM2)
-#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED()     LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_RTCAPB)
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()     LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_USART2)
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()       LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_SPI2)
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()       LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C1)
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()       LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C2)
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()       LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_I2C3)
-#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED()        LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_DAC)
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()     LL_C2_APB1_GRP1_IsEnabledClockSleep(LL_C2_APB1_GRP1_PERIPH_LPTIM1)
-
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()    LL_C2_APB1_GRP2_IsEnabledClockSleep(LL_C2_APB1_GRP2_PERIPH_LPUART1)
-#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()     LL_C2_APB1_GRP2_IsEnabledClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM2)
-#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED()     LL_C2_APB1_GRP2_IsEnabledClockSleep(LL_C2_APB1_GRP2_PERIPH_LPTIM3)
-#else
-#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()       LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_TIM2)
-#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED()     LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_RTCAPB)
-#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()     LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_USART2)
-#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()       LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_SPI2)
-#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()       LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_I2C1)
-#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()       LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_I2C2)
-#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()       LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_I2C3)
-#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED()        LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_DAC)
-#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()     LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_LPTIM1)
-
-#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()    LL_APB1_GRP2_IsEnabledClockSleep(LL_APB1_GRP2_PERIPH_LPUART1)
-#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()     LL_APB1_GRP2_IsEnabledClockSleep(LL_APB1_GRP2_PERIPH_LPTIM2)
-#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED()     LL_APB1_GRP2_IsEnabledClockSleep(LL_APB1_GRP2_PERIPH_LPTIM3)
-#endif /* CORE_CM0PLUS */
-
-#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED()       LL_APB1_GRP1_IsEnabledClockSleep(LL_APB1_GRP1_PERIPH_WWDG)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED()        LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_ADC)
-#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()       LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM1)
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()       LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_SPI1)
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()     LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_USART1)
-#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()      LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM16)
-#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()      LL_C2_APB2_GRP1_IsEnabledClockSleep(LL_C2_APB2_GRP1_PERIPH_TIM17)
-#else
-#define __HAL_RCC_ADC_IS_CLK_SLEEP_ENABLED()        LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_ADC)
-#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()       LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_TIM1)
-#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()       LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_SPI1)
-#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()     LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_USART1)
-#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()      LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_TIM16)
-#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()      LL_APB2_GRP1_IsEnabledClockSleep(LL_APB2_GRP1_PERIPH_TIM17)
-#endif /* CORE_CM0PLUS */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable_Status APB3 Peripheral Clock Sleep Enabled or Disabled Status
-  * @brief  Check whether the APB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_SUBGHZSPI_IS_CLK_SLEEP_ENABLED()    \
-  LL_C2_APB3_GRP1_IsEnabledClockSleep(LL_C2_APB3_GRP1_PERIPH_SUBGHZSPI)
-#else
-#define __HAL_RCC_SUBGHZSPI_IS_CLK_SLEEP_ENABLED()    \
-  LL_APB3_GRP1_IsEnabledClockSleep(LL_APB3_GRP1_PERIPH_SUBGHZSPI)
-#endif /* CORE_CM0PLUS */
-
-/* Aliases used by CubeMX for HAL SUBGHZ Init, MspInit and DeInit generation */
-#define __HAL_RCC_SUBGHZ_IS_CLK_SLEEP_ENABLED()       __HAL_RCC_SUBGHZSPI_IS_CLK_SLEEP_ENABLED()
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
-  * @{
-  */
-
-/** @brief  Macros to force or release the Backup domain reset.
-  * @note   This function resets the RTC peripheral (including the backup registers)
-  *         and the RTC clock source selection in RCC_CSR register.
-  * @note   The SRAM2 is not affected by this reset.
-  * @retval None
-  */
-#define __HAL_RCC_BACKUPRESET_FORCE()   LL_RCC_ForceBackupDomainReset()
-#define __HAL_RCC_BACKUPRESET_RELEASE() LL_RCC_ReleaseBackupDomainReset()
-/**
-  * @}
-  */
-
-/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
-  * @{
-  */
-
-/** @brief  Macros to enable or disable the RTC clock.
-  * @note   As the RTC is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using
-  *         HAL_PWR_EnableBkUpAccess() function before to configure the RTC
-  *         (to be done once after reset).
-  * @note   These macros must be used after the RTC clock source was selected.
-  * @retval None
-  */
-#define __HAL_RCC_RTC_ENABLE()         LL_RCC_EnableRTC()
-#define __HAL_RCC_RTC_DISABLE()        LL_RCC_DisableRTC()
-/**
-  * @}
-  */
-
-/** @brief  Macros to enable the Internal High Speed oscillator (HSI).
-  * @note   The HSI is stopped by hardware when entering STOP, STANDBY or SHUTDOWN modes.
-  *         It is enabled by hardware to force the HSI oscillator ON when STOPWUCK=1
-  *         or HSIASFS = 1 when leaving Stop modes, or in case of failure of the HSE
-  *         crystal oscillator and Security System CSS is enabled.
-  * @note   After enabling the HSI, the application software should wait on HSIRDY
-  *         flag to be set indicating that HSI clock is stable and can be used as
-  *         system clock source.
-  * @retval None
-  */
-#define __HAL_RCC_HSI_ENABLE()  LL_RCC_HSI_Enable()
-
-/** @brief  Macro to disable the Internal High Speed oscillator (HSI).
-  * @note   HSI can not be stopped if it is used as system clock source. In this case,
-  *         you have to select another source of the system clock then stop the HSI.
-  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
-  *         clock cycles.
-  * @retval None
-  */
-#define __HAL_RCC_HSI_DISABLE() LL_RCC_HSI_Disable()
-
-/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal HSI RC.
-  * @param  __HSICALIBRATIONVALUE__ specifies the calibration trimming value
-  *         (default is RCC_HSICALIBRATION_DEFAULT).
-  *         This parameter must be a number between Min_data=0 and Max_Data=127.
-  * @retval None
-  */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__)  \
-  LL_RCC_HSI_SetCalibTrimming(__HSICALIBRATIONVALUE__)
-
-/**
-  * @brief    Macros to enable or disable the wakeup the Internal High Speed oscillator (HSI)
-  *           in parallel to the Internal Multi Speed oscillator (MSI) used at system wakeup.
-  * @note     The enable of this function has not effect on the HSION bit.
-  *           This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-#define __HAL_RCC_HSIAUTOMATIC_START_ENABLE()   LL_RCC_HSI_EnableAutoFromStop()
-#define __HAL_RCC_HSIAUTOMATIC_START_DISABLE()  LL_RCC_HSI_DisableAutoFromStop()
-
-/**
-  * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
-  *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
-  * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
-  *           speed because of the HSI startup time.
-  * @note     The enable of this function has not effect on the HSION bit.
-  * @retval None
-  */
-#define __HAL_RCC_HSISTOP_ENABLE()     LL_RCC_HSI_EnableInStopMode()
-#define __HAL_RCC_HSISTOP_DISABLE()    LL_RCC_HSI_DisableInStopMode()
-
-/**
-  * @brief  Macros to enable or disable the Internal Multi Speed oscillator (MSI).
-  * @note   The MSI is stopped by hardware when entering STOP and STANDBY modes.
-  *         It is used (enabled by hardware) as system clock source after
-  *         startup from Reset, wakeup from STOP and STANDBY mode, or in case
-  *         of failure of the HSE used directly or indirectly as system clock
-  *         (if the Clock Security System CSS is enabled).
-  * @note   MSI can not be stopped if it is used as system clock source.
-  *         In this case, you have to select another source of the system
-  *         clock then stop the MSI.
-  * @note   After enabling the MSI, the application software should wait on
-  *         MSIRDY flag to be set indicating that MSI clock is stable and can
-  *         be used as system clock source.
-  * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
-  *         clock cycles.
-  * @retval None
-  */
-#define __HAL_RCC_MSI_ENABLE()  LL_RCC_MSI_Enable()
-#define __HAL_RCC_MSI_DISABLE() LL_RCC_MSI_Disable()
-
-/** @brief  Macro to adjust the Internal Multi Speed oscillator (MSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal MSI RC.
-  *         Refer to the Application Note AN3300 for more details on how to
-  *         calibrate the MSI.
-  * @param  __MSICALIBRATIONVALUE__  specifies the calibration trimming value
-  *         (default is @ref RCC_MSICALIBRATION_DEFAULT).
-  *         This parameter must be a number between 0 and 255.
-  * @retval None
-  */
-#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICALIBRATIONVALUE__)  \
-  LL_RCC_MSI_SetCalibTrimming(__MSICALIBRATIONVALUE__)
-
-/**
-  * @brief  Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode
-  * @note     After restart from Reset , the MSI clock is around 4 MHz.
-  *           After stop the startup clock can be MSI (at any of its possible
-  *           frequencies, the one that was used before entering stop mode) or HSI.
-  *          After Standby its frequency can be selected between 4 possible values
-  *          (1, 2, 4 or 8 MHz).
-  * @note     MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready
-  *          (MSIRDY=1).
-  * @note    The MSI clock range after reset can be modified on the fly.
-  * @param  __MSIRANGEVALUE__ specifies the MSI clock range.
-  *         This parameter must be one of the following values:
-  *            @arg @ref RCC_MSIRANGE_0  MSI clock is around 100 KHz
-  *            @arg @ref RCC_MSIRANGE_1  MSI clock is around 200 KHz
-  *            @arg @ref RCC_MSIRANGE_2  MSI clock is around 400 KHz
-  *            @arg @ref RCC_MSIRANGE_3  MSI clock is around 800 KHz
-  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz
-  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2 MHz
-  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4 MHz (default after Reset)
-  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8 MHz
-  *            @arg @ref RCC_MSIRANGE_8  MSI clock is around 16 MHz
-  *            @arg @ref RCC_MSIRANGE_9  MSI clock is around 24 MHz
-  *            @arg @ref RCC_MSIRANGE_10  MSI clock is around 32 MHz
-  *            @arg @ref RCC_MSIRANGE_11  MSI clock is around 48 MHz
-  * @retval None
-  */
-#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__)  do {                                                            \
-                                                            SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);                         \
-                                                            MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, (__MSIRANGEVALUE__)); \
-                                                          } while(0)
-
-/**
-  * @brief  Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode
-  *         After Standby its frequency can be selected between 4 possible values (1, 2, 4 or 8 MHz).
-  * @param  __MSIRANGEVALUE__ specifies the MSI clock range.
-  *         This parameter must be one of the following values:
-  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz
-  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2 MHz
-  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4 MHz (default after Reset)
-  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8 MHz
-  * @retval None
-  */
-#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) \
-  MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, (__MSIRANGEVALUE__) << 4U)
-
-/** @brief  Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode
-  * @retval MSI clock range.
-  *         This parameter must be one of the following values:
-  *            @arg @ref RCC_MSIRANGE_0  MSI clock is around 100 KHz
-  *            @arg @ref RCC_MSIRANGE_1  MSI clock is around 200 KHz
-  *            @arg @ref RCC_MSIRANGE_2  MSI clock is around 400 KHz
-  *            @arg @ref RCC_MSIRANGE_3  MSI clock is around 800 KHz
-  *            @arg @ref RCC_MSIRANGE_4  MSI clock is around 1 MHz
-  *            @arg @ref RCC_MSIRANGE_5  MSI clock is around 2 MHz
-  *            @arg @ref RCC_MSIRANGE_6  MSI clock is around 4 MHz (default after Reset)
-  *            @arg @ref RCC_MSIRANGE_7  MSI clock is around 8 MHz
-  *            @arg @ref RCC_MSIRANGE_8  MSI clock is around 16 MHz
-  *            @arg @ref RCC_MSIRANGE_9  MSI clock is around 24 MHz
-  *            @arg @ref RCC_MSIRANGE_10  MSI clock is around 32 MHz
-  *            @arg @ref RCC_MSIRANGE_11  MSI clock is around 48 MHz
-  */
-#define __HAL_RCC_GET_MSI_RANGE()  ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) != 0U) ?       \
-                                    (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)) :  \
-                                    (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> 4))
-
-/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
-  * @note   After enabling the LSI, the application software should wait on
-  *         LSIRDY flag to be set indicating that LSI clock is stable and can
-  *         be used to clock the IWDG and/or the RTC.
-  * @note   LSI can not be disabled if the IWDG is running.
-  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
-  *         clock cycles.
-  * @retval None
-  */
-#define __HAL_RCC_LSI_ENABLE()         LL_RCC_LSI_Enable()
-#define __HAL_RCC_LSI_DISABLE()        LL_RCC_LSI_Disable()
-
-/**
-  * @brief  Macro to configure the External High Speed oscillator (HSE).
-  * @note   Transition RCC_HSE_BYPASS_PWR to RCC_HSE_ON and RCC_HSE_ON to
-  *         RCC_HSE_BYPASS_PWR are not supported by this macro. User should
-  *         request a transition to RCC_HSE_OFF first and then RCC_HSE_ON or
-  *         RCC_HSE_BYPASS_PWR.
-  * @note   After enabling the HSE (RCC_HSE_ON, RCC_HSE_BYPASS_PWR),
-  *         the application software should wait on HSERDY flag to be set indicating
-  *         that HSE clock is stable and can be used to clock the PLL and/or system clock.
-  * @note   HSE state can not be changed if it is used directly or through the
-  *         PLL as system clock. In this case, you have to select another source
-  *         of the system clock then change the HSE state (ex. disable it).
-  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
-  * @note   PB0 must be configured in analog mode prior enabling the HSE with
-  *         RCC_HSE_BYPASS_PWR.
-  * @param  __STATE__  specifies the new state of the HSE.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_HSE_OFF         Turn OFF the HSE oscillator, HSERDY flag
-  *                                          goes low after 6 HSE oscillator clock cycles.
-  *            @arg @ref RCC_HSE_ON          Turn ON the HSE oscillator.
-  *            @arg @ref RCC_HSE_BYPASS_PWR  HSE32 driven from an external TCXO powered by the PB0-VDDTCXO pin.
-  * @retval None
-  */
-#define __HAL_RCC_HSE_CONFIG(__STATE__)  do {                                            \
-                                              if((__STATE__) == RCC_HSE_ON)              \
-                                              {                                          \
-                                                LL_RCC_HSE_Enable();                     \
-                                              }                                          \
-                                              else if((__STATE__) == RCC_HSE_BYPASS_PWR) \
-                                              {                                          \
-                                                LL_RCC_HSE_EnableTcxo();                 \
-                                                LL_RCC_HSE_Enable();                     \
-                                              }                                          \
-                                              else                                       \
-                                              {                                          \
-                                                LL_RCC_HSE_Disable();                    \
-                                                LL_RCC_HSE_DisableTcxo();                \
-                                              }                                          \
-                                            } while(0U)
-
-/** @brief  Macros to enable or disable the HSE Prescaler
-  * @note   HSE prescaler shall be enabled when HSE is used as
-  *         system clock source and Voltage scaling range 1
-  *         (Low-power range) is selected.
-  * @retval None
-  */
-#define __HAL_RCC_HSE_DIV2_ENABLE()         LL_RCC_HSE_EnableDiv2()
-#define __HAL_RCC_HSE_DIV2_DISABLE()        LL_RCC_HSE_DisableDiv2()
-
-/**
-  * @brief  Macro to configure the External Low Speed oscillator (LSE).
-  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
-  *         supported by this macro. User should request a transition to LSE Off
-  *         first and then LSE On or LSE Bypass.
-  * @note   As the LSE is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using
-  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
-  *         (to be done once after reset).
-  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
-  *         software should wait on LSERDY flag to be set indicating that LSE clock
-  *         is stable and can be used to clock the RTC.
-  * @param  __STATE__  specifies the new state of the LSE.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_LSE_OFF  Turn OFF the LSE oscillator, LSERDY flag goes low after
-  *                              6 LSE oscillator clock cycles.
-  *            @arg @ref RCC_LSE_ON  Turn ON the LSE oscillator.
-  *            @arg @ref RCC_LSE_BYPASS  LSE oscillator bypassed with external clock.
-  * @retval None
-  */
-#define __HAL_RCC_LSE_CONFIG(__STATE__)  do {                                          \
-                                              if((__STATE__) == RCC_LSE_ON)            \
-                                              {                                        \
-                                                LL_RCC_LSE_Enable();                   \
-                                              }                                        \
-                                              else if((__STATE__) == RCC_LSE_BYPASS)   \
-                                              {                                        \
-                                                LL_RCC_LSE_EnableBypass();             \
-                                                LL_RCC_LSE_Enable();                   \
-                                              }                                        \
-                                              else                                     \
-                                              {                                        \
-                                                LL_RCC_LSE_Disable();                  \
-                                                LL_RCC_LSE_DisableBypass();            \
-                                              }                                        \
-                                            } while(0U)
-
-/** @brief  Macro to configure the RTC clock (RTCCLK).
-  * @note   As the RTC clock configuration bits are in the Backup domain and write
-  *         access is denied to this domain after reset, you have to enable write
-  *         access using the Power Backup Access macro before to configure
-  *         the RTC clock source (to be done once after reset).
-  * @note   Once the RTC clock is configured it cannot be changed unless the
-  *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
-  *         a Power On Reset (POR).
-  *
-  * @param  __RTC_CLKSOURCE__  specifies the RTC clock source.
-  *         This parameter can be one of the following values:*
-  *            @arg @ref RCC_RTCCLKSOURCE_NONE  none clock selected as RTC clock.
-  *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
-  *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
-  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
-  *
-  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
-  *         work in STOP and STANDBY modes, and can be used as wakeup source.
-  *         However, when the HSE clock is used as RTC clock source, the RTC
-  *         cannot be used in STOP and STANDBY modes.
-  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
-  *         RTC clock source).
-  * @retval None
-  */
-#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__)  LL_RCC_SetRTCClockSource(__RTC_CLKSOURCE__)
-
-/** @brief  Macro to get the RTC clock source.
-  * @retval The returned value can be one of the following:
-  *            @arg @ref RCC_RTCCLKSOURCE_NONE  none clock selected as RTC clock.
-  *            @arg @ref RCC_RTCCLKSOURCE_LSE  LSE selected as RTC clock.
-  *            @arg @ref RCC_RTCCLKSOURCE_LSI  LSI selected as RTC clock.
-  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32  HSE clock divided by 32 selected
-  */
-#define  __HAL_RCC_GET_RTC_SOURCE() LL_RCC_GetRTCClockSource()
-
-/** @brief  Macros to enable or disable the main PLL.
-  * @note   After enabling the main PLL, the application software should wait on
-  *         PLLRDY flag to be set indicating that PLL clock is stable and can
-  *         be used as system clock source.
-  * @note   The main PLL can not be disabled if it is used as system clock source
-  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
-  * @retval None
-  */
-#define __HAL_RCC_PLL_ENABLE()         LL_RCC_PLL_Enable()
-#define __HAL_RCC_PLL_DISABLE()        LL_RCC_PLL_Disable()
-
-/** @brief  Macro to configure the PLL clock source.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __PLLSOURCE__  specifies the PLL entry clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
-  * @retval None
-  *
-  */
-#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
-/**
-  * @brief  Macro to configure the main PLL clock source, multiplication and division factors.
-  * @note   This function must be used only when the main PLL is disabled.
-  *
-  * @param  __PLLSOURCE__  specifies the PLL entry clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_PLLSOURCE_NONE  No clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_MSI  MSI oscillator clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_HSI  HSI oscillator clock selected as PLL clock entry
-  *            @arg @ref RCC_PLLSOURCE_HSE  HSE oscillator clock selected as PLL clock entry
-  *
-  * @param  __PLLM__  specifies the division factor for PLL VCO input clock.
-  *         This parameter must be a value of @ref RCC_PLLM_Clock_Divider.
-  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 2.66 to 16 MHz. It is recommended to select a frequency
-  *         of 16 MHz to limit PLL jitter.
-  *
-  * @param  __PLLN__  specifies the multiplication factor for PLL VCO output clock.
-  *         This parameter must be a number between 6 and 127.
-  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
-  *         output frequency is between 96 and 344 MHz.
-  *
-  * @param  __PLLP__  specifies the division factor for ADC clock.
-  *         This parameter must be a value of @ref RCC_PLLP_Clock_Divider.
-  *
-  * @param  __PLLQ__  specifies the division factor for I2S2 and RNG clocks.
-  *         This parameter must be a value of @ref RCC_PLLQ_Clock_Divider
-  *
-  * @note   RNG need a frequency lower than or equal to 48 MHz to work correctly.
-  *
-  * @param  __PLLR__  specifies the division factor for the main system clock.
-  *         This parameter must be a value of @ref RCC_PLLR_Clock_Divider
-  * @note   You have to set the PLLR parameter correctly to not exceed 48 MHZ.
-  * @retval None
-  */
-#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
-  MODIFY_REG(RCC->PLLCFGR,                                                    \
-             (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN |      \
-              RCC_PLLCFGR_PLLP   | RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR),      \
-             ((uint32_t) (__PLLSOURCE__)                      |               \
-              (uint32_t) (__PLLM__)                           |               \
-              (uint32_t) ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) |               \
-              (uint32_t) (__PLLP__)                           |               \
-              (uint32_t) (__PLLQ__)                           |               \
-              (uint32_t) (__PLLR__)))
-
-/** @brief  Macro to get the oscillator used as PLL clock source.
-  * @retval The oscillator used as PLL clock source. The returned value can be one
-  *         of the following:
-  *              @arg @ref RCC_PLLSOURCE_NONE No oscillator is used as PLL clock source.
-  *              @arg @ref RCC_PLLSOURCE_MSI MSI oscillator is used as PLL clock source.
-  *              @arg @ref RCC_PLLSOURCE_HSI HSI oscillator is used as PLL clock source.
-  *              @arg @ref RCC_PLLSOURCE_HSE HSE oscillator is used as PLL clock source.
-  */
-#define __HAL_RCC_GET_PLL_OSCSOURCE()  LL_RCC_PLL_GetMainSource()
-
-/**
-  * @brief  Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_I2S2CLK, RCC_PLL_RNGCLK, RCC_PLL_ADCCLK)
-  * @note   Enabling/disabling clock outputs RCC_PLL_I2S2CLK, RCC_PLL_RNGCLK and RCC_PLL_ADCCLK can be done at anytime
-  *         without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
-  *         be stopped if used as System Clock.
-  * @param  __PLLCLOCKOUT__  specifies the PLL clock to be output.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg @ref RCC_PLL_ADCCLK  This clock is used to generate the clock for ADC
-  *            @arg @ref RCC_PLL_I2S2CLK  This Clock is used to generate the clock for the I2S
-  *            @arg @ref RCC_PLL_RNGCLK  This clock is used to generate the clock for RNG
-  *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 48 MHz)
-  * @retval None
-  */
-#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__)   SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
-
-#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__)  CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
-
-/**
-  * @brief  Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_I2S2CLK, RCC_PLL_RNGCLK, RCC_PLL_ADCCLK)
-  * @param  __PLLCLOCKOUT__  specifies the output PLL clock to be checked.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_PLL_ADCCLK  same
-  *            @arg @ref RCC_PLL_I2S2CLK  This Clock is used to generate the clock for the I2S
-  *            @arg @ref RCC_PLL_RNGCLK  This clock is used to generate the clock for RNG
-  *            @arg @ref RCC_PLL_SYSCLK  This Clock is used to generate the high speed system clock (up to 48 MHz)
-  * @retval SET / RESET
-  */
-#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__)  READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
-
-/**
-  * @brief  Macro to configure the system clock source.
-  * @param  __SYSCLKSOURCE__  specifies the system clock source.
-  *          This parameter can be one of the following values:
-  *              @arg @ref RCC_SYSCLKSOURCE_MSI MSI oscillator is used as system clock source.
-  *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
-  *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
-  *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
-  * @retval None
-  */
-#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__)  LL_RCC_SetSysClkSource(__SYSCLKSOURCE__)
-
-/** @brief  Macro to get the clock source used as system clock.
-  * @retval The clock source used as system clock. The returned value can be one
-  *         of the following:
-  *              @arg @ref RCC_SYSCLKSOURCE_STATUS_MSI MSI used as system clock.
-  *              @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock.
-  *              @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock.
-  *              @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock.
-  */
-#define __HAL_RCC_GET_SYSCLK_SOURCE()  LL_RCC_GetSysClkSource()
-
-/**
-  * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.
-  * @note   As the LSE is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using
-  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
-  *         (to be done once after reset).
-  * @param  __LSEDRIVE__  specifies the new state of the LSE drive capability.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_LSEDRIVE_LOW  LSE oscillator low drive capability.
-  *            @arg @ref RCC_LSEDRIVE_MEDIUMLOW  LSE oscillator medium low drive capability.
-  *            @arg @ref RCC_LSEDRIVE_MEDIUMHIGH  LSE oscillator medium high drive capability.
-  *            @arg @ref RCC_LSEDRIVE_HIGH  LSE oscillator high drive capability.
-  * @retval None
-  */
-#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__)  LL_RCC_LSE_SetDriveCapability(__LSEDRIVE__)
-
-/**
-  * @brief  Macro to configure the wake up from stop clock.
-  * @param  __STOPWUCLK__  specifies the clock source used after wake up from stop.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_STOP_WAKEUPCLOCK_MSI  MSI selected as system clock source
-  *            @arg @ref RCC_STOP_WAKEUPCLOCK_HSI  HSI selected as system clock source
-  * @retval None
-  */
-#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__)  LL_RCC_SetClkAfterWakeFromStop(__STOPWUCLK__)
-
-
-/** @brief  Macro to configure the MCO clock.
-  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK  MCO output disabled
-  *            @arg @ref RCC_MCO1SOURCE_SYSCLK  System  clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_MSI     MSI clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_HSI     HSI clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_HSE     HSE clock selected as MCO sourcee
-  *            @arg @ref RCC_MCO1SOURCE_PLLCLK  Main PLL clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_LSI  LSI clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_LSE  LSE clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_PLLPCLK  main PLLP clock selected as MCO source
-  *            @arg @ref RCC_MCO1SOURCE_PLLQCLK  main PLLQ clock selected as MCO source
-  * @param  __MCODIV__ specifies the MCO clock prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_MCODIV_1   MCO clock source is divided by 1
-  *            @arg @ref RCC_MCODIV_2   MCO clock source is divided by 2
-  *            @arg @ref RCC_MCODIV_4   MCO clock source is divided by 4
-  *            @arg @ref RCC_MCODIV_8   MCO clock source is divided by 8
-  *            @arg @ref RCC_MCODIV_16  MCO clock source is divided by 16
-  */
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__)  LL_RCC_ConfigMCO((__MCOCLKSOURCE__), (__MCODIV__))
-
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
-  * @brief macros to manage the specified RCC Flags and interrupts.
-  * @{
-  */
-
-/** @brief  Enable RCC interrupt.
-  * @param  __INTERRUPT__  specifies the RCC interrupt sources to be enabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY     LSI ready interrupt enable
-  *            @arg @ref RCC_IT_LSERDY      LSE ready interrupt enable
-  *            @arg @ref RCC_IT_MSIRDY      HSI ready interrupt enable
-  *            @arg @ref RCC_IT_HSIRDY      HSI ready interrupt enable
-  *            @arg @ref RCC_IT_HSERDY      HSE ready interrupt enable
-  *            @arg @ref RCC_IT_PLLRDY      Main PLL ready interrupt enable
-  *            @arg @ref RCC_IT_LSECSS      LSE Clock security system interrupt enable
-  * @retval None
-  */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt.
-  * @param  __INTERRUPT__  specifies the RCC interrupt sources to be disabled.
-    *         This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY     LSI ready interrupt enable
-  *            @arg @ref RCC_IT_LSERDY      LSE ready interrupt enable
-  *            @arg @ref RCC_IT_MSIRDY      HSI ready interrupt enable
-  *            @arg @ref RCC_IT_HSIRDY      HSI ready interrupt enable
-  *            @arg @ref RCC_IT_HSERDY      HSE ready interrupt enable
-  *            @arg @ref RCC_IT_PLLRDY      Main PLL ready interrupt enable
-  *            @arg @ref RCC_IT_LSECSS      LSE Clock security system interrupt enable
-  * @retval None
-  */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
-
-/** @brief  Clear RCC interrupt pending bits (Perform Byte access to RCC_CICR[17:0]
-  *         bits to clear the selected interrupt pending bits.
-  * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt clear
-  *            @arg @ref RCC_IT_LSERDY   LSE ready interrupt clear
-  *            @arg @ref RCC_IT_MSIRDY   HSI ready interrupt clear
-  *            @arg @ref RCC_IT_HSIRDY   HSI ready interrupt clear
-  *            @arg @ref RCC_IT_HSERDY   HSE ready interrupt clear
-  *            @arg @ref RCC_IT_PLLRDY   Main PLL ready interrupt clear
-  *            @arg @ref RCC_IT_HSECSS   HSE Clock security system interrupt clear
-  *            @arg @ref RCC_IT_LSECSS   LSE Clock security system interrupt clear
-  */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
-
-/** @brief  Check whether the RCC interrupt has occurred or not.
-  * @param  __INTERRUPT__  specifies the RCC interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_IT_LSIRDY  LSI ready interrupt flag
-  *            @arg @ref RCC_IT_LSERDY   LSE ready interrupt flag
-  *            @arg @ref RCC_IT_MSIRDY   HSI ready interrupt flag
-  *            @arg @ref RCC_IT_HSIRDY   HSI ready interrupt flag
-  *            @arg @ref RCC_IT_HSERDY   HSE ready interrupt flag
-  *            @arg @ref RCC_IT_PLLRDY   Main PLL ready interrupt flag
-  *            @arg @ref RCC_IT_HSECSS   HSE Clock security system interrupt flag
-  *            @arg @ref RCC_IT_LSECSS   LSE Clock security system interrupt flag
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags.
-  *        The reset flags are: LPWRRSTF, WWDGRSTF, IWDGRSTF, SFTRSTF,
-           BORRSTF, PINRSTF, OBLRSTF, and RFILARSTF.
-  * @retval None
- */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() LL_RCC_ClearResetFlags()
-
-/** @brief  Check whether the selected RCC flag is set or not.
-  * @param  __FLAG__  specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_FLAG_MSIRDY     MSI oscillator clock ready
-  *            @arg @ref RCC_FLAG_HSIRDY     HSI oscillator clock ready
-  *            @arg @ref RCC_FLAG_HSERDY     HSE oscillator clock ready
-  *            @arg @ref RCC_FLAG_PLLRDY     Main PLL clock ready
-  *            @arg @ref RCC_FLAG_LSERDY     LSE oscillator clock ready
-  *            @arg @ref RCC_FLAG_LSECSSD    Clock security system failure on LSE oscillator detection
-  *            @arg @ref RCC_FLAG_LSESYSRDY  LSE system clock ready flag
-  *            @arg @ref RCC_FLAG_LSIRDY     LSI oscillator clock ready
-  *            @arg @ref RCC_FLAG_RFRST      Sub-GHz radio reset flag
-  *            @arg @ref RCC_FLAG_RFILARSTF  Sub-GHz radio illegal command flag
-  *            @arg @ref RCC_FLAG_BORRST     BOR reset
-  *            @arg @ref RCC_FLAG_OBLRST     OBLRST reset
-  *            @arg @ref RCC_FLAG_PINRST     Pin reset
-  *            @arg @ref RCC_FLAG_SFTRST     Software reset
-  *            @arg @ref RCC_FLAG_IWDGRST    Independent Watchdog reset
-  *            @arg @ref RCC_FLAG_WWDGRST    Window Watchdog reset
-  *            @arg @ref RCC_FLAG_LPWRRST    Low Power reset
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_GET_FLAG(__FLAG__)                                                 \
-  (((((((__FLAG__) >> REG_INDEX_POS) == CR_REG_INDEX) ? RCC->CR :                    \
-      ((((__FLAG__) >> REG_INDEX_POS) == BDCR_REG_INDEX) ? RCC->BDCR :               \
-       ((((__FLAG__) >> REG_INDEX_POS) == CSR_REG_INDEX) ? RCC->CSR : RCC->CIFR))) & \
-     (1U << ((__FLAG__) & RCC_FLAG_MASK))) != RESET) ? 1UL : 0UL)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Include RCC HAL Extended module */
-#include "stm32wlxx_hal_rcc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_Exported_Functions
-  * @{
-  */
-
-
-/** @addtogroup RCC_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group2
-  * @{
-  */
-
-/* Peripheral Control functions  **********************************************/
-void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void              HAL_RCC_EnableCSS(void);
-uint32_t          HAL_RCC_GetSysClockFreq(void);
-
-uint32_t          HAL_RCC_GetHCLKFreq(void);
-#if defined(DUAL_CORE)
-uint32_t          HAL_RCC_GetHCLK2Freq(void);
-#endif /* DUAL_CORE */
-uint32_t          HAL_RCC_GetHCLK3Freq(void);
-
-uint32_t          HAL_RCC_GetPCLK1Freq(void);
-uint32_t          HAL_RCC_GetPCLK2Freq(void);
-
-void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
-/* LSE & HSE CSS NMI IRQ handler */
-void              HAL_RCC_NMI_IRQHandler(void);
-/* User Callbacks in non blocking mode (IT mode) */
-void              HAL_RCC_CSSCallback(void);
-
-uint32_t          HAL_RCC_GetResetSource(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h

@@ -1,704 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_rcc_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of RCC HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_RCC_EX_H
-#define STM32WLxx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-#include "stm32wlxx_ll_exti.h"
-#include "stm32wlxx_ll_pwr.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCCEx
-  * @{
-  */
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup RCCEx_Private_Constants
-  * @{
-  */
-/* Define used for IS_RCC_* macros below */
-#define RCC_PERIPHCLOCK_ALL             (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_I2S2 | \
-                                         RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
-                                         RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
-                                         RCC_PERIPHCLK_LPTIM3 | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RNG | \
-                                         RCC_PERIPHCLK_RTC )
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @addtogroup RCCEx_Private_Macros
-  * @{
-  */
-
-#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
-                                       ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
-
-#define IS_RCC_PERIPHCLOCK(__SELECTION__)   ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \
-                                             (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u))
-
-#define IS_RCC_USART1CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2)  || \
-                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
-                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)    || \
-                                             ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
-
-#define IS_RCC_USART2CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1)  || \
-                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
-                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)    || \
-                                             ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
-
-#define IS_RCC_I2S2CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_I2S2CLKSOURCE_PLL)  || \
-                                           ((__SOURCE__) == RCC_I2S2CLKSOURCE_HSI)  || \
-                                           ((__SOURCE__) == RCC_I2S2CLKSOURCE_PIN))
-
-#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1)  || \
-                                              ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
-                                              ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE)    || \
-                                              ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
-
-#define IS_RCC_I2C1CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
-                                           ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
-                                           ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
-
-#define IS_RCC_I2C2CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
-                                           ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
-                                           ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
-
-
-#define IS_RCC_I2C3CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
-                                           ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
-                                           ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
-
-#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
-                                             ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI)   || \
-                                             ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI)   || \
-                                             ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
-
-#define IS_RCC_LPTIM2CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \
-                                             ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI)   || \
-                                             ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI)   || \
-                                             ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
-
-#define IS_RCC_LPTIM3CLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_LPTIM3CLKSOURCE_PCLK1) || \
-                                             ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSI)   || \
-                                             ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_HSI)   || \
-                                             ((__SOURCE__) == RCC_LPTIM3CLKSOURCE_LSE))
-
-#define IS_RCC_RNGCLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_RNGCLKSOURCE_PLL)     || \
-                                          ((__SOURCE__) == RCC_RNGCLKSOURCE_LSI)     || \
-                                          ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE)     || \
-                                          ((__SOURCE__) == RCC_RNGCLKSOURCE_MSI))
-
-#define IS_RCC_ADCCLKSOURCE(__SOURCE__)  (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
-                                          ((__SOURCE__) == RCC_ADCCLKSOURCE_HSI)  || \
-                                          ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL)  || \
-                                          ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
-
-/**
-  * @}
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
-  * @{
-  */
-
-/**
-  * @brief  RCC extended clocks structure definition
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
-                                        This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  uint32_t Usart1ClockSelection;   /*!< Specifies USART1 clock source.
-                                        This parameter can be a value of @ref RCCEx_USART1_Clock_Source    */
-
-  uint32_t Usart2ClockSelection;   /*!< Specifies USART2 clock source.
-                                        This parameter can be a value of @ref RCCEx_USART2_Clock_Source    */
-
-  uint32_t I2s2ClockSelection;     /*!< Specifies I2S2 clock source.
-                                        This parameter can be a value of @ref RCCEx_I2S2_Clock_Source      */
-
-  uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source.
-                                        This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source   */
-
-  uint32_t I2c1ClockSelection;     /*!< Specifies I2C1 clock source.
-                                        This parameter can be a value of @ref RCCEx_I2C1_Clock_Source      */
-
-  uint32_t I2c2ClockSelection;     /*!< Specifies I2C2 clock source.
-                                        This parameter can be a value of @ref RCCEx_I2C2_Clock_Source      */
-
-  uint32_t I2c3ClockSelection;     /*!< Specifies I2C3 clock source.
-                                        This parameter can be a value of @ref RCCEx_I2C3_Clock_Source      */
-
-  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source.
-                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source    */
-
-  uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source.
-                                        This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source    */
-
-  uint32_t Lptim3ClockSelection;   /*!< Specifies LPTIM3 clock source.
-                                        This parameter can be a value of @ref RCCEx_LPTIM3_Clock_Source    */
-
-  uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source.
-                                      This parameter can be a value of @ref RCCEx_ADC_Clock_Source         */
-
-  uint32_t RngClockSelection;      /*!< Specifies RNG clock source.
-                                        This parameter can be a value of @ref RCCEx_RNG_Clock_Source       */
-
-  uint32_t RTCClockSelection;      /*!< Specifies RTC clock source.
-                                        This parameter can be a value of @ref RCC_RTC_Clock_Source         */
-
-} RCC_PeriphCLKInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
-  * @{
-  */
-#define RCC_LSCOSOURCE_LSI             LL_RCC_LSCO_CLKSOURCE_LSI  /*!< LSI selection for low speed clock output */
-#define RCC_LSCOSOURCE_LSE             LL_RCC_LSCO_CLKSOURCE_LSE  /*!< LSE selection for low speed clock output */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
-  * @{
-  */
-#define RCC_PERIPHCLK_USART1           0x00000001U  /*!< USART1 Peripheral Clock Selection      */
-#define RCC_PERIPHCLK_USART2           0x00000002U  /*!< USART2 Peripheral Clock Selection      */
-#define RCC_PERIPHCLK_I2S2             0x00000010U  /*!< I2S2 Peripheral Clock Selection        */
-#define RCC_PERIPHCLK_LPUART1          0x00000020U  /*!< LPUART1 Peripheral Clock Selection     */
-#define RCC_PERIPHCLK_I2C1             0x00000040U  /*!< I2C1 Peripheral Clock Selection        */
-#define RCC_PERIPHCLK_I2C2             0x00000080U  /*!< I2C2 Peripheral Clock Selection        */
-#define RCC_PERIPHCLK_I2C3             0x00000100U  /*!< I2C3 Peripheral Clock Selection        */
-#define RCC_PERIPHCLK_LPTIM1           0x00000200U  /*!< LPTIM1 Peripheral Clock Selection      */
-#define RCC_PERIPHCLK_LPTIM2           0x00000400U  /*!< LPTIM2 Peripheral Clock Selection      */
-#define RCC_PERIPHCLK_LPTIM3           0x00000800U  /*!< LPTIM3 Peripheral Clock Selection      */
-#define RCC_PERIPHCLK_ADC              0x00004000U  /*!< ADC Peripheral Clock Selection         */
-#define RCC_PERIPHCLK_RNG              0x00008000U  /*!< RNG Peripheral Clock Selection         */
-#define RCC_PERIPHCLK_RTC              0x00010000U  /*!< RTC Peripheral Clock Selection         */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
-  * @{
-  */
-#define RCC_USART1CLKSOURCE_PCLK2      LL_RCC_USART1_CLKSOURCE_PCLK2   /*!< APB2 clock selected as USART1 clock   */
-#define RCC_USART1CLKSOURCE_SYSCLK     LL_RCC_USART1_CLKSOURCE_SYSCLK  /*!< SYSCLK clock selected as USART1 clock */
-#define RCC_USART1CLKSOURCE_HSI        LL_RCC_USART1_CLKSOURCE_HSI     /*!< HSI clock selected as USART1 clock    */
-#define RCC_USART1CLKSOURCE_LSE        LL_RCC_USART1_CLKSOURCE_LSE     /*!< LSE clock selected as USART1 clock    */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
-  * @{
-  */
-#define RCC_USART2CLKSOURCE_PCLK1      LL_RCC_USART2_CLKSOURCE_PCLK1   /*!< APB1 clock selected as USART2 clock*/
-#define RCC_USART2CLKSOURCE_SYSCLK     LL_RCC_USART2_CLKSOURCE_SYSCLK  /*!< SYSCLK clock selected as USART2 clock*/
-#define RCC_USART2CLKSOURCE_HSI        LL_RCC_USART2_CLKSOURCE_HSI     /*!< HSI clock selected as USART2 clock*/
-#define RCC_USART2CLKSOURCE_LSE        LL_RCC_USART2_CLKSOURCE_LSE     /*!< LSE clock selected as USART2 clock*/
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2S2_Clock_Source I2S Clock Source
-  * @{
-  */
-#define RCC_I2S2CLKSOURCE_PLL        LL_RCC_I2S2_CLKSOURCE_PLL       /*!< PLL "Q" clock selected as I2S2 clock source */
-#define RCC_I2S2CLKSOURCE_HSI        LL_RCC_I2S2_CLKSOURCE_HSI       /*!< HSI clock selected as I2S2 clock */
-#define RCC_I2S2CLKSOURCE_PIN        LL_RCC_I2S2_CLKSOURCE_PIN       /*!< External clock selected as I2S2 clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
-  * @{
-  */
-#define RCC_LPUART1CLKSOURCE_PCLK1     LL_RCC_LPUART1_CLKSOURCE_PCLK1    /*!< APB1 clock selected as LPUART1 clock*/
-#define RCC_LPUART1CLKSOURCE_SYSCLK    LL_RCC_LPUART1_CLKSOURCE_SYSCLK   /*!< SYSCLK clock selected as LPUART1 clock*/
-#define RCC_LPUART1CLKSOURCE_HSI       LL_RCC_LPUART1_CLKSOURCE_HSI      /*!< HSI clock selected as LPUART1 clock*/
-#define RCC_LPUART1CLKSOURCE_LSE       LL_RCC_LPUART1_CLKSOURCE_LSE      /*!< LSE clock selected as LPUART1 clock*/
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
-  * @{
-  */
-#define RCC_I2C1CLKSOURCE_PCLK1        LL_RCC_I2C1_CLKSOURCE_PCLK1   /*!< APB1 clock selected as I2C1 clock */
-#define RCC_I2C1CLKSOURCE_SYSCLK       LL_RCC_I2C1_CLKSOURCE_SYSCLK  /*!< SYSCLK clock selected as I2C1 clock */
-#define RCC_I2C1CLKSOURCE_HSI          LL_RCC_I2C1_CLKSOURCE_HSI     /*!< HSI clock selected as I2C1 clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
-  * @{
-  */
-#define RCC_I2C2CLKSOURCE_PCLK1        LL_RCC_I2C2_CLKSOURCE_PCLK1   /*!< APB1 clock selected as I2C2 clock */
-#define RCC_I2C2CLKSOURCE_SYSCLK       LL_RCC_I2C2_CLKSOURCE_SYSCLK  /*!< SYSCLK clock selected as I2C2 clock */
-#define RCC_I2C2CLKSOURCE_HSI          LL_RCC_I2C2_CLKSOURCE_HSI     /*!< HSI clock selected as I2C2 clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
-  * @{
-  */
-#define RCC_I2C3CLKSOURCE_PCLK1        LL_RCC_I2C3_CLKSOURCE_PCLK1   /*!< APB1 clock selected as I2C3 clock */
-#define RCC_I2C3CLKSOURCE_SYSCLK       LL_RCC_I2C3_CLKSOURCE_SYSCLK  /*!< SYSCLK clock selected as I2C3 clock */
-#define RCC_I2C3CLKSOURCE_HSI          LL_RCC_I2C3_CLKSOURCE_HSI     /*!< HSI clock selected as I2C3 clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
-  * @{
-  */
-#define RCC_LPTIM1CLKSOURCE_PCLK1      LL_RCC_LPTIM1_CLKSOURCE_PCLK1  /*!< APB1 clock selected as LPTIM1 clock */
-#define RCC_LPTIM1CLKSOURCE_LSI        LL_RCC_LPTIM1_CLKSOURCE_LSI    /*!< LSI clock selected as LPTIM1 clock  */
-#define RCC_LPTIM1CLKSOURCE_HSI        LL_RCC_LPTIM1_CLKSOURCE_HSI    /*!< HSI clock selected as LPTIM1 clock  */
-#define RCC_LPTIM1CLKSOURCE_LSE        LL_RCC_LPTIM1_CLKSOURCE_LSE    /*!< LSE clock selected as LPTIM1 clock  */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source
-  * @{
-  */
-#define RCC_LPTIM2CLKSOURCE_PCLK1      LL_RCC_LPTIM2_CLKSOURCE_PCLK1  /*!< APB1 clock selected as LPTIM2 clock */
-#define RCC_LPTIM2CLKSOURCE_LSI        LL_RCC_LPTIM2_CLKSOURCE_LSI    /*!< LSI clock selected as LPTIM2 clock  */
-#define RCC_LPTIM2CLKSOURCE_HSI        LL_RCC_LPTIM2_CLKSOURCE_HSI    /*!< HSI clock selected as LPTIM2 clock  */
-#define RCC_LPTIM2CLKSOURCE_LSE        LL_RCC_LPTIM2_CLKSOURCE_LSE    /*!< LSE clock selected as LPTIM2 clock  */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_LPTIM3_Clock_Source LPTIM3 Clock Source
-  * @{
-  */
-#define RCC_LPTIM3CLKSOURCE_PCLK1      LL_RCC_LPTIM3_CLKSOURCE_PCLK1  /*!< APB1 clock selected as LPTIM3 clock */
-#define RCC_LPTIM3CLKSOURCE_LSI        LL_RCC_LPTIM3_CLKSOURCE_LSI    /*!< LSI clock selected as LPTIM3 clock  */
-#define RCC_LPTIM3CLKSOURCE_HSI        LL_RCC_LPTIM3_CLKSOURCE_HSI    /*!< HSI clock selected as LPTIM3 clock  */
-#define RCC_LPTIM3CLKSOURCE_LSE        LL_RCC_LPTIM3_CLKSOURCE_LSE    /*!< LSE clock selected as LPTIM3 clock  */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
-  * @{
-  */
-#define RCC_RNGCLKSOURCE_PLL           LL_RCC_RNG_CLKSOURCE_PLL  /*!< PLL "Q" clock selected as RNG clock     */
-#define RCC_RNGCLKSOURCE_LSI           LL_RCC_RNG_CLKSOURCE_LSI  /*!< LSI clock selected as RNG clock         */
-#define RCC_RNGCLKSOURCE_LSE           LL_RCC_RNG_CLKSOURCE_LSE  /*!< LSE clock selected as RNG clock         */
-#define RCC_RNGCLKSOURCE_MSI           LL_RCC_RNG_CLKSOURCE_MSI  /*!< MSI clock selected as RNG clock         */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
-  * @{
-  */
-#define RCC_ADCCLKSOURCE_NONE          LL_RCC_ADC_CLKSOURCE_NONE    /*!< None clock selected as ADC clock        */
-#define RCC_ADCCLKSOURCE_HSI           LL_RCC_ADC_CLKSOURCE_HSI     /*!< HSI clock selected as ADC clock     */
-#define RCC_ADCCLKSOURCE_PLL           LL_RCC_ADC_CLKSOURCE_PLL     /*!< PLL "P" clock selected as ADC clock     */
-#define RCC_ADCCLKSOURCE_SYSCLK        LL_RCC_ADC_CLKSOURCE_SYSCLK  /*!< SYSCLK clock selected as ADC clock      */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line
-  * @{
-  */
-#define  RCC_EXTI_LINE_LSECSS          EXTI_IMR1_IM19  /*!< External interrupt line 18 connected to the LSE CSS EXTI Line */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_EXTI_LINE_HSECSS  RCC HSE CSS external interrupt line
-  * @{
-  */
-#define  RCC_EXTI_LINE_HSECSS          EXTI_IMR2_IM43  /*!< External interrupt line 43 connected to the HSE CSS EXTI Line */
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
-  * @{
-  */
-
-/*============================================================================*/
-
-/** @brief  Macro to configure the USART1 clock (USART1CLK).
-  * @param  __USART1_CLKSOURCE__ specifies the USART1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_USART1CLKSOURCE_PCLK2   PCLK2 selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_HSI     HSI selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_LSE     LSE selected as USART1 clock
-  * @retval None
-  */
-#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__)  LL_RCC_SetUSARTClockSource(__USART1_CLKSOURCE__)
-
-/** @brief  Macro to get the USART1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_USART1CLKSOURCE_PCLK2   PCLK2 selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_HSI     HSI selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_SYSCLK  System Clock selected as USART1 clock
-  *            @arg @ref RCC_USART1CLKSOURCE_LSE     LSE selected as USART1 clock
-  */
-#define __HAL_RCC_GET_USART1_SOURCE()  LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE)
-
-/** @brief  Macro to configure the USART2 clock (USART2CLK).
-  * @param  __USART2_CLKSOURCE__ specifies the USART2 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_USART2CLKSOURCE_PCLK1   PCLK1 selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_HSI     HSI selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_LSE     LSE selected as USART2 clock
-  * @retval None
-  */
-#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__)  LL_RCC_SetUSARTClockSource(__USART2_CLKSOURCE__)
-
-/** @brief  Macro to get the USART2 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_USART2CLKSOURCE_PCLK1   PCLK1 selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_HSI     HSI selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_SYSCLK  System Clock selected as USART2 clock
-  *            @arg @ref RCC_USART2CLKSOURCE_LSE     LSE selected as USART2 clock
-  */
-#define __HAL_RCC_GET_USART2_SOURCE()  LL_RCC_GetUSARTClockSource(LL_RCC_USART2_CLKSOURCE)
-
-/** @brief  Macro to configure the I2S2 clock (I2S2CLK).
-  * @param  __I2S2_CLKSOURCE__ specifies the I2S2 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_I2S2CLKSOURCE_PLL           PLL "Q" selected as I2S2 clock
-  *            @arg @ref RCC_I2S2CLKSOURCE_HSI           HSI selected as I2S2 clock
-  *            @arg @ref RCC_I2S2CLKSOURCE_PIN           External clock selected as I2S2 clock
-  * @retval None
-  */
-#define __HAL_RCC_I2S2_CONFIG(__I2S2_CLKSOURCE__)  LL_RCC_SetI2SClockSource(__I2S2_CLKSOURCE__)
-
-/** @brief  Macro to get the I2S2 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_I2S2CLKSOURCE_PLL       PLL "Q" selected as I2S2 clock
-  *            @arg @ref RCC_I2S2CLKSOURCE_HSI       HSI selected as I2S2 clock
-  *            @arg @ref RCC_I2S2CLKSOURCE_PIN       External clock selected as I2S2 clock
-  */
-#define __HAL_RCC_GET_I2S2_SOURCE()  LL_RCC_GetI2SClockSource(LL_RCC_I2S2_CLKSOURCE)
-
-/** @brief  Macro to configure the LPUART clock (LPUART1CLK).
-  * @param  __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1   PCLK1 selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_HSI     HSI selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_LSE     LSE selected as LPUART1 clock
-  * @retval None
-  */
-#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__)  LL_RCC_SetLPUARTClockSource(__LPUART1_CLKSOURCE__)
-
-/** @brief  Macro to get the LPUART1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_LPUART1CLKSOURCE_PCLK1   PCLK1 selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_HSI     HSI selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK  System Clock selected as LPUART1 clock
-  *            @arg @ref RCC_LPUART1CLKSOURCE_LSE     LSE selected as LPUART1 clock
-  */
-#define __HAL_RCC_GET_LPUART1_SOURCE()  LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE)
-
-/** @brief  Macro to configure the I2C1 clock (I2C1CLK).
-  * @param  __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1   PCLK1 selected as I2C1 clock
-  *            @arg @ref RCC_I2C1CLKSOURCE_HSI     HSI selected as I2C1 clock
-  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
-  * @retval None
-  */
-#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__)  LL_RCC_SetI2CClockSource(__I2C1_CLKSOURCE__)
-
-/** @brief  Macro to get the I2C1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_I2C1CLKSOURCE_PCLK1   PCLK1 selected as I2C1 clock
-  *            @arg @ref RCC_I2C1CLKSOURCE_HSI     HSI selected as I2C1 clock
-  *            @arg @ref RCC_I2C1CLKSOURCE_SYSCLK  System Clock selected as I2C1 clock
-  */
-#define __HAL_RCC_GET_I2C1_SOURCE()  LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE)
-
-/** @brief  Macro to configure the I2C2 clock (I2C2CLK).
-  * @param  __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1   PCLK1 selected as I2C2 clock
-  *            @arg @ref RCC_I2C2CLKSOURCE_HSI     HSI selected as I2C2 clock
-  *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
-  * @retval None
-  */
-#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__)  LL_RCC_SetI2CClockSource(__I2C2_CLKSOURCE__)
-
-/** @brief  Macro to get the I2C2 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_I2C2CLKSOURCE_PCLK1   PCLK1 selected as I2C2 clock
-  *            @arg @ref RCC_I2C2CLKSOURCE_HSI     HSI selected as I2C2 clock
-  *            @arg @ref RCC_I2C2CLKSOURCE_SYSCLK  System Clock selected as I2C2 clock
-  */
-#define __HAL_RCC_GET_I2C2_SOURCE()  LL_RCC_GetI2CClockSource(LL_RCC_I2C2_CLKSOURCE)
-
-/** @brief  Macro to configure the I2C3 clock (I2C3CLK).
-  * @param  __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1   PCLK1 selected as I2C3 clock
-  *            @arg @ref RCC_I2C3CLKSOURCE_HSI     HSI selected as I2C3 clock
-  *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
-  * @retval None
-  */
-#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__)  LL_RCC_SetI2CClockSource(__I2C3_CLKSOURCE__)
-
-/** @brief  Macro to get the I2C3 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_I2C3CLKSOURCE_PCLK1   PCLK1 selected as I2C3 clock
-  *            @arg @ref RCC_I2C3CLKSOURCE_HSI     HSI selected as I2C3 clock
-  *            @arg @ref RCC_I2C3CLKSOURCE_SYSCLK  System Clock selected as I2C3 clock
-  */
-#define __HAL_RCC_GET_I2C3_SOURCE()  LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE)
-
-/** @brief  Macro to configure the LPTIM1 clock (LPTIM1CLK).
-  * @param  __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK selected as LPTIM1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI   HSI selected as LPTIM1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI   LSI selected as LPTIM1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE   LSE selected as LPTIM1 clock
-  * @retval None
-  */
-#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__)  LL_RCC_SetLPTIMClockSource(__LPTIM1_CLKSOURCE__)
-
-/** @brief  Macro to get the LPTIM1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1  PCLK selected as LPTIM1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSI   HSI selected as LPTIM1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_HSI   System Clock selected as LPTIM1 clock
-  *            @arg @ref RCC_LPTIM1CLKSOURCE_LSE   LSE selected as LPTIM1 clock
-  */
-#define __HAL_RCC_GET_LPTIM1_SOURCE()  LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE)
-
-/** @brief  Macro to configure the LPTIM2 clock (LPTIM2CLK).
-  * @param  __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1  PCLK selected as LPTIM2 clock
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI   HSI selected as LPTIM2 clock
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI   LSI selected as LPTIM2 clock
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE   LSE selected as LPTIM2 clock
-  * @retval None
-  */
-#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__)  LL_RCC_SetLPTIMClockSource(__LPTIM2_CLKSOURCE__)
-
-/** @brief  Macro to get the LPTIM2 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1  PCLK selected as LPTIM2 clock
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSI   HSI selected as LPTIM2 clock
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_HSI   System Clock selected as LPTIM2 clock
-  *            @arg @ref RCC_LPTIM2CLKSOURCE_LSE   LSE selected as LPTIM2 clock
-  */
-#define __HAL_RCC_GET_LPTIM2_SOURCE()  LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE)
-
-/** @brief  Macro to configure the LPTIM3 clock (LPTIM3CLK).
-  * @param  __LPTIM3_CLKSOURCE__ specifies the LPTIM3 clock source.
-  *          This parameter can be one of the following values:
-  *            @arg @ref RCC_LPTIM3CLKSOURCE_PCLK1  PCLK selected as LPTIM3 clock
-  *            @arg @ref RCC_LPTIM3CLKSOURCE_LSI   HSI selected as LPTIM3 clock
-  *            @arg @ref RCC_LPTIM3CLKSOURCE_HSI   LSI selected as LPTIM3 clock
-  *            @arg @ref RCC_LPTIM3CLKSOURCE_LSE   LSE selected as LPTIM3 clock
-  * @retval None
-  */
-#define __HAL_RCC_LPTIM3_CONFIG(__LPTIM3_CLKSOURCE__)  LL_RCC_SetLPTIMClockSource(__LPTIM3_CLKSOURCE__)
-
-/** @brief  Macro to get the LPTIM3 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_LPTIM3CLKSOURCE_PCLK1  PCLK selected as LPTIM3 clock
-  *            @arg @ref RCC_LPTIM3CLKSOURCE_LSI   HSI selected as LPTIM3 clock
-  *            @arg @ref RCC_LPTIM3CLKSOURCE_HSI   System Clock selected as LPTIM3 clock
-  *            @arg @ref RCC_LPTIM3CLKSOURCE_LSE   LSE selected as LPTIM3 clock
-  */
-#define __HAL_RCC_GET_LPTIM3_SOURCE()  LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM3_CLKSOURCE)
-
-/** @brief  Macro to configure the RNG clock.
-  * @param  __RNG_CLKSOURCE__ specifies the RNG clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_RNGCLKSOURCE_PLL      PLL "Q" Clock selected as RNG clock
-  *            @arg @ref RCC_RNGCLKSOURCE_LSI      LSI selected as RNG clock
-  *            @arg @ref RCC_RNGCLKSOURCE_LSE      LSE selected as RNG clock
-  *            @arg @ref RCC_RNGCLKSOURCE_MSI      MSI selected as RNG clock
-  * @retval None
-  */
-#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__)  LL_RCC_SetRNGClockSource(__RNG_CLKSOURCE__)
-
-/** @brief  Macro to get the RNG clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_RNGCLKSOURCE_PLL      PLL "Q" Clock selected as RNG clock
-  *            @arg @ref RCC_RNGCLKSOURCE_LSI      LSI selected as RNG clock
-  *            @arg @ref RCC_RNGCLKSOURCE_LSE      LSE selected as RNG clock
-  *            @arg @ref RCC_RNGCLKSOURCE_MSI      MSI selected as RNG clock
-  */
-#define __HAL_RCC_GET_RNG_SOURCE()  LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE)
-
-/** @brief  Macro to configure the ADC interface clock.
-  * @param  __ADC_CLKSOURCE__ specifies the ADC digital interface clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_ADCCLKSOURCE_NONE    No clock selected as ADC clock
-  *            @arg @ref RCC_ADCCLKSOURCE_HSI     HSI Clock selected as ADC clock
-  *            @arg @ref RCC_ADCCLKSOURCE_PLL     PLL "P" Clock selected as ADC clock
-  *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock
-  * @retval None
-  */
-#define __HAL_RCC_ADC_CONFIG(__ADC_CLKSOURCE__)  LL_RCC_SetADCClockSource(__ADC_CLKSOURCE__)
-
-/** @brief  Macro to get the ADC clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_ADCCLKSOURCE_NONE    No clock selected as ADC clock
-  *            @arg @ref RCC_ADCCLKSOURCE_HSI     HSI Clock selected as ADC clock
-  *            @arg @ref RCC_ADCCLKSOURCE_PLL     PLL "P" Clock selected as ADC clock
-  *            @arg @ref RCC_ADCCLKSOURCE_SYSCLK  System Clock selected as ADC clock
-  */
-#define __HAL_RCC_GET_ADC_SOURCE()  LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE)
-
-
-#if defined(DUAL_CORE)
-
-#if defined(CORE_CM0PLUS)
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()            LL_C2_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS)
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()           LL_C2_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS)
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()         LL_C2_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS)
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()        LL_C2_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS)
-
-#define __HAL_RCC_HSECSS_EXTI_ENABLE_IT()            LL_C2_EXTI_EnableIT_32_63(RCC_EXTI_LINE_HSECSS)
-#define __HAL_RCC_HSECSS_EXTI_DISABLE_IT()           LL_C2_EXTI_DisableIT_32_63(RCC_EXTI_LINE_HSECSS)
-#else
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()            LL_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS)
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()           LL_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS)
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()         LL_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS)
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()        LL_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS)
-
-#define __HAL_RCC_HSECSS_EXTI_ENABLE_IT()            LL_EXTI_EnableIT_32_63(RCC_EXTI_LINE_HSECSS)
-#define __HAL_RCC_HSECSS_EXTI_DISABLE_IT()           LL_EXTI_DisableIT_32_63(RCC_EXTI_LINE_HSECSS)
-#endif /* CORE_CM0PLUS */
-
-#else
-
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()            LL_EXTI_EnableIT_0_31(RCC_EXTI_LINE_LSECSS)
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()           LL_EXTI_DisableIT_0_31(RCC_EXTI_LINE_LSECSS)
-#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()         LL_EXTI_EnableEvent_0_31(RCC_EXTI_LINE_LSECSS)
-#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()        LL_EXTI_DisableEvent_0_31(RCC_EXTI_LINE_LSECSS)
-
-#define __HAL_RCC_HSECSS_EXTI_ENABLE_IT()            LL_EXTI_EnableIT_32_63(RCC_EXTI_LINE_HSECSS)
-#define __HAL_RCC_HSECSS_EXTI_DISABLE_IT()           LL_EXTI_DisableIT_32_63(RCC_EXTI_LINE_HSECSS)
-
-#endif /* DUAL_CORE */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RCCEx_Exported_Functions_Group1
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCCEx_Exported_Functions_Group2
-  * @{
-  */
-
-void              HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
-
-void              HAL_RCCEx_EnableLSECSS(void);
-void              HAL_RCCEx_DisableLSECSS(void);
-void              HAL_RCCEx_EnableLSECSS_IT(void);
-void              HAL_RCCEx_LSECSS_IRQHandler(void);
-void              HAL_RCCEx_LSECSS_Callback(void);
-
-void              HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
-void              HAL_RCCEx_DisableLSCO(void);
-
-void              HAL_RCCEx_EnableMSIPLLMode(void);
-void              HAL_RCCEx_DisableMSIPLLMode(void);
-
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_RCC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rng.h

@@ -1,391 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_rng.h
-  * @author  MCD Application Team
-  * @brief   Header file of RNG HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_RNG_H
-#define STM32WLxx_HAL_RNG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-#if defined (RNG)
-
-/** @defgroup RNG RNG
-  * @brief RNG HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup RNG_Exported_Types RNG Exported Types
-  * @{
-  */
-
-/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
-  * @{
-  */
-typedef struct
-{
-  uint32_t                    ClockErrorDetection; /*!< CED Clock error detection */
-} RNG_InitTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
-  * @{
-  */
-typedef enum
-{
-  HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */
-  HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */
-  HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */
-  HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */
-  HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */
-
-} HAL_RNG_StateTypeDef;
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
-  * @{
-  */
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-typedef struct  __RNG_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-{
-  RNG_TypeDef                 *Instance;    /*!< Register base address   */
-
-  RNG_InitTypeDef             Init;         /*!< RNG configuration parameters */
-
-  HAL_LockTypeDef             Lock;         /*!< RNG locking object      */
-
-  __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */
-
-  __IO  uint32_t              ErrorCode;    /*!< RNG Error code          */
-
-  uint32_t                    RandomNumber; /*!< Last Generated RNG Data */
-
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-  void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit);  /*!< RNG Data Ready Callback    */
-  void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng);                            /*!< RNG Error Callback         */
-
-  void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng);                          /*!< RNG Msp Init callback      */
-  void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng);                        /*!< RNG Msp DeInit callback    */
-#endif  /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-} RNG_HandleTypeDef;
-
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL RNG Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_RNG_ERROR_CB_ID                   = 0x00U,     /*!< RNG Error Callback ID          */
-
-  HAL_RNG_MSPINIT_CB_ID                 = 0x01U,     /*!< RNG MspInit callback ID        */
-  HAL_RNG_MSPDEINIT_CB_ID               = 0x02U      /*!< RNG MspDeInit callback ID      */
-
-} HAL_RNG_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL RNG Callback pointer definition
-  */
-typedef  void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng);                                  /*!< pointer to a common RNG callback function */
-typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit);   /*!< pointer to an RNG Data Ready specific callback function */
-
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RNG_Exported_Constants RNG Exported Constants
-  * @{
-  */
-
-/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
-  * @{
-  */
-#define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
-#define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
-#define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
-  * @{
-  */
-#define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
-#define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
-#define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
-  * @{
-  */
-#define RNG_CED_ENABLE          0x00000000U /*!< Clock error detection Enabled  */
-#define RNG_CED_DISABLE         RNG_CR_CED  /*!< Clock error detection Disabled */
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Error_Definition   RNG Error Definition
-  * @{
-  */
-#define  HAL_RNG_ERROR_NONE             0x00000000U    /*!< No error          */
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-#define  HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U    /*!< Invalid Callback error  */
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-#define  HAL_RNG_ERROR_TIMEOUT          0x00000002U    /*!< Timeout error     */
-#define  HAL_RNG_ERROR_BUSY             0x00000004U    /*!< Busy error        */
-#define  HAL_RNG_ERROR_SEED             0x00000008U    /*!< Seed error        */
-#define  HAL_RNG_ERROR_CLOCK            0x00000010U    /*!< Clock error       */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RNG_Exported_Macros RNG Exported Macros
-  * @{
-  */
-
-/** @brief Reset RNG handle state
-  * @param  __HANDLE__ RNG Handle
-  * @retval None
-  */
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->State = HAL_RNG_STATE_RESET;       \
-                                                       (__HANDLE__)->MspInitCallback = NULL;            \
-                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                    } while(0U)
-#else
-#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Enables the RNG peripheral.
-  * @param  __HANDLE__ RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
-
-/**
-  * @brief  Disables the RNG peripheral.
-  * @param  __HANDLE__ RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
-
-/**
-  * @brief  Check the selected RNG flag status.
-  * @param  __HANDLE__ RNG Handle
-  * @param  __FLAG__ RNG flag
-  *          This parameter can be one of the following values:
-  *            @arg RNG_FLAG_DRDY:  Data ready
-  *            @arg RNG_FLAG_CECS:  Clock error current status
-  *            @arg RNG_FLAG_SECS:  Seed error current status
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clears the selected RNG flag status.
-  * @param  __HANDLE__ RNG handle
-  * @param  __FLAG__ RNG flag to clear
-  * @note   WARNING: This is a dummy macro for HAL code alignment,
-  *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
-  * @retval None
-  */
-#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
-
-/**
-  * @brief  Enables the RNG interrupts.
-  * @param  __HANDLE__ RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
-
-/**
-  * @brief  Disables the RNG interrupts.
-  * @param  __HANDLE__ RNG Handle
-  * @retval None
-  */
-#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
-
-/**
-  * @brief  Checks whether the specified RNG interrupt has occurred or not.
-  * @param  __HANDLE__ RNG Handle
-  * @param  __INTERRUPT__ specifies the RNG interrupt status flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg RNG_IT_DRDY: Data ready interrupt
-  *            @arg RNG_IT_CEI: Clock error interrupt
-  *            @arg RNG_IT_SEI: Seed error interrupt
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Clear the RNG interrupt status flags.
-  * @param  __HANDLE__ RNG Handle
-  * @param  __INTERRUPT__ specifies the RNG interrupt status flag to clear.
-  *          This parameter can be one of the following values:
-  *            @arg RNG_IT_CEI: Clock error interrupt
-  *            @arg RNG_IT_SEI: Seed error interrupt
-  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
-  * @retval None
-  */
-#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
-
-/**
-  * @}
-  */
-
-/* Include RNG HAL Extended module */
-#include "stm32wlxx_hal_rng_ex.h"
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_Exported_Functions RNG Exported Functions
-  * @{
-  */
-
-/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
-HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
-void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
-void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
-                                           pRNG_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
-#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
-HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
-uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
-
-void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
-void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
-
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
-  * @{
-  */
-HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
-uint32_t             HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RNG_Private_Macros RNG Private Macros
-  * @{
-  */
-#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
-                       ((IT) == RNG_IT_SEI))
-
-#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
-                           ((FLAG) == RNG_FLAG_CECS) || \
-                           ((FLAG) == RNG_FLAG_SECS))
-
-/**
-  * @brief Verify the RNG Clock Error Detection mode.
-  * @param __MODE__ RNG Clock Error Detection mode
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_RNG_CED(__MODE__)   (((__MODE__) == RNG_CED_ENABLE) || \
-                                ((__MODE__) == RNG_CED_DISABLE))
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RNG_Private_Functions RNG Private functions
-  * @{
-  */
-HAL_StatusTypeDef RNG_RecoverSeedError(RNG_HandleTypeDef *hrng);
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-
-#endif /* RNG */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32WLxx_HAL_RNG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rng_ex.h

@@ -1,250 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_rng_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of RNG HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_RNG_EX_H
-#define STM32WLxx_HAL_RNG_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-#if defined(RNG)
-#if defined(RNG_CR_CONDRST)
-
-/** @defgroup RNG_Ex RNG_Ex
-  * @brief RNG Extension HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types
-  * @brief RNG_Ex Exported types
-  * @{
-  */
-
-/**
-  * @brief RNG_Ex Configuration Structure definition
-  */
-
-typedef struct
-{
-  uint32_t        Config1;           /*!< Config1 must be a value between 0 and 0x3F */
-  uint32_t        Config2;           /*!< Config2 must be a value between 0 and 0x7 */
-  uint32_t        Config3;           /*!< Config3 must be a value between 0 and 0xF */
-  uint32_t        ClockDivider;      /*!< Clock Divider factor.This parameter can
-                                          be a value of @ref RNG_Ex_Clock_Divider_Factor   */
-  uint32_t        NistCompliance;    /*!< NIST compliance.This parameter can be a
-                                          value of @ref RNG_Ex_NIST_Compliance   */
-} RNG_ConfigTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants
-  * @{
-  */
-
-/** @defgroup RNG_Ex_Clock_Divider_Factor  Value used to configure an internal
-  *            programmable divider acting on the incoming RNG clock
-  * @{
-  */
-#define RNG_CLKDIV_BY_1       (0x00000000UL)      /*!< No clock division  */
-#define RNG_CLKDIV_BY_2       (RNG_CR_CLKDIV_0)
-/*!< 2 RNG clock cycles per internal RNG clock    */
-#define RNG_CLKDIV_BY_4       (RNG_CR_CLKDIV_1)
-/*!< 4 RNG clock cycles per internal RNG clock    */
-#define RNG_CLKDIV_BY_8       (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
-/*!< 8 RNG clock cycles per internal RNG clock    */
-#define RNG_CLKDIV_BY_16      (RNG_CR_CLKDIV_2)
-/*!< 16 RNG clock cycles per internal RNG clock   */
-#define RNG_CLKDIV_BY_32      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
-/*!< 32 RNG clock cycles per internal RNG clock   */
-#define RNG_CLKDIV_BY_64      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
-/*!< 64 RNG clock cycles per internal RNG clock   */
-#define RNG_CLKDIV_BY_128     (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
-/*!< 128 RNG clock cycles per internal RNG clock  */
-#define RNG_CLKDIV_BY_256     (RNG_CR_CLKDIV_3)
-/*!< 256 RNG clock cycles per internal RNG clock  */
-#define RNG_CLKDIV_BY_512     (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
-/*!< 512 RNG clock cycles per internal RNG clock  */
-#define RNG_CLKDIV_BY_1024    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
-/*!< 1024 RNG clock cycles per internal RNG clock */
-#define RNG_CLKDIV_BY_2048    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
-/*!< 2048 RNG clock cycles per internal RNG clock  */
-#define RNG_CLKDIV_BY_4096    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
-/*!< 4096 RNG clock cycles per internal RNG clock  */
-#define RNG_CLKDIV_BY_8192    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
-/*!< 8192 RNG clock cycles per internal RNG clock  */
-#define RNG_CLKDIV_BY_16384   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
-/*!< 16384 RNG clock cycles per internal RNG clock */
-#define RNG_CLKDIV_BY_32768   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
-/*!< 32768 RNG clock cycles per internal RNG clock */
-/**
-  * @}
-  */
-
-/** @defgroup RNG_Ex_NIST_Compliance  NIST Compliance configuration
-  * @{
-  */
-#define RNG_NIST_COMPLIANT     (0x00000000UL) /*!< NIST compliant configuration*/
-#define RNG_CUSTOM_NIST        (RNG_CR_NISTC) /*!< Custom NIST configuration */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros
-  * @{
-  */
-
-#define IS_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) (((__CLOCK_DIV__) == RNG_CLKDIV_BY_1)     || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2)     || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4)     || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8)     || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16)    || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32)    || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_64)    || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_128)   || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_256)   || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_512)   || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_1024)  || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2048)  || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4096)  || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8192)  || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16384) || \
-                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32768))
-
-
-#define IS_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == RNG_NIST_COMPLIANT) || \
-                                                     ((__NIST_COMPLIANCE__) == RNG_CUSTOM_NIST))
-
-#define IS_RNG_CONFIG1(__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
-
-#define IS_RNG_CONFIG2(__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
-
-#define IS_RNG_CONFIG3(__CONFIG3__) ((__CONFIG3__) <= 0xFUL)
-
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions
-  * @{
-  */
-
-/** @addtogroup RNG_Ex_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
-HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
-HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);
-
-/**
-  * @}
-  */
-
-/** @addtogroup RNG_Ex_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* RNG_CR_CONDRST */
-#endif /* RNG */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32WLxx_HAL_RNG_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h

@@ -1,963 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_rtc.h
-  * @author  MCD Application Team
-  * @brief   Header file of RTC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_RTC_H
-#define STM32WLxx_HAL_RTC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RTC RTC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_Types RTC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
-  HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
-  HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
-  HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
-  HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
-
-} HAL_RTCStateTypeDef;
-
-/**
-  * @brief  RTC Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t HourFormat;        /*!< Specifies the RTC Hour Format.
-                                 This parameter can be a value of @ref RTC_Hour_Formats */
-
-  uint32_t AsynchPrediv;      /*!< Specifies the RTC Asynchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
-
-  uint32_t SynchPrediv;       /*!< Specifies the RTC Synchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
-
-  uint32_t OutPut;            /*!< Specifies which signal will be routed to the RTC output.
-                                 This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
-
-  uint32_t OutPutRemap;       /*!< Specifies the remap for RTC output.
-                                 This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */
-
-  uint32_t OutPutPolarity;    /*!< Specifies the polarity of the output signal.
-                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
-
-  uint32_t OutPutType;        /*!< Specifies the RTC Output Pin mode.
-                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
-
-  uint32_t OutPutPullUp;      /*!< Specifies the RTC Output Pull-Up mode.
-                                 This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */
-
-  uint32_t BinMode;           /*!< Specifies the RTC binary mode.
-                                 This parameter can be a value of @ref RTCEx_Binary_Mode */
-
-  uint32_t BinMixBcdU;        /*!< Specifies the BCD calendar update if and only if BinMode = RTC_BINARY_MIX.
-                                 This parameter can be a value of @ref RTCEx_Binary_mix_BCDU */
-} RTC_InitTypeDef;
-
-
-/**
-  * @brief  RTC Enabled features Structure definition
-  */
-typedef struct
-{
-  uint32_t RtcFeatures;
-  uint32_t TampFeatures;
-} RTC_IsEnabledTypeDef;
-
-
-/**
-  * @brief  RTC Time structure definition
-  */
-typedef struct
-{
-  uint8_t Hours;            /*!< Specifies the RTC Time Hour.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
-
-  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
-  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-
-  uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
-                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */
-
-  uint32_t SubSeconds;      /*!< Specifies the RTC_SSR RTC Sub Second register content.
-                                 This field is not used by HAL_RTC_SetTime.
-                                 If the free running 32 bit counter is not activated (mode binary none)
-                                    - This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity
-                                 else
-                                    - This parameter corresponds to the free running 32 bit counter. */
-
-  uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
-                                 corresponding to Synchronous pre-scaler factor value (PREDIV_S)
-                                 This parameter corresponds to a time unit range between [0-1] Second
-                                 with [1 Sec / SecondFraction +1] granularity.
-                                 This field will be used only by HAL_RTC_GetTime function */
-
-  uint32_t DayLightSaving;  /*!< This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
-
-  uint32_t StoreOperation;  /*!< This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */
-} RTC_TimeTypeDef;
-
-/**
-  * @brief  RTC Date structure definition
-  */
-typedef struct
-{
-  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
-                         This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
-  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
-                         This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
-  uint8_t Date;     /*!< Specifies the RTC Date.
-                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-
-  uint8_t Year;     /*!< Specifies the RTC Date Year.
-                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-
-} RTC_DateTypeDef;
-
-/**
-  * @brief  RTC Alarm structure definition
-  */
-typedef struct
-{
-  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
-
-  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
-                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
-  uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
-                                      if Binary mode is RTC_BINARY_ONLY or is RTC_BINARY_MIX
-                                        This parameter can be a value of @ref RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions
-                                      else if Binary mode is RTC_BINARY_NONE
-                                        This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
-
-  uint32_t BinaryAutoClr;        /*!< Clear synchronously counter (RTC_SSR) on binary alarm.
-                                      RTC_ALARMSUBSECONDBIN_AUTOCLR_YES must only be used if Binary mode is RTC_BINARY_ONLY
-                                      This parameter can be a value of @ref RTCEx_Alarm_Sub_Seconds_binary_Clear_Definitions */
-
-  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
-                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
-  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
-                                      If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
-                                      If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
-
-  uint32_t Alarm;                /*!< Specifies the alarm .
-                                      This parameter can be a value of @ref RTC_Alarms_Definitions */
-} RTC_AlarmTypeDef;
-
-/**
-  * @brief  RTC Handle Structure definition
-  */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-typedef struct __RTC_HandleTypeDef
-#else
-typedef struct
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
-{
-  RTC_TypeDef               *Instance;  /*!< Legacy register base address. Not used anymore, the driver directly uses cmsis base address */
-
-  RTC_InitTypeDef           Init;       /*!< RTC required parameters  */
-
-  HAL_LockTypeDef           Lock;       /*!< RTC locking object       */
-
-  __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */
-
-  RTC_IsEnabledTypeDef      IsEnabled; /*!< Flag to avoid treatment of the interrupts activated by the other core  */
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-  void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc);                    /*!< RTC Alarm A Event callback            */
-  void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc);                    /*!< RTC Alarm B Event callback            */
-  void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc);                 /*!< RTC TimeStamp Event callback          */
-  void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc);               /*!< RTC WakeUpTimer Event callback        */
-  void (* SSRUEventCallback)(struct __RTC_HandleTypeDef *hrtc);                      /*!< RTC SSRU Event callback               */
-  void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);                   /*!< RTC Tamper 1 Event callback           */
-  void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc);                   /*!< RTC Tamper 2 Event callback           */
-  void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);                   /*!< RTC Tamper 3 Event callback           */
-  void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 3 Event callback  */
-  void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 5 Event callback  */
-  void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 6 Event callback  */
-  void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 8 Event callback  */
-  void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc);                        /*!< RTC Msp Init callback                 */
-  void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc);                      /*!< RTC Msp DeInit callback               */
-
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
-
-} RTC_HandleTypeDef;
-
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL RTC Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_RTC_ALARM_A_EVENT_CB_ID           =  0u,    /*!< RTC Alarm A Event Callback ID      */
-  HAL_RTC_ALARM_B_EVENT_CB_ID           =  1u,    /*!< RTC Alarm B Event Callback ID      */
-  HAL_RTC_TIMESTAMP_EVENT_CB_ID         =  2u,    /*!< RTC TimeStamp Event Callback ID    */
-  HAL_RTC_WAKEUPTIMER_EVENT_CB_ID       =  3u,    /*!< RTC WakeUp Timer Event Callback ID */
-  HAL_RTC_SSRU_EVENT_CB_ID              =  4u,    /*!< RTC SSR Underflow Event Callback ID */
-  HAL_RTC_TAMPER1_EVENT_CB_ID           =  5u,    /*!< RTC Tamper 1 Callback ID           */
-  HAL_RTC_TAMPER2_EVENT_CB_ID           =  6u,    /*!< RTC Tamper 2 Callback ID           */
-  HAL_RTC_TAMPER3_EVENT_CB_ID           =  7u,    /*!< RTC Tamper 3 Callback ID           */
-  HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID  =  8u,    /*!< RTC Internal Tamper 3 Callback ID  */
-  HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID  =  9u,    /*!< RTC Internal Tamper 5 Callback ID  */
-  HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID  = 10u,    /*!< RTC Internal Tamper 6 Callback ID  */
-  HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID  = 11u,    /*!< RTC Internal Tamper 8 Callback ID  */
-  HAL_RTC_MSPINIT_CB_ID                 = 12u,    /*!< RTC Msp Init callback ID           */
-  HAL_RTC_MSPDEINIT_CB_ID               = 13u     /*!< RTC Msp DeInit callback ID         */
-} HAL_RTC_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL RTC Callback pointer definition
-  */
-typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to an RTC callback function */
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Constants RTC Exported Constants
-  * @{
-  */
-
-/** @defgroup RTC_Hour_Formats RTC Hour Formats
-  * @{
-  */
-#define RTC_HOURFORMAT_24                   0x00000000u
-#define RTC_HOURFORMAT_12                   RTC_CR_FMT
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
-  * @{
-  */
-#define RTC_OUTPUT_DISABLE                  0x00000000u
-#define RTC_OUTPUT_ALARMA                   RTC_CR_OSEL_0
-#define RTC_OUTPUT_ALARMB                   RTC_CR_OSEL_1
-#define RTC_OUTPUT_WAKEUP                   RTC_CR_OSEL
-#define RTC_OUTPUT_TAMPER                   RTC_CR_TAMPOE
-/**
-  * @}
-  */
-
-
-/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
-  * @{
-  */
-#define RTC_OUTPUT_POLARITY_HIGH            0x00000000u
-#define RTC_OUTPUT_POLARITY_LOW             RTC_CR_POL
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
-  * @{
-  */
-#define RTC_OUTPUT_TYPE_PUSHPULL            0x00000000u
-#define RTC_OUTPUT_TYPE_OPENDRAIN           RTC_CR_TAMPALRM_TYPE
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT
-  * @{
-  */
-#define RTC_OUTPUT_PULLUP_NONE              0x00000000u
-#define RTC_OUTPUT_PULLUP_ON                RTC_CR_TAMPALRM_PU
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
-  * @{
-  */
-#define RTC_OUTPUT_REMAP_NONE               0x00000000u
-#define RTC_OUTPUT_REMAP_POS1               RTC_CR_OUT2EN
-/**
-  * @}
-  */
-
-/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
-  * @{
-  */
-#define RTC_HOURFORMAT12_AM                 0x0u
-#define RTC_HOURFORMAT12_PM                 0x1u
-/**
-  * @}
-  */
-
-/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
-  * @{
-  */
-#define RTC_DAYLIGHTSAVING_SUB1H            RTC_CR_SUB1H
-#define RTC_DAYLIGHTSAVING_ADD1H            RTC_CR_ADD1H
-#define RTC_DAYLIGHTSAVING_NONE             0x00000000u
-/**
-  * @}
-  */
-
-/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
-  * @{
-  */
-#define RTC_STOREOPERATION_RESET            0x00000000u
-#define RTC_STOREOPERATION_SET              RTC_CR_BKP
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Input_parameter_format_definitions RTC input or output data format for date (Year, Month, Weekday) and time (Hours, Minutes, Seconds).
-  *           Warning : It Should not be confused with the Binary mode @ref RTCEx_Binary_Mode.
-  * @{
-  */
-#define RTC_FORMAT_BIN                      0x00000000u /* This parameter will trigger a SW conversion to fit with the native BCD format of the HW Calendar.
-                                                           It should not be confused with the Binary mode @ref RTCEx_Binary_Mode. */
-
-#define RTC_FORMAT_BCD                      0x00000001u /* Native format of the HW Calendar.
-                                                           It should not be confused with the Binary mode @ref RTCEx_Binary_Mode. */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
-  * @{
-  */
-
-/* Coded in BCD format */
-#define RTC_MONTH_JANUARY                   ((uint8_t)0x01U)
-#define RTC_MONTH_FEBRUARY                  ((uint8_t)0x02U)
-#define RTC_MONTH_MARCH                     ((uint8_t)0x03U)
-#define RTC_MONTH_APRIL                     ((uint8_t)0x04U)
-#define RTC_MONTH_MAY                       ((uint8_t)0x05U)
-#define RTC_MONTH_JUNE                      ((uint8_t)0x06U)
-#define RTC_MONTH_JULY                      ((uint8_t)0x07U)
-#define RTC_MONTH_AUGUST                    ((uint8_t)0x08U)
-#define RTC_MONTH_SEPTEMBER                 ((uint8_t)0x09U)
-#define RTC_MONTH_OCTOBER                   ((uint8_t)0x10U)
-#define RTC_MONTH_NOVEMBER                  ((uint8_t)0x11U)
-#define RTC_MONTH_DECEMBER                  ((uint8_t)0x12U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
-  * @{
-  */
-#define RTC_WEEKDAY_MONDAY                  ((uint8_t)0x01U)
-#define RTC_WEEKDAY_TUESDAY                 ((uint8_t)0x02U)
-#define RTC_WEEKDAY_WEDNESDAY               ((uint8_t)0x03U)
-#define RTC_WEEKDAY_THURSDAY                ((uint8_t)0x04U)
-#define RTC_WEEKDAY_FRIDAY                  ((uint8_t)0x05U)
-#define RTC_WEEKDAY_SATURDAY                ((uint8_t)0x06U)
-#define RTC_WEEKDAY_SUNDAY                  ((uint8_t)0x07U)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
-  * @{
-  */
-#define RTC_ALARMDATEWEEKDAYSEL_DATE        0x00000000u
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY     RTC_ALRMAR_WDSEL
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
-  * @{
-  */
-#define RTC_ALARMMASK_NONE                  0x00000000u
-#define RTC_ALARMMASK_DATEWEEKDAY           RTC_ALRMAR_MSK4
-#define RTC_ALARMMASK_HOURS                 RTC_ALRMAR_MSK3
-#define RTC_ALARMMASK_MINUTES               RTC_ALRMAR_MSK2
-#define RTC_ALARMMASK_SECONDS               RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL                   (RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS  | \
-                                             RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS)
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
-  * @{
-  */
-#define RTC_ALARM_A                         RTC_CR_ALRAE
-#define RTC_ALARM_B                         RTC_CR_ALRBE
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
-  * @{
-  */
-#define RTC_ALARMSUBSECONDMASK_ALL          0x00000000u                                                              /*!< All Alarm SS fields are masked.
-                                                                                                                          There is no comparison on sub seconds
-                                                                                                                          for Alarm */
-#define RTC_ALARMSUBSECONDMASK_SS14_1       RTC_ALRMASSR_MASKSS_0                                                    /*!< SS[14:1] not used in Alarm
-                                                                                                                          comparison. Only SS[0] is compared.    */
-#define RTC_ALARMSUBSECONDMASK_SS14_2       RTC_ALRMASSR_MASKSS_1                                                    /*!< SS[14:2] not used in Alarm
-                                                                                                                          comparison. Only SS[1:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_3       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)                          /*!< SS[14:3] not used in Alarm
-                                                                                                                          comparison. Only SS[2:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_4       RTC_ALRMASSR_MASKSS_2                                                    /*!< SS[14:4] not used in Alarm
-                                                                                                                          comparison. Only SS[3:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_5       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)                          /*!< SS[14:5] not used in Alarm
-                                                                                                                          comparison. Only SS[4:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_6       (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)                          /*!< SS[14:6] not used in Alarm
-                                                                                                                          comparison. Only SS[5:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_7       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)  /*!< SS[14:7] not used in Alarm
-                                                                                                                          comparison. Only SS[6:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_8       RTC_ALRMASSR_MASKSS_3                                                    /*!< SS[14:8] not used in Alarm
-                                                                                                                          comparison. Only SS[7:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_9       (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)                          /*!< SS[14:9] not used in Alarm
-                                                                                                                          comparison. Only SS[8:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_10      (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)                          /*!< SS[14:10] not used in Alarm
-                                                                                                                          comparison. Only SS[9:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_11      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14:11] not used in Alarm
-                                                                                                                          comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_12      (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)                          /*!< SS[14:12] not used in Alarm
-                                                                                                                          comparison.Only SS[11:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_13      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14:13] not used in Alarm
-                                                                                                                          comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14         (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)  /*!< SS[14] not used in Alarm
-                                                                                                                          comparison. Only SS[13:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_NONE         RTC_ALRMASSR_MASKSS                                                      /*!< SS[14:0] are compared and must match
-                                                                                                                          to activate alarm. */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
-  * @{
-  */
-#define RTC_IT_TS                           RTC_CR_TSIE        /*!< Enable Timestamp Interrupt    */
-#define RTC_IT_WUT                          RTC_CR_WUTIE       /*!< Enable Wakeup timer Interrupt */
-#define RTC_IT_SSRU                         RTC_CR_SSRUIE      /*!< Enable SSR Underflow Interrupt */
-#define RTC_IT_ALRA                         RTC_CR_ALRAIE      /*!< Enable Alarm A Interrupt      */
-#define RTC_IT_ALRB                         RTC_CR_ALRBIE      /*!< Enable Alarm B Interrupt      */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Flag_Mask    RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
-  * @{
-  */
-#define RTC_FLAG_MASK                       0x001Fu            /*!< RTC flags mask (5bits) */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
-  *        Elements values convention: 000000XX000YYYYYb
-  *           - YYYYY  : Interrupt flag position in the XX register (5bits)
-  *           - XX  : Interrupt status register (2bits)
-  *                 - 01: ICSR register
-  *                 - 10: SR or SCR or MISR or SMISR registers
-  * @{
-  */
-#define RTC_FLAG_RECALPF                    (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */
-#define RTC_FLAG_INITF                      (0x00000100U | RTC_ICSR_INITF_Pos)   /*!< Initialization flag */
-#define RTC_FLAG_RSF                        (0x00000100U | RTC_ICSR_RSF_Pos)     /*!< Registers synchronization flag */
-#define RTC_FLAG_INITS                      (0x00000100U | RTC_ICSR_INITS_Pos)   /*!< Initialization status flag */
-#define RTC_FLAG_SHPF                       (0x00000100U | RTC_ICSR_SHPF_Pos)    /*!< Shift operation pending flag */
-#define RTC_FLAG_WUTWF                      (0x00000100U | RTC_ICSR_WUTWF_Pos)   /*!< Wakeup timer write flag */
-#define RTC_FLAG_SSRUF                      (0x00000200U | RTC_SR_SSRUF_Pos)     /*!< SSR underflow flag */
-#define RTC_FLAG_ITSF                       (0x00000200U | RTC_SR_ITSF_Pos)      /*!< Internal Time-stamp flag */
-#define RTC_FLAG_TSOVF                      (0x00000200U | RTC_SR_TSOVF_Pos)     /*!< Time-stamp overflow flag */
-#define RTC_FLAG_TSF                        (0x00000200U | RTC_SR_TSF_Pos)       /*!< Time-stamp flag */
-#define RTC_FLAG_WUTF                       (0x00000200U | RTC_SR_WUTF_Pos)      /*!< Wakeup timer flag */
-#define RTC_FLAG_ALRBF                      (0x00000200U | RTC_SR_ALRBF_Pos)     /*!< Alarm B flag */
-#define RTC_FLAG_ALRAF                      (0x00000200U | RTC_SR_ALRAF_Pos)     /*!< Alarm A flag */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions
-  * @{
-  */
-#define RTC_CLEAR_SSRUF                     RTC_SCR_CSSRUF   /*!< Clear SSR underflow flag */
-#define RTC_CLEAR_ITSF                      RTC_SCR_CITSF    /*!< Clear Internal Time-stamp flag */
-#define RTC_CLEAR_TSOVF                     RTC_SCR_CTSOVF   /*!< Clear Time-stamp overflow flag */
-#define RTC_CLEAR_TSF                       RTC_SCR_CTSF     /*!< Clear Time-stamp flag */
-#define RTC_CLEAR_WUTF                      RTC_SCR_CWUTF    /*!< Clear Wakeup timer flag */
-#define RTC_CLEAR_ALRBF                     RTC_SCR_CALRBF   /*!< Clear Alarm B flag */
-#define RTC_CLEAR_ALRAF                     RTC_SCR_CALRAF   /*!< Clear Alarm A flag */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RTC_Exported_Macros RTC Exported Macros
-  * @{
-  */
-
-/** @brief Reset RTC handle state
-  * @param  __HANDLE__ RTC handle.
-  * @retval None
-  */
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
-                                                      (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
-                                                      (__HANDLE__)->MspInitCallback = NULL;\
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
-                                                     }while(0)
-#else
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Disable the write protection for RTC registers.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
-                        do{                                       \
-                            RTC->WPR = 0xCAU;   \
-                            RTC->WPR = 0x53U;   \
-                          } while(0U)
-
-/**
-  * @brief  Enable the write protection for RTC registers.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
-                        do{                                       \
-                            RTC->WPR = 0xFFU;   \
-                          } while(0U)
-
-/**
-  * @brief  Add 1 hour (summer time change).
-  * @note   This interface is deprecated.
-  *         To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __BKP__ Backup
-  *         This parameter can be:
-  *            @arg @ref RTC_STOREOPERATION_RESET
-  *            @arg @ref RTC_STOREOPERATION_SET
-  * @retval None
-  */
-#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__)                         \
-                        do {                                                              \
-                            __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                \
-                            SET_BIT(RTC->CR, RTC_CR_ADD1H);            \
-                            MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \
-                            __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                 \
-                        } while(0);
-
-/**
-  * @brief  Subtract 1 hour (winter time change).
-  * @note   This interface is deprecated. 
-  *         To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __BKP__ Backup
-  *         This parameter can be:
-  *            @arg @ref RTC_STOREOPERATION_RESET
-  *            @arg @ref RTC_STOREOPERATION_SET
-  * @retval None
-  */
-#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__)                         \
-                        do {                                                              \
-                            __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                \
-                            SET_BIT(RTC->CR, RTC_CR_SUB1H);            \
-                            MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \
-                            __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                 \
-                        } while(0);
-
-/**
- * @brief  Enable the RTC ALARMA peripheral.
- * @param  __HANDLE__ specifies the RTC handle.
- * @retval None
- */
-#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)  (RTC->CR |= (RTC_CR_ALRAE))
-
-/**
-  * @brief  Disable the RTC ALARMA peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)  (RTC->CR &= ~(RTC_CR_ALRAE))
-
-/**
-  * @brief  Enable the RTC ALARMB peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)   (RTC->CR |= (RTC_CR_ALRBE))
-
-/**
-  * @brief  Disable the RTC ALARMB peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)  (RTC->CR &= ~(RTC_CR_ALRBE))
-
-/**
-  * @brief  Enable the RTC Alarm interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
-  *          This parameter can be any combination of the following values:
-  *             @arg @ref RTC_IT_ALRA Alarm A interrupt
-  *             @arg @ref RTC_IT_ALRB Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (RTC->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Alarm interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg @ref RTC_IT_ALRA Alarm A interrupt
-  *            @arg @ref RTC_IT_ALRB Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
-  *         This parameter can be:
-  *            @arg @ref RTC_IT_ALRA Alarm A interrupt
-  *            @arg @ref RTC_IT_ALRB Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)
-
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
-  *         This parameter can be:
-  *            @arg @ref RTC_IT_ALRA Alarm A interrupt
-  *            @arg @ref RTC_IT_ALRB Alarm B interrupt
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
-
-/**
-  * @brief  Get the selected RTC Alarms flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Alarm Flag sources to check.
-  *         This parameter can be:
-  *            @arg @ref RTC_FLAG_ALRAF
-  *            @arg @ref RTC_FLAG_ALRBF
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)   (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
-
-/**
-  * @brief  Clear the RTC Alarms pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.
-  *          This parameter can be:
-  *             @arg @ref RTC_FLAG_ALRAF
-  *             @arg @ref RTC_FLAG_ALRBF
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)   (((__FLAG__) == RTC_FLAG_ALRAF) ? ((RTC->SCR = (RTC_CLEAR_ALRAF))) : \
-                                                           (RTC->SCR = (RTC_CLEAR_ALRBF)))
-
-#if defined(CORE_CM0PLUS)
-#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->C2IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->C2EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()        (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-#else
-#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
-#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
-#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()        (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
-#endif
-
-
-/**
-  * @}
-  */
-
-/* Include RTC HAL Extended module */
-#include "stm32wlxx_hal_rtc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Functions RTC Exported Functions
-  * @{
-  */
-
-/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
-
-void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
-void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
-  * @{
-  */
-/* RTC Time and Date functions ************************************************/
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-void              HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
-uint32_t          HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
-  * @{
-  */
-/* RTC Alarm functions ********************************************************/
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
-void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @defgroup  RTC_Exported_Functions_Group4 Peripheral Control functions
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
-  * @{
-  */
-/* Peripheral State functions *************************************************/
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTC_Private_Constants RTC Private Constants
-  * @{
-  */
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK                (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
-                                            RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
-                                            RTC_TR_SU)
-#define RTC_DR_RESERVED_MASK                (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
-                                            RTC_DR_MT | RTC_DR_MU | RTC_DR_DT  | \
-                                            RTC_DR_DU)
-#define RTC_INIT_MASK                       0xFFFFFFFFu
-#define RTC_RSF_MASK                        (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
-
-#define RTC_TIMEOUT_VALUE                   1000u
-
-#define RTC_EXTI_LINE_ALARM_EVENT           EXTI_IMR1_IM17  /*!< External interrupt line 17 Connected to the RTC Alarm event */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTC_Private_Macros RTC Private Macros
-  * @{
-  */
-
-/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
-  * @{
-  */
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
-                                ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
-                                ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
-                                ((OUTPUT) == RTC_OUTPUT_WAKEUP)  || \
-                                ((OUTPUT) == RTC_OUTPUT_TAMPER))
-
-#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
-                                        ((FORMAT) == RTC_HOURFORMAT_24))
-
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
-                                ((POL) == RTC_OUTPUT_POLARITY_LOW))
-
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
-                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-
-#define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \
-                                    ((TYPE) == RTC_OUTPUT_PULLUP_ON))
-
-#define IS_RTC_OUTPUT_REMAP(REMAP)   (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
-                                      ((REMAP) == RTC_OUTPUT_REMAP_POS1))
-
-#define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || \
-                                  ((PM) == RTC_HOURFORMAT12_PM))
-
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
-                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
-                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
-
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
-                                           ((OPERATION) == RTC_STOREOPERATION_SET))
-
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \
-                               ((FORMAT) == RTC_FORMAT_BCD))
-
-#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99u)
-
-#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1u) && ((MONTH) <= 12u))
-
-#define IS_RTC_DATE(DATE)              (((DATE) >= 1u) && ((DATE) <= 31u))
-
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
-                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-
-#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0UL)
-
-#define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || \
-                                  ((ALARM) == RTC_ALARM_B))
-
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
-
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)          (((MASK) == 0UL) || \
-                                                    (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE)))
-
-#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))
-
-#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))
-
-#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0u) && ((HOUR) <= 12u))
-
-#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23u)
-
-#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59u)
-
-#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59u)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions -------------------------------------------------------------*/
-/** @defgroup RTC_Private_Functions RTC Private Functions
-  * @{
-  */
-HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef  RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
-uint8_t            RTC_ByteToBcd2(uint8_t Value);
-uint8_t            RTC_Bcd2ToByte(uint8_t Value);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h

@@ -1,1374 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_rtc_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of RTC HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_RTC_EX_H
-#define STM32WLxx_HAL_RTC_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RTCEx RTCEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
-  * @{
-  */
-
-/** @defgroup RTCEx_Tamper_structure_definition RTCEx Tamper structure definition
-  * @{
-  */
-typedef struct
-{
-  uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pins */
-
-  uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Trigger */
-
-  uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.
-                                             This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */
-
-  uint32_t MaskFlag;                    /*!< Specifies the Tamper Flag masking.
-                                             This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */
-
-  uint32_t Filter;                      /*!< Specifies the TAMP Filter Tamper.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Filter */
-
-  uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies */
-
-  uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration */
-
-  uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pull_UP */
-
-  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
-                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */
-} RTC_TamperTypeDef;
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition
-  * @{
-  */
-typedef struct
-{
-  uint32_t IntTamper;                   /*!< Specifies the Internal Tamper Pin.
-                                             This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */
-
-  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
-                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */
-
-  uint32_t NoErase;                     /*!< Specifies the internal Tamper no erase mode.
-                                             This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */
-} RTC_InternalTamperTypeDef;
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
-  * @{
-  */
-#define RTC_TIMESTAMPEDGE_RISING        0x00000000u
-#define RTC_TIMESTAMPEDGE_FALLING       RTC_CR_TSEDGE
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
-  * @{
-  */
-#define RTC_TIMESTAMPPIN_DEFAULT              0x00000000u
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
-  * @{
-  */
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        0x00000000u
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         RTC_CR_WUCKSEL_0
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         RTC_CR_WUCKSEL_1
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      RTC_CR_WUCKSEL_2
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
-  * @{
-  */
-#define RTC_SMOOTHCALIB_PERIOD_32SEC   0x00000000u              /*!< If RTCCLK = 32768 Hz, Smooth calibration
-                                                                     period is 32s,  else 2exp20 RTCCLK pulses */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC   RTC_CALR_CALW16          /*!< If RTCCLK = 32768 Hz, Smooth calibration
-                                                                     period is 16s, else 2exp19 RTCCLK pulses */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC    RTC_CALR_CALW8           /*!< If RTCCLK = 32768 Hz, Smooth calibration
-                                                                     period is 8s, else 2exp18 RTCCLK pulses */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions
-  * @{
-  */
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET    RTC_CALR_CALP         /*!< The number of RTCCLK pulses added
-                                                                     during a X -second window = Y - CALM[8:0]
-                                                                     with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET  0x00000000u           /*!< The number of RTCCLK pulses subbstited
-                                                                     during a 32-second window = CALM[8:0] */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_calib_low_power_Definitions RTCEx Smooth calib Low Power Definitions
-  * @{
-  */
-#define RTC_LPCAL_SET                     RTC_CALR_LPCAL        /*!< Calibration window is 220 ck_apre,
-                                                                     which is the required configuration for
-                                                                     ultra-low consumption mode. */
-#define RTC_LPCAL_RESET                   0x00000000u           /*!< Calibration window is 220 RTCCLK,
-                                                                     which is a high-consumption mode.
-                                                                     This mode should be set only when less
-                                                                     than 32s calibration window is required. */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
- * @{
- */
-#define RTC_CALIBOUTPUT_512HZ            0x00000000u
-#define RTC_CALIBOUTPUT_1HZ              RTC_CR_COSEL
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions
-  * @{
-  */
-#define RTC_SHIFTADD1S_RESET      0x00000000u
-#define RTC_SHIFTADD1S_SET        RTC_SHIFTR_ADD1S
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pins  RTCEx Tamper Pins Definition
-  * @{
-  */
-#define RTC_TAMPER_1                        TAMP_CR1_TAMP1E
-#define RTC_TAMPER_2                        TAMP_CR1_TAMP2E
-#define RTC_TAMPER_3                        TAMP_CR1_TAMP3E
-#define RTC_TAMPER_ALL                      (TAMP_CR1_TAMP1E | TAMP_CR1_TAMP2E |  TAMP_CR1_TAMP3E)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Internal_Tamper_Pins  RTCEx Internal Tamper Pins Definition
-  * @{
-  */
-#define RTC_INT_TAMPER_3                    TAMP_CR1_ITAMP3E
-#define RTC_INT_TAMPER_5                    TAMP_CR1_ITAMP5E
-#define RTC_INT_TAMPER_6                    TAMP_CR1_ITAMP6E
-#define RTC_INT_TAMPER_8                    TAMP_CR1_ITAMP8E
-#define RTC_INT_TAMPER_ALL                  (TAMP_CR1_ITAMP3E | TAMP_CR1_ITAMP5E | TAMP_CR1_ITAMP6E | TAMP_CR1_ITAMP8E)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Trigger  RTCEx Tamper Trigger
-  * @{
-  */
-#define RTC_TAMPERTRIGGER_RISINGEDGE        0x00u  /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
-#define RTC_TAMPERTRIGGER_FALLINGEDGE       0x01u  /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
-#define RTC_TAMPERTRIGGER_LOWLEVEL          0x02u  /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
-#define RTC_TAMPERTRIGGER_HIGHLEVEL         0x03u  /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_MaskFlag  RTCEx Tamper MaskFlag
-  * @{
-  */
-#define RTC_TAMPERMASK_FLAG_DISABLE         0x00u
-#define RTC_TAMPERMASK_FLAG_ENABLE          0x01u
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_EraseBackUp  RTCEx Tamper EraseBackUp
-* @{
-*/
-#define RTC_TAMPER_ERASE_BACKUP_ENABLE      0x00u
-#define RTC_TAMPER_ERASE_BACKUP_DISABLE     0x01u
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Filter  RTCEx Tamper Filter
-  * @{
-  */
-#define RTC_TAMPERFILTER_DISABLE           0x00000000U             /*!< Tamper filter is disabled */
-#define RTC_TAMPERFILTER_2SAMPLE           TAMP_FLTCR_TAMPFLT_0    /*!< Tamper is activated after 2
-                                                                         consecutive samples at the active level */
-#define RTC_TAMPERFILTER_4SAMPLE           TAMP_FLTCR_TAMPFLT_1    /*!< Tamper is activated after 4
-                                                                         consecutive samples at the active level */
-#define RTC_TAMPERFILTER_8SAMPLE           TAMP_FLTCR_TAMPFLT      /*!< Tamper is activated after 8
-                                                                         consecutive samples at the active level */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies  RTCEx Tamper Sampling Frequencies
-  * @{
-  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  0x00000000U                                     /*!< Each of the tamper inputs are sampled
-                                                                                                      with a frequency =  RTCCLK / 32768 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  TAMP_FLTCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled
-                                                                                                      with a frequency =  RTCCLK / 16384 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   TAMP_FLTCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled
-                                                                                                      with a frequency =  RTCCLK / 8192  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
-                                                                                                      with a frequency =  RTCCLK / 4096  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   TAMP_FLTCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled
-                                                                                                      with a frequency =  RTCCLK / 2048  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
-                                                                                                      with a frequency =  RTCCLK / 1024  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
-                                                                                                      with a frequency =  RTCCLK / 512   */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1 | \
-                                                  TAMP_FLTCR_TAMPFREQ_2)                         /*!< Each of the tamper inputs are sampled
-                                                                                                      with a frequency =  RTCCLK / 256   */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration  RTCEx Tamper Pin Precharge Duration
-  * @{
-  */
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK     0x00000000U                                       /*!< Tamper pins are pre-charged before
-                                                                                                        sampling during 1 RTCCLK cycle  */
-#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK     TAMP_FLTCR_TAMPPRCH_0                             /*!< Tamper pins are pre-charged before
-                                                                                                        sampling during 2 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK     TAMP_FLTCR_TAMPPRCH_1                             /*!< Tamper pins are pre-charged before
-                                                                                                        sampling during 4 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK     (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1)   /*!< Tamper pins are pre-charged before
-                                                                                                        sampling during 8 RTCCLK cycles */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pull_UP  RTCEx Tamper Pull UP
-  * @{
-  */
-#define RTC_TAMPER_PULLUP_ENABLE           0x00000000u           /*!< Tamper pins are pre-charged before sampling */
-#define RTC_TAMPER_PULLUP_DISABLE          TAMP_FLTCR_TAMPPUDIS  /*!< Tamper pins pre-charge is disabled          */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection RTCEx Tamper TimeStamp On Tamper Detection Definitions
-  * @{
-  */
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE  0x00000000u    /*!< TimeStamp on Tamper Detection event is not saved */
-#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE   RTC_CR_TAMPTS  /*!< TimeStamp on Tamper Detection event saved        */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Internal_Tamper_Interrupt  RTCEx Internal Tamper Interrupt
-  * @{
-  */
-#define RTC_IT_TAMP_1                      TAMP_IER_TAMP1IE     /*!< Tamper 1 Interrupt */
-#define RTC_IT_TAMP_2                      TAMP_IER_TAMP2IE     /*!< Tamper 2 Interrupt */
-#define RTC_IT_TAMP_3                      TAMP_IER_TAMP3IE     /*!< Tamper 3 Interrupt */
-#define RTC_IT_TAMP_ALL                    (TAMP_IER_TAMP1IE | TAMP_IER_TAMP2IE | TAMP_IER_TAMP3IE)
-
-#define RTC_IT_INT_TAMP_3                  TAMP_IER_ITAMP3IE
-#define RTC_IT_INT_TAMP_5                  TAMP_IER_ITAMP5IE
-#define RTC_IT_INT_TAMP_6                  TAMP_IER_ITAMP6IE
-#define RTC_IT_INT_TAMP_8                  TAMP_IER_ITAMP8IE
-#define RTC_IT_INT_TAMP_ALL                (TAMP_IER_ITAMP3IE | TAMP_IER_ITAMP5IE | TAMP_IER_ITAMP6IE | TAMP_IER_ITAMP8IE)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Flags  RTCEx Flags
-  * @{
-  */
-#define RTC_FLAG_TAMP_1                    TAMP_SR_TAMP1F
-#define RTC_FLAG_TAMP_2                    TAMP_SR_TAMP2F
-#define RTC_FLAG_TAMP_3                    TAMP_SR_TAMP3F
-#define RTC_FLAG_TAMP_ALL                  (RTC_FLAG_TAMP1 | RTC_FLAG_TAMP2 | RTC_FLAG_TAMP3 )
-
-
-#define RTC_FLAG_INT_TAMP_3                 TAMP_SR_ITAMP3F
-#define RTC_FLAG_INT_TAMP_5                 TAMP_SR_ITAMP5F
-#define RTC_FLAG_INT_TAMP_6                 TAMP_SR_ITAMP6F
-#define RTC_FLAG_INT_TAMP_8                 TAMP_SR_ITAMP8F
-#define RTC_FLAG_INT_TAMP_ALL               (RTC_FLAG_INT_TAMP3 | RTC_FLAG_INT_TAMP5 | RTC_FLAG_INT_TAMP6 | RTC_FLAG_INT_TAMP8)
-/**
-  * @}
-  */
-
-
-/** @defgroup RTCEx_MonotonicCounter_Instance  RTCEx Monotonic Counter Instance Definition
-  * @{
-  */
-#define RTC_MONOTONIC_COUNTER_1           0u   /*!< Monotonic counter 1 */
-/**
-  * @}
-  */
-
-
-/** @defgroup RTCEx_Backup_Registers  RTCEx Backup Registers Definition
-  * @{
-  */
-#define RTC_BKP_NUMBER                    RTC_BACKUP_NB
-#define RTC_BKP_DR0                       0x00u
-#define RTC_BKP_DR1                       0x01u
-#define RTC_BKP_DR2                       0x02u
-#define RTC_BKP_DR3                       0x03u
-#define RTC_BKP_DR4                       0x04u
-#define RTC_BKP_DR5                       0x05u
-#define RTC_BKP_DR6                       0x06u
-#define RTC_BKP_DR7                       0x07u
-#define RTC_BKP_DR8                       0x08u
-#define RTC_BKP_DR9                       0x09u
-#define RTC_BKP_DR10                      0x0Au
-#define RTC_BKP_DR11                      0x0Bu
-#define RTC_BKP_DR12                      0x0Cu
-#define RTC_BKP_DR13                      0x0Du
-#define RTC_BKP_DR14                      0x0Eu
-#define RTC_BKP_DR15                      0x0Fu
-#define RTC_BKP_DR16                      0x10u
-#define RTC_BKP_DR17                      0x11u
-#define RTC_BKP_DR18                      0x12u
-#define RTC_BKP_DR19                      0x13u
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Binary_Mode RTC Binary Mode (32-bit free-running counter configuration).
-  *           Warning : It Should not be confused with the Binary format @ref RTC_Input_parameter_format_definitions.
-  * @{
-  */
-#define RTC_BINARY_NONE                     0x00000000u      /*!< Free running BCD calendar mode (Binary mode disabled). */
-#define RTC_BINARY_ONLY                     RTC_ICSR_BIN_0   /*!< Free running Binary mode (BCD mode disabled) */
-#define RTC_BINARY_MIX                      RTC_ICSR_BIN_1   /*!< Free running BCD calendar and Binary mode */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Binary_mix_BCDU If Binary mode is RTC_BINARY_MIX, the BCD calendar second is incremented using the SSR Least Significant Bits.
-  * @{
-  */
-#define RTC_BINARY_MIX_BCDU_0  0x00000000u                   /*!<  The 1s BCD calendar increment is generated each time SS[7:0] = 0 */
-#define RTC_BINARY_MIX_BCDU_1  (0x1UL << RTC_ICSR_BCDU_Pos)  /*!<  The 1s BCD calendar increment is generated each time SS[8:0] = 0 */
-#define RTC_BINARY_MIX_BCDU_2  (0x2UL << RTC_ICSR_BCDU_Pos)  /*!<  The 1s BCD calendar increment is generated each time SS[9:0] = 0 */
-#define RTC_BINARY_MIX_BCDU_3  (0x3UL << RTC_ICSR_BCDU_Pos)  /*!<  The 1s BCD calendar increment is generated each time SS[10:0] = 0 */
-#define RTC_BINARY_MIX_BCDU_4  (0x4UL << RTC_ICSR_BCDU_Pos)  /*!<  The 1s BCD calendar increment is generated each time SS[11:0] = 0 */
-#define RTC_BINARY_MIX_BCDU_5  (0x5UL << RTC_ICSR_BCDU_Pos)  /*!<  The 1s BCD calendar increment is generated each time SS[12:0] = 0 */
-#define RTC_BINARY_MIX_BCDU_6  (0x6UL << RTC_ICSR_BCDU_Pos)  /*!<  The 1s BCD calendar increment is generated each time SS[13:0] = 0 */
-#define RTC_BINARY_MIX_BCDU_7  (0x7UL << RTC_ICSR_BCDU_Pos)  /*!<  The 1s BCD calendar increment is generated each time SS[14:0] = 0 */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Masks_Definitions RTC Alarm Sub Seconds with binary mode Masks Definitions
-  * @{
-  */
-#define RTC_ALARMSUBSECONDBINMASK_ALL           0x00000000u                                                             /*!< All Alarm SS fields are masked.
-                                                                                                                          There is no comparison on sub seconds for Alarm */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_1        (1UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:1] are don't care in Alarm
-                                                                                                                          comparison. Only SS[0] is compared.    */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_2        (2UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:2] are don't care in Alarm
-                                                                                                                          comparison. Only SS[1:0] are compared  */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_3        (3UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:3] are don't care in Alarm
-                                                                                                                          comparison. Only SS[2:0] are compared  */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_4        (4UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:4] are don't care in Alarm
-                                                                                                                          comparison. Only SS[3:0] are compared  */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_5        (5UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:5] are don't care in Alarm
-                                                                                                                          comparison. Only SS[4:0] are compared  */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_6        (6UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:6] are don't care in Alarm
-                                                                                                                          comparison. Only SS[5:0] are compared  */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_7        (7UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:7] are don't care in Alarm
-                                                                                                                          comparison. Only SS[6:0] are compared  */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_8        (8UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:8] are don't care in Alarm
-                                                                                                                          comparison. Only SS[7:0] are compared  */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_9        (9UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:9] are don't care in Alarm
-                                                                                                                          comparison. Only SS[8:0] are compared  */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_10      (10UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:10] are don't care in Alarm
-                                                                                                                          comparison. Only SS[9:0] are compared  */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_11      (11UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:11] are don't care in Alarm
-                                                                                                                          comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_12      (12UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:12] are don't care in Alarm
-                                                                                                                          comparison.Only SS[11:0] are compared  */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_13      (13UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:13] are don't care in Alarm
-                                                                                                                          comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_14      (14UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:14] are don't care in Alarm
-                                                                                                                          comparison. Only SS[13:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_15      (15UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:15] are don't care in Alarm
-                                                                                                                          comparison. Only SS[14:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_16      (16UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:16] are don't care in Alarm
-                                                                                                                          comparison. Only SS[15:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_17      (17UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:17] are don't care in Alarm
-                                                                                                                          comparison. Only SS[16:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_18      (18UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:18] are don't care in Alarm
-                                                                                                                          comparison. Only SS[17:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_19      (19UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:19] are don't care in Alarm
-                                                                                                                          comparison. Only SS[18:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_20      (20UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:20] are don't care in Alarm
-                                                                                                                          comparison. Only SS[19:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_21      (21UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:21] are don't care in Alarm
-                                                                                                                          comparison. Only SS[20:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_22      (22UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:22] are don't care in Alarm
-                                                                                                                          comparison. Only SS[21:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_23      (23UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:23] are don't care in Alarm
-                                                                                                                          comparison. Only SS[22:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_24      (24UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:24] are don't care in Alarm
-                                                                                                                          comparison. Only SS[23:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_25      (25UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:25] are don't care in Alarm
-                                                                                                                          comparison. Only SS[24:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_26      (26UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:26] are don't care in Alarm
-                                                                                                                          comparison. Only SS[25:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_27      (27UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:27] are don't care in Alarm
-                                                                                                                          comparison. Only SS[26:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_28      (28UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:28] are don't care in Alarm
-                                                                                                                          comparison. Only SS[27:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_29      (29UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:29] are don't care in Alarm
-                                                                                                                          comparison. Only SS[28:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31_30      (30UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:30] are don't care in Alarm
-                                                                                                                          comparison. Only SS[29:0] are compared */
-#define RTC_ALARMSUBSECONDBINMASK_SS31         (31UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31] is don't care in Alarm
-                                                                                                                          comparison. Only SS[30:0] are compared  */
-#define RTC_ALARMSUBSECONDBINMASK_NONE         (32UL << RTC_ALRMASSR_MASKSS_Pos)                                        /*!< SS[31:0] are compared and must match to activate alarm. */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Alarm_Sub_Seconds_binary_Clear_Definitions RTC Alarm Sub Seconds with binary mode auto clear Definitions
-  * @{
-  */
-#define RTC_ALARMSUBSECONDBIN_AUTOCLR_NO    0UL                  /*!<  The synchronous Binary counter (SS[31:0] in RTC_SSR) is free-running. */
-#define RTC_ALARMSUBSECONDBIN_AUTOCLR_YES   RTC_ALRMASSR_SSCLR   /*!<  The synchronous Binary counter (SS[31:0] in RTC_SSR) is running from 0xFFFF FFFF to
-                                                                          RTC_ALRMABINR -> SS[31:0] value and is automatically reloaded with 0xFFFF FFFF
-                                                                          whenreaching RTC_ALRMABINR -> SS[31:0]. */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
-  * @{
-  */
-
-/** @brief  Clear the specified RTC pending flag.
-  * @param  __HANDLE__ specifies the RTC Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref RTC_CLEAR_ITSF               Clear Internal Time-stamp flag
-  *            @arg @ref RTC_CLEAR_TSOVF              Clear Time-stamp overflow flag
-  *            @arg @ref RTC_CLEAR_TSF                Clear Time-stamp flag
-  *            @arg @ref RTC_CLEAR_WUTF               Clear Wakeup timer flag
-  *            @arg @ref RTC_CLEAR_ALRBF              Clear Alarm B flag
-  *            @arg @ref RTC_CLEAR_ALRAF              Clear Alarm A flag
-  * @retval None
-  */
-#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__)   (RTC->SCR = (__FLAG__))
-
-/** @brief  Check whether the specified RTC flag is set or not.
-  * @param  __HANDLE__ specifies the RTC Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref RTC_FLAG_RECALPF             Recalibration pending Flag
-  *            @arg @ref RTC_FLAG_INITF               Initialization flag
-  *            @arg @ref RTC_FLAG_RSF                 Registers synchronization flag
-  *            @arg @ref RTC_FLAG_INITS               Initialization status flag
-  *            @arg @ref RTC_FLAG_SHPF                Shift operation pending flag
-  *            @arg @ref RTC_FLAG_WUTWF               Wakeup timer write flag
-  *            @arg @ref RTC_FLAG_ITSF                Internal Time-stamp flag
-  *            @arg @ref RTC_FLAG_TSOVF               Time-stamp overflow flag
-  *            @arg @ref RTC_FLAG_TSF                 Time-stamp flag
-  *            @arg @ref RTC_FLAG_WUTF                Wakeup timer flag
-  *            @arg @ref RTC_FLAG_ALRBF               Alarm B flag
-  *            @arg @ref RTC_FLAG_ALRAF               Alarm A flag
-  * @retval None
-  */
-#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__)    (((((__FLAG__)) >> 8U) == 1U) ? (RTC->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \
-                                                     (RTC->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))))
-
-/* ---------------------------------WAKEUPTIMER---------------------------------*/
-/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
-  * @{
-  */
-/**
-  * @brief  Enable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      (RTC->CR |= (RTC_CR_WUTE))
-
-/**
-  * @brief  Disable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     (RTC->CR &= ~(RTC_CR_WUTE))
-
-/**
-  * @brief  Enable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
-  *         This parameter can be:
-  *            @arg @ref RTC_IT_WUT WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (RTC->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
-  *         This parameter can be:
-  *            @arg @ref RTC_IT_WUT WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   (RTC->CR &= ~(__INTERRUPT__))
-
-
-/**
-  * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
-  *         This parameter can be:
-  *            @arg @ref RTC_IT_WUT  WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)       ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != 0UL) ? 1UL : 0UL)
-/**
-  * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
-  *         This parameter can be:
-  *            @arg @ref RTC_IT_WUT  WakeUpTimer interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   ((((RTC->CR) & (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)
-
-/**
-  * @brief  Get the selected RTC WakeUpTimers flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
-  *          This parameter can be:
-  *             @arg @ref RTC_FLAG_WUTF
-  *             @arg @ref RTC_FLAG_WUTWF
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
-
-/**
-  * @brief  Clear the RTC Wake Up timers pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
-  *         This parameter can be:
-  *            @arg @ref RTC_FLAG_WUTF
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__)     (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF))
-
-/* WAKE-UP TIMER EXTI */
-/* ------------------ */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->C2IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->C2EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-#else
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
-#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
-#endif
-
-/**
-  * @}
-  */
-
-
-
-
-
-/* ---------------------------------TIMESTAMP---------------------------------*/
-/** @defgroup RTCEx_Timestamp RTC Timestamp
-  * @{
-  */
-/**
-  * @brief  Enable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       (RTC->CR |= (RTC_CR_TSE))
-
-/**
-  * @brief  Disable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      (RTC->CR &= ~(RTC_CR_TSE))
-
-/**
-  * @brief  Enable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
-  *         This parameter can be:
-  *            @arg @ref RTC_IT_TS TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     (RTC->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
-  *         This parameter can be:
-  *            @arg @ref RTC_IT_TS TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    (RTC->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
-  *         This parameter can be:
-  *            @arg @ref RTC_IT_TS TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)
-/**
-  * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
-  *         This parameter can be:
-  *            @arg @ref RTC_IT_TS TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
-
-/**
-  * @brief  Get the selected RTC TimeStamps flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
-  *         This parameter can be:
-  *            @arg @ref RTC_FLAG_TSF
-  *            @arg @ref RTC_FLAG_TSOVF
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
-
-/**
-  * @brief  Clear the RTC Time Stamps pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC TimeStamp Flag to clear.
-  *          This parameter can be:
-  *             @arg @ref RTC_FLAG_TSF
-  *             @arg @ref RTC_FLAG_TSOVF
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))
-
-/* TIMESTAMP EXTI */
-/* -------------- */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->C2IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
-#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
-#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT()     (EXTI->C2EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
-#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT()    (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
-#else
-#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
-#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
-#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT()     (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
-#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT()    (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
-#endif
-
-/**
-  * @brief  Enable the RTC internal TimeStamp peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                (RTC->CR |= (RTC_CR_ITSE))
-
-/**
-  * @brief  Disable the RTC internal TimeStamp peripheral.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               (RTC->CR &= ~(RTC_CR_ITSE))
-
-/**
-  * @brief  Get the selected RTC Internal Time Stamps flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not.
-  *         This parameter can be:
-  *            @arg @ref RTC_FLAG_ITSF
-  * @retval None
-  */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
-
-/**
-  * @brief  Clear the RTC Internal Time Stamps pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear.
-  * This parameter can be:
-  *             @arg @ref RTC_FLAG_ITSF
-  * @retval None
-  */
-#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)     (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF))
-
-/**
-  * @brief  Enable the RTC TimeStamp on Tamper detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__)                       (RTC->CR |= (RTC_CR_TAMPTS))
-
-/**
-  * @brief  Disable the RTC TimeStamp on Tamper detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__)                      (RTC->CR &= ~(RTC_CR_TAMPTS))
-
-/**
-  * @brief  Enable the RTC Tamper detection output.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__)                       (RTC->CR |= (RTC_CR_TAMPOE))
-
-/**
-  * @brief  Disable the RTC Tamper detection output.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__)                      (RTC->CR &= ~(RTC_CR_TAMPOE))
-
-
-/**
-  * @}
-  */
-
-
-/* ------------------------------Calibration----------------------------------*/
-/** @defgroup RTCEx_Calibration RTC Calibration
-  * @{
-  */
-
-/**
-  * @brief  Enable the RTC calibration output.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)               (RTC->CR |= (RTC_CR_COE))
-
-/**
-  * @brief  Disable the calibration output.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)              (RTC->CR &= ~(RTC_CR_COE))
-
-
-/**
-  * @brief  Enable the clock reference detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)               (RTC->CR |= (RTC_CR_REFCKON))
-
-/**
-  * @brief  Disable the clock reference detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)              (RTC->CR &= ~(RTC_CR_REFCKON))
-
-
-/**
-  * @brief  Get the selected RTC shift operations flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC shift operation Flag is pending or not.
-  *          This parameter can be:
-  *             @arg @ref RTC_FLAG_SHPF
-  * @retval None
-  */
-#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)                (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
-/**
-  * @}
-  */
-
-
-/* ------------------------------Tamper----------------------------------*/
-/** @defgroup RTCEx_Tamper RTCEx tamper
-  * @{
-  */
-/**
-  * @brief  Enable the TAMP Tamper input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __TAMPER__ specifies the RTC Tamper source to be enabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg  RTC_TAMPER_ALL: All tampers
-  *            @arg  RTC_TAMPER_1: Tamper1
-  *            @arg  RTC_TAMPER_2: Tamper2
-  *            @arg  RTC_TAMPER_3: Tamper3
-  *            @arg  RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts
-  *            @arg  RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt
-  *            @arg  RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt
-  *            @arg  RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt
-  *            @arg  RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__)           (TAMP->CR1 |= (__TAMPER__))
-
-/**
-  * @brief  Disable the TAMP Tamper input detection.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __TAMPER__ specifies the RTC Tamper sources to be enabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg  RTC_TAMPER_ALL: All tampers
-  *            @arg  RTC_TAMPER_1: Tamper1
-  *            @arg  RTC_TAMPER_2: Tamper2
-  *            @arg  RTC_TAMPER_3: Tamper3
-  *            @arg  RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts
-  *            @arg  RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt
-  *            @arg  RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt
-  *            @arg  RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt
-  *            @arg  RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt
-  */
-#define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__)           (TAMP->CR1 &= ~(__TAMPER__))
-
-
-/**************************************************************************************************/
-/**
-  * @brief  Enable the TAMP Tamper interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg  RTC_IT_TAMP_ALL: All tampers interrupts
-  *            @arg  RTC_IT_TAMP_1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP_2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP_3: Tamper3 interrupt
-  *            @arg  RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts
-  *            @arg  RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt
-  *            @arg  RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt
-  *            @arg  RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt
-  *            @arg  RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        (TAMP->IER |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the TAMP Tamper interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg  RTC_IT_TAMP_ALL: All tampers interrupts
-  *            @arg  RTC_IT_TAMP_1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP_2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP_3: Tamper3 interrupt
-  *            @arg  RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts
-  *            @arg  RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt
-  *            @arg  RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt
-  *            @arg  RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt
-  *            @arg  RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       (TAMP->IER &= ~(__INTERRUPT__))
-
-
-/**************************************************************************************************/
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP_ALL: All tampers interrupts
-  *            @arg  RTC_IT_TAMP_1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP_2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP_3: Tamper3 interrupt
-  *            @arg  RTC_IT_INT_TAMP_ALL: All Internal Tamper interrupts
-  *            @arg  RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt
-  *            @arg  RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt
-  *            @arg  RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt
-  *            @arg  RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)     ((((TAMP->MISR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
-
-
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP_ALL: All tampers interrupts
-  *            @arg  RTC_IT_TAMP_1: Tamper1 interrupt
-  *            @arg  RTC_IT_TAMP_2: Tamper2 interrupt
-  *            @arg  RTC_IT_TAMP_3: Tamper3 interrupt
-  *            @arg  RTC_IT_INT_TAMP_ALL: All internal tampers interrupts
-  *            @arg  RTC_IT_INT_TAMP_3: Internal Tamper3 interrupt
-  *            @arg  RTC_IT_INT_TAMP_5: Internal Tamper5 interrupt
-  *            @arg  RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt
-  *            @arg  RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    ((((TAMP->IER) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
-
-
-/**
-  * @brief  Get the selected RTC Tampers flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Tamper Flag is pending or not.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP_1: Tamper1 flag
-  *             @arg RTC_FLAG_TAMP_2: Tamper2 flag
-  *             @arg RTC_FLAG_TAMP_3: Tamper3 flag
-  *             @arg RTC_FLAG_INT_TAMP_3: Internal Tamper3 interrupt
-  *             @arg RTC_FLAG_INT_TAMP_5: Internal Tamper5 interrupt
-  *             @arg RTC_FLAG_INT_TAMP_6: Internal Tamper6 interrupt
-  *             @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)        ((((TAMP->SR) & (__FLAG__)) != 0U) ? 1UL : 0UL)
-
-/**
-  * @brief  Clear the RTC Tamper's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Tamper Flag to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_TAMP_ALL: All tampers flag
-  *             @arg RTC_FLAG_TAMP_1: Tamper1 flag
-  *             @arg RTC_FLAG_TAMP_2: Tamper2 flag
-  *             @arg RTC_FLAG_TAMP_3: Tamper3 flag
-  *             @arg RTC_FLAG_INT_TAMP_ALL: All Internal Tamper flags
-  *             @arg RTC_FLAG_INT_TAMP_3: Internal Tamper3 interrupt
-  *             @arg RTC_FLAG_INT_TAMP_5: Internal Tamper5 interrupt
-  *             @arg RTC_FLAG_INT_TAMP_6: Internal Tamper6 interrupt
-  *             @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      (((TAMP->SCR) = (__FLAG__)))
-
-/* TAMPER EXTI */
-/* ----------- */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RTC_TAMPER_EXTI_ENABLE_IT()        (EXTI->C2IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
-#define __HAL_RTC_TAMPER_EXTI_DISABLE_IT()       (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
-#define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT()     (EXTI->C2EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
-#define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT()    (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
-#else
-#define __HAL_RTC_TAMPER_EXTI_ENABLE_IT()        (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
-#define __HAL_RTC_TAMPER_EXTI_DISABLE_IT()       (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
-#define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT()     (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
-#define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT()    (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
-#endif
-
-/**
-  * @}
-  */
-
-/* --------------------------------- SSR Underflow ---------------------------------*/
-/** @defgroup RTCEx_SSR_Underflow RTC SSR Underflow
-  * @{
-  */
-
-/**
-  * @brief  Enable the RTC SSRU interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC SSRU interrupt sources to be enabled.
-  *         This parameter can be:
-  *            @arg @ref RTC_IT_SSRU SSRU interrupt
-  * @retval None
-  */
-#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (RTC->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC SSRU interrupt.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC SSRU interrupt sources to be disabled.
-  *         This parameter can be:
-  *            @arg @ref RTC_IT_SSRU SSRU interrupt
-  * @retval None
-  */
-#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__)   (RTC->CR &= ~(__INTERRUPT__))
-
-
-/**
-  * @brief  Check whether the specified RTC SSRU interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC SSRU interrupt to check.
-  *         This parameter can be:
-  *            @arg @ref RTC_IT_SSRU  SSRU interrupt
-  * @retval None
-  */
-#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__)       (((RTC->MISR) & ((__INTERRUPT__) >> 1) != 0U) ? 1U : 0U)
-/**
-  * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
-  *         This parameter can be:
-  *            @arg @ref RTC_IT_SSRU  SSRU interrupt
-  * @retval None
-  */
-#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
-
-/**
-  * @brief  Get the selected RTC SSRU's flag status.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC SSRU Flag is pending or not.
-  *          This parameter can be:
-  *             @arg @ref RTC_FLAG_SSRUF
-  * @retval None
-  */
-#define __HAL_RTC_SSRU_GET_FLAG(__HANDLE__, __FLAG__)   (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
-
-/**
-  * @brief  Clear the RTC Wake Up timer's pending flags.
-  * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC SSRU Flag to clear.
-  *         This parameter can be:
-  *            @arg @ref RTC_FLAG_SSRUF
-  * @retval None
-  */
-#define __HAL_RTC_SSRU_CLEAR_FLAG(__HANDLE__, __FLAG__)     (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_SSRUF))
-
-/* SSR Underflow EXTI */
-/* ------------------ */
-#if defined(CORE_CM0PLUS)
-#define __HAL_RTC_SSRU_EXTI_ENABLE_IT()       (EXTI->C2IMR1 |= RTC_EXTI_LINE_SSRU_EVENT)
-#define __HAL_RTC_SSRU_EXTI_DISABLE_IT()      (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_SSRU_EVENT))
-#define __HAL_RTC_SSRU_EXTI_ENABLE_EVENT()    (EXTI->C2EMR1 |= RTC_EXTI_LINE_SSRU_EVENT)
-#define __HAL_RTC_SSRU_EXTI_DISABLE_EVENT()   (EXTI->C2EMR1 &= ~(RTC_EXTI_LINE_SSRU_EVENT))
-#else
-#define __HAL_RTC_SSRU_EXTI_ENABLE_IT()       (EXTI->IMR1 |= RTC_EXTI_LINE_SSRU_EVENT)
-#define __HAL_RTC_SSRU_EXTI_DISABLE_IT()      (EXTI->IMR1 &= ~(RTC_EXTI_LINE_SSRU_EVENT))
-#define __HAL_RTC_SSRU_EXTI_ENABLE_EVENT()    (EXTI->EMR1 |= RTC_EXTI_LINE_SSRU_EVENT)
-#define __HAL_RTC_SSRU_EXTI_DISABLE_EVENT()   (EXTI->EMR1 &= ~(RTC_EXTI_LINE_SSRU_EVENT))
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
-  * @{
-  */
-
-/* RTC TimeStamp functions *****************************************/
-/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
-void              HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-
-/* RTC Wake-up functions ******************************************************/
-/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
- * @{
- */
-
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, uint32_t WakeUpAutoClr);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Extended Control functions ************************************************/
-/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
- * @{
- */
-
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
-HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib);
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance);
-HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *Value);
-HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateSSRU(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/* Extended RTC features functions *******************************************/
-/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
-  * @{
-  */
-
-void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper);
-HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout);
-void              HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions
- * @{
- */
-void              HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t          HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
-  * @{
-  */
-/*#define RTC_EXTI_LINE_ALARM_EVENT           EXTI_IMR1_IM17 */ /*!< External interrupt line 17 Connected to the RTC Alarm event (defined in rtc.h) */
-#define RTC_EXTI_LINE_SSRU_EVENT              EXTI_IMR1_IM18 /*!< External interrupt line 18 Connected to the RTC SSR Underflow event  */
-#define RTC_EXTI_LINE_TIMESTAMP_EVENT         EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC Time Stamp events */
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       EXTI_IMR1_IM20 /*!< External interrupt line 20 Connected to the RTC Wakeup event */
-#define RTC_EXTI_LINE_TAMPER_EVENT            EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC tamper events */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
-  * @{
-  */
-
-/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
-  * @{
-  */
-#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
-                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
-
-
-#define IS_RTC_TIMESTAMP_PIN(PIN)  (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
-
-
-
-#define IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
-                                                       ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
-
-#define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE)    (((MODE) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \
-                                                      ((MODE) == RTC_TAMPERDETECTIONOUTPUT_DISABLE))
-
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
-                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-
-#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= RTC_WUTR_WUT)
-
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
-                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
-                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
-
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
-                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
-
-#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
-
-#define IS_RTC_LOW_POWER_CALIB(LPCAL) (((LPCAL) == RTC_LPCAL_SET) || \
-                                       ((LPCAL) == RTC_LPCAL_RESET))
-
-
-#define IS_RTC_TAMPER(__TAMPER__)                ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \
-                                                  (((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U))
-
-#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__)   ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0x00U) && \
-                                                  (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U))
-
-#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__)       (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE)  || \
-                                                  ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
-                                                  ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL)    || \
-                                                  ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
-
-#define IS_RTC_TAMPER_ERASE_MODE(__MODE__)       (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
-                                                  ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
-
-#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)  (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \
-                                                  ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))
-
-#define IS_RTC_TAMPER_FILTER(__FILTER__)         (((__FILTER__) == RTC_TAMPERFILTER_DISABLE)  || \
-                                                  ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
-                                                  ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
-                                                  ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))
-
-#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__)    (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
-                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
-                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
-                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
-                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
-                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
-                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
-                                                  ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
-
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__)   (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
-                                                          ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
-                                                          ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
-                                                          ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
-
-#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__)    (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
-                                                  ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))
-
-#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
-                                                              ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
-
-#define IS_RTC_BKP(__BKP__)   ((__BKP__) < RTC_BKP_NUMBER)
-
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
-                                 ((SEL) == RTC_SHIFTADD1S_SET))
-
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
-
-#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
-                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
-
-#define IS_RTC_BINARY_MODE(MODE) (((MODE) == RTC_BINARY_NONE) || \
-                                  ((MODE) == RTC_BINARY_ONLY) || \
-                                   ((MODE) == RTC_BINARY_MIX ))
-
-#define IS_RTC_BINARY_MIX_BCDU(BDCU) (((BDCU) == RTC_BINARY_MIX_BCDU_0) || \
-                                      ((BDCU) == RTC_BINARY_MIX_BCDU_1) || \
-                                      ((BDCU) == RTC_BINARY_MIX_BCDU_2) || \
-                                      ((BDCU) == RTC_BINARY_MIX_BCDU_3) || \
-                                      ((BDCU) == RTC_BINARY_MIX_BCDU_4) || \
-                                      ((BDCU) == RTC_BINARY_MIX_BCDU_5) || \
-                                      ((BDCU) == RTC_BINARY_MIX_BCDU_6) || \
-                                      ((BDCU) == RTC_BINARY_MIX_BCDU_7))
-
-#define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK)   (((MASK) == 0u) || \
-                                                    (((MASK) >= RTC_ALARMSUBSECONDBINMASK_SS31_1) && ((MASK) <= RTC_ALARMSUBSECONDBINMASK_NONE)))
-
-#define IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(SEL) (((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_NO) || \
-                                               ((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_YES))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_RTC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smartcard.h

@@ -1,1155 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_smartcard.h
-  * @author  MCD Application Team
-  * @brief   Header file of SMARTCARD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_SMARTCARD_H
-#define STM32WLxx_HAL_SMARTCARD_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SMARTCARD
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
-  * @{
-  */
-
-/**
-  * @brief SMARTCARD Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.
-                                           The baud rate register is computed using the following formula:
-                                              Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate)))
-                                           where usart_ker_ckpres is the USART input clock divided by a prescaler */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits.
-                                           This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
-
-  uint16_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref SMARTCARD_Parity
-                                           @note The parity is enabled by default (PCE is forced to 1).
-                                                 Since the WordLength is forced to 8 bits + parity, M is
-                                                 forced to 1 and the parity bit is the 9th bit. */
-
-  uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref SMARTCARD_Mode */
-
-  uint16_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
-                                           This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
-
-  uint16_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref SMARTCARD_Clock_Phase */
-
-  uint16_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                           This parameter can be a value of @ref SMARTCARD_Last_Bit */
-
-  uint16_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
-                                           Selecting the single sample method increases the receiver tolerance to clock
-                                           deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
-
-  uint8_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler.
-                                           This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied
-                                           by 2 to give the division factor of the source clock frequency */
-
-  uint8_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time applied after stop bits. */
-
-  uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled
-                                           in case of parity error.
-                                           This parameter can be a value of @ref SMARTCARD_NACK_Enable */
-
-  uint32_t TimeOutEnable;             /*!< Specifies whether the receiver timeout is enabled.
-                                            This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
-
-  uint32_t TimeOutValue;              /*!< Specifies the receiver time out value in number of baud blocks:
-                                           it is used to implement the Character Wait Time (CWT) and
-                                           Block Wait Time (BWT). It is coded over 24 bits. */
-
-  uint8_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
-                                           This parameter can be any value from 0x0 to 0xFF */
-
-  uint8_t AutoRetryCount;             /*!< Specifies the SmartCard auto-retry count (number of retries in
-                                            receive and transmit mode). When set to 0, retransmission is
-                                            disabled. Otherwise, its maximum value is 7 (before signalling
-                                            an error) */
-
-  uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the USART clock source.
-                                           This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */
-
-} SMARTCARD_InitTypeDef;
-
-/**
-  * @brief  SMARTCARD advanced features initialization structure definition
-  */
-typedef struct
-{
-  uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several
-                                           advanced features may be initialized at the same time. This parameter
-                                           can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
-
-  uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.
-                                           This parameter can be a value of @ref SMARTCARD_Tx_Inv  */
-
-  uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.
-                                           This parameter can be a value of @ref SMARTCARD_Rx_Inv  */
-
-  uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic
-                                           vs negative/inverted logic).
-                                           This parameter can be a value of @ref SMARTCARD_Data_Inv */
-
-  uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.
-                                           This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
-
-  uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.
-                                           This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
-
-  uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.
-                                           This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
-
-  uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.
-                                           This parameter can be a value of @ref SMARTCARD_MSB_First */
-
-  uint16_t TxCompletionIndication;     /*!< Specifies which transmission completion indication is used: before (when
-                                            relevant flag is available) or once guard time period has elapsed.
-                                           This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */
-} SMARTCARD_AdvFeatureInitTypeDef;
-
-/**
-  * @brief HAL SMARTCARD State definition
-  * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition).
-  *        - gState contains SMARTCARD state information related to global Handle management
-  *          and also information related to Tx operations.
-  *          gState value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : (Not Used)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
-  *          b4-b3  (not used)
-  *             xx : Should be set to 00
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (Peripheral busy with some configuration or internal operations)
-  *          b1     (not used)
-  *             x  : Should be set to 0
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  *        - RxState contains information related to Rx operations.
-  *          RxState value coding follow below described bitmap :
-  *          b7-b6  (not used)
-  *             xx : Should be set to 00
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized)
-  *          b4-b2  (not used)
-  *            xxx : Should be set to 000
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     (not used)
-  *             x  : Should be set to 0.
-  */
-typedef uint32_t HAL_SMARTCARD_StateTypeDef;
-
-/**
-  * @brief  SMARTCARD handle Structure definition
-  */
-typedef struct __SMARTCARD_HandleTypeDef
-{
-  USART_TypeDef                     *Instance;             /*!< USART registers base address                          */
-
-  SMARTCARD_InitTypeDef             Init;                  /*!< SmartCard communication parameters                    */
-
-  SMARTCARD_AdvFeatureInitTypeDef   AdvancedInit;          /*!< SmartCard advanced features initialization parameters */
-
-  uint8_t                           *pTxBuffPtr;           /*!< Pointer to SmartCard Tx transfer Buffer               */
-
-  uint16_t                          TxXferSize;            /*!< SmartCard Tx Transfer size                            */
-
-  __IO uint16_t                     TxXferCount;           /*!< SmartCard Tx Transfer Counter                         */
-
-  uint8_t                           *pRxBuffPtr;           /*!< Pointer to SmartCard Rx transfer Buffer               */
-
-  uint16_t                          RxXferSize;            /*!< SmartCard Rx Transfer size                            */
-
-  __IO uint16_t                     RxXferCount;           /*!< SmartCard Rx Transfer Counter                         */
-
-  uint16_t                          NbRxDataToProcess;     /*!< Number of data to process during RX ISR execution     */
-
-  uint16_t                          NbTxDataToProcess;     /*!< Number of data to process during TX ISR execution     */
-
-  uint32_t                          FifoMode;              /*!< Specifies if the FIFO mode will be used.
-                                                                This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */
-
-  void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Rx IRQ handler                    */
-
-  void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Tx IRQ handler                    */
-
-  DMA_HandleTypeDef                 *hdmatx;               /*!< SmartCard Tx DMA Handle parameters                    */
-
-  DMA_HandleTypeDef                 *hdmarx;               /*!< SmartCard Rx DMA Handle parameters                    */
-
-  HAL_LockTypeDef                   Lock;                  /*!< Locking object                                        */
-
-  __IO HAL_SMARTCARD_StateTypeDef   gState;                /*!< SmartCard state information related to global Handle management
-                                                                and also related to Tx operations.
-                                                                This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-
-  __IO HAL_SMARTCARD_StateTypeDef   RxState;               /*!< SmartCard state information related to Rx operations.
-                                                                This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
-
-  __IO uint32_t                     ErrorCode;             /*!< SmartCard Error code                                  */
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-  void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Tx Complete Callback             */
-
-  void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Rx Complete Callback             */
-
-  void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);             /*!< SMARTCARD Error Callback                   */
-
-  void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Abort Complete Callback          */
-
-  void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */
-
-  void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);  /*!< SMARTCARD Abort Receive Complete Callback  */
-
-  void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);        /*!< SMARTCARD Rx Fifo Full Callback            */
-
-  void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);       /*!< SMARTCARD Tx Fifo Empty Callback           */
-
-  void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);           /*!< SMARTCARD Msp Init callback                */
-
-  void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Msp DeInit callback              */
-#endif  /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-} SMARTCARD_HandleTypeDef;
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL SMARTCARD Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_SMARTCARD_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SMARTCARD Tx Complete Callback ID             */
-  HAL_SMARTCARD_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SMARTCARD Rx Complete Callback ID             */
-  HAL_SMARTCARD_ERROR_CB_ID                   = 0x02U,    /*!< SMARTCARD Error Callback ID                   */
-  HAL_SMARTCARD_ABORT_COMPLETE_CB_ID          = 0x03U,    /*!< SMARTCARD Abort Complete Callback ID          */
-  HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U,    /*!< SMARTCARD Abort Transmit Complete Callback ID */
-  HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x05U,    /*!< SMARTCARD Abort Receive Complete Callback ID  */
-  HAL_SMARTCARD_RX_FIFO_FULL_CB_ID            = 0x06U,    /*!< SMARTCARD Rx Fifo Full Callback ID            */
-  HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID           = 0x07U,    /*!< SMARTCARD Tx Fifo Empty Callback ID           */
-
-  HAL_SMARTCARD_MSPINIT_CB_ID                 = 0x08U,    /*!< SMARTCARD MspInit callback ID                 */
-  HAL_SMARTCARD_MSPDEINIT_CB_ID               = 0x09U     /*!< SMARTCARD MspDeInit callback ID               */
-
-} HAL_SMARTCARD_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL SMARTCARD Callback pointer definition
-  */
-typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard);  /*!< pointer to an SMARTCARD callback function */
-
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-/**
-  * @brief  SMARTCARD clock sources
-  */
-typedef enum
-{
-  SMARTCARD_CLOCKSOURCE_PCLK1     = 0x00U, /*!< PCLK1 clock source         */
-  SMARTCARD_CLOCKSOURCE_PCLK2     = 0x01U, /*!< PCLK2 clock source         */
-  SMARTCARD_CLOCKSOURCE_HSI       = 0x02U, /*!< HSI clock source           */
-  SMARTCARD_CLOCKSOURCE_SYSCLK    = 0x04U, /*!< SYSCLK clock source        */
-  SMARTCARD_CLOCKSOURCE_LSE       = 0x08U, /*!< LSE clock source           */
-  SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U  /*!< undefined clock source     */
-} SMARTCARD_ClockSourceTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported Constants
-  * @{
-  */
-
-/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
-  * @{
-  */
-#define HAL_SMARTCARD_STATE_RESET            0x00000000U                     /*!< Peripheral is not initialized
-                                                                                  Value is allowed for gState and RxState */
-#define HAL_SMARTCARD_STATE_READY            0x00000020U                     /*!< Peripheral Initialized and ready for use
-                                                                                  Value is allowed for gState and RxState */
-#define HAL_SMARTCARD_STATE_BUSY             0x00000024U                     /*!< an internal process is ongoing
-                                                                                  Value is allowed for gState only */
-#define HAL_SMARTCARD_STATE_BUSY_TX          0x00000021U                     /*!< Data Transmission process is ongoing
-                                                                                  Value is allowed for gState only */
-#define HAL_SMARTCARD_STATE_BUSY_RX          0x00000022U                     /*!< Data Reception process is ongoing
-                                                                                  Value is allowed for RxState only */
-#define HAL_SMARTCARD_STATE_BUSY_TX_RX       0x00000023U                     /*!< Data Transmission and Reception process is ongoing
-                                                                                  Not to be used for neither gState nor RxState.
-                                                                                  Value is result of combination (Or) between gState and RxState values */
-#define HAL_SMARTCARD_STATE_TIMEOUT          0x000000A0U                     /*!< Timeout state
-                                                                                  Value is allowed for gState only */
-#define HAL_SMARTCARD_STATE_ERROR            0x000000E0U                     /*!< Error
-                                                                                  Value is allowed for gState only */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
-  * @{
-  */
-#define HAL_SMARTCARD_ERROR_NONE             ((uint32_t)0x00000000U)         /*!< No error                */
-#define HAL_SMARTCARD_ERROR_PE               ((uint32_t)0x00000001U)         /*!< Parity error            */
-#define HAL_SMARTCARD_ERROR_NE               ((uint32_t)0x00000002U)         /*!< Noise error             */
-#define HAL_SMARTCARD_ERROR_FE               ((uint32_t)0x00000004U)         /*!< frame error             */
-#define HAL_SMARTCARD_ERROR_ORE              ((uint32_t)0x00000008U)         /*!< Overrun error           */
-#define HAL_SMARTCARD_ERROR_DMA              ((uint32_t)0x00000010U)         /*!< DMA transfer error      */
-#define HAL_SMARTCARD_ERROR_RTO              ((uint32_t)0x00000020U)         /*!< Receiver TimeOut error  */
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)         /*!< Invalid Callback error  */
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
-  * @{
-  */
-#define SMARTCARD_WORDLENGTH_9B             USART_CR1_M0                    /*!< SMARTCARD frame length */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
-  * @{
-  */
-#define SMARTCARD_STOPBITS_0_5              USART_CR2_STOP_0                /*!< SMARTCARD frame with 0.5 stop bit  */
-#define SMARTCARD_STOPBITS_1_5              USART_CR2_STOP                  /*!< SMARTCARD frame with 1.5 stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Parity SMARTCARD Parity
-  * @{
-  */
-#define SMARTCARD_PARITY_EVEN               USART_CR1_PCE                   /*!< SMARTCARD frame even parity */
-#define SMARTCARD_PARITY_ODD                (USART_CR1_PCE | USART_CR1_PS)  /*!< SMARTCARD frame odd parity  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
-  * @{
-  */
-#define SMARTCARD_MODE_RX                   USART_CR1_RE                    /*!< SMARTCARD RX mode        */
-#define SMARTCARD_MODE_TX                   USART_CR1_TE                    /*!< SMARTCARD TX mode        */
-#define SMARTCARD_MODE_TX_RX                (USART_CR1_TE |USART_CR1_RE)    /*!< SMARTCARD RX and TX mode */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
-  * @{
-  */
-#define SMARTCARD_POLARITY_LOW              0x00000000U                     /*!< SMARTCARD frame low polarity  */
-#define SMARTCARD_POLARITY_HIGH             USART_CR2_CPOL                  /*!< SMARTCARD frame high polarity */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
-  * @{
-  */
-#define SMARTCARD_PHASE_1EDGE               0x00000000U                     /*!< SMARTCARD frame phase on first clock transition  */
-#define SMARTCARD_PHASE_2EDGE               USART_CR2_CPHA                  /*!< SMARTCARD frame phase on second clock transition */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
-  * @{
-  */
-#define SMARTCARD_LASTBIT_DISABLE           0x00000000U                     /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
-#define SMARTCARD_LASTBIT_ENABLE            USART_CR2_LBCL                  /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin     */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
-  * @{
-  */
-#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    0x00000000U                     /*!< SMARTCARD frame one-bit sample disabled */
-#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     USART_CR3_ONEBIT                /*!< SMARTCARD frame one-bit sample enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
-  * @{
-  */
-#define SMARTCARD_NACK_DISABLE              0x00000000U                     /*!< SMARTCARD NACK transmission disabled  */
-#define SMARTCARD_NACK_ENABLE               USART_CR3_NACK                  /*!< SMARTCARD NACK transmission enabled */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
-  * @{
-  */
-#define SMARTCARD_TIMEOUT_DISABLE           0x00000000U                     /*!< SMARTCARD receiver timeout disabled */
-#define SMARTCARD_TIMEOUT_ENABLE            USART_CR2_RTOEN                 /*!< SMARTCARD receiver timeout enabled  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_ClockPrescaler  SMARTCARD Clock Prescaler
-  * @{
-  */
-#define SMARTCARD_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
-#define SMARTCARD_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
-#define SMARTCARD_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
-#define SMARTCARD_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
-#define SMARTCARD_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
-#define SMARTCARD_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
-#define SMARTCARD_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
-#define SMARTCARD_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
-#define SMARTCARD_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
-#define SMARTCARD_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
-#define SMARTCARD_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
-#define SMARTCARD_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_TXINV_DISABLE  0x00000000U                  /*!< TX pin active level inversion disable */
-#define SMARTCARD_ADVFEATURE_TXINV_ENABLE   USART_CR2_TXINV              /*!< TX pin active level inversion enable  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_RXINV_DISABLE  0x00000000U                  /*!< RX pin active level inversion disable */
-#define SMARTCARD_ADVFEATURE_RXINV_ENABLE   USART_CR2_RXINV              /*!< RX pin active level inversion enable  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE  0x00000000U                /*!< Binary data inversion disable */
-#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE   USART_CR2_DATAINV          /*!< Binary data inversion enable  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_SWAP_DISABLE   0x00000000U                  /*!< TX/RX pins swap disable */
-#define SMARTCARD_ADVFEATURE_SWAP_ENABLE    USART_CR2_SWAP               /*!< TX/RX pins swap enable  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   0x00000000U                /*!< RX overrun enable  */
-#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  USART_CR3_OVRDIS           /*!< RX overrun disable */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR   0x00000000U           /*!< DMA enable on Reception Error  */
-#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR  USART_CR3_DDRE        /*!< DMA disable on Reception Error */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_MSB_First   SMARTCARD advanced feature MSB first
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      0x00000000U           /*!< Most significant bit sent/received first disable */
-#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       USART_CR2_MSBFIRST    /*!< Most significant bit sent/received first enable  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
-  * @{
-  */
-#define SMARTCARD_RXDATA_FLUSH_REQUEST      USART_RQR_RXFRQ              /*!< Receive data flush request */
-#define SMARTCARD_TXDATA_FLUSH_REQUEST      USART_RQR_TXFRQ              /*!< Transmit data flush request */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
-  * @{
-  */
-#define SMARTCARD_IT_MASK                   0x001FU   /*!< SMARTCARD interruptions flags mask  */
-#define SMARTCARD_CR_MASK                   0x00E0U   /*!< SMARTCARD control register mask     */
-#define SMARTCARD_CR_POS                    5U        /*!< SMARTCARD control register position */
-#define SMARTCARD_ISR_MASK                  0x1F00U   /*!< SMARTCARD ISR register mask         */
-#define SMARTCARD_ISR_POS                   8U        /*!< SMARTCARD ISR register position     */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros
-  * @{
-  */
-
-/** @brief  Reset SMARTCARD handle states.
-  * @param  __HANDLE__ SMARTCARD handle.
-  * @retval None
-  */
-#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
-                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
-                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
-                                                            (__HANDLE__)->MspInitCallback = NULL;                 \
-                                                            (__HANDLE__)->MspDeInitCallback = NULL;               \
-                                                          } while(0U)
-#else
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
-                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
-                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
-                                                          } while(0U)
-#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS  */
-
-/** @brief  Flush the Smartcard Data registers.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                      \
-  do{                                                                     \
-    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
-    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
-  } while(0U)
-
-/** @brief  Clear the specified SMARTCARD pending flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
-  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
-  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
-  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
-  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag
-  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
-  *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
-  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
-  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
-  *            @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief  Clear the SMARTCARD PE pending flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
-
-/** @brief  Clear the SMARTCARD FE pending flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
-
-/** @brief  Clear the SMARTCARD NE pending flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
-
-/** @brief  Clear the SMARTCARD ORE pending flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
-
-/** @brief  Clear the SMARTCARD IDLE pending flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
-
-/** @brief  Check whether the specified Smartcard flag is set or not.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
-  *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
-  *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
-  *            @arg @ref SMARTCARD_FLAG_BUSY  Busy flag
-  *            @arg @ref SMARTCARD_FLAG_EOBF  End of block flag
-  *            @arg @ref SMARTCARD_FLAG_RTOF  Receiver timeout flag
-  *            @arg @ref SMARTCARD_FLAG_TXE   Transmit data register empty flag
-  *            @arg @ref SMARTCARD_FLAG_TC    Transmission complete flag
-  *            @arg @ref SMARTCARD_FLAG_RXNE  Receive data register not empty flag
-  *            @arg @ref SMARTCARD_FLAG_IDLE  Idle line detection flag
-  *            @arg @ref SMARTCARD_FLAG_ORE   Overrun error flag
-  *            @arg @ref SMARTCARD_FLAG_NE    Noise error flag
-  *            @arg @ref SMARTCARD_FLAG_FE    Framing error flag
-  *            @arg @ref SMARTCARD_FLAG_PE    Parity error flag
-  *            @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag
-  *            @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag
-  *            @arg @ref SMARTCARD_FLAG_TXFE  TXFIFO Empty flag
-  *            @arg @ref SMARTCARD_FLAG_RXFF  RXFIFO Full flag
-  *            @arg @ref SMARTCARD_FLAG_RXFT  SMARTCARD RXFIFO threshold flag
-  *            @arg @ref SMARTCARD_FLAG_TXFT  SMARTCARD TXFIFO threshold flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Enable the specified SmartCard interrupt.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
-  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
-  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
-  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
-  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)
-  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
-  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
-  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
-  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
-  *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
-  *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
-  *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
-  *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
-  *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
-  *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
-  * @retval None
-  */
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
-                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
-                                                                ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
-
-/** @brief  Disable the specified SmartCard interrupt.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
-  *          This parameter can be one of the following values:
-  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
-  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
-  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
-  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
-  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)
-  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
-  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
-  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
-  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
-  *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
-  *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
-  *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
-  *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
-  *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
-  *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
-  * @retval None
-  */
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
-                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
-                                                                ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
-
-/** @brief  Check whether the specified SmartCard interrupt has occurred or not.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
-  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
-  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
-  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
-  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)
-  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
-  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
-  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
-  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
-  *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
-  *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
-  *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
-  *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
-  *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
-  *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
-                                                             & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
-
-/** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt
-  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt
-  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt
-  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt
-  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)
-  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt
-  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt
-  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt
-  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)
-  *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption
-  *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption
-  *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption
-  *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption
-  *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption
-  *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
-  * @retval The new state of __INTERRUPT__ (SET or RESET).
-  */
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
-                                                                     (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
-                                                                      (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK)))  != 0U) ? SET : RESET)
-
-/** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
-  *                       to clear the corresponding interrupt.
-  *          This parameter can be one of the following values:
-  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
-  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
-  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
-  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
-  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detection clear flag
-  *            @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag
-  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
-  *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
-  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
-  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
-
-/** @brief  Set a specific SMARTCARD request flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __REQ__ specifies the request flag to set
-  *          This parameter can be one of the following values:
-  *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
-  *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
-  * @retval None
-  */
-#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
-
-/** @brief  Enable the SMARTCARD one bit sample method.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief  Disable the SMARTCARD one bit sample method.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
-                                                            &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
-
-/** @brief  Enable the USART associated to the SMARTCARD Handle.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
-
-/** @brief  Disable the USART associated to the SMARTCARD Handle
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
-
-/**
-  * @}
-  */
-
-/* Private macros -------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
-  * @{
-  */
-
-/** @brief  Report the SMARTCARD clock source.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @param  __CLOCKSOURCE__ output variable.
-  * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
-  */
-#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
-  do {                                                         \
-    if((__HANDLE__)->Instance == USART1)                       \
-    {                                                          \
-      switch(__HAL_RCC_GET_USART1_SOURCE())                    \
-      {                                                        \
-        case RCC_USART1CLKSOURCE_PCLK2:                        \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;     \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
-          break;                                               \
-        case RCC_USART1CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
-          break;                                               \
-        default:                                               \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
-          break;                                               \
-      }                                                        \
-    }                                                          \
-    else if((__HANDLE__)->Instance == USART2)                  \
-    {                                                          \
-      switch(__HAL_RCC_GET_USART2_SOURCE())                    \
-      {                                                        \
-        case RCC_USART2CLKSOURCE_PCLK1:                        \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;     \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_HSI:                          \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_SYSCLK:                       \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK;    \
-          break;                                               \
-        case RCC_USART2CLKSOURCE_LSE:                          \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
-          break;                                               \
-        default:                                               \
-          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
-          break;                                               \
-      }                                                        \
-    }                                                          \
-    else                                                       \
-    {                                                          \
-      (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
-    }                                                          \
-  } while(0U)
-
-/** @brief  Check the Baud rate range.
-  * @note   The maximum Baud Rate is derived from the maximum clock on WB (48 MHz)
-  *         divided by the oversampling used on the SMARTCARD (i.e. 16).
-  * @param  __BAUDRATE__ Baud rate set by the configuration function.
-  * @retval Test result (TRUE or FALSE)
-  */
-#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 3000001U)
-
-/** @brief  Check the block length range.
-  * @note   The maximum SMARTCARD block length is 0xFF.
-  * @param  __LENGTH__ block length.
-  * @retval Test result (TRUE or FALSE)
-  */
-#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
-
-/** @brief  Check the receiver timeout value.
-  * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
-  * @param  __TIMEOUTVALUE__ receiver timeout value.
-  * @retval Test result (TRUE or FALSE)
-  */
-#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
-
-/** @brief  Check the SMARTCARD autoretry counter value.
-  * @note   The maximum number of retransmissions is 0x7.
-  * @param  __COUNT__ number of retransmissions.
-  * @retval Test result (TRUE or FALSE)
-  */
-#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7U)
-
-/** @brief Ensure that SMARTCARD frame length is valid.
-  * @param __LENGTH__ SMARTCARD frame length.
-  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
-  */
-#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
-
-/** @brief Ensure that SMARTCARD frame number of stop bits is valid.
-  * @param __STOPBITS__ SMARTCARD frame number of stop bits.
-  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
-  */
-#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
-                                             ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
-
-/** @brief Ensure that SMARTCARD frame parity is valid.
-  * @param __PARITY__ SMARTCARD frame parity.
-  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
-  */
-#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
-                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))
-
-/** @brief Ensure that SMARTCARD communication mode is valid.
-  * @param __MODE__ SMARTCARD communication mode.
-  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
-  */
-#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
-
-/** @brief Ensure that SMARTCARD frame polarity is valid.
-  * @param __CPOL__ SMARTCARD frame polarity.
-  * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
-  */
-#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
-                                         || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
-
-/** @brief Ensure that SMARTCARD frame phase is valid.
-  * @param __CPHA__ SMARTCARD frame phase.
-  * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
-  */
-#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
-
-/** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
-  * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
-  * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
-  */
-#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
-                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
-
-/** @brief Ensure that SMARTCARD frame sampling is valid.
-  * @param __ONEBIT__ SMARTCARD frame sampling.
-  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
-  */
-#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
-                                                 ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
-
-/** @brief Ensure that SMARTCARD NACK transmission setting is valid.
-  * @param __NACK__ SMARTCARD NACK transmission setting.
-  * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
-  */
-#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
-                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))
-
-/** @brief Ensure that SMARTCARD receiver timeout setting is valid.
-  * @param __TIMEOUT__ SMARTCARD receiver timeout setting.
-  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
-  */
-#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
-                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
-
-/** @brief Ensure that SMARTCARD clock Prescaler is valid.
-  * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
-  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
-  */
-#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1)   || \
-                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2)   || \
-                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4)   || \
-                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6)   || \
-                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8)   || \
-                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10)  || \
-                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12)  || \
-                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16)  || \
-                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32)  || \
-                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64)  || \
-                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
-                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))
-
-/** @brief Ensure that SMARTCARD advanced features initialization is valid.
-  * @param __INIT__ SMARTCARD advanced features initialization.
-  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
-  */
-#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
-                                                               SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
-                                                               SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
-                                                               SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
-                                                               SMARTCARD_ADVFEATURE_SWAP_INIT              | \
-                                                               SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
-                                                               SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
-                                                               SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
-
-/** @brief Ensure that SMARTCARD frame TX inversion setting is valid.
-  * @param __TXINV__ SMARTCARD frame TX inversion setting.
-  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
-  */
-#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
-                                                  ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
-
-/** @brief Ensure that SMARTCARD frame RX inversion setting is valid.
-  * @param __RXINV__ SMARTCARD frame RX inversion setting.
-  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
-  */
-#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
-                                                  ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
-
-/** @brief Ensure that SMARTCARD frame data inversion setting is valid.
-  * @param __DATAINV__ SMARTCARD frame data inversion setting.
-  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
-  */
-#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
-                                                      ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
-
-/** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
-  * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
-  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
-  */
-#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
-                                                ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
-
-/** @brief Ensure that SMARTCARD frame overrun setting is valid.
-  * @param __OVERRUN__ SMARTCARD frame overrun setting.
-  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
-  */
-#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
-                                           ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
-
-/** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
-  * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
-  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
-  */
-#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
-                                                       ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
-
-/** @brief Ensure that SMARTCARD frame MSB first setting is valid.
-  * @param __MSBFIRST__ SMARTCARD frame MSB first setting.
-  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
-  */
-#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
-                                                        ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
-
-/** @brief Ensure that SMARTCARD request parameter is valid.
-  * @param __PARAM__ SMARTCARD request parameter.
-  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
-  */
-#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
-                                                   ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
-
-/**
-  * @}
-  */
-
-/* Include SMARTCARD HAL Extended module */
-#include "stm32wlxx_hal_smartcard_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMARTCARD_Exported_Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-/** @addtogroup SMARTCARD_Exported_Functions_Group1
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
-
-#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
-                                                 HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
-                                                   HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* IO operation functions *****************************************************/
-/** @addtogroup SMARTCARD_Exported_Functions_Group2
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
-                                         uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
-                                        uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
-  * @}
-  */
-
-/* Peripheral State and Error functions ***************************************/
-/** @addtogroup SMARTCARD_Exported_Functions_Group4
-  * @{
-  */
-
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
-uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_SMARTCARD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smartcard_ex.h

@@ -1,338 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_smartcard_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of SMARTCARD HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_SMARTCARD_EX_H
-#define STM32WLxx_HAL_SMARTCARD_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SMARTCARDEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @addtogroup SMARTCARDEx_Exported_Constants  SMARTCARD Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
-  * @{
-  */
-#define SMARTCARD_TCBGT      SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
-#define SMARTCARD_TC         SMARTCARD_IT_TC    /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
-  * @{
-  */
-#define SMARTCARD_ADVFEATURE_NO_INIT                 0x00000000U    /*!< No advanced feature initialization                  */
-#define SMARTCARD_ADVFEATURE_TXINVERT_INIT           0x00000001U    /*!< TX pin active level inversion                       */
-#define SMARTCARD_ADVFEATURE_RXINVERT_INIT           0x00000002U    /*!< RX pin active level inversion                       */
-#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         0x00000004U    /*!< Binary data inversion                               */
-#define SMARTCARD_ADVFEATURE_SWAP_INIT               0x00000008U    /*!< TX/RX pins swap                                     */
-#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U    /*!< RX overrun disable                                  */
-#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U    /*!< DMA disable on Reception Error                      */
-#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           0x00000080U    /*!< Most significant bit sent/received first            */
-#define SMARTCARD_ADVFEATURE_TXCOMPLETION            0x00000100U    /*!< TX completion indication before of after guard time */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode
-  * @brief    SMARTCARD FIFO mode
-  * @{
-  */
-#define SMARTCARD_FIFOMODE_DISABLE        0x00000000U                   /*!< FIFO mode disable */
-#define SMARTCARD_FIFOMODE_ENABLE         USART_CR1_FIFOEN              /*!< FIFO mode enable  */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
-  * @brief    SMARTCARD TXFIFO level
-  * @{
-  */
-#define SMARTCARD_TXFIFO_THRESHOLD_1_8    0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */
-#define SMARTCARD_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                        /*!< TXFIFO reaches 1/4 of its depth */
-#define SMARTCARD_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                        /*!< TXFIFO reaches 1/2 of its depth */
-#define SMARTCARD_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)  /*!< TXFIFO reaches 3/4 of its depth */
-#define SMARTCARD_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                        /*!< TXFIFO reaches 7/8 of its depth */
-#define SMARTCARD_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)  /*!< TXFIFO becomes empty            */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
-  * @brief    SMARTCARD RXFIFO level
-  * @{
-  */
-#define SMARTCARD_RXFIFO_THRESHOLD_1_8   0x00000000U                                /*!< RXFIFO FIFO reaches 1/8 of its depth */
-#define SMARTCARD_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                        /*!< RXFIFO FIFO reaches 1/4 of its depth */
-#define SMARTCARD_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                        /*!< RXFIFO FIFO reaches 1/2 of its depth */
-#define SMARTCARD_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)  /*!< RXFIFO FIFO reaches 3/4 of its depth */
-#define SMARTCARD_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                        /*!< RXFIFO FIFO reaches 7/8 of its depth */
-#define SMARTCARD_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)  /*!< RXFIFO FIFO becomes full             */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the ISR register
-  * @{
-  */
-#define SMARTCARD_FLAG_TCBGT          USART_ISR_TCBGT         /*!< SMARTCARD transmission complete before guard time completion */
-#define SMARTCARD_FLAG_REACK          USART_ISR_REACK         /*!< SMARTCARD receive enable acknowledge flag  */
-#define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK         /*!< SMARTCARD transmit enable acknowledge flag */
-#define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY          /*!< SMARTCARD busy flag                        */
-#define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF          /*!< SMARTCARD end of block flag                */
-#define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF          /*!< SMARTCARD receiver timeout flag            */
-#define SMARTCARD_FLAG_TXE            USART_ISR_TXE_TXFNF     /*!< SMARTCARD transmit data register empty     */
-#define SMARTCARD_FLAG_TXFNF          USART_ISR_TXE_TXFNF     /*!< SMARTCARD TXFIFO not full                  */
-#define SMARTCARD_FLAG_TC             USART_ISR_TC            /*!< SMARTCARD transmission complete            */
-#define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE_RXFNE    /*!< SMARTCARD read data register not empty     */
-#define SMARTCARD_FLAG_RXFNE          USART_ISR_RXNE_RXFNE    /*!< SMARTCARD RXFIFO not empty                 */
-#define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE          /*!< SMARTCARD idle line detection              */
-#define SMARTCARD_FLAG_ORE            USART_ISR_ORE           /*!< SMARTCARD overrun error                    */
-#define SMARTCARD_FLAG_NE             USART_ISR_NE            /*!< SMARTCARD noise error                      */
-#define SMARTCARD_FLAG_FE             USART_ISR_FE            /*!< SMARTCARD frame error                      */
-#define SMARTCARD_FLAG_PE             USART_ISR_PE            /*!< SMARTCARD parity error                     */
-#define SMARTCARD_FLAG_TXFE           USART_ISR_TXFE          /*!< SMARTCARD TXFIFO Empty flag                */
-#define SMARTCARD_FLAG_RXFF           USART_ISR_RXFF          /*!< SMARTCARD RXFIFO Full flag                 */
-#define SMARTCARD_FLAG_RXFT           USART_ISR_RXFT          /*!< SMARTCARD RXFIFO threshold flag            */
-#define SMARTCARD_FLAG_TXFT           USART_ISR_TXFT          /*!< SMARTCARD TXFIFO threshold flag            */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
-  *        Elements values convention: 000ZZZZZ0XXYYYYYb
-  *           - YYYYY  : Interrupt source position in the XX register (5 bits)
-  *           - XX  : Interrupt source register (2 bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  *           - ZZZZZ  : Flag position in the ISR register(5 bits)
-  * @{
-  */
-#define SMARTCARD_IT_PE                     0x0028U           /*!< SMARTCARD parity error interruption                 */
-#define SMARTCARD_IT_TXE                    0x0727U           /*!< SMARTCARD transmit data register empty interruption */
-#define SMARTCARD_IT_TXFNF                  0x0727U           /*!< SMARTCARD TX FIFO not full interruption             */
-#define SMARTCARD_IT_TC                     0x0626U           /*!< SMARTCARD transmission complete interruption        */
-#define SMARTCARD_IT_RXNE                   0x0525U           /*!< SMARTCARD read data register not empty interruption */
-#define SMARTCARD_IT_RXFNE                  0x0525U           /*!< SMARTCARD RXFIFO not empty interruption             */
-#define SMARTCARD_IT_IDLE                   0x0424U           /*!< SMARTCARD idle line detection interruption          */
-
-#define SMARTCARD_IT_ERR                    0x0060U           /*!< SMARTCARD error interruption         */
-#define SMARTCARD_IT_ORE                    0x0300U           /*!< SMARTCARD overrun error interruption */
-#define SMARTCARD_IT_NE                     0x0200U           /*!< SMARTCARD noise error interruption   */
-#define SMARTCARD_IT_FE                     0x0100U           /*!< SMARTCARD frame error interruption   */
-
-#define SMARTCARD_IT_EOB                    0x0C3BU           /*!< SMARTCARD end of block interruption     */
-#define SMARTCARD_IT_RTO                    0x0B3AU           /*!< SMARTCARD receiver timeout interruption */
-#define SMARTCARD_IT_TCBGT                  0x1978U           /*!< SMARTCARD transmission complete before guard time completion interruption */
-
-#define SMARTCARD_IT_RXFF                    0x183FU          /*!< SMARTCARD RXFIFO full interruption                  */
-#define SMARTCARD_IT_TXFE                    0x173EU          /*!< SMARTCARD TXFIFO empty interruption                 */
-#define SMARTCARD_IT_RXFT                    0x1A7CU          /*!< SMARTCARD RXFIFO threshold reached interruption     */
-#define SMARTCARD_IT_TXFT                    0x1B77U          /*!< SMARTCARD TXFIFO threshold reached interruption     */
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
-  * @{
-  */
-#define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */
-#define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */
-#define SMARTCARD_CLEAR_NEF                 USART_ICR_NECF    /*!< SMARTCARD noise error detected clear flag  */
-#define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */
-#define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */
-#define SMARTCARD_CLEAR_TXFECF              USART_ICR_TXFECF  /*!< TXFIFO empty Clear Flag                    */
-#define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */
-#define SMARTCARD_CLEAR_TCBGTF              USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
-#define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */
-#define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Exported macros -----------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
-  * @{
-  */
-
-/** @brief  Set the Transmission Completion flag
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @note  If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
-  *        AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
-  *        to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
-  * @retval None
-  */
-#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)                                                \
-  do {                                                                                                       \
-    if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
-    {                                                                                                        \
-      (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                      \
-    }                                                                                                        \
-    else                                                                                                     \
-    {                                                                                                        \
-      assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
-    }                                                                                                        \
-  } while(0U)
-
-/** @brief  Return the transmission completion flag.
-  * @param  __HANDLE__ specifies the SMARTCARD Handle.
-  * @note  Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
-  *        When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
-  *        reported.
-  * @retval Transmission completion flag
-  */
-#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__)  \
-  (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) :  (SMARTCARD_FLAG_TCBGT))
-
-
-/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
-  * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
-  * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
-  */
-#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
-                                                              ((__TXCOMPLETE__) == SMARTCARD_TC))
-
-/** @brief Ensure that SMARTCARD FIFO mode is valid.
-  * @param __STATE__ SMARTCARD FIFO mode.
-  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
-  */
-#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
-                                                ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
-
-/** @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
-  * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
-  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
-  */
-#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
-                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
-                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
-                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
-                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
-                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
-
-/** @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
-  * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
-  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
-  */
-#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
-                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
-                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
-                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
-                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
-                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMARTCARDEx_Exported_Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-/* IO operation methods *******************************************************/
-
-/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* Peripheral Control functions ***********************************************/
-void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
-void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
-HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMARTCARDEx_Exported_Functions_Group2
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard);
-
-/**
-  * @}
-  */
-
-/** @addtogroup SMARTCARDEx_Exported_Functions_Group3
-  * @{
-  */
-
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
-HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
-HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_SMARTCARD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smbus.h

@@ -1,789 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_smbus.h
-  * @author  MCD Application Team
-  * @brief   Header file of SMBUS HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_SMBUS_H
-#define STM32WLxx_HAL_SMBUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-#include "stm32wlxx_hal_smbus_ex.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SMBUS
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
-  * @{
-  */
-
-/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
-  * @brief  SMBUS Configuration Structure definition
-  * @{
-  */
-typedef struct
-{
-  uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
-                                        This parameter calculated by referring to SMBUS initialization section
-                                        in Reference manual */
-  uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
-                                        This parameter can be a value of @ref SMBUS_Analog_Filter */
-
-  uint32_t OwnAddress1;            /*!< Specifies the first device own address.
-                                        This parameter can be a 7-bit or 10-bit address. */
-
-  uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
-                                        This parameter can be a value of @ref SMBUS_addressing_mode */
-
-  uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
-                                        This parameter can be a value of @ref SMBUS_dual_addressing_mode */
-
-  uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
-                                        This parameter can be a 7-bit address. */
-
-  uint32_t OwnAddress2Masks;       /*!< Specifies the acknowledge mask address second device own address
-                                        if dual addressing mode is selected
-                                        This parameter can be a value of @ref SMBUS_own_address2_masks. */
-
-  uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
-                                        This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
-
-  uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
-                                        This parameter can be a value of @ref SMBUS_nostretch_mode */
-
-  uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
-                                        This parameter can be a value of @ref SMBUS_packet_error_check_mode */
-
-  uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
-                                        This parameter can be a value of @ref SMBUS_peripheral_mode */
-
-  uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
-                                        (Enable bits and different timeout values)
-                                        This parameter calculated by referring to SMBUS initialization section
-                                        in Reference manual */
-} SMBUS_InitTypeDef;
-/**
-  * @}
-  */
-
-/** @defgroup HAL_state_definition HAL state definition
-  * @brief  HAL State definition
-  * @{
-  */
-#define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
-#define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
-#define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
-#define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */
-#define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
-#define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
-#define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
-#define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */
-#define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */
-#define HAL_SMBUS_STATE_LISTEN          (0x00000008U)  /*!< Address Listen Mode is ongoing                */
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
-  * @brief  SMBUS Error Code definition
-  * @{
-  */
-#define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
-#define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
-#define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */
-#define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
-#define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
-#define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
-#define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
-#define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
-#define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-#define HAL_SMBUS_ERROR_INVALID_CALLBACK  (0x00000100U)  /*!< Invalid Callback error   */
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-#define HAL_SMBUS_ERROR_INVALID_PARAM    (0x00000200U)   /*!< Invalid Parameters error */
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
-  * @brief  SMBUS handle Structure definition
-  * @{
-  */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-typedef struct __SMBUS_HandleTypeDef
-#else
-typedef struct
-#endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-{
-  I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
-
-  SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
-
-  uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
-
-  uint16_t                     XferSize;        /*!< SMBUS transfer size                */
-
-  __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
-
-  __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
-
-  __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
-
-  HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
-
-  __IO uint32_t                State;           /*!< SMBUS communication state          */
-
-  __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
-
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-  void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Master Tx Transfer completed callback */
-  void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Master Rx Transfer completed callback */
-  void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Slave Tx Transfer completed callback  */
-  void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Slave Rx Transfer completed callback  */
-  void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Listen Complete callback              */
-  void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Error callback                        */
-
-  void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
-  /*!< SMBUS Slave Address Match callback */
-
-  void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Msp Init callback                     */
-  void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
-  /*!< SMBUS Msp DeInit callback                   */
-
-#endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-} SMBUS_HandleTypeDef;
-
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL SMBUS Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< SMBUS Master Tx Transfer completed callback ID  */
-  HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< SMBUS Master Rx Transfer completed callback ID  */
-  HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< SMBUS Slave Tx Transfer completed callback ID   */
-  HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< SMBUS Slave Rx Transfer completed callback ID   */
-  HAL_SMBUS_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< SMBUS Listen Complete callback ID               */
-  HAL_SMBUS_ERROR_CB_ID                   = 0x05U,    /*!< SMBUS Error callback ID                         */
-
-  HAL_SMBUS_MSPINIT_CB_ID                 = 0x06U,    /*!< SMBUS Msp Init callback ID                      */
-  HAL_SMBUS_MSPDEINIT_CB_ID               = 0x07U     /*!< SMBUS Msp DeInit callback ID                    */
-
-} HAL_SMBUS_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL SMBUS Callback pointer definition
-  */
-typedef  void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
-/*!< pointer to an SMBUS callback function */
-typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
-                                            uint16_t AddrMatchCode);
-/*!< pointer to an SMBUS Address Match callback function */
-
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
-  * @{
-  */
-
-/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
-  * @{
-  */
-#define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)
-#define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
-  * @{
-  */
-#define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)
-#define SMBUS_ADDRESSINGMODE_10BIT              (0x00000002U)
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
-  * @{
-  */
-
-#define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)
-#define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
-  * @{
-  */
-
-#define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)
-#define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)
-#define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)
-#define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)
-#define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)
-#define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)
-#define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)
-#define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)
-/**
-  * @}
-  */
-
-
-/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
-  * @{
-  */
-#define SMBUS_GENERALCALL_DISABLE               (0x00000000U)
-#define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
-  * @{
-  */
-#define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)
-#define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
-  * @{
-  */
-#define SMBUS_PEC_DISABLE                       (0x00000000U)
-#define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
-  * @{
-  */
-#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN
-#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)
-#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
-  * @{
-  */
-
-#define  SMBUS_SOFTEND_MODE                     (0x00000000U)
-#define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
-#define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
-#define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
-  * @{
-  */
-
-#define  SMBUS_NO_STARTSTOP                     (0x00000000U)
-#define  SMBUS_GENERATE_STOP                    (uint32_t)(0x80000000U | I2C_CR2_STOP)
-#define  SMBUS_GENERATE_START_READ              (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
-#define  SMBUS_GENERATE_START_WRITE             (uint32_t)(0x80000000U | I2C_CR2_START)
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
-  * @{
-  */
-
-/* List of XferOptions in usage of :
- * 1- Restart condition when direction change
- * 2- No Restart condition in other use cases
- */
-#define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
-#define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
-#define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
-#define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
-#define  SMBUS_FIRST_FRAME_WITH_PEC             ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
-#define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
-#define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
-
-/* List of XferOptions in usage of :
- * 1- Restart condition in all use cases (direction change or not)
- */
-#define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
-#define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
-#define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
-#define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
-  * @brief SMBUS Interrupt definition
-  *        Elements values convention: 0xXXXXXXXX
-  *           - XXXXXXXX  : Interrupt control mask
-  * @{
-  */
-#define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
-#define SMBUS_IT_TCI                            I2C_CR1_TCIE
-#define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
-#define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
-#define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
-#define SMBUS_IT_RXI                            I2C_CR1_RXIE
-#define SMBUS_IT_TXI                            I2C_CR1_TXIE
-#define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
-                                                 SMBUS_IT_NACKI | SMBUS_IT_TXI)
-#define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
-                                                 SMBUS_IT_RXI)
-#define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
-#define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
-/**
-  * @}
-  */
-
-/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
-  * @brief Flag definition
-  *        Elements values convention: 0xXXXXYYYY
-  *           - XXXXXXXX  : Flag mask
-  * @{
-  */
-
-#define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
-#define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
-#define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE
-#define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR
-#define  SMBUS_FLAG_AF                          I2C_ISR_NACKF
-#define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF
-#define  SMBUS_FLAG_TC                          I2C_ISR_TC
-#define  SMBUS_FLAG_TCR                         I2C_ISR_TCR
-#define  SMBUS_FLAG_BERR                        I2C_ISR_BERR
-#define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO
-#define  SMBUS_FLAG_OVR                         I2C_ISR_OVR
-#define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR
-#define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT
-#define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT
-#define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY
-#define  SMBUS_FLAG_DIR                         I2C_ISR_DIR
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros ------------------------------------------------------------*/
-/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
-  * @{
-  */
-
-/** @brief  Reset SMBUS handle state.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @retval None
-  */
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)           do{                                               \
-                                                                 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;  \
-                                                                 (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                 (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                               } while(0)
-#else
-#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)         ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-
-/** @brief  Enable the specified SMBUS interrupts.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable.
-  *        This parameter can be one of the following values:
-  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
-  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
-  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
-  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
-  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
-  *
-  * @retval None
-  */
-#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
-
-/** @brief  Disable the specified SMBUS interrupts.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to disable.
-  *        This parameter can be one of the following values:
-  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
-  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
-  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
-  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
-  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
-  *
-  * @retval None
-  */
-#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
-
-/** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
-  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
-  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
-  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
-  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
-  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
-  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
-  *
-  * @retval The new state of __IT__ (SET or RESET).
-  */
-#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
-  ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified SMBUS flag is set or not.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
-  *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status
-  *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty
-  *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
-  *            @arg @ref SMBUS_FLAG_AF      NACK received flag
-  *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
-  *            @arg @ref SMBUS_FLAG_TC      Transfer complete (master mode)
-  *            @arg @ref SMBUS_FLAG_TCR     Transfer complete reload
-  *            @arg @ref SMBUS_FLAG_BERR    Bus error
-  *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
-  *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
-  *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
-  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
-  *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
-  *            @arg @ref SMBUS_FLAG_BUSY    Bus busy
-  *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)
-  *
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define SMBUS_FLAG_MASK  (0x0001FFFFU)
-#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
-  (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
-    ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
-
-/** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
-  *            @arg @ref SMBUS_FLAG_AF      NACK received flag
-  *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
-  *            @arg @ref SMBUS_FLAG_BERR    Bus error
-  *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
-  *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
-  *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
-  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
-  *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
-  *
-  * @retval None
-  */
-#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
-
-/** @brief  Enable the specified SMBUS peripheral.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @retval None
-  */
-#define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief  Disable the specified SMBUS peripheral.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @retval None
-  */
-#define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
-
-/** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
-  * @param  __HANDLE__ specifies the SMBUS Handle.
-  * @retval None
-  */
-#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
-
-/**
-  * @}
-  */
-
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
-  * @{
-  */
-
-#define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
-                                                         ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
-
-#define IS_SMBUS_DIGITAL_FILTER(FILTER)                 ((FILTER) <= 0x0000000FU)
-
-#define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
-                                                         ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
-
-#define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
-                                                         ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
-
-#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK01)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK02)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK03)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK04)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK05)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK06)    || \
-                                                         ((MASK) == SMBUS_OA2_MASK07))
-
-#define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
-                                                         ((CALL) == SMBUS_GENERALCALL_ENABLE))
-
-#define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
-                                                         ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
-
-#define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
-                                                         ((PEC) == SMBUS_PEC_ENABLE))
-
-#define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)   || \
-                                                         ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
-                                                         ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
-
-#define IS_SMBUS_TRANSFER_MODE(MODE)                 (((MODE) == SMBUS_RELOAD_MODE)                          || \
-                                                      ((MODE) == SMBUS_AUTOEND_MODE)                         || \
-                                                      ((MODE) == SMBUS_SOFTEND_MODE)                         || \
-                                                      ((MODE) == SMBUS_SENDPEC_MODE)                         || \
-                                                      ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
-                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
-                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
-                                                      ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
-                                                                  SMBUS_RELOAD_MODE )))
-
-
-#define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
-                                                         ((REQUEST) == SMBUS_GENERATE_START_READ)        || \
-                                                         ((REQUEST) == SMBUS_GENERATE_START_WRITE)       || \
-                                                         ((REQUEST) == SMBUS_NO_STARTSTOP))
-
-
-#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)   (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \
-                                                      ((REQUEST) == SMBUS_FIRST_FRAME)                       || \
-                                                      ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
-                                                      ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
-                                                      ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
-                                                      ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC)              || \
-                                                      ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
-                                                      ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
-
-#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)             || \
-                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)    || \
-                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)           || \
-                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
-
-#define SMBUS_RESET_CR1(__HANDLE__)                    ((__HANDLE__)->Instance->CR1 &= \
-                                                        (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
-                                                                               I2C_CR1_PECEN)))
-#define SMBUS_RESET_CR2(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 &= \
-                                                        (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
-                                                                               I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
-                                                                               I2C_CR2_RD_WRN)))
-
-#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
-                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
-                                                                       (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
-                                                                      (~I2C_CR2_RD_WRN)) : \
-                                                           (uint32_t)((((uint32_t)(__ADDRESS__) & \
-                                                                        (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
-                                                                       (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
-
-#define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
-#define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
-#define SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
-#define SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
-#define SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
-
-#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
-                                                          ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
-#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__)          ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
-
-#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)
-#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
-  * @{
-  */
-
-/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
-HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
-                                             HAL_SMBUS_CallbackIDTypeDef CallbackID,
-                                             pSMBUS_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
-                                               HAL_SMBUS_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
-                                                 pSMBUS_AddrCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
-#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
-  * @{
-  */
-
-/* IO operation functions  *****************************************************/
-/** @addtogroup Blocking_mode_Polling Blocking mode Polling
-  * @{
-  */
-/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
-                                          uint32_t Timeout);
-/**
-  * @}
-  */
-
-/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
-  * @{
-  */
-/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
-                                               uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
-                                              uint8_t *pData, uint16_t Size, uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
-HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
-                                              uint32_t XferOptions);
-HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
-                                             uint32_t XferOptions);
-
-HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
-/**
-  * @}
-  */
-
-/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
-  * @{
-  */
-/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
-void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
-void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
-void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
-
-/**
-  * @}
-  */
-
-/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
-  *  @{
-  */
-
-/* Peripheral State and Errors functions  **************************************************/
-uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
-uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
-  * @{
-  */
-/* Private functions are defined in stm32wlxx_hal_smbus.c file */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32WLxx_HAL_SMBUS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smbus_ex.h

@@ -1,138 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_smbus_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of SMBUS HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_SMBUS_EX_H
-#define STM32WLxx_HAL_SMBUS_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SMBUSEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
-  * @{
-  */
-
-/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
-  * @{
-  */
-#define SMBUS_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */
-#define SMBUS_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */
-#define SMBUS_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */
-#define SMBUS_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */
-#define SMBUS_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */
-#define SMBUS_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */
-#define SMBUS_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
-  * @{
-  */
-
-/** @addtogroup SMBUSEx_Exported_Functions_Group3 SMBUS Extended FastModePlus Functions
-  * @{
-  */
-void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
-void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
-  * @{
-  */
-#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6))  == SMBUS_FASTMODEPLUS_PB6)   || \
-                                           (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7))  == SMBUS_FASTMODEPLUS_PB7)   || \
-                                           (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8))  == SMBUS_FASTMODEPLUS_PB8)   || \
-                                           (((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9))  == SMBUS_FASTMODEPLUS_PB9)   || \
-                                           (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1)  || \
-                                           (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2)  || \
-                                           (((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3))
-/**
-  * @}
-  */
-
-/* Private Functions ---------------------------------------------------------*/
-/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
-  * @{
-  */
-/* Private functions are defined in stm32wlxx_hal_smbus_ex.c file */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_SMBUS_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_spi.h

@@ -1,852 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_spi.h
-  * @author  MCD Application Team
-  * @brief   Header file of SPI HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_SPI_H
-#define STM32WLxx_HAL_SPI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Types SPI Exported Types
-  * @{
-  */
-
-/**
-  * @brief  SPI Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Mode;                /*!< Specifies the SPI operating mode.
-                                     This parameter can be a value of @ref SPI_Mode */
-
-  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
-                                     This parameter can be a value of @ref SPI_Direction */
-
-  uint32_t DataSize;            /*!< Specifies the SPI data size.
-                                     This parameter can be a value of @ref SPI_Data_Size */
-
-  uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
-                                     This parameter can be a value of @ref SPI_Clock_Polarity */
-
-  uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
-                                     This parameter can be a value of @ref SPI_Clock_Phase */
-
-  uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
-                                     hardware (NSS pin) or by software using the SSI bit.
-                                     This parameter can be a value of @ref SPI_Slave_Select_management */
-
-  uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
-                                     used to configure the transmit and receive SCK clock.
-                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
-                                     @note The communication clock is derived from the master
-                                     clock. The slave clock does not need to be set. */
-
-  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
-  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.
-                                     This parameter can be a value of @ref SPI_TI_mode */
-
-  uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
-                                     This parameter can be a value of @ref SPI_CRC_Calculation */
-
-  uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
-                                     This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
-
-  uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
-                                     CRC Length is only used with Data8 and Data16, not other data size
-                                     This parameter can be a value of @ref SPI_CRC_length */
-
-  uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .
-                                     This parameter can be a value of @ref SPI_NSSP_Mode
-                                     This mode is activated by the NSSP bit in the SPIx_CR2 register and
-                                     it takes effect only if the SPI interface is configured as Motorola SPI
-                                     master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
-                                     CPOL setting is ignored).. */
-} SPI_InitTypeDef;
-
-/**
-  * @brief  HAL SPI State structure definition
-  */
-typedef enum
-{
-  HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
-  HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
-  HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
-  HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
-  HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
-  HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
-  HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
-  HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
-} HAL_SPI_StateTypeDef;
-
-/**
-  * @brief  SPI handle Structure definition
-  */
-typedef struct __SPI_HandleTypeDef
-{
-  SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
-
-  SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
-
-  uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
-
-  uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
-
-  __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */
-
-  uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
-
-  uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
-
-  __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */
-
-  uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */
-
-  void (*RxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Rx ISR       */
-
-  void (*TxISR)(struct __SPI_HandleTypeDef *hspi);   /*!< function pointer on Tx ISR       */
-
-  DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
-
-  DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
-
-  HAL_LockTypeDef            Lock;           /*!< Locking object                           */
-
-  __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
-
-  __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-  void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Tx Completed callback          */
-  void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);             /*!< SPI Rx Completed callback          */
-  void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);           /*!< SPI TxRx Completed callback        */
-  void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Tx Half Completed callback     */
-  void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);         /*!< SPI Rx Half Completed callback     */
-  void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI TxRx Half Completed callback   */
-  void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);              /*!< SPI Error callback                 */
-  void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Abort callback                 */
-  void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);            /*!< SPI Msp Init callback              */
-  void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);          /*!< SPI Msp DeInit callback            */
-
-#endif  /* USE_HAL_SPI_REGISTER_CALLBACKS */
-} SPI_HandleTypeDef;
-
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-/**
-  * @brief  HAL SPI Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_SPI_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SPI Tx Completed callback ID         */
-  HAL_SPI_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SPI Rx Completed callback ID         */
-  HAL_SPI_TX_RX_COMPLETE_CB_ID          = 0x02U,    /*!< SPI TxRx Completed callback ID       */
-  HAL_SPI_TX_HALF_COMPLETE_CB_ID        = 0x03U,    /*!< SPI Tx Half Completed callback ID    */
-  HAL_SPI_RX_HALF_COMPLETE_CB_ID        = 0x04U,    /*!< SPI Rx Half Completed callback ID    */
-  HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05U,    /*!< SPI TxRx Half Completed callback ID  */
-  HAL_SPI_ERROR_CB_ID                   = 0x06U,    /*!< SPI Error callback ID                */
-  HAL_SPI_ABORT_CB_ID                   = 0x07U,    /*!< SPI Abort callback ID                */
-  HAL_SPI_MSPINIT_CB_ID                 = 0x08U,    /*!< SPI Msp Init callback ID             */
-  HAL_SPI_MSPDEINIT_CB_ID               = 0x09U     /*!< SPI Msp DeInit callback ID           */
-
-} HAL_SPI_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL SPI Callback pointer definition
-  */
-typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
-
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
-  * @{
-  */
-
-/** @defgroup SPI_Error_Code SPI Error Code
-  * @{
-  */
-#define HAL_SPI_ERROR_NONE              (0x00000000U)   /*!< No error                               */
-#define HAL_SPI_ERROR_MODF              (0x00000001U)   /*!< MODF error                             */
-#define HAL_SPI_ERROR_CRC               (0x00000002U)   /*!< CRC error                              */
-#define HAL_SPI_ERROR_OVR               (0x00000004U)   /*!< OVR error                              */
-#define HAL_SPI_ERROR_FRE               (0x00000008U)   /*!< FRE error                              */
-#define HAL_SPI_ERROR_DMA               (0x00000010U)   /*!< DMA transfer error                     */
-#define HAL_SPI_ERROR_FLAG              (0x00000020U)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
-#define HAL_SPI_ERROR_ABORT             (0x00000040U)   /*!< Error during SPI Abort procedure       */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define HAL_SPI_ERROR_INVALID_CALLBACK  (0x00000080U)   /*!< Invalid Callback error                 */
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Mode SPI Mode
-  * @{
-  */
-#define SPI_MODE_SLAVE                  (0x00000000U)
-#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Direction SPI Direction Mode
-  * @{
-  */
-#define SPI_DIRECTION_2LINES            (0x00000000U)
-#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Data_Size SPI Data Size
-  * @{
-  */
-#define SPI_DATASIZE_4BIT               (0x00000300U)
-#define SPI_DATASIZE_5BIT               (0x00000400U)
-#define SPI_DATASIZE_6BIT               (0x00000500U)
-#define SPI_DATASIZE_7BIT               (0x00000600U)
-#define SPI_DATASIZE_8BIT               (0x00000700U)
-#define SPI_DATASIZE_9BIT               (0x00000800U)
-#define SPI_DATASIZE_10BIT              (0x00000900U)
-#define SPI_DATASIZE_11BIT              (0x00000A00U)
-#define SPI_DATASIZE_12BIT              (0x00000B00U)
-#define SPI_DATASIZE_13BIT              (0x00000C00U)
-#define SPI_DATASIZE_14BIT              (0x00000D00U)
-#define SPI_DATASIZE_15BIT              (0x00000E00U)
-#define SPI_DATASIZE_16BIT              (0x00000F00U)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
-  * @{
-  */
-#define SPI_POLARITY_LOW                (0x00000000U)
-#define SPI_POLARITY_HIGH               SPI_CR1_CPOL
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Phase SPI Clock Phase
-  * @{
-  */
-#define SPI_PHASE_1EDGE                 (0x00000000U)
-#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
-  * @{
-  */
-#define SPI_NSS_SOFT                    SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT              (0x00000000U)
-#define SPI_NSS_HARD_OUTPUT             (SPI_CR2_SSOE << 16U)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
-  * @{
-  */
-#define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
-#define SPI_NSS_PULSE_DISABLE           (0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
-  * @{
-  */
-#define SPI_BAUDRATEPRESCALER_2         (0x00000000U)
-#define SPI_BAUDRATEPRESCALER_4         (SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_8         (SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_16        (SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_32        (SPI_CR1_BR_2)
-#define SPI_BAUDRATEPRESCALER_64        (SPI_CR1_BR_2 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_128       (SPI_CR1_BR_2 | SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_256       (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
-  * @{
-  */
-#define SPI_FIRSTBIT_MSB                (0x00000000U)
-#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
-/**
-  * @}
-  */
-
-/** @defgroup SPI_TI_mode SPI TI Mode
-  * @{
-  */
-#define SPI_TIMODE_DISABLE              (0x00000000U)
-#define SPI_TIMODE_ENABLE               SPI_CR2_FRF
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
-  * @{
-  */
-#define SPI_CRCCALCULATION_DISABLE      (0x00000000U)
-#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_length SPI CRC Length
-  * @{
-  * This parameter can be one of the following values:
-  *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size
-  *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
-  *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
-  */
-#define SPI_CRC_LENGTH_DATASIZE         (0x00000000U)
-#define SPI_CRC_LENGTH_8BIT             (0x00000001U)
-#define SPI_CRC_LENGTH_16BIT            (0x00000002U)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
-  * @{
-  * This parameter can be one of the following values:
-  *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
-  *          RXNE event is generated if the FIFO
-  *          level is greater or equal to 1/4(8-bits).
-  *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
-  *          level is greater or equal to 1/2(16 bits). */
-#define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
-#define SPI_RXFIFO_THRESHOLD_HF         (0x00000000U)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
-  * @{
-  */
-#define SPI_IT_TXE                      SPI_CR2_TXEIE
-#define SPI_IT_RXNE                     SPI_CR2_RXNEIE
-#define SPI_IT_ERR                      SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Flags_definition SPI Flags Definition
-  * @{
-  */
-#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */
-#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */
-#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */
-#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */
-#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */
-#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */
-#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
-#define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level                     */
-#define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level                        */
-#define SPI_FLAG_MASK                   (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
-                                         | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
-/**
-  * @}
-  */
-
-/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
-  * @{
-  */
-#define SPI_FTLVL_EMPTY                 (0x00000000U)
-#define SPI_FTLVL_QUARTER_FULL          (0x00000800U)
-#define SPI_FTLVL_HALF_FULL             (0x00001000U)
-#define SPI_FTLVL_FULL                  (0x00001800U)
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
-  * @{
-  */
-#define SPI_FRLVL_EMPTY                 (0x00000000U)
-#define SPI_FRLVL_QUARTER_FULL          (0x00000200U)
-#define SPI_FRLVL_HALF_FULL             (0x00000400U)
-#define SPI_FRLVL_FULL                  (0x00000600U)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SPI_Exported_Macros SPI Exported Macros
-  * @{
-  */
-
-/** @brief  Reset SPI handle state.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \
-                                                                    (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                                  } while(0)
-#else
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-
-/** @brief  Enable the specified SPI interrupts.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief  Disable the specified SPI interrupts.
-  * @param  __HANDLE__ specifies the SPI handle.
-  *         This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__ specifies the interrupt source to disable.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief  Check whether the specified SPI interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
-                                                              & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
-  *            @arg SPI_FLAG_CRCERR: CRC error flag
-  *            @arg SPI_FLAG_MODF: Mode fault flag
-  *            @arg SPI_FLAG_OVR: Overrun flag
-  *            @arg SPI_FLAG_BSY: Busy flag
-  *            @arg SPI_FLAG_FRE: Frame format error flag
-  *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
-  *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the SPI CRCERR pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
-
-/** @brief  Clear the SPI MODF pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)             \
-  do{                                                    \
-    __IO uint32_t tmpreg_modf = 0x00U;                   \
-    tmpreg_modf = (__HANDLE__)->Instance->SR;            \
-    CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
-    UNUSED(tmpreg_modf);                                 \
-  } while(0U)
-
-/** @brief  Clear the SPI OVR pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
-  do{                                              \
-    __IO uint32_t tmpreg_ovr = 0x00U;              \
-    tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
-    tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
-    UNUSED(tmpreg_ovr);                            \
-  } while(0U)
-
-/** @brief  Clear the SPI FRE pending flag.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
-  do{                                              \
-    __IO uint32_t tmpreg_fre = 0x00U;              \
-    tmpreg_fre = (__HANDLE__)->Instance->SR;       \
-    UNUSED(tmpreg_fre);                            \
-  }while(0U)
-
-/** @brief  Enable the SPI peripheral.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/** @brief  Disable the SPI peripheral.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
-  * @{
-  */
-
-/** @brief  Set the SPI transmit-only mode.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief  Set the SPI receive-only mode.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief  Reset the CRC calculation of the SPI.
-  * @param  __HANDLE__ specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
-                                       SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __SR__  copy of SPI SR register.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
-  *            @arg SPI_FLAG_CRCERR: CRC error flag
-  *            @arg SPI_FLAG_MODF: Mode fault flag
-  *            @arg SPI_FLAG_OVR: Overrun flag
-  *            @arg SPI_FLAG_BSY: Busy flag
-  *            @arg SPI_FLAG_FRE: Frame format error flag
-  *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
-  *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
-  * @retval SET or RESET.
-  */
-#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
-                                          ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI Interrupt is set or not.
-  * @param  __CR2__  copy of SPI CR2 register.
-  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval SET or RESET.
-  */
-#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
-                                                     (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks if SPI Mode parameter is in allowed range.
-  * @param  __MODE__ specifies the SPI Mode.
-  *         This parameter can be a value of @ref SPI_Mode
-  * @retval None
-  */
-#define IS_SPI_MODE(__MODE__)      (((__MODE__) == SPI_MODE_SLAVE)   || \
-                                    ((__MODE__) == SPI_MODE_MASTER))
-
-/** @brief  Checks if SPI Direction Mode parameter is in allowed range.
-  * @param  __MODE__ specifies the SPI Direction Mode.
-  *         This parameter can be a value of @ref SPI_Direction
-  * @retval None
-  */
-#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES)        || \
-                                    ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
-                                    ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief  Checks if SPI Direction Mode parameter is 2 lines.
-  * @param  __MODE__ specifies the SPI Direction Mode.
-  * @retval None
-  */
-#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
-
-/** @brief  Checks if SPI Direction Mode parameter is 1 or 2 lines.
-  * @param  __MODE__ specifies the SPI Direction Mode.
-  * @retval None
-  */
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
-                                                    ((__MODE__) == SPI_DIRECTION_1LINE))
-
-/** @brief  Checks if SPI Data Size parameter is in allowed range.
-  * @param  __DATASIZE__ specifies the SPI Data Size.
-  *         This parameter can be a value of @ref SPI_Data_Size
-  * @retval None
-  */
-#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_9BIT)  || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_8BIT)  || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_7BIT)  || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_6BIT)  || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_5BIT)  || \
-                                       ((__DATASIZE__) == SPI_DATASIZE_4BIT))
-
-/** @brief  Checks if SPI Serial clock steady state parameter is in allowed range.
-  * @param  __CPOL__ specifies the SPI serial clock steady state.
-  *         This parameter can be a value of @ref SPI_Clock_Polarity
-  * @retval None
-  */
-#define IS_SPI_CPOL(__CPOL__)      (((__CPOL__) == SPI_POLARITY_LOW) || \
-                                    ((__CPOL__) == SPI_POLARITY_HIGH))
-
-/** @brief  Checks if SPI Clock Phase parameter is in allowed range.
-  * @param  __CPHA__ specifies the SPI Clock Phase.
-  *         This parameter can be a value of @ref SPI_Clock_Phase
-  * @retval None
-  */
-#define IS_SPI_CPHA(__CPHA__)      (((__CPHA__) == SPI_PHASE_1EDGE) || \
-                                    ((__CPHA__) == SPI_PHASE_2EDGE))
-
-/** @brief  Checks if SPI Slave Select parameter is in allowed range.
-  * @param  __NSS__ specifies the SPI Slave Select management parameter.
-  *         This parameter can be a value of @ref SPI_Slave_Select_management
-  * @retval None
-  */
-#define IS_SPI_NSS(__NSS__)        (((__NSS__) == SPI_NSS_SOFT)       || \
-                                    ((__NSS__) == SPI_NSS_HARD_INPUT) || \
-                                    ((__NSS__) == SPI_NSS_HARD_OUTPUT))
-
-/** @brief  Checks if SPI NSS Pulse parameter is in allowed range.
-  * @param  __NSSP__ specifies the SPI NSS Pulse Mode parameter.
-  *         This parameter can be a value of @ref SPI_NSSP_Mode
-  * @retval None
-  */
-#define IS_SPI_NSSP(__NSSP__)      (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
-                                    ((__NSSP__) == SPI_NSS_PULSE_DISABLE))
-
-/** @brief  Checks if SPI Baudrate prescaler parameter is in allowed range.
-  * @param  __PRESCALER__ specifies the SPI Baudrate prescaler.
-  *         This parameter can be a value of @ref SPI_BaudRate_Prescaler
-  * @retval None
-  */
-#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8)   || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64)  || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
-                                                  ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
-
-/** @brief  Checks if SPI MSB LSB transmission parameter is in allowed range.
-  * @param  __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
-  *         This parameter can be a value of @ref SPI_MSB_LSB_transmission
-  * @retval None
-  */
-#define IS_SPI_FIRST_BIT(__BIT__)  (((__BIT__) == SPI_FIRSTBIT_MSB) || \
-                                    ((__BIT__) == SPI_FIRSTBIT_LSB))
-
-/** @brief  Checks if SPI TI mode parameter is in allowed range.
-  * @param  __MODE__ specifies the SPI TI mode.
-  *         This parameter can be a value of @ref SPI_TI_mode
-  * @retval None
-  */
-#define IS_SPI_TIMODE(__MODE__)    (((__MODE__) == SPI_TIMODE_DISABLE) || \
-                                    ((__MODE__) == SPI_TIMODE_ENABLE))
-
-/** @brief  Checks if SPI CRC calculation enabled state is in allowed range.
-  * @param  __CALCULATION__ specifies the SPI CRC calculation enable state.
-  *         This parameter can be a value of @ref SPI_CRC_Calculation
-  * @retval None
-  */
-#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
-                                                 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
-
-/** @brief  Checks if SPI CRC length is in allowed range.
-  * @param  __LENGTH__ specifies the SPI CRC length.
-  *         This parameter can be a value of @ref SPI_CRC_length
-  * @retval None
-  */
-#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
-                                       ((__LENGTH__) == SPI_CRC_LENGTH_8BIT)     || \
-                                       ((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
-
-/** @brief  Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
-  * @param  __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
-  *         This parameter must be a number between Min_Data = 0 and Max_Data = 65535
-  * @retval None
-  */
-#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U)    && \
-                                               ((__POLYNOMIAL__) <= 0xFFFFU) && \
-                                              (((__POLYNOMIAL__)&0x1U) != 0U))
-
-/** @brief  Checks if DMA handle is valid.
-  * @param  __HANDLE__ specifies a DMA Handle.
-  * @retval None
-  */
-#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
-
-/**
-  * @}
-  */
-
-/* Include SPI HAL Extended module */
-#include "stm32wlxx_hal_spi_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
-HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions  ***************************************************/
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
-                                          uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
-                                             uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
-                                              uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
-
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_spi_ex.h

@@ -1,75 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_spi_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of SPI HAL Extended module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_SPI_EX_H
-#define STM32WLxx_HAL_SPI_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SPIEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPIEx_Exported_Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-/* IO operation functions *****************************************************/
-/** @addtogroup SPIEx_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_SPI_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32WLxx_HAL/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h

@@ -1,414 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32wlxx_hal_subghz.h
-  * @author  MCD Application Team
-  * @brief   Header file of SUBGHZ HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; Copyright (c) 2020 STMicroelectronics.
-  * All rights reserved.</center></h2>
-  *
-  * This software component is licensed by ST under BSD 3-Clause license,
-  * the "License"; You may not use this file except in compliance with the
-  * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32WLxx_HAL_SUBGHZ_H
-#define STM32WLxx_HAL_SUBGHZ_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32wlxx_hal_def.h"
-
-/* Include low level driver */
-#include "stm32wlxx_ll_spi.h"
-
-/** @addtogroup STM32WLxx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SUBGHZ
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SUBGHZ_Exported_Types SUBGHZ Exported Types
-  * @{
-  */
-
-/**
-  * @brief  SPI Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudratePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
-                                     used to configure SUBGHZSPI clock.
-                                     This parameter can be a value of @ref SUBGHZ_SPI_BAUDRATE_Prescaler  */
-} SUBGHZ_InitTypeDef;
-
-/**
-  * @brief  HAL SUBGHZ State structure definition
-  */
-typedef enum
-{
-  HAL_SUBGHZ_STATE_RESET                    = 0x00U,    /*!< Peripheral not Initialized                  */
-  HAL_SUBGHZ_STATE_READY                    = 0x01U,    /*!< Peripheral Initialized and ready for use    */
-  HAL_SUBGHZ_STATE_BUSY                     = 0x02U,    /*!< an internal process is ongoing              */
-} HAL_SUBGHZ_StateTypeDef;
-
-/**
-  * @brief  HAL SUBGHZ CAD Status structure definition
-  */
-typedef enum
-{
-  HAL_SUBGHZ_CAD_CLEAR                      = 0x00U,    /*!< Channel activity cleared                    */
-  HAL_SUBGHZ_CAD_DETECTED                   = 0x01U,    /*!< Channel activity detected                   */
-} HAL_SUBGHZ_CadStatusTypeDef;
-
-/**
-  * @brief  SUBGHZ handle Structure definition
-  */
-#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1)
-typedef struct __SUBGHZ_HandleTypeDef
-#else
-typedef struct
-#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
-{
-  SUBGHZ_InitTypeDef                        Init;       /*!< SUBGHZ communication parameters             */
-
-  uint8_t                                   DeepSleep;  /*!< SUBGHZ deep sleep state                     */
-
-  HAL_LockTypeDef                           Lock;       /*!< Locking object                              */
-
-  __IO HAL_SUBGHZ_StateTypeDef              State;      /*!< SUBGHZ communication state                  */
-
-  __IO uint32_t                             ErrorCode;  /*!< SUBGHZ Error code                           */
-
-#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1)
-  void (* TxCpltCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz);                /*!< SUBGHZ Tx Completed callback          */
-  void (* RxCpltCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz);                /*!< SUBGHZ Rx Completed callback          */
-  void (* PreambleDetectedCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz);      /*!< SUBGHZ Preamble detected callback     */
-  void (* SyncWordValidCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz);         /*!< SUBGHZ Synchro word valid callback    */
-  void (* HeaderValidCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz);           /*!< SUBGHZ Header valid callback          */
-  void (* HeaderErrorCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz);           /*!< SUBGHZ Header error callback          */
-  void (* CRCErrorCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz);              /*!< SUBGHZ CRC Error callback             */
-  void (* CADStatusCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus); /*!< SUBGHZ CAD Status callback            */
-  void (* RxTxTimeoutCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz);           /*!< SUBGHZ Rx Tx Timeout callback         */
-  void (* MspInitCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz);               /*!< SUBGHZ Msp Init callback              */
-  void (* MspDeInitCallback)(struct __SUBGHZ_HandleTypeDef *hsubghz);             /*!< SUBGHZ Msp DeInit callback            */
-#endif  /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
-} SUBGHZ_HandleTypeDef;
-
-#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL SUBGHZ Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_SUBGHZ_TX_COMPLETE_CB_ID              = 0x00U,    /*!< SUBGHZ Tx Completed callback ID             */
-  HAL_SUBGHZ_RX_COMPLETE_CB_ID              = 0x01U,    /*!< SUBGHZ Rx Completed callback ID             */
-  HAL_SUBGHZ_PREAMBLE_DETECTED_CB_ID        = 0x02U,    /*!< SUBGHZ Preamble detected callback ID        */
-  HAL_SUBGHZ_SYNCWORD_VALID_CB_ID           = 0x03U,    /*!< SUBGHZ Synchro word valid callback ID       */
-  HAL_SUBGHZ_HEADER_VALID_CB_ID             = 0x04U,    /*!< SUBGHZ Header valid callback ID             */
-  HAL_SUBGHZ_HEADER_ERROR_CB_ID             = 0x05U,    /*!< SUBGHZ Header error callback ID             */
-  HAL_SUBGHZ_CRC_ERROR_CB_ID                = 0x06U,    /*!< SUBGHZ CRC error callback ID                */
-  HAL_SUBGHZ_RX_TX_TIMEOUT_CB_ID            = 0x07U,    /*!< SUBGHZ Rx Tx timeout callback ID            */
-  HAL_SUBGHZ_MSPINIT_CB_ID                  = 0x08U,    /*!< SUBGHZ Msp Init callback ID                 */
-  HAL_SUBGHZ_MSPDEINIT_CB_ID                = 0x09U     /*!< SUBGHZ Msp DeInit callback ID               */
-
-} HAL_SUBGHZ_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL SUBGHZ Callback pointer definition
-  */
-typedef  void (*pSUBGHZ_CallbackTypeDef)(SUBGHZ_HandleTypeDef *hsubghz); /*!< pointer to an SUBGHZ callback function */
-typedef  void (*pSUBGHZ_CadStatusCallbackTypeDef)(SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus); /*!< pointer to an CAD Status callback function */
-#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
-
-/*
- * @brief  HAL SUBGHZ Radio Set Command enumeration definition
- */
-typedef enum
-{
-  RADIO_SET_SLEEP                           = 0x84U,
-  RADIO_SET_STANDBY                         = 0x80U,
-  RADIO_SET_FS                              = 0xC1U,
-  RADIO_SET_TX                              = 0x83U,
-  RADIO_SET_RX                              = 0x82U,
-  RADIO_SET_RXDUTYCYCLE                     = 0x94U,
-  RADIO_SET_CAD                             = 0xC5U,
-  RADIO_SET_TXCONTINUOUSWAVE                = 0xD1U,
-  RADIO_SET_TXCONTINUOUSPREAMBLE            = 0xD2U,
-  RADIO_SET_PACKETTYPE                      = 0x8AU,
-  RADIO_SET_RFFREQUENCY                     = 0x86U,
-  RADIO_SET_TXPARAMS                        = 0x8EU,
-  RADIO_SET_PACONFIG                        = 0x95U,
-  RADIO_SET_CADPARAMS                       = 0x88U,
-  RADIO_SET_BUFFERBASEADDRESS               = 0x8FU,
-  RADIO_SET_MODULATIONPARAMS                = 0x8BU,
-  RADIO_SET_PACKETPARAMS                    = 0x8CU,
-  RADIO_RESET_STATS                         = 0x00U,
-  RADIO_CFG_DIOIRQ                          = 0x08U,
-  RADIO_CLR_IRQSTATUS                       = 0x02U,
-  RADIO_CALIBRATE                           = 0x89U,
-  RADIO_CALIBRATEIMAGE                      = 0x98U,
-  RADIO_SET_REGULATORMODE                   = 0x96U,
-  RADIO_SET_TCXOMODE                        = 0x97U,
-  RADIO_SET_TXFALLBACKMODE                  = 0x93U,
-  RADIO_SET_RFSWITCHMODE                    = 0x9DU,
-  RADIO_SET_STOPRXTIMERONPREAMBLE           = 0x9FU,
-  RADIO_SET_LORASYMBTIMEOUT                 = 0xA0U,
-  RADIO_CLR_ERROR                           = 0x07U
-} SUBGHZ_RadioSetCmd_t;
-
-
-/**
-  * @brief  HAL SUBGHZ Radio Get Command enumeration definition
-  */
-typedef enum
-{
-  RADIO_GET_STATUS                          = 0xC0U,
-  RADIO_GET_PACKETTYPE                      = 0x11U,
-  RADIO_GET_RXBUFFERSTATUS                  = 0x13U,
-  RADIO_GET_PACKETSTATUS                    = 0x14U,
-  RADIO_GET_RSSIINST                        = 0x15U,
-  RADIO_GET_STATS                           = 0x10U,
-  RADIO_GET_IRQSTATUS                       = 0x12U,
-  RADIO_GET_ERROR                           = 0x17U
-} SUBGHZ_RadioGetCmd_t;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SUBGHZ_Exported_Constants SUBGHZ Exported Constants
-  * @{
-  */
-
-/** @defgroup SUBGHZ_Error_Code SUBGHZ Error Code definition
-  * @brief  SUBGHZ Error Code definition
-  * @{
-  */
-#define HAL_SUBGHZ_ERROR_NONE               (0x00000000U)   /*!< No error                         */
-#define HAL_SUBGHZ_ERROR_TIMEOUT            (0x00000001U)   /*!< Timeout Error                    */
-#define HAL_SUBGHZ_ERROR_RF_BUSY            (0x00000002U)   /*!< RF Busy Error                    */
-#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1)
-#define HAL_SUBGHZ_ERROR_INVALID_CALLBACK   (0x00000080U)   /*!< Invalid Callback error           */
-#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup SUBGHZ_SPI_BAUDRATE_Prescaler SUBGHZ BaudRate Prescaler
-  * @{
-  */
-#define SUBGHZSPI_BAUDRATEPRESCALER_2       (0x00000000U)
-#define SUBGHZSPI_BAUDRATEPRESCALER_4       (SPI_CR1_BR_0)
-#define SUBGHZSPI_BAUDRATEPRESCALER_8       (SPI_CR1_BR_1)
-#define SUBGHZSPI_BAUDRATEPRESCALER_16      (SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#define SUBGHZSPI_BAUDRATEPRESCALER_32      (SPI_CR1_BR_2)
-#define SUBGHZSPI_BAUDRATEPRESCALER_64      (SPI_CR1_BR_2 | SPI_CR1_BR_0)
-#define SUBGHZSPI_BAUDRATEPRESCALER_128     (SPI_CR1_BR_2 | SPI_CR1_BR_1)
-#define SUBGHZSPI_BAUDRATEPRESCALER_256     (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SUBGHZ_Private_Constants SUBGHZ Private Constants
-  * @{
-  */
-
-/**
-  * @brief SUBGHZSPI_Interrupts SUBGHZSPI Interrupts
-  */
-#define SUBGHZ_IT_TX_CPLT                   0x0001U
-#define SUBGHZ_IT_RX_CPLT                   0x0002U
-#define SUBGHZ_IT_PREAMBLE_DETECTED         0x0004U
-#define SUBGHZ_IT_SYNCWORD_VALID            0x0008U
-#define SUBGHZ_IT_HEADER_VALID              0x0010U
-#define SUBGHZ_IT_HEADER_ERROR              0x0020U
-#define SUBGHZ_IT_CRC_ERROR                 0x0040U
-#define SUBGHZ_IT_CAD_DONE                  0x0080U
-#define SUBGHZ_IT_CAD_ACTIVITY_DETECTED     0x0100U
-#define SUBGHZ_IT_RX_TX_TIMEOUT             0x0200U
-
-/**
-  * @brief SUBGHZ Radio Read/Write Command definition
-  */
-#define SUBGHZ_RADIO_WRITE_REGISTER         0x0DU
-#define SUBGHZ_RADIO_READ_REGISTER          0x1DU
-#define SUBGHZ_RADIO_WRITE_BUFFER           0x0EU
-#define SUBGHZ_RADIO_READ_BUFFER            0x1EU
-/**
-  * @}
-  */
-
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup SUBGHZ_Exported_Macros SUBGHZ Exported Macros
-  * @{
-  */
-
-/** @brief  Reset SUBGHZ handle state.
-  * @param  __HANDLE__ specifies the SUBGHZ Handle.
-  * @retval None
-  */
-#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1)
-#define __HAL_SUBGHZ_RESET_HANDLE_STATE(__HANDLE__)             do{                                                  \
-                                                                    (__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET;    \
-                                                                    (__HANDLE__)->MspInitCallback = NULL;            \
-                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \
-                                                                  } while(0U)
-#else
-#define __HAL_SUBGHZ_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SUBGHZ_STATE_RESET)
-#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* Private macros -----------------------------------------------------------*/
-/** @defgroup SUBGHZ_Private_Macros SUBGHZ Private Macros
-  * @{
-  */
-
-/** @brief  Check whether the specified SPI Interrupt is set or not.
-  * @param  __SUBGHZ_IRQ__  copy of SUBGHZ IRQ Register.
-  * @param  __INTERRUPT__ specifies the SUBGHZ interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg SUBGHZ_IT_TX_DONE
-  *            @arg SUBGHZ_IT_RX_DONE
-  *            @arg SUBGHZ_IT_PREAMBLE_DETECTED
-  *            @arg SUBGHZ_IT_SYNCWORD_VALID
-  *            @arg SUBGHZ_IT_HEADER_VALID
-  *            @arg SUBGHZ_IT_HEADER_ERROR
-  *            @arg SUBGHZ_IT_CRC_ERROR
-  *            @arg SUBGHZ_IT_CAD_DONE
-  *            @arg SUBGHZ_IT_CAD_ACTIVITY_DETECTED
-  *            @arg SUBGHZ_IT_RX_TX_TIMEOUT
-  * @retval SET or RESET.
-  */
-#define SUBGHZ_CHECK_IT_SOURCE(__SUBGHZ_IRQ__, __INTERRUPT__)       \
-  ((((__SUBGHZ_IRQ__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks if SUBGHZSPI Baudrate prescaler parameter is in allowed range.
-  * @param  __PRESCALER__ specifies the SUBGHZSPI Baudrate prescaler.
-  *         This parameter can be a value of @ref SUBGHZ_SPI_BAUDRATE_Prescaler
-  * @retval None
-  */
-#define IS_SUBGHZSPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_2)    || \
-                                                        ((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_4)    || \
-                                                        ((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_8)    || \
-                                                        ((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_16)   || \
-                                                        ((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_32)   || \
-                                                        ((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_64)   || \
-                                                        ((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_128)  || \
-                                                        ((__PRESCALER__) == SUBGHZSPI_BAUDRATEPRESCALER_256))
-/**
-  * @}
-  */
-
-/* Exported functions ------------------------------------------------------- */
-/** @addtogroup SUBGHZ_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SUBGHZ_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz);
-HAL_StatusTypeDef HAL_SUBGHZ_DeInit(SUBGHZ_HandleTypeDef *hsubghz);
-void              HAL_SUBGHZ_MspInit(SUBGHZ_HandleTypeDef *hsubghz);
-void              HAL_SUBGHZ_MspDeInit(SUBGHZ_HandleTypeDef *hsubghz);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_SUBGHZ_RegisterCallback(SUBGHZ_HandleTypeDef *hsubghz,
-                                              HAL_SUBGHZ_CallbackIDTypeDef CallbackID,
-                                              pSUBGHZ_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SUBGHZ_UnRegisterCallback(SUBGHZ_HandleTypeDef *hsubghz,
-                                                HAL_SUBGHZ_CallbackIDTypeDef CallbackID);
-HAL_StatusTypeDef HAL_SUBGHZ_RegisterCadStatusCallback(SUBGHZ_HandleTypeDef *hsubghz,
-                                                       pSUBGHZ_CadStatusCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SUBGHZ_UnRegisterCadStatusCallback(SUBGHZ_HandleTypeDef *hsubghz);
-#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @addtogroup SUBGHZ_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions  ***************************************************/
-HAL_StatusTypeDef HAL_SUBGHZ_ExecSetCmd(SUBGHZ_HandleTypeDef *hsubghz, SUBGHZ_RadioSetCmd_t Command, uint8_t *pBuffer,
-                                        uint16_t Size);
-HAL_StatusTypeDef HAL_SUBGHZ_ExecGetCmd(SUBGHZ_HandleTypeDef *hsubghz, SUBGHZ_RadioGetCmd_t Command, uint8_t *pBuffer,
-                                        uint16_t Size);
-HAL_StatusTypeDef HAL_SUBGHZ_WriteBuffer(SUBGHZ_HandleTypeDef *hsubghz, uint8_t Offset, uint8_t *pBuffer,
-                                         uint16_t Size);
-HAL_StatusTypeDef HAL_SUBGHZ_ReadBuffer(SUBGHZ_HandleTypeDef *hsubghz, uint8_t Offset, uint8_t *pBuffer,
-                                        uint16_t Size);
-HAL_StatusTypeDef HAL_SUBGHZ_WriteRegisters(SUBGHZ_HandleTypeDef *hsubghz, uint16_t Address, uint8_t *pBuffer,
-                                            uint16_t Size);
-HAL_StatusTypeDef HAL_SUBGHZ_ReadRegisters(SUBGHZ_HandleTypeDef *hsubghz, uint16_t Address, uint8_t *pBuffer,
-                                           uint16_t Size);
-
-HAL_StatusTypeDef HAL_SUBGHZ_WriteRegister(SUBGHZ_HandleTypeDef *hsubghz, uint16_t Address, uint8_t Value);
-HAL_StatusTypeDef HAL_SUBGHZ_ReadRegister(SUBGHZ_HandleTypeDef *hsubghz, uint16_t Address, uint8_t *pValue);
-
-void HAL_SUBGHZ_IRQHandler(SUBGHZ_HandleTypeDef *hsubghz);
-void HAL_SUBGHZ_TxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz);
-void HAL_SUBGHZ_RxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz);
-void HAL_SUBGHZ_PreambleDetectedCallback(SUBGHZ_HandleTypeDef *hsubghz);
-void HAL_SUBGHZ_SyncWordValidCallback(SUBGHZ_HandleTypeDef *hsubghz);
-void HAL_SUBGHZ_HeaderValidCallback(SUBGHZ_HandleTypeDef *hsubghz);
-void HAL_SUBGHZ_HeaderErrorCallback(SUBGHZ_HandleTypeDef *hsubghz);
-void HAL_SUBGHZ_CRCErrorCallback(SUBGHZ_HandleTypeDef *hsubghz);
-void HAL_SUBGHZ_CADStatusCallback(SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus);
-void HAL_SUBGHZ_RxTxTimeoutCallback(SUBGHZ_HandleTypeDef *hsubghz);
-/**
-  * @}
-  */
-
-/** @addtogroup SUBGHZ_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State and Error functions ***************************************/
-HAL_SUBGHZ_StateTypeDef HAL_SUBGHZ_GetState(SUBGHZ_HandleTypeDef *hsubghz);
-uint32_t                HAL_SUBGHZ_GetError(SUBGHZ_HandleTypeDef *hsubghz);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32WLxx_HAL_SUBGHZ_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/