Merge pull request #3257 from FlyGoat/mips-refine-v1

MIPS Base Code Refine v1

bsp/ls1bdev/Kconfig

@@ -0,0 +1,44 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$RTT_DIR/libcpu/mips/common/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_LS1B
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+if RT_USING_SERIAL
+config RT_USING_UART0
+    bool "Using RT_USING_UART0"
+    default y
+config RT_USING_UART1
+    bool "Using RT_USING_UART1"
+    default n
+config RT_USING_UART3
+    bool "Using RT_USING_UART3"
+    default n
+
+config RT_UART_RX_BUFFER_SIZE
+    int "The rx buffer size"
+    default 64 if RT_USING_SERIAL
+    default 64
+endif
+

bsp/ls1bdev/SConstruct

@@ -14,10 +14,10 @@ TARGET = 'rtthread.' + rtconfig.TARGET_EXT
 
 DefaultEnvironment(tools=[])
 env = Environment(tools = ['mingw'],
-	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-	AR = rtconfig.AR, ARFLAGS = '-rc',
-	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
 
 Export('RTT_ROOT')

bsp/ls1bdev/applications/application.c

@@ -1,59 +0,0 @@
-/*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-06-25     Bernard      first version
- * 2011-08-08     lgnq         modified for Loongson LS1B
- */
-
-#include <rtthread.h>
-#include <ls1b.h>
-
-#ifdef RT_USING_RTGUI
-#include <rtgui/rtgui.h>
-extern void rt_hw_dc_init(void);
-#endif
-
-void rt_init_thread_entry(void *parameter)
-{
-#ifdef RT_USING_RTGUI
-	{
-		rt_device_t dc;
-
-		/* init Display Controller */
-		rt_hw_dc_init();
-
-		/* find Display Controller device */
-		dc = rt_device_find("dc");
-
-		/* set Display Controller device as rtgui graphic driver */
-		rtgui_graphic_set_device(dc);
-	}
-#endif
-
-#ifdef RT_USING_COMPONENTS_INIT
-	/* initialization RT-Thread Components */
-	rt_components_init();
-#endif
-}
-
-int rt_application_init(void)
-{
-	rt_thread_t tid;
-
-	/* create initialization thread */
-	tid = rt_thread_create("init",
-							rt_init_thread_entry, RT_NULL,
-							4096, 8, 20);
-	if (tid != RT_NULL)
-		rt_thread_startup(tid);
-
-	return 0;
-}

bsp/ls1bdev/applications/main.c

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-10     zhuangwei    first version
+ */
+
+#include <rtthread.h>
+
+int main(int argc, char** argv)
+{   
+
+    return 0;
+}

bsp/ls1bdev/applications/startup.c

@@ -1,92 +0,0 @@
-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2012, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-06-25     Bernard      first version
- * 2011-08-08     lgnq         modified for Loongson LS1B
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-#define A_K0BASE		0x80000000
-
-/**
- * @addtogroup Loongson LS1B
- */
-
-/*@{*/
-
-extern unsigned char __bss_end;
-
-extern int rt_application_init(void);
-
-extern void tlb_refill_exception(void);
-extern void general_exception(void);
-extern void irq_exception(void);
-extern void rt_hw_cache_init(void);
-extern void invalidate_writeback_dcache_all(void);
-extern void invalidate_icache_all(void);
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-    /* disable interrupt first */
-    rt_hw_interrupt_disable();
-
-    /* init cache */
-    rt_hw_cache_init();
-    /* init hardware interrupt */
-    rt_hw_interrupt_init();
-
-    /* copy vector */
-    rt_memcpy((void *)A_K0BASE, tlb_refill_exception, 0x20);
-    rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x20);
-    rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x20);
-
-    invalidate_writeback_dcache_all();
-    invalidate_icache_all();
-
-    /* init board */
-    rt_hw_board_init();
-
-    /* show version */
-    rt_show_version();
-
-#ifdef RT_USING_HEAP
-    rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
-#endif
-
-    /* init scheduler system */
-    rt_system_scheduler_init();
-
-    /* initialize timer */
-    rt_system_timer_init();
-
-    /* initialize timer thread */
-    rt_system_timer_thread_init();
-
-    /* init idle thread */
-    rt_thread_idle_init();
-
-    /* init application */
-    rt_application_init();
-
-    /* start scheduler */
-    rt_system_scheduler_start();
-
-    /* never reach here */
-    return;
-}
-
-/*@}*/

bsp/ls1bdev/drivers/board.c

@@ -11,6 +11,7 @@
  * Date           Author       Notes
  * 2010-06-25     Bernard      first version
  * 2011-08-08     lgnq         modified for Loongson LS1B
+ * 2019-12-04     Jiaxun Yang  Adapt new MIPS generic code
  */
 
 #include <rtthread.h>
@@ -20,92 +21,68 @@
 #include "uart.h"
 #include "ls1b.h"
 
+#ifdef RT_USING_RTGUI
+#include <rtgui/rtgui.h>
+rt_device_t dc;
+extern void rt_hw_dc_init(void);
+#endif
+
+extern unsigned char __bss_end;
+
 /**
  * @addtogroup Loongson LS1B
  */
  
 /*@{*/
 
-/**
- * This is the timer interrupt service routine.
- */
-void rt_hw_timer_handler(void)
-{
-	unsigned int count;
-
-	count = read_c0_compare();
-	write_c0_compare(count);
-	write_c0_count(0);
-
-	/* increase a OS tick */
-	rt_tick_increase();
-}
-
-/**
- * This function will initial OS timer
- */
-void rt_hw_timer_init(void)
-{
-	write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
-	write_c0_count(0);
-}
-
 /**
  * This function will initial sam7s64 board.
  */
 void rt_hw_board_init(void)
 {
-#ifdef RT_USING_UART
-	/* init hardware UART device */
-	rt_hw_uart_init();
+    /* init hardware interrupt */
+    rt_hw_exception_init();
+    
+    /* init hardware interrupt */
+    rt_hw_interrupt_init();
+    
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
+#endif
+
+#ifdef RT_USING_SERIAL
+    /* init hardware UART device */
+    rt_hw_uart_init();
 #endif
 
 #ifdef RT_USING_CONSOLE
-	/* set console device */
-	rt_console_set_device("uart0");
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
+    /* init operating system timer */
+    rt_hw_timer_init();
 
-	/* init operating system timer */
-	rt_hw_timer_init();
+#ifdef RT_USING_FPU
+    /* init hardware fpu */
+    rt_hw_fpu_init();
+#endif
 
-	rt_kprintf("current sr: 0x%08x\n", read_c0_status());
-}
+#ifdef RT_USING_RTGUI
+    rt_device_t dc;
 
-#define __raw_out_put(unr) \
-	while (*ptr) \
-	{ \
-		if (*ptr == '\n') \
-		{ \
-			/* FIFO status, contain valid data */ \
-			while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \
-			/* write data */ \
-			UART_DAT(UART##unr##_BASE) = '\r'; \
-		} \
-		/* FIFO status, contain valid data */ \
-		while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \
-		/* write data */ \
-		UART_DAT(UART##unr##_BASE) = *ptr; \
-		ptr ++; \
-	}
+    /* init Display Controller */
+    rt_hw_dc_init();
 
-/* UART line status register value */
-#define UARTLSR_ERROR	(1 << 7)
-#define UARTLSR_TE		(1 << 6)
-#define UARTLSR_TFE		(1 << 5)
-#define UARTLSR_BI		(1 << 4)
-#define UARTLSR_FE		(1 << 3)
-#define UARTLSR_PE		(1 << 2)
-#define UARTLSR_OE		(1 << 1)
-#define UARTLSR_DR		(1 << 0)
-void rt_hw_console_output(const char *ptr)
-{
-#if defined(RT_USING_UART0)
-    __raw_out_put(0);
-#elif defined(RT_USING_UART1)
-    __raw_out_put(1);
-#elif defined(RT_USING_UART3)
-    __raw_out_put(3);
+    /* find Display Controller device */
+    dc = rt_device_find("dc");
+
+    /* set Display Controller device as rtgui graphic driver */
+    rtgui_graphic_set_device(dc);
 #endif
-}
 
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+}
 /*@}*/

bsp/ls1bdev/drivers/uart.c

@@ -23,257 +23,257 @@
 
 /*@{*/
 
-#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
+#if defined(RT_USING_DEVICE)
 
 struct rt_uart_ls1b
 {
-	struct rt_device parent;
+    struct rt_device parent;
 
-	rt_uint32_t hw_base;
-	rt_uint32_t irq;
+    rt_uint32_t hw_base;
+    rt_uint32_t irq;
 
-	/* buffer for reception */
-	rt_uint8_t read_index, save_index;
-	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
+    /* buffer for reception */
+    rt_uint8_t read_index, save_index;
+    rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
 }uart_device;
 
 static void rt_uart_irqhandler(int irqno, void *param)
 {
-	rt_ubase_t level;
-	rt_uint8_t isr;
-	struct rt_uart_ls1b *uart = &uart_device;
-
-	/* read interrupt status and clear it */
-	isr = UART_IIR(uart->hw_base);
-	isr = (isr >> 1) & 0x3;
-
-	/* receive data available */
-	if (isr & 0x02)
-	{
-		/* Receive Data Available */
-		while (UART_LSR(uart->hw_base) & UARTLSR_DR)
-		{
-			uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
-
-			level = rt_hw_interrupt_disable();
-			uart->save_index ++;
-			if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
-				uart->save_index = 0;
-			rt_hw_interrupt_enable(level);
-		}
-
-		/* invoke callback */
-		if (uart->parent.rx_indicate != RT_NULL)
-		{
-			rt_size_t length;
-			if (uart->read_index > uart->save_index)
-				length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
-			else
-				length = uart->save_index - uart->read_index;
-
-			uart->parent.rx_indicate(&uart->parent, length);
-		}
-	}
-
-	return;
+    rt_ubase_t level;
+    rt_uint8_t isr;
+    struct rt_uart_ls1b *uart = &uart_device;
+
+    /* read interrupt status and clear it */
+    isr = UART_IIR(uart->hw_base);
+    isr = (isr >> 1) & 0x3;
+
+    /* receive data available */
+    if (isr & 0x02)
+    {
+        /* Receive Data Available */
+        while (UART_LSR(uart->hw_base) & UARTLSR_DR)
+        {
+            uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
+
+            level = rt_hw_interrupt_disable();
+            uart->save_index ++;
+            if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
+                uart->save_index = 0;
+            rt_hw_interrupt_enable(level);
+        }
+
+        /* invoke callback */
+        if (uart->parent.rx_indicate != RT_NULL)
+        {
+            rt_size_t length;
+            if (uart->read_index > uart->save_index)
+                length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
+            else
+                length = uart->save_index - uart->read_index;
+
+            uart->parent.rx_indicate(&uart->parent, length);
+        }
+    }
+
+    return;
 }
 
 static rt_err_t rt_uart_init(rt_device_t dev)
 {
-	rt_uint32_t baud_div;
-	struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+    rt_uint32_t baud_div;
+    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
 
-	RT_ASSERT(uart != RT_NULL);
+    RT_ASSERT(uart != RT_NULL);
 
 #if 0
-	/* init UART Hardware */
-	UART_IER(uart->hw_base) = 0; /* clear interrupt */
-	UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */
+    /* init UART Hardware */
+    UART_IER(uart->hw_base) = 0; /* clear interrupt */
+    UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */
 
-	/* enable UART clock */
-	/* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
-	UART_LCR(uart->hw_base) = 0x3;
+    /* enable UART clock */
+    /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
+    UART_LCR(uart->hw_base) = 0x3;
 
-	/* set baudrate */
-	baud_div = DEV_CLK / 16 / UART_BAUDRATE;
-	UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
+    /* set baudrate */
+    baud_div = DEV_CLK / 16 / UART_BAUDRATE;
+    UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
 
-	UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
-	UART_LSB(uart->hw_base) = baud_div & 0xff;
+    UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
+    UART_LSB(uart->hw_base) = baud_div & 0xff;
 
-	UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
+    UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
 
-	/* Enable UART unit, enable and clear FIFO */
-	UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
+    /* Enable UART unit, enable and clear FIFO */
+    UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
 #endif
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
-
-	RT_ASSERT(uart != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Enable the UART Interrupt */
-		UART_IER(uart->hw_base) |= UARTIER_IRXE;
-
-		/* install interrupt */
-		rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART");
-		rt_hw_interrupt_umask(uart->irq);
-	}
-	return RT_EOK;
+    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+
+    RT_ASSERT(uart != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* Enable the UART Interrupt */
+        UART_IER(uart->hw_base) |= UARTIER_IRXE;
+
+        /* install interrupt */
+        rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART");
+        rt_hw_interrupt_umask(uart->irq);
+    }
+    return RT_EOK;
 }
 
 static rt_err_t rt_uart_close(rt_device_t dev)
 {
-	struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
 
-	RT_ASSERT(uart != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Disable the UART Interrupt */
-		UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
-	}
+    RT_ASSERT(uart != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* Disable the UART Interrupt */
+        UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
 {
-	rt_uint8_t *ptr;
-	struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
-
-	RT_ASSERT(uart != RT_NULL);
-
-	/* point to buffer */
-	ptr = (rt_uint8_t *)buffer;
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
-
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (uart->read_index != uart->save_index)
-			{
-				*ptr = uart->rx_buffer[uart->read_index];
-
-				uart->read_index ++;
-				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
-					uart->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
-
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
-
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
-
-			ptr ++;
-			size --;
-		}
-
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
-
-	return 0;
+    rt_uint8_t *ptr;
+    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+
+    RT_ASSERT(uart != RT_NULL);
+
+    /* point to buffer */
+    ptr = (rt_uint8_t *)buffer;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        while (size)
+        {
+            /* interrupt receive */
+            rt_base_t level;
+
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
+            if (uart->read_index != uart->save_index)
+            {
+                *ptr = uart->rx_buffer[uart->read_index];
+
+                uart->read_index ++;
+                if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    uart->read_index = 0;
+            }
+            else
+            {
+                /* no data in rx buffer */
+
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+                break;
+            }
+
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
+
+            ptr ++;
+            size --;
+        }
+
+        return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    }
+
+    return 0;
 }
 
 static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
 {
-	char *ptr;
-	struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
-
-	RT_ASSERT(uart != RT_NULL);
-
-	ptr = (char *)buffer;
-
-	if (dev->flag & RT_DEVICE_FLAG_STREAM)
-	{
-		/* stream mode */
-		while (size)
-		{
-			if (*ptr == '\n')
-			{
-				/* FIFO status, contain valid data */
-				while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
-				/* write data */
-				UART_DAT(uart->hw_base) = '\r';
-			}
-
-			/* FIFO status, contain valid data */
-			while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
-			/* write data */
-			UART_DAT(uart->hw_base) = *ptr;
-
-			ptr ++;
-			size --;
-		}
-	}
-	else
-	{
-		while (size != 0)
-		{
-			/* FIFO status, contain valid data */
-			while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
-
-			/* write data */
-			UART_DAT(uart->hw_base) = *ptr;
-
-			ptr++;
-			size--;
-		}
-	}
-
-	return (rt_size_t)ptr - (rt_size_t)buffer;
+    char *ptr;
+    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+
+    RT_ASSERT(uart != RT_NULL);
+
+    ptr = (char *)buffer;
+
+    if (dev->flag & RT_DEVICE_FLAG_STREAM)
+    {
+        /* stream mode */
+        while (size)
+        {
+            if (*ptr == '\n')
+            {
+                /* FIFO status, contain valid data */
+                while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
+                /* write data */
+                UART_DAT(uart->hw_base) = '\r';
+            }
+
+            /* FIFO status, contain valid data */
+            while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
+            /* write data */
+            UART_DAT(uart->hw_base) = *ptr;
+
+            ptr ++;
+            size --;
+        }
+    }
+    else
+    {
+        while (size != 0)
+        {
+            /* FIFO status, contain valid data */
+            while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
+
+            /* write data */
+            UART_DAT(uart->hw_base) = *ptr;
+
+            ptr++;
+            size--;
+        }
+    }
+
+    return (rt_size_t)ptr - (rt_size_t)buffer;
 }
 
 void rt_hw_uart_init(void)
 {
-	struct rt_uart_ls1b *uart;
+    struct rt_uart_ls1b *uart;
 
-	/* get uart device */
-	uart = &uart_device;
+    /* get uart device */
+    uart = &uart_device;
 
-	/* device initialization */
-	uart->parent.type = RT_Device_Class_Char;
-	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
-	uart->read_index = uart->save_index = 0;
+    /* device initialization */
+    uart->parent.type = RT_Device_Class_Char;
+    rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
+    uart->read_index = uart->save_index = 0;
 
 #if defined(RT_USING_UART0)
-	uart->hw_base = UART0_BASE;
-	uart->irq = LS1B_UART0_IRQ;
+    uart->hw_base = UART0_BASE;
+    uart->irq = LS1B_UART0_IRQ;
 #elif defined(RT_USING_UART1)
-	uart->hw_base = UART1_BASE;
-	uart->irq = LS1B_UART1_IRQ;
+    uart->hw_base = UART1_BASE;
+    uart->irq = LS1B_UART1_IRQ;
 #elif defined(RT_USING_UART3)
-	uart->hw_base = UART3_BASE;
-	uart->irq = LS1B_UART3_IRQ;
+    uart->hw_base = UART3_BASE;
+    uart->irq = LS1B_UART3_IRQ;
 #endif
 
-	/* device interface */
-	uart->parent.init       = rt_uart_init;
-	uart->parent.open       = rt_uart_open;
-	uart->parent.close      = rt_uart_close;
-	uart->parent.read       = rt_uart_read;
-	uart->parent.write      = rt_uart_write;
-	uart->parent.control    = RT_NULL;
-	uart->parent.user_data  = RT_NULL;
-
-	rt_device_register(&uart->parent, "uart0",
-						RT_DEVICE_FLAG_RDWR |
-						RT_DEVICE_FLAG_STREAM |
-						RT_DEVICE_FLAG_INT_RX);
+    /* device interface */
+    uart->parent.init       = rt_uart_init;
+    uart->parent.open       = rt_uart_open;
+    uart->parent.close      = rt_uart_close;
+    uart->parent.read       = rt_uart_read;
+    uart->parent.write      = rt_uart_write;
+    uart->parent.control    = RT_NULL;
+    uart->parent.user_data  = RT_NULL;
+
+    rt_device_register(&uart->parent, "uart0",
+                        RT_DEVICE_FLAG_RDWR |
+                        RT_DEVICE_FLAG_STREAM |
+                        RT_DEVICE_FLAG_INT_RX);
 }
 #endif /* end of UART */
 

bsp/ls1bdev/drivers/uart.h

@@ -16,8 +16,9 @@
 #define __UART_H__
 
 #include "ls1b.h"
+#include <rthw.h>
 
-#define UART0_BASE			0xBFE40000
+#define UART0_BASE		    0xBFE40000
 #define UART0_1_BASE		0xBFE41000
 #define UART0_2_BASE		0xBFE42000
 #define UART0_3_BASE		0xBFE43000
@@ -31,43 +32,43 @@
 #define UART5_BASE			0xBFE7C000
 
 /* UART registers */
-#define UART_DAT(base)		__REG8(base + 0x00)
-#define UART_IER(base)		__REG8(base + 0x01)
-#define UART_IIR(base)		__REG8(base + 0x02)
-#define UART_FCR(base)		__REG8(base + 0x02)
-#define UART_LCR(base)		__REG8(base + 0x03)
-#define UART_MCR(base)		__REG8(base + 0x04)
-#define UART_LSR(base)		__REG8(base + 0x05)
-#define UART_MSR(base)		__REG8(base + 0x06)
+#define UART_DAT(base)		HWREG8(base + 0x00)
+#define UART_IER(base)		HWREG8(base + 0x01)
+#define UART_IIR(base)		HWREG8(base + 0x02)
+#define UART_FCR(base)		HWREG8(base + 0x02)
+#define UART_LCR(base)		HWREG8(base + 0x03)
+#define UART_MCR(base)		HWREG8(base + 0x04)
+#define UART_LSR(base)		HWREG8(base + 0x05)
+#define UART_MSR(base)		HWREG8(base + 0x06)
 
-#define UART_LSB(base)		__REG8(base + 0x00)
-#define UART_MSB(base)		__REG8(base + 0x01)
+#define UART_LSB(base)		HWREG8(base + 0x00)
+#define UART_MSB(base)		HWREG8(base + 0x01)
 
 /* UART0 registers */
-#define UART0_DAT			__REG8(UART0_BASE + 0x00)
-#define UART0_IER			__REG8(UART0_BASE + 0x01)
-#define UART0_IIR			__REG8(UART0_BASE + 0x02)
-#define UART0_FCR			__REG8(UART0_BASE + 0x02)
-#define UART0_LCR			__REG8(UART0_BASE + 0x03)
-#define UART0_MCR			__REG8(UART0_BASE + 0x04)
-#define UART0_LSR			__REG8(UART0_BASE + 0x05)
-#define UART0_MSR			__REG8(UART0_BASE + 0x06)
+#define UART0_DAT			HWREG8(UART0_BASE + 0x00)
+#define UART0_IER			HWREG8(UART0_BASE + 0x01)
+#define UART0_IIR			HWREG8(UART0_BASE + 0x02)
+#define UART0_FCR			HWREG8(UART0_BASE + 0x02)
+#define UART0_LCR			HWREG8(UART0_BASE + 0x03)
+#define UART0_MCR			HWREG8(UART0_BASE + 0x04)
+#define UART0_LSR			HWREG8(UART0_BASE + 0x05)
+#define UART0_MSR			HWREG8(UART0_BASE + 0x06)
 
-#define UART0_LSB			__REG8(UART0_BASE + 0x00)
-#define UART0_MSB			__REG8(UART0_BASE + 0x01)
+#define UART0_LSB			HWREG8(UART0_BASE + 0x00)
+#define UART0_MSB			HWREG8(UART0_BASE + 0x01)
 
 /* UART1 registers */
-#define UART1_DAT			__REG8(UART1_BASE + 0x00)
-#define UART1_IER			__REG8(UART1_BASE + 0x01)
-#define UART1_IIR			__REG8(UART1_BASE + 0x02)
-#define UART1_FCR			__REG8(UART1_BASE + 0x02)
-#define UART1_LCR			__REG8(UART1_BASE + 0x03)
-#define UART1_MCR			__REG8(UART1_BASE + 0x04)
-#define UART1_LSR			__REG8(UART1_BASE + 0x05)
-#define UART1_MSR			__REG8(UART1_BASE + 0x06)
+#define UART1_DAT			HWREG8(UART1_BASE + 0x00)
+#define UART1_IER			HWREG8(UART1_BASE + 0x01)
+#define UART1_IIR			HWREG8(UART1_BASE + 0x02)
+#define UART1_FCR			HWREG8(UART1_BASE + 0x02)
+#define UART1_LCR			HWREG8(UART1_BASE + 0x03)
+#define UART1_MCR			HWREG8(UART1_BASE + 0x04)
+#define UART1_LSR			HWREG8(UART1_BASE + 0x05)
+#define UART1_MSR			HWREG8(UART1_BASE + 0x06)
 
-#define UART1_LSB			__REG8(UART1_BASE + 0x00)
-#define UART1_MSB			__REG8(UART1_BASE + 0x01)
+#define UART1_LSB			HWREG8(UART1_BASE + 0x00)
+#define UART1_MSB			HWREG8(UART1_BASE + 0x01)
 
 /* UART interrupt enable register value */
 #define UARTIER_IME		(1 << 3)

bsp/ls1bdev/ls1b_ram.lds

@@ -11,6 +11,7 @@
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
  * 2010-09-04     bernard      move the beginning entry to 0x80200000
+ * 2019-12-04     Jiaxun Yang  Adapt new memory layout
  */
 
 OUTPUT_ARCH(mips)
@@ -19,16 +20,19 @@ GROUP(-lgcc -lc)
 ENTRY(_start)
 SECTIONS
 {
-    . = 0x80200000 ;
-
-    .start :
-    {
-        *(.start);
-    }
-
-    . = ALIGN(4);
+    . = 0x80200000;
     .text : 
     {
+	start = ABSOLUTE(.);
+	 *(.selfboot);
+	 *(.selfboot_data);
+	. = ALIGN(4);
+	__selfboot_end = .;
+	. = ALIGN(0x1000);
+	__ebase_entry = .;
+     	KEEP(*(.exc_vectors))
+     	__ebase_end = .;
+	 *(.start);
          *(.text)
          *(.text.*)
          *(.rodata)
@@ -76,6 +80,15 @@ SECTIONS
          *(.sdata)
          *(.sdata.*)
     }
+    _edata = .;
+
+    .stack :
+    {
+        . = ALIGN(8);
+        _system_stack_start = .;
+        . = . + 0x400; /* 1kb system stack */
+        _system_stack = .;
+    }
 
     .sbss : 
     {

bsp/ls1bdev/readme.txt → bsp/ls1bdev/readme.md

@@ -1,4 +1,4 @@
-this bsp is based on LS1G DEMO BOARD V1.1
+This bsp is based on LS1B DEMO BOARD V1.1
 
 # download script for RT-Thread
 ifaddr syn0 192.168.1.100;load tftp://192.168.1.5/rtthread.elf;g

bsp/ls1bdev/rtconfig.h

@@ -1,223 +1,163 @@
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
-
-// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
-#define RT_NAME_MAX	10
-// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
-#define RT_ALIGN_SIZE	4
-// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
-// <item description="8">8</item>
-// <item description="32">32</item>
-// <item description="256">256</item>
-// </integer>
-#define RT_THREAD_PRIORITY_MAX	32
-// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
-#define RT_TICK_PER_SECOND	100
-// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
-#define RT_DEBUG
-#define RT_DEBUG_COLOR
-// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
-// #define RT_THREAD_DEBUG
-// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
-#define RT_USING_OVERFLOW_CHECK
-// <bool name="RT_USING_INTERRUPT_INFO" description="Show more interrupt description" default="true" />
-#define RT_USING_INTERRUPT_INFO
-// </section>
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
 
-// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
-// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
-// #define RT_USING_TIMER_SOFT
-// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
-#define RT_TIMER_THREAD_PRIO	4
-// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
-#define RT_TIMER_THREAD_STACK_SIZE	512
-// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
-#define RT_TIMER_TICK_PER_SECOND	10
-// </section>
-
-// <section name="IPC" description="Inter-Thread communication" default="always" >
-// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
 #define RT_USING_SEMAPHORE
-// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
 #define RT_USING_MUTEX
-// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
 #define RT_USING_EVENT
-// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
 #define RT_USING_MAILBOX
-// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
 #define RT_USING_MESSAGEQUEUE
-// </section>
 
-// <section name="MM" description="Memory Management" default="always" >
-// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
+/* Memory Management */
+
 #define RT_USING_MEMPOOL
-// <bool name="RT_USING_MEMHEAP" description="Using Memory Heap Object in the system" default="true" />
-#define RT_USING_MEMHEAP
-// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
-#define RT_USING_HEAP
-// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
 #define RT_USING_SMALL_MEM
-// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
-// #define RT_USING_SLAB
-// </section>
+#define RT_USING_HEAP
 
-// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
-#define RT_USING_DEVICE
-// <bool name="RT_USING_UART" description="Using UART" default="true" />
-#define RT_USING_UART
-// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
-#define RT_USING_UART0
-// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
-#define RT_UART_RX_BUFFER_SIZE	64
-// </section>
+/* Kernel Device Object */
 
-// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
+#define RT_USING_DEVICE
 #define RT_USING_CONSOLE
-// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
-#define RT_CONSOLEBUF_SIZE	128
-// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
-#define RT_CONSOLE_DEVICE_NAME	"uart0"
-// </section>
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart"
+#define RT_VER_NUM 0x40002
+
+/* RT-Thread Components */
 
-// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
 #define RT_USING_COMPONENTS_INIT
-// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
 #define RT_USING_FINSH
-// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
-// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
 #define FINSH_USING_DESCRIPTION
-// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
-#define FINSH_THREAD_STACK_SIZE	4096
-// </section>
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
 
-// <section name="RT_USING_LIBC" description="C Runtime library setting" default="true" >
 #define RT_USING_LIBC
-// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
-#define RT_USING_PTHREADS
-// </section>
-
-// <section name="RT_USING_DFS" description="Device file system" default="true" >
-// #define RT_USING_DFS
-// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
-// #define DFS_USING_WORKDIR
-// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
-#define DFS_FILESYSTEMS_MAX	2
-// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
-#define DFS_FD_MAX	4
-// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
-#define RT_USING_DFS_ELMFAT
-// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
-// <item description="LFN1">1</item>
-// <item description="LFN1">2</item>
-// </integer>
-#define RT_DFS_ELM_USE_LFN	1
-// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
-#define RT_DFS_ELM_MAX_LFN	64
-// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
-// #define RT_USING_DFS_YAFFS2
-// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
-// #define RT_USING_DFS_UFFS
-// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
-// #define RT_USING_DFS_DEVFS
-// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
-// #define RT_USING_DFS_NFS
-// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
-#define RT_NFS_HOST_EXPORT	"192.168.1.5:/"
-// </section>
-
-// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
-// #define RT_USING_LWIP
-// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
-#define RT_LWIP_ICMP
-// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
-// #define RT_LWIP_IGMP
-// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
-#define RT_LWIP_UDP
-// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
-#define RT_LWIP_TCP
-// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
-#define RT_LWIP_DNS
-// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
-#define RT_LWIP_PBUF_NUM	4
-// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
-#define RT_LWIP_TCP_PCB_NUM	3
-// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
-#define RT_LWIP_TCP_SND_BUF	2048
-// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
-#define RT_LWIP_TCP_WND	2048
-// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
-// #define RT_LWIP_SNMP
-// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
-// #define RT_LWIP_DHCP
-// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="4" />
-#define RT_LWIP_TCP_SEG_NUM	4
-// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
-#define RT_LWIP_TCPTHREAD_PRIORITY	12
-// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE	8
-// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
-#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
-// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
-#define RT_LWIP_ETHTHREAD_PRIORITY	14
-// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE	8
-// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
-#define RT_LWIP_ETHTHREAD_STACKSIZE	512
-// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
-#define RT_LWIP_IPADDR0 192
-#define RT_LWIP_IPADDR1 168
-#define RT_LWIP_IPADDR2 1
-#define RT_LWIP_IPADDR3 30
-// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
-#define RT_LWIP_GWADDR0 192
-#define RT_LWIP_GWADDR1 168
-#define RT_LWIP_GWADDR2 1
-#define RT_LWIP_GWADDR3 1
-// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
-#define RT_LWIP_MSKADDR0 255
-#define RT_LWIP_MSKADDR1 255
-#define RT_LWIP_MSKADDR2 255
-#define RT_LWIP_MSKADDR3 0
-// </section>
-
-// <section name="RT_USING_MODULE" description="Application module" default="true" >
-// #define RT_USING_MODULE
-// </section>
-
-// <section name="RT_USING_RTGUI" description="RTGUI, a graphic user interface" default="true" >
-// #define RT_USING_RTGUI
-// <integer name="RTGUI_NAME_MAX" description="Maximal size of RTGUI object name length" default="16" />
-#define RTGUI_NAME_MAX	16
-// <bool name="RTGUI_USING_FONT16" description="Support 16 weight font" default="true" />
-#define RTGUI_USING_FONT16
-// <bool name="RTGUI_USING_FONT12" description="Support 12 weight font" default="true" />
-#define RTGUI_USING_FONT12
-// <bool name="RTGUI_USING_FONTHZ" description="Support Chinese font" default="true" />
-#define RTGUI_USING_FONTHZ
-// <bool name="RTGUI_USING_DFS_FILERW" description="Using DFS as file interface " default="true" />
-#define RTGUI_USING_DFS_FILERW
-// <bool name="RTGUI_USING_HZ_FILE" description="Using font file as Chinese font" default="false" />
-// #define RTGUI_USING_HZ_FILE
-// <bool name="RTGUI_USING_HZ_BMP" description="Using Chinese bitmap font" default="true" />
-#define RTGUI_USING_HZ_BMP
-// <bool name="RTGUI_USING_SMALL_SIZE" description="Using small size in RTGUI" default="false" />
-#define RTGUI_USING_SMALL_SIZE
-// <bool name="RTGUI_USING_MOUSE_CURSOR" description="Using mouse cursor in RTGUI" default="false" />
-// #define RTGUI_USING_MOUSE_CURSOR
-// <bool name="RTGUI_IMAGE_XPM" description="Using xpm image in RTGUI" default="true" />
-#define RTGUI_IMAGE_XPM
-// <bool name="RTGUI_IMAGE_JPEG" description="Using jpeg image in RTGUI" default="true" />
-// #define RTGUI_IMAGE_JPEG
-// <bool name="RTGUI_IMAGE_PNG" description="Using png image in RTGUI" default="true" />
-// #define RTGUI_IMAGE_PNG
-// <bool name="RTGUI_IMAGE_BMP" description="Using bmp image in RTGUI" default="true" />
-#define RTGUI_IMAGE_BMP
-// </section>
-
-// </RDTConfigurator>
+#define RT_USING_POSIX
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread MIPS CPU */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+#define SOC_LS1B
+#define RT_USING_UART0
+#define RT_UART_RX_BUFFER_SIZE 64
 
 #endif

bsp/ls1bdev/rtconfig.py

@@ -2,7 +2,7 @@ import os
 
 # CPU options
 ARCH='mips'
-CPU ='loongson_1b'
+CPU ='gs232'
 
 # toolchains options
 CROSS_TOOL  = 'gcc'
@@ -12,7 +12,8 @@ if os.getenv('RTT_CC'):
 
 if  CROSS_TOOL == 'gcc':
 	PLATFORM    = 'gcc'
-	EXEC_PATH   = r'C:\Program Files\CodeSourcery\Sourcery G++ Lite For MIPS ELF\bin'
+	EXEC_PATH   = "/opt/mips-2016.05/bin"
+#	EXEC_PATH   = r'D:\mgc\embedded\codebench\bin'
 else:
     print('================ERROR============================')
     print('Not support %s yet!' % CROSS_TOOL)
@@ -37,7 +38,7 @@ READELF = PREFIX + 'readelf'
 
 DEVICE = ' -mips32'
 CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
-AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp -DSYSTEM_STACK=0x80003fe8'
+AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
 LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls1b_ram.lds'
 
 CPATH = ''

bsp/ls1cdev/Kconfig

@@ -9,108 +9,118 @@ config RTT_DIR
     string
     option env="RTT_ROOT"
     default "../.."
-    
+
 config PKGS_DIR
     string
     option env="PKGS_ROOT"
     default "packages"
 
 source "$RTT_DIR/Kconfig"
+source "$RTT_DIR/libcpu/mips/common/Kconfig"
 source "$PKGS_DIR/Kconfig"
 
 config SOC_1C300
-    bool 
+    bool
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     default y
 
+choice
+    prompt "Board Type"
+        config RT_LS1C_OPENLOONGSON
+            bool "OpenLoongson Board"
+        config RT_LS1C_BAICAIBOARD
+            bool "Baicai Board"
+endchoice
+
 config RT_USING_SELF_BOOT
     bool "Enable RT-Thread run without bootloader"
     default n
-	
+
+if RT_USING_SELF_BOOT
+    config RT_SELF_BOOT_DEBUG
+    bool "Debug self boot code"
+    default n
+endif
+
 if RT_USING_SERIAL
 config RT_USING_UART2
     bool "Using RT_USING_UART2"
-    default y      
+    default y
 config RT_USING_UART1
     bool "Using RT_USING_UART1"
-    default y      
+    default y
 config RT_USING_UART3
     bool "Using RT_USING_UART3"
-    default n      
+    default n
 
 config RT_UART_RX_BUFFER_SIZE
-    int "The rx buffer size"        
+    int "The rx buffer size"
     default 64 if RT_USING_SERIAL
-    default 64 
-endif  
+    default 64
+endif
 
 config RT_USING_GMAC_INT_MODE
     bool "Using RT_USING_GMAC_INT_MODE"
     default y
-	
-config RT_USING_FPU
-    bool "Using RT_USING_FPU"
-    default y
-	
+
 config RT_USING_SPI0
     bool "Enable SPI0"
 	select RT_USING_SPI
-    default y      
+    default y
 
 config RT_USING_SPI1
     bool "Enable SPI1"
 	select RT_USING_SPI
-    default y      
-	
+    default y
+
 if RT_USING_I2C
 config RT_USING_I2C1
     bool "Enable I2C1"
     default y
-	
+
 config RT_USING_I2C2
-    bool "Enable I2C2"  
-    default y 
+    bool "Enable I2C2"
+    default y
 endif
 
-	
+
 config USING_BXCAN0
     bool "Enable CAN0"
 	select RT_USING_CAN
-    default y      
-  
+    default y
+
 config USING_BXCAN1
     bool "Enable CAN1"
 	select RT_USING_CAN
-    default y      
+    default y
 
 if RT_USING_CAN
 config RT_CAN_USING_HDR
     bool "Using RT_CAN_USING_HDR"
 	select RT_USING_CAN
-    default y  
-endif    
+    default y
+endif
 
 choice
     prompt "Touch format"
     default NO_TOUCH
 
     config NO_TOUCH
-        bool "with no touch"	
-		
+        bool "with no touch"
+
 if RT_USING_RTGUI
     config XPT2046_USING_TOUCH
         bool "with XPT2046 touch"
-endif    
+endif
 
     config TINA_USING_TOUCH
-        bool "with TINA touch"		
+        bool "with TINA touch"
 endchoice
 
 if RT_USING_RTC
 config RT_RTC_NAME
     string "RT_RTC_NAME"
-    default "RTC" 
-endif    
+    default "RTC"
+endif
 
-    

bsp/ls1cdev/SConstruct

@@ -16,10 +16,10 @@ rtconfig.AFLAGS += ' -I' + str(Dir('#'))
 
 DefaultEnvironment(tools=[])
 env = Environment(tools = ['mingw'],
-	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-	AR = rtconfig.AR, ARFLAGS = '-rc',
-	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
 env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
 
 Export('RTT_ROOT')
@@ -29,9 +29,9 @@ Export('rtconfig')
 objs = PrepareBuilding(env, RTT_ROOT)
 
 if GetDepend('RT_USING_SELF_BOOT'):
-    rtconfig.LFLAGS += " -Ttext 0x80010000"
+    rtconfig.LFLAGS += " -Ttext 0x80000000"
 else:
-	rtconfig.LFLAGS += " -Ttext 0x80200000"    
+    rtconfig.LFLAGS += " -Ttext 0x80200000"
 env.Replace(LINKFLAGS = rtconfig.LFLAGS)
 
 if GetDepend('RT_USING_FPU'):
@@ -39,9 +39,9 @@ if GetDepend('RT_USING_FPU'):
     env['ASFLAGS']   = env['ASFLAGS'].replace('-msoft-float', '-mhard-float')
     env['CXXFLAGS']  = env['CXXFLAGS'].replace('-msoft-float', '-mhard-float')
     env['LINKFLAGS'] = env['LINKFLAGS'].replace('-msoft-float', '-mhard-float')
-    
+
 if GetDepend('RT_USING_RTGUI'):
     objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
-    
+
 # make a building
 DoBuilding(TARGET, objs)

bsp/ls1cdev/drivers/SConscript

@@ -1,7 +1,7 @@
 from building import *
 
 cwd = GetCurrentDir()
-src = Glob('*.c')
+src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
 
 CPPPATH = [cwd]
 

bsp/ls1cdev/drivers/board.c

@@ -8,74 +8,20 @@
  * 2010-06-25     Bernard      first version
  * 2011-08-08     lgnq            modified for Loongson LS1B
  * 2015-07-06     chinesebear  modified for Loongson LS1C
+ * 2019-12-04     Jiaxun Yang  Adapt new generic MIPS code
  */
 
 #include <rtthread.h>
 #include <rthw.h>
+#include <mips.h>
 
 #include "board.h"
 #include "drv_uart.h"
 #include "ls1c.h"
 
-#define A_K0BASE		0x80000000
-
 extern unsigned char __bss_end;
 
-
-extern void tlb_refill_exception(void);
-extern void general_exception(void);
-extern void irq_exception(void);
-extern void rt_hw_cache_init(void);
-extern void invalidate_writeback_dcache_all(void);
-extern void invalidate_icache_all(void);
-
-/**
- * This is the timer interrupt service routine.
- */
-void rt_hw_timer_handler(void)
-{
-	unsigned int count;
-
-	count = read_c0_compare();
-	write_c0_compare(count);
-	write_c0_count(0);
-
-	/* increase a OS tick */
-	rt_tick_increase();
-}
-
-/**
- * This function will initial OS timer
- */
-void rt_hw_timer_init(void)
-{
-	write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
-	write_c0_count(0);
-}
-
-
-/**
- * init hardware FPU
- */
-void rt_hw_fpu_init(void)
-{
-    rt_uint32_t c0_status = 0;
-    rt_uint32_t c1_status = 0;
-
-    // 使能协处理器1--FPU
-    c0_status = read_c0_status();
-    c0_status |= (ST0_CU1 | ST0_FR);
-    write_c0_status(c0_status);
-
-    // 配置FPU
-    c1_status = read_c1_status();
-    c1_status |= (FPU_CSR_FS | FPU_CSR_FO | FPU_CSR_FN);    // set FS, FO, FN
-    c1_status &= ~(FPU_CSR_ALL_E);                          // disable exception
-    c1_status = (c1_status & (~FPU_CSR_RM)) | FPU_CSR_RN;   // set RN
-    write_c1_status(c1_status);
-
-    return ;
-}
+#define RT_HW_HEAP_END    (0x80000000 + MEM_SIZE)
 
 
 /**
@@ -83,35 +29,24 @@ void rt_hw_fpu_init(void)
  */
 void rt_hw_board_init(void)
 {
-	/* init cache */
-	rt_hw_cache_init();
-	
-	/* init hardware interrupt */
-	rt_hw_interrupt_init();
-
-	/* clear bev */
-	write_c0_status(read_c0_status()&(~(1<<22)));
-
-	/* copy vector */
-	rt_memcpy((void *)A_K0BASE, tlb_refill_exception, 0x80);
-	rt_memcpy((void *)(A_K0BASE + 0x180), general_exception, 0x80);
-	rt_memcpy((void *)(A_K0BASE + 0x200), irq_exception, 0x80);
-
-	invalidate_writeback_dcache_all();
-	invalidate_icache_all();
-	
+    /* init hardware interrupt */
+    rt_hw_exception_init();
+    
+    /* init hardware interrupt */
+    rt_hw_interrupt_init();
+    
 #ifdef RT_USING_HEAP
-	rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
+    rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
 #endif
 
 #ifdef RT_USING_SERIAL
-	/* init hardware UART device */
-	rt_hw_uart_init();
+    /* init hardware UART device */
+    rt_hw_uart_init();
 #endif
 
 #ifdef RT_USING_CONSOLE
-	/* set console device */
-	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
     /* init operating system timer */
     rt_hw_timer_init();

bsp/ls1cdev/drivers/board.h

@@ -8,15 +8,55 @@
  * 2010-06-25     Bernard        first version
  * 2011-08-08     lgnq             modified for Loongson LS1B
  * 2015-07-06     chinesebear   modified for Loongson LS1C
+ * 2019-12-04     Jiaxun Yang   Add board config defines
  */
 
 #ifndef __BOARD_H__
 #define __BOARD_H__
+#include <rtconfig.h>
 
+#ifndef __ASSEMBLY__
 void rt_hw_board_init(void);
+#endif
+
+/*
+* SDRAM config
+*
+* Take IS42S16400 SDRAM chip as a example
+* The specfication is
+* Size 8MB
+* WIDTH: 16 bits
+* COL WIDTH: 8 bits, so we should take the 8 power of 2, it's 256
+* ROW WIDTH: 12 bits, so we take the 12 power of 2, it's 4K
+*
+* Please reference macro SD_PARA0 and SDRAM registers intruduction
+* in user's manual to edit the SDRAM config.
+*/
+
+#if defined(RT_LS1C_BAICAIBOARD)
+/* 8MByte IS42S16400 appeared in bacai_board V1.x V2.x */
+#define MEM_SIZE        (0x800000)
+#define SDRAM_WIDTH     (WIDTH_16)
+#define SDRAM_COL       (COL_256)
+#define SDRAM_ROW       (ROW_4K)
+#elif defined(RT_LS1C_OPENLOONGSON)
+/* 32MByte appeared in SmartLoong board */
+#define MEM_SIZE        (0x2000000)
+#define SDRAM_WIDTH     (WIDTH_16)
+#define SDRAM_COL       (COL_512)
+#define SDRAM_ROW       (ROW_8K)
+#else
+#error Unknown Board
+#endif
+
+/* Early Debug config */
+#define EARLY_DEBUG /* UART2 serial print debug in early stage */
+#define EARLY_DEBUG_BAUD  (115200)
 
-/* 32M SDRAM */
-#define RT_HW_HEAP_END    (0x80000000 + 32 * 1024 * 1024)
+/* Clock config */
 #define CPU_HZ            (252 * 1000000)
+#define PLL_MULT          (0x54)  /* When external clock is 24Mhz PLL=504Mhz */
+#define SDRAM_DIV         (0)     /* SDRAM is CPU divided by 2*/
+#define CPU_DIV           (2)     /* CPU clock is PLL divided by 2 */
 
 #endif

bsp/ls1cdev/drivers/drv_uart.h

@@ -12,6 +12,7 @@
 #define __DRV_UART_H__
 
 #include "ls1c.h"
+#include <rthw.h>
 
 #define DEV_CLK 252000000 // 252MHz
 #define UART_BAUDRATE 115200
@@ -31,43 +32,43 @@
 #define UART11_BASE         0xBFE4Cb00
 
 /* UART registers */
-#define UART_DAT(base)      __REG8(base + 0x00)
-#define UART_IER(base)      __REG8(base + 0x01)
-#define UART_IIR(base)      __REG8(base + 0x02)
-#define UART_FCR(base)      __REG8(base + 0x02)
-#define UART_LCR(base)      __REG8(base + 0x03)
-#define UART_MCR(base)      __REG8(base + 0x04)
-#define UART_LSR(base)      __REG8(base + 0x05)
-#define UART_MSR(base)      __REG8(base + 0x06)
-
-#define UART_LSB(base)      __REG8(base + 0x00)
-#define UART_MSB(base)      __REG8(base + 0x01)
+#define UART_DAT(base)      HWREG8(base + 0x00)
+#define UART_IER(base)      HWREG8(base + 0x01)
+#define UART_IIR(base)      HWREG8(base + 0x02)
+#define UART_FCR(base)      HWREG8(base + 0x02)
+#define UART_LCR(base)      HWREG8(base + 0x03)
+#define UART_MCR(base)      HWREG8(base + 0x04)
+#define UART_LSR(base)      HWREG8(base + 0x05)
+#define UART_MSR(base)      HWREG8(base + 0x06)
+
+#define UART_LSB(base)      HWREG8(base + 0x00)
+#define UART_MSB(base)      HWREG8(base + 0x01)
 
 /* UART0 registers */
-#define UART0_DAT           __REG8(UART0_BASE + 0x00)
-#define UART0_IER           __REG8(UART0_BASE + 0x01)
-#define UART0_IIR           __REG8(UART0_BASE + 0x02)
-#define UART0_FCR           __REG8(UART0_BASE + 0x02)
-#define UART0_LCR           __REG8(UART0_BASE + 0x03)
-#define UART0_MCR           __REG8(UART0_BASE + 0x04)
-#define UART0_LSR           __REG8(UART0_BASE + 0x05)
-#define UART0_MSR           __REG8(UART0_BASE + 0x06)
-
-#define UART0_LSB           __REG8(UART0_BASE + 0x00)
-#define UART0_MSB           __REG8(UART0_BASE + 0x01)
+#define UART0_DAT           HWREG8(UART0_BASE + 0x00)
+#define UART0_IER           HWREG8(UART0_BASE + 0x01)
+#define UART0_IIR           HWREG8(UART0_BASE + 0x02)
+#define UART0_FCR           HWREG8(UART0_BASE + 0x02)
+#define UART0_LCR           HWREG8(UART0_BASE + 0x03)
+#define UART0_MCR           HWREG8(UART0_BASE + 0x04)
+#define UART0_LSR           HWREG8(UART0_BASE + 0x05)
+#define UART0_MSR           HWREG8(UART0_BASE + 0x06)
+
+#define UART0_LSB           HWREG8(UART0_BASE + 0x00)
+#define UART0_MSB           HWREG8(UART0_BASE + 0x01)
 
 /* UART1 registers */
-#define UART1_DAT           __REG8(UART1_BASE + 0x00)
-#define UART1_IER           __REG8(UART1_BASE + 0x01)
-#define UART1_IIR           __REG8(UART1_BASE + 0x02)
-#define UART1_FCR           __REG8(UART1_BASE + 0x02)
-#define UART1_LCR           __REG8(UART1_BASE + 0x03)
-#define UART1_MCR           __REG8(UART1_BASE + 0x04)
-#define UART1_LSR           __REG8(UART1_BASE + 0x05)
-#define UART1_MSR           __REG8(UART1_BASE + 0x06)
-
-#define UART1_LSB           __REG8(UART1_BASE + 0x00)
-#define UART1_MSB           __REG8(UART1_BASE + 0x01)
+#define UART1_DAT           HWREG8(UART1_BASE + 0x00)
+#define UART1_IER           HWREG8(UART1_BASE + 0x01)
+#define UART1_IIR           HWREG8(UART1_BASE + 0x02)
+#define UART1_FCR           HWREG8(UART1_BASE + 0x02)
+#define UART1_LCR           HWREG8(UART1_BASE + 0x03)
+#define UART1_MCR           HWREG8(UART1_BASE + 0x04)
+#define UART1_LSR           HWREG8(UART1_BASE + 0x05)
+#define UART1_MSR           HWREG8(UART1_BASE + 0x06)
+
+#define UART1_LSB           HWREG8(UART1_BASE + 0x00)
+#define UART1_MSB           HWREG8(UART1_BASE + 0x01)
 
 /* UART interrupt enable register value */
 #define UARTIER_IME     (1 << 3)

bsp/ls1cdev/drivers/net/synopGMAC_plat.h

@@ -39,14 +39,6 @@
 typedef int bool;
 //typedef unsigned long dma_addr_t;
 
-//sw
-/* write/read MMIO register */
-#define writeb(val, addr) (*(volatile u8*)(addr) = (val))
-#define writew(val, addr) (*(volatile u16*)(addr) = (val))
-#define writel(val, addr) (*(volatile u32*)(addr) = (val))
-#define readb(addr) (*(volatile u8*)(addr))
-#define readw(addr) (*(volatile u16*)(addr))
-#define readl(addr) (*(volatile u32*)(addr))
 
 
 #define KUSEG_ADDR              0x0

bsp/ls1cdev/drivers/selfboot.h

@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#ifndef __RT_LS1C_SELFBOOT_H
+#define __RT_LS1C_SELFBOOT_H
+
+/* SDRAM PARAM macro */
+#define	SD_FREQ	(((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM)
+
+
+/* SDRAM ROW */
+#define	ROW_1K		0x7
+#define	ROW_2K		0x0
+#define	ROW_4K		0x1
+#define	ROW_8K		0x2
+#define	ROW_16K		0x3
+/* SDRAM COL */
+#define	COL_256		0x7
+#define	COL_512		0x0
+#define	COL_1K		0x1
+#define	COL_2K		0x2
+#define	COL_4K		0x3
+/* SDRAM WIDTH */
+#define	WIDTH_8		0x0
+#define	WIDTH_16	0x1
+#define	WIDTH_32	0x2
+
+#define	TRCD		3
+#define	TCL			3
+#define	TRP			3
+#define	TRFC		8
+#define	TRAS		6
+#define	TREF		0x818
+#define	TWR			2
+
+#define	DEF_SEL		0x1
+#define	DEF_SEL_N	0x0
+#define	HANG_UP		0x1
+#define	HANG_UP_N	0x0
+#define	CFG_VALID	0x1
+
+#include "board.h"
+
+#define	SD_PARA0	(0x7f<<25 | \
+					(TRAS << 21) | \
+					(TRFC << 17) | (TRP << 14) | (TCL << 11) | \
+					(TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \
+					SDRAM_ROW)
+
+#define	SD_PARA1	((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
+
+#define	SD_PARA1_EN	((CFG_VALID << 9) | (HANG_UP_N << 8) | \
+					(DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
+
+#define LS1C_CBUS_FIRST1      0xBFE011C4
+#define LS1C_UART2_BASE       0xBFE48000
+
+/* UART register offset*/
+#define LS1C_UART_DAT_OFFSET            (0)
+#define LS1C_UART_IER_OFFSET            (1)
+#define LS1C_UART_IIR_OFFSET            (2)
+#define LS1C_UART_FCR_OFFSET            (2)
+#define LS1C_UART_LCR_OFFSET            (3)
+#define LS1C_UART_MCR_OFFSET            (4)
+#define LS1C_UART_LSR_OFFSET            (5)
+#define LS1C_UART_MSR_OFFSET            (6)
+
+#define LS1C_UART_LSB_OFFSET            (0)
+#define LS1C_UART_MSB_OFFSET            (1)
+
+/* interrupt enable register */
+#define	IER_IRxE	0x1
+#define	IER_ITxE	0x2
+#define	IER_ILE	    0x4
+#define	IER_IME	    0x8
+
+/* interrupt identification register */
+#define	IIR_IMASK	0xf	/* mask */
+#define	IIR_RXTOUT	0xc	/* receive timeout */
+#define	IIR_RLS		0x6	/* receive line status */
+#define	IIR_RXRDY	0x4	/* receive ready */
+#define	IIR_TXRDY	0x2	/* transmit ready */
+#define	IIR_NOPEND	0x1	/* nothing */
+#define	IIR_MLSC	0x0	/* modem status */
+#define	IIR_FIFO_MASK	0xc0	/* set if FIFOs are enabled */
+
+/* fifo control register */
+#define	FIFO_ENABLE	0x01	/* enable fifo */
+#define	FIFO_RCV_RST	0x02	/* reset receive fifo */
+#define	FIFO_XMT_RST	0x04	/* reset transmit fifo */
+#define	FIFO_DMA_MODE	0x08	/* enable dma mode */
+#define	FIFO_TRIGGER_1	0x00	/* trigger at 1 char */
+#define	FIFO_TRIGGER_4	0x40	/* trigger at 4 chars */
+#define	FIFO_TRIGGER_8	0x80	/* trigger at 8 chars */
+#define	FIFO_TRIGGER_14	0xc0	/* trigger at 14 chars */
+
+/* character format control register */
+#define	CFCR_DLAB	0x80	/* divisor latch */
+#define	CFCR_SBREAK	0x40	/* send break */
+#define	CFCR_PZERO	0x30	/* zero parity */
+#define	CFCR_PONE	0x20	/* one parity */
+#define	CFCR_PEVEN	0x10	/* even parity */
+#define	CFCR_PODD	0x00	/* odd parity */
+#define	CFCR_PENAB	0x08	/* parity enable */
+#define	CFCR_STOPB	0x04	/* 2 stop bits */
+#define	CFCR_8BITS	0x03	/* 8 data bits */
+#define	CFCR_7BITS	0x02	/* 7 data bits */
+#define	CFCR_6BITS	0x01	/* 6 data bits */
+#define	CFCR_5BITS	0x00	/* 5 data bits */
+
+/* modem control register */
+#define	MCR_LOOPBACK	0x10	/* loopback */
+#define	MCR_IENABLE	0x08	/* output 2 = int enable */
+#define	MCR_DRS		0x04	/* output 1 = xxx */
+#define	MCR_RTS		0x02	/* enable RTS */
+#define	MCR_DTR		0x01	/* enable DTR */
+
+/* line status register */
+#define	LSR_RCV_FIFO	0x80	/* error in receive fifo */
+#define	LSR_TSRE	0x40	/* transmitter empty */
+#define	LSR_TXRDY	0x20	/* transmitter ready */
+#define	LSR_BI		0x10	/* break detected */
+#define	LSR_FE		0x08	/* framing error */
+#define	LSR_PE		0x04	/* parity error */
+#define	LSR_OE		0x02	/* overrun error */
+#define	LSR_RXRDY	0x01	/* receiver ready */
+#define	LSR_RCV_MASK	0x1f
+
+
+/* External clock frequency */
+#define AHB_CLK                 (24000000)
+#define APB_CLK                 (AHB_CLK)
+
+
+/* START_FREQ register bits */
+#define M_PLL_SHIFT             (8)
+#define M_PLL                   (0xff << M_PLL_SHIFT)
+#define FRAC_N_SHIFT            (16)
+#define FRAC_N                  (0xff << FRAC_N_SHIFT)
+#define DIV_SDRAM_SHIFT         (0)
+#define DIV_SDRAM               (0x3  << DIV_SDRAM_SHIFT)
+
+/* CLK_DIV_PARAM register bits */
+#define DIV_PIX_EN              (0x1  << 31)
+#define DIV_PIX                 (0x7f << 24)
+#define DIV_CAM_EN              (0x1  << 23)
+#define DIV_CAM                 (0x7f << 16)
+#define DIV_CPU_EN              (0x1  << 15)
+#define DIV_CPU                 (0x7f << 8)
+#define DIV_PIX_VALID           (0x1  << 5)
+#define DIV_PIX_SEL             (0x1  << 4)
+#define DIV_CAM_VALID           (0x1  << 3)
+#define DIV_CAM_SEL             (0x1  << 2)
+#define DIV_CPU_VALID           (0x1  << 1)
+#define DIV_CPU_SEL             (0x1  << 0)
+
+#define DIV_PIX_SHIFT           (24)
+#define DIV_CAM_SHIFT           (16)
+#define DIV_CPU_SHIFT           (8)
+
+#endif

bsp/ls1cdev/drivers/selfboot_gcc.S

@@ -0,0 +1,549 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Origin Authors: Loongson Technology Corporation Limited,
+ * caogos <1207280597@qq.com>, Jiaxun Yang <jiaxun.yang@flygoat.com>,
+ *
+ * Also thanks to Liu Shiwei <liushiwei@gmail.com> and other Loongson
+ * Community developers.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#include <rtconfig.h>
+
+#ifdef RT_USING_SELF_BOOT
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include <mips.h>
+#include "selfboot.h"
+#include "ls1c.h"
+#include "cache.h"
+
+/*
+ *   Register usage:
+ *
+ *	s0	link versus load offset, used to relocate absolute adresses.
+ *	s1	free
+ *	s2	memory size
+ *	s3	free
+ *	s4	free
+ *	s5	dbg
+ *	s6	sdCfg
+ *	s7	rasave
+ *	s8	free
+ */
+
+#define tmpsize		s1
+#define msize		s2
+#define bonito		s4
+#define dbg			s5
+#define sdCfg		s6
+
+
+/* Macros */
+#ifdef RT_SELF_BOOT_DEBUG
+#define	PRINTSTR(str) \
+    .pushsection .selfboot_data; .align 4; 98: .asciz str; .popsection; la a0, 98b; bal stringserial; nop
+#else
+#define PRINTSTR(x)
+#endif
+
+#define	DELAY(count)	\
+    li v0, count;	\
+99:			\
+    bnez	v0, 99b;\
+    addiu	v0, -1
+
+.section ".selfboot", "ax"
+.set	noreorder
+.set	mips32
+.globl	_start
+.extern	start
+_start:
+
+/* NMI/Reset vector starts here*/
+  mtc0  zero, CP0_STATUS /* set cp0 status register to zero */
+  mtc0  zero, CP0_CAUSE /* set cp0 cause register to zero */
+
+  li  t0, ST0_BEV /* set exception vector to in flash location */
+  mtc0 t0, CP0_STATUS
+
+  /* Speed up SPI reading */
+  li  t0, 0xbfe80000 /* load SPI0 controler base address to t0 */
+  li  t1, 0x17 /* load "div 4, fast_read + burst_en + memory_en double I/O" to
+                * to t0 for write, not all the flash chips support this mode */
+  sb  t1, 0x4(t0) /* set sfc_param register */
+  li  t1, 0x05
+  sb  t1, 0x6(t0) /* set sfc_timing register */
+
+  bal	locate			/* branch out of vector and get current address to ra */
+    nop
+
+/* in-flash exception vectors start here */
+/* save the exception types to a0 and print out PANIC message in exc_common */
+#define EXC_TLB_REFILL 0x0
+#define EXC_CACHE_ERR	0x1
+#define EXC_GEN	0x2
+#define EXC_INT	0x3
+
+.org 0x200 /* 0xbfc00200 TLB_REFILL exception */
+  li a0, EXC_TLB_REFILL
+  b exc_common
+  nop
+
+.org 0x300 /* 0xbfc00300 Cache Error exception */
+  li a0, EXC_CACHE_ERR
+  b exc_common
+  nop
+
+.org 0x380 /* 0xbfc00300 General exception */
+  li	a0,EXC_GEN
+  b exc_common
+  nop
+
+.org 0x400 /* 0xbfc00400 Interrupt exception */
+  li a0, EXC_INT
+  b exc_common
+  nop
+
+1: /* impossible to reach here, so make a dead loop */
+  b 1b
+  nop
+
+exc_common: /* try one cause and pass to next */
+  li	s1, EXC_TLB_REFILL
+  bne a0, s1, 1f
+  nop
+  PRINTSTR("\r\nEARLY_PANIC: Exception TLB Refill")
+  b print_cause
+  nop
+1:
+  li	s1, EXC_CACHE_ERR
+  bne a0, s1, 1f
+  nop
+  PRINTSTR("\r\nEARLY_PANIC: CACHE Error: ")
+  mfc0 a0, CP0_CACHEERR
+  bal hexserial
+  nop
+  b print_cause
+  nop
+1:
+  li	s1, EXC_GEN
+  bne a0, s1, 1f
+  nop
+  PRINTSTR("\r\nEARLY_PANIC: General Exception")
+  b print_cause
+  nop
+1:
+  li	s1, EXC_INT
+  bne a0, s1, print_cause /* if all exceptions in a0 not reached,
+                          * print_cause directly*/
+  nop
+  PRINTSTR("\r\nEARLY_PANIC: Interrupt Exception")
+print_cause:
+  PRINTSTR("\r\nCAUSE=")
+  mfc0	a0, CP0_CAUSE
+  bal	hexserial
+  nop
+
+  PRINTSTR("\r\nSTATUS=")
+  mfc0	a0, CP0_STATUS
+  bal	hexserial
+  nop
+
+  PRINTSTR("\r\nERRORPC=")
+  mfc0	a0, CP0_ERROREPC
+  bal	hexserial
+  nop
+
+  PRINTSTR("\r\nEPC=")
+  mfc0	a0, CP0_EPC
+  bal	hexserial
+  nop
+
+  PRINTSTR("\r\nBADADDR=")
+  mfc0	a0, CP0_BADVADDR
+  bal	hexserial
+  nop
+
+  PRINTSTR("\r\nEARLY: LOOP! Noting to do")
+1: /* Make a dead loop here, wait user to reset the MCU */
+  b 1b
+  nop
+
+/* locate here, continue the start progress */
+
+locate:
+  /* fix the absolute address by ra */
+  la  s0, start /* s0 = start */
+  subu  s0, ra, s0 /* s0 = ra - s0 */
+  and s0, 0xffff0000 /* s0 = s0 & 0xffff0000 */
+
+  li	t0, 0xbfe78030 /* load PLL/SDRAM freq config register base to t0 */
+  li	t2, (0x80000008 | (PLL_MULT << 8) | (0x3 << 2) | SDRAM_DIV) /* Set PLL
+                                                                  * MULT and PLL DIV */
+  li	t3, (0x00008003 | (CPU_DIV << 8)) /* set CPU DEV */
+
+  li	t1, 0x2
+    sw	t1, 0x4(t0) /* disable CPU_DIV_VALID firstly for adjustment */
+    sw	t2, 0x0(t0) /* write START_FREQ */
+    sw	t3, 0x4(t0) /* write CLK_DIV_PARAM */
+
+/* start to initialize debug uart port */
+  la	v0, LS1C_UART2_BASE /* load UART2 base to v0, only UART2 can be debug port */
+1:
+    li	v1, FIFO_ENABLE|FIFO_RCV_RST|FIFO_XMT_RST|FIFO_TRIGGER_4 /* clear Rx,Tx FIFO
+                                                                * declear 4 bit int trigger */
+    sb	v1, LS1C_UART_FCR_OFFSET(v0) /* write FCR (FIFO control register) */
+    li	v1, CFCR_DLAB /* reach freq div register */
+    sb	v1, LS1C_UART_LCR_OFFSET(v0) /* write LCR (Line control register)*/
+    /* Set UART2 reuse with GPIO36,37*/
+    li		a0, LS1C_CBUS_FIRST1 /* load CBUS_FIRST1 offset to a0 */
+    lw		a1, 0x10(a0) /* load value from CBUS_SECOND1 to a1 */
+    ori		a1, 0x30 /* a1 |= 0x30, GPIO36,37 as secondary function */
+    sw		a1, 0x10(a0) /* write back modified CBUS_SECOND1 from a1 */
+  /* Caculate PLL and bit rate */
+    li		a0, 0xbfe78030 /* load START_FREQ register address to a0 */
+    lw		a1, 0(a0) /* load value from START_FREQ to a1*/
+    srl		a1, 8 /* a1 >>= 8 */
+    andi	a1, 0xff /* a1 &= 0xff, as a1=PLL_MULT */
+    li		a2, APB_CLK /* a2 = APB_CLK = 24Mhz (External Clock Freq) */
+    srl		a2, 2 /* a2 = a2 >> 2 = APB_CLK/4 */
+    multu	a1, a2 /* hilo = a1 * a2 = PLL_MULT * APB_CLK /4 */
+    mflo	v1 /* v1 = lo. put low 32 bit of a1 * a2 to v1 as PLL freq */
+    /* Determine if we need to devide the clock */
+    lw		a1, 4(a0) /* load value frm CLK_DIV_PARAM to a1 */
+    andi	a2, a1, DIV_CPU_SEL /* a2 = a1 & DIV_CPU_SEL, if CPU_SEL=1, devide the clock,
+                            * if CPU_SEL=0, bypass the clock */
+    bnez	a2, 1f /* if (a2 != 0), branch to next tag 1 */
+    nop
+    li		v1, APB_CLK /* v1 = APB_CLK */
+    b		3f
+    nop
+1: /* Determine if the CPU_DIV is valid*/
+    andi	a2, a1, DIV_CPU_EN /* a2 = a1 & DIV_CPU_EN */
+    bnez	a2, 2f /* if (a2 != 0), branch to next tag 2 */
+    nop
+    srl		v1, 1 /* v1 >>= 1, so v1 = APB_CLK/4 * PLL_MULT/2 */
+    b		3f
+    nop
+2: /* caculate CPU freq */
+    andi	a1, DIV_CPU /* a1 &= DIV_CPU */
+    srl		a1, DIV_CPU_SHIFT /* a1 >>= DIV_CPU_SHIFT */
+    divu	v1, a1 /* lo = v1/a1, hi = v1 % a1 */
+    mflo	v1 /* v1 = lo, CPU Freq */
+3:
+    li		a1, (16 * EARLY_DEBUG_BAUD) /* a1 = 16 * BIT RATE */
+    divu	v1, v1, a1 /* v1 = v1 / a1 */
+    srl     v1, 1  /* v1 >>= 1 */
+    sb	v1, LS1C_UART_LSB_OFFSET(v0) /* write 8bit low into LSB */
+    srl	v1, 8 /* v1 >>= 8 */
+    sb	v1, LS1C_UART_MSB_OFFSET(v0) /* write 8bit low into MSB */
+
+    li	v1, CFCR_8BITS /* 8n1, no check */
+    sb	v1, LS1C_UART_LCR_OFFSET(v0) /* write to LCR (Line Control Register) */
+
+#ifdef EARLY_DEBUG_UART_FLOW_CTRL
+    li	v1, MCR_DTR|MCR_RTS /* valid DTR and RTS */
+    sb	v1, LS1C_UART_MCR_OFFSET(v0) /* write to MCR (MODEM Control Register) */
+#endif
+
+    li	v1, 0x0 /* disable all the interruptions */
+    sb	v1, LS1C_UART_IER_OFFSET(v0) /* write to IER (Interruptions Enable Registers) */
+
+    PRINTSTR("\r\INFO: Loongson 1C300 Starting :) \r\n")
+
+  /* disable all GPIOs for conflict functions */
+  li a0,0xbfd00000
+  sw zero,0x10c0(a0)	/* disable GPIO 0-31 */
+  sw zero,0x10c4(a0)	/* disable GPIO 32-63 */
+  sw zero,0x10c8(a0)	/* disable GPIO 64-95 */
+  sw zero,0x10cc(a0)
+
+  li t0, 0xffffffff
+  sw t0, 0x10d0(a0)
+  sw t0, 0x10d4(a0)
+  sw t0, 0x10d8(a0)
+  sw t0, 0x10dc(a0)
+
+  sw t0, 0x10f0(a0)
+  sw t0, 0x10f4(a0)
+  sw t0, 0x10f8(a0)
+  sw t0, 0x10fc(a0)
+
+  PRINTSTR("\r\INFO: All GPIOs are disabled\r\n")
+
+  /* SDRAM initialize starts here */
+
+  li msize, MEM_SIZE
+
+#ifdef EJTAG_SEL_AS_SDRAM_CS1
+  li		a0, 0xbfd011c0
+  lw		a1, 0x40(a0)
+  ori	a1, 0x01
+  sw		a1, 0x40(a0)
+  PRINTSTR("\r\INFO: EJTAG_SEL PIN as SDRAM_CS1\r\n")
+#endif
+
+/*
+* recommanded by user manual, we should write SD_CONFIG[31:0] first, then
+* write SD_CONFIG[63:32]. Repeat writing for three times, valid the config in
+* the last time.
+*/
+
+/* write first time */
+li  	t1, 0xbfd00410 /* load SD_CONFIG[31:0] address to t1 */
+li		a1, SD_PARA0 /* get the memory config from macro SD_PARA0 */
+sw		a1, 0x0(t1) /* write to SD_CONFIG[31:0] */
+li		a1, SD_PARA1
+sw		a1, 0x4(t1) /* write to SD_CONFIG[63:32] with offset */
+PRINTSTR("\r\INFO: SDRAM Config Pass1\r\n")
+
+/* write second time,the same */
+li		a1, SD_PARA0
+sw		a1, 0x0(t1)
+li		a1, SD_PARA1
+sw		a1, 0x4(t1)
+PRINTSTR("\r\INFO: SDRAM Config Pass2\r\n")
+
+/* write third time, enable controller this time */
+li		a1, SD_PARA0
+sw		a1, 0x0(t1)
+li		a1, SD_PARA1_EN /* enable it */
+sw		a1, 0x4(t1)
+PRINTSTR("\r\INFO: SDRAM initialize compeleted\r\n")
+
+
+/* initialize cache */
+bal     cache_init /* branch to cache_init */
+nop
+
+/* enable cache */
+mfc0   a0, CP0_CONFIG /* load cp0 config to a0 */
+and    a0, a0, ~((1<<12) | 7) /* a0 = a0 & ~((1<<12) | 7) */
+or     a0, a0, 2 /* a0 |= 2 */
+mtc0   a0, CP0_CONFIG /* write back to CP0 config */
+
+/*
+* relocate: copy selfboot code to memory in kseg0, fix PC and jump to kseg0.
+* in order to speed up the copy progress, we will execute copy code in kseg0
+*/
+
+PRINTSTR("\r\INFO: Relocating")
+la		t0, text_copy_start /* load the adress of start tag to t0 */
+move		t2, t0
+addu		t0, s0 /* correct t0 address in rom by s0 */
+la		t1, text_copy_end
+
+selfboot_copy_loop:
+lw		v0, (t0) /* copy from memory address in t0 to register v0  */
+sw		v0, (t2) /* write data in register v0 to memory address t0 */
+addiu		t0, 0x4 /* t0 moves forward 4 bytes */
+addiu		t2, 0x4 /* t2 moves forward 4 bytes */
+ble		t2, t1, selfboot_copy_loop /* if t1 <= t2 loop to continue the copy */
+nop
+
+la		t0, text_copy_start /* load start address to t0 */
+jr		t0 /* jump to 122 in kseg0 to start copy code progress */
+nop
+
+text_copy_start:
+/* Copy code to memory*/
+la		a0, start /* load address of start symbol to a0  */
+addu		a1, a0, s0 /* correct a0 to address in flash */
+la		a2, _edata /* load symbol _edata address to a2 */
+subu	t1, a2, a0 /* t1 = a2 - a0, the space of text area */
+
+move	t0, a0 /* the start address in ram */
+move	t1, a1 /* the start address in rom */
+move	t2, a2 /* the end address in rom (symbol _edata) */
+
+/* copy text section */
+1:
+and	t3, t0, 0x0000ffff /* t3 = t0 & 0x0000ffff, get low 16 bit */
+bnez	t3, 2f /* if t3 != 0, jump to next tag 2 */
+nop
+2:
+lw		t3, 0(t1) /* copy 4 bit from memory address t1 to register t3 */
+nop
+sw		t3, 0(t0) /* copy 4 bit from register t3 to memory address in t0 */
+addu	t0, 4 /* t0 move forward 4 bytes */
+addu	t1, 4 /* t1 move forward 4 bytes */
+bne	t2, t0, 1b /* if t2 != t0, branch to last tag 1 to continue copy */
+nop
+/* copy text section done. */
+
+move	a0, msize  /* a0 = msize, will be passed to main */
+srl	a0, 20 /* a0 >>= 20, convert to unit in MB */
+
+/* execute main */
+la		v0, _rtthread_entry /* load address of function main to v0 */
+jalr	v0 /* call address in v0, congrats! all low_level things done!
+          * switch brain out of assembly */
+nop
+text_copy_end: /* end of self-copy in memory */
+
+loop: /* impossible to reach here, make a dead loop */
+b	loop
+nop
+
+/* functions here */
+
+LEAF(stringserial) /* print out the string in address passed in a0  */
+    nop
+    move	a2, ra  /* save the return address to a2 */
+    addu	a1, a0, s0 /* correct the address in ROM */
+    lbu	a0, 0(a1) /* read the first byte in memory address a1 to a0 */
+1:
+    beqz	a0, 2f /* if a0 == 0, jump to next tag 2, empty char */
+    nop
+    bal	tgt_putchar /* print a char */
+    addiu	a1, 1 /* a1 += 1 move forward to next byte */
+    b	1b /* branch to the last tag 1, continue */
+    lbu	a0, 0(a1) /* load the next bit from address a1 to a0, in delay solt,
+                * will be execuated before branch */
+2:
+    j	a2 /* return */
+    nop
+END(stringserial)
+
+
+LEAF(hexserial) /* print out single hex char passed in register a0 */
+    nop
+    move	a2, ra /* move return address from ra to a2  */
+    move	a1, a0 /* move hex char from register a0 to a1 */
+    li	a3, 7 /* load 7 to a3 */
+1:
+    rol	a0, a1, 4 /* rotate left ward shift for 4 bit in a1 to a0 */
+    move	a1, a0
+    and	a0, 0xf
+    la	v0, hexchar
+
+.pushsection .selfboot_data
+.align	4
+hexchar:
+        .ascii	"0123456789abcdef"
+.popsection
+.align	4
+
+    addu	v0, s0
+    addu	v0, a0
+    bal	tgt_putchar
+    lbu	a0, 0(v0)
+
+    bnez	a3, 1b
+    addu	a3, -1
+
+    j	a2
+    nop
+END(hexserial)
+
+LEAF(tgt_putchar) /* print out a char in a0 */
+    la	v0, LS1C_UART2_BASE /* load UART register address to a0 */
+    lbu	v1, LS1C_UART_LSR_OFFSET(v0) /* load value from LSR to v0 */
+1:
+    and	v1, LSR_TXRDY /* v1 &= LSR_TXRDY determine wether we can send by TFE bit */
+    beqz	v1, 1b /* if (v1 == 0) jump to last 1 tag, waiting until TFE is 1 */
+    lbu	v1, LS1C_UART_LSR_OFFSET(v0) /* load value from LSR to v0 again, in delay solt */
+
+    sb	a0, LS1C_UART_DAT_OFFSET(v0) /* write a0 into DAT, send out */
+    j	ra /*  */
+    nop
+END(tgt_putchar)
+
+LEAF(CPU_SetSR) /* modify SR value, arg 1 = set bits, arg 2 = clear bits. */
+    mfc0    v0, CP0_STATUS
+    not v1, a1
+    and v1, v0
+    or  v1, a0
+    mtc0    v1, CP0_STATUS
+    nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+    j   ra
+    nop
+END(CPU_SetSR)
+
+cache_init:
+    move t1, ra
+####part 2####
+cache_detect_4way:
+    mfc0	t4, CP0_CONFIG,1 /* move CP0 CONFIG to t4 */
+    lui		v0, 0x7 /* v0 = 0x7 << 16 */
+    and		v0, t4, v0 /* v0 = t4 & v0 */
+    srl		t3, v0, 16 /* t3 = v0 >> 16  Icache组相联数 IA */
+
+    li		t5, 0x800 		//32*64
+    srl		v1, t4,22		//v1 = t4 >> 22
+    andi	v1, 7			//Icache每路的组数 64x2^S IS
+    sll		t5, v1			//InstCacheSetSize
+    sll		t5, t3			//t5 InstCacheSize
+
+
+    andi	v0, t4, 0x0380
+    srl		t7, v0, 7		//DA
+
+    li		t6, 0x800       // 32*64
+    srl		v1, t4,13
+    andi	v1, 7			//DS
+    sll		t6, v1          // DataCacheSetSize
+    sll		t6, t7          // t5 DataCacheSize
+
+####part 3####
+    lui		a0, 0x8000			//a0 = 0x8000 << 16
+    addu	a1, $0, t5
+    addu	a2, $0, t6
+cache_init_d2way:
+/* a0=0x80000000, a1=icache_size, a2=dcache_size */
+/* a3, v0 and v1 used as local registers */
+    mtc0	$0, CP0_TAGHI
+    addu	v0, $0, a0 /* v0 = 0 + a0 */
+    addu	v1, a0, a2 /* v1 = a0 + a2 */
+1:	slt		a3, v0, v1 /* a3 = v0 < v1 ? 1 : 0 */
+    beq		a3, $0, 1f /* if (a3 == 0) goto 1f */
+    nop
+    mtc0	$0, CP0_TAGLO
+    cache	Index_Store_Tag_D, 0x0(v0) /* 1 way */
+4:	beq		$0, $0, 1b
+    addiu	v0, v0, 0x20
+1:
+cache_flush_i2way:
+    addu	v0, $0, a0
+    addu	v1, a0, a1
+1:
+    slt		a3, v0, v1
+    beq		a3, $0, 1f
+    nop
+    cache	Index_Invalidate_I, 0x0(v0) /* 1 way */
+4:
+    beq		$0, $0, 1b
+    addiu	v0, v0, 0x20
+1:
+cache_flush_d2way:
+    addu	v0, $0, a0
+    addu	v1, a0, a2
+1:	slt		a3, v0, v1
+    beq		a3, $0, 1f
+    nop
+    cache	Index_Writeback_Inv_D, 0x0(v0) /* 1 way */
+4:	beq		$0, $0, 1b
+    addiu	v0, v0, 0x20
+
+1:
+cache_init_finish:
+    jr	t1
+    nop
+#endif

bsp/ls1cdev/ls1c_ram.lds

@@ -12,6 +12,7 @@
  * 2010-05-17     swkyer       first version
  * 2010-09-04     bernard      move the beginning entry to 0x80200000
  * 2018-05-12     zhuangwei    use -Ttext
+ * 2019-12-04     Jiaxun Yang  Adapt new memory layout
  */
 
 OUTPUT_ARCH(mips)
@@ -20,13 +21,19 @@ GROUP(-lgcc -lc)
 ENTRY(_start)
 SECTIONS
 {
-    . = 0x80000000 ;
-
     . = ALIGN(4);
     .text : 
     {
-		start = ABSOLUTE(.);
-		*(.start);
+	start = ABSOLUTE(.);
+	 *(.selfboot);
+	 *(.selfboot_data);
+	. = ALIGN(4);
+	__selfboot_end = .;
+	. = ALIGN(0x1000);
+	__ebase_entry = .;
+     	KEEP(*(.exc_vectors))
+     	__ebase_end = .;
+	 *(.start);
          *(.text)
          *(.text.*)
          *(.rodata)
@@ -74,6 +81,15 @@ SECTIONS
          *(.sdata)
          *(.sdata.*)
     }
+    _edata = .;
+
+    .stack :
+    {
+        . = ALIGN(8);
+        _system_stack_start = .;
+        . = . + 0x400; /* 1kb system stack */
+        _system_stack = .;
+    }
 
     .sbss : 
     {

bsp/ls1cdev/rtconfig.h

@@ -8,28 +8,16 @@
 
 #define RT_NAME_MAX 10
 #define RT_ALIGN_SIZE 8
-/* RT_THREAD_PRIORITY_8 is not set */
 #define RT_THREAD_PRIORITY_32
-/* RT_THREAD_PRIORITY_256 is not set */
 #define RT_THREAD_PRIORITY_MAX 32
 #define RT_TICK_PER_SECOND 1000
 #define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
 #define RT_IDLE_HOOK_LIST_SIZE 4
 #define IDLE_THREAD_STACK_SIZE 1024
-/* RT_USING_TIMER_SOFT is not set */
 #define RT_DEBUG
 #define RT_DEBUG_COLOR
-/* RT_DEBUG_INIT_CONFIG is not set */
-/* RT_DEBUG_THREAD_CONFIG is not set */
-/* RT_DEBUG_SCHEDULER_CONFIG is not set */
-/* RT_DEBUG_IPC_CONFIG is not set */
-/* RT_DEBUG_TIMER_CONFIG is not set */
-/* RT_DEBUG_IRQ_CONFIG is not set */
-/* RT_DEBUG_MEM_CONFIG is not set */
-/* RT_DEBUG_SLAB_CONFIG is not set */
-/* RT_DEBUG_MEMHEAP_CONFIG is not set */
-/* RT_DEBUG_MODULE_CONFIG is not set */
 
 /* Inter-Thread communication */
 
@@ -38,27 +26,22 @@
 #define RT_USING_EVENT
 #define RT_USING_MAILBOX
 #define RT_USING_MESSAGEQUEUE
-/* RT_USING_SIGNALS is not set */
 
 /* Memory Management */
 
 #define RT_USING_MEMPOOL
 #define RT_USING_MEMHEAP
-/* RT_USING_NOHEAP is not set */
 #define RT_USING_SMALL_MEM
-/* RT_USING_SLAB is not set */
-/* RT_USING_MEMHEAP_AS_HEAP is not set */
-/* RT_USING_MEMTRACE is not set */
 #define RT_USING_HEAP
 
 /* Kernel Device Object */
 
 #define RT_USING_DEVICE
-/* RT_USING_DEVICE_OPS is not set */
 #define RT_USING_INTERRUPT_INFO
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart2"
+#define RT_VER_NUM 0x40002
 
 /* RT-Thread Components */
 
@@ -69,7 +52,6 @@
 
 /* C++ features */
 
-/* RT_USING_CPLUSPLUS is not set */
 
 /* Command shell */
 
@@ -79,14 +61,11 @@
 #define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
 #define FINSH_USING_DESCRIPTION
-/* FINSH_ECHO_DISABLE_DEFAULT is not set */
 #define FINSH_THREAD_PRIORITY 20
 #define FINSH_THREAD_STACK_SIZE 4096
 #define FINSH_CMD_SIZE 80
-/* FINSH_USING_AUTH is not set */
 #define FINSH_USING_MSH
 #define FINSH_USING_MSH_DEFAULT
-/* FINSH_USING_MSH_ONLY is not set */
 #define FINSH_ARG_MAX 10
 
 /* Device virtual file system */
@@ -96,29 +75,6 @@
 #define DFS_FILESYSTEMS_MAX 2
 #define DFS_FILESYSTEM_TYPES_MAX 2
 #define DFS_FD_MAX 4
-/* RT_USING_DFS_MNTTABLE is not set */
-#define RT_USING_DFS_ELMFAT
-
-/* elm-chan's FatFs, Generic FAT Filesystem Module */
-
-#define RT_DFS_ELM_CODE_PAGE 936
-#define RT_DFS_ELM_WORD_ACCESS
-#define RT_DFS_ELM_USE_LFN_0
-/* RT_DFS_ELM_USE_LFN_1 is not set */
-/* RT_DFS_ELM_USE_LFN_2 is not set */
-/* RT_DFS_ELM_USE_LFN_3 is not set */
-#define RT_DFS_ELM_USE_LFN 0
-#define RT_DFS_ELM_MAX_LFN 64
-#define RT_DFS_ELM_DRIVES 2
-#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
-/* RT_DFS_ELM_USE_ERASE is not set */
-#define RT_DFS_ELM_REENTRANT
-/* RT_USING_DFS_DEVFS is not set */
-/* RT_USING_DFS_ROMFS is not set */
-/* RT_USING_DFS_RAMFS is not set */
-/* RT_USING_DFS_UFFS is not set */
-/* RT_USING_DFS_JFFS2 is not set */
-/* RT_USING_DFS_NFS is not set */
 
 /* Device Drivers */
 
@@ -126,200 +82,95 @@
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
 #define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_CAN
-/* RT_CAN_USING_HDR is not set */
-/* RT_USING_HWTIMER is not set */
-/* RT_USING_CPUTIME is not set */
 #define RT_USING_I2C
 #define RT_USING_I2C_BITOPS
 #define RT_USING_PIN
-/* RT_USING_PWM is not set */
-/* RT_USING_MTD_NOR is not set */
-/* RT_USING_MTD_NAND is not set */
-/* RT_USING_MTD is not set */
-/* RT_USING_PM is not set */
-/* RT_USING_RTC is not set */
-/* RT_USING_SDIO is not set */
 #define RT_USING_SPI
 #define RT_USING_SPI_MSD
-/* RT_USING_SFUD is not set */
-/* RT_USING_W25QXX is not set */
-/* RT_USING_GD is not set */
-/* RT_USING_ENC28J60 is not set */
-/* RT_USING_SPI_WIFI is not set */
-/* RT_USING_WDT is not set */
-/* RT_USING_AUDIO is not set */
-
-/* Using WiFi */
-
-/* RT_USING_WIFI is not set */
 
 /* Using USB */
 
-/* RT_USING_USB_HOST is not set */
-/* RT_USING_USB_DEVICE is not set */
 
 /* POSIX layer and C standard library */
 
 #define RT_USING_LIBC
 #define RT_USING_PTHREADS
-/* RT_USING_POSIX is not set */
-/* RT_USING_MODULE is not set */
+#define PTHREAD_NUM_MAX 8
 
 /* Network */
 
 /* Socket abstraction layer */
 
-/* RT_USING_SAL is not set */
+
+/* Network interface device */
+
 
 /* light weight TCP/IP stack */
 
-#define RT_USING_LWIP
-#define RT_USING_LWIP141
-/* RT_USING_LWIP202 is not set */
-/* RT_USING_LWIP210 is not set */
-#define RT_LWIP_IGMP
-#define RT_LWIP_ICMP
-/* RT_LWIP_SNMP is not set */
-#define RT_LWIP_DNS
-#define RT_LWIP_DHCP
-#define IP_SOF_BROADCAST 1
-#define IP_SOF_BROADCAST_RECV 1
-
-/* Static IPv4 Address */
-
-#define RT_LWIP_IPADDR "192.168.1.254"
-#define RT_LWIP_GWADDR "192.168.1.1"
-#define RT_LWIP_MSKADDR "255.255.255.0"
-#define RT_LWIP_UDP
-#define RT_LWIP_TCP
-/* RT_LWIP_RAW is not set */
-/* RT_LWIP_PPP is not set */
-#define RT_MEMP_NUM_NETCONN 8
-#define RT_LWIP_PBUF_NUM 4
-#define RT_LWIP_RAW_PCB_NUM 4
-#define RT_LWIP_UDP_PCB_NUM 4
-#define RT_LWIP_TCP_PCB_NUM 3
-#define RT_LWIP_TCP_SEG_NUM 40
-#define RT_LWIP_TCP_SND_BUF 4096
-#define RT_LWIP_TCP_WND 2048
-#define RT_LWIP_TCPTHREAD_PRIORITY 12
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
-#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
-/* LWIP_NO_RX_THREAD is not set */
-/* LWIP_NO_TX_THREAD is not set */
-#define RT_LWIP_ETHTHREAD_PRIORITY 14
-#define RT_LWIP_ETHTHREAD_STACKSIZE 512
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
-/* RT_LWIP_REASSEMBLY_FRAG is not set */
-#define LWIP_NETIF_STATUS_CALLBACK 1
-#define SO_REUSE 1
-#define LWIP_SO_RCVTIMEO 1
-#define LWIP_SO_SNDTIMEO 1
-#define LWIP_SO_RCVBUF 1
-/* RT_LWIP_NETIF_LOOPBACK is not set */
-#define LWIP_NETIF_LOOPBACK 0
-/* RT_LWIP_STATS is not set */
-/* RT_LWIP_DEBUG is not set */
-
-/* Modbus master and slave stack */
-
-/* RT_USING_MODBUS is not set */
 
 /* AT commands */
 
-/* RT_USING_AT is not set */
-/* LWIP_USING_DHCPD is not set */
 
 /* VBUS(Virtual Software BUS) */
 
-/* RT_USING_VBUS is not set */
 
 /* Utilities */
 
-/* RT_USING_LOGTRACE is not set */
-/* RT_USING_RYM is not set */
-/* RT_USING_ULOG is not set */
 
-/* RT-Thread online packages */
-
-/* system packages */
+/* RT-Thread MIPS CPU */
 
-/* RT-Thread GUI Engine */
 
-/* PKG_USING_GUIENGINE is not set */
-/* PKG_USING_LWEXT4 is not set */
-/* PKG_USING_PARTITION is not set */
-/* PKG_USING_SQLITE is not set */
-/* PKG_USING_RTI is not set */
+/* RT-Thread online packages */
 
 /* IoT - internet of things */
 
-/* PKG_USING_PAHOMQTT is not set */
-/* PKG_USING_WEBCLIENT is not set */
-/* PKG_USING_MONGOOSE is not set */
-/* PKG_USING_WEBTERMINAL is not set */
-/* PKG_USING_CJSON is not set */
-/* PKG_USING_LJSON is not set */
-/* PKG_USING_EZXML is not set */
-/* PKG_USING_NANOPB is not set */
-/* PKG_USING_GAGENT_CLOUD is not set */
 
 /* Wi-Fi */
 
 /* Marvell WiFi */
 
-/* PKG_USING_WLANMARVELL is not set */
 
 /* Wiced WiFi */
 
-/* PKG_USING_WLAN_WICED is not set */
-/* PKG_USING_COAP is not set */
-/* PKG_USING_NOPOLL is not set */
-/* PKG_USING_NETUTILS is not set */
+
+/* IoT Cloud */
+
 
 /* security packages */
 
-/* PKG_USING_MBEDTLS is not set */
-/* PKG_USING_libsodium is not set */
-/* PKG_USING_TINYCRYPT is not set */
 
 /* language packages */
 
-/* PKG_USING_JERRYSCRIPT is not set */
-/* PKG_USING_MICROPYTHON is not set */
 
 /* multimedia packages */
 
-/* PKG_USING_OPENMV is not set */
 
 /* tools packages */
 
-/* PKG_USING_CMBACKTRACE is not set */
-/* PKG_USING_EASYLOGGER is not set */
-/* PKG_USING_SYSTEMVIEW is not set */
-/* PKG_USING_IPERF is not set */
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
 
 /* miscellaneous packages */
 
-/* PKG_USING_FASTLZ is not set */
-/* PKG_USING_MINILZO is not set */
-/* PKG_USING_QUICKLZ is not set */
-/* PKG_USING_MULTIBUTTON is not set */
 
-/* example package: hello */
+/* samples: kernel and components samples */
 
-/* PKG_USING_HELLO is not set */
-/* RT_USING_SELF_BOOT is not set */
+#define SOC_1C300
+#define RT_LS1C_BAICAIBOARD
+#define RT_USING_SELF_BOOT
+#define RT_SELF_BOOT_DEBUG
 #define RT_USING_UART2
+#define RT_USING_UART1
 #define RT_UART_RX_BUFFER_SIZE 64
 #define RT_USING_GMAC_INT_MODE
-/* RT_USING_FPU is not set */
-/* RT_USING_SPI0 is not set */
-/* RT_USING_SPI1 is not set */
 #define RT_USING_I2C1
 #define RT_USING_I2C2
-#define USING_BXCAN0
-#define USING_BXCAN1
+#define NO_TOUCH
 
 #endif

bsp/ls1cdev/rtconfig.py

@@ -2,7 +2,7 @@ import os
 
 # CPU options
 ARCH='mips'
-CPU ='loongson_1c'
+CPU ='gs232'
 
 # toolchains options
 CROSS_TOOL  = 'gcc'
@@ -12,8 +12,8 @@ if os.getenv('RTT_CC'):
 
 if  CROSS_TOOL == 'gcc':
 	PLATFORM    = 'gcc'
-#	EXEC_PATH   = "/opt/mips-2015.05/bin"
-	EXEC_PATH   = r'D:\mgc\embedded\codebench\bin'
+	EXEC_PATH   = "/opt/mips-2016.05/bin"
+#	EXEC_PATH   = r'D:\mgc\embedded\codebench\bin'
 else:
     print('================ERROR===========================')
     print('Not support %s yet!' % CROSS_TOOL)
@@ -41,7 +41,7 @@ READELF = PREFIX + 'readelf'
 
 DEVICE = ' -mips32 -msoft-float -mfp32'
 CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
-AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp -DSYSTEM_STACK=0x80003fe8'
+AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
 LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls1c_ram.lds'
 
 CPATH = ''

bsp/mipssim/Kconfig

@@ -0,0 +1,31 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+# you can change the RTT_ROOT default "../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$RTT_DIR/libcpu/mips/common/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config MIPSSIM
+    bool
+    select ARCH_MIPS
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select RT_USING_DEVICE
+    default y

bsp/mipssim/README.md

@@ -0,0 +1,15 @@
+MIPSSIM 板级支持包
+
+
+---
+
+## 1. 简介
+
+本BSP用于在MIPSSIM或QEMU的MIPSSIM Machine模拟器中运行RT-Thread。
+使用mips-sde-elf工具链编译。
+在QEMU中使用如下命令运行：
+```
+qemu-system-mipsel -M mipssim -cpu P5600 -nographic -kernel ./rtthread.elf
+```
+
+MIPSSIM拥有一个8250串口和一个MIPSNET网卡外设，本BSP目前仅实现了串口。

bsp/mipssim/SConscript

@@ -0,0 +1,12 @@
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/mipssim/SConstruct

@@ -0,0 +1,38 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+rtconfig.AFLAGS += ' -I' + str(Dir('#'))
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+   
+env.Replace(LINKFLAGS = rtconfig.LFLAGS)
+
+if GetDepend('RT_USING_FPU'):
+    env['CCFLAGS']   = env['CCFLAGS'].replace('-msoft-float', '-mhard-float')
+    env['ASFLAGS']   = env['ASFLAGS'].replace('-msoft-float', '-mhard-float')
+    env['CXXFLAGS']  = env['CXXFLAGS'].replace('-msoft-float', '-mhard-float')
+    env['LINKFLAGS'] = env['LINKFLAGS'].replace('-msoft-float', '-mhard-float')
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/mipssim/applications/SConscript

@@ -0,0 +1,8 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+
+group = DefineGroup('Applications', src, depend = [''])
+
+Return('group')

bsp/mipssim/applications/main.c

@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-05-10     zhuangwei    first version
+ */
+
+#include <rtthread.h>
+
+int main(int argc, char** argv)
+{   
+
+    return 0;
+}

bsp/mipssim/drivers/SConscript

@@ -0,0 +1,10 @@
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/mipssim/drivers/board.c

@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+/**
+ * @addtogroup mipssim
+ */
+
+/*@{*/
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "mips_regs.h"
+#include "exception.h"
+#include "drv_uart.h"
+
+#define CPU_HZ	(100 * 1000 * 1000)
+#define RT_HW_HEAP_END	(0x80000000 + 64 * 1024 * 1024)
+
+extern unsigned char __bss_end;
+
+/**
+ * this function will reset CPU
+ *
+ */
+void rt_hw_cpu_reset(void)
+{
+    rt_kprintf("reboot system...\n");
+    while (1);
+}
+
+/**
+ * this function will shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown(void)
+{
+    rt_kprintf("shutdown...\n");
+
+    while (1);
+}
+
+
+/**
+ * This is the timer interrupt service routine.
+ */
+void rt_hw_timer_handler(void)
+{
+    unsigned int count;
+
+    count = read_c0_compare();
+    write_c0_compare(count);
+    write_c0_count(0);
+    /* increase a OS tick */
+    rt_tick_increase();
+}
+
+/**
+ * This function will initial OS timer
+ */
+void rt_hw_timer_init(void)
+{
+    write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
+    write_c0_count(0);
+    mips_unmask_cpu_irq(7);
+}
+
+/**
+ * Board level initialization
+ */
+void rt_hw_board_init(void)
+{
+    rt_hw_exception_init();
+
+    /* init hardware interrupt */
+    rt_hw_interrupt_init();
+
+    #ifdef RT_USING_FPU
+    /* init hardware fpu */
+    rt_hw_fpu_init();
+    #endif
+
+#ifdef RT_USING_SERIAL
+    /* init hardware UART device */
+    rt_hw_uart_init();
+    /* set console device */
+    rt_console_set_device("uart");
+#endif
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
+#endif
+
+    /* init operating system timer */
+    rt_hw_timer_init();
+
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+    rt_kprintf("Current SR: 0x%08x\n", read_c0_status());
+
+}
+
+/*@}*/

bsp/mipssim/drivers/cpuinit_gcc.S

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include <mips.h>
+
+    .section ".text", "ax"
+    .set noreorder
+
+    .globl  rt_cpu_early_init
+rt_cpu_early_init:
+     mfc0	t0, CP0_CONFIG
+     ori	t0, 3
+     mtc0	t0, CP0_CONFIG
+     ehb
+     jr	ra

bsp/mipssim/drivers/drv_uart.c

@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+/**
+ * @addtogroup mipssim
+ */
+
+/*@{*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include "drv_uart.h"
+
+#define TRUE 1
+#define FALSE 0
+
+struct rt_uart_mipssim
+{
+    void *base;
+    rt_uint32_t IRQ;
+};
+
+static rt_err_t mipssim_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct rt_uart_mipssim *uart_dev = RT_NULL;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data;
+
+    UART_IER(uart_dev->base) = 0; /* clear interrupt */
+    UART_FCR(uart_dev->base) = 0xc1; /* reset UART Rx/Tx */
+    /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
+    UART_LCR(uart_dev->base) = 0x3;
+    UART_MCR(uart_dev->base) = 0x3;
+    UART_LSR(uart_dev->base) = 0x60;
+    UART_MSR(uart_dev->base) = 0xb0;
+
+    return RT_EOK;
+}
+
+static rt_err_t mipssim_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct rt_uart_mipssim *uart_dev = RT_NULL;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT: /* Disable RX IRQ */
+        rt_hw_interrupt_mask(uart_dev->IRQ);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT: /* Enable RX IRQ */
+        rt_hw_interrupt_umask(uart_dev->IRQ);
+        UART_IER(uart_dev->base) |= (IER_IRxE|IER_ILE);
+        break;
+
+    default:
+        break;
+    }
+
+    return RT_EOK;
+
+}
+
+static rt_bool_t uart_is_transmit_empty(struct rt_uart_mipssim *uart_dev)
+{
+    unsigned char status = UART_LSR(uart_dev->base);
+
+    if (status & (UARTLSR_TE | UARTLSR_TFE))
+    {
+        return TRUE;
+    }
+    else
+    {
+        return FALSE;
+    }
+}
+
+static int mipssim_uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct rt_uart_mipssim *uart_dev = RT_NULL;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data;
+
+    while (FALSE == uart_is_transmit_empty(uart_dev))
+        ;
+
+    UART_DAT(uart_dev->base) = c;
+
+    return 1;
+}
+
+static int mipssim_uart_getc(struct rt_serial_device *serial)
+{
+    struct rt_uart_mipssim *uart_dev = RT_NULL;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data;
+
+    if (LSR_RXRDY & UART_LSR(uart_dev->base))
+    {
+        return UART_DAT(uart_dev->base);
+    }
+
+    return -1;
+}
+
+/* UART interrupt handler */
+static void uart_irq_handler(int vector, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device *)param;
+    struct rt_uart_mipssim *uart_dev = RT_NULL;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart_dev = (struct rt_uart_mipssim *)serial->parent.user_data;
+    unsigned char iir = UART_IIR(uart_dev->base);
+
+    /* Find out interrupt reason */
+    if ((IIR_RXTOUT & iir) || (IIR_RXRDY & iir))
+    {
+        rt_interrupt_enter();
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+        rt_interrupt_leave();
+    }
+
+}
+
+static const struct rt_uart_ops mipssim_uart_ops =
+{
+    mipssim_uart_configure,
+    mipssim_uart_control,
+    mipssim_uart_putc,
+    mipssim_uart_getc,
+};
+
+struct rt_uart_mipssim uart_dev0 =
+{
+    (void *)UART0_BASE,
+    4,
+};
+struct rt_serial_device serial;
+
+
+void rt_hw_uart_init(void)
+{
+    struct rt_uart_mipssim *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    uart = &uart_dev0;
+
+    serial.ops    = &mipssim_uart_ops;
+    serial.config = config;
+
+    rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial, "UART");
+
+    /* register UART device */
+    rt_hw_serial_register(&serial,
+                          "uart",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+}
+/*@}*/

bsp/mipssim/drivers/drv_uart.h

@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#ifndef _MIPSSIM_DRV_UART_H__
+#define _MIPSSIM_DRV_UART_H__
+
+#include "mipssim.h"
+#include <rthw.h>
+
+/* UART registers */
+#define UART_DAT(base)		HWREG8(base + 0x00)
+#define UART_IER(base)		HWREG8(base + 0x01)
+#define UART_IIR(base)		HWREG8(base + 0x02)
+#define UART_FCR(base)		HWREG8(base + 0x02)
+#define UART_LCR(base)		HWREG8(base + 0x03)
+#define UART_MCR(base)		HWREG8(base + 0x04)
+#define UART_LSR(base)		HWREG8(base + 0x05)
+#define UART_MSR(base)		HWREG8(base + 0x06)
+
+#define UART_LSB(base)		HWREG8(base + 0x00)
+#define UART_MSB(base)		HWREG8(base + 0x01)
+
+/* interrupt enable register */
+#define	IER_IRxE	0x1	/* 接收有效数据中断使能 */
+#define	IER_ITxE	0x2	/* 传输保存寄存器为空中断使能 */
+#define	IER_ILE	    0x4	/* 接收器线路状态中断使能 */
+#define	IER_IME	    0x8	/* Modem状态中断使能 */
+
+/* interrupt identification register */
+#define	IIR_IMASK	0xf	/* mask */
+#define	IIR_RXTOUT	0xc	/* receive timeout */
+#define	IIR_RLS		0x6	/* receive line status */
+#define	IIR_RXRDY	0x4	/* receive ready */
+#define	IIR_TXRDY	0x2	/* transmit ready */
+#define	IIR_NOPEND	0x1	/* nothing */
+#define	IIR_MLSC	0x0	/* modem status */
+#define	IIR_FIFO_MASK	0xc0	/* set if FIFOs are enabled */
+
+/* fifo control register */
+#define	FIFO_ENABLE	    0x01	/* enable fifo */
+#define	FIFO_RCV_RST	0x02	/* reset receive fifo */
+#define	FIFO_XMT_RST	0x04	/* reset transmit fifo */
+#define	FIFO_DMA_MODE	0x08	/* enable dma mode */
+#define	FIFO_TRIGGER_1	0x00	/* trigger at 1 char */
+#define	FIFO_TRIGGER_4	0x40	/* trigger at 4 chars */
+#define	FIFO_TRIGGER_8	0x80	/* trigger at 8 chars */
+#define	FIFO_TRIGGER_14	0xc0	/* trigger at 14 chars */
+
+// 线路控制寄存器
+/* character format control register */
+#define	CFCR_DLAB	0x80	/* divisor latch */
+#define	CFCR_SBREAK	0x40	/* send break */
+#define	CFCR_PZERO	0x30	/* zero parity */
+#define	CFCR_PONE	0x20	/* one parity */
+#define	CFCR_PEVEN	0x10	/* even parity */
+#define	CFCR_PODD	0x00	/* odd parity */
+#define	CFCR_PENAB	0x08	/* parity enable */
+#define	CFCR_STOPB	0x04	/* 2 stop bits */
+#define	CFCR_8BITS	0x03	/* 8 data bits */
+#define	CFCR_7BITS	0x02	/* 7 data bits */
+#define	CFCR_6BITS	0x01	/* 6 data bits */
+#define	CFCR_5BITS	0x00	/* 5 data bits */
+
+/* modem control register */
+#define	MCR_LOOPBACK	0x10	/* loopback */
+#define	MCR_IENABLE	0x08	/* output 2 = int enable */
+#define	MCR_DRS		0x04	/* output 1 = xxx */
+#define	MCR_RTS		0x02	/* enable RTS */
+#define	MCR_DTR		0x01	/* enable DTR */
+
+/* line status register */
+#define	LSR_RCV_FIFO	0x80	/* error in receive fifo */
+#define	LSR_TSRE	0x40	/* transmitter empty */
+#define	LSR_TXRDY	0x20	/* transmitter ready */
+#define	LSR_BI		0x10	/* break detected */
+#define	LSR_FE		0x08	/* framing error */
+#define	LSR_PE		0x04	/* parity error */
+#define	LSR_OE		0x02	/* overrun error */
+#define	LSR_RXRDY	0x01	/* receiver ready */
+#define	LSR_RCV_MASK	0x1f
+
+
+/* UART interrupt enable register value */
+#define UARTIER_IME		(1 << 3)
+#define UARTIER_ILE		(1 << 2)
+#define UARTIER_ITXE	(1 << 1)
+#define UARTIER_IRXE	(1 << 0)
+
+/* UART line control register value */
+#define UARTLCR_DLAB	(1 << 7)
+#define UARTLCR_BCB		(1 << 6)
+#define UARTLCR_SPB		(1 << 5)
+#define UARTLCR_EPS		(1 << 4)
+#define UARTLCR_PE		(1 << 3)
+#define UARTLCR_SB		(1 << 2)
+
+/* UART line status register value */
+#define UARTLSR_ERROR	(1 << 7)
+#define UARTLSR_TE		(1 << 6)
+#define UARTLSR_TFE		(1 << 5)
+#define UARTLSR_BI		(1 << 4)
+#define UARTLSR_FE		(1 << 3)
+#define UARTLSR_PE		(1 << 2)
+#define UARTLSR_OE		(1 << 1)
+#define UARTLSR_DR		(1 << 0)
+
+#endif

bsp/mipssim/drivers/interrupt.c

@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+/**
+ * @addtogroup mipssim
+ */
+
+/*@{*/
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <exception.h>
+
+#define MAX_INTR 32
+
+static struct rt_irq_desc irq_handle_table[MAX_INTR];
+
+static void rt_hw_interrupt_handler(int vector, void *param)
+{
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    rt_uint32_t idx;
+    rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
+    for (idx = 0; idx < MAX_INTR; idx ++)
+    {
+        irq_handle_table[idx].handler = rt_hw_interrupt_handler;
+    }
+}
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+                                         void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector >= 0 && vector < MAX_INTR)
+    {
+        old_handler = irq_handle_table[vector].handler;
+
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+        irq_handle_table[vector].handler = handler;
+        irq_handle_table[vector].param = param;
+    }
+
+    return old_handler;
+}
+
+void rt_hw_timer_handler(void);
+
+void rt_do_mips_cpu_irq(rt_uint32_t ip)
+{
+    void *param;
+    rt_isr_handler_t irq_func;
+
+    if (ip == 7) {
+        rt_hw_timer_handler();
+    } else {
+        irq_func = irq_handle_table[ip].handler;
+                param = irq_handle_table[ip].param;
+
+                /* do interrupt */
+                irq_func(ip, param);
+    }
+}
+
+void rt_hw_interrupt_umask(int irq)
+{
+    mips_unmask_cpu_irq(irq);
+}
+
+void rt_hw_interrupt_mask(int irq)
+{
+    mips_mask_cpu_irq(irq);
+}
+/*@}*/

bsp/mipssim/drivers/mipssim.h

@@ -0,0 +1,14 @@
+#ifndef _MIPSSIM_H__
+#define _MIPSSIM_H__
+
+#include <mips.h>
+
+#define ISA_MMIO_BASE   0x1fd00000
+
+#define UART0_ISA_OFF   0x3f8
+#define UART0_BASE KSEG1ADDR(ISA_MMIO_BASE + UART0_ISA_OFF)
+
+void rt_hw_timer_handler(void);
+void rt_hw_uart_init(void);
+
+#endif

bsp/mipssim/mipssim_ram.lds

@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+OUTPUT_ARCH(mips)
+GROUP(-lgcc -lc)
+
+ENTRY(_start)
+SECTIONS
+{
+    . = 0x80000000 ;
+    .text :
+    {
+        __ebase_entry = .;
+        KEEP(*(.exc_vectors))
+        __ebase_end = .;
+        start = .;
+        *(.start);
+            . = ALIGN(4);	 
+            *(.text)
+            *(.text.*)
+            *(.rodata)
+            *(.rodata.*)
+            *(.rodata1)
+            *(.rodata1.*)
+
+
+            /* section information for finsh shell */
+            . = ALIGN(4);
+            __fsymtab_start = .;
+            KEEP(*(FSymTab))
+            __fsymtab_end = .;
+            . = ALIGN(4);
+            __vsymtab_start = .;
+            KEEP(*(VSymTab))
+            __vsymtab_end = .;
+            . = ALIGN(4);
+
+            . = ALIGN(4);
+            __rt_init_start = .;
+            KEEP(*(SORT(.rti_fn*)))
+            __rt_init_end = .;
+            . = ALIGN(4);
+
+            . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+        . = ALIGN(4);
+    }
+    
+    .eh_frame_hdr : 
+    { 
+         *(.eh_frame_hdr) 
+         *(.eh_frame_entry)
+    }
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+    . = ALIGN(4);
+    .data : 
+    {
+         *(.data)
+         *(.data.*)
+        
+         *(.data1)
+         *(.data1.*)
+
+         . = ALIGN(8);
+         _gp = ABSOLUTE(.);     /* Base of small data */
+         
+         *(.sdata)
+         *(.sdata.*)
+    }
+
+    .stack :
+    {
+        . = ALIGN(8);
+        _system_stack_start = .;
+        . = . + 0x1000;
+        _system_stack = .;
+    }
+
+    .sbss : 
+    {
+        __bss_start = .;
+        *(.sbss)
+        *(.sbss.*)
+        *(.dynsbss)
+        *(.scommon)
+    }
+
+    .bss :
+    {
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        *(COMMON)
+        __bss_end = .;
+    }
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/mipssim/rtconfig.h

@@ -0,0 +1,160 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 2048
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 2048
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 512
+#define RT_CONSOLE_DEVICE_NAME "uart"
+#define RT_VER_NUM 0x40002
+#define ARCH_MIPS
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_PTHREADS
+#define PTHREAD_NUM_MAX 8
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+#define RT_USING_UTEST
+#define UTEST_THR_STACK_SIZE 4096
+#define UTEST_THR_PRIORITY 20
+
+/* RT-Thread MIPS CPU */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+#define MIPSSIM
+
+#endif

bsp/mipssim/rtconfig.py

@@ -0,0 +1,61 @@
+import os
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = '../..'
+
+# CPU options
+ARCH='mips'
+CPU ='common'
+
+# toolchains options
+CROSS_TOOL  = 'gcc'
+
+if os.getenv('RTT_CC'):
+	CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM    = 'gcc'
+	EXEC_PATH   = "/opt/mips-2016.05/bin"
+#	EXEC_PATH   = r'D:\mgc\embedded\codebench\bin'
+else:
+    print('================ERROR===========================')
+    print('Not support %s yet!' % CROSS_TOOL)
+    print('=================================================')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD       = 'debug'
+
+PREFIX = 'mips-sde-elf-'
+CC = PREFIX + 'gcc'
+AS = PREFIX + 'gcc'
+AR = PREFIX + 'ar'
+LINK = PREFIX + 'gcc'
+TARGET_EXT = 'elf'
+SIZE = PREFIX + 'size'
+OBJDUMP = PREFIX + 'objdump'
+OBJCPY = PREFIX + 'objcopy'
+READELF = PREFIX + 'readelf'
+
+DEVICE = ' -mips32r2 -msoft-float -mfp32'
+CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer'
+AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp'
+LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T mipssim_ram.lds'
+CXXFLAGS = CFLAGS
+
+CPATH = ''
+LPATH = ''
+
+if BUILD == 'debug':
+    CFLAGS += ' -O0 -gdwarf-2'
+    AFLAGS += ' -gdwarf-2'
+else:
+    CFLAGS += ' -O2'
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+READELF_ACTION = READELF + ' -a $TARGET > rtt.map\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'

libcpu/mips/SConscript

@@ -13,6 +13,7 @@ list  = os.listdir(cwd)
 group = group + SConscript(os.path.join('common', 'SConscript'))
 
 # cpu porting code files
-group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
+if rtconfig.CPU != 'common':
+    group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
 
 Return('group')

libcpu/mips/common/Kconfig

@@ -0,0 +1,9 @@
+menu "RT-Thread MIPS CPU"
+
+    config RT_USING_FPU
+        bool "Using Float Point Unit"
+        default n
+        help
+            Using Float Point Unit in code.
+
+endmenu

libcpu/mips/common/asm.h

@@ -1,19 +1,16 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
+ * Assembly Macros For MIPS
  *
- * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
- * Copyright (C) 1999 by Silicon Graphics, Inc.
- * Copyright (C) 2001 MIPS Technologies, Inc.
- * Copyright (C) 2002  Maciej W. Rozycki
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * Some useful macros for MIPS assembler code
+ * SPDX-License-Identifier: Apache-2.0
  *
- * Some of the routines below contain useless nops that will be optimized
- * away by gas in -O mode. These nops are however required to fill delay
- * slots in noreorder mode.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
  */
+
+
 #ifndef __ASM_H__
 #define __ASM_H__
 
@@ -21,94 +18,94 @@
  * LEAF - declare leaf routine
  */
 #define	LEAF(symbol)                        \
-		.globl	symbol;                     \
-		.align	2;                          \
-		.type	symbol,@function;           \
-		.ent	symbol,0;                   \
+        .globl	symbol;                     \
+        .align	2;                          \
+        .type	symbol,@function;           \
+        .ent	symbol,0;                   \
 symbol:		.frame	sp,0,ra
 
 /*
  * NESTED - declare nested routine entry point
  */
 #define	NESTED(symbol, framesize, rpc)      \
-		.globl	symbol;                     \
-		.align	2;                          \
-		.type	symbol,@function;           \
-		.ent	symbol,0;                   \
+        .globl	symbol;                     \
+        .align	2;                          \
+        .type	symbol,@function;           \
+        .ent	symbol,0;                   \
 symbol:		.frame	sp, framesize, rpc
 
 /*
  * END - mark end of function
  */
 #define	END(function)                       \
-		.end	function;		        	\
-		.size	function,.-function
+        .end	function;		        	\
+        .size	function,.-function
 
 /*
  * EXPORT - export definition of symbol
  */
 #define EXPORT(symbol)						\
-		.globl	symbol;                     \
+        .globl	symbol;                     \
 symbol:
 
 /*
  * FEXPORT - export definition of a function symbol
  */
 #define FEXPORT(symbol)						\
-		.globl	symbol;						\
-		.type	symbol,@function;			\
+        .globl	symbol;						\
+        .type	symbol,@function;			\
 symbol:
 
 /*
  * Global data declaration with size.
  */
 #define EXPORTS(name,sz) 		\
-  	.globl name; 				\
-  	.type name,@object; 		\
-  	.size name,sz; 				\
+      .globl name; 				\
+      .type name,@object; 		\
+      .size name,sz; 				\
 name:
 
 /*
  * Weak data declaration with size.
  */
 #define WEXPORT(name,sz) 		\
-  	.weakext name; 				\
-  	.type name,@object; 		\
-  	.size name,sz; 				\
+      .weakext name; 				\
+      .type name,@object; 		\
+      .size name,sz; 				\
 name:
 
 /*
  * Global data reference with size.
  */
 #define	IMPORT(name, size) 		\
-	.extern	name,size
+    .extern	name,size
 
 /*
  * Global zeroed data.
  */
 #define BSS(name,size) 			\
-  	.type name,@object; 		\
-	.comm	name,size
+      .type name,@object; 		\
+    .comm	name,size
 
 /*
  * Local zeroed data.
  */
 #define LBSS(name,size) 		\
-  	.lcomm	name,size
+      .lcomm	name,size
 
 
 /*
  * ABS - export absolute symbol
  */
 #define	ABS(symbol,value)       \
-		.globl	symbol;         \
+        .globl	symbol;         \
 symbol		=	value
 
 
 #define	TEXT(msg)               \
-		.pushsection .data;		\
+        .pushsection .data;		\
 8:		.asciiz	msg;            \
-		.popsection;
+        .popsection;
 
 
 #define ENTRY(name) 			\

libcpu/mips/loongson_1b/context_gcc.S → libcpu/mips/common/context_gcc.S

@@ -5,42 +5,19 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-11     bernard      port to Loongson SoC3210
- * 2011-08-08     lgnq         port to Loongson LS1B
- * 2019-07-19     Zhou Yanjie  clean up code
+ * 2019-12-04     Jiaxun Yang  Initial version
  */
 
 #ifndef __ASSEMBLY__
 #define __ASSEMBLY__
 #endif
 
-#include "../common/mips_def.h"
-#include "../common/stackframe.h"
+#include "mips_regs.h"
+#include "stackframe.h"
 
     .section ".text", "ax"
     .set noreorder
 
-/*
- * rt_base_t rt_hw_interrupt_disable()
- */
-    .globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mfc0    v0, CP0_STATUS
-    and     v1, v0, 0xfffffffe
-    mtc0    v1, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level)
- */
-    .globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    mtc0    a0, CP0_STATUS
-    jr      ra
-    nop
-
 /*
  * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
  * a0 --> from
@@ -63,7 +40,6 @@ rt_hw_context_switch:
     .globl rt_hw_context_switch_to
 rt_hw_context_switch_to:
     lw      sp, 0(a0)       /* get new task stack pointer */
-
     RESTORE_ALL_AND_RET
 
 /*
@@ -94,57 +70,54 @@ _reswitch:
  */
     .globl rt_interrupt_enter
     .globl rt_interrupt_leave
+    .globl rt_general_exc_dispatch
     .globl mips_irq_handle
 mips_irq_handle:
     SAVE_ALL
 
-    mfc0    t0, CP0_CAUSE
-    and     t1, t0, 0xff
-	bnez	t1, spurious_interrupt		/* check exception */
-	nop
-
-	/* let k0 keep the current context sp */
-    move    k0, sp 
+    /* let k0 keep the current context sp */
+    move    k0, sp
     /* switch to kernel stack */
-    li      sp, SYSTEM_STACK
+    la      sp, _system_stack
 
     jal     rt_interrupt_enter
     nop
-    jal     rt_interrupt_dispatch
+    /* Get Old SP from k0 as paremeter in a0 */
+    move	a0, k0
+    jal     rt_general_exc_dispatch
     nop
     jal     rt_interrupt_leave
     nop
 
-    /* switch sp back to thread's context */
+    /* switch sp back to thread context */
     move    sp, k0
 
     /*
-     * if rt_thread_switch_interrupt_flag set, jump to
-     * rt_hw_context_switch_interrupt_do and don't return
-     */
+    * if rt_thread_switch_interrupt_flag set, jump to
+    * rt_hw_context_switch_interrupt_do and do not return
+    */
     la      k0, rt_thread_switch_interrupt_flag
     lw      k1, 0(k0)
     beqz    k1, spurious_interrupt
     nop
     sw      zero, 0(k0)                     /* clear flag */
-	nop
+    nop
 
     /*
-     * switch to the new thread
-     */
+    * switch to the new thread
+    */
     la      k0, rt_interrupt_from_thread
     lw      k1, 0(k0)
     nop
-    sw      sp, 0(k1)                       /* store sp in preempted tasks's TCB */
+    sw      sp, 0(k1)                       /* store sp in preempted task TCB */
 
     la      k0, rt_interrupt_to_thread
     lw      k1, 0(k0)
     nop
-    lw      sp, 0(k1)                       /* get new task's stack pointer */
+    lw      sp, 0(k1)                       /* get new task stack pointer */
     j       spurious_interrupt
     nop
 
 spurious_interrupt:
     RESTORE_ALL_AND_RET
-
     .set reorder

libcpu/mips/common/entry_gcc.S

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include <mips.h>
+#include <rtconfig.h>
+
+    .section ".start", "ax"
+    .set noreorder
+
+    /* the program entry */
+    .globl  _rtthread_entry
+_rtthread_entry:
+#ifndef RT_USING_SELF_BOOT
+    .globl  _start
+_start:
+#endif
+    la	ra, _rtthread_entry
+
+    /* disable interrupt */
+    mtc0	zero, CP0_CAUSE
+    mtc0	zero, CP0_STATUS	# Set CPU to disable interrupt.
+    ehb
+    /* setup stack pointer */
+    la	sp, _system_stack
+    la	gp, _gp
+
+    bal	rt_cpu_early_init
+    nop
+
+    /* clear bss */
+    la	t0, __bss_start
+    la	t1, __bss_end
+_clr_bss_loop:
+    sw	zero, 0(t0)
+    bne	t0, t1, _clr_bss_loop
+    addiu	t0, t0, 4
+
+    /* jump to RT-Thread RTOS */
+    jal	rtthread_startup
+    nop
+
+    /* restart, never die */
+    j	_start
+    nop

libcpu/mips/common/exception.c

@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include "exception.h"
+#include "mips_regs.h"
+
+/**
+ * @addtogroup MIPS
+ */
+
+/*@{*/
+
+extern rt_uint32_t __ebase_entry;
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+rt_base_t rt_hw_interrupt_disable(void)
+{
+    rt_base_t status = read_c0_status();
+    clear_c0_status(ST0_IE);
+    return status;
+}
+
+void rt_hw_interrupt_enable(rt_base_t level)
+{
+    write_c0_status(level);
+}
+
+/**
+ * exception handle table
+ */
+#define RT_EXCEPTION_MAX	31
+exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
+
+/**
+ * setup the exception handle
+ */
+exception_func_t rt_set_except_vector(int n, exception_func_t func)
+{
+    exception_func_t old_handler = sys_exception_handlers[n];
+
+    if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
+    {
+        return 0;
+    }
+
+    sys_exception_handlers[n] = func;
+
+    return old_handler;
+}
+
+void mips_dump_regs(struct pt_regs *regs) {
+    int i, j;
+    for(i = 0; i < 32 / 4; i++) {
+        for(j = 0; j < 4; j++) {
+            int reg = 4 * i + j;
+            rt_kprintf("%d: 0x%08x, ", reg, regs->regs[reg]);
+        }
+        rt_kprintf("\n");
+    }
+}
+
+void tlb_refill_handler(void)
+{
+    rt_kprintf("TLB-Miss Happens, EPC: 0x%08x\n", read_c0_epc());
+    rt_hw_cpu_shutdown();
+}
+
+void cache_error_handler(void)
+{
+    rt_kprintf("Cache Exception Happens, EPC: 0x%08x\n", read_c0_epc());
+    rt_hw_cpu_shutdown();
+}
+
+static void unhandled_exception_handle(struct pt_regs *regs)
+{
+    rt_kprintf("Unknown Exception, EPC: 0x%08x, CAUSE: 0x%08x\n", read_c0_epc(), read_c0_cause());
+    rt_kprintf("ST0: 0x%08x ",regs->cp0_status);
+    rt_kprintf("ErrorPC: 0x%08x\n",read_c0_errorepc());
+    mips_dump_regs(regs);
+    rt_hw_cpu_shutdown();
+}
+
+static void install_default_exception_handler(void)
+{
+    rt_int32_t i;
+
+    for (i=0; i<RT_EXCEPTION_MAX; i++)
+        sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
+}
+
+int rt_hw_exception_init(void)
+{
+    rt_uint32_t ebase = (rt_uint32_t)&__ebase_entry;
+    write_c0_ebase(ebase);
+    clear_c0_status(ST0_BEV | ST0_ERL | ST0_EXL);
+    clear_c0_status(ST0_IM | ST0_IE);
+    set_c0_status(ST0_CU0);
+    /* install the default exception handler */
+    install_default_exception_handler();
+
+    return RT_EOK;
+}
+
+void rt_general_exc_dispatch(struct pt_regs *regs)
+{
+    rt_uint32_t cause, exccode;
+
+    exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
+
+    if (exccode == 0) {
+        rt_uint32_t status, pending;
+        status = read_c0_status();
+        pending = (cause & CAUSEF_IP) & (status & ST0_IM);
+        if (pending & CAUSEF_IP0)
+            rt_do_mips_cpu_irq(0);
+        if (pending & CAUSEF_IP1)
+            rt_do_mips_cpu_irq(1);
+        if (pending & CAUSEF_IP2)
+            rt_do_mips_cpu_irq(2);
+        if (pending & CAUSEF_IP3)
+            rt_do_mips_cpu_irq(3);
+        if (pending & CAUSEF_IP4)
+            rt_do_mips_cpu_irq(4);
+        if (pending & CAUSEF_IP5)
+            rt_do_mips_cpu_irq(5);
+        if (pending & CAUSEF_IP6)
+            rt_do_mips_cpu_irq(6);
+        if (pending & CAUSEF_IP7)
+            rt_do_mips_cpu_irq(7);
+    } else {
+        if (sys_exception_handlers[exccode])
+            sys_exception_handlers[exccode](regs);
+    }
+}
+
+/* Mask means disable the interrupt */
+void mips_mask_cpu_irq(rt_uint32_t irq)
+{
+    clear_c0_status(1 << (STATUSB_IP0 + irq));
+}
+
+/* Unmask means enable the interrupt */
+void mips_unmask_cpu_irq(rt_uint32_t irq)
+{
+    set_c0_status(1 << (STATUSB_IP0 + irq));
+}
+
+/*@}*/

libcpu/mips/common/exception.h

@@ -1,166 +1,28 @@
 /*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2010-05-17     swkyer       first version
+ * 2019-12-04     Jiaxun Yang  Initial version
  */
+
 #ifndef __EXCEPTION_H__
 #define __EXCEPTION_H__
 
+#include "ptrace.h"
 
-/*
- * important register numbers
- */
-#define REG_EPC				37
-#define REG_FP				72
-#define REG_SP				29
-
-/*
- * Stack layout for the GDB exception handler
- * Derived from the stack layout described in asm-mips/stackframe.h
- *
- * The first PTRSIZE*6 bytes are argument save space for C subroutines.
- */
-#define NUMREGS				90
-
-#define GDB_FR_REG0			(PTRSIZE*6)			/* 0 */
-#define GDB_FR_REG1			((GDB_FR_REG0) + LONGSIZE)	/* 1 */
-#define GDB_FR_REG2			((GDB_FR_REG1) + LONGSIZE)	/* 2 */
-#define GDB_FR_REG3			((GDB_FR_REG2) + LONGSIZE)	/* 3 */
-#define GDB_FR_REG4			((GDB_FR_REG3) + LONGSIZE)	/* 4 */
-#define GDB_FR_REG5			((GDB_FR_REG4) + LONGSIZE)	/* 5 */
-#define GDB_FR_REG6			((GDB_FR_REG5) + LONGSIZE)	/* 6 */
-#define GDB_FR_REG7			((GDB_FR_REG6) + LONGSIZE)	/* 7 */
-#define GDB_FR_REG8			((GDB_FR_REG7) + LONGSIZE)	/* 8 */
-#define GDB_FR_REG9	        ((GDB_FR_REG8) + LONGSIZE)	/* 9 */
-#define GDB_FR_REG10		((GDB_FR_REG9) + LONGSIZE)	/* 10 */
-#define GDB_FR_REG11		((GDB_FR_REG10) + LONGSIZE)	/* 11 */
-#define GDB_FR_REG12		((GDB_FR_REG11) + LONGSIZE)	/* 12 */
-#define GDB_FR_REG13		((GDB_FR_REG12) + LONGSIZE)	/* 13 */
-#define GDB_FR_REG14		((GDB_FR_REG13) + LONGSIZE)	/* 14 */
-#define GDB_FR_REG15		((GDB_FR_REG14) + LONGSIZE)	/* 15 */
-#define GDB_FR_REG16		((GDB_FR_REG15) + LONGSIZE)	/* 16 */
-#define GDB_FR_REG17		((GDB_FR_REG16) + LONGSIZE)	/* 17 */
-#define GDB_FR_REG18		((GDB_FR_REG17) + LONGSIZE)	/* 18 */
-#define GDB_FR_REG19		((GDB_FR_REG18) + LONGSIZE)	/* 19 */
-#define GDB_FR_REG20		((GDB_FR_REG19) + LONGSIZE)	/* 20 */
-#define GDB_FR_REG21		((GDB_FR_REG20) + LONGSIZE)	/* 21 */
-#define GDB_FR_REG22		((GDB_FR_REG21) + LONGSIZE)	/* 22 */
-#define GDB_FR_REG23		((GDB_FR_REG22) + LONGSIZE)	/* 23 */
-#define GDB_FR_REG24		((GDB_FR_REG23) + LONGSIZE)	/* 24 */
-#define GDB_FR_REG25		((GDB_FR_REG24) + LONGSIZE)	/* 25 */
-#define GDB_FR_REG26		((GDB_FR_REG25) + LONGSIZE)	/* 26 */
-#define GDB_FR_REG27		((GDB_FR_REG26) + LONGSIZE)	/* 27 */
-#define GDB_FR_REG28		((GDB_FR_REG27) + LONGSIZE)	/* 28 */
-#define GDB_FR_REG29		((GDB_FR_REG28) + LONGSIZE)	/* 29 */
-#define GDB_FR_REG30		((GDB_FR_REG29) + LONGSIZE)	/* 30 */
-#define GDB_FR_REG31		((GDB_FR_REG30) + LONGSIZE)	/* 31 */
-
-/*
- * Saved special registers
- */
-#define GDB_FR_STATUS		((GDB_FR_REG31) + LONGSIZE)	/* 32 */
-#define GDB_FR_LO			((GDB_FR_STATUS) + LONGSIZE)	/* 33 */
-#define GDB_FR_HI			((GDB_FR_LO) + LONGSIZE)	/* 34 */
-#define GDB_FR_BADVADDR		((GDB_FR_HI) + LONGSIZE)	/* 35 */
-#define GDB_FR_CAUSE		((GDB_FR_BADVADDR) + LONGSIZE)	/* 36 */
-#define GDB_FR_EPC			((GDB_FR_CAUSE) + LONGSIZE)	/* 37 */
-
-///*
-// * Saved floating point registers
-// */
-//#define GDB_FR_FPR0		((GDB_FR_EPC) + LONGSIZE)	/* 38 */
-//#define GDB_FR_FPR1		((GDB_FR_FPR0) + LONGSIZE)	/* 39 */
-//#define GDB_FR_FPR2		((GDB_FR_FPR1) + LONGSIZE)	/* 40 */
-//#define GDB_FR_FPR3		((GDB_FR_FPR2) + LONGSIZE)	/* 41 */
-//#define GDB_FR_FPR4		((GDB_FR_FPR3) + LONGSIZE)	/* 42 */
-//#define GDB_FR_FPR5		((GDB_FR_FPR4) + LONGSIZE)	/* 43 */
-//#define GDB_FR_FPR6		((GDB_FR_FPR5) + LONGSIZE)	/* 44 */
-//#define GDB_FR_FPR7		((GDB_FR_FPR6) + LONGSIZE)	/* 45 */
-//#define GDB_FR_FPR8		((GDB_FR_FPR7) + LONGSIZE)	/* 46 */
-//#define GDB_FR_FPR9		((GDB_FR_FPR8) + LONGSIZE)	/* 47 */
-//#define GDB_FR_FPR10		((GDB_FR_FPR9) + LONGSIZE)	/* 48 */
-//#define GDB_FR_FPR11		((GDB_FR_FPR10) + LONGSIZE)	/* 49 */
-//#define GDB_FR_FPR12		((GDB_FR_FPR11) + LONGSIZE)	/* 50 */
-//#define GDB_FR_FPR13		((GDB_FR_FPR12) + LONGSIZE)	/* 51 */
-//#define GDB_FR_FPR14		((GDB_FR_FPR13) + LONGSIZE)	/* 52 */
-//#define GDB_FR_FPR15		((GDB_FR_FPR14) + LONGSIZE)	/* 53 */
-//#define GDB_FR_FPR16		((GDB_FR_FPR15) + LONGSIZE)	/* 54 */
-//#define GDB_FR_FPR17		((GDB_FR_FPR16) + LONGSIZE)	/* 55 */
-//#define GDB_FR_FPR18		((GDB_FR_FPR17) + LONGSIZE)	/* 56 */
-//#define GDB_FR_FPR19		((GDB_FR_FPR18) + LONGSIZE)	/* 57 */
-//#define GDB_FR_FPR20		((GDB_FR_FPR19) + LONGSIZE)	/* 58 */
-//#define GDB_FR_FPR21		((GDB_FR_FPR20) + LONGSIZE)	/* 59 */
-//#define GDB_FR_FPR22		((GDB_FR_FPR21) + LONGSIZE)	/* 60 */
-//#define GDB_FR_FPR23		((GDB_FR_FPR22) + LONGSIZE)	/* 61 */
-//#define GDB_FR_FPR24		((GDB_FR_FPR23) + LONGSIZE)	/* 62 */
-//#define GDB_FR_FPR25		((GDB_FR_FPR24) + LONGSIZE)	/* 63 */
-//#define GDB_FR_FPR26		((GDB_FR_FPR25) + LONGSIZE)	/* 64 */
-//#define GDB_FR_FPR27		((GDB_FR_FPR26) + LONGSIZE)	/* 65 */
-//#define GDB_FR_FPR28		((GDB_FR_FPR27) + LONGSIZE)	/* 66 */
-//#define GDB_FR_FPR29		((GDB_FR_FPR28) + LONGSIZE)	/* 67 */
-//#define GDB_FR_FPR30		((GDB_FR_FPR29) + LONGSIZE)	/* 68 */
-//#define GDB_FR_FPR31		((GDB_FR_FPR30) + LONGSIZE)	/* 69 */
-//
-//#define GDB_FR_FSR		((GDB_FR_FPR31) + LONGSIZE)	/* 70 */
-//#define GDB_FR_FIR		((GDB_FR_FSR) + LONGSIZE)	/* 71 */
-//#define GDB_FR_FRP		((GDB_FR_FIR) + LONGSIZE)	/* 72 */
-//
-//#define GDB_FR_DUMMY		((GDB_FR_FRP) + LONGSIZE)	/* 73, unused ??? */
-//
-///*
-// * Again, CP0 registers
-// */
-//#define GDB_FR_CP0_INDEX	((GDB_FR_DUMMY) + LONGSIZE)	/* 74 */
-#define GDB_FR_FRP			((GDB_FR_EPC) + LONGSIZE)	/* 72 */
-#define GDB_FR_CP0_INDEX	((GDB_FR_FRP) + LONGSIZE)	/* 74 */
-
-#define GDB_FR_CP0_RANDOM	((GDB_FR_CP0_INDEX) + LONGSIZE)	/* 75 */
-#define GDB_FR_CP0_ENTRYLO0	((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
-#define GDB_FR_CP0_ENTRYLO1	((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
-#define GDB_FR_CP0_CONTEXT	((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
-#define GDB_FR_CP0_PAGEMASK	((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
-#define GDB_FR_CP0_WIRED	((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
-#define GDB_FR_CP0_REG7		((GDB_FR_CP0_WIRED) + LONGSIZE)	/* 81 */
-#define GDB_FR_CP0_REG8		((GDB_FR_CP0_REG7) + LONGSIZE)	/* 82 */
-#define GDB_FR_CP0_REG9		((GDB_FR_CP0_REG8) + LONGSIZE)	/* 83 */
-#define GDB_FR_CP0_ENTRYHI	((GDB_FR_CP0_REG9) + LONGSIZE)	/* 84 */
-#define GDB_FR_CP0_REG11	((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
-#define GDB_FR_CP0_REG12	((GDB_FR_CP0_REG11) + LONGSIZE)	/* 86 */
-#define GDB_FR_CP0_REG13	((GDB_FR_CP0_REG12) + LONGSIZE)	/* 87 */
-#define GDB_FR_CP0_REG14	((GDB_FR_CP0_REG13) + LONGSIZE)	/* 88 */
-#define GDB_FR_CP0_PRID		((GDB_FR_CP0_REG14) + LONGSIZE)	/* 89 */
-
-#define GDB_FR_SIZE			((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
-
-/*
- * This is the same as above, but for the high-level
- * part of the INT stub.
- */
-typedef struct pt_regs_s
-{
-	/* Saved main processor registers. */
-	rt_base_t regs[32];
-	/* Saved special registers. */
-	rt_base_t cp0_status;
-	rt_base_t hi;
-	rt_base_t lo;
-	rt_base_t cp0_badvaddr;
-	rt_base_t cp0_cause;
-	rt_base_t cp0_epc;
-} pt_regs_t;
+#ifndef __ASSEMBLY__
 
-typedef void (* exception_func_t)(pt_regs_t *regs);
+typedef void (* exception_func_t)(struct pt_regs *regs);
 
+extern int rt_hw_exception_init(void);
 extern exception_func_t sys_exception_handlers[];
+extern void rt_do_mips_cpu_irq(rt_uint32_t ip);
 exception_func_t rt_set_except_vector(int n, exception_func_t func);
-void install_default_execpt_handle(void);
+extern void mips_mask_cpu_irq(rt_uint32_t irq);
+extern void mips_unmask_cpu_irq(rt_uint32_t irq);
+#endif
 
 #endif /* end of __EXCEPTION_H__ */

libcpu/mips/common/exception_gcc.S

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+    .section ".exc_vectors", "ax"
+    .extern tlb_refill_handler
+    .extern cache_error_handler
+    .extern mips_irq_handle
+
+    /* 0x0 - TLB refill handler */
+    .global tlb_refill_exception
+    .type	tlb_refill_exception,@function
+ebase_start:
+tlb_refill_exception:
+    b	_general_exception_handler
+    nop
+
+    /* 0x100 - Cache error handler */
+    .org ebase_start + 0x100
+    j	cache_error_handler
+    nop
+
+    /* 0x180 - Exception/Interrupt handler */
+    .global general_exception
+    .type	general_exception,@function
+    .org ebase_start + 0x180
+general_exception:
+    b	_general_exception_handler
+    nop
+
+    /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
+    .global irq_exception
+    .type	irq_exception,@function
+    .org ebase_start + 0x200
+irq_exception:
+    b	_general_exception_handler
+    nop
+
+    /* general exception handler */
+_general_exception_handler:
+    .set	noreorder
+    la	$k0, mips_irq_handle
+    jr	$k0
+    nop
+    .set	reorder
+
+    /* interrupt handler */
+_irq_handler:
+    .set	noreorder
+    la	$k0, mips_irq_handle
+    jr	$k0
+    nop
+    .set	reorder

libcpu/mips/common/mips.h

@@ -12,14 +12,12 @@
 #define _COMMON_MIPS_H_
 
 #include "mips_cfg.h"
-
+#include "ptrace.h"
 #include "mips_types.h"
-#include "mips_asm.h"
-#include "mips_def.h"
+#include "asm.h"
 #include "mips_regs.h"
 #include "mips_addrspace.h"
 #include "mips_cache.h"
-#include "mips_context.h"
-#include "mips_excpt.h"
+#include "exception.h"
 
 #endif /* _COMMON_MIPS_H_ */

libcpu/mips/common/mips_addrspace.h

@@ -1,25 +1,11 @@
 /*
- * File      : mips_addrspace.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016Äê9ÔÂ12ÈÕ     Urey         the first version
+ * 2019-12-04     Jiaxun Yang  Initial version
  */
 
 #ifndef _MIPS_ADDRSPACE_H_
@@ -108,11 +94,11 @@
  * Memory segments (32bit kernel mode addresses)
  * These are the traditional names used in the 32-bit universe.
  */
-//#define KUSEGBASE			0x00000000
-//#define KSEG0BASE			0x80000000
-//#define KSEG1BASE			0xa0000000
-//#define KSEG2BASE			0xc0000000
-//#define KSEG3BASE			0xe0000000
+#define KUSEGBASE			0x00000000
+#define KSEG0BASE			0x80000000
+#define KSEG1BASE			0xa0000000
+#define KSEG2BASE			0xc0000000
+#define KSEG3BASE			0xe0000000
 
 #define CKUSEG			0x00000000
 #define CKSEG0			0x80000000
@@ -147,14 +133,6 @@
  * Returns the uncached address of a sdram address
  */
 #ifndef __ASSEMBLY__
-#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
-/* We use a 36 bit physical address map here and
-   cannot access physical memory directly from core */
-#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
-#else	/* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
-#endif	/* CONFIG_SOC_AU1X00 */
-#endif	/* __ASSEMBLY__ */
 
 /*
  * The ultimate limited of the 64-bit MIPS architecture:  2 bits for selecting
@@ -162,46 +140,19 @@
  * R8000 implements most with its 48-bit physical address space.
  */
 #define TO_PHYS_MASK	_CONST64_(0x07ffffffffffffff)	/* 2^^59 - 1 */
-
-#ifndef CONFIG_CPU_R8000
-
-/*
- * The R8000 doesn't have the 32-bit compat spaces so we don't define them
- * in order to catch bugs in the source code.
- */
-
 #define COMPAT_K1BASE32		_CONST64_(0xffffffffa0000000)
 #define PHYS_TO_COMPATK1(x)	((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
 
-#endif
-
 #define KDM_TO_PHYS(x)		(_ACAST64_ (x) & TO_PHYS_MASK)
 #define PHYS_TO_K0(x)		(_ACAST64_ (x) | CAC_BASE)
+#endif
 
 
 #ifndef __ASSEMBLY__
-/*
- * Change virtual addresses to physical addresses and vv.
- * These are trivial on the 1:1 Linux/MIPS mapping
- */
-static inline phys_addr_t virt_to_phys(volatile void * address)
-{
-#ifndef CONFIG_64BIT
-	return CPHYSADDR(address);
-#else
-	return XPHYSADDR(address);
+#define REG8( addr )		  (*(volatile u8 *) (addr))
+#define REG16( addr )		  (*(volatile u16 *)(addr))
+#define REG32( addr )		  (*(volatile u32 *)(addr))
+#define REG64( addr )		  (*(volatile u64 *)(addr))
 #endif
-}
-
-static inline void * phys_to_virt(unsigned long address)
-{
-#ifndef CONFIG_64BIT
-	return (void *)KSEG0ADDR(address);
-#else
-	return (void *)CKSEG0ADDR(address);
-#endif
-}
-#endif
-
 
 #endif /* _MIPS_ADDRSPACE_H_ */

libcpu/mips/common/mips_asm.h

@@ -1,447 +0,0 @@
-/*
- * File      : mips_asm.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016Äê9ÔÂ7ÈÕ     Urey         the first version
- */
-
-#ifndef _MIPS_ASM_H_
-#define _MIPS_ASM_H_
-
-
-/* ********************************************************************* */
-/* Interface macro & data definition */
-
-#ifdef __ASSEMBLY__
-
-/******** ASSEMBLER SPECIFIC DEFINITIONS ********/
-
-#ifdef  __ghs__
-#define ALIGN(x) .##align (1 << (x))
-#else
-#define ALIGN(x) .##align (x)
-#endif
-
-#ifdef __ghs__
-#define SET_MIPS3()
-#define SET_MIPS0()
-#define SET_PUSH()
-#define SET_POP()
-#else
-#define SET_MIPS3() .##set mips3
-#define SET_MIPS0() .##set mips0
-#define SET_PUSH()  .##set push
-#define SET_POP()   .##set pop
-#endif
-
-/*  Different assemblers have different requirements for how to
- *  indicate that the next section is bss :
- *
- *  Some use :   .bss
- *  Others use : .section bss
- *
- *  We select which to use based on _BSS_OLD_, which may be defined
- *  in makefile.
- */
-#ifdef _BSS_OLD_
-#define BSS	.##section bss
-#else
-#define BSS	.##bss
-#endif
-
-#define LEAF(name)\
-  		.##text;\
-  		.##globl	name;\
-  		.##ent	name;\
-name:
-
-
-#define SLEAF(name)\
-  		.##text;\
-  		.##ent	name;\
-name:
-
-
-#ifdef __ghs__
-#define END(name)\
-  		.##end	name
-#else
-#define END(name)\
-  		.##size name,.-name;\
-  		.##end	name
-#endif
-
-
-#define EXTERN(name)
-
-#else
-
-#define U64 unsigned long long
-#define U32 unsigned int
-#define U16 unsigned short
-#define U8  unsigned char
-#define S64 signed long long
-#define S32 int
-#define S16 short int
-#define S8  signed char
-//#define bool U8
-
-#ifndef _SIZE_T_
-#define _SIZE_T_
-#ifdef __ghs__
-   typedef unsigned int size_t;
-#else
-   typedef unsigned long size_t;
-#endif
-#endif
-
-/* Sets the result on bPort */
-#define BIT_SET(bPort,bBitMask)        (bPort |= bBitMask)
-#define BIT_CLR(bPort,bBitMask)        (bPort &= ~bBitMask)
-
-/* Returns the result */
-#define GET_BIT_SET(bPort,bBitMask)    (bPort | bBitMask)
-#define GET_BIT_CLR(bPort,bBitMask)    (bPort & ~bBitMask)
-
-/* Returns 0 if the condition is False & a non-zero value if it is True */
-#define TEST_BIT_SET(bPort,bBitMask)   (bPort & bBitMask)
-#define TEST_BIT_CLR(bPort,bBitMask)   ((~bPort) & bBitMask)
-
-/* Split union definitions */
-typedef union tunSU16
-{
-        U16 hwHW;
-        struct tst2U8
-        {
-                U8 bB0;
-                U8 bB1;
-        }st2U8;
-}tunSU16;
-
-typedef union tunSU32
-{
-        U32 wW;
-        struct tst2U16
-        {
-                U16 hwHW0;
-                U16 hwHW1;
-        }st2U16;
-        struct tst4U8
-        {
-                U8 bB0;
-                U8 bB1;
-                U8 bB2;
-                U8 bB3;
-        }st4U8;
-}tunSU32;
-
-#endif /* #ifdef __ASSEMBLY__ */
-
-
-/******** DEFINITIONS FOR BOTH ASSEMBLER AND C ********/
-
-
-#define  NO_ERR             0x00000000     /* operation completed successfully */
-#define  ERR                0xffffffff     /* operation completed not successfully */
-
-#define False 0
-#define True !False
-
-#ifndef NULL
-#define NULL		      	((void *)0)
-#endif//NULL
-
-#ifndef MIN
-#define MIN(x,y)           ((x) < (y) ? (x) : (y))
-#endif//MIN
-
-#ifndef MAX
-#define MAX(x,y)      		((x) > (y) ? (x) : (y))
-#endif//MAX
-
-#define MAXUINT(w)	(\
-		((w) == sizeof(U8))  ? 0xFFU :\
-		((w) == sizeof(U16)) ? 0xFFFFU :\
-		((w) == sizeof(U32)) ? 0xFFFFFFFFU : 0\
-		        )
-
-#define MAXINT(w)	(\
-		((w) == sizeof(S8))  ? 0x7F :\
-		((w) == sizeof(S16)) ? 0x7FFF :\
-		((w) == sizeof(S32)) ? 0x7FFFFFFF : 0\
-		        )
-
-#define MSK(n)			  ((1 << (n)) - 1)
-
-#define KUSEG_MSK		  0x80000000
-#define KSEG_MSK		  0xE0000000
-
-#define KUSEGBASE		  0x00000000
-#define KSEG0BASE		  0x80000000
-#define KSEG1BASE		  0xA0000000
-#define KSSEGBASE		  0xC0000000
-#define KSEG3BASE		  0xE0000000
-
-/*  Below macros perform the following functions :
- *
- *  KSEG0    : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG0.
- *  KSEG1    : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG1.
- *  PHYS     : Converts KSEG0/1 or physical addr (below 0.5GB) to physical address.
- *  KSSEG    : Not relevant for converting, but used for determining range.
- *  KSEG3    : Not relevant for converting, but used for determining range.
- *  KUSEG    : Not relevant for converting, but used for determining range.
- *  KSEG0A   : Same as KSEG0 but operates on register rather than constant.
- *  KSEG1A   : Same as KSEG1 but operates on register rather than constant.
- *  PHYSA    : Same as PHYS  but operates on register rather than constant.
- *  CACHED   : Alias for KSEG0 macro .
- *	       (Note that KSEG0 cache attribute is determined by K0
- *	       field of Config register, but this is typically cached).
- *  UNCACHED : Alias for KSEG1 macro .
- */
-#ifdef __ASSEMBLY__
-#define KSEG0(addr)     (((addr) & ~KSEG_MSK)  | KSEG0BASE)
-#define KSEG1(addr)     (((addr) & ~KSEG_MSK)  | KSEG1BASE)
-#define KSSEG(addr)     (((addr) & ~KSEG_MSK)  | KSSEGBASE)
-#define KSEG3(addr)     (((addr) & ~KSEG_MSK)  | KSEG3BASE)
-#define KUSEG(addr)     (((addr) & ~KUSEG_MSK) | KUSEGBASE)
-#define PHYS(addr)      ( (addr) & ~KSEG_MSK)
-#define KSEG0A(reg) 	and reg, ~KSEG_MSK; or reg, KSEG0BASE
-#define KSEG1A(reg) 	and reg, ~KSEG_MSK; or reg, KSEG1BASE
-#define PHYSA(reg)	and reg, ~KSEG_MSK
-#else
-#define KSEG0(addr)     (((U32)(addr) & ~KSEG_MSK)  | KSEG0BASE)
-#define KSEG1(addr)     (((U32)(addr) & ~KSEG_MSK)  | KSEG1BASE)
-#define KSSEG(addr)	(((U32)(addr) & ~KSEG_MSK)  | KSSEGBASE)
-#define KSEG3(addr)	(((U32)(addr) & ~KSEG_MSK)  | KSEG3BASE)
-#define KUSEG(addr)	(((U32)(addr) & ~KUSEG_MSK) | KUSEGBASE)
-#define PHYS(addr) 	((U32)(addr)  & ~KSEG_MSK)
-#endif
-
-#define CACHED(addr)	KSEG0(addr)
-#define UNCACHED(addr)	KSEG1(addr)
-
-
-#ifdef __ASSEMBLY__
-/* Macroes to access variables at constant addresses
- * Compensates for signed 16 bit displacement
- * Typical use:	li	a0, HIKSEG1(ATLAS_ASCIIWORD)
- *		sw	v1, LO_OFFS(ATLAS_ASCIIWORD)(a0)
- */
-#define HIKSEG0(addr)	((KSEG0(addr) + 0x8000) & 0xffff0000)
-#define HIKSEG1(addr)	((KSEG1(addr) + 0x8000) & 0xffff0000)
-#define HI_PART(addr)	(((addr) + 0x8000) & 0xffff0000)
-#define LO_OFFS(addr)	((addr) & 0xffff)
-#endif
-
-
-/* Most/Least significant 32 bit from 64 bit double word */
-#define HI32(data64)		  ((U32)(data64 >> 32))
-#define LO32(data64)		  ((U32)(data64 & 0xFFFFFFFF))
-
-#if ((!defined(__ASSEMBLY__)) && (!defined(__LANGUAGE_ASSEMBLY)))
-#define REG8( addr )		  (*(volatile U8 *) (addr))
-#define REG16( addr )		  (*(volatile U16 *)(addr))
-#define REG32( addr )		  (*(volatile U32 *)(addr))
-#define REG64( addr )		  (*(volatile U64 *)(addr))
-#endif
-
-/* Register field mapping */
-#define REGFIELD(reg, rfld)	  (((reg) & rfld##_MSK) >> rfld##_SHF)
-
-/* absolute register address, access 					*/
-#define	REGA(addr)		  REG32(addr)
-
-/* physical register address, access: base address + offsett		*/
-#define	REGP(base,phys)	REG32( (U32)(base) + (phys) )
-
-/* relative register address, access: base address + offsett		*/
-#define REG(base,offs)  REG32( (U32)(base) + offs##_##OFS )
-
-/* relative register address, access: base address + offsett		*/
-#define REG_8(base,offs)  REG8( (U32)(base) + offs##_##OFS )
-
-/* relative register address, access: base address + offsett		*/
-#define REG_16(base,offs)  REG16( (U32)(base) + offs##_##OFS )
-
-/* relative register address, access: base address + offsett		*/
-#define REG_64(base,offs)  REG64( (U32)(base) + offs##_##OFS )
-
-/**************************************
- * Macroes not used by YAMON any more
- * (kept for backwards compatibility)
- */
-/* register read field							*/
-#define	REGARD(addr,fld)	((REGA(addr) & addr##_##fld##_##MSK) 	\
-			 >> addr##_##fld##_##SHF)
-
-/* register write numeric field value					*/
-#define	REGAWRI(addr,fld,intval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\
-				 | ((intval) << addr##_##fld##_##SHF))
-
-/* register write enumerated field value				*/
-#define	REGAWRE(addr,fld,enumval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\
-			| ((addr##_##fld##_##enumval) << addr##_##fld##_##SHF))
-
-
-/* Examples:
- *
- *	exccode = REGARD(CPU_CAUSE,EXC);
- *
- *	REGA(SDR_CONTROL) = REGAWRI(OSG_CONTROL,TMO,17)
- *			 | REGAWRE(OSG_CONTROL,DTYPE,PC1);
- */
-
-
-/* register read field							*/
-#define	REGRD(base,offs,fld) ((REG(base,offs) & offs##_##fld##_##MSK) 	\
-			 >> offs##_##fld##_##SHF)
-
-/* register write numeric field value					*/
-#define	REGWRI(base,offs,fld,intval)((REG(base,offs)& ~(offs##_##fld##_##MSK))\
-                                 | (((intval) << offs##_##fld##_##SHF) & offs##_##fld##_##MSK))
-
-/* register write enumerated field value				*/
-#define	REGWRE(base,offs,fld,enumval)((REG(base,offs) & ~(offs##_##fld##_##MSK))\
-				| ((offs##_##fld##_##enumval) << offs##_##fld##_##SHF))
-
-
-/* physical register read field							*/
-#define	REGPRD(base,phys,fld) ((REGP(base,phys) & phys##_##fld##_##MSK) 	\
-			 >> phys##_##fld##_##SHF)
-
-/* physical register write numeric field value					*/
-#define	REGPWRI(base,phys,fld,intval)((REGP(base,phys)& ~(phys##_##fld##_##MSK))\
-				 | ((intval) << phys##_##fld##_##SHF))
-
-/* physical register write enumerated field value				*/
-#define	REGPWRE(base,phys,fld,enumval)((REGP(base,phys) & ~(phys##_##fld##_##MSK))\
-				| ((phys##_##fld##_##enumval) << phys##_##fld##_##SHF))
-/*
- * End of macroes not used by YAMON any more
- *********************************************/
-
-/* Endian related macros */
-
-#define SWAP_BYTEADDR32( addr )   ( (addr) ^ 0x3 )
-#define SWAP_U16ADDR32( addr ) ( (addr) ^ 0x2 )
-
-/* Set byte address to little endian format */
-#ifdef EL
-#define SWAP_BYTEADDR_EL(addr) 	  addr
-#else
-#define SWAP_BYTEADDR_EL(addr)    SWAP_BYTEADDR32( addr )
-#endif
-
-/* Set byte address to big endian format */
-#ifdef EB
-#define SWAP_BYTEADDR_EB(addr) 	  addr
-#else
-#define SWAP_BYTEADDR_EB(addr)    SWAP_BYTEADDR32( addr )
-#endif
-
-/* Set U16 address to little endian format */
-#ifdef EL
-#define SWAP_U16ADDR_EL(addr)  addr
-#else
-#define SWAP_U16ADDR_EL(addr)  SWAP_U16ADDR32( addr )
-#endif
-
-/* Set U16 address to big endian format */
-#ifdef EB
-#define SWAP_U16ADDR_EB(addr)  addr
-#else
-#define SWAP_U16ADDR_EB(addr)  SWAP_U16ADDR32( addr )
-#endif
-
-#ifdef EL
-#define REGW32LE(addr, data)      REG32(addr) = (data)
-#define REGR32LE(addr, data)      (data)      = REG32(addr)
-#else
-#define REGW32LE(addr, data)      REG32(addr) = SWAPEND32(data)
-#define REGR32LE(addr, data)      (data)      = REG32(addr), (data) = SWAPEND32(data)
-#endif
-
-/* Set of 'LE'-macros, convert by BE: */
-#ifdef EL
-#define CPU_TO_LE32( value ) (value)
-#define LE32_TO_CPU( value ) (value)
-
-#define CPU_TO_LE16( value ) (value)
-#define LE16_TO_CPU( value ) (value)
-#else
-#define CPU_TO_LE32( value ) ( (                ((U32)value)  << 24) |   \
-                               ((0x0000FF00UL & ((U32)value)) <<  8) |   \
-                               ((0x00FF0000UL & ((U32)value)) >>  8) |   \
-                               (                ((U32)value)  >> 24)   )
-#define LE32_TO_CPU( value ) CPU_TO_LE32( value )
-
-#define CPU_TO_LE16( value ) ( ((U16)(((U16)value)  << 8)) |   \
-                               ((U16)(((U16)value)  >> 8))   )
-#define LE16_TO_CPU( value ) CPU_TO_LE16( value )
-#endif
-
-/* Set of 'BE'-macros, convert by LE: */
-#ifdef EB
-#define CPU_TO_BE32( value ) (value)
-#define BE32_TO_CPU( value ) (value)
-
-#define CPU_TO_BE16( value ) (value)
-#define BE16_TO_CPU( value ) (value)
-#else
-#define CPU_TO_BE32( value ) ( (                ((U32)value)  << 24) |   \
-                               ((0x0000FF00UL & ((U32)value)) <<  8) |   \
-                               ((0x00FF0000UL & ((U32)value)) >>  8) |   \
-                               (                ((U32)value)  >> 24)   )
-#define BE32_TO_CPU( value ) CPU_TO_BE32( value )
-
-#define CPU_TO_BE16( value ) ( ((U16)(((U16)value)  << 8)) |   \
-                               ((U16)(((U16)value)  >> 8))   )
-#define BE16_TO_CPU( value ) CPU_TO_BE16( value )
-#endif
-
-
-/* Control characters */
-#define CTRL_A          ('A'-0x40)
-#define CTRL_B          ('B'-0x40)
-#define CTRL_C          ('C'-0x40)
-#define CTRL_D          ('D'-0x40)
-#define CTRL_E          ('E'-0x40)
-#define CTRL_F          ('F'-0x40)
-#define CTRL_H          ('H'-0x40)
-#define CTRL_K          ('K'-0x40)
-#define CTRL_N          ('N'-0x40)
-#define CTRL_P          ('P'-0x40)
-#define CTRL_U          ('U'-0x40)
-#define BACKSPACE       0x08
-#define DEL             0x7F
-#define TAB             0x09
-#define CR              0x0D /* Enter Key */
-#define LF              0x0A
-#define ESC             0x1B
-#define SP              0x20
-#define CSI             0x9B
-
-
-/* DEF2STR(x) converts #define symbol to string */
-#define DEF2STR1(x) #x
-#define DEF2STR(x)  DEF2STR1(x)
-
-
-#endif /* _MIPS_ASM_H_ */

libcpu/mips/common/mips_cache.c

@@ -19,7 +19,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016Äê9ÔÂ7ÈÕ     Urey         the first version
+ * 2016-09-07    Urey         the first version
  */
 
 #include <rtthread.h>

libcpu/mips/common/mips_cache.h

@@ -19,7 +19,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016Äê9ÔÂ10ÈÕ     Urey         the first version
+ * 2016-09-07     Urey         the first version
  */
 
 #ifndef _MIPS_CACHE_H_
@@ -38,11 +38,7 @@
 #define INDEX_LOAD_TAG_D        0x05
 #define INDEX_STORE_TAG_I       0x08
 #define INDEX_STORE_TAG_D       0x09
-#if defined(CONFIG_CPU_LOONGSON2)
-#define HIT_INVALIDATE_I        0x00
-#else
 #define HIT_INVALIDATE_I        0x10
-#endif
 #define HIT_INVALIDATE_D        0x11
 #define HIT_WRITEBACK_INV_D     0x15
 

libcpu/mips/common/mips_cfg.h

@@ -19,7 +19,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016Äê9ÔÂ10ÈÕ     Urey         the first version
+ * 2016-09-07     Urey         the first version
  */
 
 #ifndef _MIPS_CFG_H_
@@ -30,12 +30,12 @@
 typedef struct mips32_core_cfg
 {
     uint16_t icache_line_size;
-//    uint16_t icache_lines_per_way;
-//    uint16_t icache_ways;
+    uint16_t icache_lines_per_way;
+    uint16_t icache_ways;
     uint16_t icache_size;
     uint16_t dcache_line_size;
-//    uint16_t dcache_lines_per_way;
-//    uint16_t dcache_ways;
+    uint16_t dcache_lines_per_way;
+    uint16_t dcache_ways;
     uint16_t dcache_size;
 
     uint16_t max_tlb_entries;	/* number of tlb entry */

libcpu/mips/common/mips_context.h

@@ -1,280 +0,0 @@
-/*
- * File      : mips_context_asm.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016Äê9ÔÂ7ÈÕ     Urey         the first version
- */
-
-#ifndef _MIPS_CONTEXT_ASM_H_
-#define _MIPS_CONTEXT_ASM_H_
-
-#define CONTEXT_SIZE	( STK_CTX_SIZE + FPU_ADJ )
-#ifdef __mips_hard_float
-#define FPU_ADJ			(32 * 4 + 8)		/* FP0-FP31 + CP1_STATUS */
-#define FPU_CTX			( CONTEXT_SIZE - FPU_ADJ )
-#else
-#define FPU_ADJ			0
-#endif
-
-
-
-#ifdef __ASSEMBLY__
-
-#ifdef __mips_hard_float
-.global _fpctx_save
-.global _fpctx_load
-#endif
-
-.macro SAVE_CONTEXT
-	.set    push
-	.set    noat
-	.set    noreorder
-	.set    volatile
-
-	//save SP
-	move	k1, 	sp
-	move	k0, 	sp
-	subu 	sp, 	k1, 	CONTEXT_SIZE
-	sw		k0, 	(29 * 4)(sp)
-
-	//save REG
-	sw		$0, 	( 0 * 4)(sp)
-	sw		$1, 	( 1 * 4)(sp)
-	sw		$2, 	( 2 * 4)(sp)
-	sw		$3, 	( 3 * 4)(sp)
-	sw		$4, 	( 4 * 4)(sp)
-	sw		$5, 	( 5 * 4)(sp)
-	sw		$6, 	( 6 * 4)(sp)
-	sw		$7, 	( 7 * 4)(sp)
-	sw		$8,     ( 8 * 4)(sp)
-	sw		$9,     ( 9 * 4)(sp)
-	sw		$10,    (10 * 4)(sp)
-	sw		$11,    (11 * 4)(sp)
-	sw		$12,    (12 * 4)(sp)
-	sw		$13,    (13 * 4)(sp)
-	sw		$14,    (14 * 4)(sp)
-	sw		$15,    (15 * 4)(sp)
-	sw		$16,    (16 * 4)(sp)
-	sw		$17,    (17 * 4)(sp)
-	sw		$18,    (18 * 4)(sp)
-	sw		$19,    (19 * 4)(sp)
-	sw		$20,    (20 * 4)(sp)
-	sw		$21,    (21 * 4)(sp)
-	sw		$22,    (22 * 4)(sp)
-	sw		$23,    (23 * 4)(sp)
-	sw		$24,    (24 * 4)(sp)
-	sw		$25, 	(25 * 4)(sp)
-	/* K0 K1 */
-	sw		$28, 	(28 * 4)(sp)
-	/* SP */
-	sw		$30,    (30 * 4)(sp)
-	sw		$31, 	(31 * 4)(sp)
-
-	/* STATUS CAUSE EPC.... */
-	mfc0	$2, 	CP0_STATUS
-	sw		$2, 	STK_OFFSET_SR(sp)
-
-	mfc0	$2, 	CP0_CAUSE
-	sw		$2, 	STK_OFFSET_CAUSE(sp)
-
-	mfc0	$2, 	CP0_BADVADDR
-	sw		$2, 	STK_OFFSET_BADVADDR(sp)
-
-	MFC0	$2, 	CP0_EPC
-	sw		$2, 	STK_OFFSET_EPC(sp)
-
-	mfhi	$2
-	sw		$2,     STK_OFFSET_HI(sp)
-
-	mflo	$2
-	sw		$2,     STK_OFFSET_LO(sp)
-#ifdef __mips_hard_float
-	add		a0,		sp,STK_CTX_SIZE
-
-    mfc0 	t0, 	CP0_STATUS
-    .set	push
-    .set	at
-    or      t0,   	M_StatusCU1
-    .set 	push
-    mtc0 	t0, 	CP0_STATUS
-
-    cfc1 	t0,  	CP1_STATUS
-    sw      t0   ,  0x00(a0)
-	swc1    $f0,(0x04 *  1)(a0)
-	swc1    $f1,(0x04 *  2)(a0)
-	swc1    $f2,(0x04 *  3)(a0)
-	swc1    $f3,(0x04 *  4)(a0)
-	swc1    $f4,(0x04 *  5)(a0)
-	swc1    $f5,(0x04 *  6)(a0)
-	swc1    $f6,(0x04 *  7)(a0)
-	swc1    $f7,(0x04 *  8)(a0)
-	swc1    $f8,(0x04 *  9)(a0)
-	swc1    $f9,(0x04 * 10)(a0)
-	swc1   $f10,(0x04 * 11)(a0)
-	swc1   $f11,(0x04 * 12)(a0)
-	swc1   $f12,(0x04 * 13)(a0)
-	swc1   $f13,(0x04 * 14)(a0)
-	swc1   $f14,(0x04 * 15)(a0)
-	swc1   $f15,(0x04 * 16)(a0)
-	swc1   $f16,(0x04 * 17)(a0)
-	swc1   $f17,(0x04 * 18)(a0)
-	swc1   $f18,(0x04 * 19)(a0)
-	swc1   $f19,(0x04 * 20)(a0)
-	swc1   $f20,(0x04 * 21)(a0)
-	swc1   $f21,(0x04 * 22)(a0)
-	swc1   $f22,(0x04 * 23)(a0)
-	swc1   $f23,(0x04 * 24)(a0)
-	swc1   $f24,(0x04 * 25)(a0)
-	swc1   $f25,(0x04 * 26)(a0)
-	swc1   $f26,(0x04 * 27)(a0)
-	swc1   $f27,(0x04 * 28)(a0)
-	swc1   $f28,(0x04 * 29)(a0)
-	swc1   $f29,(0x04 * 30)(a0)
-	swc1   $f30,(0x04 * 31)(a0)
-	swc1   $f31,(0x04 * 32)(a0)
-
-	nop
-#endif
-
-	//restore a0
-	lw		a0,		(REG_A0 * 4)(sp)
-
-	.set	pop
-.endm
-
-
-.macro RESTORE_CONTEXT
-	.set    push
-	.set    noat
-	.set    noreorder
-	.set    volatile
-
-#ifdef __mips_hard_float
-	add		a0,	sp,STK_CTX_SIZE
-
-    mfc0 	t0, CP0_STATUS
-    .set	push
-    .set	at
-    or      t0, M_StatusCU1
-    .set	noat
-    mtc0	t0, CP0_STATUS
-
-    lw      t0   ,   0x00(a0)
-	lwc1    $f0,(0x04 *  1)(a0)
-	lwc1    $f1,(0x04 *  2)(a0)
-	lwc1    $f2,(0x04 *  3)(a0)
-	lwc1    $f3,(0x04 *  4)(a0)
-	lwc1    $f4,(0x04 *  5)(a0)
-	lwc1    $f5,(0x04 *  6)(a0)
-	lwc1    $f6,(0x04 *  7)(a0)
-	lwc1    $f7,(0x04 *  8)(a0)
-	lwc1    $f8,(0x04 *  9)(a0)
-	lwc1    $f9,(0x04 * 10)(a0)
-	lwc1   $f10,(0x04 * 11)(a0)
-	lwc1   $f11,(0x04 * 12)(a0)
-	lwc1   $f12,(0x04 * 13)(a0)
-	lwc1   $f13,(0x04 * 14)(a0)
-	lwc1   $f14,(0x04 * 15)(a0)
-	lwc1   $f15,(0x04 * 16)(a0)
-	lwc1   $f16,(0x04 * 17)(a0)
-	lwc1   $f17,(0x04 * 18)(a0)
-	lwc1   $f18,(0x04 * 19)(a0)
-	lwc1   $f19,(0x04 * 20)(a0)
-	lwc1   $f20,(0x04 * 21)(a0)
-	lwc1   $f21,(0x04 * 22)(a0)
-	lwc1   $f22,(0x04 * 23)(a0)
-	lwc1   $f23,(0x04 * 24)(a0)
-	lwc1   $f24,(0x04 * 25)(a0)
-	lwc1   $f25,(0x04 * 26)(a0)
-	lwc1   $f26,(0x04 * 27)(a0)
-	lwc1   $f27,(0x04 * 28)(a0)
-	lwc1   $f28,(0x04 * 29)(a0)
-	lwc1   $f29,(0x04 * 30)(a0)
-	lwc1   $f30,(0x04 * 31)(a0)
-	lwc1   $f31,(0x04 * 32)(a0)
-    ctc1 	t0,     CP1_STATUS                                            ;/*  restore fpp status reg      */
-
-	nop
-#endif
-
-	/* ͨÓüĴæÆ÷ */
-	/* ZERO */
-	lw		$1,  	( 1 * 4)(sp)
-	/* V0   */
-	lw		$3,  	( 3 * 4)(sp)
-	lw		$4,  	( 4 * 4)(sp)
-	lw		$5,  	( 5 * 4)(sp)
-	lw		$6,  	( 6 * 4)(sp)
-	lw		$7,  	( 7 * 4)(sp)
-	lw		$8, 	( 8 * 4)(sp)
-	lw		$9, 	( 9 * 4)(sp)
-	lw		$10,    (10 * 4)(sp)
-	lw		$11,    (11 * 4)(sp)
-	lw		$12,    (12 * 4)(sp)
-	lw		$13,    (13 * 4)(sp)
-	lw		$14,    (14 * 4)(sp)
-	lw		$15,    (15 * 4)(sp)
-	lw		$16,    (16 * 4)(sp)
-	lw		$17,    (17 * 4)(sp)
-	lw		$18,    (18 * 4)(sp)
-	lw		$19,    (19 * 4)(sp)
-	lw		$20,    (20 * 4)(sp)
-	lw		$21,    (21 * 4)(sp)
-	lw		$22,    (22 * 4)(sp)
-	lw		$23, 	(23 * 4)(sp)
-	lw		$24, 	(24 * 4)(sp)
-	lw		$25, 	(25 * 4)(sp)
-	lw		$26, 	(26 * 4)(sp)
-	lw		$27, 	(27 * 4)(sp)
-	lw		$28, 	(28 * 4)(sp)
-	/* SP */
-	lw		$30, 	(30 * 4)(sp)
-	lw		$31, 	(31 * 4)(sp)
-
-
-	/* STATUS CAUSE EPC.... */
-	lw		$2,    STK_OFFSET_HI(sp)
-	mthi	$2
-	lw		$2, 	STK_OFFSET_LO(sp)
-	mtlo	$2
-
-	lw		$2, 	STK_OFFSET_SR(sp)
-	mtc0	$2, 	CP0_STATUS
-
-	lw		$2, 	STK_OFFSET_BADVADDR(sp)
-	mtc0	$2, 	CP0_BADVADDR
-
-	lw		$2, 	STK_OFFSET_CAUSE(sp)
-	mtc0	$2, 	CP0_CAUSE
-
-	lw		$2, 	STK_OFFSET_EPC(sp)
-	MTC0	$2, 	CP0_EPC
-
-	//restore $2
-	lw		$2,  	( 2 * 4)(sp)
-	//restore sp
-	lw		$29, 	(29 * 4)(sp)
-
-	eret
-	nop
-    .set    pop
-.endm
-#endif
-#endif /* _MIPS_CONTEXT_ASM_H_ */

libcpu/mips/common/mips_def.h

@@ -1,2296 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016-09-07     Urey         first version
- */
-
-#ifndef _COMMON_MIPS_DEF_H_
-#define _COMMON_MIPS_DEF_H_
-
-
-/*
- ************************************************************************
- *                I N S T R U C T I O N   F O R M A T S                 *
- ************************************************************************
- *
- * The following definitions describe each field in an instruction.  There
- * is one diagram for each type of instruction, with field definitions
- * following the diagram for that instruction.  Note that if a field of
- * the same name and position is defined in an earlier diagram, it is
- * not defined again in the subsequent diagram.  Only new fields are
- * defined for each diagram.
- *
- * R-Type (operate)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |           |   rs    |   rt    |   rd    |   sa    |           |
- * |   Opcode  |         |         |       Tcode       |   func    |
- * |           |                  Bcode                |     | sel |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnOpcode		26
-#define M_InstnOpcode		(0x3f << S_InstnOpcode)
-#define S_InstnRS			21
-#define M_InstnRS			(0x1f << S_InstnRS)
-#define S_InstnRT			16
-#define M_InstnRT			(0x1f << S_InstnRT)
-#define S_InstnRD			11
-#define M_InstnRD			(0x1f << S_InstnRD)
-#define S_InstnSA			6
-#define M_InstnSA			(0x1f << S_InstnSA)
-#define S_InstnTcode		6
-#define M_InstnTcode		(0x3ff << S_InstnTcode)
-#define S_InstnBcode		6
-#define M_InstnBcode		(0xfffff << S_InstnBcode)
-#define S_InstnFunc		0
-#define M_InstnFunc		(0x3f << S_InstnFunc)
-#define S_InstnSel			0
-#define M_InstnSel			(0x7 << S_InstnSel)
-
-/*
- * I-Type (load, store, branch, immediate)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   rs    |   rt    |             Offset            |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnOffset		0
-#define M_InstnOffset		(0xffff << S_InstnOffset)
-
-/*
- * I-Type (pref)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   rs    |  hint   |             Offset            |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnHint		S_InstnRT
-#define M_InstnHint		M_InstnRT
-
-/*
- * J-Type (jump)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |                    JIndex                         |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnJIndex		0
-#define M_InstnJIndex		(0x03ffffff << S_InstnJIndex)
-
-/*
- * FP R-Type (operate)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   fmt   |   ft    |   fs    |   fd    |   func    |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnFmt		S_InstnRS
-#define M_InstnFmt		M_InstnRS
-#define S_InstnFT		S_InstnRT
-#define M_InstnFT		M_InstnRT
-#define S_InstnFS		S_InstnRD
-#define M_InstnFS		M_InstnRD
-#define S_InstnFD		S_InstnSA
-#define M_InstnFD		M_InstnSA
-
-/*
- * FP R-Type (cpu <-> cpu data movement))
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   sub   |   rt    |   fs    |          0          |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnSub		S_InstnRS
-#define M_InstnSub		M_InstnRS
-
-/*
- * FP R-Type (compare)
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |           |         |         |         |     | |C|           |
- * |   Opcode  |   fmt   |   ft    |   fs    |  cc |0|A|   func    |
- * |           |         |         |         |     | |B|           |
- * |           |         |         |         |     | |S|           |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnCCcmp		8
-#define M_InstnCCcmp		(0x7 << S_InstnCCcmp)
-#define S_InstnCABS		6
-#define M_InstnCABS		(0x1 << S_InstnCABS)
-
-/*
- * FP R-Type (FPR conditional move on FP cc)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   fmt   |  cc |n|t|   fs    |   fd    |   func    |
- * |           |         |     |d|f|         |         |           |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnCC		18
-#define M_InstnCC		(0x7 << S_InstnCC)
-#define S_InstnND		17
-#define M_InstnND		(0x1 << S_InstnND)
-#define S_InstnTF		16
-#define M_InstnTF		(0x1 << S_InstnTF)
-
-/*
- * FP R-Type (3-operand operate)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   fr    |   ft    |   fs    |   fd    | op4 | fmt3|
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnFR		S_InstnRS
-#define M_InstnFR		M_InstnRS
-#define S_InstnOp4		3
-#define M_InstnOp4		(0x7 << S_InstnOp4)
-#define S_InstnFmt3		0
-#define M_InstnFmt3		(0x7 << S_InstnFmt3)
-
-/*
- * FP R-Type (Indexed load, store)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   rs    |   rt    |   0     |   fd    |   func    |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-/*
- * FP R-Type (prefx)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   rs    |   rt    |  hint   |    0    |   func    |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define S_InstnHintX		S_InstnRD
-#define M_InstnHintX		M_InstnRD
-
-/*
- * FP R-Type (GPR conditional move on FP cc)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |    rs   |  cc |n|t|   rd    |    0    |   func    |
- * |           |         |     |d|f|         |         |           |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-/*
- * FP I-Type (load, store)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   rs    |    ft   |           Offset              |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-/*
- * FP I-Type (branch)
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |   Opcode  |   fmt   |  cc |n|t|           Offset              |
- * |           |         |     |d|f|                               |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-
-/*
- *************************************************************************
- *         V I R T U A L   A D D R E S S   D E F I N I T I O N S         *
- *************************************************************************
- */
-
-#ifdef MIPSADDR64
-#define A_K0BASE		UNS64Const(0xffffffff80000000)
-#define A_K1BASE		UNS64Const(0xffffffffa0000000)
-#define A_K2BASE		UNS64Const(0xffffffffc0000000)
-#define A_K3BASE		UNS64Const(0xffffffffe0000000)
-#define A_REGION		UNS64Const(0xc000000000000000)
-#define A_XKPHYS_ATTR		UNS64Const(0x3800000000000000)
-#else
-#define A_K0BASE		0x80000000
-#define A_K1BASE		0xa0000000
-#define A_K2BASE		0xc0000000
-#define A_K3BASE		0xe0000000
-#endif
-#define M_KMAPPED		0x40000000		/* KnSEG address is mapped if bit is one */
-
-
-#ifdef MIPS_Model64
-
-#define S_VMAP64                62
-#define M_VMAP64                UNS64Const(0xc000000000000000)
-
-#define K_VMode11               3
-#define K_VMode10               2
-#define K_VMode01               1
-#define K_VMode00               0
-
-#define S_KSEG3                 29
-#define M_KSEG3                 (0x7 << S_KSEG3)
-#define K_KSEG3                 7
-
-#define S_SSEG                  29
-#define M_SSEG                  (0x7 << S_KSEG3)
-#define K_SSEG                  6
-
-#define S_KSSEG                 29
-#define M_KSSEG                 (0x7 << S_KSEG3)
-#define K_KSSEG                 6
-
-#define S_KSEG1                 29
-#define M_KSEG1                 (0x7 << S_KSEG3)
-#define K_KSEG1                 5
-
-#define S_KSEG0                 29
-#define M_KSEG0                 (0x7 << S_KSEG3)
-#define K_KSEG0                 4
-
-#define S_XKSEG                 29
-#define M_XKSEG                 (0x7 << S_KSEG3)
-#define K_XKSEG                 3
-
-#define S_USEG                  31
-#define M_USEG                  (0x1 << S_USEG)
-#define K_USEG                  0
-
-#define S_EjtagProbeMem         20
-#define M_EjtagProbeMem         (0x1 << S_EjtagProbeMem)
-#define K_EjtagProbeMem         0
-
-
-
-#else
-
-#define S_KSEG3                 29
-#define M_KSEG3                 (0x7 << S_KSEG3)
-#define K_KSEG3                 7
-
-#define S_KSSEG                 29
-#define M_KSSEG                 (0x7 << S_KSSEG)
-#define K_KSSEG                 6
-
-#define S_SSEG                  29
-#define M_SSEG                  (0x7 << S_SSEG)
-#define K_SSEG                  6
-
-#define S_KSEG1                 29
-#define M_KSEG1                 (0x7 << S_KSEG1)
-#define K_KSEG1                 5
-
-#define S_KSEG0                 29
-#define M_KSEG0                 (0x7 << S_KSEG0)
-#define K_KSEG0                 4
-
-#define S_KUSEG                 31
-#define M_KUSEG                 (0x1 << S_KUSEG)
-#define K_KUSEG                 0
-
-#define S_SUSEG                 31
-#define M_SUSEG                 (0x1 << S_SUSEG)
-#define K_SUSEG                 0
-
-#define S_USEG                  31
-#define M_USEG                  (0x1 << S_USEG)
-#define K_USEG                  0
-
-#define K_EjtagLower            0xff200000
-#define K_EjtagUpper            0xff3fffff
-
-#define S_EjtagProbeMem         20
-#define M_EjtagProbeMem         (0x1 << S_EjtagProbeMem)
-#define K_EjtagProbeMem         0
-
-#endif
-
-
-
-/*
- *************************************************************************
- *   C A C H E   I N S T R U C T I O N   O P E R A T I O N   C O D E S   *
- *************************************************************************
- */
-
-/*
- * Cache encodings
- */
-#define K_CachePriI		0			/* Primary Icache */
-#define K_CachePriD		1			/* Primary Dcache */
-#define K_CachePriU		1			/* Unified primary */
-#define K_CacheTerU		2			/* Unified Tertiary */
-#define K_CacheSecU		3			/* Unified secondary */
-
-
-/*
- * Function encodings
- */
-#define S_CacheFunc		2			/* Amount to shift function encoding within 5-bit field */
-#define K_CacheIndexInv		0			/* Index invalidate */
-#define K_CacheIndexWBInv       0			/* Index writeback invalidate */
-#define K_CacheIndexLdTag	1			/* Index load tag */
-#define K_CacheIndexStTag	2			/* Index store tag */
-#define K_CacheHitInv		4			/* Hit Invalidate */
-#define K_CacheFill		5			/* Fill (Icache only) */
-#define K_CacheHitWBInv		5			/* Hit writeback invalidate */
-#define K_CacheHitWB		6			/* Hit writeback */
-#define K_CacheFetchLock	7			/* Fetch and lock */
-
-#define ICIndexInv		((K_CacheIndexInv << S_CacheFunc) | K_CachePriI)
-#define DCIndexWBInv		((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD)
-#define DCIndexInv		DCIndexWBInv
-#define ICIndexLdTag		((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI)
-#define DCIndexLdTag		((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD)
-#define ICIndexStTag		((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI)
-#define DCIndexStTag		((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD)
-#define ICHitInv		((K_CacheHitInv << S_CacheFunc) | K_CachePriI)
-#define DCHitInv		((K_CacheHitInv << S_CacheFunc) | K_CachePriD)
-#define ICFill			((K_CacheFill << S_CacheFunc) | K_CachePriI)
-#define DCHitWBInv		((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD)
-#define DCHitWB			((K_CacheHitWB << S_CacheFunc) | K_CachePriD)
-#define ICFetchLock		((K_CacheFetchLock << S_CacheFunc) | K_CachePriI)
-#define DCFetchLock		((K_CacheFetchLock << S_CacheFunc) | K_CachePriD)
-
-
-/*
- *************************************************************************
- *          P R E F E T C H   I N S T R U C T I O N   H I N T S          *
- *************************************************************************
- */
-
-#define PrefLoad		0
-#define PrefStore		1
-#define PrefLoadStreamed	4
-#define PrefStoreStreamed	5
-#define PrefLoadRetained	6
-#define PrefStoreRetained	7
-#define PrefWBInval		25
-#define PrefNudge		25
-
-
-/*
- *************************************************************************
- *             C P U   R E G I S T E R   D E F I N I T I O N S           *
- *************************************************************************
- */
-
-
-/*
- *************************************************************************
- *                  S O F T W A R E   G P R   N A M E S                  *
- *************************************************************************
- */
-#ifdef __ASSEMBLY__
-#define zero			 $0
-#define AT			 $1
-#define v0			 $2
-#define v1			 $3
-#define a0			 $4
-#define a1			 $5
-#define a2			 $6
-#define a3			 $7
-#define t0			 $8
-#define t1			 $9
-#define t2			$10
-#define t3			$11
-#define t4			$12
-#define t5			$13
-#define t6			$14
-#define t7			$15
-#define s0			$16
-#define s1			$17
-#define s2			$18
-#define s3			$19
-#define s4			$20
-#define s5			$21
-#define s6			$22
-#define s7			$23
-#define t8			$24
-#define t9			$25
-#define k0			$26
-#define k1			$27
-#define gp			$28
-#define sp			$29
-#define fp			$30
-#define ra			$31
-
-/*
- * The following registers are used by the AVP environment and
- * are not part of the normal software definitions.
- */
-
-#ifdef MIPSAVPENV
-#define repc			$25			/* Expected exception PC */
-#define tid			$30			/* Current test case address */
-#endif
-
-
-/*
- *************************************************************************
- *                  H A R D W A R E   G P R   N A M E S                  *
- *************************************************************************
- *
- * In the AVP environment, several of the `r' names are removed from the
- * name space because they are used by the kernel for special purposes.
- * Removing them causes assembly rather than runtime errors for tests that
- * use the `r' names.
- *
- *	- r25 (repc) is used as the expected PC on an exception
- *	- r26-r27 (k0, k1) are used in the exception handler
- *	- r30 (tid) is used as the current test address
- */
-
-#define r0			 $0
-#define r1			 $1
-#define r2			 $2
-#define r3			 $3
-#define r4			 $4
-#define r5			 $5
-#define r6			 $6
-#define r7			 $7
-#define r8			 $8
-#define r9			 $9
-#define r10			$10
-#define r11			$11
-#define r12			$12
-#define r13			$13
-#define r14			$14
-#define r15			$15
-#define r16			$16
-#define r17			$17
-#define r18			$18
-#define r19			$19
-#define r20			$20
-#define r21			$21
-#define r22			$22
-#define r23			$23
-#define r24			$24
-#ifdef MIPSAVPENV
-#define r25			r25_unknown
-#define r26			r26_unknown
-#define r27			r27_unknown
-#else
-#define r25			$25
-#define r26			$26
-#define r27			$27
-#endif
-#define r28			$28
-#define r29			$29
-#ifdef MIPSAVPENV
-#define r30			r30_unknown
-#else
-#define r30			$30
-#endif
-#define r31			$31
-
-#endif
-
-/*
- *************************************************************************
- *                H A R D W A R E   G P R   I N D I C E S                *
- *************************************************************************
- *
- * These definitions provide the index (number) of the GPR, as opposed
- * to the assembler register name ($n).
- */
-
-#define R_r0			 0
-#define R_r1			 1
-#define R_r2			 2
-#define R_r3			 3
-#define R_r4			 4
-#define R_r5			 5
-#define R_r6			 6
-#define R_r7			 7
-#define R_r8			 8
-#define R_r9			 9
-#define R_r10			10
-#define R_r11			11
-#define R_r12			12
-#define R_r13			13
-#define R_r14			14
-#define R_r15			15
-#define R_r16			16
-#define R_r17			17
-#define R_r18			18
-#define R_r19			19
-#define R_r20			20
-#define R_r21			21
-#define R_r22			22
-#define R_r23			23
-#define R_r24			24
-#define R_r25			25
-#define R_r26			26
-#define R_r27			27
-#define R_r28			28
-#define R_r29			29
-#define R_r30			30
-#define R_r31			31
-#define R_hi			32			/* Hi register */
-#define R_lo			33			/* Lo register */
-
-
-/*
- *************************************************************************
- *                  S O F T W A R E   G P R   M A S K S                  *
- *************************************************************************
- *
- * These definitions provide the bit mask corresponding to the GPR number
- */
-
-#define M_AT			 (1<<1)
-#define M_v0			 (1<<2)
-#define M_v1			 (1<<3)
-#define M_a0			 (1<<4)
-#define M_a1			 (1<<5)
-#define M_a2			 (1<<6)
-#define M_a3			 (1<<7)
-#define M_t0			 (1<<8)
-#define M_t1			 (1<<9)
-#define M_t2			(1<<10)
-#define M_t3			(1<<11)
-#define M_t4			(1<<12)
-#define M_t5			(1<<13)
-#define M_t6			(1<<14)
-#define M_t7			(1<<15)
-#define M_s0			(1<<16)
-#define M_s1			(1<<17)
-#define M_s2			(1<<18)
-#define M_s3			(1<<19)
-#define M_s4			(1<<20)
-#define M_s5			(1<<21)
-#define M_s6			(1<<22)
-#define M_s7			(1<<23)
-#define M_t8			(1<<24)
-#define M_t9			(1<<25)
-#define M_k0			(1<<26)
-#define M_k1			(1<<27)
-#define M_gp			(1<<28)
-#define M_sp			(1<<29)
-#define M_fp			(1<<30)
-#define M_ra			(1<<31)
-
-
-/*
- *************************************************************************
- *             C P 0   R E G I S T E R   D E F I N I T I O N S           *
- *************************************************************************
- * Each register has the following definitions:
- *
- *	C0_rrr		The register number (as a $n value)
- *	R_C0_rrr	The register index (as an integer corresponding
- *			to the register number)
- *
- * Each field in a register has the following definitions:
- *
- *	S_rrrfff	The shift count required to right-justify
- *			the field.  This corresponds to the bit
- *			number of the right-most bit in the field.
- *	M_rrrfff	The Mask required to isolate the field.
- *
- * Register diagrams included below as comments correspond to the
- * MIPS32 and MIPS64 architecture specifications.  Refer to other
- * sources for register diagrams for older architectures.
- */
-
-
-/*
- ************************************************************************
- *                 I N D E X   R E G I S T E R   ( 0 )                  *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |P|                         0                       |   Index   | Index
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Index		$0
-#define R_C0_Index		0
-#define C0_INX			C0_Index		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_IndexP		31			/* Probe failure (R)*/
-#define M_IndexP		(0x1 << S_IndexP)
-
-#define S_IndexIndex		0			/* TLB index (R/W)*/
-#define M_IndexIndex		(0x3f << S_IndexIndex)
-
-#define M_Index0Fields		0x7fffffc0
-#define M_IndexRFields		0x80000000
-
-
-/*
- ************************************************************************
- *                R A N D O M   R E G I S T E R   ( 1 )                 *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                            0                      |   Index   | Random
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Random		$1
-#define R_C0_Random		1
-#define C0_RAND			$1			/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_RandomIndex		0			/* TLB random index (R)*/
-#define M_RandomIndex		(0x3f << S_RandomIndex)
-
-#define M_Random0Fields		0xffffffc0
-#define M_RandomRFields		0x0000003f
-
-
-/*
- ************************************************************************
- *              E N T R Y L O 0   R E G I S T E R   ( 2 )               *
- ************************************************************************
- *
- *  6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * | Fill (0) //| 0 |                     PFN                       |  C  |D|V|G| EntryLo0
- * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_EntryLo0		$2
-#define R_C0_EntryLo0		2
-#define C0_TLBLO_0		C0_EntryLo0		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_EntryLoPFN		6			/* PFN (R/W) */
-#define M_EntryLoPFN		(0xffffff << S_EntryLoPFN)
-#define S_EntryLoC		3			/* Coherency attribute (R/W) */
-#define M_EntryLoC		(0x7 << S_EntryLoC)
-#define S_EntryLoD		2			/* Dirty (R/W) */
-#define M_EntryLoD		(0x1 << S_EntryLoD)
-#define S_EntryLoV		1			/* Valid (R/W) */
-#define M_EntryLoV		(0x1 << S_EntryLoV)
-#define S_EntryLoG		0			/* Global (R/W) */
-#define M_EntryLoG		(0x1 << S_EntryLoG)
-#define M_EntryLoOddPFN		(0x1 << S_EntryLoPFN)	/* Odd PFN bit */
-#define S_EntryLo_RS		K_PageAlign		/* Right-justify PFN */
-#define S_EntryLo_LS		S_EntryLoPFN		/* Position PFN to appropriate position */
-
-#define M_EntryLo0Fields	0x00000000
-#define M_EntryLoRFields	0xc0000000
-#define M_EntryLo0Fields64	UNS64Const(0x0000000000000000)
-#define M_EntryLoRFields64	UNS64Const(0xffffffffc0000000)
-
-/*
- * Cache attribute values in the C field of EntryLo and the
- * K0 field of Config
- */
-#define K_CacheAttrCWTnWA	0			/* Cacheable, write-thru, no write allocate */
-#define K_CacheAttrCWTWA	1			/* Cacheable, write-thru, write allocate */
-#define K_CacheAttrU		2			/* Uncached */
-#define K_CacheAttrC		3			/* Cacheable */
-#define K_CacheAttrCN		3			/* Cacheable, non-coherent */
-#define K_CacheAttrCCE		4			/* Cacheable, coherent, exclusive */
-#define K_CacheAttrCCS		5			/* Cacheable, coherent, shared */
-#define K_CacheAttrCCU		6			/* Cacheable, coherent, update */
-#define K_CacheAttrUA		7			/* Uncached accelerated */
-
-
-/*
- ************************************************************************
- *              E N T R Y L O 1   R E G I S T E R   ( 3 )               *
- ************************************************************************
- *
- *  6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * | Fill (0) //| 0 |                     PFN                       |  C  |D|V|G| EntryLo1
- * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_EntryLo1		$3
-#define R_C0_EntryLo1		3
-#define C0_TLBLO_1		C0_EntryLo1		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-/*
- * Field definitions are as given for EntryLo0 above
- */
-
-
-/*
- ************************************************************************
- *               C O N T E X T   R E G I S T E R   ( 4 )                *
- ************************************************************************
- *
- *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  //       PTEBase    |            BadVPN<31:13>            |   0   | Context
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Context		$4
-#define R_C0_Context		4
-#define C0_CTXT			C0_Context		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_ContextPTEBase	23			/* PTE base (R/W) */
-#define M_ContextPTEBase	(0x1ff << S_ContextPTEBase)
-#define S_ContextBadVPN		4			/* BadVPN2 (R) */
-#define M_ContextBadVPN		(0x7ffff << S_ContextBadVPN)
-#define S_ContextBadVPN_LS	9			/* Position BadVPN to bit 31 */
-#define S_ContextBadVPN_RS	13			/* Right-justify shifted BadVPN field */
-
-#define M_Context0Fields	0x0000000f
-#define M_ContextRFields	0x007ffff0
-#define M_Context0Fields64	UNS64Const(0x000000000000000f)
-#define M_ContextRFields64	UNS64Const(0x00000000007ffff0)
-
-
-/*
- ************************************************************************
- *              P A G E M A S K   R E G I S T E R   ( 5 )               *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |      0      |        Mask           |            0            | PageMask
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_PageMask		$5
-#define R_C0_PageMask		5			/* Mask (R/W) */
-#define C0_PGMASK		C0_PageMask		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_PageMaskMask		13
-#define M_PageMaskMask		(0xfff << S_PageMaskMask)
-
-#define M_PageMask0Fields	0xfe001fff
-#define M_PageMaskRFields	0x00000000
-
-/*
- * Values in the Mask field
- */
-#define K_PageMask4K		0x000			/* K_PageMasknn values are values for use */
-#define K_PageMask16K		0x003			/* with KReqPageAttributes or KReqPageMask macros */
-#define K_PageMask64K		0x00f
-#define K_PageMask256K		0x03f
-#define K_PageMask1M		0x0ff
-#define K_PageMask4M		0x3ff
-#define K_PageMask16M		0xfff
-
-#define M_PageMask4K		(K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */
-#define M_PageMask16K		(K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */
-#define M_PageMask64K		(K_PageMask64K << S_PageMaskMask)
-#define M_PageMask256K		(K_PageMask256K << S_PageMaskMask)
-#define M_PageMask1M		(K_PageMask1M << S_PageMaskMask)
-#define M_PageMask4M		(K_PageMask4M << S_PageMaskMask)
-#define M_PageMask16M		(K_PageMask16M << S_PageMaskMask)
-
-
-/*
- ************************************************************************
- *                 W I R E D   R E G I S T E R   ( 6 )                  *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                            0                      |   Index   | Wired
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Wired		$6
-#define R_C0_Wired		6
-#define C0_TLBWIRED		C0_Wired		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_WiredIndex		0			/* TLB wired boundary (R/W) */
-#define M_WiredIndex		(0x3f << S_WiredIndex)
-
-#define M_Wired0Fields		0xffffffc0
-#define M_WiredRFields		0x00000000
-
-
-/*
- ************************************************************************
- *              B A D V A D D R   R E G I S T E R   ( 8 )               *
- ************************************************************************
- *
- *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  //                     Bad Virtual Address                        | BadVAddr
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_BadVAddr		$8
-#define R_C0_BadVAddr		8
-#define C0_BADVADDR		C0_BadVAddr		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define M_BadVAddrOddPage	K_PageSize		/* Even/Odd VA bit for pair of PAs */
-
-#define M_BadVAddr0Fields	0x00000000
-#define M_BadVAddrRFields	0xffffffff
-#define M_BadVAddr0Fields64	UNS64Const(0x0000000000000000)
-#define M_BadVAddrRFields64	UNS64Const(0xffffffffffffffff)
-
-/*
- ************************************************************************
- *                 C O U N T   R E G I S T E R   ( 9 )                  *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                         Count Value                           | Count
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Count		$9
-#define R_C0_Count		9
-#define C0_COUNT		C0_Count		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define M_Count0Fields		0x00000000
-#define M_CountRFields		0x00000000
-
-
-/*
- ************************************************************************
- *              E N T R Y H I   R E G I S T E R   ( 1 0 )               *
- ************************************************************************
- *
- *  6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * | R | Fill //                 VPN2                 |    0    |     ASID      | EntryHi
- * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_EntryHi		$10
-#define R_C0_EntryHi		10
-#define C0_TLBHI		C0_EntryHi		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_EntryHiR64		62			/* Region (R/W) */
-#define M_EntryHiR64		UNS64Const(0xc000000000000000)
-#define S_EntryHiVPN2		13			/* VPN/2 (R/W) */
-#define M_EntryHiVPN2		(0x7ffff << S_EntryHiVPN2)
-#define M_EntryHiVPN264		UNS64Const(0x000000ffffffe000)
-#define S_EntryHiASID		0			/* ASID (R/W) */
-#define M_EntryHiASID		(0xff << S_EntryHiASID)
-#define S_EntryHiVPN_Shf	S_EntryHiVPN2
-
-#define M_EntryHi0Fields	0x00001f00
-#define M_EntryHiRFields	0x00000000
-#define M_EntryHi0Fields64	UNS64Const(0x0000000000001f00)
-#define M_EntryHiRFields64	UNS64Const(0x3fffff0000000000)
-
-
-/*
- ************************************************************************
- *              C O M P A R E   R E G I S T E R   ( 1 1 )               *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                        Compare Value                          | Compare
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Compare		$11
-#define R_C0_Compare		11
-#define C0_COMPARE		C0_Compare		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define M_Compare0Fields	0x00000000
-#define M_CompareRFields	0x00000000
-
-
-/*
- ************************************************************************
- *               S T A T U S   R E G I S T E R   ( 1 2 )                *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |C|C|C|C|R|F|R|M|P|B|T|S|M| | R |I|I|I|I|I|I|I|I|K|S|U|U|R|E|E|I|
- * |U|U|U|U|P|R|E|X|X|E|S|R|M| | s |M|M|M|M|M|M|M|M|X|X|X|M|s|R|X|E| Status
- * |3|2|1|0| | | | | |V| | |I| | v |7|6|5|4|3|2|1|0| | | | |v|L|L| |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Status		$12
-#define R_C0_Status		12
-#define C0_SR			C0_Status		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_StatusCU		28			/* Coprocessor enable (R/W) */
-#define M_StatusCU		(0xf << S_StatusCU)
-#define S_StatusCU3		31
-#define M_StatusCU3     	(0x1 << S_StatusCU3)
-#define S_StatusCU2		30
-#define M_StatusCU2		(0x1 << S_StatusCU2)
-#define S_StatusCU1		29
-#define M_StatusCU1		(0x1 << S_StatusCU1)
-#define S_StatusCU0		28
-#define M_StatusCU0		(0x1 << S_StatusCU0)
-#define S_StatusRP		27			/* Enable reduced power mode (R/W) */
-#define M_StatusRP		(0x1 << S_StatusRP)
-#define S_StatusFR		26			/* Enable 64-bit FPRs (MIPS64 only) (R/W) */
-#define M_StatusFR		(0x1 << S_StatusFR)
-#define S_StatusRE		25			/* Enable reverse endian (R/W) */
-#define M_StatusRE		(0x1 << S_StatusRE)
-#define S_StatusMX		24			/* Enable access to MDMX resources (MIPS64 only) (R/W) */
-#define M_StatusMX		(0x1 << S_StatusMX)
-#define S_StatusPX		23			/* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */
-#define M_StatusPX		(0x1 << S_StatusPX)
-#define S_StatusBEV		22			/* Enable Boot Exception Vectors (R/W) */
-#define M_StatusBEV		(0x1 << S_StatusBEV)
-#define S_StatusTS		21			/* Denote TLB shutdown (R/W) */
-#define M_StatusTS		(0x1 << S_StatusTS)
-#define S_StatusSR		20			/* Denote soft reset (R/W) */
-#define M_StatusSR		(0x1 << S_StatusSR)
-#define S_StatusNMI		19
-#define M_StatusNMI		(0x1 << S_StatusNMI)	/* Denote NMI (R/W) */
-#define S_StatusIM		8			/* Interrupt mask (R/W) */
-#define M_StatusIM		(0xff << S_StatusIM)
-#define S_StatusIM7		15
-#define M_StatusIM7		(0x1 << S_StatusIM7)
-#define S_StatusIM6		14
-#define M_StatusIM6		(0x1 << S_StatusIM6)
-#define S_StatusIM5		13
-#define M_StatusIM5		(0x1 << S_StatusIM5)
-#define S_StatusIM4		12
-#define M_StatusIM4		(0x1 << S_StatusIM4)
-#define S_StatusIM3		11
-#define M_StatusIM3		(0x1 << S_StatusIM3)
-#define S_StatusIM2		10
-#define M_StatusIM2		(0x1 << S_StatusIM2)
-#define S_StatusIM1		9
-#define M_StatusIM1		(0x1 << S_StatusIM1)
-#define S_StatusIM0		8
-#define M_StatusIM0		(0x1 << S_StatusIM0)
-#define S_StatusKX		7			/* Enable access to extended kernel addresses (MIPS64 only) (R/W) */
-#define M_StatusKX		(0x1 << S_StatusKX)
-#define S_StatusSX		6			/* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */
-#define M_StatusSX		(0x1 << S_StatusSX)
-#define S_StatusUX		5			/* Enable access to extended user addresses (MIPS64 only) (R/W) */
-#define M_StatusUX		(0x1 << S_StatusUX)
-#define S_StatusKSU		3			/* Two-bit current mode (R/W) */
-#define M_StatusKSU		(0x3 << S_StatusKSU)
-#define S_StatusUM		4			/* User mode if supervisor mode not implemented (R/W) */
-#define M_StatusUM		(0x1 << S_StatusUM)
-#define S_StatusSM		3			/* Supervisor mode (R/W) */
-#define M_StatusSM		(0x1 << S_StatusSM)
-#define S_StatusERL		2			/* Denotes error level (R/W) */
-#define M_StatusERL		(0x1 << S_StatusERL)
-#define S_StatusEXL		1			/* Denotes exception level (R/W) */
-#define M_StatusEXL		(0x1 << S_StatusEXL)
-#define S_StatusIE		0			/* Enables interrupts (R/W) */
-#define M_StatusIE		(0x1 << S_StatusIE)
-
-#define M_Status0Fields		0x00040000
-#define M_StatusRFields		0x058000e0		/* FR, MX, PX, KX, SX, UX unused in MIPS32 */
-#define M_Status0Fields64	0x00040000
-#define M_StatusRFields64	0x00000000
-
-/*
- * Values in the KSU field
- */
-#define K_StatusKSU_U		2			/* User mode in KSU field */
-#define K_StatusKSU_S		1			/* Supervisor mode in KSU field */
-#define K_StatusKSU_K		0			/* Kernel mode in KSU field */
-
-
-/*
- ************************************************************************
- *                C A U S E   R E G I S T E R   ( 1 3 )                 *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |B| | C |       |I|W|           |I|I|I|I|I|I|I|I| |         | R |
- * |D| | E | Rsvd  |V|P|    Rsvd   |P|P|P|P|P|P|P|P| | ExcCode | s | Cause
- * | | |   |       | | |           |7|6|5|4|3|2|1|0| |         | v |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Cause		$13
-#define R_C0_Cause		13
-#define C0_CAUSE		C0_Cause		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_CauseBD		31
-#define M_CauseBD		(0x1 << S_CauseBD)
-#define S_CauseCE		28
-#define M_CauseCE		(0x3<< S_CauseCE)
-#define S_CauseIV		23
-#define M_CauseIV		(0x1 << S_CauseIV)
-#define S_CauseWP		22
-#define M_CauseWP		(0x1 << S_CauseWP)
-#define S_CauseIP		8
-#define M_CauseIP		(0xff << S_CauseIP)
-#define S_CauseIPEXT		10
-#define M_CauseIPEXT		(0x3f << S_CauseIPEXT)
-#define S_CauseIP7		15
-#define M_CauseIP7		(0x1 << S_CauseIP7)
-#define S_CauseIP6		14
-#define M_CauseIP6		(0x1 << S_CauseIP6)
-#define S_CauseIP5		13
-#define M_CauseIP5		(0x1 << S_CauseIP5)
-#define S_CauseIP4		12
-#define M_CauseIP4		(0x1 << S_CauseIP4)
-#define S_CauseIP3		11
-#define M_CauseIP3		(0x1 << S_CauseIP3)
-#define S_CauseIP2		10
-#define M_CauseIP2		(0x1 << S_CauseIP2)
-#define S_CauseIP1		9
-#define M_CauseIP1		(0x1 << S_CauseIP1)
-#define S_CauseIP0		8
-#define M_CauseIP0		(0x1 << S_CauseIP0)
-#define S_CauseExcCode		2
-#define M_CauseExcCode		(0x1f << S_CauseExcCode)
-
-#define M_Cause0Fields		0x4f3f0083
-#define M_CauseRFields		0xb000fc7c
-
-/*
- * Values in the CE field
- */
-#define K_CauseCE0		0			/* Coprocessor 0 in the CE field */
-#define K_CauseCE1		1			/* Coprocessor 1 in the CE field */
-#define K_CauseCE2		2			/* Coprocessor 2 in the CE field */
-#define K_CauseCE3		3			/* Coprocessor 3 in the CE field */
-
-/*
- * Values in the ExcCode field
- */
-#define	EX_INT			0			/* Interrupt */
-#define	EXC_INT			(EX_INT << S_CauseExcCode)
-#define	EX_MOD			1			/* TLB modified */
-#define	EXC_MOD			(EX_MOD << S_CauseExcCode)
-#define	EX_TLBL		        2			/* TLB exception (load or ifetch) */
-#define	EXC_TLBL		(EX_TLBL << S_CauseExcCode)
-#define	EX_TLBS		        3			/* TLB exception (store) */
-#define	EXC_TLBS		(EX_TLBS << S_CauseExcCode)
-#define	EX_ADEL		        4			/* Address error (load or ifetch) */
-#define	EXC_ADEL		(EX_ADEL << S_CauseExcCode)
-#define	EX_ADES		        5			/* Address error (store) */
-#define	EXC_ADES		(EX_ADES << S_CauseExcCode)
-#define	EX_IBE			6			/* Instruction Bus Error */
-#define	EXC_IBE			(EX_IBE << S_CauseExcCode)
-#define	EX_DBE			7			/* Data Bus Error */
-#define	EXC_DBE			(EX_DBE << S_CauseExcCode)
-#define	EX_SYS			8			/* Syscall */
-#define	EXC_SYS			(EX_SYS << S_CauseExcCode)
-#define	EX_SYSCALL		EX_SYS
-#define	EXC_SYSCALL		EXC_SYS
-#define	EX_BP			9			/* Breakpoint */
-#define	EXC_BP			(EX_BP << S_CauseExcCode)
-#define	EX_BREAK		EX_BP
-#define	EXC_BREAK		EXC_BP
-#define	EX_RI			10			/* Reserved instruction */
-#define	EXC_RI			(EX_RI << S_CauseExcCode)
-#define	EX_CPU			11			/* CoProcessor Unusable */
-#define	EXC_CPU			(EX_CPU << S_CauseExcCode)
-#define	EX_OV			12			/* OVerflow */
-#define	EXC_OV			(EX_OV << S_CauseExcCode)
-#define	EX_TR		    	13			/* Trap instruction */
-#define	EXC_TR			(EX_TR << S_CauseExcCode)
-#define	EX_TRAP			EX_TR
-#define	EXC_TRAP		EXC_TR
-#define EX_FPE			15			/* floating point exception */
-#define EXC_FPE			(EX_FPE << S_CauseExcCode)
-#define EX_C2E			18			/* COP2 exception */
-#define EXC_C2E			(EX_C2E << S_CauseExcCode)
-#define EX_MDMX			22			/* MDMX exception */
-#define EXC_MDMX		(EX_MDMX << S_CauseExcCode)
-#define EX_WATCH		23			/* Watch exception */
-#define EXC_WATCH		(EX_WATCH << S_CauseExcCode)
-#define	EX_MCHECK	        24			/* Machine check exception */
-#define	EXC_MCHECK 		(EX_MCHECK << S_CauseExcCode)
-#define	EX_CacheErr	        30			/* Cache error caused re-entry to Debug Mode */
-#define	EXC_CacheErr 		(EX_CacheErr << S_CauseExcCode)
-
-
-/*
- ************************************************************************
- *                   E P C   R E G I S T E R   ( 1 4 )                  *
- ************************************************************************
- *
- *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  //                        Exception PC                            | EPC
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_EPC			$14
-#define R_C0_EPC		14
-
-#define M_EPC0Fields		0x00000000
-#define M_EPCRFields		0x00000000
-#define M_EPC0Fields64		UNS64Const(0x0000000000000000)
-#define M_EPCRFields64		UNS64Const(0x0000000000000000)
-
-/*
- ************************************************************************
- *                  P R I D   R E G I S T E R   ( 1 5 )                 *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  Company Opts |   Company ID  |  Procesor ID  |   Revision    | PRId
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_PRId			$15
-#define R_C0_PRId		15
-#define C0_PRID			C0_PRID			/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_PRIdCoOpt		24			/* Company options (R) */
-#define M_PRIdCoOpt		(0xff << S_PRIdCoOpt)
-#define S_PRIdCoID		16			/* Company ID (R) */
-#define M_PRIdCoID		(0xff << S_PRIdCoID)
-#define S_PRIdImp		8			/* Implementation ID (R) */
-#define M_PRIdImp		(0xff << S_PRIdImp)
-#define S_PRIdRev		0			/* Revision (R) */
-#define M_PRIdRev		(0xff << S_PRIdRev)
-
-#define M_PRId0Fields		0x00000000
-#define M_PRIdRFields		0xffffffff
-/*
- * Values in the Company ID field
- */
-#define K_PRIdCoID_MIPS	1
-#define K_PRIdCoID_Broadcom 2
-#define K_PRIdCoID_Alchemy 3
-#define K_PRIdCoID_SiByte 4
-#define K_PRIdCoID_SandCraft 5
-#define K_PRIdCoID_Philips 6
-#define K_PRIdCoID_NextAvailable 7 /* Next available encoding */
-
-
-/*
- * Values in the implementation number field
- */
-#define K_PRIdImp_Jade		0x80
-#define K_PRIdImp_Opal		0x81
-#define K_PRIdImp_Ruby		0x82
-#define K_PRIdImp_JadeLite	0x83
-#define K_PRIdImp_4KEc          0x84    /* Emerald with TLB MMU */
-#define K_PRIdImp_4KEmp         0x85    /* Emerald with FM MMU */
-#define K_PRIdImp_4KSc          0x86    /* Coral */
-
-#define K_PRIdImp_R3000		0x01
-#define K_PRIdImp_R4000		0x04
-#define K_PRIdImp_R10000	0x09
-#define K_PRIdImp_R4300		0x0b
-#define K_PRIdImp_R5000		0x23
-#define K_PRIdImp_R5200		0x28
-#define K_PRIdImp_R5400		0x54
-
-/*
- ************************************************************************
- *               C O N F I G   R E G I S T E R   ( 1 6 )                *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |M|                             |B| A |  A  |               | K | Config
- * | | Reserved for Implementations|E| T |  R  |    Reserved   | 0 |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Config		$16
-#define R_C0_Config		16
-#define C0_CONFIG		C0_Config		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_ConfigMore		31			/* Additional config registers present (R) */
-#define M_ConfigMore		(0x1 << S_ConfigMore)
-#define S_ConfigImpl		16			/* Implementation-specific fields */
-#define M_ConfigImpl		(0x7fff << S_ConfigImpl)
-#define S_ConfigBE		15			/* Denotes big-endian operation (R) */
-#define M_ConfigBE		(0x1 << S_ConfigBE)
-#define S_ConfigAT		13			/* Architecture type (R) */
-#define M_ConfigAT		(0x3 << S_ConfigAT)
-#define S_ConfigAR		10			/* Architecture revision (R) */
-#define M_ConfigAR		(0x7 << S_ConfigAR)
-#define S_ConfigMT		7			/* MMU Type (R) */
-#define M_ConfigMT		(0x7 << S_ConfigMT)
-#define S_ConfigK0		0			/* Kseg0 coherency algorithm (R/W) */
-#define M_ConfigK0		(0x7 << S_ConfigK0)
-
-/*
- * The following definitions are technically part of the "reserved for
- * implementations" field, but are the semi-standard definition used in
- * fixed-mapping MMUs to control the cacheability of kuseg and kseg2/3
- * references.  For that reason, they are included here, but may be
- * overridden by true implementation-specific definitions
- */
-#define S_ConfigK23		28			/* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */
-#define M_ConfigK23		(0x7 << S_ConfigK23)
-#define S_ConfigKU		25			/* Kuseg coherency algorithm (FM MMU only) (R/W) */
-#define M_ConfigKU		(0x7 << S_ConfigKU)
-
-#define M_Config0Fields		0x00000078
-#define M_ConfigRFields		0x8000ff80
-
-/*
- * Values in the AT field
- */
-#define K_ConfigAT_MIPS32	0			/* MIPS32 */
-#define K_ConfigAT_MIPS64S	1			/* MIPS64 with 32-bit addresses */
-#define K_ConfigAT_MIPS64	2			/* MIPS64 with 32/64-bit addresses */
-
-/*
- * Values in the MT field
- */
-#define K_ConfigMT_NoMMU	0			/* No MMU */
-#define K_ConfigMT_TLBMMU	1			/* Standard TLB MMU */
-#define K_ConfigMT_BATMMU	2			/* Standard BAT MMU */
-#define K_ConfigMT_FMMMU	3			/* Standard Fixed Mapping MMU */
-
-
-/*
- ************************************************************************
- *         C O N F I G 1   R E G I S T E R   ( 1 6, SELECT 1 )          *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |M|  MMU Size |  IS |  IL |  IA |  DS |  DL |  DA |C|M|P|W|C|E|F| Config1
- * | |           |     |     |     |     |     |     |2|D|C|R|A|P|P|
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Config1		$16,1
-#define R_C0_Config1		16
-
-#define S_Config1More		31			/* Additional Config registers present (R) */
-#define M_Config1More		(0x1 << S_Config1More)
-#define S_Config1MMUSize 	25			/* Number of MMU entries - 1 (R) */
-#define M_Config1MMUSize 	(0x3f << S_Config1MMUSize)
-#define S_Config1IS		22			/* Icache sets per way (R) */
-#define M_Config1IS		(0x7 << S_Config1IS)
-#define S_Config1IL		19			/* Icache line size (R) */
-#define M_Config1IL		(0x7 << S_Config1IL)
-#define S_Config1IA		16			/* Icache associativity - 1 (R) */
-#define M_Config1IA		(0x7 << S_Config1IA)
-#define S_Config1DS		13			/* Dcache sets per way (R) */
-#define M_Config1DS		(0x7 << S_Config1DS)
-#define S_Config1DL		10			/* Dcache line size (R) */
-#define M_Config1DL		(0x7 << S_Config1DL)
-#define S_Config1DA		7			/* Dcache associativity (R) */
-#define M_Config1DA		(0x7 << S_Config1DA)
-#define S_Config1C2		6			/* Coprocessor 2 present (R) */
-#define M_Config1C2		(0x1 << S_Config1C2)
-#define S_Config1MD		5			/* Denotes MDMX present (R) */
-#define M_Config1MD		(0x1 << S_Config1MD)
-#define S_Config1PC		4			/* Denotes performance counters present (R) */
-#define M_Config1PC		(0x1 << S_Config1PC)
-#define S_Config1WR		3			/* Denotes watch registers present (R) */
-#define M_Config1WR		(0x1 << S_Config1WR)
-#define S_Config1CA		2			/* Denotes MIPS-16 present (R) */
-#define M_Config1CA		(0x1 << S_Config1CA)
-#define S_Config1EP		1			/* Denotes EJTAG present (R) */
-#define M_Config1EP		(0x1 << S_Config1EP)
-#define S_Config1FP		0			/* Denotes floating point present (R) */
-#define M_Config1FP		(0x1 << S_Config1FP)
-
-#define M_Config10Fields	0x00000060
-#define M_Config1RFields	0x7fffff9f
-
-/*
- * The following macro generates a table that is indexed
- * by the Icache or Dcache sets field in Config1 and
- * contains the decoded value of sets per way
- */
-#define Config1CacheSets()	\
-	HALF(64);		\
-	HALF(128);		\
-	HALF(256);		\
-	HALF(512);		\
-	HALF(1024);		\
-	HALF(2048);		\
-	HALF(4096);		\
-	HALF(8192);
-
-/*
- * The following macro generates a table that is indexed
- * by the Icache or Dcache line size field in Config1 and
- * contains the decoded value of the cache line size, in bytes
- */
-#define Config1CacheLineSize()	\
-	HALF(0);		\
-	HALF(4);		\
-	HALF(8);		\
-	HALF(16);		\
-	HALF(32);		\
-	HALF(64);		\
-	HALF(128);		\
-	HALF(256);
-
-
-/*
- ************************************************************************
- *         C O N F I G 2   R E G I S T E R   ( 1 6, SELECT 2 )          *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |M|           |     |     |     |     |     |     | | | | | |S|T| Config1
- * | |           |     |     |     |     |     |     | | | | | |M|L|
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Config2		$16,2
-#define R_C0_Config2		16
-
-#define S_Config2More		31			/* Additional Config registers present (R) */
-#define M_Config2More		(0x1 << S_Config2More)
-#define S_Config2SM		1			/* Denotes SmartMIPS ASE present (R) */
-#define M_Config2SM		(0x1 << S_Config2SM)
-#define S_Config2TL		0			/* Denotes Tracing Logic present (R) */
-#define M_Config2TL		(0x1 << S_Config2TL)
-
-#define M_Config20Fields	0xfffffffc
-#define M_Config2RFields	0x00000003
-
-/*
- ************************************************************************
- *                L L A D D R   R E G I S T E R   ( 1 7 )               *
- ************************************************************************
- *
- *  6 6    3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 2    1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |    //                      LL Physical Address                       | LLAddr
- * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_LLAddr		$17
-#define R_C0_LLAddr		17
-#define C0_LLADDR		C0_LLAddr		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define M_LLAddr0Fields		0x00000000
-#define M_LLAddrRFields		0x00000000
-#define M_LLAddr0Fields64	UNS64Const(0x0000000000000000)
-#define M_LLAddrRFields64	UNS64Const(0x0000000000000000)
-
-
-/*
- ************************************************************************
- *               W A T C H L O   R E G I S T E R   ( 1 8 )              *
- ************************************************************************
- *
- *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  //                    Watch Virtual Address                 |I|R|W| WatchLo
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_WatchLo		$18
-#define R_C0_WatchLo		18
-#define C0_WATCHLO		C0_WatchLo		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_WatchLoVAddr		3			/* Watch virtual address (R/W) */
-#define M_WatchLoVAddr		(0x1fffffff << S_WatchLoVAddr)
-#define S_WatchLoI		2			/* Enable Istream watch (R/W) */
-#define M_WatchLoI		(0x1 << S_WatchLoI)
-#define S_WatchLoR		1			/* Enable data read watch (R/W) */
-#define M_WatchLoR		(0x1 << S_WatchLoR)
-#define S_WatchLoW		0			/* Enable data write watch (R/W) */
-#define M_WatchLoW		(0x1 << S_WatchLoW)
-
-#define M_WatchLo0Fields	0x00000000
-#define M_WatchLoRFields	0x00000000
-#define M_WatchLo0Fields64	UNS64Const(0x0000000000000000)
-#define M_WatchLoRFields64	UNS64Const(0x0000000000000000)
-
-#define M_WatchLoEnables	(M_WatchLoI | M_WatchLoR | M_WatchLoW)
-
-
-/*
- ************************************************************************
- *               W A T C H H I   R E G I S T E R   ( 1 9 )              *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |M|G|    Rsvd   |      ASID     |  Rsvd |       Mask      |  0  | WatchHi
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_WatchHi		$19
-#define R_C0_WatchHi		19
-#define C0_WATCHHI		C0_WatchHi		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_WatchHiM		31			/* Denotes additional Watch registers present (R) */
-#define M_WatchHiM		(0x1 << S_WatchHiM)
-#define S_WatchHiG		30			/* Enable ASID-independent Watch match (R/W) */
-#define M_WatchHiG		(0x1 << S_WatchHiG)
-#define S_WatchHiASID		16			/* ASID value to match (R/W) */
-#define M_WatchHiASID		(0xff << S_WatchHiASID)
-#define S_WatchHiMask		3			/* Address inhibit mask (R/W) */
-#define M_WatchHiMask		(0x1ff << S_WatchHiMask)
-
-#define M_WatchHi0Fields	0x3f00f007
-#define M_WatchHiRFields	0x80000000
-
-
-/*
- ************************************************************************
- *             X C O N T E X T   R E G I S T E R   ( 2 0 )              *
- ************************************************************************
- *
- *  6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  // PTEBase  | R |                      BadVPN2<39:13>                 |   0   | XContext
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_XContext		$20
-#define R_C0_XContext		20
-#define C0_EXTCTXT		C0_XContext		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_XContextBadVPN2	4			/* BadVPN2 (R) */
-#define S_XContextBadVPN	S_XContextBadVPN2
-
-#define M_XContext0Fields	0x0000000f
-
-
-/*
- ************************************************************************
- *                 D E B U G   R E G I S T E R   ( 2 3 )                *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |D|D|N|L|D|H|C|I|M|C|D|I|D|D|     |         |N|S|   |D|D|D|D|D|D|
- * |B|M|o|S|o|a|o|B|C|a|B|E|D|D|EJTAG|DExcCode |o|S|   |I|I|D|D|B|S|
- * |D| |D|N|z|l|u|u|h|c|u|X|B|B| ver |         |S|t|   |N|B|B|B|p|S|
- * | | |C|M|e|t|n|s|e|h|s|I|S|L|     |         |S| | 0 |T| |S|L| | | Debug
- * | | |R| | | |t|E|c|e|E| |I|I|     |         |t| |   | | | | | | |
- * | | | | | | |D|P|k|E|P| |m|m|     |         | | |   | | | | | | |
- * | | | | | | |M| |P|P| | |p|p|     |         | | |   | | | | | | |
- * | | | | | | | | | | | | |r|r|     |         | | |   | | | | | | |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_Debug		$23	/* EJTAG */
-#define R_C0_Debug		23
-
-#define S_DebugDBD		31			/* Debug branch delay (R) */
-#define M_DebugDBD		(0x1 << S_DebugDBD)
-#define S_DebugDM		30			/* Debug mode (R) */
-#define M_DebugDM		(0x1 << S_DebugDM)
-#define S_DebugNoDCR		29			/* No debug control register present (R) */
-#define M_DebugNoDCR		(0x1 << S_DebugNoDCR)
-#define S_DebugLSNM		28			/* Load/Store Normal Memory (R/W) */
-#define M_DebugLSNM		(0x1 << S_DebugLSNM)
-#define S_DebugDoze		27			/* Doze (R) */
-#define M_DebugDoze		(0x1 << S_DebugDoze)
-#define S_DebugHalt		26			/* Halt (R) */
-#define M_DebugHalt		(0x1 << S_DebugHalt)
-#define S_DebugCountDM		25			/* Count register behavior in debug mode (R/W) */
-#define M_DebugCountDM		(0x1 << S_DebugCountDM)
-#define S_DebugIBusEP		24			/* Imprecise Instn Bus Error Pending (R/W) */
-#define M_DebugIBusEP		(0x1 << S_DebugIBusEP)
-#define S_DebugMCheckP		23			/* Imprecise Machine Check Pending (R/W) */
-#define M_DebugMCheckP		(0x1 << S_DebugMCheckP)
-#define S_DebugCacheEP		22			/* Imprecise Cache Error Pending (R/W) */
-#define M_DebugCacheEP		(0x1 << S_DebugCacheEP)
-#define S_DebugDBusEP		21			/* Imprecise Data Bus Error Pending (R/W) */
-#define M_DebugDBusEP		(0x1 << S_DebugDBusEP)
-#define S_DebugIEXI		20			/* Imprecise Exception Inhibit (R/W) */
-#define M_DebugIEXI		(0x1 << S_DebugIEXI)
-#define S_DebugDDBSImpr		19			/* Debug data break store imprecise (R) */
-#define M_DebugDDBSImpr		(0x1 << S_DebugDDBSImpr)
-#define S_DebugDDBLImpr		18			/* Debug data break load imprecise (R) */
-#define M_DebugDDBLImpr		(0x1 << S_DebugDDBLImpr)
-#define S_DebugEJTAGver		15			/* EJTAG version number (R) */
-#define M_DebugEJTAGver		(0x7 << S_DebugEJTAGver)
-#define S_DebugDExcCode		10			/* Debug exception code (R) */
-#define M_DebugDExcCode		(0x1f << S_DebugDExcCode)
-#define S_DebugNoSSt		9			/* No single step implemented (R) */
-#define M_DebugNoSSt		(0x1 << S_DebugNoSSt)
-#define S_DebugSSt		8			/* Single step enable (R/W) */
-#define M_DebugSSt		(0x1 << S_DebugSSt)
-#define S_DebugDINT		5			/* Debug interrupt (R) */
-#define M_DebugDINT		(0x1 << S_DebugDINT)
-#define S_DebugDIB		4			/* Debug instruction break (R) */
-#define M_DebugDIB		(0x1 << S_DebugDIB)
-#define S_DebugDDBS		3			/* Debug data break store (R) */
-#define M_DebugDDBS		(0x1 << S_DebugDDBS)
-#define S_DebugDDBL		2			/* Debug data break load (R) */
-#define M_DebugDDBL		(0x1 << S_DebugDDBL)
-#define S_DebugDBp		1			/* Debug breakpoint (R) */
-#define M_DebugDBp		(0x1 << S_DebugDBp)
-#define S_DebugDSS		0			/* Debug single step (R) */
-#define M_DebugDSS		(0x1 << S_DebugDSS)
-
-#define M_Debug0Fields	0x01f000c0
-#define M_DebugRFields	0xec0ffe3f
-
-
-/*
- ************************************************************************
- *                 D E P C   R E G I S T E R   ( 2 4 )                  *
- ************************************************************************
- *
- *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  //                  EJTAG Debug Exception PC                      | DEPC
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-
-#define C0_DEPC			$24
-#define R_C0_DEPC		24
-
-#define M_DEEPC0Fields		0x00000000
-#define M_DEEPCRFields		0x00000000
-#define M_DEEPC0Fields64	UNS64Const(0x0000000000000000)
-#define M_DEEPCRFields64	UNS64Const(0x0000000000000000)
-
-
-/*
- ************************************************************************
- *              P E R F C N T   R E G I S T E R   ( 2 5 )               *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * | |                                       |           |I| | | |E|
- * |M|                    0                  |   Event   |E|U|S|K|X| PerfCnt
- * | |                                       |           | | | | |L|
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- *
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                          Event Count                          | PerfCnt
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_PerfCnt		$25
-#define R_C0_PerfCnt		25
-#define C0_PRFCNT0		C0_PerfCnt		/* OBSOLETE - DO NOT USE IN NEW CODE */
-#define C0_PRFCNT1		C0_PerfCnt		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define S_PerfCntM		31			/* More performance counters exist (R) */
-#define M_PerfCntM		(1 << S_PerfCntM)
-#define S_PerfCntEvent		5			/* Enabled event (R/W) */
-#define M_PerfCntEvent		(0x3f << S_PerfCntEvent)
-#define S_PerfCntIE		4			/* Interrupt Enable (R/W) */
-#define M_PerfCntIE		(1 << S_PerfCntIE)
-#define S_PerfCntU		3			/* Enable counting in User Mode (R/W) */
-#define M_PerfCntU		(1 << S_PerfCntU)
-#define S_PerfCntS		2			/* Enable counting in Supervisor Mode (R/W) */
-#define M_PerfCntS		(1 << S_PerfCntS)
-#define S_PerfCntK		1			/* Enable counting in Kernel Mode (R/W) */
-#define M_PerfCntK		(1 << S_PerfCntK)
-#define S_PerfCntEXL		0			/* Enable counting while EXL==1 (R/W) */
-#define M_PerfCntEXL		(1 << S_PerfCntEXL)
-
-#define M_PerfCnt0Fields	0x7ffff800
-#define M_PerfCntRFields	0x80000000
-
-
-/*
- ************************************************************************
- *               E R R C T L   R E G I S T E R   ( 2 6 )                *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                        Error Control                          | ErrCtl
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_ErrCtl		$26
-#define R_C0_ErrCtl		26
-#define C0_ECC			$26		/* OBSOLETE - DO NOT USE IN NEW CODE */
-#define R_C0_ECC		26		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define M_ErrCtl0Fields		0x00000000
-#define M_ErrCtlRFields		0x00000000
-
-
-/*
- ************************************************************************
- *             C A C H E E R R   R E G I S T E R   ( 2 7 )              * CacheErr
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                     Cache Error Control                       | CacheErr
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_CacheErr		$27
-#define R_C0_CacheErr		27
-#define C0_CACHE_ERR		C0_CacheErr		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define M_CacheErr0Fields	0x00000000
-#define M_CachErrRFields	0x00000000
-
-
-/*
- ************************************************************************
- *                T A G L O   R E G I S T E R   ( 2 8 )                 * TagLo
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                            TagLo                              | TagLo
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_TagLo		$28
-#define R_C0_TagLo		28
-#define C0_TAGLO		C0_TagLo		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-/*
- * Some implementations use separate TagLo registers for the
- * instruction and data caches.  In those cases, the following
- * definitions can be used in relevant code
- */
-
-#define C0_ITagLo		$28,0
-#define C0_DTagLo		$28,2
-
-#define M_TagLo0Fields		0x00000000
-#define M_TagLoRFields		0x00000000
-
-
-/*
- ************************************************************************
- *        D A T A L O   R E G I S T E R   ( 2 8, SELECT 1 )             * DataLo
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                           DataLo                              | DataLo
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_DataLo		$28,1
-#define R_C0_DataLo		28
-
-/*
- * Some implementations use separate DataLo registers for the
- * instruction and data caches.  In those cases, the following
- * definitions can be used in relevant code
- */
-
-#define C0_IDataLo		$28,1
-#define C0_DDataLo		$28,3
-
-#define M_DataLo0Fields		0x00000000
-#define M_DataLoRFields		0xffffffff
-
-
-/*
- ************************************************************************
- *                T A G H I   R E G I S T E R   ( 2 9 )                 * TagHi
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                            TagHi                              | TagHi
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_TagHi		$29
-#define R_C0_TagHi		29
-#define C0_TAGHI		C0_TagHi		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-/*
- * Some implementations use separate TagHi registers for the
- * instruction and data caches.  In those cases, the following
- * definitions can be used in relevant code
- */
-
-#define C0_ITagHi		$29,0
-#define C0_DTagHi		$29,2
-
-#define M_TagHi0Fields		0x00000000
-#define M_TagHiRFields		0x00000000
-
-
-/*
- ************************************************************************
- *        D A T A H I   R E G I S T E R   ( 2 9, SELECT 1 )             * DataHi
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                           DataHi                              | DataHi
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_DataHi		$29,1
-#define R_C0_DataHi		29
-
-/*
- * Some implementations use separate DataHi registers for the
- * instruction and data caches.  In those cases, the following
- * definitions can be used in relevant code
- */
-
-#define C0_IDataHi		$29,1
-#define C0_DDataHi		$29,3
-
-#define M_DataHi0Fields		0x00000000
-#define M_DataHiRFields		0xffffffff
-
-
-/*
- ************************************************************************
- *            E R R O R E P C   R E G I S T E R   ( 3 0 )               *
- ************************************************************************
- *
- *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  //                          Error PC                              | ErrorEPC
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_ErrorEPC		$30
-#define R_C0_ErrorEPC		30
-#define C0_ERROR_EPC		C0_ErrorEPC		/* OBSOLETE - DO NOT USE IN NEW CODE */
-
-#define M_ErrorEPC0Fields	0x00000000
-#define M_ErrorEPCRFields	0x00000000
-#define M_ErrorEPC0Fields64	UNS64Const(0x0000000000000000)
-#define M_ErrorEPCRFields64	UNS64Const(0x0000000000000000)
-
-
-/*
- ************************************************************************
- *            D E S A V E   R E G I S T E R   ( 3 1 )                   *
- ************************************************************************
- *
- *  6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |  //                   EJTAG Register Save Value                    | DESAVE
- * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C0_DESAVE		$31
-#define R_C0_DESAVE		31
-
-#define M_DESAVE0Fields		0x00000000
-#define M_DESAVERFields		0x00000000
-#define M_DESAVE0Fields64	UNS64Const(0x0000000000000000)
-#define M_DESAVERFields64	UNS64Const(0x0000000000000000)
-
-
-/*
- *************************************************************************
- *             C P 1   R E G I S T E R   D E F I N I T I O N S           *
- *************************************************************************
- */
-
-
-/*
- *************************************************************************
- *                  H A R D W A R E   F P R   N A M E S                  *
- *************************************************************************
- */
-
-#define fp0			$f0
-#define fp1			$f1
-#define fp2			$f2
-#define fp3			$f3
-#define fp4			$f4
-#define fp5			$f5
-#define fp6			$f6
-#define fp7			$f7
-#define fp8			$f8
-#define fp9			$f9
-#define fp10			$f10
-#define fp11			$f11
-#define fp12			$f12
-#define fp13			$f13
-#define fp14			$f14
-#define fp15			$f15
-#define fp16			$f16
-#define fp17			$f17
-#define fp18			$f18
-#define fp19			$f19
-#define fp20			$f20
-#define fp21			$f21
-#define fp22			$f22
-#define fp23			$f23
-#define fp24			$f24
-#define fp25			$f25
-#define fp26			$f26
-#define fp27			$f27
-#define fp28			$f28
-#define fp29			$f29
-#define fp30			$f30
-#define fp31			$f31
-
-/*
- * The following definitions are used to convert an FPR name
- * into the corresponding even or odd name, respectively.
- * This is used in macro substitution in the AVPs.
- */
-
-#define fp1_even		$f0
-#define fp3_even		$f2
-#define fp5_even		$f4
-#define fp7_even		$f6
-#define fp9_even		$f8
-#define fp11_even		$f10
-#define fp13_even		$f12
-#define fp15_even		$f14
-#define fp17_even		$f16
-#define fp19_even		$f18
-#define fp21_even		$f20
-#define fp23_even		$f22
-#define fp25_even		$f24
-#define fp27_even		$f26
-#define fp29_even		$f28
-#define fp31_even		$f30
-
-#define fp0_odd			$f1
-#define fp2_odd			$f3
-#define fp4_odd			$f5
-#define fp6_odd			$f7
-#define fp8_odd			$f9
-#define fp10_odd		$f11
-#define fp12_odd		$f13
-#define fp14_odd		$f15
-#define fp16_odd		$f17
-#define fp18_odd		$f19
-#define fp20_odd		$f21
-#define fp22_odd		$f23
-#define fp24_odd		$f25
-#define fp26_odd		$f27
-#define fp28_odd		$f29
-#define fp30_odd		$f31
-
-
-/*
- *************************************************************************
- *                H A R D W A R E   F P R   I N D I C E S                *
- *************************************************************************
- *
- * These definitions provide the index (number) of the FPR, as opposed
- * to the assembler register name ($n).
- */
-
-#define R_fp0			 0
-#define R_fp1			 1
-#define R_fp2			 2
-#define R_fp3			 3
-#define R_fp4			 4
-#define R_fp5			 5
-#define R_fp6			 6
-#define R_fp7			 7
-#define R_fp8			 8
-#define R_fp9			 9
-#define R_fp10			10
-#define R_fp11			11
-#define R_fp12			12
-#define R_fp13			13
-#define R_fp14			14
-#define R_fp15			15
-#define R_fp16			16
-#define R_fp17			17
-#define R_fp18			18
-#define R_fp19			19
-#define R_fp20			20
-#define R_fp21			21
-#define R_fp22			22
-#define R_fp23			23
-#define R_fp24			24
-#define R_fp25			25
-#define R_fp26			26
-#define R_fp27			27
-#define R_fp28			28
-#define R_fp29			29
-#define R_fp30			30
-#define R_fp31			31
-
-
-/*
- *************************************************************************
- *                  H A R D W A R E   F C R   N A M E S                  *
- *************************************************************************
- */
-
-#define fc0			$0
-#define fc25			$25
-#define fc26			$26
-#define fc28			$28
-#define fc31			$31
-
-
-/*
- *************************************************************************
- *                H A R D W A R E   F C R   I N D I C E S                *
- *************************************************************************
- *
- * These definitions provide the index (number) of the FCR, as opposed
- * to the assembler register name ($n).
- */
-
-#define R_fc0			 0
-#define R_fc25			25
-#define R_fc26			26
-#define R_fc28			28
-#define R_fc31			31
-
-
-/*
- *************************************************************************
- *                  H A R D W A R E   F C C   N A M E S                  *
- *************************************************************************
- */
-
-#define cc0			$fcc0
-#define cc1			$fcc1
-#define cc2			$fcc2
-#define cc3			$fcc3
-#define cc4			$fcc4
-#define cc5			$fcc5
-#define cc6			$fcc6
-#define cc7			$fcc7
-
-
-/*
- *************************************************************************
- *                H A R D W A R E   F C C   I N D I C E S                *
- *************************************************************************
- *
- * These definitions provide the index (number) of the CC, as opposed
- * to the assembler register name ($n).
- */
-
-#define R_cc0			0
-#define R_cc1			1
-#define R_cc2			2
-#define R_cc3			3
-#define R_cc4			4
-#define R_cc5			5
-#define R_cc6			6
-#define R_cc7			7
-
-
-/*
- ************************************************************************
- *             I M P L E M E N T A T I O N   R E G I S T E R            *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |Reserved for Additional|3|P|D|S| Implementation|   Revision    | FIR
- * |  Configuration Bits   |D|S| | |               |               |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C1_FIR			$0
-#define R_C1_FIR			0
-
-#define S_FIRConfigS		16
-#define M_FIRConfigS		(0x1 << S_FIRConfigS)
-#define S_FIRConfigD		17
-#define M_FIRConfigD		(0x1 << S_FIRConfigD)
-#define S_FIRConfigPS		18
-#define M_FIRConfigPS   	(0x1 << S_FIRConfigPS)
-#define S_FIRConfig3D		19
-#define M_FIRConfig3D		(0x1 << S_FIRConfig3D)
-#define M_FIRConfigAll		(M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D)
-
-#define S_FIRImp		8
-#define M_FIRImp		(0xff << S_FIRImp)
-
-#define S_FIRRev		0
-#define M_FIRRev		(0xff << S_FIRRev)
-
-#define M_FIR0Fields		0xfff00000
-#define M_FIRRFields		0x000fffff
-
-/*
- ************************************************************************
- *          C O N D I T I O N   C O D E S   R E G I S T E R             *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                      0                        |      CC       | FCCR
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C1_FCCR			$25
-#define R_C1_FCCR		25
-
-#define S_FCCRCC		0
-#define M_FCCRCC		(0xff << S_FCCRCC)
-#define S_FCCRCC7		7
-#define M_FCCRCC7		(0x1 << S_FCCRCC7)
-#define S_FCCRCC6		6
-#define M_FCCRCC6		(0x1 << S_FCCRCC6)
-#define S_FCCRCC5		5
-#define M_FCCRCC5		(0x1 << S_FCCRCC5)
-#define S_FCCRCC4		4
-#define M_FCCRCC4		(0x1 << S_FCCRCC4)
-#define S_FCCRCC3		3
-#define M_FCCRCC3		(0x1 << S_FCCRCC3)
-#define S_FCCRCC2		2
-#define M_FCCRCC2		(0x1 << S_FCCRCC2)
-#define S_FCCRCC1		1
-#define M_FCCRCC1		(0x1 << S_FCCRCC1)
-#define S_FCCRCC0		0
-#define M_FCCRCC0		(0x1 << S_FCCRCC0)
-
-#define M_FCCR0Fields		0xffffff00
-#define M_FCCRRFields		0x000000ff
-
-
-/*
- ************************************************************************
- *                 E X C E P T I O N S   R E G I S T E R                *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |             0             |   Cause   |    0    |  Flags  | 0 | FEXR
- * |                           |E|V|Z|O|U|I|         |V|Z|O|U|I|   |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C1_FEXR			$26
-#define R_C1_FEXR		26
-
-#define S_FEXRExc		12
-#define M_FEXRExc		(0x3f << S_FEXRExc)
-#define S_FEXRExcE		17
-#define M_FEXRExcE		(0x1 << S_FEXRExcE)
-#define S_FEXRExcV		16
-#define M_FEXRExcV		(0x1 << S_FEXRExcV)
-#define S_FEXRExcZ		15
-#define M_FEXRExcZ		(0x1 << S_FEXRExcZ)
-#define S_FEXRExcO		14
-#define M_FEXRExcO		(0x1 << S_FEXRExcO)
-#define S_FEXRExcU		13
-#define M_FEXRExcU		(0x1 << S_FEXRExcU)
-#define S_FEXRExcI		12
-#define M_FEXRExcI		(0x1 << S_FEXRExcI)
-
-#define S_FEXRFlg		2
-#define M_FEXRFlg		(0x1f << S_FEXRFlg)
-#define S_FEXRFlgV		6
-#define M_FEXRFlgV		(0x1 << S_FEXRFlgV)
-#define S_FEXRFlgZ		5
-#define M_FEXRFlgZ		(0x1 << S_FEXRFlgZ)
-#define S_FEXRFlgO		4
-#define M_FEXRFlgO		(0x1 << S_FEXRFlgO)
-#define S_FEXRFlgU		3
-#define M_FEXRFlgU		(0x1 << S_FEXRFlgU)
-#define S_FEXRFlgI		2
-#define M_FEXRFlgI		(0x1 << S_FEXRFlgI)
-
-#define M_FEXR0Fields		0xfffc0f83
-#define M_FEXRRFields		0x00000000
-
-
-/*
- ************************************************************************
- *                    E N A B L E S   R E G I S T E R                   *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |                   0                   | Enables |   0   |F|RM | FENR
- * |                                       |V|Z|O|U|I|       |S|   |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C1_FENR			$28
-#define R_C1_FENR		28
-
-#define S_FENREna		7
-#define M_FENREna		(0x1f << S_FENREna)
-#define S_FENREnaV		11
-#define M_FENREnaV		(0x1 << S_FENREnaV)
-#define S_FENREnaZ		10
-#define M_FENREnaZ		(0x1 << S_FENREnaZ)
-#define S_FENREnaO		9
-#define M_FENREnaO		(0x1 << S_FENREnaO)
-#define S_FENREnaU		8
-#define M_FENREnaU		(0x1 << S_FENREnaU)
-#define S_FENREnaI		7
-#define M_FENREnaI		(0x1 << S_FENREnaI)
-
-#define S_FENRFS		2
-#define M_FENRFS		(0x1 << S_FENRFS)
-
-#define S_FENRRM		0
-#define M_FENRRM		(0x3 << S_FENRRM)
-
-#define M_FENR0Fields		0xfffff078
-#define M_FENRRFields		0x00000000
-
-
-/*
- ************************************************************************
- *           C O N T R O L  /  S T A T U S   R E G I S T E R            *
- ************************************************************************
- *
- *  3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
- *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- * |     FCC     |F|C|Imp|  0  |   Cause   | Enables |  Flags  | RM| FCSR
- * |7|6|5|4|3|2|1|S|C|   |     |E|V|Z|O|U|I|V|Z|O|U|I|V|Z|O|U|I|   |
- * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
- */
-
-#define C1_FCSR			$31
-#define R_C1_FCSR		31
-
-#define S_FCSRFCC7_1		25			/* Floating point condition codes 7..1 (R/W) */
-#define M_FCSRFCC7_1		(0x7f << S_FCSRFCC7_1)
-#define S_FCSRCC7		31
-#define M_FCSRCC7		(0x1 << S_FCSRCC7)
-#define S_FCSRCC6		30
-#define M_FCSRCC6		(0x1 << S_FCSRCC6)
-#define S_FCSRCC5		29
-#define M_FCSRCC5		(0x1 << S_FCSRCC5)
-#define S_FCSRCC4		28
-#define M_FCSRCC4		(0x1 << S_FCSRCC4)
-#define S_FCSRCC3		27
-#define M_FCSRCC3		(0x1 << S_FCSRCC3)
-#define S_FCSRCC2		26
-#define M_FCSRCC2		(0x1 << S_FCSRCC2)
-#define S_FCSRCC1		25
-#define M_FCSRCC1		(0x1 << S_FCSRCC1)
-
-#define S_FCSRFS		24			/* Flush denorms to zero (R/W) */
-#define M_FCSRFS		(0x1 << S_FCSRFS)
-
-#define S_FCSRCC0		23			/* Floating point condition code 0 (R/W) */
-#define M_FCSRCC0		(0x1 << S_FCSRCC0)
-#define S_FCSRCC		S_FCSRCC0
-#define M_FCSRCC		M_FCSRCC0
-
-#define S_FCSRImpl		21			/* Implementation-specific control bits (R/W) */
-#define M_FCSRImpl		(0x3 << S_FCSRImpl)
-
-#define S_FCSRExc		12			/* Exception cause (R/W) */
-#define M_FCSRExc		(0x3f << S_FCSRExc)
-#define S_FCSRExcE		17
-#define M_FCSRExcE		(0x1 << S_FCSRExcE)
-#define S_FCSRExcV		16
-#define M_FCSRExcV		(0x1 << S_FCSRExcV)
-#define S_FCSRExcZ		15
-#define M_FCSRExcZ		(0x1 << S_FCSRExcZ)
-#define S_FCSRExcO		14
-#define M_FCSRExcO		(0x1 << S_FCSRExcO)
-#define S_FCSRExcU		13
-#define M_FCSRExcU		(0x1 << S_FCSRExcU)
-#define S_FCSRExcI		12
-#define M_FCSRExcI		(0x1 << S_FCSRExcI)
-
-#define S_FCSREna		7			/* Exception enable (R/W) */
-#define M_FCSREna		(0x1f << S_FCSREna)
-#define S_FCSREnaV		11
-#define M_FCSREnaV		(0x1 << S_FCSREnaV)
-#define S_FCSREnaZ		10
-#define M_FCSREnaZ		(0x1 << S_FCSREnaZ)
-#define S_FCSREnaO		9
-#define M_FCSREnaO		(0x1 << S_FCSREnaO)
-#define S_FCSREnaU		8
-#define M_FCSREnaU		(0x1 << S_FCSREnaU)
-#define S_FCSREnaI		7
-#define M_FCSREnaI		(0x1 << S_FCSREnaI)
-
-#define S_FCSRFlg		2			/* Exception flags (R/W) */
-#define M_FCSRFlg		(0x1f << S_FCSRFlg)
-#define S_FCSRFlgV		6
-#define M_FCSRFlgV		(0x1 << S_FCSRFlgV)
-#define S_FCSRFlgZ		5
-#define M_FCSRFlgZ		(0x1 << S_FCSRFlgZ)
-#define S_FCSRFlgO		4
-#define M_FCSRFlgO		(0x1 << S_FCSRFlgO)
-#define S_FCSRFlgU		3
-#define M_FCSRFlgU		(0x1 << S_FCSRFlgU)
-#define S_FCSRFlgI		2
-#define M_FCSRFlgI		(0x1 << S_FCSRFlgI)
-
-#define S_FCSRRM		0			/* Rounding mode (R/W) */
-#define M_FCSRRM		(0x3 << S_FCSRRM)
-
-#define M_FCSR0Fields		0x001c0000
-#define M_FCSRRFields		0x00000000
-
-/*
- * Values in the rounding mode field (of both FCSR and FCCR)
- */
-#define K_FCSRRM_RN		0
-#define K_FCSRRM_RZ		1
-#define K_FCSRRM_RP		2
-#define K_FCSRRM_RM		3
-
-#endif /* _COMMON_MIPS_DEF_H_ */

libcpu/mips/common/mips_excpt.h

@@ -1,39 +0,0 @@
-/*
- * File      : mips_excpt.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2016Äê9ÔÂ7ÈÕ     Urey         the first version
- */
-
-#ifndef _MIPS_EXCPT_H_
-#define _MIPS_EXCPT_H_
-
-#include "mips_regs.h"
-
-#ifndef __ASSEMBLY__
-typedef void (* exception_func_t)(mips_reg_ctx *regs);
-
-//extern exception_func_t mips_exception_handlers[];
-
-int rt_hw_exception_init(void);
-exception_func_t rt_set_except_vector(int n, exception_func_t func);
-void install_default_execpt_handle(void);
-#endif /* __ASSEMBLY__ */
-#endif /* _MIPS_EXCPT_H_ */

libcpu/mips/common/mips_fpu.h

@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#ifndef _MIPS_FPU_H_
+#define _MIPS_FPU_H_
+
+#ifndef __ASSEMBLY__
+
+#include <mips_regs.h>
+/**
+ * init hardware FPU
+ */
+#ifdef RT_USING_FPU
+inline void rt_hw_fpu_init(void)
+{
+    rt_uint32_t c0_status = 0;
+    rt_uint32_t c1_status = 0;
+
+    /* Enable CU1 */
+    c0_status = read_c0_status();
+    c0_status |= (ST0_CU1 | ST0_FR);
+    write_c0_status(c0_status);
+
+    /* FCSR Configs */
+    c1_status = read_c1_status();
+    c1_status |= (FPU_CSR_FS | FPU_CSR_FO | FPU_CSR_FN);    /* Set FS, FO, FN */
+    c1_status &= ~(FPU_CSR_ALL_E);                          /* Disable exception */
+    c1_status = (c1_status & (~FPU_CSR_RM)) | FPU_CSR_RN;   /* Set RN */
+    write_c1_status(c1_status);
+
+    return ;
+}
+#else
+    inline void rt_hw_fpu_init(void){} /* Do nothing */
+#endif
+
+#endif
+
+#endif

libcpu/mips/common/mips_regs.h

@@ -1,202 +1,96 @@
 /*
- * File      : mips_regs.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016年9月7日     Urey         the first version
+ * 2019-12-04     Jiaxun Yang  Initial version
  */
 
 #ifndef _MIPS_REGS_H_
 #define _MIPS_REGS_H_
 
+#define REG_A0	4
+#define REG_SP	29
+#define REG_GP	28
+#define REG_FP	30
+#define REG_RA	31
+
+#define zero	$0	/* wired zero */
+#define AT	$1	/* assembler temp  - uppercase because of ".set at" */
+#define v0	$2	/* return value */
+#define v1	$3
+#define a0	$4	/* argument registers */
+#define a1	$5
+#define a2	$6
+#define a3	$7
+#define t0	$8	/* caller saved */
+#define t1	$9
+#define t2	$10
+#define t3	$11
+#define t4	$12
+#define ta0	$12
+#define t5	$13
+#define ta1	$13
+#define t6	$14
+#define ta2	$14
+#define t7	$15
+#define ta3	$15
+#define s0	$16	/* callee saved */
+#define s1	$17
+#define s2	$18
+#define s3	$19
+#define s4	$20
+#define s5	$21
+#define s6	$22
+#define s7	$23
+#define t8	$24	/* caller saved */
+#define t9	$25
+#define jp	$25	/* PIC jump register */
+#define k0	$26	/* kernel scratch */
+#define k1	$27
+#define gp	$28	/* global pointer */
+#define sp	$29	/* stack pointer */
+#define fp	$30	/* frame pointer */
+#define s8	$30	/* same like fp! */
+#define ra	$31	/* return address */
+
+#define fv0	$f0	 /* return value */
+#define fv0f	$f1
+#define fv1	$f2
+#define fv1f	$f3
+#define fa0	$f12	 /* argument registers */
+#define fa0f	$f13
+#define fa1	$f14
+#define fa1f	$f15
+#define ft0	$f4	 /* caller saved */
+#define ft0f	$f5
+#define ft1	$f6
+#define ft1f	$f7
+#define ft2	$f8
+#define ft2f	$f9
+#define ft3	$f10
+#define ft3f	$f11
+#define ft4	$f16
+#define ft4f	$f17
+#define ft5	$f18
+#define ft5f	$f19
+#define fs0	$f20	 /* callee saved */
+#define fs0f	$f21
+#define fs1	$f22
+#define fs1f	$f23
+#define fs2	$f24
+#define fs2f	$f25
+#define fs3	$f26
+#define fs3f	$f27
+#define fs4	$f28
+#define fs4f	$f29
+#define fs5	$f30
+#define fs5f	$f31
+
+#define fcr31	$31	 /* FPU status register */
 
-#if !defined(__ASSEMBLY__) && !defined(ASSEMBLY)
-#include <rtdef.h>
-
-#define MIPS_REG_NR             32
-typedef struct {
-    rt_uint32_t  regs[MIPS_REG_NR];                             	/*  32 个通用目的寄存器         */
-    rt_uint32_t  CP0Status;                                        	/*  CP0 协处理器状态寄存器      */
-    rt_uint32_t  CP0DataHI;                                        	/*  除数高位寄存器              */
-    rt_uint32_t  CP0DataLO;                                        	/*  除数低位寄存器              */
-    rt_uint32_t  CP0BadVAddr;                                      	/*  出错地址寄存器              */
-    rt_uint32_t  CP0Cause;                                         	/*  产生中断或者异常查看的寄存器*/
-    rt_uint32_t  CP0EPC;                                           	/*  程序计数器寄存器			*/
-} mips_reg_ctx;
-
-#define MIPS_ARG_REG_NR         4
-typedef struct
-{
-	rt_uint32_t  args[MIPS_ARG_REG_NR];                              /*  4 个参数寄存器              */
-} mips_arg_ctx;
-
-struct linkctx
-{
-	rt_uint32_t id;
-	struct linkctx *next;
-};
-
-struct fpctx
-{
-  struct linkctx link;
-  rt_uint32_t fcsr;
-  rt_uint32_t reserved;
-};
-
-
-struct fp32ctx
-{
-  struct fpctx fp;
-  union
-    {
-      double d[16];	/* even doubles */
-      float s[32];	/* even singles, padded */
-    };
-};
-
-struct fp64ctx
-{
-  struct fpctx fp;
-  union
-    {
-      double d[32];	/* even doubles, followed by odd doubles */
-      float s[64];	/* even singles, followed by odd singles, padded */
-    };
-};
-
-#endif /* !defined(__ASSEMBLY__) && !defined(ASSEMBLY) */
-
-#define MIPS_STK_CTX_WORD_SIZE			38
-#define SZREG			4
-/*********************************************************************************************************
-  MIPS 的寄存器索引
-*********************************************************************************************************/
-#define REG_ZERO                0                                       /*  wired zero                  */
-#define REG_AT                  1                                       /*  assembler temp              */
-#define REG_V0                  2                                       /*  return reg 0                */
-#define REG_V1                  3                                       /*  return reg 1                */
-#define REG_A0                  4                                       /*  arg reg 0                   */
-#define REG_A1                  5                                       /*  arg reg 1                   */
-#define REG_A2                  6                                       /*  arg reg 2                   */
-#define REG_A3                  7                                       /*  arg reg 3                   */
-#define REG_T0                  8                                       /*  caller saved 0              */
-#define REG_T1                  9                                       /*  caller saved 1              */
-#define REG_T2                  10                                      /*  caller saved 2              */
-#define REG_T3                  11                                      /*  caller saved 3              */
-#define REG_T4                  12                                      /*  caller saved 4              */
-#define REG_T5                  13                                      /*  caller saved 5              */
-#define REG_T6                  14                                      /*  caller saved 6              */
-#define REG_T7                  15                                      /*  caller saved 7              */
-#define REG_S0                  16                                      /*  callee saved 0              */
-#define REG_S1                  17                                      /*  callee saved 1              */
-#define REG_S2                  18                                      /*  callee saved 2              */
-#define REG_S3                  19                                      /*  callee saved 3              */
-#define REG_S4                  20                                      /*  callee saved 4              */
-#define REG_S5                  21                                      /*  callee saved 5              */
-#define REG_S6                  22                                      /*  callee saved 6              */
-#define REG_S7                  23                                      /*  callee saved 7              */
-#define REG_T8                  24                                      /*  caller saved 8              */
-#define REG_T9                  25                                      /*  caller saved 9              */
-#define REG_K0                  26                                      /*  kernel temp 0               */
-#define REG_K1                  27                                      /*  kernel temp 1               */
-#define REG_GP                  28                                      /*  global pointer              */
-#define REG_SP                  29                                      /*  stack pointer               */
-#define REG_S8                  30                                      /*  callee saved 8              */
-#define REG_FP                  REG_S8                                  /*  callee saved 8              */
-#define REG_RA                  31                                      /*  return address              */
-
-#define STK_CTX_SIZE            (MIPS_STK_CTX_WORD_SIZE * SZREG)
-#define STK_OFFSET_SR           ((32 + 0) * SZREG)
-#define STK_OFFSET_HI           ((32 + 1) * SZREG)
-#define STK_OFFSET_LO           ((32 + 2) * SZREG)
-#define STK_OFFSET_BADVADDR     ((32 + 3) * SZREG)
-#define STK_OFFSET_CAUSE        ((32 + 4) * SZREG)
-#define STK_OFFSET_EPC          ((32 + 5) * SZREG)
-
-#define STK_OFFSET_LAST         ((MIPS_STK_CTX_WORD_SIZE - 1) * SZREG)
-
-#define FP32CTX_CSR	((SZREG)*2)
-#define FP64CTX_CSR	((SZREG)*2)
-
-#define LINKCTX_ID      ((SZREG)*0)
-#define LINKCTX_NEXT    ((SZREG)*1)
-#define LINKCTX_TYPE_MSA        0x004D5341
-#define LINKCTX_TYPE_FP32       0x46503332
-#define LINKCTX_TYPE_FP64       0x46503634
-#define LINKCTX_TYPE_FMSA       0x463D5341
-#define LINKCTX_TYPE_DSP        0x00445350
-#define LINKCTX_TYPE_STKSWP     0x53574150
-#define LINKCTX_TYPE_XPA	0x00585041
-
-#define FP32CTX_0	((SZREG)*4)
-#define FP32CTX_2	(FP32CTX_0 + (1 * 8))
-#define FP32CTX_4	(FP32CTX_0 + (2 * 8))
-#define FP32CTX_6	(FP32CTX_0 + (3 * 8))
-#define FP32CTX_8	(FP32CTX_0 + (4 * 8))
-#define FP32CTX_10	(FP32CTX_0 + (5 * 8))
-#define FP32CTX_12	(FP32CTX_0 + (6 * 8))
-#define FP32CTX_14	(FP32CTX_0 + (7 * 8))
-#define FP32CTX_16	(FP32CTX_0 + (8 * 8))
-#define FP32CTX_18	(FP32CTX_0 + (9 * 8))
-#define FP32CTX_20	(FP32CTX_0 + (10 * 8))
-#define FP32CTX_22	(FP32CTX_0 + (11 * 8))
-#define FP32CTX_24	(FP32CTX_0 + (12 * 8))
-#define FP32CTX_26	(FP32CTX_0 + (13 * 8))
-#define FP32CTX_28	(FP32CTX_0 + (14 * 8))
-#define FP32CTX_30	(FP32CTX_0 + (15 * 8))
-#define FP32CTX_SIZE	(FP32CTX_30 + (17 * 8))
-
-#define FP64CTX_0	((SZREG)*4)
-#define FP64CTX_2	(FP64CTX_0 + (1 * 8))
-#define FP64CTX_4	(FP64CTX_0 + (2 * 8))
-#define FP64CTX_6	(FP64CTX_0 + (3 * 8))
-#define FP64CTX_8	(FP64CTX_0 + (4 * 8))
-#define FP64CTX_10	(FP64CTX_0 + (5 * 8))
-#define FP64CTX_12	(FP64CTX_0 + (6 * 8))
-#define FP64CTX_14	(FP64CTX_0 + (7 * 8))
-#define FP64CTX_16	(FP64CTX_0 + (8 * 8))
-#define FP64CTX_18	(FP64CTX_0 + (9 * 8))
-#define FP64CTX_20	(FP64CTX_0 + (10 * 8))
-#define FP64CTX_22	(FP64CTX_0 + (11 * 8))
-#define FP64CTX_24	(FP64CTX_0 + (12 * 8))
-#define FP64CTX_26	(FP64CTX_0 + (13 * 8))
-#define FP64CTX_28	(FP64CTX_0 + (14 * 8))
-#define FP64CTX_30	(FP64CTX_0 + (15 * 8))
-#define FP64CTX_1	(FP64CTX_30 + (1 * 8))
-#define FP64CTX_3	(FP64CTX_30 + (2 * 8))
-#define FP64CTX_5	(FP64CTX_30 + (3 * 8))
-#define FP64CTX_7	(FP64CTX_30 + (4 * 8))
-#define FP64CTX_9	(FP64CTX_30 + (5 * 8))
-#define FP64CTX_11	(FP64CTX_30 + (6 * 8))
-#define FP64CTX_13	(FP64CTX_30 + (7 * 8))
-#define FP64CTX_15	(FP64CTX_30 + (8 * 8))
-#define FP64CTX_17	(FP64CTX_30 + (9 * 8))
-#define FP64CTX_19	(FP64CTX_30 + (10 * 8))
-#define FP64CTX_21	(FP64CTX_30 + (11 * 8))
-#define FP64CTX_23	(FP64CTX_30 + (12 * 8))
-#define FP64CTX_25	(FP64CTX_30 + (13 * 8))
-#define FP64CTX_27	(FP64CTX_30 + (14 * 8))
-#define FP64CTX_29	(FP64CTX_30 + (15 * 8))
-#define FP64CTX_31	(FP64CTX_30 + (16 * 8))
-#define FP64CTX_SIZE	(FP64CTX_31 + (17 * 8))
-
-#define FPCTX_SIZE()	(mips_getsr() & ST0_FR ? FP64CTX_SIZE : FP32CTX_SIZE)
 
 /*
  * The following macros are especially useful for __asm__
@@ -284,75 +178,128 @@ struct fp64ctx
 /*
  * Coprocessor 1 (FPU) register names
  */
-#define CP1_REVISION   $0
-#define CP1_STATUS     $31
+#define CP1_REVISION	$0
+#define CP1_UFR		$1
+#define CP1_UNFR	$4
+#define CP1_FCCR	$25
+#define CP1_FEXR	$26
+#define CP1_FENR	$28
+#define CP1_STATUS	$31
+
 
 /*
- * FPU Status Register Values
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
  */
+#define MIPS_FPIR_S		(_ULCAST_(1) << 16)
+#define MIPS_FPIR_D		(_ULCAST_(1) << 17)
+#define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
+#define MIPS_FPIR_3D		(_ULCAST_(1) << 19)
+#define MIPS_FPIR_W		(_ULCAST_(1) << 20)
+#define MIPS_FPIR_L		(_ULCAST_(1) << 21)
+#define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
+#define MIPS_FPIR_HAS2008	(_ULCAST_(1) << 23)
+#define MIPS_FPIR_UFRP		(_ULCAST_(1) << 28)
+#define MIPS_FPIR_FREP		(_ULCAST_(1) << 29)
+
 /*
- * Status Register Values
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
  */
-
-#define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
-#define FPU_CSR_COND    0x00800000      /* $fcc0 */
-#define FPU_CSR_COND0   0x00800000      /* $fcc0 */
-#define FPU_CSR_COND1   0x02000000      /* $fcc1 */
-#define FPU_CSR_COND2   0x04000000      /* $fcc2 */
-#define FPU_CSR_COND3   0x08000000      /* $fcc3 */
-#define FPU_CSR_COND4   0x10000000      /* $fcc4 */
-#define FPU_CSR_COND5   0x20000000      /* $fcc5 */
-#define FPU_CSR_COND6   0x40000000      /* $fcc6 */
-#define FPU_CSR_COND7   0x80000000      /* $fcc7 */
+#define MIPS_FCCR_CONDX_S	0
+#define MIPS_FCCR_CONDX		(_ULCAST_(255) << MIPS_FCCR_CONDX_S)
+#define MIPS_FCCR_COND0_S	0
+#define MIPS_FCCR_COND0		(_ULCAST_(1) << MIPS_FCCR_COND0_S)
+#define MIPS_FCCR_COND1_S	1
+#define MIPS_FCCR_COND1		(_ULCAST_(1) << MIPS_FCCR_COND1_S)
+#define MIPS_FCCR_COND2_S	2
+#define MIPS_FCCR_COND2		(_ULCAST_(1) << MIPS_FCCR_COND2_S)
+#define MIPS_FCCR_COND3_S	3
+#define MIPS_FCCR_COND3		(_ULCAST_(1) << MIPS_FCCR_COND3_S)
+#define MIPS_FCCR_COND4_S	4
+#define MIPS_FCCR_COND4		(_ULCAST_(1) << MIPS_FCCR_COND4_S)
+#define MIPS_FCCR_COND5_S	5
+#define MIPS_FCCR_COND5		(_ULCAST_(1) << MIPS_FCCR_COND5_S)
+#define MIPS_FCCR_COND6_S	6
+#define MIPS_FCCR_COND6		(_ULCAST_(1) << MIPS_FCCR_COND6_S)
+#define MIPS_FCCR_COND7_S	7
+#define MIPS_FCCR_COND7		(_ULCAST_(1) << MIPS_FCCR_COND7_S)
 
 /*
- * X the exception cause indicator
- * E the exception enable
- * S the sticky/flag bit
-*/
-#define FPU_CSR_ALL_X   0x0003f000
-#define FPU_CSR_UNI_X   0x00020000
-#define FPU_CSR_INV_X   0x00010000
-#define FPU_CSR_DIV_X   0x00008000
-#define FPU_CSR_OVF_X   0x00004000
-#define FPU_CSR_UDF_X   0x00002000
-#define FPU_CSR_INE_X   0x00001000
-
-#define FPU_CSR_ALL_E   0x00000f80
-#define FPU_CSR_INV_E   0x00000800
-#define FPU_CSR_DIV_E   0x00000400
-#define FPU_CSR_OVF_E   0x00000200
-#define FPU_CSR_UDF_E   0x00000100
-#define FPU_CSR_INE_E   0x00000080
-
-#define FPU_CSR_ALL_S   0x0000007c
-#define FPU_CSR_INV_S   0x00000040
-#define FPU_CSR_DIV_S   0x00000020
-#define FPU_CSR_OVF_S   0x00000010
-#define FPU_CSR_UDF_S   0x00000008
-#define FPU_CSR_INE_S   0x00000004
-
-/* rounding mode */
-#define FPU_CSR_RN      0x0     /* nearest */
-#define FPU_CSR_RZ      0x1     /* towards zero */
-#define FPU_CSR_RU      0x2     /* towards +Infinity */
-#define FPU_CSR_RD      0x3     /* towards -Infinity */
-
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
+ */
+#define MIPS_FENR_FS_S		2
+#define MIPS_FENR_FS		(_ULCAST_(1) << MIPS_FENR_FS_S)
 
 /*
- * Values for PageMask register
+ * FPU Status Register Values
  */
-#ifdef CONFIG_CPU_VR41XX
+#define FPU_CSR_COND_S	23					/* $fcc0 */
+#define FPU_CSR_COND	(_ULCAST_(1) << FPU_CSR_COND_S)
+
+#define FPU_CSR_FS_S	24		/* flush denormalised results to 0 */
+#define FPU_CSR_FS	(_ULCAST_(1) << FPU_CSR_FS_S)
+
+#define FPU_CSR_FO      0x00400000
+#define FPU_CSR_FN      0x00200000
+
+#define FPU_CSR_CONDX_S	25					/* $fcc[7:1] */
+#define FPU_CSR_CONDX	(_ULCAST_(127) << FPU_CSR_CONDX_S)
+#define FPU_CSR_COND1_S	25					/* $fcc1 */
+#define FPU_CSR_COND1	(_ULCAST_(1) << FPU_CSR_COND1_S)
+#define FPU_CSR_COND2_S	26					/* $fcc2 */
+#define FPU_CSR_COND2	(_ULCAST_(1) << FPU_CSR_COND2_S)
+#define FPU_CSR_COND3_S	27					/* $fcc3 */
+#define FPU_CSR_COND3	(_ULCAST_(1) << FPU_CSR_COND3_S)
+#define FPU_CSR_COND4_S	28					/* $fcc4 */
+#define FPU_CSR_COND4	(_ULCAST_(1) << FPU_CSR_COND4_S)
+#define FPU_CSR_COND5_S	29					/* $fcc5 */
+#define FPU_CSR_COND5	(_ULCAST_(1) << FPU_CSR_COND5_S)
+#define FPU_CSR_COND6_S	30					/* $fcc6 */
+#define FPU_CSR_COND6	(_ULCAST_(1) << FPU_CSR_COND6_S)
+#define FPU_CSR_COND7_S	31					/* $fcc7 */
+#define FPU_CSR_COND7	(_ULCAST_(1) << FPU_CSR_COND7_S)
 
-/* Why doesn't stupidity hurt ... */
+/*
+ * Bits 22:20 of the FPU Status Register will be read as 0,
+ * and should be written as zero.
+ */
+#define FPU_CSR_RSVD	(_ULCAST_(7) << 20)
 
-#define PM_1K		0x00000000
-#define PM_4K		0x00001800
-#define PM_16K		0x00007800
-#define PM_64K		0x0001f800
-#define PM_256K		0x0007f800
+#define FPU_CSR_ABS2008	(_ULCAST_(1) << 19)
+#define FPU_CSR_NAN2008	(_ULCAST_(1) << 18)
 
-#else
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X	0x0003f000
+#define FPU_CSR_UNI_X	0x00020000
+#define FPU_CSR_INV_X	0x00010000
+#define FPU_CSR_DIV_X	0x00008000
+#define FPU_CSR_OVF_X	0x00004000
+#define FPU_CSR_UDF_X	0x00002000
+#define FPU_CSR_INE_X	0x00001000
+
+#define FPU_CSR_ALL_E	0x00000f80
+#define FPU_CSR_INV_E	0x00000800
+#define FPU_CSR_DIV_E	0x00000400
+#define FPU_CSR_OVF_E	0x00000200
+#define FPU_CSR_UDF_E	0x00000100
+#define FPU_CSR_INE_E	0x00000080
+
+#define FPU_CSR_ALL_S	0x0000007c
+#define FPU_CSR_INV_S	0x00000040
+#define FPU_CSR_DIV_S	0x00000020
+#define FPU_CSR_OVF_S	0x00000010
+#define FPU_CSR_UDF_S	0x00000008
+#define FPU_CSR_INE_S	0x00000004
+
+/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
+#define FPU_CSR_RM	0x00000003
+#define FPU_CSR_RN	0x0	/* nearest */
+#define FPU_CSR_RZ	0x1	/* towards zero */
+#define FPU_CSR_RU	0x2	/* towards +Infinity */
+#define FPU_CSR_RD	0x3	/* towards -Infinity */
 
 #define PM_4K		0x00000000
 #define PM_16K		0x00006000
@@ -364,7 +311,6 @@ struct fp64ctx
 #define PM_64M		0x07ffe000
 #define PM_256M		0x1fffe000
 
-#endif
 
 /*
  * Values used for computation of new tlb entries
@@ -440,38 +386,6 @@ struct fp64ctx
 #define ST0_IL			(_ULCAST_(1) << 23)
 #define ST0_DL			(_ULCAST_(1) << 24)
 
-/*
- * Bitfields in the TX39 family CP0 Configuration Register 3
- */
-#define TX39_CONF_ICS_SHIFT	19
-#define TX39_CONF_ICS_MASK	0x00380000
-#define TX39_CONF_ICS_1KB 	0x00000000
-#define TX39_CONF_ICS_2KB 	0x00080000
-#define TX39_CONF_ICS_4KB 	0x00100000
-#define TX39_CONF_ICS_8KB 	0x00180000
-#define TX39_CONF_ICS_16KB 	0x00200000
-
-#define TX39_CONF_DCS_SHIFT	16
-#define TX39_CONF_DCS_MASK	0x00070000
-#define TX39_CONF_DCS_1KB 	0x00000000
-#define TX39_CONF_DCS_2KB 	0x00010000
-#define TX39_CONF_DCS_4KB 	0x00020000
-#define TX39_CONF_DCS_8KB 	0x00030000
-#define TX39_CONF_DCS_16KB 	0x00040000
-
-#define TX39_CONF_CWFON 	0x00004000
-#define TX39_CONF_WBON  	0x00002000
-#define TX39_CONF_RF_SHIFT	10
-#define TX39_CONF_RF_MASK	0x00000c00
-#define TX39_CONF_DOZE		0x00000200
-#define TX39_CONF_HALT		0x00000100
-#define TX39_CONF_LOCK		0x00000080
-#define TX39_CONF_ICE		0x00000020
-#define TX39_CONF_DCE		0x00000010
-#define TX39_CONF_IRSIZE_SHIFT	2
-#define TX39_CONF_IRSIZE_MASK	0x0000000c
-#define TX39_CONF_DRSIZE_SHIFT	0
-#define TX39_CONF_DRSIZE_MASK	0x00000003
 
 /*
  * Status register bits available in all MIPS CPUs.
@@ -729,77 +643,77 @@ struct fp64ctx
 
 #define __read_32bit_c0_register(source, sel)				\
 ({ int __res;								\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			"mfc0\t%0, " #source "\n\t"			\
-			: "=r" (__res));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mfc0\t%0, " #source ", " #sel "\n\t"		\
-			".set\tmips0\n\t"				\
-			: "=r" (__res));				\
-	__res;								\
+    if (sel == 0)							\
+        __asm__ __volatile__(					\
+            "mfc0\t%0, " #source "\n\t"			\
+            : "=r" (__res));				\
+    else								\
+        __asm__ __volatile__(					\
+            ".set\tmips32\n\t"				\
+            "mfc0\t%0, " #source ", " #sel "\n\t"		\
+            ".set\tmips0\n\t"				\
+            : "=r" (__res));				\
+    __res;								\
 })
 
 #define __read_64bit_c0_register(source, sel)				\
 ({ unsigned long __res;							\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			".set\tmips3\n\t"				\
-			"dmfc0\t%0, " #source "\n\t"			\
-			".set\tmips0"					\
-			: "=r" (__res));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmfc0\t%0, " #source ", " #sel "\n\t"		\
-			".set\tmips0"					\
-			: "=r" (__res));				\
-	__res;								\
+    if (sel == 0)							\
+        __asm__ __volatile__(					\
+            ".set\tmips3\n\t"				\
+            "dmfc0\t%0, " #source "\n\t"			\
+            ".set\tmips0"					\
+            : "=r" (__res));				\
+    else								\
+        __asm__ __volatile__(					\
+            ".set\tmips64\n\t"				\
+            "dmfc0\t%0, " #source ", " #sel "\n\t"		\
+            ".set\tmips0"					\
+            : "=r" (__res));				\
+    __res;								\
 })
 
 #define __write_32bit_c0_register(register, sel, value)			\
 do {									\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			"mtc0\t%z0, " #register "\n\t"			\
-			: : "Jr" (value));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
-			".set\tmips0"					\
-			: : "Jr" (value));				\
+    if (sel == 0)							\
+        __asm__ __volatile__(					\
+            "mtc0\t%z0, " #register "\n\t"			\
+            : : "Jr" (value));				\
+    else								\
+        __asm__ __volatile__(					\
+            ".set\tmips32\n\t"				\
+            "mtc0\t%z0, " #register ", " #sel "\n\t"	\
+            ".set\tmips0"					\
+            : : "Jr" (value));				\
 } while (0)
 
 #define __write_64bit_c0_register(register, sel, value)			\
 do {									\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			".set\tmips3\n\t"				\
-			"dmtc0\t%z0, " #register "\n\t"			\
-			".set\tmips0"					\
-			: : "Jr" (value));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmtc0\t%z0, " #register ", " #sel "\n\t"	\
-			".set\tmips0"					\
-			: : "Jr" (value));				\
+    if (sel == 0)							\
+        __asm__ __volatile__(					\
+            ".set\tmips3\n\t"				\
+            "dmtc0\t%z0, " #register "\n\t"			\
+            ".set\tmips0"					\
+            : : "Jr" (value));				\
+    else								\
+        __asm__ __volatile__(					\
+            ".set\tmips64\n\t"				\
+            "dmtc0\t%z0, " #register ", " #sel "\n\t"	\
+            ".set\tmips0"					\
+            : : "Jr" (value));				\
 } while (0)
 
 #define __read_ulong_c0_register(reg, sel)				\
-	((sizeof(unsigned long) == 4) ?					\
-	__read_32bit_c0_register(reg, sel) :				\
-	__read_64bit_c0_register(reg, sel))
+    ((sizeof(unsigned long) == 4) ?					\
+    __read_32bit_c0_register(reg, sel) :				\
+    __read_64bit_c0_register(reg, sel))
 
 #define __write_ulong_c0_register(reg, sel, val)			\
 do {									\
-	if (sizeof(unsigned long) == 4)					\
-		__write_32bit_c0_register(reg, sel, val);		\
-	else								\
-		__write_64bit_c0_register(reg, sel, val);		\
+    if (sizeof(unsigned long) == 4)					\
+        __write_32bit_c0_register(reg, sel, val);		\
+    else								\
+        __write_64bit_c0_register(reg, sel, val);		\
 } while (0)
 
 /*
@@ -808,59 +722,59 @@ do {									\
  */
 #define __read_64bit_c0_split(source, sel)				\
 ({									\
-	unsigned long long val;						\
-	unsigned long flags;						\
-									\
-	local_irq_save(flags);						\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmfc0\t%M0, " #source "\n\t"			\
-			"dsll\t%L0, %M0, 32\n\t"			\
-			"dsrl\t%M0, %M0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			".set\tmips0"					\
-			: "=r" (val));					\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dmfc0\t%M0, " #source ", " #sel "\n\t"		\
-			"dsll\t%L0, %M0, 32\n\t"			\
-			"dsrl\t%M0, %M0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			".set\tmips0"					\
-			: "=r" (val));					\
-	local_irq_restore(flags);					\
-									\
-	val;								\
+    unsigned long long val;						\
+    unsigned long flags;						\
+                                    \
+    local_irq_save(flags);						\
+    if (sel == 0)							\
+        __asm__ __volatile__(					\
+            ".set\tmips64\n\t"				\
+            "dmfc0\t%M0, " #source "\n\t"			\
+            "dsll\t%L0, %M0, 32\n\t"			\
+            "dsrl\t%M0, %M0, 32\n\t"			\
+            "dsrl\t%L0, %L0, 32\n\t"			\
+            ".set\tmips0"					\
+            : "=r" (val));					\
+    else								\
+        __asm__ __volatile__(					\
+            ".set\tmips64\n\t"				\
+            "dmfc0\t%M0, " #source ", " #sel "\n\t"		\
+            "dsll\t%L0, %M0, 32\n\t"			\
+            "dsrl\t%M0, %M0, 32\n\t"			\
+            "dsrl\t%L0, %L0, 32\n\t"			\
+            ".set\tmips0"					\
+            : "=r" (val));					\
+    local_irq_restore(flags);					\
+                                    \
+    val;								\
 })
 
 #define __write_64bit_c0_split(source, sel, val)			\
 do {									\
-	unsigned long flags;						\
-									\
-	local_irq_save(flags);						\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dsll\t%L0, %L0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			"dsll\t%M0, %M0, 32\n\t"			\
-			"or\t%L0, %L0, %M0\n\t"				\
-			"dmtc0\t%L0, " #source "\n\t"			\
-			".set\tmips0"					\
-			: : "r" (val));					\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips64\n\t"				\
-			"dsll\t%L0, %L0, 32\n\t"			\
-			"dsrl\t%L0, %L0, 32\n\t"			\
-			"dsll\t%M0, %M0, 32\n\t"			\
-			"or\t%L0, %L0, %M0\n\t"				\
-			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\
-			".set\tmips0"					\
-			: : "r" (val));					\
-	local_irq_restore(flags);					\
+    unsigned long flags;						\
+                                    \
+    local_irq_save(flags);						\
+    if (sel == 0)							\
+        __asm__ __volatile__(					\
+            ".set\tmips64\n\t"				\
+            "dsll\t%L0, %L0, 32\n\t"			\
+            "dsrl\t%L0, %L0, 32\n\t"			\
+            "dsll\t%M0, %M0, 32\n\t"			\
+            "or\t%L0, %L0, %M0\n\t"				\
+            "dmtc0\t%L0, " #source "\n\t"			\
+            ".set\tmips0"					\
+            : : "r" (val));					\
+    else								\
+        __asm__ __volatile__(					\
+            ".set\tmips64\n\t"				\
+            "dsll\t%L0, %L0, 32\n\t"			\
+            "dsrl\t%L0, %L0, 32\n\t"			\
+            "dsll\t%M0, %M0, 32\n\t"			\
+            "or\t%L0, %L0, %M0\n\t"				\
+            "dmtc0\t%L0, " #source ", " #sel "\n\t"		\
+            ".set\tmips0"					\
+            : : "r" (val));					\
+    local_irq_restore(flags);					\
 } while (0)
 
 #define read_c0_index()		__read_32bit_c0_register($0, 0)
@@ -906,6 +820,9 @@ do {									\
 
 #define read_c0_prid()		__read_32bit_c0_register($15, 0)
 
+#define read_c0_ebase()		__read_32bit_c0_register($15, 1)
+#define write_c0_ebase(val)	__write_32bit_c0_register($15, 1, val)
+
 #define read_c0_config()	__read_32bit_c0_register($16, 0)
 #define read_c0_config1()	__read_32bit_c0_register($16, 1)
 #define read_c0_config2()	__read_32bit_c0_register($16, 2)
@@ -1001,20 +918,20 @@ do {									\
 #define read_32bit_cp0_register(source)                         \
 ({ int __res;                                                   \
         __asm__ __volatile__(                                   \
-	".set\tpush\n\t"					\
-	".set\treorder\n\t"					\
+    ".set\tpush\n\t"					\
+    ".set\treorder\n\t"					\
         "mfc0\t%0,"STR(source)"\n\t"                            \
-	".set\tpop"						\
+    ".set\tpop"						\
         : "=r" (__res));                                        \
         __res;})
 
 #define read_32bit_cp0_set1_register(source)                    \
 ({ int __res;                                                   \
         __asm__ __volatile__(                                   \
-	".set\tpush\n\t"					\
-	".set\treorder\n\t"					\
+    ".set\tpush\n\t"					\
+    ".set\treorder\n\t"					\
         "cfc0\t%0,"STR(source)"\n\t"                            \
-	".set\tpop"						\
+    ".set\tpop"						\
         : "=r" (__res));                                        \
         __res;})
 
@@ -1033,13 +950,13 @@ do {									\
 #define write_32bit_cp0_register(register,value)                \
         __asm__ __volatile__(                                   \
         "mtc0\t%0,"STR(register)"\n\t"				\
-	"nop"							\
+    "nop"							\
         : : "r" (value));
 
 #define write_32bit_cp0_set1_register(register,value)           \
         __asm__ __volatile__(                                   \
         "ctc0\t%0,"STR(register)"\n\t"				\
-	"nop"							\
+    "nop"							\
         : : "r" (value));
 
 #define write_64bit_cp0_register(register,value)                \
@@ -1055,16 +972,16 @@ do {									\
 #define read_mips32_cp0_config1()                               \
 ({ int __res;                                                   \
         __asm__ __volatile__(                                   \
-	".set\tnoreorder\n\t"                                   \
-	".set\tnoat\n\t"                                        \
-	"#.set\tmips64\n\t"					\
-	"#mfc0\t$1, $16, 1\n\t"					\
-	"#.set\tmips0\n\t"					\
-     	".word\t0x40018001\n\t"                                 \
-	"move\t%0,$1\n\t"                                       \
-	".set\tat\n\t"                                          \
-	".set\treorder"                                         \
-	:"=r" (__res));                                         \
+    ".set\tnoreorder\n\t"                                   \
+    ".set\tnoat\n\t"                                        \
+    "#.set\tmips64\n\t"					\
+    "#mfc0\t$1, $16, 1\n\t"					\
+    "#.set\tmips0\n\t"					\
+         ".word\t0x40018001\n\t"                                 \
+    "move\t%0,$1\n\t"                                       \
+    ".set\tat\n\t"                                          \
+    ".set\treorder"                                         \
+    :"=r" (__res));                                         \
         __res;})
 
 #endif
@@ -1073,45 +990,51 @@ do {									\
  */
 #define read_32bit_cp1_register(source)                         \
 ({ int __res;                                                   \
-	__asm__ __volatile__(                                   \
-	".set\tpush\n\t"					\
-	".set\treorder\n\t"					\
+    __asm__ __volatile__(                                   \
+    ".set\tpush\n\t"					\
+    ".set\treorder\n\t"					\
         "cfc1\t%0,"STR(source)"\n\t"                            \
-	".set\tpop"						\
+    ".set\tpop"						\
         : "=r" (__res));                                        \
         __res;})
 
+#define write_32bit_cp1_register(register,value)                \
+        __asm__ __volatile__(                                   \
+        "ctc1\t%0,"STR(register)"\n\t"				\
+    "nop"							\
+        : : "r" (value));
+
 /* TLB operations. */
 static inline void tlb_probe(void)
 {
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		"tlbp\n\t"
-		".set reorder");
+    __asm__ __volatile__(
+        ".set noreorder\n\t"
+        "tlbp\n\t"
+        ".set reorder");
 }
 
 static inline void tlb_read(void)
 {
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		"tlbr\n\t"
-		".set reorder");
+    __asm__ __volatile__(
+        ".set noreorder\n\t"
+        "tlbr\n\t"
+        ".set reorder");
 }
 
 static inline void tlb_write_indexed(void)
 {
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		"tlbwi\n\t"
-		".set reorder");
+    __asm__ __volatile__(
+        ".set noreorder\n\t"
+        "tlbwi\n\t"
+        ".set reorder");
 }
 
 static inline void tlb_write_random(void)
 {
-	__asm__ __volatile__(
-		".set noreorder\n\t"
-		"tlbwr\n\t"
-		".set reorder");
+    __asm__ __volatile__(
+        ".set noreorder\n\t"
+        "tlbwr\n\t"
+        ".set reorder");
 }
 
 /*
@@ -1121,38 +1044,38 @@ static inline void tlb_write_random(void)
 static inline unsigned int					\
 set_c0_##name(unsigned int set)					\
 {								\
-	unsigned int res;					\
-								\
-	res = read_c0_##name();					\
-	res |= set;						\
-	write_c0_##name(res);					\
-								\
-	return res;						\
+    unsigned int res;					\
+                                \
+    res = read_c0_##name();					\
+    res |= set;						\
+    write_c0_##name(res);					\
+                                \
+    return res;						\
 }								\
-								\
+                                \
 static inline unsigned int					\
 clear_c0_##name(unsigned int clear)				\
 {								\
-	unsigned int res;					\
-								\
-	res = read_c0_##name();					\
-	res &= ~clear;						\
-	write_c0_##name(res);					\
-								\
-	return res;						\
+    unsigned int res;					\
+                                \
+    res = read_c0_##name();					\
+    res &= ~clear;						\
+    write_c0_##name(res);					\
+                                \
+    return res;						\
 }								\
-								\
+                                \
 static inline unsigned int					\
 change_c0_##name(unsigned int change, unsigned int new)		\
 {								\
-	unsigned int res;					\
-								\
-	res = read_c0_##name();					\
-	res &= ~change;						\
-	res |= (new & change);					\
-	write_c0_##name(res);					\
-								\
-	return res;						\
+    unsigned int res;					\
+                                \
+    res = read_c0_##name();					\
+    res &= ~change;						\
+    res |= (new & change);					\
+    write_c0_##name(res);					\
+                                \
+    return res;						\
 }
 
 __BUILD_SET_C0(status,CP0_STATUS)
@@ -1163,6 +1086,17 @@ __BUILD_SET_C0(config,CP0_CONFIG)
 #define set_cp0_cause(x)	set_c0_cause(x)
 #define set_cp0_config(x)	set_c0_config(x)
 
+#define read_c1_status()	read_32bit_cp1_register(31)
+#define write_c1_status(x)	write_32bit_cp1_register(31, x)
+
+#define readb(reg)		(*((volatile unsigned char *) (reg)))
+#define readw(reg)		(*((volatile unsigned short *) (reg)))
+#define readl(reg)		(*((volatile unsigned int *) (reg)))
+
+#define writeb(data, reg)	((*((volatile unsigned char *)(reg))) = (unsigned char)(data))
+#define writew(data, reg)	((*((volatile unsigned short *)(reg))) = (unsigned short)(data))
+#define writel(data, reg)	((*((volatile unsigned int *)(reg))) = (unsigned int)(data))
+
 #endif /* !__ASSEMBLY__ */
 
 #endif /* _MIPS_REGS_H_ */

libcpu/mips/common/mips_types.h

@@ -19,7 +19,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016Äê9ÔÂ7ÈÕ     Urey         the first version
+ * 2016-09-07     Urey         the first version
  */
 
 #ifndef _MIPS_TYPES_H_
@@ -87,30 +87,17 @@ typedef unsigned long long u64;
 
 #endif
 
-#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
-    || defined(CONFIG_64BIT)
-typedef u64 dma_addr_t;
-
-typedef u64 phys_addr_t;
-typedef u64 phys_size_t;
-
-#else
 typedef u32 dma_addr_t;
 
 typedef u32 phys_addr_t;
 typedef u32 phys_size_t;
 
-#endif
-typedef u64 dma64_addr_t;
 
 /*
  * Don't use phys_t.  You've been warned.
  */
-#ifdef CONFIG_64BIT_PHYS_ADDR
-typedef unsigned long long phys_t;
-#else
+
 typedef unsigned long phys_t;
-#endif
 
 #endif /* __ASSEMBLY__ */
 

libcpu/mips/common/mipscfg.h

@@ -1,32 +0,0 @@
-/*
- * File      : mipscfg.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-27     swkyer       first version
- */
-#ifndef __MIPSCFG_H__
-#define __MIPSCFG_H__
-
-
-typedef struct mips32_core_cfg
-{
-    rt_uint16_t icache_line_size;
-    rt_uint16_t icache_lines_per_way;
-    rt_uint16_t icache_ways;
-    rt_uint16_t dcache_line_size;
-    rt_uint16_t dcache_lines_per_way;
-    rt_uint16_t dcache_ways;
-
-    rt_uint16_t max_tlb_entries;	/* number of tlb entry */
-} mips32_core_cfg_t;
-
-extern mips32_core_cfg_t g_mips_core;
-
-#endif /* end of __MIPSCFG_H__ */

libcpu/mips/common/mipsregs.h

@@ -1,706 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Modified for further R[236]000 support by Paul M. Antoine, 1996.
- * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000, 07 MIPS Technologies, Inc.
- * Copyright (C) 2003, 2004  Maciej W. Rozycki
- *
- * Change Logs:
- * Date           Author       Notes
- *
- */
-#ifndef __MIPSREGS_H__
-#define __MIPSREGS_H__
-
-/*
- * The following macros are especially useful for __asm__
- * inline assembler.
- */
-#ifndef __STR
-#define __STR(x) #x
-#endif
-#ifndef STR
-#define STR(x) __STR(x)
-#endif
-
-/*
- *  Configure language
- */
-#ifdef __ASSEMBLY__
-#define _ULCAST_
-#else
-#define _ULCAST_ (unsigned long)
-#endif
-
-/*
- * Coprocessor 0 register names
- */
-#define CP0_INDEX 			$0
-#define CP0_RANDOM		 	$1
-#define CP0_ENTRYLO0 		$2
-#define CP0_ENTRYLO1 		$3
-#define CP0_CONF 			$3
-#define CP0_CONTEXT 		$4
-#define CP0_PAGEMASK 		$5
-#define CP0_WIRED 			$6
-#define CP0_INFO 			$7
-#define CP0_BADVADDR 		$8
-#define CP0_COUNT 			$9
-#define CP0_ENTRYHI 		$10
-#define CP0_COMPARE 		$11
-#define CP0_STATUS 			$12
-#define CP0_CAUSE 			$13
-#define CP0_EPC 			$14
-#define CP0_PRID 			$15
-#define CP0_CONFIG 			$16
-#define CP0_LLADDR 			$17
-#define CP0_WATCHLO 		$18
-#define CP0_WATCHHI 		$19
-#define CP0_XCONTEXT 		$20
-#define CP0_FRAMEMASK 		$21
-#define CP0_DIAGNOSTIC 		$22
-#define CP0_DEBUG 			$23
-#define CP0_DEPC 			$24
-#define CP0_PERFORMANCE 	$25
-#define CP0_ECC 			$26
-#define CP0_CACHEERR 		$27
-#define CP0_TAGLO 			$28
-#define CP0_TAGHI 			$29
-#define CP0_ERROREPC 		$30
-#define CP0_DESAVE 			$31
-
-/*
- * R4640/R4650 cp0 register names.  These registers are listed
- * here only for completeness; without MMU these CPUs are not useable
- * by Linux.  A future ELKS port might take make Linux run on them
- * though ...
- */
-#define CP0_IBASE 			$0
-#define CP0_IBOUND 			$1
-#define CP0_DBASE 			$2
-#define CP0_DBOUND 			$3
-#define CP0_CALG 			$17
-#define CP0_IWATCH 			$18
-#define CP0_DWATCH 			$19
-
-/*
- * Coprocessor 0 Set 1 register names
- */
-#define CP0_S1_DERRADDR0  	$26
-#define CP0_S1_DERRADDR1  	$27
-#define CP0_S1_INTCONTROL 	$20
-
-/*
- * Coprocessor 0 Set 2 register names
- */
-#define CP0_S2_SRSCTL	  	$12	/* MIPSR2 */
-
-/*
- * Coprocessor 0 Set 3 register names
- */
-#define CP0_S3_SRSMAP	  	$12	/* MIPSR2 */
-
-/*
- *  TX39 Series
- */
-#define CP0_TX39_CACHE		$7
-
-/*
- * Coprocessor 1 (FPU) register names
- */
-#define CP1_REVISION   		$0
-#define CP1_STATUS     		$31
-
-/*
- * FPU Status Register Values
- */
-/*
- * Status Register Values
- */
-
-#define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
-#define FPU_CSR_COND    0x00800000      /* $fcc0 */
-#define FPU_CSR_COND0   0x00800000      /* $fcc0 */
-#define FPU_CSR_COND1   0x02000000      /* $fcc1 */
-#define FPU_CSR_COND2   0x04000000      /* $fcc2 */
-#define FPU_CSR_COND3   0x08000000      /* $fcc3 */
-#define FPU_CSR_COND4   0x10000000      /* $fcc4 */
-#define FPU_CSR_COND5   0x20000000      /* $fcc5 */
-#define FPU_CSR_COND6   0x40000000      /* $fcc6 */
-#define FPU_CSR_COND7   0x80000000      /* $fcc7 */
-
-
-/* FS/FO/FN */
-#define FPU_CSR_FS      0x01000000
-#define FPU_CSR_FO      0x00400000
-#define FPU_CSR_FN      0x00200000
-
-/*
- * Bits 18 - 20 of the FPU Status Register will be read as 0,
- * and should be written as zero.
- */
-#define FPU_CSR_RSVD	0x001c0000
-
-/*
- * X the exception cause indicator
- * E the exception enable
- * S the sticky/flag bit
-*/
-#define FPU_CSR_ALL_X   0x0003f000
-#define FPU_CSR_UNI_X   0x00020000
-#define FPU_CSR_INV_X   0x00010000
-#define FPU_CSR_DIV_X   0x00008000
-#define FPU_CSR_OVF_X   0x00004000
-#define FPU_CSR_UDF_X   0x00002000
-#define FPU_CSR_INE_X   0x00001000
-
-#define FPU_CSR_ALL_E   0x00000f80
-#define FPU_CSR_INV_E   0x00000800
-#define FPU_CSR_DIV_E   0x00000400
-#define FPU_CSR_OVF_E   0x00000200
-#define FPU_CSR_UDF_E   0x00000100
-#define FPU_CSR_INE_E   0x00000080
-
-#define FPU_CSR_ALL_S   0x0000007c
-#define FPU_CSR_INV_S   0x00000040
-#define FPU_CSR_DIV_S   0x00000020
-#define FPU_CSR_OVF_S   0x00000010
-#define FPU_CSR_UDF_S   0x00000008
-#define FPU_CSR_INE_S   0x00000004
-
-/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
-#define FPU_CSR_RM	0x00000003
-#define FPU_CSR_RN      0x0     /* nearest */
-#define FPU_CSR_RZ      0x1     /* towards zero */
-#define FPU_CSR_RU      0x2     /* towards +Infinity */
-#define FPU_CSR_RD      0x3     /* towards -Infinity */
-
-
-/*
- * R4x00 interrupt enable / cause bits
- */
-#define IE_SW0          (_ULCAST_(1) <<  8)
-#define IE_SW1          (_ULCAST_(1) <<  9)
-#define IE_IRQ0         (_ULCAST_(1) << 10)
-#define IE_IRQ1         (_ULCAST_(1) << 11)
-#define IE_IRQ2         (_ULCAST_(1) << 12)
-#define IE_IRQ3         (_ULCAST_(1) << 13)
-#define IE_IRQ4         (_ULCAST_(1) << 14)
-#define IE_IRQ5         (_ULCAST_(1) << 15)
-
-/*
- * R4x00 interrupt cause bits
- */
-#define C_SW0           (_ULCAST_(1) <<  8)
-#define C_SW1           (_ULCAST_(1) <<  9)
-#define C_IRQ0          (_ULCAST_(1) << 10)
-#define C_IRQ1          (_ULCAST_(1) << 11)
-#define C_IRQ2          (_ULCAST_(1) << 12)
-#define C_IRQ3          (_ULCAST_(1) << 13)
-#define C_IRQ4          (_ULCAST_(1) << 14)
-#define C_IRQ5          (_ULCAST_(1) << 15)
-
-/*
- * Bitfields in the R4xx0 cp0 status register
- */
-#define ST0_IE					0x00000001
-#define ST0_EXL					0x00000002
-#define ST0_ERL					0x00000004
-#define ST0_KSU					0x00000018
-#  define KSU_USER					0x00000010
-#  define KSU_SUPERVISOR			0x00000008
-#  define KSU_KERNEL				0x00000000
-#define ST0_UX					0x00000020
-#define ST0_SX					0x00000040
-#define ST0_KX 					0x00000080
-#define ST0_DE					0x00010000
-#define ST0_CE					0x00020000
-
-/*
- * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
- * cacheops in userspace.  This bit exists only on RM7000 and RM9000
- * processors.
- */
-#define ST0_CO					0x08000000
-
-/*
- * Bitfields in the R[23]000 cp0 status register.
- */
-#define ST0_IEC                 0x00000001
-#define ST0_KUC					0x00000002
-#define ST0_IEP					0x00000004
-#define ST0_KUP					0x00000008
-#define ST0_IEO					0x00000010
-#define ST0_KUO					0x00000020
-/* bits 6 & 7 are reserved on R[23]000 */
-#define ST0_ISC					0x00010000
-#define ST0_SWC					0x00020000
-#define ST0_CM					0x00080000
-
-/*
- * Bits specific to the R4640/R4650
- */
-#define ST0_UM					(_ULCAST_(1) <<  4)
-#define ST0_IL					(_ULCAST_(1) << 23)
-#define ST0_DL					(_ULCAST_(1) << 24)
-
-/*
- * Enable the MIPS DSP ASE
- */
-#define ST0_MX					0x01000000
-
-/*
- * Bitfields in the TX39 family CP0 Configuration Register 3
- */
-#define TX39_CONF_ICS_SHIFT		19
-#define TX39_CONF_ICS_MASK		0x00380000
-#define TX39_CONF_ICS_1KB 		0x00000000
-#define TX39_CONF_ICS_2KB 		0x00080000
-#define TX39_CONF_ICS_4KB 		0x00100000
-#define TX39_CONF_ICS_8KB 		0x00180000
-#define TX39_CONF_ICS_16KB 		0x00200000
-
-#define TX39_CONF_DCS_SHIFT		16
-#define TX39_CONF_DCS_MASK		0x00070000
-#define TX39_CONF_DCS_1KB 		0x00000000
-#define TX39_CONF_DCS_2KB 		0x00010000
-#define TX39_CONF_DCS_4KB 		0x00020000
-#define TX39_CONF_DCS_8KB 		0x00030000
-#define TX39_CONF_DCS_16KB 		0x00040000
-
-#define TX39_CONF_CWFON 		0x00004000
-#define TX39_CONF_WBON  		0x00002000
-#define TX39_CONF_RF_SHIFT		10
-#define TX39_CONF_RF_MASK		0x00000c00
-#define TX39_CONF_DOZE			0x00000200
-#define TX39_CONF_HALT			0x00000100
-#define TX39_CONF_LOCK			0x00000080
-#define TX39_CONF_ICE			0x00000020
-#define TX39_CONF_DCE			0x00000010
-#define TX39_CONF_IRSIZE_SHIFT	2
-#define TX39_CONF_IRSIZE_MASK	0x0000000c
-#define TX39_CONF_DRSIZE_SHIFT	0
-#define TX39_CONF_DRSIZE_MASK	0x00000003
-
-/*
- * Status register bits available in all MIPS CPUs.
- */
-#define  ST0_IM			    0x0000ff00
-#define  STATUSB_IP0		8
-#define  STATUSF_IP0		(_ULCAST_(1) <<  8)
-#define  STATUSB_IP1		9
-#define  STATUSF_IP1		(_ULCAST_(1) <<  9)
-#define  STATUSB_IP2		10
-#define  STATUSF_IP2		(_ULCAST_(1) << 10)
-#define  STATUSB_IP3		11
-#define  STATUSF_IP3		(_ULCAST_(1) << 11)
-#define  STATUSB_IP4		12
-#define  STATUSF_IP4		(_ULCAST_(1) << 12)
-#define  STATUSB_IP5		13
-#define  STATUSF_IP5		(_ULCAST_(1) << 13)
-#define  STATUSB_IP6		14
-#define  STATUSF_IP6		(_ULCAST_(1) << 14)
-#define  STATUSB_IP7		15
-#define  STATUSF_IP7		(_ULCAST_(1) << 15)
-#define  STATUSB_IP8		0
-#define  STATUSF_IP8		(_ULCAST_(1) <<  0)
-#define  STATUSB_IP9		1
-#define  STATUSF_IP9		(_ULCAST_(1) <<  1)
-#define  STATUSB_IP10		2
-#define  STATUSF_IP10		(_ULCAST_(1) <<  2)
-#define  STATUSB_IP11		3
-#define  STATUSF_IP11		(_ULCAST_(1) <<  3)
-#define  STATUSB_IP12		4
-#define  STATUSF_IP12		(_ULCAST_(1) <<  4)
-#define  STATUSB_IP13		5
-#define  STATUSF_IP13		(_ULCAST_(1) <<  5)
-#define  STATUSB_IP14		6
-#define  STATUSF_IP14		(_ULCAST_(1) <<  6)
-#define  STATUSB_IP15		7
-#define  STATUSF_IP15		(_ULCAST_(1) <<  7)
-#define  ST0_CH				0x00040000
-#define  ST0_SR				0x00100000
-#define  ST0_TS				0x00200000
-#define  ST0_BEV			0x00400000
-#define  ST0_RE				0x02000000
-#define  ST0_FR				0x04000000
-#define  ST0_CU				0xf0000000
-#define  ST0_CU0			0x10000000
-#define  ST0_CU1			0x20000000
-#define  ST0_CU2			0x40000000
-#define  ST0_CU3			0x80000000
-#define  ST0_XX				0x80000000	/* MIPS IV naming */
-
-/*
- * Bitfields and bit numbers in the coprocessor 0 cause register.
- *
- * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
- */
-#define  CAUSEB_EXCCODE		2
-#define  CAUSEF_EXCCODE		(_ULCAST_(31)  <<  2)
-#define  CAUSEB_IP			8
-#define  CAUSEF_IP			(_ULCAST_(255) <<  8)
-#define  CAUSEB_IP0			8
-#define  CAUSEF_IP0			(_ULCAST_(1)   <<  8)
-#define  CAUSEB_IP1			9
-#define  CAUSEF_IP1			(_ULCAST_(1)   <<  9)
-#define  CAUSEB_IP2			10
-#define  CAUSEF_IP2			(_ULCAST_(1)   << 10)
-#define  CAUSEB_IP3			11
-#define  CAUSEF_IP3			(_ULCAST_(1)   << 11)
-#define  CAUSEB_IP4			12
-#define  CAUSEF_IP4			(_ULCAST_(1)   << 12)
-#define  CAUSEB_IP5			13
-#define  CAUSEF_IP5			(_ULCAST_(1)   << 13)
-#define  CAUSEB_IP6			14
-#define  CAUSEF_IP6			(_ULCAST_(1)   << 14)
-#define  CAUSEB_IP7			15
-#define  CAUSEF_IP7			(_ULCAST_(1)   << 15)
-#define  CAUSEB_IV			23
-#define  CAUSEF_IV			(_ULCAST_(1)   << 23)
-#define  CAUSEB_CE			28
-#define  CAUSEF_CE			(_ULCAST_(3)   << 28)
-#define  CAUSEB_BD			31
-#define  CAUSEF_BD			(_ULCAST_(1)   << 31)
-
-/*
- * Bits in the coprocessor 0 config register.
- */
-/* Generic bits.  */
-#define CONF_CM_CACHABLE_NO_WA			0
-#define CONF_CM_CACHABLE_WA				1
-#define CONF_CM_UNCACHED				2
-#define CONF_CM_CACHABLE_NONCOHERENT	3
-#define CONF_CM_CACHABLE_CE				4
-#define CONF_CM_CACHABLE_COW			5
-#define CONF_CM_CACHABLE_CUW			6
-#define CONF_CM_CACHABLE_ACCELERATED	7
-#define CONF_CM_CMASK					7
-#define CONF_BE							(_ULCAST_(1) << 15)
-
-/* Bits common to various processors.  */
-#define CONF_CU				(_ULCAST_(1) <<  3)
-#define CONF_DB				(_ULCAST_(1) <<  4)
-#define CONF_IB				(_ULCAST_(1) <<  5)
-#define CONF_DC				(_ULCAST_(7) <<  6)
-#define CONF_IC				(_ULCAST_(7) <<  9)
-#define CONF_EB				(_ULCAST_(1) << 13)
-#define CONF_EM				(_ULCAST_(1) << 14)
-#define CONF_SM				(_ULCAST_(1) << 16)
-#define CONF_SC				(_ULCAST_(1) << 17)
-#define CONF_EW				(_ULCAST_(3) << 18)
-#define CONF_EP				(_ULCAST_(15)<< 24)
-#define CONF_EC				(_ULCAST_(7) << 28)
-#define CONF_CM				(_ULCAST_(1) << 31)
-
-/* Bits specific to the R4xx0.  */
-#define R4K_CONF_SW			(_ULCAST_(1) << 20)
-#define R4K_CONF_SS			(_ULCAST_(1) << 21)
-#define R4K_CONF_SB			(_ULCAST_(3) << 22)
-
-/* Bits specific to the R5000.  */
-#define R5K_CONF_SE			(_ULCAST_(1) << 12)
-#define R5K_CONF_SS			(_ULCAST_(3) << 20)
-
-/* Bits specific to the RM7000.  */
-#define RM7K_CONF_SE		(_ULCAST_(1) <<  3)
-#define RM7K_CONF_TE		(_ULCAST_(1) << 12)
-#define RM7K_CONF_CLK		(_ULCAST_(1) << 16)
-#define RM7K_CONF_TC		(_ULCAST_(1) << 17)
-#define RM7K_CONF_SI		(_ULCAST_(3) << 20)
-#define RM7K_CONF_SC		(_ULCAST_(1) << 31)
-
-/* Bits specific to the R10000.  */
-#define R10K_CONF_DN		(_ULCAST_(3) <<  3)
-#define R10K_CONF_CT		(_ULCAST_(1) <<  5)
-#define R10K_CONF_PE		(_ULCAST_(1) <<  6)
-#define R10K_CONF_PM		(_ULCAST_(3) <<  7)
-#define R10K_CONF_EC		(_ULCAST_(15)<<  9)
-#define R10K_CONF_SB		(_ULCAST_(1) << 13)
-#define R10K_CONF_SK		(_ULCAST_(1) << 14)
-#define R10K_CONF_SS		(_ULCAST_(7) << 16)
-#define R10K_CONF_SC		(_ULCAST_(7) << 19)
-#define R10K_CONF_DC		(_ULCAST_(7) << 26)
-#define R10K_CONF_IC		(_ULCAST_(7) << 29)
-
-/* Bits specific to the VR41xx.  */
-#define VR41_CONF_CS		(_ULCAST_(1) << 12)
-#define VR41_CONF_M16		(_ULCAST_(1) << 20)
-#define VR41_CONF_AD		(_ULCAST_(1) << 23)
-
-/* Bits specific to the R30xx.  */
-#define R30XX_CONF_FDM		(_ULCAST_(1) << 19)
-#define R30XX_CONF_REV		(_ULCAST_(1) << 22)
-#define R30XX_CONF_AC		(_ULCAST_(1) << 23)
-#define R30XX_CONF_RF		(_ULCAST_(1) << 24)
-#define R30XX_CONF_HALT		(_ULCAST_(1) << 25)
-#define R30XX_CONF_FPINT	(_ULCAST_(7) << 26)
-#define R30XX_CONF_DBR		(_ULCAST_(1) << 29)
-#define R30XX_CONF_SB		(_ULCAST_(1) << 30)
-#define R30XX_CONF_LOCK		(_ULCAST_(1) << 31)
-
-/* Bits specific to the TX49.  */
-#define TX49_CONF_DC		(_ULCAST_(1) << 16)
-#define TX49_CONF_IC		(_ULCAST_(1) << 17)  /* conflict with CONF_SC */
-#define TX49_CONF_HALT		(_ULCAST_(1) << 18)
-#define TX49_CONF_CWFON		(_ULCAST_(1) << 27)
-
-/* Bits specific to the MIPS32/64 PRA.  */
-#define MIPS_CONF_MT		(_ULCAST_(7) <<  7)
-#define MIPS_CONF_AR		(_ULCAST_(7) << 10)
-#define MIPS_CONF_AT		(_ULCAST_(3) << 13)
-#define MIPS_CONF_M			(_ULCAST_(1) << 31)
-
-/*
- * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
- */
-#define MIPS_CONF1_FP		(_ULCAST_(1) <<  0)
-#define MIPS_CONF1_EP		(_ULCAST_(1) <<  1)
-#define MIPS_CONF1_CA		(_ULCAST_(1) <<  2)
-#define MIPS_CONF1_WR		(_ULCAST_(1) <<  3)
-#define MIPS_CONF1_PC		(_ULCAST_(1) <<  4)
-#define MIPS_CONF1_MD		(_ULCAST_(1) <<  5)
-#define MIPS_CONF1_C2		(_ULCAST_(1) <<  6)
-#define MIPS_CONF1_DA		(_ULCAST_(7) <<  7)
-#define MIPS_CONF1_DL		(_ULCAST_(7) << 10)
-#define MIPS_CONF1_DS		(_ULCAST_(7) << 13)
-#define MIPS_CONF1_IA		(_ULCAST_(7) << 16)
-#define MIPS_CONF1_IL		(_ULCAST_(7) << 19)
-#define MIPS_CONF1_IS		(_ULCAST_(7) << 22)
-#define MIPS_CONF1_TLBS		(_ULCAST_(63)<< 25)
-
-#define MIPS_CONF2_SA		(_ULCAST_(15)<<  0)
-#define MIPS_CONF2_SL		(_ULCAST_(15)<<  4)
-#define MIPS_CONF2_SS		(_ULCAST_(15)<<  8)
-#define MIPS_CONF2_SU		(_ULCAST_(15)<< 12)
-#define MIPS_CONF2_TA		(_ULCAST_(15)<< 16)
-#define MIPS_CONF2_TL		(_ULCAST_(15)<< 20)
-#define MIPS_CONF2_TS		(_ULCAST_(15)<< 24)
-#define MIPS_CONF2_TU		(_ULCAST_(7) << 28)
-
-#define MIPS_CONF3_TL		(_ULCAST_(1) <<  0)
-#define MIPS_CONF3_SM		(_ULCAST_(1) <<  1)
-#define MIPS_CONF3_MT		(_ULCAST_(1) <<  2)
-#define MIPS_CONF3_SP		(_ULCAST_(1) <<  4)
-#define MIPS_CONF3_VINT		(_ULCAST_(1) <<  5)
-#define MIPS_CONF3_VEIC		(_ULCAST_(1) <<  6)
-#define MIPS_CONF3_LPA		(_ULCAST_(1) <<  7)
-#define MIPS_CONF3_DSP		(_ULCAST_(1) << 10)
-
-/*
- * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
- */
-#define MIPS_FPIR_S			(_ULCAST_(1) << 16)
-#define MIPS_FPIR_D			(_ULCAST_(1) << 17)
-#define MIPS_FPIR_PS		(_ULCAST_(1) << 18)
-#define MIPS_FPIR_3D		(_ULCAST_(1) << 19)
-#define MIPS_FPIR_W			(_ULCAST_(1) << 20)
-#define MIPS_FPIR_L			(_ULCAST_(1) << 21)
-#define MIPS_FPIR_F64		(_ULCAST_(1) << 22)
-
-/*
- * R10000 performance counter definitions.
- *
- * FIXME: The R10000 performance counter opens a nice way to implement CPU
- *        time accounting with a precission of one cycle.  I don't have
- *        R10000 silicon but just a manual, so ...
- */
-
-/*
- * Events counted by counter #0
- */
-#define CE0_CYCLES						0
-#define CE0_INSN_ISSUED					1
-#define CE0_LPSC_ISSUED					2
-#define CE0_S_ISSUED					3
-#define CE0_SC_ISSUED					4
-#define CE0_SC_FAILED					5
-#define CE0_BRANCH_DECODED				6
-#define CE0_QW_WB_SECONDARY				7
-#define CE0_CORRECTED_ECC_ERRORS		8
-#define CE0_ICACHE_MISSES				9
-#define CE0_SCACHE_I_MISSES				10
-#define CE0_SCACHE_I_WAY_MISSPREDICTED	11
-#define CE0_EXT_INTERVENTIONS_REQ		12
-#define CE0_EXT_INVALIDATE_REQ			13
-#define CE0_VIRTUAL_COHERENCY_COND		14
-#define CE0_INSN_GRADUATED				15
-
-/*
- * Events counted by counter #1
- */
-#define CE1_CYCLES						0
-#define CE1_INSN_GRADUATED				1
-#define CE1_LPSC_GRADUATED				2
-#define CE1_S_GRADUATED					3
-#define CE1_SC_GRADUATED				4
-#define CE1_FP_INSN_GRADUATED			5
-#define CE1_QW_WB_PRIMARY				6
-#define CE1_TLB_REFILL					7
-#define CE1_BRANCH_MISSPREDICTED		8
-#define CE1_DCACHE_MISS					9
-#define CE1_SCACHE_D_MISSES				10
-#define CE1_SCACHE_D_WAY_MISSPREDICTED	11
-#define CE1_EXT_INTERVENTION_HITS		12
-#define CE1_EXT_INVALIDATE_REQ			13
-#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS	14
-#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS	15
-
-/*
- * These flags define in which privilege mode the counters count events
- */
-#define CEB_USER		8	/* Count events in user mode, EXL = ERL = 0 */
-#define CEB_SUPERVISOR	4	/* Count events in supvervisor mode EXL = ERL = 0 */
-#define CEB_KERNEL		2	/* Count events in kernel mode EXL = ERL = 0 */
-#define CEB_EXL			1	/* Count events with EXL = 1, ERL = 0 */
-
-
-#ifndef __ASSEMBLY__
-
-/*
- * Macros to access the system control coprocessor
- */
-#define __read_32bit_c0_register(source, sel)				\
-({ int __res;								\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			"mfc0\t%0, " #source "\n\t"			\
-			: "=r" (__res));				\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mfc0\t%0, " #source ", " #sel "\n\t"		\
-			".set\tmips0\n\t"				\
-			: "=r" (__res));				\
-	__res;								\
-})
-
-#define __write_32bit_c0_register(register, sel, value)			\
-do {									\
-	if (sel == 0)							\
-		__asm__ __volatile__(					\
-			"mtc0\t%z0, " #register "\n\t"			\
-			: : "Jr" ((unsigned int)(value)));		\
-	else								\
-		__asm__ __volatile__(					\
-			".set\tmips32\n\t"				\
-			"mtc0\t%z0, " #register ", " #sel "\n\t"	\
-			".set\tmips0"					\
-			: : "Jr" ((unsigned int)(value)));		\
-} while (0)
-
-#define read_c0_index()			__read_32bit_c0_register($0, 0)
-#define write_c0_index(val)		__write_32bit_c0_register($0, 0, val)
-
-#define read_c0_random()		__read_32bit_c0_register($1, 0)
-#define write_c0_random(val)	__write_32bit_c0_register($1, 0, val)
-
-#define read_c0_entrylo0()		__read_32bit_c0_register($2, 0)
-#define write_c0_entrylo0(val)	__write_32bit_c0_register($2, 0, val)
-
-#define read_c0_entrylo1()		__read_32bit_c0_register($3, 0)
-#define write_c0_entrylo1(val)	__write_32bit_c0_register($3, 0, val)
-
-#define read_c0_conf()			__read_32bit_c0_register($3, 0)
-#define write_c0_conf(val)		__write_32bit_c0_register($3, 0, val)
-
-#define read_c0_context()		__read_32bit_c0_register($4, 0)
-#define write_c0_context(val)	__write_32bit_c0_register($4, 0, val)
-
-#define read_c0_userlocal()		__read_32bit_c0_register($4, 2)
-#define write_c0_userlocal(val)	__write_32bit_c0_register($4, 2, val)
-
-#define read_c0_pagemask()		__read_32bit_c0_register($5, 0)
-#define write_c0_pagemask(val)	__write_32bit_c0_register($5, 0, val)
-
-#define read_c0_wired()			__read_32bit_c0_register($6, 0)
-#define write_c0_wired(val)		__write_32bit_c0_register($6, 0, val)
-
-#define read_c0_info()			__read_32bit_c0_register($7, 0)
-
-#define read_c0_cache()			__read_32bit_c0_register($7, 0)	/* TX39xx */
-#define write_c0_cache(val)		__write_32bit_c0_register($7, 0, val)
-
-#define read_c0_badvaddr()		__read_32bit_c0_register($8, 0)
-#define write_c0_badvaddr(val)	__write_32bit_c0_register($8, 0, val)
-
-#define read_c0_count()			__read_32bit_c0_register($9, 0)
-#define write_c0_count(val)		__write_32bit_c0_register($9, 0, val)
-
-#define read_c0_count2()		__read_32bit_c0_register($9, 6) /* pnx8550 */
-#define write_c0_count2(val)	__write_32bit_c0_register($9, 6, val)
-
-#define read_c0_count3()		__read_32bit_c0_register($9, 7) /* pnx8550 */
-#define write_c0_count3(val)	__write_32bit_c0_register($9, 7, val)
-
-#define read_c0_entryhi()		__read_32bit_c0_register($10, 0)
-#define write_c0_entryhi(val)	__write_32bit_c0_register($10, 0, val)
-
-#define read_c0_compare()		__read_32bit_c0_register($11, 0)
-#define write_c0_compare(val)	__write_32bit_c0_register($11, 0, val)
-
-#define read_c0_compare2()		__read_32bit_c0_register($11, 6) /* pnx8550 */
-#define write_c0_compare2(val)	__write_32bit_c0_register($11, 6, val)
-
-#define read_c0_compare3()		__read_32bit_c0_register($11, 7) /* pnx8550 */
-#define write_c0_compare3(val)	__write_32bit_c0_register($11, 7, val)
-
-#define read_c0_status()		__read_32bit_c0_register($12, 0)
-#define write_c0_status(val)	__write_32bit_c0_register($12, 0, val)
-
-#define read_c0_cause()			__read_32bit_c0_register($13, 0)
-#define write_c0_cause(val)		__write_32bit_c0_register($13, 0, val)
-
-#define read_c0_epc()			__read_32bit_c0_register($14, 0)
-#define write_c0_epc(val)		__write_32bit_c0_register($14, 0, val)
-
-#define read_c0_prid()			__read_32bit_c0_register($15, 0)
-
-#define read_c0_ebase()			__read_32bit_c0_register($15, 1)
-#define write_c0_ebase(val)		__write_32bit_c0_register($15, 1, val)
-
-#define read_c0_config()		__read_32bit_c0_register($16, 0)
-#define read_c0_config1()		__read_32bit_c0_register($16, 1)
-#define read_c0_config2()		__read_32bit_c0_register($16, 2)
-#define read_c0_config3()		__read_32bit_c0_register($16, 3)
-#define write_c0_config(val)	__write_32bit_c0_register($16, 0, val)
-#define write_c0_config1(val)	__write_32bit_c0_register($16, 1, val)
-#define write_c0_config2(val)	__write_32bit_c0_register($16, 2, val)
-#define write_c0_config3(val)	__write_32bit_c0_register($16, 3, val)
-
-
-/*
- * Macros to access the floating point coprocessor control registers
- */
-#define read_32bit_cp1_register(source)                         \
-({ int __res;                                                   \
-	__asm__ __volatile__(                                   \
-	".set\tpush\n\t"					\
-	".set\treorder\n\t"					\
-	/* gas fails to assemble cfc1 for some archs (octeon).*/ \
-	".set\tmips1\n\t"					\
-        "cfc1\t%0,"STR(source)"\n\t"                            \
-	".set\tpop"						\
-        : "=r" (__res));                                        \
-        __res;})
-#define write_32bit_cp1_register(register, value)   \
-do {                                        \
-    __asm__ __volatile__(                   \
-        "ctc1\t%z0, "STR(register)"\n\t"      \
-        : : "Jr" ((unsigned int)(value)));  \
-} while (0)
-        
-#define read_c1_status()            read_32bit_cp1_register(CP1_STATUS)
-#define read_c1_revision()          read_32bit_cp1_register(CP1_REVISION);
-#define write_c1_status(val)        write_32bit_cp1_register(CP1_STATUS, val)
-
-
-#endif /* end of __ASSEMBLY__ */
-
-#endif /* end of __MIPSREGS_H__ */
-

libcpu/mips/common/ptrace.h

@@ -0,0 +1,126 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#ifndef _MIPS_PTRACE_H
+#define _MIPS_PTRACE_H
+
+#include "asm.h"
+#include "mips_regs.h"
+
+#define FP_REG_SIZE 8
+#define NUM_FPU_REGS 16
+
+#ifndef __ASSEMBLY__
+#include <rtthread.h>
+
+struct mips_fpu_struct {
+    rt_uint64_t	fpr[NUM_FPU_REGS];
+    rt_uint32_t	fcr31;
+    rt_uint32_t	pad;
+};
+
+struct pt_regs {
+    /* Only O32 Need This! */
+    /* Pad bytes for argument save space on the stack. */
+    rt_uint32_t pad0[8];
+
+    /* Saved main processor registers. */
+    rt_uint32_t regs[32];
+
+    /* Saved special registers. */
+    rt_uint32_t cp0_status;
+    rt_uint32_t hi;
+    rt_uint32_t lo;
+    rt_uint32_t cp0_badvaddr;
+    rt_uint32_t cp0_cause;
+    rt_uint32_t cp0_epc;
+
+#ifdef RT_USING_FPU
+    /* FPU Registers */
+    /* Unlike Linux Kernel, we save these registers unconditionally,
+     * so it should be a part of pt_regs */
+    struct mips_fpu_struct fpu;
+#endif
+} __aligned(8);
+#endif
+
+/* Note: For call stack o32 ABI has 0x8 shadowsoace Here  */
+#define PT_R0		(0x8 * LONGSIZE)	/* 0 */
+#define PT_R1		((PT_R0) + LONGSIZE)	/* 1 */
+#define PT_R2		((PT_R1) + LONGSIZE)	/* 2 */
+#define PT_R3		((PT_R2) + LONGSIZE)	/* 3 */
+#define PT_R4		((PT_R3) + LONGSIZE)	/* 4 */
+#define PT_R5		((PT_R4) + LONGSIZE)	/* 5 */
+#define PT_R6		((PT_R5) + LONGSIZE)	/* 6 */
+#define PT_R7		((PT_R6) + LONGSIZE)	/* 7 */
+#define PT_R8		((PT_R7) + LONGSIZE)	/* 8 */
+#define PT_R9		((PT_R8) + LONGSIZE)	/* 9 */
+#define PT_R10		((PT_R9) + LONGSIZE)	/* 10 */
+#define PT_R11		((PT_R10) + LONGSIZE)	/* 11 */
+#define PT_R12		((PT_R11) + LONGSIZE)	/* 12 */
+#define PT_R13		((PT_R12) + LONGSIZE)	/* 13 */
+#define PT_R14		((PT_R13) + LONGSIZE)	/* 14 */
+#define PT_R15		((PT_R14) + LONGSIZE)	/* 15 */
+#define PT_R16		((PT_R15) + LONGSIZE)	/* 16 */
+#define PT_R17		((PT_R16) + LONGSIZE)	/* 17 */
+#define PT_R18		((PT_R17) + LONGSIZE)	/* 18 */
+#define PT_R19		((PT_R18) + LONGSIZE)	/* 19 */
+#define PT_R20		((PT_R19) + LONGSIZE)	/* 20 */
+#define PT_R21		((PT_R20) + LONGSIZE)	/* 21 */
+#define PT_R22		((PT_R21) + LONGSIZE)	/* 22 */
+#define PT_R23		((PT_R22) + LONGSIZE)	/* 23 */
+#define PT_R24		((PT_R23) + LONGSIZE)	/* 24 */
+#define PT_R25		((PT_R24) + LONGSIZE)	/* 25 */
+#define PT_R26		((PT_R25) + LONGSIZE)	/* 26 */
+#define PT_R27		((PT_R26) + LONGSIZE)	/* 27 */
+#define PT_R28		((PT_R27) + LONGSIZE)	/* 28 */
+#define PT_R29		((PT_R28) + LONGSIZE)	/* 29 */
+#define PT_R30		((PT_R29) + LONGSIZE)	/* 30 */
+#define PT_R31		((PT_R30) + LONGSIZE)	/* 31 */
+
+/*
+ * Saved special registers
+ */
+#define PT_STATUS	((PT_R31) + LONGSIZE)	/* 32 */
+#define PT_HI		((PT_STATUS) + LONGSIZE)	/* 33 */
+#define PT_LO		((PT_HI) + LONGSIZE)	/* 34 */
+#define PT_BADVADDR	((PT_LO) + LONGSIZE)	/* 35 */
+#define PT_CAUSE	((PT_BADVADDR) + LONGSIZE)	/* 36 */
+#define PT_EPC		((PT_CAUSE) + LONGSIZE)	/* 37 */
+
+#define PT_REG_END		((PT_EPC) + LONGSIZE) /* Align already ensured manually */
+
+#ifdef RT_USING_FPU
+#define PT_FPU_R0               (PT_REG_END)
+#define PT_FPU_R2               ((PT_FPU_R0) + FP_REG_SIZE)
+#define PT_FPU_R4               ((PT_FPU_R2) + FP_REG_SIZE)
+#define PT_FPU_R6               ((PT_FPU_R4) + FP_REG_SIZE)
+#define PT_FPU_R8               ((PT_FPU_R6) + FP_REG_SIZE)
+#define PT_FPU_R10              ((PT_FPU_R8) + FP_REG_SIZE)
+#define PT_FPU_R12              ((PT_FPU_R10) + FP_REG_SIZE)
+#define PT_FPU_R14              ((PT_FPU_R12) + FP_REG_SIZE)
+#define PT_FPU_R16              ((PT_FPU_R14) + FP_REG_SIZE)
+#define PT_FPU_R18              ((PT_FPU_R16) + FP_REG_SIZE)
+#define PT_FPU_R20              ((PT_FPU_R18) + FP_REG_SIZE)
+#define PT_FPU_R22              ((PT_FPU_R20) + FP_REG_SIZE)
+#define PT_FPU_R24              ((PT_FPU_R22) + FP_REG_SIZE)
+#define PT_FPU_R26              ((PT_FPU_R24) + FP_REG_SIZE)
+#define PT_FPU_R28              ((PT_FPU_R26) + FP_REG_SIZE)
+#define PT_FPU_R30              ((PT_FPU_R28) + FP_REG_SIZE)
+#define PT_FPU_FCSR31           ((PT_FPU_R30) + FP_REG_SIZE)
+#define PT_FPU_PAD0             ((PT_FPU_FCSR31) + LONGSIZE)
+
+#define PT_FPU_END     	        ((PT_FPU_PAD0) + LONGSIZE)
+#define PT_SIZE			PT_FPU_END
+#else
+#define PT_SIZE			PT_REG_END
+#endif
+
+#endif

libcpu/mips/common/stack.c

@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#include <rtthread.h>
+
+#include "mips.h"
+
+register rt_uint32_t $GP __asm__ ("$28");
+
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
+{
+    static rt_uint32_t wSR=0;
+    static rt_uint32_t wGP;
+    rt_uint8_t *stk;
+
+    struct pt_regs *pt;
+
+    rt_uint32_t i;
+
+    /* Get stack aligned */
+    stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8);
+    stk -= sizeof(struct pt_regs);
+    pt =  (struct pt_regs*)stk;
+
+    for (i = 0; i < 8; ++i)
+    {
+        pt->pad0[i] = 0xdeadbeef;
+    }
+
+    /* Fill Stack register numbers */
+    for (i = 0; i < 32; ++i)
+    {
+        pt->regs[i] = 0xdeadbeef;
+    }
+
+    pt->regs[REG_SP] = (rt_uint32_t)stk;
+    pt->regs[REG_A0] = (rt_uint32_t)parameter;
+    pt->regs[REG_GP] = (rt_uint32_t)$GP;
+    pt->regs[REG_FP] = (rt_uint32_t)0x0;
+    pt->regs[REG_RA] = (rt_uint32_t)texit;
+
+    pt->hi	= 0x0;
+    pt->lo	= 0x0;
+    pt->cp0_status = (ST0_IE | ST0_CU0 | ST0_IM);
+#ifdef RT_USING_FPU
+    pt->cp0_status |= (ST0_CU1 | ST0_FR);
+#endif
+    pt->cp0_cause	= read_c0_cause();
+    pt->cp0_epc	= (rt_uint32_t)tentry;
+    pt->cp0_badvaddr	= 0x0;
+
+    return stk;
+}

libcpu/mips/common/stackframe.h

@@ -1,228 +1,250 @@
 /*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
- * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) 2007  Maciej W. Rozycki
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
  */
+
 #ifndef __STACKFRAME_H__
 #define __STACKFRAME_H__
 
 #include "asm.h"
-#include "mipsregs.h"
-
-/*
- * Stack layout for the INT exception handler
- * Derived from the stack layout described in asm-mips/stackframe.h
- *
- * The first PTRSIZE*6 bytes are argument save space for C subroutines.
- */
-
-//#define PT_R0		(PTRSIZE*6)			/* 0 */
-#define PT_R0		(0)						/* 0 */
-#define PT_R1		((PT_R0) + LONGSIZE)	/* 1 */
-#define PT_R2		((PT_R1) + LONGSIZE)	/* 2 */
-#define PT_R3		((PT_R2) + LONGSIZE)	/* 3 */
-#define PT_R4		((PT_R3) + LONGSIZE)	/* 4 */
-#define PT_R5		((PT_R4) + LONGSIZE)	/* 5 */
-#define PT_R6		((PT_R5) + LONGSIZE)	/* 6 */
-#define PT_R7		((PT_R6) + LONGSIZE)	/* 7 */
-#define PT_R8		((PT_R7) + LONGSIZE)	/* 8 */
-#define PT_R9		((PT_R8) + LONGSIZE)	/* 9 */
-#define PT_R10		((PT_R9) + LONGSIZE)	/* 10 */
-#define PT_R11		((PT_R10) + LONGSIZE)	/* 11 */
-#define PT_R12		((PT_R11) + LONGSIZE)	/* 12 */
-#define PT_R13		((PT_R12) + LONGSIZE)	/* 13 */
-#define PT_R14		((PT_R13) + LONGSIZE)	/* 14 */
-#define PT_R15		((PT_R14) + LONGSIZE)	/* 15 */
-#define PT_R16		((PT_R15) + LONGSIZE)	/* 16 */
-#define PT_R17		((PT_R16) + LONGSIZE)	/* 17 */
-#define PT_R18		((PT_R17) + LONGSIZE)	/* 18 */
-#define PT_R19		((PT_R18) + LONGSIZE)	/* 19 */
-#define PT_R20		((PT_R19) + LONGSIZE)	/* 20 */
-#define PT_R21		((PT_R20) + LONGSIZE)	/* 21 */
-#define PT_R22		((PT_R21) + LONGSIZE)	/* 22 */
-#define PT_R23		((PT_R22) + LONGSIZE)	/* 23 */
-#define PT_R24		((PT_R23) + LONGSIZE)	/* 24 */
-#define PT_R25		((PT_R24) + LONGSIZE)	/* 25 */
-#define PT_R26		((PT_R25) + LONGSIZE)	/* 26 */
-#define PT_R27		((PT_R26) + LONGSIZE)	/* 27 */
-#define PT_R28		((PT_R27) + LONGSIZE)	/* 28 */
-#define PT_R29		((PT_R28) + LONGSIZE)	/* 29 */
-#define PT_R30		((PT_R29) + LONGSIZE)	/* 30 */
-#define PT_R31		((PT_R30) + LONGSIZE)	/* 31 */
-
-/*
- * Saved special registers
- */
-#define PT_STATUS	((PT_R31) + LONGSIZE)	/* 32 */
-#define PT_HI		((PT_STATUS) + LONGSIZE)	/* 33 */
-#define PT_LO		((PT_HI) + LONGSIZE)	/* 34 */
-#define PT_BADVADDR	((PT_LO) + LONGSIZE)	/* 35 */
-#define PT_CAUSE	((PT_BADVADDR) + LONGSIZE)	/* 36 */
-#define PT_EPC		((PT_CAUSE) + LONGSIZE)	/* 37 */
-
-#define PT_SIZE		((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
-
-
-		.macro	SAVE_AT
-		.set	push
-		.set	noat
-		LONG_S	$1, PT_R1(sp)
-		.set	pop
-		.endm
-
-		.macro	SAVE_TEMP
-		mfhi	v1
-		LONG_S	$8, PT_R8(sp)
-		LONG_S	$9, PT_R9(sp)
-		LONG_S	v1, PT_HI(sp)
-		mflo	v1
-		LONG_S	$10, PT_R10(sp)
-		LONG_S	$11, PT_R11(sp)
-		LONG_S	v1,  PT_LO(sp)
-		LONG_S	$12, PT_R12(sp)
-		LONG_S	$13, PT_R13(sp)
-		LONG_S	$14, PT_R14(sp)
-		LONG_S	$15, PT_R15(sp)
-		LONG_S	$24, PT_R24(sp)
-		.endm
-
-		.macro	SAVE_STATIC
-		LONG_S	$16, PT_R16(sp)
-		LONG_S	$17, PT_R17(sp)
-		LONG_S	$18, PT_R18(sp)
-		LONG_S	$19, PT_R19(sp)
-		LONG_S	$20, PT_R20(sp)
-		LONG_S	$21, PT_R21(sp)
-		LONG_S	$22, PT_R22(sp)
-		LONG_S	$23, PT_R23(sp)
-		LONG_S	$30, PT_R30(sp)
-		.endm
-
-		.macro	get_saved_sp
-		nop
-		.endm
-
-		.macro	SAVE_SOME
-		.set	push
-		.set	noat
-		.set	reorder
-        move	k1, sp
-8:		move	k0, sp
-		PTR_SUBU sp, k1, PT_SIZE
-		LONG_S	k0, PT_R29(sp)
-		LONG_S	$3, PT_R3(sp)
-		LONG_S	$0, PT_R0(sp)
-		mfc0	v1, CP0_STATUS
-		LONG_S	$2, PT_R2(sp)
-		LONG_S	v1, PT_STATUS(sp)
-		LONG_S	$4, PT_R4(sp)
-		mfc0	v1, CP0_CAUSE
-		LONG_S	$5, PT_R5(sp)
-		LONG_S	v1, PT_CAUSE(sp)
-		LONG_S	$6, PT_R6(sp)
-		MFC0	v1, CP0_EPC
-		LONG_S	$7, PT_R7(sp)
-		LONG_S	v1, PT_EPC(sp)
-		LONG_S	$25, PT_R25(sp)
-		LONG_S	$28, PT_R28(sp)
-		LONG_S	$31, PT_R31(sp)
-		.set	pop
-		.endm
-
-		.macro	SAVE_ALL
-		SAVE_SOME
-		SAVE_AT
-		SAVE_TEMP
-		SAVE_STATIC
-		.endm
-
-		.macro	RESTORE_AT
-		.set	push
-		.set	noat
-		LONG_L	$1,  PT_R1(sp)
-		.set	pop
-		.endm
-
-		.macro	RESTORE_TEMP
-		LONG_L	$24, PT_LO(sp)
-		LONG_L	$8, PT_R8(sp)
-		LONG_L	$9, PT_R9(sp)
-		mtlo	$24
-		LONG_L	$24, PT_HI(sp)
-		LONG_L	$10, PT_R10(sp)
-		LONG_L	$11, PT_R11(sp)
-		mthi	$24
-		LONG_L	$12, PT_R12(sp)
-		LONG_L	$13, PT_R13(sp)
-		LONG_L	$14, PT_R14(sp)
-		LONG_L	$15, PT_R15(sp)
-		LONG_L	$24, PT_R24(sp)
-		.endm
-
-		.macro	RESTORE_STATIC
-		LONG_L	$16, PT_R16(sp)
-		LONG_L	$17, PT_R17(sp)
-		LONG_L	$18, PT_R18(sp)
-		LONG_L	$19, PT_R19(sp)
-		LONG_L	$20, PT_R20(sp)
-		LONG_L	$21, PT_R21(sp)
-		LONG_L	$22, PT_R22(sp)
-		LONG_L	$23, PT_R23(sp)
-		LONG_L	$30, PT_R30(sp)
-		.endm
-
-		.macro	RESTORE_SOME
-		.set	push
-		.set	reorder
-		.set	noat
-		LONG_L	v0, PT_STATUS(sp)
-		mtc0	v0, CP0_STATUS
-		LONG_L	v1, PT_EPC(sp)
-		MTC0	v1, CP0_EPC
-		LONG_L	$31, PT_R31(sp)
-		LONG_L	$28, PT_R28(sp)
-		LONG_L	$25, PT_R25(sp)
-		LONG_L	$7,  PT_R7(sp)
-		LONG_L	$6,  PT_R6(sp)
-		LONG_L	$5,  PT_R5(sp)
-		LONG_L	$4,  PT_R4(sp)
-		LONG_L	$3,  PT_R3(sp)
-		LONG_L	$2,  PT_R2(sp)
-		.set	pop
-		.endm
-
-		.macro	RESTORE_SP_AND_RET
-		LONG_L	sp, PT_R29(sp)
-		.set	mips3
-		eret
-		.set	mips0
-		.endm
-
-
-		.macro	RESTORE_SP
-		LONG_L	sp, PT_R29(sp)
-		.endm
-
-		.macro	RESTORE_ALL
-		RESTORE_TEMP
-		RESTORE_STATIC
-		RESTORE_AT
-		RESTORE_SOME
-		RESTORE_SP
-		.endm
-
-		.macro	RESTORE_ALL_AND_RET
-		RESTORE_TEMP
-		RESTORE_STATIC
-		RESTORE_AT
-		RESTORE_SOME
-		RESTORE_SP_AND_RET
-		.endm
+#include "mips_regs.h"
+#include "ptrace.h"
+
+/* You MUST ensure FP is enabled before SAVE_FPU! */
+    .macro SAVE_FPU
+    .set push
+    .set noreorder
+#ifdef RT_USING_FPU
+    /* Ensure CU1 (FPU) is enabled */
+    MFC0 v1, CP0_STATUS
+    ori v1, ST0_CU1
+    MTC0 v1, CP0_STATUS
+    SSNOP
+    cfc1 v1, fcr31
+    /* Store as delay slot */
+    s.d $f0, PT_FPU_R0(sp)
+    s.d $f2, PT_FPU_R2(sp)
+    s.d $f4, PT_FPU_R4(sp)
+    s.d $f6, PT_FPU_R6(sp)
+    s.d $f8, PT_FPU_R8(sp)
+    s.d $f10, PT_FPU_R10(sp)
+    s.d $f12, PT_FPU_R12(sp)
+    s.d $f14, PT_FPU_R14(sp)
+    s.d $f16, PT_FPU_R16(sp)
+    s.d $f18, PT_FPU_R18(sp)
+    s.d $f20, PT_FPU_R20(sp)
+    s.d $f22, PT_FPU_R22(sp)
+    s.d $f24, PT_FPU_R24(sp)
+    s.d $f26, PT_FPU_R26(sp)
+    s.d $f28, PT_FPU_R28(sp)
+    s.d $f30, PT_FPU_R30(sp)
+    LONG_S v1, PT_FPU_FCSR31(sp)
+#endif
+    .set reorder
+    .set pop
+    .endm
+
+    .macro	SAVE_AT
+    .set	push
+    .set	noat
+    LONG_S	$1, PT_R1(sp)
+    .set	pop
+    .endm
+
+    .macro	SAVE_TEMP
+    mfhi	v1
+    LONG_S	$8, PT_R8(sp)
+    LONG_S	$9, PT_R9(sp)
+    LONG_S	v1, PT_HI(sp)
+    mflo	v1
+    LONG_S	$10, PT_R10(sp)
+    LONG_S	$11, PT_R11(sp)
+    LONG_S	v1,  PT_LO(sp)
+    LONG_S	$12, PT_R12(sp)
+    LONG_S	$13, PT_R13(sp)
+    LONG_S	$14, PT_R14(sp)
+    LONG_S	$15, PT_R15(sp)
+    LONG_S	$24, PT_R24(sp)
+    .endm
+
+    .macro	SAVE_STATIC
+    LONG_S	$16, PT_R16(sp)
+    LONG_S	$17, PT_R17(sp)
+    LONG_S	$18, PT_R18(sp)
+    LONG_S	$19, PT_R19(sp)
+    LONG_S	$20, PT_R20(sp)
+    LONG_S	$21, PT_R21(sp)
+    LONG_S	$22, PT_R22(sp)
+    LONG_S	$23, PT_R23(sp)
+    LONG_S	$30, PT_R30(sp)
+    .endm
+
+    .macro	SAVE_SOME
+    .set	push
+    .set	noat
+    .set	reorder
+    move	k1, sp
+    move	k0, sp
+    PTR_SUBU sp, k1, PT_SIZE
+    LONG_S	k0, PT_R29(sp)
+    LONG_S	$3, PT_R3(sp)
+    LONG_S	$0, PT_R0(sp)
+    MFC0	v1, CP0_STATUS
+    LONG_S	$2, PT_R2(sp)
+    LONG_S	v1, PT_STATUS(sp)
+    LONG_S	$4, PT_R4(sp)
+    MFC0	v1, CP0_CAUSE
+    LONG_S	$5, PT_R5(sp)
+    LONG_S	v1, PT_CAUSE(sp)
+    LONG_S	$6, PT_R6(sp)
+    MFC0	v1, CP0_EPC
+    LONG_S	$7, PT_R7(sp)
+    LONG_S	v1, PT_EPC(sp)
+    LONG_S	$25, PT_R25(sp)
+    LONG_S	$28, PT_R28(sp)
+    LONG_S	$31, PT_R31(sp)
+    .set	pop
+    .endm
+
+    .macro	SAVE_ALL
+    SAVE_SOME
+    SAVE_AT
+    SAVE_TEMP
+    SAVE_FPU
+    SAVE_STATIC
+    .endm
+
+    .macro RESTORE_FPU
+    .set push
+    .set noreorder
+#ifdef RT_USING_FPU
+    /* Ensure CU1 (FPU) is enabled */
+    MFC0 v1, CP0_STATUS
+    ori v1, ST0_CU1
+    MTC0 v1, CP0_STATUS
+    SSNOP
+    LONG_L v1, PT_FPU_FCSR31(sp)
+    ctc1 v1, fcsr31
+    l.d $f0, PT_FPU_R0(sp)
+    l.d $f2, PT_FPU_R2(sp)
+    l.d $f4, PT_FPU_R4(sp)
+    l.d $f6, PT_FPU_R6(sp)
+    l.d $f8, PT_FPU_R8(sp)
+    l.d $f10, PT_FPU_R10(sp)
+    l.d $f12, PT_FPU_R12(sp)
+    l.d $f14, PT_FPU_R14(sp)
+    l.d $f16, PT_FPU_R16(sp)
+    l.d $f18, PT_FPU_R18(sp)
+    l.d $f20, PT_FPU_R20(sp)
+    l.d $f22, PT_FPU_R22(sp)
+    l.d $f24, PT_FPU_R24(sp)
+    l.d $f26, PT_FPU_R26(sp)
+    l.d $f28, PT_FPU_R28(sp)
+    l.d $f30, PT_FPU_R30(sp)
+#endif
+    .set reorder
+    .set pop
+    .endm
+
+    .macro	RESTORE_AT
+    .set	push
+    .set	noat
+    LONG_L	$1,  PT_R1(sp)
+    .set	pop
+    .endm
+
+    .macro	RESTORE_TEMP
+    LONG_L	$24, PT_LO(sp)
+    LONG_L	$8, PT_R8(sp)
+    LONG_L	$9, PT_R9(sp)
+    mtlo	$24
+    LONG_L	$24, PT_HI(sp)
+    LONG_L	$10, PT_R10(sp)
+    LONG_L	$11, PT_R11(sp)
+    mthi	$24
+    LONG_L	$12, PT_R12(sp)
+    LONG_L	$13, PT_R13(sp)
+    LONG_L	$14, PT_R14(sp)
+    LONG_L	$15, PT_R15(sp)
+    LONG_L	$24, PT_R24(sp)
+    .endm
+
+    .macro	RESTORE_STATIC
+    LONG_L	$16, PT_R16(sp)
+    LONG_L	$17, PT_R17(sp)
+    LONG_L	$18, PT_R18(sp)
+    LONG_L	$19, PT_R19(sp)
+    LONG_L	$20, PT_R20(sp)
+    LONG_L	$21, PT_R21(sp)
+    LONG_L	$22, PT_R22(sp)
+    LONG_L	$23, PT_R23(sp)
+    LONG_L	$30, PT_R30(sp)
+    .endm
+
+#define STATMASK 0x1f
+
+    .macro	RESTORE_SOME
+    .set	push
+    .set	reorder
+    .set	noat
+    mfc0	a0, CP0_STATUS
+    ori	a0, STATMASK
+    xori	a0, STATMASK
+    mtc0	a0, CP0_STATUS
+    li	v1, (ST0_CU1 | ST0_FR | ST0_IM)
+    and	a0, v1, a0
+    LONG_L	v0, PT_STATUS(sp)
+    li	v1, ~(ST0_CU1 | ST0_FR | ST0_IM)
+    and	v0, v1
+    or	v0, a0
+    mtc0	v0, CP0_STATUS
+    LONG_L	v1, PT_EPC(sp)
+    MTC0	v1, CP0_EPC
+    LONG_L	$31, PT_R31(sp)
+    LONG_L	$28, PT_R28(sp)
+    LONG_L	$25, PT_R25(sp)
+    LONG_L	$7,  PT_R7(sp)
+    LONG_L	$6,  PT_R6(sp)
+    LONG_L	$5,  PT_R5(sp)
+    LONG_L	$4,  PT_R4(sp)
+    LONG_L	$3,  PT_R3(sp)
+    LONG_L	$2,  PT_R2(sp)
+    .set	pop
+    .endm
+
+    .macro	RESTORE_SP_AND_RET
+    LONG_L	sp, PT_R29(sp)
+    eret
+    nop
+    .endm
+
+
+    .macro	RESTORE_SP
+    LONG_L	sp, PT_R29(sp)
+    .endm
+
+    .macro	RESTORE_ALL
+    RESTORE_TEMP
+    RESTORE_FPU
+    RESTORE_STATIC
+    RESTORE_AT
+    RESTORE_SOME
+    RESTORE_SP
+    .endm
+
+    .macro	RESTORE_ALL_AND_RET
+    RESTORE_TEMP
+    RESTORE_FPU
+    RESTORE_STATIC
+    RESTORE_AT
+    RESTORE_SOME
+    RESTORE_SP_AND_RET
+    .endm
 
 #endif /* end of __STACKFRAME_H__ */
 

libcpu/mips/gs232/cache.c

@@ -0,0 +1,231 @@
+/*
+ * Cache Ops For Loongson GS232
+ *
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-07-09     Bernard        first version
+ * 2011-08-08     lgnq             modified for LS1B
+ * 2015-07-08     chinesebear   modified for loongson 1c
+ */
+
+#include <rtthread.h>
+#include <mips.h>
+
+#define K0BASE			0x80000000
+#define PRID_LS1C		0x4220
+
+extern void Clear_TagLo (void);
+extern void Invalidate_Icache_Ls1c(unsigned int);
+extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int);
+extern void Invalidate_Dcache_Fill_Ls1c(unsigned int);
+extern void Writeback_Invalidate_Dcache(unsigned int);
+extern void enable_cpu_cache(void);
+
+typedef struct cacheinfo_t
+{
+    unsigned int	icache_size;
+    unsigned int	dcache_size;
+    unsigned int	icacheline_size;
+    unsigned int	dcacheline_size;
+} cacheinfo_t ;
+
+typedef struct cacheop_t
+{
+    void (*Clear_TagLo) (void);
+    void (*Invalidate_Icache) (unsigned int);
+    void (*Invalidate_Dcache_Fill) (unsigned int);
+    void (*Invalidate_Dcache_ClearTag) (unsigned int);
+    void (*Init_Cache)(void);
+} cacheop_t ;
+
+static cacheop_t cacheop, *pcacheop;
+static cacheinfo_t cacheinfo, *pcacheinfo;
+
+int identify_cpu(void)
+{
+    unsigned int cpu_id;
+
+    pcacheop = &cacheop;
+    pcacheinfo = &cacheinfo;
+
+    rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
+    cpu_id = read_c0_prid();
+    switch (cpu_id)
+    {
+    case PRID_LS1C:
+        rt_kprintf("CPU:Loongson 1C\n");
+        pcacheop->Clear_TagLo = Clear_TagLo;
+        pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c;
+        pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c;
+        pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c;
+        break;
+    default:
+        rt_kprintf("Unknown CPU type, system halted!\n");
+        while (1)
+        {
+            ;
+        }
+        break;
+    }
+
+    return 0;
+}
+
+void probe_cache(void)
+{
+    unsigned int config1 = read_c0_config1();
+    unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
+    unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
+
+    if ((icache_line_size = ((config1 >> 19) & 7)))
+        icache_line_size = 2 << icache_line_size;
+    else
+        icache_line_size = icache_line_size;
+    icache_sets = 64 << ((config1 >> 22) & 7);
+    icache_ways = 1 + ((config1 >> 16) & 7);
+    icache_size = icache_sets * icache_ways * icache_line_size;
+
+    if ((dcache_line_size = ((config1 >> 10) & 7)))
+        dcache_line_size = 2 << dcache_line_size;
+    else
+        dcache_line_size = dcache_line_size;
+    dcache_sets = 64 << ((config1 >> 13) & 7);
+    dcache_ways = 1 + ((config1 >> 7) & 7);
+    dcache_size = dcache_sets * dcache_ways * dcache_line_size;
+
+    rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
+    rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
+
+    pcacheinfo->icache_size = icache_size;
+    pcacheinfo->dcache_size = dcache_size;
+    pcacheinfo->icacheline_size = icache_line_size;
+    pcacheinfo->dcacheline_size = dcache_line_size;
+
+    return ;
+}
+
+void invalidate_writeback_dcache_all(void)
+{
+    unsigned int start = K0BASE;
+    unsigned int end = (start + pcacheinfo->dcache_size);
+
+    while (start < end)
+    {
+        Writeback_Invalidate_Dcache(start);  //hit writeback invalidate
+        start += pcacheinfo->dcacheline_size;
+    }
+}
+
+void invalidate_writeback_dcache(unsigned long addr, int size)
+{
+    unsigned long start, end;
+
+    start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
+    end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
+
+    while (start <end)
+    {
+        Writeback_Invalidate_Dcache(start);
+        start += pcacheinfo->dcacheline_size;
+    }
+}
+
+void invalidate_icache_all(void)
+{
+    unsigned int start = K0BASE;
+    unsigned int end = (start + pcacheinfo->icache_size);
+
+    while (start < end)
+    {
+        pcacheop->Invalidate_Icache(start);
+        start += pcacheinfo->icacheline_size;
+    }
+}
+
+void invalidate_dcache_all(void)
+{
+    unsigned int start = K0BASE;
+    unsigned int end  = (start + pcacheinfo->dcache_size);
+    while (start <end)
+    {
+        Invalidate_Dcache_Fill_Ls1c(start);
+        start += pcacheinfo->icacheline_size;
+    }
+}
+
+//with cache disabled
+void init_dcache(void)
+{
+    unsigned int start = K0BASE;
+    unsigned int end = (start + pcacheinfo->dcache_size);
+
+    while (start < end)
+    {
+        pcacheop->Invalidate_Dcache_ClearTag(start);
+        start += pcacheinfo->dcacheline_size;
+    }
+
+}
+
+void rt_hw_cache_init(void)
+{
+    unsigned int start, end;
+
+    /* 1. identify cpu and probe cache */
+    identify_cpu();
+    probe_cache();
+
+    start = K0BASE;
+    end = (start + pcacheinfo->icache_size);
+
+    /*
+     *	2. clear CP0 taglo/taghi register;
+     */
+    pcacheop->Clear_TagLo();
+
+    /*
+     *	3. invalidate instruction cache;
+     */
+    while (start < end)
+    {
+        pcacheop->Invalidate_Icache(start); //index invalidate icache
+        start += pcacheinfo->icacheline_size;
+    }
+
+    /*
+     *	4. invalidate data cache;
+     */
+    start = K0BASE;
+    end = (start + pcacheinfo->dcache_size);
+    while(start < end)
+    {
+        pcacheop->Invalidate_Dcache_ClearTag(start);
+        start += pcacheinfo->dcacheline_size;
+    }
+
+    start = K0BASE;
+    while(start < end)
+    {
+        pcacheop->Invalidate_Dcache_Fill(start);  //index invalidate dcache
+        start += pcacheinfo->dcacheline_size;
+    }
+
+    start = K0BASE;
+    while(start < end)
+    {
+        pcacheop->Invalidate_Dcache_ClearTag(start);
+        start += pcacheinfo->dcacheline_size;
+    }
+
+    /* enable cache */
+    enable_cpu_cache();
+    rt_kprintf("enable cpu cache done\n");
+
+    return ;
+}
+
+

libcpu/mips/loongson_1b/cache.h → libcpu/mips/gs232/cache.h

@@ -1,20 +1,19 @@
 /*
- * File      : cache.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * Cache Ops For Loongson GS232
+ * 
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ * 
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- * 2011-08-08     lgnq         modified for LS1B
+ * 2010-07-09     Bernard        first version
+ * 2011-08-08     lgnq             modified for LS1B
+ * 2015-07-08     chinesebear   modified for loongson 1c
  */
+
 #ifndef	__CACHE_H__
 #define	__CACHE_H__
-
 /*
  * Cache Operations
  */

libcpu/mips/loongson_1c/cache_gcc.S → libcpu/mips/gs232/cache_gcc.S

@@ -16,12 +16,10 @@
 #define __ASSEMBLY__
 #endif
 
-#include "../common/mipsregs.h"
-#include "../common/mips_def.h"
-#include "../common/asm.h"
+#include <mips.h>
 #include "cache.h"
 
-	.ent	cache_init
+    .ent	cache_init
     .global cache_init
     .set noreorder
 cache_init:
@@ -71,84 +69,84 @@ cache_i4way:
         sllv    t5, t4, t5
 #if 0
     la	t0, memvar
-	sw	t7, 0x0(t0) #ways
-	sw	t5, 0x4(t0) #icache size
-	sw	t6, 0x8(t0) #dcache size
+    sw	t7, 0x0(t0) #ways
+    sw	t5, 0x4(t0) #icache size
+    sw	t6, 0x8(t0) #dcache size
 #endif
 ####part 3####
-	.set	mips3
-	lui	a0, 0x8000
-	addu	a1, $0, t5
-	addu	a2, $0, t6
+    .set	mips3
+    lui	a0, 0x8000
+    addu	a1, $0, t5
+    addu	a2, $0, t6
 cache_init_d2way:
 #a0=0x80000000, a1=icache_size, a2=dcache_size
 #a3, v0 and v1 used as local registers
-	mtc0	$0, CP0_TAGHI
-	addu	v0, $0, a0
-	addu	v1, a0, a2
+    mtc0	$0, CP0_TAGHI
+    addu	v0, $0, a0
+    addu	v1, a0, a2
 1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	mtc0	$0, CP0_TAGLO
-	beq	t7, 1, 4f
-	cache	Index_Store_Tag_D, 0x0(v0)	# 1 way
-	beq	t7, 2 ,4f
-	cache	Index_Store_Tag_D, 0x1(v0)	# 2 way
-	cache	Index_Store_Tag_D, 0x2(v0)	# 4 way
-	cache	Index_Store_Tag_D, 0x3(v0)
+    beq	a3, $0, 1f
+    nop
+    mtc0	$0, CP0_TAGLO
+    beq	t7, 1, 4f
+    cache	Index_Store_Tag_D, 0x0(v0)	# 1 way
+    beq	t7, 2 ,4f
+    cache	Index_Store_Tag_D, 0x1(v0)	# 2 way
+    cache	Index_Store_Tag_D, 0x2(v0)	# 4 way
+    cache	Index_Store_Tag_D, 0x3(v0)
 4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
+    addiu	v0, v0, 0x20
 1:
 cache_flush_i2way:
-	addu	v0, $0, a0
-	addu	v1, a0, a1
+    addu	v0, $0, a0
+    addu	v1, a0, a1
 1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	beq	t3, 1, 4f
-	cache	Index_Invalidate_I, 0x0(v0)	# 1 way
-	beq	t3, 2, 4f
-	cache	Index_Invalidate_I, 0x1(v0)	# 2 way
-	cache	Index_Invalidate_I, 0x2(v0)
-	cache	Index_Invalidate_I, 0x3(v0)	# 4 way
+    beq	a3, $0, 1f
+    nop
+    beq	t3, 1, 4f
+    cache	Index_Invalidate_I, 0x0(v0)	# 1 way
+    beq	t3, 2, 4f
+    cache	Index_Invalidate_I, 0x1(v0)	# 2 way
+    cache	Index_Invalidate_I, 0x2(v0)
+    cache	Index_Invalidate_I, 0x3(v0)	# 4 way
 4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
+    addiu	v0, v0, 0x20
 1:
 cache_flush_d2way:
-	addu	v0, $0, a0
-	addu	v1, a0, a2
+    addu	v0, $0, a0
+    addu	v1, a0, a2
 1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	beq	t7, 1, 4f
-	cache	Index_Writeback_Inv_D, 0x0(v0) 	#1 way
-	beq	t7, 2, 4f
-	cache	Index_Writeback_Inv_D, 0x1(v0)	# 2 way
-	cache	Index_Writeback_Inv_D, 0x2(v0)
-	cache	Index_Writeback_Inv_D, 0x3(v0)	# 4 way
+    beq	a3, $0, 1f
+    nop
+    beq	t7, 1, 4f
+    cache	Index_Writeback_Inv_D, 0x0(v0) 	#1 way
+    beq	t7, 2, 4f
+    cache	Index_Writeback_Inv_D, 0x1(v0)	# 2 way
+    cache	Index_Writeback_Inv_D, 0x2(v0)
+    cache	Index_Writeback_Inv_D, 0x3(v0)	# 4 way
 4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
+    addiu	v0, v0, 0x20
 1:
 cache_init_finish:
-	jr	t1
+    jr	t1
     nop
     .set reorder
-	.end cache_init
+    .end cache_init
 
 ###########################
 #  Enable CPU cache       #
 ###########################
 
 LEAF(enable_cpu_cache)
-	.set noreorder
-	mfc0	t0, CP0_CONFIG
-	nop
-	and		t0, ~0x03
-	or		t0, 0x03
-	mtc0	t0, CP0_CONFIG
-	nop
-	.set reorder
-	j	ra
+    .set noreorder
+    mfc0	t0, CP0_CONFIG
+    nop
+    and		t0, ~0x03
+    or		t0, 0x03
+    mtc0	t0, CP0_CONFIG
+    nop
+    .set reorder
+    j	ra
 END (enable_cpu_cache)
     
 ###########################
@@ -156,26 +154,26 @@ END (enable_cpu_cache)
 ###########################
 
 LEAF(disable_cpu_cache)
-	.set noreorder
-	mfc0	t0, CP0_CONFIG
-	nop
-	and		t0, ~0x03
-	or 		t0, 0x2
-	mtc0	t0, CP0_CONFIG
-	nop
-	.set reorder
-	j	ra
+    .set noreorder
+    mfc0	t0, CP0_CONFIG
+    nop
+    and		t0, ~0x03
+    or 		t0, 0x2
+    mtc0	t0, CP0_CONFIG
+    nop
+    .set reorder
+    j	ra
 END (disable_cpu_cache)
 
 /**********************************/
 /* Invalidate Instruction Cache	  */
 /**********************************/
 LEAF(Clear_TagLo)
-	.set 	noreorder
-	mtc0	zero, CP0_TAGLO
-	nop
-	.set 	reorder
-	j		ra
+    .set 	noreorder
+    mtc0	zero, CP0_TAGLO
+    nop
+    .set 	reorder
+    j		ra
 END(Clear_TagLo)
 
     .set mips3
@@ -183,38 +181,38 @@ END(Clear_TagLo)
 /* Invalidate Instruction Cache	  */
 /**********************************/
 LEAF(Invalidate_Icache_Ls1c)
-	.set	noreorder
-	cache	Index_Invalidate_I,0(a0)
-	cache	Index_Invalidate_I,1(a0)
-	cache	Index_Invalidate_I,2(a0)
-	cache	Index_Invalidate_I,3(a0)
-	.set	reorder
-	j		ra
+    .set	noreorder
+    cache	Index_Invalidate_I,0(a0)
+    cache	Index_Invalidate_I,1(a0)
+    cache	Index_Invalidate_I,2(a0)
+    cache	Index_Invalidate_I,3(a0)
+    .set	reorder
+    j		ra
 END(Invalidate_Icache_Ls1c)
 
 /**********************************/
 /* Invalidate Data Cache		  */
 /**********************************/
 LEAF(Invalidate_Dcache_ClearTag_Ls1c)
-	.set	noreorder
-	cache	Index_Store_Tag_D, 0(a0)	# BDSLOT: clear tag
-	cache	Index_Store_Tag_D, 1(a0)	# BDSLOT: clear tag
-	.set	reorder
-	j		ra
+    .set	noreorder
+    cache	Index_Store_Tag_D, 0(a0)	# BDSLOT: clear tag
+    cache	Index_Store_Tag_D, 1(a0)	# BDSLOT: clear tag
+    .set	reorder
+    j		ra
 END(Invalidate_Dcache_ClearTag_Ls1c)
 
 LEAF(Invalidate_Dcache_Fill_Ls1c)
-	.set	noreorder
-	cache	Index_Writeback_Inv_D, 0(a0)	# BDSLOT: clear tag
-	cache	Index_Writeback_Inv_D, 1(a0)	# BDSLOT: clear tag
-	.set	reorder
-	j		ra
+    .set	noreorder
+    cache	Index_Writeback_Inv_D, 0(a0)	# BDSLOT: clear tag
+    cache	Index_Writeback_Inv_D, 1(a0)	# BDSLOT: clear tag
+    .set	reorder
+    j		ra
 END(Invalidate_Dcache_Fill_Ls1c)
 
 LEAF(Writeback_Invalidate_Dcache)
-	.set noreorder
-	cache	Hit_Writeback_Inv_D, (a0)
-	.set reorder
-	j	ra
+    .set noreorder
+    cache	Hit_Writeback_Inv_D, (a0)
+    .set reorder
+    j	ra
 END(Writeback_Invalidate_Dcache)
     .set mips0

libcpu/mips/gs232/cpuinit_gcc.S

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include <mips.h>
+
+    .section ".start", "ax"
+    .set noreorder
+
+    .globl  rt_cpu_early_init
+rt_cpu_early_init:
+     jr	ra
+     nop

libcpu/mips/gs232/cpuport.c

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * 
+ * Change Logs:
+ * Date                Author         Notes
+ * 2010-07-09     Bernard        first version
+ * 2010-09-11     Bernard        add CPU reset implementation
+ * 2015-07-06     chinesebear  modified for loongson 1c
+ */
+
+#include <rtthread.h>
+#include "gs232.h"
+
+/**
+ * @addtogroup Loongson GS232
+ */
+
+/*@{*/
+
+/**
+ * this function will reset CPU
+ *
+ */
+void rt_hw_cpu_reset(void)
+{
+    /* open the watch-dog */
+    WDT_EN = 0x01; 		/* watch dog enable */
+    WDT_TIMER = 0x01;	/* watch dog will be timeout after 1 tick */
+    WDT_SET = 0x01;		/* watch dog start */
+
+    rt_kprintf("reboot system...\n");
+    while (1);
+}
+
+/**
+ * this function will shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown(void)
+{
+    rt_kprintf("shutdown...\n");
+
+    while (1);
+}
+
+
+#define Hit_Invalidate_I    0x10
+#define Hit_Invalidate_D    0x11
+#define CONFIG_SYS_CACHELINE_SIZE   32
+#define Hit_Writeback_Inv_D 0x15
+
+
+void flush_cache(unsigned long start_addr, unsigned long size)
+{
+    unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+    unsigned long addr = start_addr & ~(lsize - 1);
+    unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+    while (1) {
+        cache_op(Hit_Writeback_Inv_D, addr);
+        cache_op(Hit_Invalidate_I, addr);
+        if (addr == aend)
+            break;
+        addr += lsize;
+    }
+}
+
+
+/*@}*/
+

libcpu/mips/gs232/gs232.h

@@ -0,0 +1,67 @@
+/*
+ * Misc define for GS232
+ * 
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ * 
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#ifndef __GS232_H__
+#define __GS232_H__
+
+#include <mips.h>
+
+#define INTC_BASE			0xBFD01040
+
+#define GS232_INTC_CELLS		5
+#define GS232_NR_IRQS			(32 * GS232_INTC_CELLS)
+
+#define GMAC0_BASE			0xBFE10000
+#define GMAC0_DMA_BASE		0xBFE11000
+#define GMAC1_BASE			0xBFE20000
+#define GMAC1_DMA_BASE		0xBFE21000
+#define I2C0_BASE			0xBFE58000
+#define PWM0_BASE			0xBFE5C000
+#define PWM1_BASE			0xBFE5C010
+#define PWM2_BASE			0xBFE5C020
+#define PWM3_BASE			0xBFE5C030
+#define WDT_BASE			0xBFE5C060
+#define RTC_BASE			0xBFE64000
+#define I2C1_BASE			0xBFE68000
+#define I2C2_BASE			0xBFE70000
+#define AC97_BASE			0xBFE74000
+#define NAND_BASE			0xBFE78000
+#define SPI_BASE			0xBFE80000
+#define CAN1_BASE			0xBF004300
+#define CAN0_BASE			0xBF004400
+
+#ifndef __ASSEMBLY__
+#include <rthw.h>
+
+/* Watch Dog registers */
+#define WDT_EN				HWREG32(WDT_BASE + 0x00)
+#define WDT_SET				HWREG32(WDT_BASE + 0x04)
+#define WDT_TIMER			HWREG32(WDT_BASE + 0x08)
+
+#define PLL_FREQ 			HWREG32(0xbfe78030)
+#define PLL_DIV_PARAM 		HWREG32(0xbfe78034)
+
+struct gs232_intc_regs
+{
+    volatile unsigned int int_isr;
+    volatile unsigned int int_en;
+    volatile unsigned int int_set;
+    volatile unsigned int int_clr;        /* offset 0x10*/
+    volatile unsigned int int_pol;
+    volatile unsigned int int_edge;        /* offset 0 */
+}; 
+
+extern void rt_hw_timer_init(void);
+
+#endif
+
+#endif

libcpu/mips/gs232/interrupt.c

@@ -0,0 +1,162 @@
+/*
+ * Interrupt handle for GS232
+ * 
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ * 
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-10-15     Bernard      first version
+ * 2010-10-15     lgnq           modified for LS1B
+ * 2013-03-29     aozima       Modify the interrupt interface implementations.
+ * 2015-07-06     chinesebear modified for loongson 1c
+ * 2019-12-04     Jiaxun Yang   Generialize
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include "gs232.h"
+
+
+#define MAX_INTR            (GS232_NR_IRQS)
+
+static struct rt_irq_desc irq_handle_table[MAX_INTR];
+void rt_interrupt_dispatch(void *ptreg);
+void rt_hw_timer_handler();
+
+static struct gs232_intc_regs volatile *gs232_hw0_icregs
+= (struct gs232_intc_regs volatile *)(INTC_BASE);
+
+/**
+ * @addtogroup Loongson GS232
+ */
+
+/*@{*/
+
+static void rt_hw_interrupt_handler(int vector, void *param)
+{
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    rt_int32_t idx;
+    rt_int32_t i;
+    rt_uint32_t c0_status = 0;
+
+    for (i=0; i < GS232_INTC_CELLS; i++)
+    {
+        /* Disable */
+        (gs232_hw0_icregs+i)->int_en = 0x0;
+        /* Trigger active low */
+        (gs232_hw0_icregs+i)->int_pol = -1;	   /* Must be done here */
+        /* Make all interrupts level triggered */
+        (gs232_hw0_icregs+i)->int_edge = 0x00000000;
+        /* Mask all interrupts */
+        (gs232_hw0_icregs+i)->int_clr = 0xffffffff;
+        mips_unmask_cpu_irq(i + 2);
+    }
+
+    rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
+    for (idx = 0; idx < MAX_INTR; idx ++)
+    {
+        irq_handle_table[idx].handler = rt_hw_interrupt_handler;
+    }
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    /* mask interrupt */
+    (gs232_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    (gs232_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+                                         void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector >= 0 && vector < MAX_INTR)
+    {
+        old_handler = irq_handle_table[vector].handler;
+
+#ifdef RT_USING_INTERRUPT_INFO
+        rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+        irq_handle_table[vector].handler = handler;
+        irq_handle_table[vector].param = param;
+    }
+
+    return old_handler;
+}
+
+
+/**
+ * ִ Call ISR
+ * @IRQn ID of IRQ
+ */
+void gs232_do_IRQ(int IRQn)
+{
+    rt_isr_handler_t irq_func;
+    void *param;
+
+    irq_func = irq_handle_table[IRQn].handler;
+    param    = irq_handle_table[IRQn].param;
+
+    irq_func(IRQn, param);
+
+#ifdef RT_USING_INTERRUPT_INFO
+    irq_handle_table[IRQn].counter++;
+#endif
+
+    return ;
+}
+
+
+void rt_do_mips_cpu_irq(rt_uint32_t ip)
+{
+    rt_uint32_t intstatus, irq, n;
+
+    if (ip == 7) {
+        rt_hw_timer_handler();
+    } else {
+        n = ip - 2;
+        /* Receive interrupt signal, compute the irq */
+        intstatus = (gs232_hw0_icregs+n)->int_isr & (gs232_hw0_icregs+n)->int_en;
+        if (0 == intstatus)
+            return ;
+
+        irq = __rt_ffs(intstatus) - 1;
+        gs232_do_IRQ((n<<5) + irq);
+
+        /* ack interrupt */
+        (gs232_hw0_icregs+n)->int_clr |= (1 << irq);
+    }
+}
+
+
+/*@}*/
+
+

libcpu/mips/gs232/ls1b.h

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ * 
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-08-08     lgnq         first version
+ */
+
+#ifndef __LS1B_H__
+#define __LS1B_H__
+
+#include <gs232.h>
+
+#define LS1B_ACPI_IRQ	0
+#define LS1B_HPET_IRQ	1
+#define LS1B_UART0_IRQ	2
+#define LS1B_UART1_IRQ	3
+#define LS1B_UART2_IRQ	4
+#define LS1B_UART3_IRQ	5
+#define LS1B_CAN0_IRQ	6
+#define LS1B_CAN1_IRQ	7
+#define LS1B_SPI0_IRQ	8
+#define LS1B_SPI1_IRQ	9
+#define LS1B_AC97_IRQ	10
+#define LS1B_MS_IRQ		11
+#define LS1B_KB_IRQ		12
+#define LS1B_DMA0_IRQ	13
+#define LS1B_DMA1_IRQ	14
+#define LS1B_NAND_IRQ	15
+#define LS1B_I2C0_IRQ	16
+#define LS1B_I2C1_IRQ	17
+#define LS1B_PWM0_IRQ	18
+#define LS1B_PWM1_IRQ	19
+#define LS1B_PWM2_IRQ	20
+#define LS1B_PWM3_IRQ	21
+#define LS1B_LPC_IRQ	22
+#define LS1B_EHCI_IRQ	32
+#define LS1B_OHCI_IRQ	33
+#define LS1B_GMAC1_IRQ	34
+#define LS1B_GMAC2_IRQ	35
+#define LS1B_SATA_IRQ	36
+#define LS1B_GPU_IRQ	37
+#define LS1B_PCI_INTA_IRQ 38
+#define LS1B_PCI_INTB_IRQ 39
+#define LS1B_PCI_INTC_IRQ 40
+#define LS1B_PCI_INTD_IRQ 41
+
+#define LS1B_GPIO_IRQ 64
+#define LS1B_GPIO_FIRST_IRQ 64
+#define LS1B_GPIO_IRQ_COUNT 96
+#define LS1B_GPIO_LAST_IRQ  (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1)
+
+#define INT_PCI_INTA	(1<<6)
+#define INT_PCI_INTB	(1<<7)
+#define INT_PCI_INTC	(1<<8)
+#define INT_PCI_INTD	(1<<9)
+
+#define LS1B_LAST_IRQ 159
+#define MIPS_CPU_TIMER_IRQ	167
+#define LS1B_INTREG_BASE 0xbfd01040
+
+#define LS1B_DMA_IRQ_BASE 168
+#define LS1B_DMA_IRQ_COUNT 16
+
+#endif

libcpu/mips/gs232/ls1c.h

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ * 
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date               Author             Notes
+ * 2011-08-08     lgnq                first version
+ * 2015-07-06     chinesebear      modified for loongson 1c
+ */
+
+#ifndef __LS1C_H__
+#define __LS1C_H__
+
+#include <gs232.h>
+
+#define LS1C_ACPI_IRQ    0
+#define LS1C_HPET_IRQ    1
+//#define LS1C_UART0_IRQ    3  // linux����3��v1.4�汾��1c�ֲ�����2�������Σ���ȷ��
+#define LS1C_UART1_IRQ   4
+#define LS1C_UART2_IRQ   5
+#define LS1C_CAN0_IRQ    6
+#define LS1C_CAN1_IRQ    7
+#define LS1C_SPI0_IRQ    8
+#define LS1C_SPI1_IRQ    9
+#define LS1C_AC97_IRQ    10
+#define LS1C_MS_IRQ      11
+#define LS1C_KB_IRQ      12
+#define LS1C_DMA0_IRQ    13
+#define LS1C_DMA1_IRQ    14
+#define LS1C_DMA2_IRQ    15
+#define LS1C_NAND_IRQ    16
+#define LS1C_PWM0_IRQ    17
+#define LS1C_PWM1_IRQ    18
+#define LS1C_PWM2_IRQ    19
+#define LS1C_PWM3_IRQ    20
+#define LS1C_RTC_INT0_IRQ  21
+#define LS1C_RTC_INT1_IRQ  22
+#define LS1C_RTC_INT2_IRQ  23
+#define LS1C_UART3_IRQ   29
+#define LS1C_ADC_IRQ     30
+#define LS1C_SDIO_IRQ    31
+
+
+#define LS1C_EHCI_IRQ   (32+0)
+#define LS1C_OHCI_IRQ   (32+1)
+#define LS1C_OTG_IRQ    (32+2)
+#define LS1C_MAC_IRQ    (32+3)
+#define LS1C_CAM_IRQ    (32+4)
+#define LS1C_UART4_IRQ  (32+5)
+#define LS1C_UART5_IRQ  (32+6)
+#define LS1C_UART6_IRQ  (32+7)
+#define LS1C_UART7_IRQ  (32+8)
+#define LS1C_UART8_IRQ  (32+9)
+#define LS1C_UART9_IRQ  (32+13)
+#define LS1C_UART10_IRQ (32+14)
+#define LS1C_UART11_IRQ (32+15)
+#define LS1C_I2C2_IRQ   (32+17)
+#define LS1C_I2C1_IRQ   (32+18)
+#define LS1C_I2C0_IRQ   (32+19)
+
+
+#define LS1C_GPIO_IRQ       64
+#define LS1C_GPIO_FIRST_IRQ 64
+#define LS1C_GPIO_IRQ_COUNT 96
+#define LS1C_GPIO_LAST_IRQ  (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1)
+
+
+#define LS1C_LAST_IRQ 159
+#define LS1C_INTREG_BASE 0xbfd01040
+
+// ��о1c���жϷ�Ϊ���飬ÿ��32��
+#define LS1C_NR_IRQS    (32*5)
+
+
+// GPIO��ź��жϺ�֮��Ļ���ת��
+#define LS1C_GPIO_TO_IRQ(GPIOn)     (LS1C_GPIO_FIRST_IRQ + (GPIOn))
+#define LS1C_IRQ_TO_GPIO(IRQn)      ((IRQn) - LS1C_GPIO_FIRST_IRQ)
+
+#endif
+

libcpu/mips/gs232/mipscfg.c

@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-05-27     swkyer       first version
+ */
+#include <rtthread.h>
+#include <mips.h>
+
+mips32_core_cfg_t g_mips_core =
+{
+    16,		/* icache_line_size */
+    256,	/* icache_lines_per_way */
+    4,		/* icache_ways */
+    16,		/* dcache_line_size */
+    256,	/* dcache_lines_per_way */
+    4,		/* dcache_ways */
+    16,		/* max_tlb_entries */
+};
+
+static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
+{
+    rt_uint16_t rets = 1;
+
+    while (n--)
+        rets *= b;
+
+    return rets;
+}
+
+static rt_uint16_t m_log2(rt_uint16_t b)
+{
+    rt_uint16_t rets = 0;
+
+    while (b != 1)
+    {
+        b /= 2;
+        rets++;
+    }
+
+    return rets;
+}
+
+/**
+ * read core attribute
+ */
+void mips32_cfg_init(void)
+{
+    rt_uint16_t val;
+    rt_uint32_t cp0_config1;
+
+    cp0_config1 = read_c0_config();
+    if (cp0_config1 & 0x80000000)
+    {
+        cp0_config1 = read_c0_config1();
+
+        val = (cp0_config1 & (7<<22))>>22;
+        g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
+        val = (cp0_config1 & (7<<19))>>19;
+        g_mips_core.icache_line_size = 2 * m_pow(2, val);
+        val = (cp0_config1 & (7<<16))>>16;
+        g_mips_core.icache_ways = val + 1;
+
+        val = (cp0_config1 & (7<<13))>>13;
+        g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
+        val = (cp0_config1 & (7<<10))>>10;
+        g_mips_core.dcache_line_size = 2 * m_pow(2, val);
+        val = (cp0_config1 & (7<<7))>>7;
+        g_mips_core.dcache_ways = val + 1;
+
+        val = (cp0_config1 & (0x3F<<25))>>25;
+        g_mips_core.max_tlb_entries = val + 1;
+    }
+}

libcpu/mips/gs232/timer.c

@@ -0,0 +1,41 @@
+/*
+ * Assembly Macros For MIPS
+ *
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-12-04     Jiaxun Yang  Initial version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <mips.h>
+#include <board.h>
+
+/**
+ * This is the timer interrupt service routine.
+ */
+void rt_hw_timer_handler(void)
+{
+	unsigned int count;
+
+	count = read_c0_compare();
+	write_c0_compare(count);
+	write_c0_count(0);
+
+	/* increase a OS tick */
+	rt_tick_increase();
+}
+
+/**
+ * This function will initial OS timer
+ */
+void rt_hw_timer_init(void)
+{
+	write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
+	write_c0_count(0);
+	mips_unmask_cpu_irq(7);
+}

libcpu/mips/loongson_1b/cache.c

@@ -1,230 +0,0 @@
-/*
- * File      : cache.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- * 2011-08-08     lgnq         modified for LS1B
- */
- 
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-
-#define K0BASE			0x80000000
-#define PRID_LS1B		0x4220
-
-extern void Clear_TagLo (void);
-extern void Invalidate_Icache_Ls1b(unsigned int);
-extern void Invalidate_Dcache_ClearTag_Ls1b(unsigned int);
-extern void Invalidate_Dcache_Fill_Ls1b(unsigned int);
-extern void Writeback_Invalidate_Dcache(unsigned int);
-extern void enable_cpu_cache(void);
-
-typedef struct cacheinfo_t 
-{
-	unsigned int	icache_size;
-	unsigned int	dcache_size;
-	unsigned int	icacheline_size;
-	unsigned int	dcacheline_size;
-} cacheinfo_t ;
-
-typedef struct cacheop_t 
-{
-	void (*Clear_TagLo) (void);
-	void (*Invalidate_Icache) (unsigned int);
-	void (*Invalidate_Dcache_Fill) (unsigned int);
-	void (*Invalidate_Dcache_ClearTag) (unsigned int);
-	void (*Init_Cache)(void);
-} cacheop_t ;
-
-static cacheop_t cacheop, *pcacheop;
-static cacheinfo_t cacheinfo, *pcacheinfo;
-
-int identify_cpu(void)
-{
-    unsigned int cpu_id;
-
-    pcacheop = &cacheop;
-    pcacheinfo = &cacheinfo;
-
-	rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
-    cpu_id = read_c0_prid();
-    switch (cpu_id)
-	{
-	case PRID_LS1B:       
-	    rt_kprintf("CPU:LS1B\n");
-	    pcacheop->Clear_TagLo = Clear_TagLo;
-	    pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1b;
-	    pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1b;
-	    pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1b;
-	    break;
-	default:
-	    rt_kprintf("Unknown CPU type, system halted!\n");
-	    while (1) 
-	    {
-	    	;
-	    }
-	    break;
-    }
-
-    return 0;
-}
-
-void probe_cache(void)
-{
-    unsigned int config1 = read_c0_config1();
-    unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
-    unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
-
-    if ((icache_line_size = ((config1 >> 19) & 7)))
-        icache_line_size = 2 << icache_line_size;
-    else
-        icache_line_size = icache_line_size;
-    icache_sets = 64 << ((config1 >> 22) & 7);
-    icache_ways = 1 + ((config1 >> 16) & 7);
-    icache_size = icache_sets * icache_ways * icache_line_size;
-    
-    if ((dcache_line_size = ((config1 >> 10) & 7)))
-        dcache_line_size = 2 << dcache_line_size;
-    else
-        dcache_line_size = dcache_line_size;
-    dcache_sets = 64 << ((config1 >> 13) & 7);
-    dcache_ways = 1 + ((config1 >> 7) & 7);
-    dcache_size = dcache_sets * dcache_ways * dcache_line_size;
-    
-    rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
-    rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
-
-    pcacheinfo->icache_size = icache_size;
-    pcacheinfo->dcache_size = dcache_size;
-    pcacheinfo->icacheline_size = icache_line_size;
-    pcacheinfo->dcacheline_size = dcache_line_size;
-
-    return ;
-}
-
-void invalidate_writeback_dcache_all(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->dcache_size);
-
-	while (start < end) 
-	{
-		Writeback_Invalidate_Dcache(start);  //hit writeback invalidate 
-		start += pcacheinfo->dcacheline_size;
-	}
-}
-
-void invalidate_writeback_dcache(unsigned long addr, int size)
-{
-	unsigned long start, end;
-			
-	start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
-	end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
-	
-	while (start <end)
-	{
-		Writeback_Invalidate_Dcache(start);
-		start += pcacheinfo->dcacheline_size;
-	}		
-}
-
-void invalidate_icache_all(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->icache_size);
-
-	while (start < end) 
-	{
-		pcacheop->Invalidate_Icache(start); 
-		start += pcacheinfo->icacheline_size;
-	}
-}
-
-void invalidate_dcache_all(void)
-{ 
-	unsigned int start = K0BASE;
-	unsigned int end  = (start + pcacheinfo->dcache_size);
-	while (start <end)
-	{
-		Invalidate_Dcache_Fill_Ls1b(start);
-		start += pcacheinfo->icacheline_size;
-	}
-}
-
-//with cache disabled
-void init_dcache(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->dcache_size);
-
-	while (start < end)
-	{
-		pcacheop->Invalidate_Dcache_ClearTag(start);
-		start += pcacheinfo->dcacheline_size;
-	}
-
-}
-
-void rt_hw_cache_init(void)
-{
-    unsigned int start, end;
-	
-	/* 1. identify cpu and probe cache */
-	identify_cpu();
-	probe_cache();
-
-	start = K0BASE;
-	end = (start + pcacheinfo->icache_size);
-
-    /*
-     *	2. clear CP0 taglo/taghi register;
-     */
-    pcacheop->Clear_TagLo();
-
-	/*
-     *	3. invalidate instruction cache;
-     */
-    while (start < end) 
-    {
-		pcacheop->Invalidate_Icache(start); //index invalidate icache 
-		start += pcacheinfo->icacheline_size;
-    }
-
-    /*
-     *	4. invalidate data cache;
-     */
-    start = K0BASE;
-    end = (start + pcacheinfo->dcache_size);
-    while(start < end) 
-    {
-		pcacheop->Invalidate_Dcache_ClearTag(start); 
-		start += pcacheinfo->dcacheline_size;
-    }
-
-    start = K0BASE;
-    while(start < end) 
-    {
-		pcacheop->Invalidate_Dcache_Fill(start);  //index invalidate dcache
-		start += pcacheinfo->dcacheline_size;
-    }
-
-    start = K0BASE;
-    while(start < end) 
-    {
-		pcacheop->Invalidate_Dcache_ClearTag(start); 
-		start += pcacheinfo->dcacheline_size;
-    }
-
-	/* enable cache */
-	enable_cpu_cache();
-	rt_kprintf("enable cpu cache done\n");
-
-	return ;
-}

libcpu/mips/loongson_1b/cache_gcc.S

@@ -1,219 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-11     bernard      port to Loongson SoC3210
- * 2011-08-08     lgnq         port to Loongson LS1B
- * 2019-07-19     Zhou Yanjie  clean up code
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mipsregs.h"
-#include "../common/mips_def.h"
-#include "../common/asm.h"
-#include "cache.h"
-
-	.ent	cache_init
-    .global cache_init
-    .set noreorder
-cache_init:
-        move t1,ra
-####part 2####
-cache_detect_4way:
-        mfc0    t4, CP0_CONFIG
-        andi    t5, t4, 0x0e00
-        srl     t5, t5, 9     #ic
-        andi    t6, t4, 0x01c0
-        srl     t6, t6, 6     #dc
-        addiu   t8, $0, 1
-        addiu   t9, $0, 2
-                                #set dcache way
-        beq     t6, $0,  cache_d1way
-        addiu   t7, $0, 1       #1 way
-        beq     t6, t8,  cache_d2way
-        addiu   t7, $0, 2       #2 way
-        beq     $0, $0, cache_d4way
-        addiu   t7, $0, 4       #4 way
-cache_d1way:
-        beq     $0, $0, 1f
-        addiu   t6, t6, 12      #1 way
-cache_d2way:
-        beq     $0, $0, 1f
-        addiu   t6, t6, 11      #2 way
-cache_d4way:
-        addiu   t6, t6, 10      #4 way (10), 2 way(11), 1 way(12)
-1:                              #set icache way
-        beq     t5, $0,  cache_i1way
-        addiu   t3, $0, 1       #1 way
-        beq     t5, t8,  cache_i2way
-        addiu   t3, $0, 2       #2 way
-        beq     $0, $0, cache_i4way
-        addiu   t3, $0, 4       #4 way
-cache_i1way:
-        beq     $0, $0, 1f
-        addiu   t5, t5, 12
-cache_i2way:
-        beq     $0, $0, 1f
-        addiu   t5, t5, 11
-cache_i4way:
-        addiu   t5, t5, 10      #4 way (10), 2 way(11), 1 way(12)
-
-1:      addiu   t4, $0, 1
-        sllv    t6, t4, t6
-        sllv    t5, t4, t5
-#if 0
-    la	t0, memvar
-	sw	t7, 0x0(t0) #ways
-	sw	t5, 0x4(t0) #icache size
-	sw	t6, 0x8(t0) #dcache size
-#endif
-####part 3####
-	.set	mips3
-	lui	a0, 0x8000
-	addu	a1, $0, t5
-	addu	a2, $0, t6
-cache_init_d2way:
-#a0=0x80000000, a1=icache_size, a2=dcache_size
-#a3, v0 and v1 used as local registers
-	mtc0	$0, CP0_TAGHI
-	addu	v0, $0, a0
-	addu	v1, a0, a2
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	mtc0	$0, CP0_TAGLO
-	beq	t7, 1, 4f
-	cache	Index_Store_Tag_D, 0x0(v0)	# 1 way
-	beq	t7, 2 ,4f
-	cache	Index_Store_Tag_D, 0x1(v0)	# 2 way
-	cache	Index_Store_Tag_D, 0x2(v0)	# 4 way
-	cache	Index_Store_Tag_D, 0x3(v0)
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_flush_i2way:
-	addu	v0, $0, a0
-	addu	v1, a0, a1
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	beq	t3, 1, 4f
-	cache	Index_Invalidate_I, 0x0(v0)	# 1 way
-	beq	t3, 2, 4f
-	cache	Index_Invalidate_I, 0x1(v0)	# 2 way
-	cache	Index_Invalidate_I, 0x2(v0)
-	cache	Index_Invalidate_I, 0x3(v0)	# 4 way
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_flush_d2way:
-	addu	v0, $0, a0
-	addu	v1, a0, a2
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	beq	t7, 1, 4f
-	cache	Index_Writeback_Inv_D, 0x0(v0) 	#1 way
-	beq	t7, 2, 4f
-	cache	Index_Writeback_Inv_D, 0x1(v0)	# 2 way
-	cache	Index_Writeback_Inv_D, 0x2(v0)
-	cache	Index_Writeback_Inv_D, 0x3(v0)	# 4 way
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_init_finish:
-	jr	t1
-    nop
-    .set reorder
-	.end cache_init
-
-###########################
-#  Enable CPU cache       #
-###########################
-
-LEAF(enable_cpu_cache)
-	.set noreorder
-	mfc0	t0, CP0_CONFIG
-	nop
-	and		t0, ~0x03
-	or		t0, 0x03
-	mtc0	t0, CP0_CONFIG
-	nop
-	.set reorder
-	j	ra
-END (enable_cpu_cache)
-    
-###########################
-#  disable CPU cache      #
-###########################
-
-LEAF(disable_cpu_cache)
-	.set noreorder
-	mfc0	t0, CP0_CONFIG
-	nop
-	and		t0, ~0x03
-	or 		t0, 0x2
-	mtc0	t0, CP0_CONFIG
-	nop
-	.set reorder
-	j	ra
-END (disable_cpu_cache)
-
-/**********************************/
-/* Invalidate Instruction Cache	  */
-/**********************************/
-LEAF(Clear_TagLo)
-	.set 	noreorder
-	mtc0	zero, CP0_TAGLO
-	nop
-	.set 	reorder
-	j		ra
-END(Clear_TagLo)
-
-    .set mips3
-/**********************************/
-/* Invalidate Instruction Cache	  */
-/**********************************/
-LEAF(Invalidate_Icache_Ls1b)
-	.set	noreorder
-	cache	Index_Invalidate_I,0(a0)
-	cache	Index_Invalidate_I,1(a0)
-	cache	Index_Invalidate_I,2(a0)
-	cache	Index_Invalidate_I,3(a0)
-	.set	reorder
-	j		ra
-END(Invalidate_Icache_Ls1b)
-
-/**********************************/
-/* Invalidate Data Cache		  */
-/**********************************/
-LEAF(Invalidate_Dcache_ClearTag_Ls1b)
-	.set	noreorder
-	cache	Index_Store_Tag_D, 0(a0)	# BDSLOT: clear tag
-	cache	Index_Store_Tag_D, 1(a0)	# BDSLOT: clear tag
-	.set	reorder
-	j		ra
-END(Invalidate_Dcache_ClearTag_Ls1b)
-
-LEAF(Invalidate_Dcache_Fill_Ls1b)
-	.set	noreorder
-	cache	Index_Writeback_Inv_D, 0(a0)	# BDSLOT: clear tag
-	cache	Index_Writeback_Inv_D, 1(a0)	# BDSLOT: clear tag
-	.set	reorder
-	j		ra
-END(Invalidate_Dcache_Fill_Ls1b)
-
-LEAF(Writeback_Invalidate_Dcache)
-	.set noreorder
-	cache	Hit_Writeback_Inv_D, (a0)
-	.set reorder
-	j	ra
-END(Writeback_Invalidate_Dcache)
-    .set mips0

libcpu/mips/loongson_1b/cpuport.c

@@ -1,124 +0,0 @@
-/*
- * File      : cpuport.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- * 2010-09-11     Bernard      add CPU reset implementation
- */
-
-#include <rtthread.h>
-#include "ls1b.h"
-
-/**
- * @addtogroup Loongson LS1B
- */
-
-/*@{*/
-
-/**
- * this function will reset CPU
- *
- */
-void rt_hw_cpu_reset(void)
-{
-	/* open the watch-dog */
-	WDT_EN = 0x01; 		/* watch dog enable */
-	WDT_TIMER = 0x01;	/* watch dog will be timeout after 1 tick */
-	WDT_SET = 0x01;		/* watch dog start */
-
-	rt_kprintf("reboot system...\n");
-	while (1);
-}
-
-/**
- * this function will shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown(void)
-{
-	rt_kprintf("shutdown...\n");
-
-	while (1);
-}
-
-extern rt_uint32_t cp0_get_cause(void);
-extern rt_uint32_t cp0_get_status(void);
-extern rt_uint32_t cp0_get_hi(void);
-extern rt_uint32_t cp0_get_lo(void);
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
-	rt_uint32_t *stk;
-    static rt_uint32_t g_sr = 0;
-
-    if (g_sr == 0)
-    {
-    	g_sr = cp0_get_status();
-    	g_sr &= 0xfffffffe;
-    	g_sr |= 0x8401;
-    }
-
-    /** Start at stack top */
-    stk = (rt_uint32_t *)stack_addr;
-	*(stk)   = (rt_uint32_t) tentry;        /* pc: Entry Point */
-	*(--stk) = (rt_uint32_t) 0xeeee; 		/* c0_cause */
-	*(--stk) = (rt_uint32_t) 0xffff;		/* c0_badvaddr */
-	*(--stk) = (rt_uint32_t) cp0_get_lo();	/* lo */
-	*(--stk) = (rt_uint32_t) cp0_get_hi();	/* hi */
-	*(--stk) = (rt_uint32_t) g_sr; 			/* C0_SR: HW2 = En, IE = En */
-	*(--stk) = (rt_uint32_t) texit;	        /* ra */
-	*(--stk) = (rt_uint32_t) 0x0000001e;	/* s8 */
-	*(--stk) = (rt_uint32_t) stack_addr;	/* sp */
-	*(--stk) = (rt_uint32_t) 0x0000001c;	/* gp */
-	*(--stk) = (rt_uint32_t) 0x0000001b;	/* k1 */
-	*(--stk) = (rt_uint32_t) 0x0000001a;	/* k0 */
-	*(--stk) = (rt_uint32_t) 0x00000019;	/* t9 */
-	*(--stk) = (rt_uint32_t) 0x00000018;	/* t8 */
-	*(--stk) = (rt_uint32_t) 0x00000017;	/* s7 */
-	*(--stk) = (rt_uint32_t) 0x00000016;	/* s6 */
-	*(--stk) = (rt_uint32_t) 0x00000015;	/* s5 */
-	*(--stk) = (rt_uint32_t) 0x00000014;	/* s4 */
-	*(--stk) = (rt_uint32_t) 0x00000013;	/* s3 */
-	*(--stk) = (rt_uint32_t) 0x00000012;	/* s2 */
-	*(--stk) = (rt_uint32_t) 0x00000011;	/* s1 */
-	*(--stk) = (rt_uint32_t) 0x00000010;	/* s0 */
-	*(--stk) = (rt_uint32_t) 0x0000000f;	/* t7 */
-	*(--stk) = (rt_uint32_t) 0x0000000e;	/* t6 */
-	*(--stk) = (rt_uint32_t) 0x0000000d;	/* t5 */
-	*(--stk) = (rt_uint32_t) 0x0000000c;	/* t4 */
-	*(--stk) = (rt_uint32_t) 0x0000000b;	/* t3 */
-	*(--stk) = (rt_uint32_t) 0x0000000a; 	/* t2 */
-	*(--stk) = (rt_uint32_t) 0x00000009;	/* t1 */
-	*(--stk) = (rt_uint32_t) 0x00000008;	/* t0 */
-	*(--stk) = (rt_uint32_t) 0x00000007;	/* a3 */
-	*(--stk) = (rt_uint32_t) 0x00000006;	/* a2 */
-	*(--stk) = (rt_uint32_t) 0x00000005;	/* a1 */
-	*(--stk) = (rt_uint32_t) parameter;	    /* a0 */
-	*(--stk) = (rt_uint32_t) 0x00000003;	/* v1 */
-	*(--stk) = (rt_uint32_t) 0x00000002;	/* v0 */
-	*(--stk) = (rt_uint32_t) 0x00000001;	/* at */
-	*(--stk) = (rt_uint32_t) 0x00000000;	/* zero */
-
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
-}
-
-/*@}*/
-

libcpu/mips/loongson_1b/exception.c

@@ -1,91 +0,0 @@
-/*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- */
-#include <rtthread.h>
-#include <rthw.h>
-#include "../common/exception.h"
-#include "../common/mipsregs.h"
-
-/**
- * @addtogroup Loongson
- */
-
-/*@{*/
-
-/**
- * exception handle table
- */
-#define RT_EXCEPTION_MAX	8
-exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
-
-/**
- * setup the exception handle
- */
-exception_func_t rt_set_except_vector(int n, exception_func_t func)
-{
-    exception_func_t old_handler = sys_exception_handlers[n];
-
-    if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
-    {
-        return 0;
-    }
-
-    sys_exception_handlers[n] = func;
-
-    return old_handler;
-}
-
-void tlb_refill_handler(void)
-{
-	rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-void cache_error_handler(void)
-{
-	rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-static void unhandled_exception_handle(pt_regs_t *regs)
-{
-	rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
-}
-
-void install_default_execpt_handle(void)
-{
-	rt_int32_t i;
-
-	for (i=0; i<RT_EXCEPTION_MAX; i++)
-		sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
-}
-
-void exception_handler(pt_regs_t *regs)
-{
-	rt_uint32_t cause;
-	rt_uint32_t index;
-
-	cause = (read_c0_cause() & read_c0_config());
-	cause = (cause & 0xfc00) >> 8;
-
-	for (index = RT_EXCEPTION_MAX; index > 0; index --)
-	{
-		if (cause & (1 << index))
-		{
-			sys_exception_handlers[index](regs);
-			cause &= ~(1 << index);
-		}
-	}
-}
-
-/*@}*/

libcpu/mips/loongson_1b/interrupt.c

@@ -1,188 +0,0 @@
-/*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-10-15     Bernard      first version
- * 2010-10-15     lgnq         modified for LS1B
- * 2013-03-29     aozima       Modify the interrupt interface implementations.
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include "ls1b.h"
-
-#define MAX_INTR 32
-
-extern rt_uint32_t rt_interrupt_nest;
-rt_uint32_t rt_interrupt_from_thread;
-rt_uint32_t rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-static struct rt_irq_desc irq_handle_table[MAX_INTR];
-void rt_interrupt_dispatch(void *ptreg);
-void rt_hw_timer_handler();
-
-static struct ls1b_intc_regs volatile *ls1b_hw0_icregs
-= (struct ls1b_intc_regs volatile *)(LS1B_INTREG_BASE);
-
-/**
- * @addtogroup Loongson LS1B
- */
-
-/*@{*/
-
-static void rt_hw_interrupt_handler(int vector, void *param)
-{
-    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
-    rt_int32_t idx;
-
-    /* pci active low */
-    ls1b_hw0_icregs->int_pol = -1;	   //must be done here 20110802 lgnq
-    /* make all interrupts level triggered */
-    (ls1b_hw0_icregs+0)->int_edge = 0x0000e000;
-    /* mask all interrupts */
-    (ls1b_hw0_icregs+0)->int_clr = 0xffffffff;
-
-    rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
-    for (idx = 0; idx < MAX_INTR; idx ++)
-    {
-        irq_handle_table[idx].handler = rt_hw_interrupt_handler;
-    }
-
-    /* init interrupt nest, and context in thread sp */
-    rt_interrupt_nest = 0;
-    rt_interrupt_from_thread = 0;
-    rt_interrupt_to_thread = 0;
-    rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
-    /* mask interrupt */
-    (ls1b_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
-    (ls1b_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-                                         void *param, const char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if (vector >= 0 && vector < MAX_INTR)
-    {
-        old_handler = irq_handle_table[vector].handler;
-
-#ifdef RT_USING_INTERRUPT_INFO
-        rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-        irq_handle_table[vector].handler = handler;
-        irq_handle_table[vector].param = param;
-    }
-
-    return old_handler;
-}
-
-void rt_interrupt_dispatch(void *ptreg)
-{
-    int irq;
-    void *param;
-    rt_isr_handler_t irq_func;
-    static rt_uint32_t status = 0;
-    rt_uint32_t c0_status;
-    rt_uint32_t c0_cause;
-    volatile rt_uint32_t cause_im;
-    volatile rt_uint32_t status_im;
-    rt_uint32_t pending_im;
-
-    /* check os timer */
-    c0_status = read_c0_status();
-    c0_cause = read_c0_cause();
-
-    cause_im = c0_cause & ST0_IM;
-    status_im = c0_status & ST0_IM;
-    pending_im = cause_im & status_im;
-
-    if (pending_im & CAUSEF_IP7)
-    {
-        rt_hw_timer_handler();
-    }
-
-    if (pending_im & CAUSEF_IP2)
-    {
-        /* the hardware interrupt */
-        status = ls1b_hw0_icregs->int_isr;
-        if (!status)
-            return;
-
-        for (irq = MAX_INTR; irq > 0; --irq)
-        {
-            if ((status & (1 << irq)))
-            {
-                status &= ~(1 << irq);
-
-                irq_func = irq_handle_table[irq].handler;
-                param = irq_handle_table[irq].param;
-
-                /* do interrupt */
-                irq_func(irq, param);
-
-#ifdef RT_USING_INTERRUPT_INFO
-                irq_handle_table[irq].counter++;
-#endif /* RT_USING_INTERRUPT_INFO */
-
-                /* ack interrupt */
-                ls1b_hw0_icregs->int_clr |= (1 << irq);
-            }
-        }
-    }
-    else if (pending_im & CAUSEF_IP3)
-    {
-        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
-    }
-    else if (pending_im & CAUSEF_IP4)
-    {
-        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
-    }
-    else if (pending_im & CAUSEF_IP5)
-    {
-        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
-    }
-    else if (pending_im & CAUSEF_IP6)
-    {
-        rt_kprintf("%s %d\r\n", __FUNCTION__, __LINE__);
-    }
-}
-
-/*@}*/

libcpu/mips/loongson_1b/ls1b.h

@@ -1,140 +0,0 @@
-/*
- * File      : ls1b.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-08-08     lgnq         first version
- */
-
-#ifndef __LS1B_H__
-#define __LS1B_H__
-
-#include "../common/mipsregs.h"
-
-#define LS1B_ACPI_IRQ	0
-#define LS1B_HPET_IRQ	1
-#define LS1B_UART0_IRQ	2
-#define LS1B_UART1_IRQ	3
-#define LS1B_UART2_IRQ	4
-#define LS1B_UART3_IRQ	5
-#define LS1B_CAN0_IRQ	6
-#define LS1B_CAN1_IRQ	7
-#define LS1B_SPI0_IRQ	8
-#define LS1B_SPI1_IRQ	9
-#define LS1B_AC97_IRQ	10
-#define LS1B_MS_IRQ		11
-#define LS1B_KB_IRQ		12
-#define LS1B_DMA0_IRQ	13
-#define LS1B_DMA1_IRQ	14
-#define LS1B_NAND_IRQ	15
-#define LS1B_I2C0_IRQ	16
-#define LS1B_I2C1_IRQ	17
-#define LS1B_PWM0_IRQ	18
-#define LS1B_PWM1_IRQ	19
-#define LS1B_PWM2_IRQ	20
-#define LS1B_PWM3_IRQ	21
-#define LS1B_LPC_IRQ	22
-#define LS1B_EHCI_IRQ	32
-#define LS1B_OHCI_IRQ	33
-#define LS1B_GMAC1_IRQ	34
-#define LS1B_GMAC2_IRQ	35
-#define LS1B_SATA_IRQ	36
-#define LS1B_GPU_IRQ	37
-#define LS1B_PCI_INTA_IRQ 38
-#define LS1B_PCI_INTB_IRQ 39
-#define LS1B_PCI_INTC_IRQ 40
-#define LS1B_PCI_INTD_IRQ 41
-
-#define LS1B_GPIO_IRQ 64
-#define LS1B_GPIO_FIRST_IRQ 64
-#define LS1B_GPIO_IRQ_COUNT 96
-#define LS1B_GPIO_LAST_IRQ  (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1)
-
-#define INT_PCI_INTA	(1<<6)
-#define INT_PCI_INTB	(1<<7)
-#define INT_PCI_INTC	(1<<8)
-#define INT_PCI_INTD	(1<<9)
-
-#define LS1B_LAST_IRQ 159
-#define MIPS_CPU_TIMER_IRQ	167
-#define LS1B_INTREG_BASE 0xbfd01040
-
-#define LS1B_DMA_IRQ_BASE 168
-#define LS1B_DMA_IRQ_COUNT 16
-
-struct ls1b_intc_regs
-{
-	volatile unsigned int int_isr;
-	volatile unsigned int int_en;
-	volatile unsigned int int_set;
-	volatile unsigned int int_clr;		/* offset 0x10*/
-	volatile unsigned int int_pol;
-   	volatile unsigned int int_edge;		/* offset 0 */
-}; 
-
-struct ls1b_cop_global_regs
-{
-	volatile unsigned int control;
-	volatile unsigned int rd_inten;
-	volatile unsigned int wr_inten;
-	volatile unsigned int rd_intisr;		/* offset 0x10*/
-	volatile unsigned int wr_intisr;
-	unsigned int unused[11];
-} ; 
-
-struct ls1b_cop_channel_regs
-{
-	volatile unsigned int rd_control;
-	volatile unsigned int rd_src;
-	volatile unsigned int rd_cnt;
-	volatile unsigned int rd_status;		/* offset 0x10*/
-	volatile unsigned int wr_control;
-	volatile unsigned int wr_src;
-	volatile unsigned int wr_cnt;
-	volatile unsigned int wr_status;		/* offset 0x10*/
-} ; 
-
-struct ls1b_cop_regs
-{
-	struct ls1b_cop_global_regs global;
-	struct ls1b_cop_channel_regs chan[8][2];
-} ;
-
-#define __REG8(addr)		*((volatile unsigned char *)(addr))
-#define __REG16(addr)		*((volatile unsigned short *)(addr))
-#define __REG32(addr)		*((volatile unsigned int *)(addr))
-
-#define GMAC0_BASE			0xBFE10000
-#define GMAC0_DMA_BASE		0xBFE11000
-#define GMAC1_BASE			0xBFE20000
-#define GMAC1_DMA_BASE		0xBFE21000
-#define I2C0_BASE			0xBFE58000
-#define PWM0_BASE			0xBFE5C000
-#define PWM1_BASE			0xBFE5C010
-#define PWM2_BASE			0xBFE5C020
-#define PWM3_BASE			0xBFE5C030
-#define WDT_BASE			0xBFE5C060
-#define RTC_BASE			0xBFE64000
-#define I2C1_BASE			0xBFE68000
-#define I2C2_BASE			0xBFE70000
-#define AC97_BASE			0xBFE74000
-#define NAND_BASE			0xBFE78000
-#define SPI_BASE			0xBFE80000
-#define CAN1_BASE			0xBF004300
-#define CAN0_BASE			0xBF004400
-
-/* Watch Dog registers */
-#define WDT_EN				__REG32(WDT_BASE + 0x00)
-#define WDT_SET				__REG32(WDT_BASE + 0x04)
-#define WDT_TIMER			__REG32(WDT_BASE + 0x08)
-
-#define PLL_FREQ 				__REG32(0xbfe78030)
-#define PLL_DIV_PARAM 			__REG32(0xbfe78034)
-
-#endif

libcpu/mips/loongson_1b/mipscfg.c

@@ -1,82 +0,0 @@
-/*
- * File      : mipscfg.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-27     swkyer       first version
- */
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-#include "../common/mipscfg.h"
-
-mips32_core_cfg_t g_mips_core =
-{
-	16,		/* icache_line_size */
-	256,	/* icache_lines_per_way */
-	4,		/* icache_ways */
-	16,		/* dcache_line_size */
-	256,	/* dcache_lines_per_way */
-	4,		/* dcache_ways */
-	16,		/* max_tlb_entries */
-};
-
-static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
-{
-	rt_uint16_t rets = 1;
-
-    while (n--)
-        rets *= b;
-
-    return rets;
-}
-
-static rt_uint16_t m_log2(rt_uint16_t b)
-{
-	rt_uint16_t rets = 0;
-
-    while (b != 1)
-    {
-        b /= 2;
-        rets++;
-    }
-
-    return rets;
-}
-
-/**
- * read core attribute
- */
-void mips32_cfg_init(void)
-{
-	rt_uint16_t val;
-	rt_uint32_t cp0_config1;
-
-	cp0_config1 = read_c0_config();
-	if (cp0_config1 & 0x80000000)
-	{
-		cp0_config1 = read_c0_config1();
-
-		val = (cp0_config1 & (7<<22))>>22;
-		g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<19))>>19;
-		g_mips_core.icache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<16))>>16;
-		g_mips_core.icache_ways = val + 1;
-
-		val = (cp0_config1 & (7<<13))>>13;
-		g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<10))>>10;
-		g_mips_core.dcache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<7))>>7;
-		g_mips_core.dcache_ways = val + 1;
-
-		val = (cp0_config1 & (0x3F<<25))>>25;
-		g_mips_core.max_tlb_entries = val + 1;
-	}
-}

libcpu/mips/loongson_1b/start_gcc.S

@@ -1,138 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-04     bernard      porting to Jz47xx
- * 2019-07-19     Zhou Yanjie  clean up code
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mips_def.h"
-#include "../common/stackframe.h"
-
-	.section ".start", "ax"
-	.set noreorder
-
-	/* the program entry */
-	.globl  _start
-_start:
-	.set	noreorder
-	la	ra, _start
-
-	/* disable interrupt */
-	mfc0	t0, CP0_STATUS
-	and 	t0, 0xfffffffe	# By default it will be disabled.
-	mtc0	t0, CP0_STATUS	# Set CPU to disable interrupt.
-	nop
-
-	/* disable cache */
-	mfc0	t0, CP0_CONFIG
-	and	t0, 0xfffffff8
-	or	t0, 0x2		# disable,!default value is not it!
-	mtc0	t0, CP0_CONFIG	# Set CPU to disable cache.
-	nop
-
-	/* setup stack pointer */
-	li	sp, SYSTEM_STACK
-	la	gp, _gp
-
-	/* clear bss */
-	la	t0, __bss_start
-	la	t1, __bss_end
-_clr_bss_loop:
-	sw	zero, 0(t0)
-	bne	t0, t1, _clr_bss_loop
-	addiu	t0, t0, 4
-
-	/* jump to RT-Thread RTOS */
-	jal	rtthread_startup
-	nop
-
-	/* restart, never die */
-	j	_start
-	nop
-	.set	reorder
-
-	.globl  cp0_get_cause
-cp0_get_cause:
-	mfc0	v0, CP0_CAUSE
-	jr	ra
-	nop
-
-	.globl  cp0_get_status
-cp0_get_status:
-	mfc0	v0, CP0_STATUS
-	jr	ra
-	nop
-
-	.globl	cp0_get_hi
-cp0_get_hi:
-	mfhi	v0
-	jr	ra
-	nop
-
-	.globl	cp0_get_lo
-cp0_get_lo:
-	mflo	v0
-	jr	ra
-	nop
-
-	.extern tlb_refill_handler
-	.extern cache_error_handler
-
-	/* Exception Handler */
-
-	/* 0x0 - TLB refill handler */
-	.section .vectors.1, "ax", %progbits
-	.global tlb_refill_exception
-	.type	tlb_refill_exception,@function
-tlb_refill_exception:
-	j	tlb_refill_handler
-	nop
-	
-	/* 0x100 - Cache error handler */
-	.section .vectors.2, "ax", %progbits
-	j	cache_error_handler
-	nop
-    
-	/* 0x180 - Exception/Interrupt handler */
-	.section .vectors.3, "ax", %progbits
-	.global general_exception
-	.type	general_exception,@function
-general_exception:
-	j	_general_exception_handler
-	nop
-    
-	/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
-	.section .vectors.4, "ax", %progbits
-	.global irq_exception
-	.type	irq_exception,@function
-irq_exception:
-	j	_irq_handler
-	nop
-	
-	.section .vectors, "ax", %progbits
-	.extern mips_irq_handle
-
-	/* general exception handler */
-_general_exception_handler:
-	.set	noreorder
-	la	k0, mips_irq_handle
-	jr	k0
-	nop
-	.set	reorder
-
-	/* interrupt handler */
-_irq_handler:
-	.set	noreorder
-	la	k0, mips_irq_handle
-	jr	k0
-	nop
-	.set	reorder

libcpu/mips/loongson_1c/SConscript

@@ -1,14 +0,0 @@
-# RT-Thread building script for component
-
-from building import *
-
-Import('rtconfig')
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
-CPPPATH = [cwd]
-ASFLAGS = ''
-
-group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
-
-Return('group')

libcpu/mips/loongson_1c/cache.c

@@ -1,233 +0,0 @@
-/*
- * File      : cache.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date                Author            Notes
- * 2010-07-09     Bernard        first version
- * 2011-08-08     lgnq             modified for LS1B
- * 2015-07-08     chinesebear   modified for loongson 1c
- */
- 
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-
-#define K0BASE			0x80000000
-#define PRID_LS1C		0x4220
-
-extern void Clear_TagLo (void);
-extern void Invalidate_Icache_Ls1c(unsigned int);
-extern void Invalidate_Dcache_ClearTag_Ls1c(unsigned int);
-extern void Invalidate_Dcache_Fill_Ls1c(unsigned int);
-extern void Writeback_Invalidate_Dcache(unsigned int);
-extern void enable_cpu_cache(void);
-
-typedef struct cacheinfo_t 
-{
-	unsigned int	icache_size;
-	unsigned int	dcache_size;
-	unsigned int	icacheline_size;
-	unsigned int	dcacheline_size;
-} cacheinfo_t ;
-
-typedef struct cacheop_t 
-{
-	void (*Clear_TagLo) (void);
-	void (*Invalidate_Icache) (unsigned int);
-	void (*Invalidate_Dcache_Fill) (unsigned int);
-	void (*Invalidate_Dcache_ClearTag) (unsigned int);
-	void (*Init_Cache)(void);
-} cacheop_t ;
-
-static cacheop_t cacheop, *pcacheop;
-static cacheinfo_t cacheinfo, *pcacheinfo;
-
-int identify_cpu(void)
-{
-    unsigned int cpu_id;
-
-    pcacheop = &cacheop;
-    pcacheinfo = &cacheinfo;
-
-	rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
-    cpu_id = read_c0_prid();
-    switch (cpu_id)
-	{
-	case PRID_LS1C:       
-	    rt_kprintf("CPU:Loongson 1C\n");
-	    pcacheop->Clear_TagLo = Clear_TagLo;
-	    pcacheop->Invalidate_Icache = Invalidate_Icache_Ls1c;
-	    pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Ls1c;
-	    pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Ls1c;
-	    break;
-	default:
-	    rt_kprintf("Unknown CPU type, system halted!\n");
-	    while (1) 
-	    {
-	    	;
-	    }
-	    break;
-    }
-
-    return 0;
-}
-
-void probe_cache(void)
-{
-    unsigned int config1 = read_c0_config1();
-    unsigned int icache_size, icache_line_size, icache_sets, icache_ways;
-    unsigned int dcache_size, dcache_line_size, dcache_sets, dcache_ways;
-
-    if ((icache_line_size = ((config1 >> 19) & 7)))
-        icache_line_size = 2 << icache_line_size;
-    else
-        icache_line_size = icache_line_size;
-    icache_sets = 64 << ((config1 >> 22) & 7);
-    icache_ways = 1 + ((config1 >> 16) & 7);
-    icache_size = icache_sets * icache_ways * icache_line_size;
-    
-    if ((dcache_line_size = ((config1 >> 10) & 7)))
-        dcache_line_size = 2 << dcache_line_size;
-    else
-        dcache_line_size = dcache_line_size;
-    dcache_sets = 64 << ((config1 >> 13) & 7);
-    dcache_ways = 1 + ((config1 >> 7) & 7);
-    dcache_size = dcache_sets * dcache_ways * dcache_line_size;
-    
-    rt_kprintf("DCache %2dkb, linesize %d bytes.\n", dcache_size >> 10, dcache_line_size);
-    rt_kprintf("ICache %2dkb, linesize %d bytes.\n", icache_size >> 10, icache_line_size);
-
-    pcacheinfo->icache_size = icache_size;
-    pcacheinfo->dcache_size = dcache_size;
-    pcacheinfo->icacheline_size = icache_line_size;
-    pcacheinfo->dcacheline_size = dcache_line_size;
-
-    return ;
-}
-
-void invalidate_writeback_dcache_all(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->dcache_size);
-
-	while (start < end) 
-	{
-		Writeback_Invalidate_Dcache(start);  //hit writeback invalidate 
-		start += pcacheinfo->dcacheline_size;
-	}
-}
-
-void invalidate_writeback_dcache(unsigned long addr, int size)
-{
-	unsigned long start, end;
-			
-	start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
-	end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
-	
-	while (start <end)
-	{
-		Writeback_Invalidate_Dcache(start);
-		start += pcacheinfo->dcacheline_size;
-	}		
-}
-
-void invalidate_icache_all(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->icache_size);
-
-	while (start < end) 
-	{
-		pcacheop->Invalidate_Icache(start); 
-		start += pcacheinfo->icacheline_size;
-	}
-}
-
-void invalidate_dcache_all(void)
-{ 
-	unsigned int start = K0BASE;
-	unsigned int end  = (start + pcacheinfo->dcache_size);
-	while (start <end)
-	{
-		Invalidate_Dcache_Fill_Ls1c(start);
-		start += pcacheinfo->icacheline_size;
-	}
-}
-
-//with cache disabled
-void init_dcache(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->dcache_size);
-
-	while (start < end)
-	{
-		pcacheop->Invalidate_Dcache_ClearTag(start);
-		start += pcacheinfo->dcacheline_size;
-	}
-
-}
-
-void rt_hw_cache_init(void)
-{
-    unsigned int start, end;
-	
-	/* 1. identify cpu and probe cache */
-	identify_cpu();
-	probe_cache();
-
-	start = K0BASE;
-	end = (start + pcacheinfo->icache_size);
-
-    /*
-     *	2. clear CP0 taglo/taghi register;
-     */
-    pcacheop->Clear_TagLo();
-
-	/*
-     *	3. invalidate instruction cache;
-     */
-    while (start < end) 
-    {
-		pcacheop->Invalidate_Icache(start); //index invalidate icache 
-		start += pcacheinfo->icacheline_size;
-    }
-
-    /*
-     *	4. invalidate data cache;
-     */
-    start = K0BASE;
-    end = (start + pcacheinfo->dcache_size);
-    while(start < end) 
-    {
-		pcacheop->Invalidate_Dcache_ClearTag(start); 
-		start += pcacheinfo->dcacheline_size;
-    }
-
-    start = K0BASE;
-    while(start < end) 
-    {
-		pcacheop->Invalidate_Dcache_Fill(start);  //index invalidate dcache
-		start += pcacheinfo->dcacheline_size;
-    }
-
-    start = K0BASE;
-    while(start < end) 
-    {
-		pcacheop->Invalidate_Dcache_ClearTag(start); 
-		start += pcacheinfo->dcacheline_size;
-    }
-
-	/* enable cache */
-	enable_cpu_cache();
-	rt_kprintf("enable cpu cache done\n");
-
-	return ;
-}
-
-

libcpu/mips/loongson_1c/cache.h

@@ -1,52 +0,0 @@
-/*
- * File      : cache.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- * 2011-08-08     lgnq         modified for LS1B
- */
-#ifndef	__CACHE_H__
-#define	__CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_I		0x04
-#define Index_Load_Tag_D		0x05
-#define Index_Load_Tag_SI		0x06
-#define Index_Load_Tag_SD		0x07
-#define Index_Store_Tag_I		0x08
-#define Index_Store_Tag_D		0x09
-#define Index_Store_Tag_SI		0x0A
-#define Index_Store_Tag_SD		0x0B
-#define Create_Dirty_Excl_D		0x0d
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_I		0x10
-#define Hit_Invalidate_D		0x11
-#define Hit_Invalidate_SI		0x12
-#define Hit_Invalidate_SD		0x13
-#define Fill					0x14
-#define Hit_Writeback_Inv_D		0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_I			0x18
-#define Hit_Writeback_D			0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD		0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI		0x1e
-#define Hit_Set_Virtual_SD		0x1f
-
-#endif

libcpu/mips/loongson_1c/context_gcc.S

@@ -1,163 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-11     bernard      port to Loongson SoC3210
- * 2011-08-08     lgnq         port to Loongson LS1B
- * 2019-07-19     Zhou Yanjie  clean up code
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mips_def.h"
-#include "../common/stackframe.h"
-#include "stackframe_fpu.h"
-
-    .section ".text", "ax"
-    .set noreorder
-
-/*
- * rt_base_t rt_hw_interrupt_disable()
- */
-    .globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mfc0    v0, CP0_STATUS
-    and     v1, v0, 0xfffffffe
-    mtc0    v1, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level)
- */
-    .globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    ori     a0, 0x00000800   
-    mtc0    a0, CP0_STATUS
-    ehb
-    mfc0    v0, CP0_CAUSE
-    ehb
-    or      v1, v0, 0x800000                 //EBASE + 0x200                                                                                                 
-    mtc0    v1, CP0_CAUSE
-    ehb
-    jr      ra
-    nop
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
- * a0 --> from
- * a1 --> to
- */
-    .globl rt_hw_context_switch
-rt_hw_context_switch:
-    mtc0    ra, CP0_EPC
-    SAVE_ALL
-    SAVE_FPU
-
-    sw      sp, 0(a0)       /* store sp in preempted tasks TCB */
-    lw      sp, 0(a1)       /* get new task stack pointer */
-
-    RESTORE_FPU
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to)/*
- * a0 --> to
- */
-    .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    lw      sp, 0(a0)       /* get new task stack pointer */
-
-    RESTORE_FPU
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
- */
-    .globl rt_thread_switch_interrupt_flag
-    .globl rt_interrupt_from_thread
-    .globl rt_interrupt_to_thread
-    .globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-    la      t0, rt_thread_switch_interrupt_flag
-    lw      t1, 0(t0)
-    nop
-    bnez    t1, _reswitch
-    nop
-    li      t1, 0x01                       /* set rt_thread_switch_interrupt_flag to 1 */
-    sw      t1, 0(t0)
-    la      t0, rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
-    sw      a0, 0(t0)
-_reswitch:
-    la      t0, rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
-    sw      a1, 0(t0)
-    jr      ra
-    nop
-
-/*
- * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
- */
-    .globl rt_interrupt_enter
-    .globl rt_interrupt_leave
-    .globl mips_irq_handle
-mips_irq_handle:
-    SAVE_ALL
-    SAVE_FPU
-
-    mfc0    t0, CP0_CAUSE
-    and     t1, t0, 0xff
-	bnez	t1, spurious_interrupt		/* check exception */
-	nop
-
-	/* let k0 keep the current context sp */
-    move    k0, sp 
-    /* switch to kernel stack */
-    li      sp, SYSTEM_STACK
-
-    jal     rt_interrupt_enter
-    nop
-    jal     rt_interrupt_dispatch
-    nop
-    jal     rt_interrupt_leave
-    nop
-
-    /* switch sp back to thread's context */
-    move    sp, k0
-
-    /*
-     * if rt_thread_switch_interrupt_flag set, jump to
-     * rt_hw_context_switch_interrupt_do and don't return
-     */
-    la      k0, rt_thread_switch_interrupt_flag
-    lw      k1, 0(k0)
-    beqz    k1, spurious_interrupt
-    nop
-    sw      zero, 0(k0)                     /* clear flag */
-	nop
-
-    /*
-     * switch to the new thread
-     */
-    la      k0, rt_interrupt_from_thread
-    lw      k1, 0(k0)
-    nop
-    sw      sp, 0(k1)                       /* store sp in preempted tasks's TCB */
-
-    la      k0, rt_interrupt_to_thread
-    lw      k1, 0(k0)
-    nop
-    lw      sp, 0(k1)                       /* get new task's stack pointer */
-    j       spurious_interrupt
-    nop
-
-spurious_interrupt:
-    RESTORE_FPU
-    RESTORE_ALL_AND_RET
-
-    .set reorder

libcpu/mips/loongson_1c/cpuport.c

@@ -1,166 +0,0 @@
-/*
- * File      : cpuport.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date                Author         Notes
- * 2010-07-09     Bernard        first version
- * 2010-09-11     Bernard        add CPU reset implementation
- * 2015-07-06     chinesebear  modified for loongson 1c
- */
-
-#include <rtthread.h>
-#include "ls1c.h"
-
-register rt_uint32_t $GP __asm__ ("$28");
-
-/**
- * @addtogroup Loongson LS1B
- */
-
-/*@{*/
-
-/**
- * this function will reset CPU
- *
- */
-void rt_hw_cpu_reset(void)
-{
-	/* open the watch-dog */
-	WDT_EN = 0x01; 		/* watch dog enable */
-	WDT_TIMER = 0x01;	/* watch dog will be timeout after 1 tick */
-	WDT_SET = 0x01;		/* watch dog start */
-
-	rt_kprintf("reboot system...\n");
-	while (1);
-}
-
-/**
- * this function will shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown(void)
-{
-	rt_kprintf("shutdown...\n");
-
-	while (1);
-}
-
-extern rt_uint32_t cp0_get_cause(void);
-extern rt_uint32_t cp0_get_status(void);
-extern rt_uint32_t cp0_get_hi(void);
-extern rt_uint32_t cp0_get_lo(void);
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
-	rt_uint32_t *stk;
-    static rt_uint32_t g_sr = 0;
-	static rt_uint32_t g_gp = 0;
-
-    if (g_sr == 0)
-    {
-    	g_sr = cp0_get_status();
-    	g_sr &= 0xfffffffe;
-    	g_sr |= 0x8401;
-
-		g_gp = $GP;
-    }
-
-    /** Start at stack top */
-    stk = (rt_uint32_t *)stack_addr;
-	*(stk)   = (rt_uint32_t) tentry;        /* pc: Entry Point */
-	*(--stk) = (rt_uint32_t) 0xeeee; 		/* c0_cause */
-	*(--stk) = (rt_uint32_t) 0xffff;		/* c0_badvaddr */
-	*(--stk) = (rt_uint32_t) cp0_get_lo();	/* lo */
-	*(--stk) = (rt_uint32_t) cp0_get_hi();	/* hi */
-	*(--stk) = (rt_uint32_t) g_sr; 			/* C0_SR: HW2 = En, IE = En */
-	*(--stk) = (rt_uint32_t) texit;	        /* ra */
-	*(--stk) = (rt_uint32_t) 0x0000001e;	/* s8 */
-	*(--stk) = (rt_uint32_t) stack_addr;	/* sp */
-	*(--stk) = (rt_uint32_t) g_gp;	        /* gp */
-	*(--stk) = (rt_uint32_t) 0x0000001b;	/* k1 */
-	*(--stk) = (rt_uint32_t) 0x0000001a;	/* k0 */
-	*(--stk) = (rt_uint32_t) 0x00000019;	/* t9 */
-	*(--stk) = (rt_uint32_t) 0x00000018;	/* t8 */
-	*(--stk) = (rt_uint32_t) 0x00000017;	/* s7 */
-	*(--stk) = (rt_uint32_t) 0x00000016;	/* s6 */
-	*(--stk) = (rt_uint32_t) 0x00000015;	/* s5 */
-	*(--stk) = (rt_uint32_t) 0x00000014;	/* s4 */
-	*(--stk) = (rt_uint32_t) 0x00000013;	/* s3 */
-	*(--stk) = (rt_uint32_t) 0x00000012;	/* s2 */
-	*(--stk) = (rt_uint32_t) 0x00000011;	/* s1 */
-	*(--stk) = (rt_uint32_t) 0x00000010;	/* s0 */
-	*(--stk) = (rt_uint32_t) 0x0000000f;	/* t7 */
-	*(--stk) = (rt_uint32_t) 0x0000000e;	/* t6 */
-	*(--stk) = (rt_uint32_t) 0x0000000d;	/* t5 */
-	*(--stk) = (rt_uint32_t) 0x0000000c;	/* t4 */
-	*(--stk) = (rt_uint32_t) 0x0000000b;	/* t3 */
-	*(--stk) = (rt_uint32_t) 0x0000000a; 	/* t2 */
-	*(--stk) = (rt_uint32_t) 0x00000009;	/* t1 */
-	*(--stk) = (rt_uint32_t) 0x00000008;	/* t0 */
-	*(--stk) = (rt_uint32_t) 0x00000007;	/* a3 */
-	*(--stk) = (rt_uint32_t) 0x00000006;	/* a2 */
-	*(--stk) = (rt_uint32_t) 0x00000005;	/* a1 */
-	*(--stk) = (rt_uint32_t) parameter;	    /* a0 */
-	*(--stk) = (rt_uint32_t) 0x00000003;	/* v1 */
-	*(--stk) = (rt_uint32_t) 0x00000002;	/* v0 */
-	*(--stk) = (rt_uint32_t) 0x00000001;	/* at */
-	*(--stk) = (rt_uint32_t) 0x00000000;	/* zero */
-
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
-}
-
-#define cache_op(op,addr)                       \
-	    __asm__ __volatile__(                       \
-				    "   .set    push                    \n" \
-				    "   .set    noreorder               \n" \
-				    "   .set    mips3\n\t               \n" \
-				    "   cache   %0, %1                  \n" \
-				    "   .set    pop                 \n" \
-				    :                               \
-				    : "i" (op), "R" (*(unsigned char *)(addr)))
-
-#if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I    0x00
-#else
-#define Hit_Invalidate_I    0x10
-#endif
-#define Hit_Invalidate_D    0x11
-#define CONFIG_SYS_CACHELINE_SIZE   32
-#define Hit_Writeback_Inv_D 0x15
-
-
-void flush_cache(unsigned long start_addr, unsigned long size)
-{
-	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
-	unsigned long addr = start_addr & ~(lsize - 1); 
-	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); 
-
-	while (1) {
-		cache_op(Hit_Writeback_Inv_D, addr);
-		cache_op(Hit_Invalidate_I, addr);
-		if (addr == aend)
-			break;
-		addr += lsize;
-	}   
-}
-
-
-/*@}*/
-

libcpu/mips/loongson_1c/exception.c

@@ -1,91 +0,0 @@
-/*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- */
-#include <rtthread.h>
-#include <rthw.h>
-#include "../common/exception.h"
-#include "../common/mipsregs.h"
-
-/**
- * @addtogroup Loongson
- */
-
-/*@{*/
-
-/**
- * exception handle table
- */
-#define RT_EXCEPTION_MAX	8
-exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
-
-/**
- * setup the exception handle
- */
-exception_func_t rt_set_except_vector(int n, exception_func_t func)
-{
-    exception_func_t old_handler = sys_exception_handlers[n];
-
-    if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
-    {
-        return 0;
-    }
-
-    sys_exception_handlers[n] = func;
-
-    return old_handler;
-}
-
-void tlb_refill_handler(void)
-{
-	rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-void cache_error_handler(void)
-{
-	rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-static void unhandled_exception_handle(pt_regs_t *regs)
-{
-	rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
-}
-
-void install_default_execpt_handle(void)
-{
-	rt_int32_t i;
-
-	for (i=0; i<RT_EXCEPTION_MAX; i++)
-		sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
-}
-
-void exception_handler(pt_regs_t *regs)
-{
-	rt_uint32_t cause;
-	rt_uint32_t index;
-
-	cause = (read_c0_cause() & read_c0_config());
-	cause = (cause & 0xfc00) >> 8;
-
-	for (index = RT_EXCEPTION_MAX; index > 0; index --)
-	{
-		if (cause & (1 << index))
-		{
-			sys_exception_handlers[index](regs);
-			cause &= ~(1 << index);
-		}
-	}
-}
-
-/*@}*/

libcpu/mips/loongson_1c/interrupt.c

@@ -1,226 +0,0 @@
-/*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date                  Author       Notes
- * 2010-10-15     Bernard      first version
- * 2010-10-15     lgnq           modified for LS1B
- * 2013-03-29     aozima       Modify the interrupt interface implementations.
- * 2015-07-06     chinesebear modified for loongson 1c
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include "ls1c.h"
-#include "ls1c_public.h"
-
-
-#define MAX_INTR            (LS1C_NR_IRQS)
-
-extern rt_uint32_t rt_interrupt_nest;
-rt_uint32_t rt_interrupt_from_thread;
-rt_uint32_t rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-static struct rt_irq_desc irq_handle_table[MAX_INTR];
-void rt_interrupt_dispatch(void *ptreg);
-void rt_hw_timer_handler();
-
-static struct ls1c_intc_regs volatile *ls1c_hw0_icregs
-= (struct ls1c_intc_regs volatile *)(LS1C_INTREG_BASE);
-
-/**
- * @addtogroup Loongson LS1B
- */
-
-/*@{*/
-
-static void rt_hw_interrupt_handler(int vector, void *param)
-{
-    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
-    rt_int32_t idx;
-    rt_int32_t i;
-    rt_uint32_t c0_status = 0;
-
-    // 设置协处理器0的状态寄存器SR的IM7-2，允许中断
-    c0_status = read_c0_status();
-    c0_status |= 0xFC00;
-    write_c0_status(c0_status);
-
-    // 龙芯1c的中断分为五组
-    for (i=0; i<5; i++)
-    {
-        /* disable */
-        (ls1c_hw0_icregs+i)->int_en = 0x0;
-        /* pci active low */
-        (ls1c_hw0_icregs+i)->int_pol = -1;	   //must be done here 20110802 lgnq
-        /* make all interrupts level triggered */
-        (ls1c_hw0_icregs+i)->int_edge = 0x00000000;
-        /* mask all interrupts */
-        (ls1c_hw0_icregs+i)->int_clr = 0xffffffff;
-    }
-
-    rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
-    for (idx = 0; idx < MAX_INTR; idx ++)
-    {
-        irq_handle_table[idx].handler = rt_hw_interrupt_handler;
-    }
-
-    /* init interrupt nest, and context in thread sp */
-    rt_interrupt_nest = 0;
-    rt_interrupt_from_thread = 0;
-    rt_interrupt_to_thread = 0;
-    rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
-    /* mask interrupt */
-    (ls1c_hw0_icregs+(vector>>5))->int_en &= ~(1 << (vector&0x1f));
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
-    (ls1c_hw0_icregs+(vector>>5))->int_en |= (1 << (vector&0x1f));
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-                                         void *param, const char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if (vector >= 0 && vector < MAX_INTR)
-    {
-        old_handler = irq_handle_table[vector].handler;
-
-#ifdef RT_USING_INTERRUPT_INFO
-        rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-        irq_handle_table[vector].handler = handler;
-        irq_handle_table[vector].param = param;
-    }
-
-    return old_handler;
-}
-
-
-/**
- * 执行中断处理函数
- * @IRQn 中断号
- */
-void ls1c_do_IRQ(int IRQn)
-{
-    rt_isr_handler_t irq_func;
-    void *param;
-
-    // 找到中断处理函数
-    irq_func = irq_handle_table[IRQn].handler;
-    param    = irq_handle_table[IRQn].param;
-
-    // 执行中断处理函数
-    irq_func(IRQn, param);
-    
-#ifdef RT_USING_INTERRUPT_INFO
-    irq_handle_table[IRQn].counter++;
-#endif
-
-    return ;
-}
-
-
-void ls1c_irq_dispatch(int n)
-{
-    rt_uint32_t intstatus, irq;
-
-    /* Receive interrupt signal, compute the irq */
-    intstatus = (ls1c_hw0_icregs+n)->int_isr & (ls1c_hw0_icregs+n)->int_en;
-    if (0 == intstatus)
-        return ;
-
-    // 执行中断处理函数
-    irq = ls1c_ffs(intstatus) - 1;
-    ls1c_do_IRQ((n<<5) + irq);
-
-    /* ack interrupt */
-    (ls1c_hw0_icregs+n)->int_clr |= (1 << irq);
-
-    return ;
-}
-
-
-void rt_interrupt_dispatch(void *ptreg)
-{
-    int irq;
-    void *param;
-    rt_isr_handler_t irq_func;
-    static rt_uint32_t status = 0;
-    rt_uint32_t c0_status;
-    rt_uint32_t c0_cause;
-    volatile rt_uint32_t cause_im;
-    volatile rt_uint32_t status_im;
-    rt_uint32_t pending_im;
-
-    /* check os timer */
-    c0_status = read_c0_status();
-    c0_cause = read_c0_cause();
-
-    cause_im = c0_cause & ST0_IM;
-    status_im = c0_status & ST0_IM;
-    pending_im = cause_im & status_im;
-
-    if (pending_im & CAUSEF_IP7)
-    {
-        rt_hw_timer_handler();
-    }
-    else if (pending_im & CAUSEF_IP2)
-    {
-        ls1c_irq_dispatch(0);
-    }
-    else if (pending_im & CAUSEF_IP3)
-    {
-        ls1c_irq_dispatch(1);
-    }
-    else if (pending_im & CAUSEF_IP4)
-    {
-        ls1c_irq_dispatch(2);
-    }
-    else if (pending_im & CAUSEF_IP5)
-    {
-        ls1c_irq_dispatch(3);
-    }
-    else if (pending_im & CAUSEF_IP6)
-    {
-        ls1c_irq_dispatch(4);
-    }
-}
-
-/*@}*/
-
-

libcpu/mips/loongson_1c/ls1c.h

@@ -1,155 +0,0 @@
-/*
- * File      : ls1c.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date               Author             Notes
- * 2011-08-08     lgnq                first version
- * 2015-07-06     chinesebear      modified for loongson 1c
- */
-
-#ifndef __LS1C_H__
-#define __LS1C_H__
-
-#include "../common/mipsregs.h"
-
-#define LS1C_ACPI_IRQ    0
-#define LS1C_HPET_IRQ    1
-//#define LS1C_UART0_IRQ    3  // linux中是3，v1.4版本的1c手册中是2，暂屏蔽，待确认
-#define LS1C_UART1_IRQ   4
-#define LS1C_UART2_IRQ   5
-#define LS1C_CAN0_IRQ    6
-#define LS1C_CAN1_IRQ    7
-#define LS1C_SPI0_IRQ    8
-#define LS1C_SPI1_IRQ    9
-#define LS1C_AC97_IRQ    10
-#define LS1C_MS_IRQ      11
-#define LS1C_KB_IRQ      12
-#define LS1C_DMA0_IRQ    13
-#define LS1C_DMA1_IRQ    14
-#define LS1C_DMA2_IRQ    15
-#define LS1C_NAND_IRQ    16
-#define LS1C_PWM0_IRQ    17
-#define LS1C_PWM1_IRQ    18
-#define LS1C_PWM2_IRQ    19
-#define LS1C_PWM3_IRQ    20
-#define LS1C_RTC_INT0_IRQ  21
-#define LS1C_RTC_INT1_IRQ  22
-#define LS1C_RTC_INT2_IRQ  23
-#define LS1C_UART3_IRQ   29
-#define LS1C_ADC_IRQ     30
-#define LS1C_SDIO_IRQ    31
-
-
-#define LS1C_EHCI_IRQ   (32+0)
-#define LS1C_OHCI_IRQ   (32+1)
-#define LS1C_OTG_IRQ    (32+2)
-#define LS1C_MAC_IRQ    (32+3)
-#define LS1C_CAM_IRQ    (32+4)
-#define LS1C_UART4_IRQ  (32+5)
-#define LS1C_UART5_IRQ  (32+6)
-#define LS1C_UART6_IRQ  (32+7)
-#define LS1C_UART7_IRQ  (32+8)
-#define LS1C_UART8_IRQ  (32+9)
-#define LS1C_UART9_IRQ  (32+13)
-#define LS1C_UART10_IRQ (32+14)
-#define LS1C_UART11_IRQ (32+15)
-#define LS1C_I2C2_IRQ   (32+17)
-#define LS1C_I2C1_IRQ   (32+18)
-#define LS1C_I2C0_IRQ   (32+19)
-
-
-#define LS1C_GPIO_IRQ       64
-#define LS1C_GPIO_FIRST_IRQ 64
-#define LS1C_GPIO_IRQ_COUNT 96
-#define LS1C_GPIO_LAST_IRQ  (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1)
-
-
-#define LS1C_LAST_IRQ 159
-#define LS1C_INTREG_BASE 0xbfd01040
-
-// 龙芯1c的中断分为五组，每组32个
-#define LS1C_NR_IRQS    (32*5)
-
-
-// GPIO编号和中断号之间的互相转换
-#define LS1C_GPIO_TO_IRQ(GPIOn)     (LS1C_GPIO_FIRST_IRQ + (GPIOn))
-#define LS1C_IRQ_TO_GPIO(IRQn)      ((IRQn) - LS1C_GPIO_FIRST_IRQ)
-
-
-struct ls1c_intc_regs
-{
-    volatile unsigned int int_isr;
-    volatile unsigned int int_en;
-    volatile unsigned int int_set;
-    volatile unsigned int int_clr;        /* offset 0x10*/
-    volatile unsigned int int_pol;
-    volatile unsigned int int_edge;        /* offset 0 */
-}; 
-
-struct ls1c_cop_global_regs
-{
-    volatile unsigned int control;
-    volatile unsigned int rd_inten;
-    volatile unsigned int wr_inten;
-    volatile unsigned int rd_intisr;        /* offset 0x10*/
-    volatile unsigned int wr_intisr;
-    unsigned int unused[11];
-} ; 
-
-struct ls1c_cop_channel_regs
-{
-    volatile unsigned int rd_control;
-    volatile unsigned int rd_src;
-    volatile unsigned int rd_cnt;
-    volatile unsigned int rd_status;        /* offset 0x10*/
-    volatile unsigned int wr_control;
-    volatile unsigned int wr_src;
-    volatile unsigned int wr_cnt;
-    volatile unsigned int wr_status;        /* offset 0x10*/
-} ; 
-
-struct ls1c_cop_regs
-{
-    struct ls1c_cop_global_regs global;
-    struct ls1c_cop_channel_regs chan[8][2];
-} ;
-
-#define __REG8(addr)        *((volatile unsigned char *)(addr))
-#define __REG16(addr)       *((volatile unsigned short *)(addr))
-#define __REG32(addr)       *((volatile unsigned int *)(addr))
-
-#define GMAC0_BASE            0xBFE10000
-#define GMAC0_DMA_BASE        0xBFE11000
-#define GMAC1_BASE            0xBFE20000
-#define GMAC1_DMA_BASE        0xBFE21000
-#define I2C0_BASE             0xBFE58000
-#define PWM0_BASE             0xBFE5C000
-#define PWM1_BASE             0xBFE5C010
-#define PWM2_BASE             0xBFE5C020
-#define PWM3_BASE             0xBFE5C030
-#define WDT_BASE              0xBFE5C060
-#define RTC_BASE              0xBFE64000
-#define I2C1_BASE             0xBFE68000
-#define I2C2_BASE             0xBFE70000
-#define AC97_BASE             0xBFE74000
-#define NAND_BASE             0xBFE78000
-#define SPI_BASE              0xBFE80000
-#define CAN1_BASE             0xBF004300
-#define CAN0_BASE             0xBF004400
-
-/* Watch Dog registers */
-#define WDT_EN               __REG32(WDT_BASE + 0x00)
-#define WDT_SET              __REG32(WDT_BASE + 0x08)
-#define WDT_TIMER            __REG32(WDT_BASE + 0x04)
-
-#define PLL_FREQ             __REG32(0xbfe78030)
-#define PLL_DIV_PARAM        __REG32(0xbfe78034)
-
-#endif
-

libcpu/mips/loongson_1c/mipscfg.c

@@ -1,82 +0,0 @@
-/*
- * File      : mipscfg.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-27     swkyer       first version
- */
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-#include "../common/mipscfg.h"
-
-mips32_core_cfg_t g_mips_core =
-{
-	16,		/* icache_line_size */
-	256,	/* icache_lines_per_way */
-	4,		/* icache_ways */
-	16,		/* dcache_line_size */
-	256,	/* dcache_lines_per_way */
-	4,		/* dcache_ways */
-	16,		/* max_tlb_entries */
-};
-
-static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
-{
-	rt_uint16_t rets = 1;
-
-    while (n--)
-        rets *= b;
-
-    return rets;
-}
-
-static rt_uint16_t m_log2(rt_uint16_t b)
-{
-	rt_uint16_t rets = 0;
-
-    while (b != 1)
-    {
-        b /= 2;
-        rets++;
-    }
-
-    return rets;
-}
-
-/**
- * read core attribute
- */
-void mips32_cfg_init(void)
-{
-	rt_uint16_t val;
-	rt_uint32_t cp0_config1;
-
-	cp0_config1 = read_c0_config();
-	if (cp0_config1 & 0x80000000)
-	{
-		cp0_config1 = read_c0_config1();
-
-		val = (cp0_config1 & (7<<22))>>22;
-		g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<19))>>19;
-		g_mips_core.icache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<16))>>16;
-		g_mips_core.icache_ways = val + 1;
-
-		val = (cp0_config1 & (7<<13))>>13;
-		g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<10))>>10;
-		g_mips_core.dcache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<7))>>7;
-		g_mips_core.dcache_ways = val + 1;
-
-		val = (cp0_config1 & (0x3F<<25))>>25;
-		g_mips_core.max_tlb_entries = val + 1;
-	}
-}

libcpu/mips/loongson_1c/sdram_cfg.h

@@ -1,85 +0,0 @@
-
-#ifndef __OPENLOONGSON_SDRAM_CFG_H
-#define __OPENLOONGSON_SDRAM_CFG_H
-
-
-//#define	SD_FREQ	(6 * PLL_M) / (2 * SDRAM_PARAM_DIV_NUM)
-#define	SD_FREQ	(((APB_CLK / 4) * (PLL_MULT / CPU_DIV)) / SDRAM_PARAM_DIV_NUM)
-
- 
-/* 颗粒行数 */
-#define	ROW_1K		0x7
-#define	ROW_2K		0x0
-#define	ROW_4K		0x1
-#define	ROW_8K		0x2
-#define	ROW_16K		0x3
-/* 颗粒列数 */
-#define	COL_256		0x7
-#define	COL_512		0x0
-#define	COL_1K		0x1
-#define	COL_2K		0x2
-#define	COL_4K		0x3
-/* 颗粒位宽 */
-#define	WIDTH_8		0x0
-#define	WIDTH_16	0x1
-#define	WIDTH_32	0x2
-
-#define	TRCD		3
-#define	TCL			3
-#define	TRP			3
-#define	TRFC		8
-#define	TRAS		6
-#define	TREF		0x818
-#define	TWR			2
-
-#define	DEF_SEL		0x1
-#define	DEF_SEL_N	0x0
-#define	HANG_UP		0x1
-#define	HANG_UP_N	0x0
-#define	CFG_VALID	0x1
-
-
-#if 0
-// 白菜板8MB
-/*
-    以型号为IS42S16400的SDRAM为例，
-    物理参数为，
-    容量：8MB
-    位宽：16位
-    列宽：8位，即2的8次方，即256
-    行宽：12位，即2的12次方，即4K
-
-    所以，
-    颗粒的位宽=WIDTH_16
-    颗粒的列数=COL_256
-    颗粒的行数=ROW_4K
-
-    再结合宏SD_PARA0和芯片手册中寄存器SD_CONFIG，相信一看就能明白
-    替换宏SD_PARA0中的行宽、列宽和位宽
-*/
-#define SDRAM_WIDTH         (WIDTH_16)
-#define SDRAM_COL           (COL_256)
-#define SDRAM_ROW           (ROW_4K)
-
-#else
-
-// 智龙32MByte
-#define SDRAM_WIDTH         (WIDTH_16)
-#define SDRAM_COL           (COL_512)
-#define SDRAM_ROW           (ROW_8K)
-
-#endif
-
-#define	SD_PARA0	(0x7f<<25 | \
-					(TRAS << 21) | \
-					(TRFC << 17) | (TRP << 14) | (TCL << 11) | \
-					(TRCD << 8) | (SDRAM_WIDTH << 6) | (SDRAM_COL << 3) | \
-					SDRAM_ROW)
-
-#define	SD_PARA1	((HANG_UP_N << 8) | (DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
-
-#define	SD_PARA1_EN	((CFG_VALID << 9) | (HANG_UP_N << 8) | \
-					(DEF_SEL_N << 7) | (TWR << 5) | (TREF >> 7))
-
-
-#endif

libcpu/mips/loongson_1c/stackframe_fpu.h

@@ -1,98 +0,0 @@
-/*
- * ls1c FPU's stackframe
- * 最开始本想，将代码加入到stackframe.h中的SAVE_ALL, RESTORE_ALL和RESTORE_ALL_AND_RET中，
- * 但考虑到源文件"stackframe.h"位于目录"libcpu\mips\common"内，怕影响到其它mips cpu
- * 所以，另外新建本源文件
- */
-#ifndef __OPENLOONGSON_STACKFRAME_FPU_H
-#define __OPENLOONGSON_STACKFRAME_FPU_H
-
-
-#include "../common/asm.h"
-#include "../common/mipsregs.h"
-#include "../common/stackframe.h"
-
-
-
-#define PT_FPU_R0               (0)
-#define PT_FPU_R2               ((PT_FPU_R0) + 2*LONGSIZE)
-#define PT_FPU_R4               ((PT_FPU_R2) + 2*LONGSIZE)
-#define PT_FPU_R6               ((PT_FPU_R4) + 2*LONGSIZE)
-#define PT_FPU_R8               ((PT_FPU_R6) + 2*LONGSIZE)
-#define PT_FPU_R10              ((PT_FPU_R8) + 2*LONGSIZE)
-#define PT_FPU_R12              ((PT_FPU_R10) + 2*LONGSIZE)
-#define PT_FPU_R14              ((PT_FPU_R12) + 2*LONGSIZE)
-#define PT_FPU_R16              ((PT_FPU_R14) + 2*LONGSIZE)
-#define PT_FPU_R18              ((PT_FPU_R16) + 2*LONGSIZE)
-#define PT_FPU_R20              ((PT_FPU_R18) + 2*LONGSIZE)
-#define PT_FPU_R22              ((PT_FPU_R20) + 2*LONGSIZE)
-#define PT_FPU_R24              ((PT_FPU_R22) + 2*LONGSIZE)
-#define PT_FPU_R26              ((PT_FPU_R24) + 2*LONGSIZE)
-#define PT_FPU_R28              ((PT_FPU_R26) + 2*LONGSIZE)
-#define PT_FPU_R30              ((PT_FPU_R28) + 2*LONGSIZE)
-
-#define PT_FPU_SIZE             ((((PT_FPU_R30) + 2*LONGSIZE) + (2*PTRSIZE-1)) & ~(2*PTRSIZE-1))
-
-
-    .macro SAVE_FPU
-    .set push
-    .set noreorder
-#ifdef RT_USING_FPU
-    move k1, sp                     /* 保存现场 */
-    and k0, k1, 0xFFFFFFF8          /* 8字节对齐 */    
-    PTR_SUBU sp, k0, PT_FPU_SIZE    /* 计算栈底 */
-    s.d $f0, PT_FPU_R0(sp)
-    s.d $f2, PT_FPU_R2(sp)
-    s.d $f4, PT_FPU_R4(sp)
-    s.d $f6, PT_FPU_R6(sp)
-    s.d $f8, PT_FPU_R8(sp)
-    s.d $f10, PT_FPU_R10(sp)
-    s.d $f12, PT_FPU_R12(sp)
-    s.d $f14, PT_FPU_R14(sp)
-    s.d $f16, PT_FPU_R16(sp)
-    s.d $f18, PT_FPU_R18(sp)
-    s.d $f20, PT_FPU_R20(sp)
-    s.d $f22, PT_FPU_R22(sp)
-    s.d $f24, PT_FPU_R24(sp)
-    s.d $f26, PT_FPU_R26(sp)
-    s.d $f28, PT_FPU_R28(sp)
-    s.d $f30, PT_FPU_R30(sp)
-    move sp, k1                     /* 恢复现场 */
-#endif
-    .set reorder
-    .set pop
-    .endm
-
-
-    .macro RESTORE_FPU
-    .set push
-    .set noreorder
-#ifdef RT_USING_FPU
-    move k1, sp                     /* 保存现场 */
-    and k0, k1, 0xFFFFFFF8          /* 8字节对齐 */
-    PTR_SUBU sp, k0, PT_FPU_SIZE    /* 计算栈底*/
-    l.d $f0, PT_FPU_R0(sp)
-    l.d $f2, PT_FPU_R2(sp)
-    l.d $f4, PT_FPU_R4(sp)
-    l.d $f6, PT_FPU_R6(sp)
-    l.d $f8, PT_FPU_R8(sp)
-    l.d $f10, PT_FPU_R10(sp)
-    l.d $f12, PT_FPU_R12(sp)
-    l.d $f14, PT_FPU_R14(sp)
-    l.d $f16, PT_FPU_R16(sp)
-    l.d $f18, PT_FPU_R18(sp)
-    l.d $f20, PT_FPU_R20(sp)
-    l.d $f22, PT_FPU_R22(sp)
-    l.d $f24, PT_FPU_R24(sp)
-    l.d $f26, PT_FPU_R26(sp)
-    l.d $f28, PT_FPU_R28(sp)
-    l.d $f30, PT_FPU_R30(sp)
-    move sp, k1                     /* 恢复现场 */
-#endif
-    .set reorder
-    .set pop
-    .endm
-
-
-#endif
-

libcpu/mips/loongson_1c/start_gcc.S

@@ -1,530 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-04     bernard      porting to JZ47xx
- * 2019-07-19     Zhou Yanjie  clean up code
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mips_def.h"
-#include "../common/stackframe.h"
-#include "sdram_cfg.h"
-#include "cache.h"
-#include "rtconfig.h"
-
-#define SR_BOOT_EXC_VEC		0x00400000
-
-
-/* config pll div for cpu and sdram */
-#define PLL_MULT            (0x54)  // 晶振为24Mhz时，PLL=504Mhz
-#define SDRAM_DIV           (0)     // SDRAM为CPU的2分频
-#define CPU_DIV             (2)     // CPU为PLL的2分频
-
-	// 配置内存大小
-#define MEM_SIZE    (0x02000000)        // 32MByte
-
-	/* Delay macro */
-#define	DELAY(count)	\
-		li v0, count;	\
-	99: 		\
-		bnez	v0, 99b;\
-		addiu	v0, -1
-
-
-#define msize		s2
-#define	output_en	s3
-
-
-
-
-	.section ".start", "ax"
-	.set noreorder
-
-	/* the program entry */
-	.globl  _start
-_start:
-	.set	noreorder
-	la	ra, _start
-
-#if !defined(RT_USING_SELF_BOOT)
-
-	/* disable interrupt */
-	mfc0	t0, CP0_STATUS
-	and 	t0, 0xfffffffe	# By default it will be disabled.
-	mtc0	t0, CP0_STATUS	# Set CPU to disable interrupt.
-	nop
-
-	/* disable cache */
-	mfc0	t0, CP0_CONFIG
-	and	t0, 0xfffffff8
-	or	t0, 0x2		# disable,!default value is not it!
-	mtc0	t0, CP0_CONFIG	# Set CPU to disable cache.
-	nop
-
-	/* setup stack pointer */
-	li	sp, SYSTEM_STACK
-	la	gp, _gp
-
-	/* clear bss */
-	la	t0, __bss_start
-	la	t1, __bss_end
-_clr_bss_loop:
-	sw	zero, 0(t0)
-	bne	t0, t1, _clr_bss_loop
-	addiu	t0, t0, 4
-
-	/* jump to RT-Thread RTOS */
-	jal	rtthread_startup
-	nop
-
-	/* restart, never die */
-	j	_start
-	nop
-	
-#else
-
-	mtc0	zero, CP0_STATUS	// 清零cp0 status寄存器
-	mtc0	zero, CP0_CAUSE		// 清零cp0 cause寄存器
-
-	/*
-	设置启动异常向量入口地址为ROM地址(0xbfc00000)
-	将寄存器cp0 status的BEV置1，使CPU采用ROM(kseg1)空间的异常入口点
-	*/
-	li	t0, SR_BOOT_EXC_VEC /* Exception to Boostrap Location */
-	mtc0	t0, CP0_STATUS
-
-	/* setup stack pointer */
-	li	sp, SYSTEM_STACK
-	la	gp, _gp
-		
-	/* initialize spi */
-	li	t0, 0xbfe80000		//地址0xbfe80000为SPI0的寄存器基地址
-	li	t1, 0x17			// div 4, fast_read + burst_en + memory_en double I/O 模式 部分SPI flash可能不支持
-	sb	t1, 0x4(t0) 		// 设置寄存器sfc_param
-	li	t1, 0x05
-	sb	t1, 0x6(t0) 		// 设置寄存器sfc_timing
-
-	/* 设置sdram cs1复用关系，开发板使用ejtag_sel gpio_0引脚(第五复用)作为第二片sdram的片选
-	  注意sw2拨码开关的设置，使用ejtag烧录pmon时需要调整拨码开关，烧录完再调整回来 */
-	li	a0, 0xbfd011c0
-	lw	a1, 0x40(a0)
-	ori a1, 0x01
-	sw	a1, 0x40(a0)
-
-
-	bal locate
-	nop
-
-	/* restart, never die */
-	j	_start
-	nop
-#endif
-
-	.set	reorder
-
-	.globl  cp0_get_cause
-cp0_get_cause:
-	mfc0	v0, CP0_CAUSE
-	jr	ra
-	nop
-
-	.globl  cp0_get_status
-cp0_get_status:
-	mfc0	v0, CP0_STATUS
-	jr	ra
-	nop
-
-	.globl	cp0_get_hi
-cp0_get_hi:
-	mfhi	v0
-	jr	ra
-	nop
-
-	.globl	cp0_get_lo
-cp0_get_lo:
-	mflo	v0
-	jr	ra
-	nop
-
-#if defined(RT_USING_SELF_BOOT)
-
-/****************************************LOCATE*********************************/
-
-/*
- *  We get here from executing a bal to get the PC value of the current execute
- *  location into ra. Check to see if we run from ROM or if this is ramloaded.
- *  寄存器ra内保持着函数的返回地址，根据ra的值来判断当前是从ROM冷启动，还是从RAM热复位的
- *  ROM冷启动由通电引起，RAM热复位为各种异常引起，比如看门狗引起的复位等，
- *  也就是RAM热复位之前CPU已经开始运行了
- *  如果是从ROM冷启动，则寄存器ra的值为指令"bal	locate"所在位置加8字节，大概在0xBFC00000附近
- *  如果是从RAM热复位，则集成器ra的值为0x80xxxxxx
- */
-locate:
-//	la		s0, uncached
-//	subu	s0, ra, s0
-    /*
-     * start.s的这段汇编程序在ROM（入口点为0xBFC00000）中运行
-     * 而编译链接时指定的起始地址是0x80100000，所以需要修正一下地址
-     * s0中保存着ra与start的差值，在后续的代码中可以起到修正地址的作用
-     * 在看看文件开始的时候，对寄存器s0用途的描述是“         link versus load offset, used to relocate absolute adresses”
-     * 除了修正地址外，还通过s0的值来判断是从ROM冷启动，还是从RAM热启动
-     */
-		
-	la		s0, _start           // s0 = _start， 其中start的地址为编译链接时，指定的0x80010000
-	subu	s0, ra, s0          // s0 = ra - s0，其中ra的值在ROM入口地址0xBFC00000附近
-	and	s0, 0xffff0000          // s0 = s0 & 0xffff0000
-
-    /*
-     * 初始化cp0的status寄存器和cause寄存器
-     * 在异常引起的(从RAM)热复位后，需要重新初始化cp0的status和cause，
-     * 如果是从ROM冷启动的，那么前面已经初始化了，这里是再次重复初始化，没有影响的
-     */
-	li		t0, SR_BOOT_EXC_VEC
-	mtc0	t0, CP0_CONFIG        // 重新初始化cp0的status寄存器
-	mtc0	zero, CP0_CAUSE       // 重新清零cp0的cause寄存器
-	.set	noreorder
-    
-	li	t0, 0xbfe78030          // 地址0xbfe78030为PLL/SDRAM频率配置寄存器的地址
-	/* 设置PLL倍频 及SDRAM分频 */
-	li	t2, (0x80000008 | (PLL_MULT << 8) | (0x3 << 2) | SDRAM_DIV)
-	/* 设置CPU分频 */
-	li	t3, (0x00008003 | (CPU_DIV << 8))
-	/* 注意：首先需要把分频使能位清零 */
-	li	t1, 0x2
-	sw	t1, 0x4(t0)         // 清零CPU_DIV_VALID，即disable
-	sw	t2, 0x0(t0)         // 写寄存器START_FREQ
-	sw	t3, 0x4(t0)         // 写寄存器CLK_DIV_PARAM
-	DELAY(2000)
-
-	/* 芯片上电默认使用gpio(输入模式）但大多时候是使用模块的功能，如lcd i2c spi ac97等
-	   所以这里把gpio都关闭，方便使用模块功能。如果上电后需要gpio输出一个确定电平，
-	   如继电器、LDE等，可以修改这里的代码。*/
-	/* disable all gpio */
-	li a0,0xbfd00000
-	sw zero,0x10c0(a0)	/* disable gpio 0-31 */
-	sw zero,0x10c4(a0)	/* disable gpio 32-63 */
-	sw zero,0x10c8(a0)	/* disable gpio 64-95 */
-	sw zero,0x10cc(a0)
-
-	li t0, 0xffffffff
-	sw t0, 0x10d0(a0)
-	sw t0, 0x10d4(a0)
-	sw t0, 0x10d8(a0)
-	sw t0, 0x10dc(a0)
-
-	sw t0, 0x10f0(a0)
-	sw t0, 0x10f4(a0)
-	sw t0, 0x10f8(a0)
-	sw t0, 0x10fc(a0)
-
-
-	/* lcd soft_reset and panel config & timing */
-#ifdef DC_FB0
-/*	li a0, 0xbc301240
-	li a1, 0x00100103
-	sw a1, 0x0(a0)
-	li a1, 0x00000103
-	sw a1, 0x0(a0)		//soft_reset
-	li a1, 0x00100103
-	sw a1, 0x0(a0)
-
-	li a1, 0x80001111
-	sw a1, 0x180(a0)	//panel config
-	li a1, 0x33333333
-	sw a1, 0x1a0(a0)*/
-#endif
-
-	li output_en, 0x1
-#ifdef FAST_STARTUP
-	li a1, 0x03000000
-	sw a1, 0x10c4(a0)
-	sw a1, 0x10d4(a0)
-	lw a2, 0x10e4(a0)
-	and a2, a1
-	beq a2, a1, get_pin_val_finish
-	nop
-	li output_en, 0x1
-
-get_pin_val_finish:
-
-#endif
-
-	/* Initializing. Standby... */
-    /*
-     *  根据s0的值判断是否为ROM冷启动
-     *  如果s0不等于0，则是ROM冷启动；如果等于0，则是RAM热复位
-     *  冷启动，则需要初始化内存，cache，加载代码到内存等
-     */
-	bnez s0, 1f     // 如果寄存器s0不等于0，则说明是ROM冷启动，则跳转到下一个标号1处进行彻底初始化
-	nop
-	li a0, 128
-
-	jal rtthread_startup    // 热复位，则直接跳转到函数main
-	nop
-1:
-
-/* use only 8wins */
-#define CPU_WIN_BASE 0xbfd00000
-#define CPU_WIN_MASK 0xbfd00040
-#define CPU_WIN_MMAP 0xbfd00080
-
-#define set_cpu_window(id, base, mask, mmap) \
-        li      t0, CPU_WIN_BASE          ;  \
-        sw      $0, 0x80+id*8(t0)         ;  \
-        li      t1, base                  ;  \
-        sw      t1, 0x00+id*8(t0)         ;  \
-        sw      $0, 0x04+id*8(t0)         ;  \
-        li      t1, mask                  ;  \
-        sw      t1, 0x40+id*8(t0)         ;  \
-        sw      $0, 0x44+id*8(t0)         ;  \
-        li      t1, mmap                  ;  \
-        sw      t1, 0x80+id*8(t0)         ;  \
-        sw      $0, 0x84+id*8(t0)
-
-/* fixup cpu window */
-cpu_win_fixup:
-	//
-	// hit         = (paddr & mask) == (mmap & mask)
-	// mapped_addr =  paddr &~mask | mmap & mask
-	//
-	// mmap[7] -> enable
-	// mmap[5] -> block trans enable
-	// mmap[4] -> cachable
-	// mmap[1:0] -> destination
-	//
-	// NOTE: the address windows has priority, win0 > win1 > ... > win7
-
-/*	set_cpu_window(0, 0x1c280000, 0xfff80000, 0x1c280083) // camera 512K
-	set_cpu_window(1, 0x1c300000, 0xfff00000, 0x1c300081) // dc 1M
-	set_cpu_window(2, 0x1fe10000, 0xffffe000, 0x1fe10082) // gmac0	8K
-	set_cpu_window(3, 0x1fe10000, 0xffff0000, 0x1fe100d0) // gmac0	64K
-	set_cpu_window(4, 0x1f000000, 0xff000000, 0x1f000082) // AXIMUX   16M
-	set_cpu_window(5, 0x00000000, 0x00000000, 0x000000f0) // ddr 0
-	set_cpu_window(6, 0x00000000, 0x00000000, 0x000000f0) // ddr 0
-	set_cpu_window(7, 0x00000000, 0x00000000, 0x000000f0) // ddr 0*/
-
-/*	set_cpu_window(0, 0x1c280000, 0xfff80000, 0x1c2800d3) // camera
-//	set_cpu_window(1, 0x1fc00000, 0xfff00000, 0x1fc000f2) //
-	set_cpu_window(2, 0x1c300000, 0xfff00000, 0x1c3000d1) // dc 1M
-//	set_cpu_window(3, 0x1f000000, 0xff000000, 0x1f0000d2) //
-	set_cpu_window(4, 0x00000000, 0x00000000, 0x000000f0)
-	set_cpu_window(5, 0x00000000, 0x00000000, 0x000000f0)
-	set_cpu_window(6, 0x00000000, 0x00000000, 0x000000f0) // ddr 0
-	set_cpu_window(7, 0x00000000, 0x00000000, 0x000000f0) // ddr 0*/
-
-	// after this fixup, the kernel code should be compiled with
-	// uncached instruction fetch patch
-
-	/* 配置内存 */
-	li msize, MEM_SIZE    
-#if !defined(NAND_BOOT_EN)
-
-    /* 
-       手册建议，先写寄存器SD_CONFIG[31:0]，然后再写寄存器的SD_CONFIG[63:32]，
-       即先写低32位，再写高32位。
-       写三次寄存器，最后一次将最高位置一，即使能
-    */
-
-    // 写第一次
-	li  	t1, 0xbfd00410      // 寄存器SD_CONFIG[31:0]的地址为0xbfd00410
-	li		a1, SD_PARA0        // 宏SD_PARA0在sdram_cfg.S中定义的
-	sw		a1, 0x0(t1)         // 将宏SD_PARA0的值写入寄存器SD_CONFIG[31:0]
-	li		a1, SD_PARA1
-	sw		a1, 0x4(t1)         // 同理，将宏SD_PARA1的值写入寄存器SD_CONFIG[63:32]
-
-	// 写第二次
-	li		a1, SD_PARA0
-	sw		a1, 0x0(t1)
-	li		a1, SD_PARA1
-	sw		a1, 0x4(t1)
-
-    // 写第三次	
-	li		a1, SD_PARA0
-	sw		a1, 0x0(t1)
-	li		a1, SD_PARA1_EN     // 使能
-	sw		a1, 0x4(t1)
-//	DELAY(100)
-#endif
-
-	/**************************************CACHE*****************************/
-	
-#define CF_7_SE         (1 << 3)        /* Secondary cache enable */
-#define CF_7_SC         (1 << 31)       /* Secondary cache not present */
-#define CF_7_TE         (1 << 12)       /* Tertiary cache enable */
-#define CF_7_TC         (1 << 17)       /* Tertiary cache not present */
-#define CF_7_TS         (3 << 20)       /* Tertiary cache size */
-#define CF_7_TS_AL      20              /* Shift to align */
-#define NOP8 nop;nop;nop;nop;nop;nop;nop;nop
-	
-do_caches:
-	/* Init caches... */
-	li	s7, 0					/* no L2 cache */
-	li	s8, 0					/* no L3 cache */
-
-	bal 	cache_init			// 调用汇编函数cache_init
-	nop
-
-	mfc0   a0, CP0_CONFIG 		// 将协处理器0的config寄存器的值加载到寄存器a0
-	and    a0, a0, ~((1<<12) | 7)	// a0 = a0 & ~((1<<12) | 7)
-	or	   a0, a0, 2				// a0 |= 2
-	mtc0   a0, CP0_CONFIG 		// 将寄存器a0的值写入协处理器0的config寄存器
-
-/***********************MEMORY DEBUGGING AND COPY SELF TO RAM***********************/
-//#include "newtest.32/mydebug.S"
-bootnow:
-	/* copy program to sdram to make copy fast */
-	/* 先将执行拷贝pmon到内存任务的代码，拷贝到内存0xa0000000 */
-	
-	/* 先确定需要拷贝的代码段为标号121到标号122之间的代码
-	 * 由于链接时指定的起始地址是0x80010000，
-	 * 而目前正在ROM（SPI NOR FLASH，起始地址为0xBFC00000）运行
-	 * 所以需要用寄存器s0来修正一下地址
-	 */
-	la		t0, 121f			// 将下一个标号121所在地址，加载到寄存器t0
-	addu	t0, s0				// 使用寄存器s0修正t0中的(标号121的)地址
-	la		t1, 122f			// 将下一个标号122所在地址，加载到寄存器t1
-	addu	t1, s0				// 使用寄存器s0修正t1中的(标号122的)地址
-	
-	li		t2, 0xa0000000		// 将立即数0xa0000000（起始地址）加载到寄存器t2
-1:
-	lw		v0, (t0)			// 将寄存器t0所指的内存地址开始4字节的数据加载到寄存器v0
-	sw		v0, (t2)			// 将寄存器v0的内容保存到寄存器t2所指的内存中
-	addu	t0, 4				// 寄存器t0向后移4字节
-	addu	t2, 4				// 寄存器t2向后移4字节
-	ble t0, t1, 1b				// 如果t0 <= t1，则跳转到上一个标号1处，继续拷贝后面的4字节
-	nop
-
-	li		t0, 0xa0000000		// 将立即数0xa0000000加载到寄存器t0
-	jr		t0					// 跳转到起始地址0xa0000000处开始执行（拷贝任务）
-	nop 	
-
-121: 
-	/* Copy PMON to execute location... */
-	/* 将固件拷贝到起始地址为0xa0010000的内存空间
-	   由于kseg0(0x8000 0000 - 0x9FFF FFFF)和kseg1(0xA000 0000 - 0xBFFF FFFF)是映射到物理内存的相同区域
-	   即拷贝到0xA000 0000开始的kseg1，就相当于拷贝到0x8000 0000开始的kseg0
-	   这就是为什么链接时，指定的地址是0x8001 0000，而拷贝的目标起始地址是0xA001 0000
-	*/
-	la		a0, _start			// 加载符号start所在地址0x80010000加载到寄存器a0中
-	addu	a1, a0, s0			// 使用寄存器s0修正寄存器a0中的地址，a1=0xBFC00000
-	la		a2, __bss_start			// 加载_edata（链接脚本中的一个符号）到寄存器a2
-	or		a0, 0xa0000000		// a0 = a0 | 0xa0000000 = 0xa0010000
-	or		a2, 0xa0000000		// a2 = a2 | 0xa0000000，修正地址_edata
-	subu	t1, a2, a0			// t1 = a2 - a0，即计算从start到_edata之间的长度（字节数）
-	srl t1, t1, 2				// t1 >>= 2，即t1除以4。(和前面类似，每次拷贝4字节，所以除以4)
-								// 似乎t1计算结果没有被使用，马上就被后面的覆盖了
-
-	move	t0, a0				// t0 = a0 = 0xa0010000 (目标起始地址)
-	move	t1, a1				// t1 = a1 = 0xBFC00000 (start在ROM中的地址，源起始地址)
-	move	t2, a2				// t2 = a2 (_edata在ROM中的地址，源结束地址)
-
-	/* copy text section */
-1:	and t3, t0, 0x0000ffff		// t3 = t0 & 0x0000ffff，取低16位
-	bnez	t3, 2f				// 如果t3不等于0，则跳转到下一个标号2处继续执行，t3的计算结果似乎没被使用，就被后面的覆盖了
-	nop
-2:	lw		t3, 0(t1)			// 从源地址t1处加载4字节到寄存器t3中
-	nop
-	sw		t3, 0(t0)			// 将寄存器t3中的4字节数据保存到目标地址t0处
-	addu	t0, 4				// 目标地址t0后移4字节
-	addu	t1, 4				// 源地址t1	  后移4字节
-	bne t2, t0, 1b				// 如果t2不等于t0，则跳到上一个标号1处继续拷贝，总的来说就是判断拷贝是否结束
-	nop
-	/* copy text section done. */
-	
-	/* clear bss */
-	la	t0, __bss_start
-	la	t1, __bss_end
-_clr_bss_loop:
-	sw	zero, 0(t0)
-	bne	t0, t1, _clr_bss_loop
-	addiu	t0, t0, 4
-
-	/* disable interrupt */
-	mfc0	t0, CP0_STATUS
-	and 	t0, 0xfffffffe	# By default it will be disabled.
-	mtc0	t0, CP0_STATUS	# Set CPU to disable interrupt.
-	nop
-
-	/* disable cache */
-	mfc0	t0, CP0_CONFIG
-	and t0, 0xfffffff8
-	or	t0, 0x2 	# disable,!default value is not it!
-	mtc0	t0, CP0_CONFIG	# Set CPU to disable cache.
-	nop
-
-	/* jump to RT-Thread RTOS */
-	jal	rtthread_startup
-	nop
-
-	/* restart, never die */
-	j	_start
-	nop
-	
-
-122:
-
-stuck:
-	b	stuck
-	nop
-#endif
-
-	.extern tlb_refill_handler
-	.extern cache_error_handler
-
-	/* Exception Handler */
-
-	/* 0x0 - TLB refill handler */
-	.section .vectors.1, "ax", %progbits
-	.global tlb_refill_exception
-	.type	tlb_refill_exception,@function
-tlb_refill_exception:
-	j	tlb_refill_handler
-	nop
-	
-	/* 0x100 - Cache error handler */
-	.section .vectors.2, "ax", %progbits
-	j	cache_error_handler
-	nop
-    
-	/* 0x180 - Exception/Interrupt handler */
-	.section .vectors.3, "ax", %progbits
-	.global general_exception
-	.type	general_exception,@function
-general_exception:
-	j	_general_exception_handler
-	nop
-    
-	/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
-	.section .vectors.4, "ax", %progbits
-	.global irq_exception
-	.type	irq_exception,@function
-irq_exception:
-	j	_irq_handler
-	nop
-	
-	.section .vectors, "ax", %progbits
-	.extern mips_irq_handle
-
-	/* general exception handler */
-_general_exception_handler:
-	.set	noreorder
-	la	k0, mips_irq_handle
-	jr	k0
-	nop
-	.set	reorder
-
-	/* interrupt handler */
-_irq_handler:
-	.set	noreorder
-	la	k0, mips_irq_handle
-	jr	k0
-	nop
-	.set	reorder