remove the bsp of nrf51822

bsp/nrf51822/Libraries/CMSIS/Include/core_cm0.h

@@ -1,711 +0,0 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V4.00
- * @date     22. August 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include  /* treat file as system include file for MISRA check */
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M0
-  @{
- */
-
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
-#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
-                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
-
-#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
-
-
-#if   defined ( __CC_ARM )
-  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
-  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
-  #define __STATIC_INLINE  static __inline
-
-#elif defined ( __GNUC__ )
-  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __ICCARM__ )
-  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
-  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TMS470__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __TASKING__ )
-  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
-  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#elif defined ( __CSMC__ )
-  #define __packed
-  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
-  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
-  #define __STATIC_INLINE  static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TMS470__ )
-  #if defined __TI__VFP_SUPPORT____
-    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )		/* Cosmic */
-  #if ( __CSMC__ & 0x400)		// FPU present for parser
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-#endif
-
-#include <stdint.h>                      /* standard types definitions                      */
-#include <core_cmInstr.h>                /* Core Instruction Access                         */
-#include <core_cmFunc.h>                 /* Core Function Access                            */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0_REV
-    #define __CM0_REV               0x0000
-    #warning "__CM0_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions                */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
-    \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_CORE  Status and Control Registers
-    \brief  Core Register type definitions.
-  @{
- */
-
-/** \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
-#else
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
-#endif
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} APSR_Type;
-
-
-/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} IPSR_Type;
-
-
-/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
-#if (__CORTEX_M != 0x04)
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
-#else
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
-#endif
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} xPSR_Type;
-
-
-/** \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
-  } b;                                   /*!< Structure used for bit  access                  */
-  uint32_t w;                            /*!< Type      used for word access                  */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-    \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
-       uint32_t RESERVED0[31];
-  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
-       uint32_t RSERVED1[31];
-  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
-       uint32_t RESERVED2[31];
-  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
-       uint32_t RESERVED3[31];
-       uint32_t RESERVED4[64];
-  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SCB     System Control Block (SCB)
-    \brief      Type definitions for the System Control Block Registers
-  @{
- */
-
-/** \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
-  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
-       uint32_t RESERVED0;
-  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
-  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
-  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
-       uint32_t RESERVED1;
-  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
-  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-    \brief      Type definitions for the System Timer Registers.
-  @{
- */
-
-/** \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
-  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
-  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup  CMSIS_core_register
-    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
-                are only accessible over DAP and not via processor. Therefore
-                they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup    CMSIS_core_register
-    \defgroup   CMSIS_core_base     Core Definitions
-    \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-    \brief      Functions that manage interrupts and exceptions via the NVIC.
-    @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
-#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
-#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
-
-
-/** \brief  Enable External Interrupt
-
-    The function enables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Disable External Interrupt
-
-    The function disables a device-specific interrupt in the NVIC interrupt controller.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Get Pending Interrupt
-
-    The function reads the pending register in the NVIC and returns the pending bit
-    for the specified interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-
-    \return             0  Interrupt status is not pending.
-    \return             1  Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief  Set Pending Interrupt
-
-    The function sets the pending bit of an external interrupt.
-
-    \param [in]      IRQn  Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief  Clear Pending Interrupt
-
-    The function clears the pending bit of an external interrupt.
-
-    \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief  Set Interrupt Priority
-
-    The function sets the priority of an interrupt.
-
-    \note The priority cannot be set for every core interrupt.
-
-    \param [in]      IRQn  Interrupt number.
-    \param [in]  priority  Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if(IRQn < 0) {
-    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-  else {
-    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
-        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief  Get Interrupt Priority
-
-    The function reads the priority of an interrupt. The interrupt
-    number can be positive to specify an external (device specific)
-    interrupt, or negative to specify an internal (core) interrupt.
-
-
-    \param [in]   IRQn  Interrupt number.
-    \return             Interrupt Priority. Value is aligned automatically to the implemented
-                        priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if(IRQn < 0) {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
-  else {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
-}
-
-
-/** \brief  System Reset
-
-    The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
-  __DSB();                                                     /* Ensure all outstanding memory accesses included
-                                                                  buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                     /* Ensure completion of memory access */
-  while(1);                                                    /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-    \brief      Functions that configure the System.
-  @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief  System Tick Configuration
-
-    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
-    Counter is in free running mode to generate periodic interrupts.
-
-    \param [in]  ticks  Number of ticks between two interrupts.
-
-    \return          0  Function succeeded.
-    \return          1  Function failed.
-
-    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-    must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
-
-  SysTick->LOAD  = ticks - 1;                                  /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
-  return (0);                                                  /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */

bsp/nrf51822/Libraries/CMSIS/Include/core_cmFunc.h

@@ -1,637 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmFunc.h
- * @brief    CMSIS Cortex-M Core Function Access Header File
- * @version  V4.00
- * @date     28. August 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq();     */
-/* intrinsic void __disable_irq();    */
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief  Enable IRQ Interrupts
-
-  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief  Disable IRQ Interrupts
-
-  This function disables IRQ interrupts by setting the I-bit in the CPSR.
-  Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief  Get Control Register
-
-    This function returns the content of the Control Register.
-
-    \return               Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Control Register
-
-    This function writes the given value to the Control Register.
-
-    \param [in]    control  Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-/** \brief  Get IPSR Register
-
-    This function returns the content of the IPSR Register.
-
-    \return               IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get APSR Register
-
-    This function returns the content of the APSR Register.
-
-    \return               APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get xPSR Register
-
-    This function returns the content of the xPSR Register.
-
-    \return               xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Get Process Stack Pointer
-
-    This function returns the current value of the Process Stack Pointer (PSP).
-
-    \return               PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Process Stack Pointer
-
-    This function assigns the given value to the Process Stack Pointer (PSP).
-
-    \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
-}
-
-
-/** \brief  Get Main Stack Pointer
-
-    This function returns the current value of the Main Stack Pointer (MSP).
-
-    \return               MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t result;
-
-  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Main Stack Pointer
-
-    This function assigns the given value to the Main Stack Pointer (MSP).
-
-    \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
-}
-
-
-/** \brief  Get Priority Mask
-
-    This function returns the current state of the priority mask bit from the Priority Mask Register.
-
-    \return               Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Priority Mask
-
-    This function assigns the given value to the Priority Mask Register.
-
-    \param [in]    priMask  Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if       (__CORTEX_M >= 0x03)
-
-/** \brief  Enable FIQ
-
-    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief  Disable FIQ
-
-    This function disables FIQ interrupts by setting the F-bit in the CPSR.
-    Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief  Get Base Priority
-
-    This function returns the current value of the Base Priority register.
-
-    \return               Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Base Priority
-
-    This function assigns the given value to the Base Priority register.
-
-    \param [in]    basePri  Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief  Get Fault Mask
-
-    This function returns the current value of the Fault Mask register.
-
-    \return               Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-/** \brief  Set Fault Mask
-
-    This function assigns the given value to the Fault Mask register.
-
-    \param [in]    faultMask  Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
-
-/** \brief  Get FPSCR
-
-    This function returns the current value of the Floating Point Status/Control register.
-
-    \return               Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  uint32_t result;
-
-  /* Empty asm statement works as a scheduling barrier */
-  __ASM volatile ("");
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  __ASM volatile ("");
-  return(result);
-#else
-   return(0);
-#endif
-}
-
-
-/** \brief  Set FPSCR
-
-    This function assigns the given value to the Floating Point Status/Control register.
-
-    \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-  /* Empty asm statement works as a scheduling barrier */
-  __ASM volatile ("");
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
-  __ASM volatile ("");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-#endif /* __CORE_CMFUNC_H */

bsp/nrf51822/Libraries/CMSIS/Include/core_cmInstr.h

@@ -1,880 +0,0 @@
-/**************************************************************************//**
- * @file     core_cmInstr.h
- * @brief    CMSIS Cortex-M Core Instruction Access Header File
- * @version  V4.00
- * @date     28. August 2014
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2014 ARM LIMITED
-
-   All rights reserved.
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-   - Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   - Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in the
-     documentation and/or other materials provided with the distribution.
-   - Neither the name of ARM nor the names of its contributors may be used
-     to endorse or promote products derived from this software without
-     specific prior written permission.
-   *
-   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-   POSSIBILITY OF SUCH DAMAGE.
-   ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
-  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-#define __ISB()                           __isb(0xF)
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()                           __dsb(0xF)
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-#define __DMB()                           __dmb(0xF)
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-#define __RBIT                            __rbit
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function executes a exclusive LDR instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function executes a exclusive LDR instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function executes a exclusive LDR instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function executes a exclusive STR instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXB(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function executes a exclusive STR instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXH(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function executes a exclusive STR instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-#define __STREXW(value, ptr)              __strex(value, ptr)
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX                           __clrex
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-
-/** \brief  Rotate Right with Extend (32 bit)
-
-    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
-
-    \param [in]    value  Value to rotate
-    \return               Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
-  rrx r0, r0
-  bx lr
-}
-#endif
-
-
-/** \brief  LDRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged LDRT instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
-
-
-/** \brief  LDRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged LDRT instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
-
-
-/** \brief  LDRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged LDRT instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
-
-
-/** \brief  STRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged STRT instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRBT(value, ptr)               __strt(value, ptr)
-
-
-/** \brief  STRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged STRT instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRHT(value, ptr)               __strt(value, ptr)
-
-
-/** \brief  STRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged STRT instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-#define __STRT(value, ptr)                __strt(value, ptr)
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
- * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/** \brief  No Operation
-
-    No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
-{
-  __ASM volatile ("nop");
-}
-
-
-/** \brief  Wait For Interrupt
-
-    Wait For Interrupt is a hint instruction that suspends execution
-    until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
-{
-  __ASM volatile ("wfi");
-}
-
-
-/** \brief  Wait For Event
-
-    Wait For Event is a hint instruction that permits the processor to enter
-    a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
-{
-  __ASM volatile ("wfe");
-}
-
-
-/** \brief  Send Event
-
-    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
-{
-  __ASM volatile ("sev");
-}
-
-
-/** \brief  Instruction Synchronization Barrier
-
-    Instruction Synchronization Barrier flushes the pipeline in the processor,
-    so that all instructions following the ISB are fetched from cache or
-    memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
-{
-  __ASM volatile ("isb");
-}
-
-
-/** \brief  Data Synchronization Barrier
-
-    This function acts as a special kind of Data Memory Barrier.
-    It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
-{
-  __ASM volatile ("dsb");
-}
-
-
-/** \brief  Data Memory Barrier
-
-    This function ensures the apparent order of the explicit memory operations before
-    and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
-{
-  __ASM volatile ("dmb");
-}
-
-
-/** \brief  Reverse byte order (32 bit)
-
-    This function reverses the byte order in integer value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-  return __builtin_bswap32(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/** \brief  Reverse byte order (16 bit)
-
-    This function reverses the byte order in two unsigned short values.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/** \brief  Reverse byte order in signed short value
-
-    This function reverses the byte order in a signed short value with sign extension to integer.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-  return (short)__builtin_bswap16(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-#endif
-}
-
-
-/** \brief  Rotate Right in unsigned value (32 bit)
-
-    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
-    \param [in]    value  Value to rotate
-    \param [in]    value  Number of Bits to rotate
-    \return               Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  return (op1 >> op2) | (op1 << (32 - op2)); 
-}
-
-
-/** \brief  Breakpoint
-
-    This function causes the processor to enter Debug state.
-    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
-    \param [in]    value  is ignored by the processor.
-                   If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
-
-/** \brief  Reverse bit order of value
-
-    This function reverses the bit order of the given value.
-
-    \param [in]    value  Value to reverse
-    \return               Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  LDR Exclusive (8 bit)
-
-    This function executes a exclusive LDR instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDR Exclusive (16 bit)
-
-    This function executes a exclusive LDR instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDR Exclusive (32 bit)
-
-    This function executes a exclusive LDR instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (8 bit)
-
-    This function executes a exclusive STR instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (16 bit)
-
-    This function executes a exclusive STR instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/** \brief  STR Exclusive (32 bit)
-
-    This function executes a exclusive STR instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
-    \return          0  Function succeeded
-    \return          1  Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/** \brief  Remove the exclusive lock
-
-    This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/** \brief  Signed Saturate
-
-    This function saturates a signed value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (1..32)
-    \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Unsigned Saturate
-
-    This function saturates an unsigned value.
-
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/** \brief  Count leading zeros
-
-    This function counts the number of leading zeros of a data value.
-
-    \param [in]  value  Value to count the leading zeros
-    \return             number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  Rotate Right with Extend (32 bit)
-
-    This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
-
-    \param [in]    value  Value to rotate
-    \return               Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/** \brief  LDRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged LDRT instruction for 8 bit value.
-
-    \param [in]    ptr  Pointer to data
-    \return             value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged LDRT instruction for 16 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/** \brief  LDRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged LDRT instruction for 32 bit values.
-
-    \param [in]    ptr  Pointer to data
-    \return        value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/** \brief  STRT Unprivileged (8 bit)
-
-    This function executes a Unprivileged STRT instruction for 8 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
-{
-   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief  STRT Unprivileged (16 bit)
-
-    This function executes a Unprivileged STRT instruction for 16 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
-{
-   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
-}
-
-
-/** \brief  STRT Unprivileged (32 bit)
-
-    This function executes a Unprivileged STRT instruction for 32 bit values.
-
-    \param [in]  value  Value to store
-    \param [in]    ptr  Pointer to location
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
-{
-   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
-}
-
-#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-
-#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
-/* Cosmic specific functions */
-#include <cmsis_csm.h>
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */

bsp/nrf51822/Libraries/SConscript

@@ -1,27 +0,0 @@
-import rtconfig
-Import('RTT_ROOT')
-from building import *
-
-# get current directory
-cwd = GetCurrentDir()
-
-# The set of source files associated with this SConscript file.
-src = Split("""
-nrf51822/Source/templates/system_nrf51.c
-""")
-
-#add for Startup script 
-if rtconfig.CROSS_TOOL == 'gcc':
-     src = src + ['nrf51822/Source/templates/arm/arm_startup_nrf51.s']
-elif rtconfig.CROSS_TOOL == 'keil':
-     src = src + ['nrf51822/Source/templates/arm/arm_startup_nrf51.s']
-elif rtconfig.CROSS_TOOL == 'iar':
-     src = src + ['nrf51822/Source/templates/arm/arm_startup_nrf51.s']
-
-path = [cwd + '/CMSIS/Include',
-        cwd + '/nrf51822/Include']
-
-CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'NRF51']
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
-
-Return('group')

bsp/nrf51822/Libraries/nrf51822/Include/compiler_abstraction.h

@@ -1,255 +0,0 @@
-/*
-
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-1. Redistributions of source code must retain the above copyright notice, this
-   list of conditions and the following disclaimer.
-
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-
-3. Neither the name of Nordic Semiconductor ASA nor the names of its
-   contributors may be used to endorse or promote products derived from this
-   software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
-
-*/
-
-#ifndef _COMPILER_ABSTRACTION_H
-#define _COMPILER_ABSTRACTION_H
-
-/*lint ++flb "Enter library region" */
-
-#ifndef NRF_STRING_CONCATENATE_IMPL
-    #define NRF_STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs
-#endif
-#ifndef NRF_STRING_CONCATENATE
-    #define NRF_STRING_CONCATENATE(lhs, rhs) NRF_STRING_CONCATENATE_IMPL(lhs, rhs)
-#endif
-
-#if defined ( __CC_ARM )
-
-    #ifndef __ASM
-        #define __ASM               __asm
-    #endif
-
-    #ifndef __INLINE
-        #define __INLINE            __inline
-    #endif
-
-    #ifndef __WEAK
-        #define __WEAK              __weak
-    #endif
-
-    #ifndef __ALIGN
-        #define __ALIGN(n)          __align(n)
-    #endif
-
-    #ifndef __PACKED
-        #define __PACKED            __packed
-    #endif
-
-    #ifndef __UNUSED
-        #define __UNUSED            __attribute__((unused))
-    #endif
-
-    #define GET_SP()                __current_sp()
-
-    #ifndef NRF_STATIC_ASSERT
-        #define NRF_STATIC_ASSERT(cond, msg) \
-            ;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) }
-    #endif
-    
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-
-    #ifndef __ASM
-        #define __ASM               __asm
-    #endif
-
-    #ifndef __INLINE
-        #define __INLINE            __inline
-    #endif
-
-    #ifndef __WEAK
-        #define __WEAK              __attribute__((weak))
-    #endif
-
-    #ifndef __ALIGN
-        #define __ALIGN(n)          __attribute__((aligned(n)))
-    #endif
-
-    #ifndef __PACKED
-        #define __PACKED            __attribute__((packed, aligned(1)))
-    #endif
-
-    #ifndef __UNUSED
-        #define __UNUSED            __attribute__((unused))
-    #endif
-
-    #define GET_SP()                __current_sp()
-
-    #ifndef NRF_STATIC_ASSERT
-        #ifdef __cplusplus
-            #ifndef _Static_assert
-                #define _Static_assert static_assert
-            #endif
-        #endif
-        #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg)
-    #endif
-
-#elif defined ( __ICCARM__ )
-
-    #ifndef __ASM
-        #define __ASM               __asm
-    #endif
-
-    #ifndef __INLINE
-        #define __INLINE            inline
-    #endif
-
-    #ifndef __WEAK
-        #define __WEAK              __weak
-    #endif
-
-    #if (__VER__ >= 8000000)
-        #ifndef __ALIGN
-            #define __ALIGN(n) __attribute__((aligned(x)))
-        #endif
-
-        #ifndef   __PACKED
-            #define __PACKED __attribute__((packed, aligned(1)))
-        #endif
-    #else
-        #ifndef __ALIGN
-            #define STRING_PRAGMA(x) _Pragma(#x)
-            #define __ALIGN(n) STRING_PRAGMA(data_alignment = n)
-        #endif
-
-        #ifndef   __PACKED
-            #define __PACKED __packed
-        #endif
-    #endif
-
-    #ifndef __UNUSED
-        #define __UNUSED
-    #endif
-    
-    #define GET_SP()                __get_SP()
-
-    #ifndef NRF_STATIC_ASSERT
-        #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
-    #endif
-
-#elif defined   ( __GNUC__ ) ||  defined   ( __clang__ )
-
-    #ifndef __ASM
-        #define __ASM               __asm
-    #endif
-
-    #ifndef __INLINE
-        #define __INLINE            inline
-    #endif
-
-    #ifndef __WEAK
-        #define __WEAK              __attribute__((weak))
-    #endif
-
-    #ifndef __ALIGN
-        #define __ALIGN(n)          __attribute__((aligned(n)))
-    #endif
-
-    #ifndef __PACKED
-        #define __PACKED           __attribute__((packed)) 
-    #endif
-
-    #ifndef __UNUSED
-        #define __UNUSED            __attribute__((unused))
-    #endif
-
-    #define GET_SP()                gcc_current_sp()
-
-    static inline unsigned int gcc_current_sp(void)
-    {
-        unsigned int stack_pointer = 0;
-        __asm__ __volatile__ ("mov %0, sp" : "=r"(stack_pointer));
-        return stack_pointer;
-    }
-
-    #ifndef NRF_STATIC_ASSERT
-        #ifdef __cplusplus
-            #ifndef _Static_assert
-                #define _Static_assert static_assert
-            #endif
-        #endif
-        #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg)
-    #endif
-
-#elif defined   ( __TASKING__ )
-
-    #ifndef __ASM
-        #define __ASM               __asm
-    #endif
-
-    #ifndef __INLINE
-        #define __INLINE            inline
-    #endif
-
-    #ifndef __WEAK
-        #define __WEAK              __attribute__((weak))
-    #endif
-
-    #ifndef __ALIGN
-        #define __ALIGN(n)          __align(n)
-    #endif
-    
-    /* Not defined for TASKING. */
-    #ifndef __PACKED
-        #define __PACKED
-    #endif
-
-    #ifndef __UNUSED
-        #define __UNUSED            __attribute__((unused))
-    #endif
-
-    #define GET_SP()                __get_MSP()
-
-    #ifndef NRF_STATIC_ASSERT
-        #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
-    #endif
-
-#endif
-
-#define NRF_MDK_VERSION_ASSERT_AT_LEAST(major, minor, micro) \
-    NRF_STATIC_ASSERT( \
-        ( \
-            (major < MDK_MAJOR_VERSION) || \
-            (major == MDK_MAJOR_VERSION && minor < MDK_MINOR_VERSION) || \
-            (major == MDK_MAJOR_VERSION && minor == MDK_MINOR_VERSION && micro < MDK_MICRO_VERSION) \
-        ), "MDK version mismatch.")
-
-#define NRF_MDK_VERSION_ASSERT_EXACT(major, minor, micro) \
-    NRF_STATIC_ASSERT( \
-        ( \
-            (major != MDK_MAJOR_VERSION) || \
-            (major != MDK_MAJOR_VERSION) || \
-            (major != MDK_MAJOR_VERSION) \
-        ), "MDK version mismatch.")
-
-/*lint --flb "Leave library region" */
-
-#endif

bsp/nrf51822/Libraries/nrf51822/Include/nrf.h

@@ -1,189 +0,0 @@
-/*
-
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-1. Redistributions of source code must retain the above copyright notice, this
-   list of conditions and the following disclaimer.
-
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-
-3. Neither the name of Nordic Semiconductor ASA nor the names of its
-   contributors may be used to endorse or promote products derived from this
-   software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
-
-*/
-
-#ifndef NRF_H
-#define NRF_H
-
-/* MDK version */
-#define MDK_MAJOR_VERSION   8 
-#define MDK_MINOR_VERSION   38 
-#define MDK_MICRO_VERSION   0 
-
-   
-/* Define coprocessor domains */
-#if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK)
-    #ifndef NRF5340_XXAA
-        #define NRF5340_XXAA
-    #endif
-#endif
-#if defined (NRF5340_XXAA_APPLICATION)
-    #ifndef NRF_APPLICATION
-        #define NRF_APPLICATION
-    #endif
-#endif
-#if defined (NRF5340_XXAA_NETWORK)
-    #ifndef NRF_NETWORK
-        #define NRF_NETWORK
-    #endif
-#endif
-
-/* Apply compatibility macros for old nRF5340 macros */
-#if defined(NRF5340_XXAA)
-    #if defined (NRF_APPLICATION)
-        #ifndef NRF5340_XXAA_APPLICATION
-            #define NRF5340_XXAA_APPLICATION
-        #endif
-    #endif
-    #if defined (NRF_NETWORK)
-        #ifndef NRF5340_XXAA_NETWORK
-            #define NRF5340_XXAA_NETWORK
-        #endif
-    #endif
-#endif
-
-/* Define NRF51_SERIES for common use in nRF51 series devices. Only if not previously defined. */
-#if defined (NRF51) ||\
-    defined (NRF51422_XXAA) ||\
-    defined (NRF51422_XXAB) ||\
-    defined (NRF51422_XXAC) ||\
-    defined (NRF51801_XXAB) ||\
-    defined (NRF51802_XXAA) ||\
-    defined (NRF51822_XXAA) ||\
-    defined (NRF51822_XXAB) ||\
-    defined (NRF51822_XXAC) ||\
-    defined (NRF51824_XXAA)
-    #ifndef NRF51_SERIES
-        #define NRF51_SERIES
-    #endif
-    #ifndef NRF51
-        #define NRF51
-    #endif
-#endif
-
-/* Redefine "old" too-generic name NRF52 to NRF52832_XXAA to keep backwards compatibility. */
-#if defined (NRF52)
-    #ifndef NRF52832_XXAA
-        #define NRF52832_XXAA
-    #endif
-#endif
-
-/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */
-#if defined (NRF52805_XXAA) || defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52820_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52833_XXAA) || defined (NRF52840_XXAA)
-    #ifndef NRF52_SERIES
-        #define NRF52_SERIES
-    #endif
-#endif
-
-/* Define NRF53_SERIES for common use in nRF53 series devices. */
-#if defined (NRF5340_XXAA)
-    #ifndef NRF53_SERIES
-        #define NRF53_SERIES
-    #endif
-#endif
-
-/* Define NRF91_SERIES for common use in nRF91 series devices. */
-#if defined (NRF9160_XXAA)
-    #ifndef NRF91_SERIES    
-        #define NRF91_SERIES
-    #endif
-#endif
-
-/* Device selection for device includes. */
-#if defined (NRF51)
-    #include "nrf51.h"
-    #include "nrf51_bitfields.h"
-    #include "nrf51_deprecated.h"
-
-#elif defined (NRF52805_XXAA)
-    #include "nrf52805.h"
-    #include "nrf52805_bitfields.h"
-    #include "nrf51_to_nrf52810.h"
-    #include "nrf52_to_nrf52810.h"
-    #include "nrf52810_to_nrf52811.h"
-#elif defined (NRF52810_XXAA)
-    #include "nrf52810.h"
-    #include "nrf52810_bitfields.h"
-    #include "nrf51_to_nrf52810.h"
-    #include "nrf52_to_nrf52810.h"
-    #include "nrf52810_name_change.h"
-#elif defined (NRF52811_XXAA)
-    #include "nrf52811.h"
-    #include "nrf52811_bitfields.h"
-    #include "nrf51_to_nrf52810.h"
-    #include "nrf52_to_nrf52810.h"
-    #include "nrf52810_to_nrf52811.h"
-#elif defined (NRF52820_XXAA)
-    #include "nrf52820.h"
-    #include "nrf52820_bitfields.h"
-    #include "nrf51_to_nrf52.h"
-    #include "nrf52_to_nrf52833.h"
-    #include "nrf52833_to_nrf52820.h"
-#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB)
-    #include "nrf52.h"
-    #include "nrf52_bitfields.h"
-    #include "nrf51_to_nrf52.h"
-    #include "nrf52_name_change.h"
-#elif defined (NRF52833_XXAA)
-    #include "nrf52833.h"
-    #include "nrf52833_bitfields.h"
-    #include "nrf52_to_nrf52833.h"
-    #include "nrf51_to_nrf52.h"
-#elif defined (NRF52840_XXAA)
-    #include "nrf52840.h"
-    #include "nrf52840_bitfields.h"
-    #include "nrf51_to_nrf52840.h"
-    #include "nrf52_to_nrf52840.h"
-
-#elif defined (NRF5340_XXAA)
-    #if defined(NRF_APPLICATION)
-        #include "nrf5340_application.h"
-        #include "nrf5340_application_bitfields.h"
-        #include "nrf5340_application_name_change.h"
-    #elif defined (NRF_NETWORK)
-        #include "nrf5340_network.h"
-        #include "nrf5340_network_bitfields.h"
-        #include "nrf5340_network_name_change.h"
-    #endif
-
-#elif defined (NRF9160_XXAA)
-    #include "nrf9160.h"
-    #include "nrf9160_bitfields.h"
-    #include "nrf9160_name_change.h"
-
-#else
-    #error "Device must be defined. See nrf.h."
-#endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */
-
-#include "compiler_abstraction.h"
-
-#endif /* NRF_H */
-

bsp/nrf51822/Libraries/nrf51822/Include/nrf51.h

@@ -1,1230 +0,0 @@
-
-/****************************************************************************************************//**
- * @file     nRF51.h
- *
- * @brief    CMSIS Cortex-M0 Peripheral Access Layer Header File for
- *           nRF51 from Nordic Semiconductor.
- *
- * @version  V522
- * @date     26. August 2014
- *
- * @note     Generated with SVDConv V2.81d 
- *           from CMSIS SVD File 'nRF51.xml' Version 522,
- *
- * @par      Copyright (c) 2013, Nordic Semiconductor ASA
- *           All rights reserved.
- *           
- *           Redistribution and use in source and binary forms, with or without
- *           modification, are permitted provided that the following conditions are met:
- *           
- *           * Redistributions of source code must retain the above copyright notice, this
- *           list of conditions and the following disclaimer.
- *           
- *           * Redistributions in binary form must reproduce the above copyright notice,
- *           this list of conditions and the following disclaimer in the documentation
- *           and/or other materials provided with the distribution.
- *           
- *           * Neither the name of Nordic Semiconductor ASA nor the names of its
- *           contributors may be used to endorse or promote products derived from
- *           this software without specific prior written permission.
- *           
- *           THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- *           AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- *           IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- *           DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- *           FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- *           DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- *           SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- *           CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- *           OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *           OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *           
- *
- *******************************************************************************************************/
-
-
-
-/** @addtogroup Nordic Semiconductor
-  * @{
-  */
-
-/** @addtogroup nRF51
-  * @{
-  */
-
-#ifndef NRF51_H
-#define NRF51_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* -------------------------  Interrupt Number Definition  ------------------------ */
-
-typedef enum {
-/* -------------------  Cortex-M0 Processor Exceptions Numbers  ------------------- */
-  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
-  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
-  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
-  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
-  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */
-  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
-  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
-/* ----------------------  nRF51 Specific Interrupt Numbers  ---------------------- */
-  POWER_CLOCK_IRQn              =   0,              /*!<   0  POWER_CLOCK                                                      */
-  RADIO_IRQn                    =   1,              /*!<   1  RADIO                                                            */
-  UART0_IRQn                    =   2,              /*!<   2  UART0                                                            */
-  SPI0_TWI0_IRQn                =   3,              /*!<   3  SPI0_TWI0                                                        */
-  SPI1_TWI1_IRQn                =   4,              /*!<   4  SPI1_TWI1                                                        */
-  GPIOTE_IRQn                   =   6,              /*!<   6  GPIOTE                                                           */
-  ADC_IRQn                      =   7,              /*!<   7  ADC                                                              */
-  TIMER0_IRQn                   =   8,              /*!<   8  TIMER0                                                           */
-  TIMER1_IRQn                   =   9,              /*!<   9  TIMER1                                                           */
-  TIMER2_IRQn                   =  10,              /*!<  10  TIMER2                                                           */
-  RTC0_IRQn                     =  11,              /*!<  11  RTC0                                                             */
-  TEMP_IRQn                     =  12,              /*!<  12  TEMP                                                             */
-  RNG_IRQn                      =  13,              /*!<  13  RNG                                                              */
-  ECB_IRQn                      =  14,              /*!<  14  ECB                                                              */
-  CCM_AAR_IRQn                  =  15,              /*!<  15  CCM_AAR                                                          */
-  WDT_IRQn                      =  16,              /*!<  16  WDT                                                              */
-  RTC1_IRQn                     =  17,              /*!<  17  RTC1                                                             */
-  QDEC_IRQn                     =  18,              /*!<  18  QDEC                                                             */
-  LPCOMP_IRQn                   =  19,              /*!<  19  LPCOMP                                                           */
-  SWI0_IRQn                     =  20,              /*!<  20  SWI0                                                             */
-  SWI1_IRQn                     =  21,              /*!<  21  SWI1                                                             */
-  SWI2_IRQn                     =  22,              /*!<  22  SWI2                                                             */
-  SWI3_IRQn                     =  23,              /*!<  23  SWI3                                                             */
-  SWI4_IRQn                     =  24,              /*!<  24  SWI4                                                             */
-  SWI5_IRQn                     =  25               /*!<  25  SWI5                                                             */
-} IRQn_Type;
-
-
-/** @addtogroup Configuration_of_CMSIS
-  * @{
-  */
-
-
-/* ================================================================================ */
-/* ================      Processor and Core Peripheral Section     ================ */
-/* ================================================================================ */
-
-/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
-#define __CM0_REV                 0x0301            /*!< Cortex-M0 Core Revision                                               */
-#define __MPU_PRESENT                  0            /*!< MPU present or not                                                    */
-#define __NVIC_PRIO_BITS               2            /*!< Number of Bits used for Priority Levels                               */
-#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
-/** @} */ /* End of group Configuration_of_CMSIS */
-
-#include "core_cm0.h"                               /*!< Cortex-M0 processor and core peripherals                              */
-#include "system_nrf51.h"                           /*!< nRF51 System                                                          */
-
-
-/* ================================================================================ */
-/* ================       Device Specific Peripheral Section       ================ */
-/* ================================================================================ */
-
-
-/** @addtogroup Device_Peripheral_Registers
-  * @{
-  */
-
-
-/* -------------------  Start of section using anonymous unions  ------------------ */
-#if defined(__CC_ARM)
-  #pragma push
-  #pragma anon_unions
-#elif defined(__ICCARM__)
-  #pragma language=extended
-#elif defined(__GNUC__)
-  /* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
-/* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
-  #pragma warning 586
-#else
-  #warning Not supported compiler type
-#endif
-
-
-typedef struct {
-  __IO uint32_t  CPU0;                              /*!< Configurable priority configuration register for CPU0.                */
-  __IO uint32_t  SPIS1;                             /*!< Configurable priority configuration register for SPIS1.               */
-  __IO uint32_t  RADIO;                             /*!< Configurable priority configuration register for RADIO.               */
-  __IO uint32_t  ECB;                               /*!< Configurable priority configuration register for ECB.                 */
-  __IO uint32_t  CCM;                               /*!< Configurable priority configuration register for CCM.                 */
-  __IO uint32_t  AAR;                               /*!< Configurable priority configuration register for AAR.                 */
-} AMLI_RAMPRI_Type;
-
-typedef struct {
-  __O  uint32_t  EN;                                /*!< Enable channel group.                                                 */
-  __O  uint32_t  DIS;                               /*!< Disable channel group.                                                */
-} PPI_TASKS_CHG_Type;
-
-typedef struct {
-  __IO uint32_t  EEP;                               /*!< Channel event end-point.                                              */
-  __IO uint32_t  TEP;                               /*!< Channel task end-point.                                               */
-} PPI_CH_Type;
-
-
-/* ================================================================================ */
-/* ================                      POWER                     ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Power Control. (POWER)
-  */
-
-typedef struct {                                    /*!< POWER Structure                                                       */
-  __I  uint32_t  RESERVED0[30];
-  __O  uint32_t  TASKS_CONSTLAT;                    /*!< Enable constant latency mode.                                         */
-  __O  uint32_t  TASKS_LOWPWR;                      /*!< Enable low power mode (variable latency).                             */
-  __I  uint32_t  RESERVED1[34];
-  __IO uint32_t  EVENTS_POFWARN;                    /*!< Power failure warning.                                                */
-  __I  uint32_t  RESERVED2[126];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[61];
-  __IO uint32_t  RESETREAS;                         /*!< Reset reason.                                                         */
-  __I  uint32_t  RESERVED4[9];
-  __I  uint32_t  RAMSTATUS;                         /*!< Ram status register.                                                  */
-  __I  uint32_t  RESERVED5[53];
-  __O  uint32_t  SYSTEMOFF;                         /*!< System off register.                                                  */
-  __I  uint32_t  RESERVED6[3];
-  __IO uint32_t  POFCON;                            /*!< Power failure configuration.                                          */
-  __I  uint32_t  RESERVED7[2];
-  __IO uint32_t  GPREGRET;                          /*!< General purpose retention register. This register is a retained
-                                                         register.                                                             */
-  __I  uint32_t  RESERVED8;
-  __IO uint32_t  RAMON;                             /*!< Ram on/off.                                                           */
-  __I  uint32_t  RESERVED9[7];
-  __IO uint32_t  RESET;                             /*!< Pin reset functionality configuration register. This register
-                                                         is a retained register.                                               */
-  __I  uint32_t  RESERVED10[3];
-  __IO uint32_t  RAMONB;                            /*!< Ram on/off.                                                           */
-  __I  uint32_t  RESERVED11[8];
-  __IO uint32_t  DCDCEN;                            /*!< DCDC converter enable configuration register.                         */
-  __I  uint32_t  RESERVED12[291];
-  __IO uint32_t  DCDCFORCE;                         /*!< DCDC power-up force register.                                         */
-} NRF_POWER_Type;
-
-
-/* ================================================================================ */
-/* ================                      CLOCK                     ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Clock control. (CLOCK)
-  */
-
-typedef struct {                                    /*!< CLOCK Structure                                                       */
-  __O  uint32_t  TASKS_HFCLKSTART;                  /*!< Start HFCLK clock source.                                             */
-  __O  uint32_t  TASKS_HFCLKSTOP;                   /*!< Stop HFCLK clock source.                                              */
-  __O  uint32_t  TASKS_LFCLKSTART;                  /*!< Start LFCLK clock source.                                             */
-  __O  uint32_t  TASKS_LFCLKSTOP;                   /*!< Stop LFCLK clock source.                                              */
-  __O  uint32_t  TASKS_CAL;                         /*!< Start calibration of LFCLK RC oscillator.                             */
-  __O  uint32_t  TASKS_CTSTART;                     /*!< Start calibration timer.                                              */
-  __O  uint32_t  TASKS_CTSTOP;                      /*!< Stop calibration timer.                                               */
-  __I  uint32_t  RESERVED0[57];
-  __IO uint32_t  EVENTS_HFCLKSTARTED;               /*!< HFCLK oscillator started.                                             */
-  __IO uint32_t  EVENTS_LFCLKSTARTED;               /*!< LFCLK oscillator started.                                             */
-  __I  uint32_t  RESERVED1;
-  __IO uint32_t  EVENTS_DONE;                       /*!< Calibration of LFCLK RC oscillator completed.                         */
-  __IO uint32_t  EVENTS_CTTO;                       /*!< Calibration timer timeout.                                            */
-  __I  uint32_t  RESERVED2[124];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[63];
-  __I  uint32_t  HFCLKRUN;                          /*!< Task HFCLKSTART trigger status.                                       */
-  __I  uint32_t  HFCLKSTAT;                         /*!< High frequency clock status.                                          */
-  __I  uint32_t  RESERVED4;
-  __I  uint32_t  LFCLKRUN;                          /*!< Task LFCLKSTART triggered status.                                     */
-  __I  uint32_t  LFCLKSTAT;                         /*!< Low frequency clock status.                                           */
-  __I  uint32_t  LFCLKSRCCOPY;                      /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
-                                                         triggered.                                                            */
-  __I  uint32_t  RESERVED5[62];
-  __IO uint32_t  LFCLKSRC;                          /*!< Clock source for the LFCLK clock.                                     */
-  __I  uint32_t  RESERVED6[7];
-  __IO uint32_t  CTIV;                              /*!< Calibration timer interval.                                           */
-  __I  uint32_t  RESERVED7[5];
-  __IO uint32_t  XTALFREQ;                          /*!< Crystal frequency.                                                    */
-} NRF_CLOCK_Type;
-
-
-/* ================================================================================ */
-/* ================                       MPU                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Memory Protection Unit. (MPU)
-  */
-
-typedef struct {                                    /*!< MPU Structure                                                         */
-  __I  uint32_t  RESERVED0[330];
-  __IO uint32_t  PERR0;                             /*!< Configuration of peripherals in mpu regions.                          */
-  __IO uint32_t  RLENR0;                            /*!< Length of RAM region 0.                                               */
-  __I  uint32_t  RESERVED1[52];
-  __IO uint32_t  PROTENSET0;                        /*!< Erase and write protection bit enable set register.                   */
-  __IO uint32_t  PROTENSET1;                        /*!< Erase and write protection bit enable set register.                   */
-  __IO uint32_t  DISABLEINDEBUG;                    /*!< Disable erase and write protection mechanism in debug mode.           */
-  __IO uint32_t  PROTBLOCKSIZE;                     /*!< Erase and write protection block size.                                */
-} NRF_MPU_Type;
-
-
-/* ================================================================================ */
-/* ================                       PU                       ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Patch unit. (PU)
-  */
-
-typedef struct {                                    /*!< PU Structure                                                          */
-  __I  uint32_t  RESERVED0[448];
-  __IO uint32_t  REPLACEADDR[8];                    /*!< Address of first instruction to replace.                              */
-  __I  uint32_t  RESERVED1[24];
-  __IO uint32_t  PATCHADDR[8];                      /*!< Relative address of patch instructions.                               */
-  __I  uint32_t  RESERVED2[24];
-  __IO uint32_t  PATCHEN;                           /*!< Patch enable register.                                                */
-  __IO uint32_t  PATCHENSET;                        /*!< Patch enable register.                                                */
-  __IO uint32_t  PATCHENCLR;                        /*!< Patch disable register.                                               */
-} NRF_PU_Type;
-
-
-/* ================================================================================ */
-/* ================                      AMLI                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief AHB Multi-Layer Interface. (AMLI)
-  */
-
-typedef struct {                                    /*!< AMLI Structure                                                        */
-  __I  uint32_t  RESERVED0[896];
-  AMLI_RAMPRI_Type RAMPRI;                          /*!< RAM configurable priority configuration structure.                    */
-} NRF_AMLI_Type;
-
-
-/* ================================================================================ */
-/* ================                      RADIO                     ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief The radio. (RADIO)
-  */
-
-typedef struct {                                    /*!< RADIO Structure                                                       */
-  __O  uint32_t  TASKS_TXEN;                        /*!< Enable radio in TX mode.                                              */
-  __O  uint32_t  TASKS_RXEN;                        /*!< Enable radio in RX mode.                                              */
-  __O  uint32_t  TASKS_START;                       /*!< Start radio.                                                          */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop radio.                                                           */
-  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable radio.                                                        */
-  __O  uint32_t  TASKS_RSSISTART;                   /*!< Start the RSSI and take one sample of the receive signal strength.    */
-  __O  uint32_t  TASKS_RSSISTOP;                    /*!< Stop the RSSI measurement.                                            */
-  __O  uint32_t  TASKS_BCSTART;                     /*!< Start the bit counter.                                                */
-  __O  uint32_t  TASKS_BCSTOP;                      /*!< Stop the bit counter.                                                 */
-  __I  uint32_t  RESERVED0[55];
-  __IO uint32_t  EVENTS_READY;                      /*!< Ready event.                                                          */
-  __IO uint32_t  EVENTS_ADDRESS;                    /*!< Address event.                                                        */
-  __IO uint32_t  EVENTS_PAYLOAD;                    /*!< Payload event.                                                        */
-  __IO uint32_t  EVENTS_END;                        /*!< End event.                                                            */
-  __IO uint32_t  EVENTS_DISABLED;                   /*!< Disable event.                                                        */
-  __IO uint32_t  EVENTS_DEVMATCH;                   /*!< A device address match occurred on the last received packet.          */
-  __IO uint32_t  EVENTS_DEVMISS;                    /*!< No device address match occurred on the last received packet.         */
-  __IO uint32_t  EVENTS_RSSIEND;                    /*!< Sampling of the receive signal strength complete. A new RSSI
-                                                         sample is ready for readout at the RSSISAMPLE register.               */
-  __I  uint32_t  RESERVED1[2];
-  __IO uint32_t  EVENTS_BCMATCH;                    /*!< Bit counter reached bit count value specified in BC register.         */
-  __I  uint32_t  RESERVED2[53];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the radio.                                              */
-  __I  uint32_t  RESERVED3[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED4[61];
-  __I  uint32_t  CRCSTATUS;                         /*!< CRC status of received packet.                                        */
-  __I  uint32_t  CD;                                /*!< Carrier detect.                                                       */
-  __I  uint32_t  RXMATCH;                           /*!< Received address.                                                     */
-  __I  uint32_t  RXCRC;                             /*!< Received CRC.                                                         */
-  __I  uint32_t  DAI;                               /*!< Device address match index.                                           */
-  __I  uint32_t  RESERVED5[60];
-  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer. Decision point: START task.                           */
-  __IO uint32_t  FREQUENCY;                         /*!< Frequency.                                                            */
-  __IO uint32_t  TXPOWER;                           /*!< Output power.                                                         */
-  __IO uint32_t  MODE;                              /*!< Data rate and modulation.                                             */
-  __IO uint32_t  PCNF0;                             /*!< Packet configuration 0.                                               */
-  __IO uint32_t  PCNF1;                             /*!< Packet configuration 1.                                               */
-  __IO uint32_t  BASE0;                             /*!< Radio base address 0. Decision point: START task.                     */
-  __IO uint32_t  BASE1;                             /*!< Radio base address 1. Decision point: START task.                     */
-  __IO uint32_t  PREFIX0;                           /*!< Prefixes bytes for logical addresses 0 to 3.                          */
-  __IO uint32_t  PREFIX1;                           /*!< Prefixes bytes for logical addresses 4 to 7.                          */
-  __IO uint32_t  TXADDRESS;                         /*!< Transmit address select.                                              */
-  __IO uint32_t  RXADDRESSES;                       /*!< Receive address select.                                               */
-  __IO uint32_t  CRCCNF;                            /*!< CRC configuration.                                                    */
-  __IO uint32_t  CRCPOLY;                           /*!< CRC polynomial.                                                       */
-  __IO uint32_t  CRCINIT;                           /*!< CRC initial value.                                                    */
-  __IO uint32_t  TEST;                              /*!< Test features enable register.                                        */
-  __IO uint32_t  TIFS;                              /*!< Inter Frame Spacing in microseconds.                                  */
-  __I  uint32_t  RSSISAMPLE;                        /*!< RSSI sample.                                                          */
-  __I  uint32_t  RESERVED6;
-  __I  uint32_t  STATE;                             /*!< Current radio state.                                                  */
-  __IO uint32_t  DATAWHITEIV;                       /*!< Data whitening initial value.                                         */
-  __I  uint32_t  RESERVED7[2];
-  __IO uint32_t  BCC;                               /*!< Bit counter compare.                                                  */
-  __I  uint32_t  RESERVED8[39];
-  __IO uint32_t  DAB[8];                            /*!< Device address base segment.                                          */
-  __IO uint32_t  DAP[8];                            /*!< Device address prefix.                                                */
-  __IO uint32_t  DACNF;                             /*!< Device address match configuration.                                   */
-  __I  uint32_t  RESERVED9[56];
-  __IO uint32_t  OVERRIDE0;                         /*!< Trim value override register 0.                                       */
-  __IO uint32_t  OVERRIDE1;                         /*!< Trim value override register 1.                                       */
-  __IO uint32_t  OVERRIDE2;                         /*!< Trim value override register 2.                                       */
-  __IO uint32_t  OVERRIDE3;                         /*!< Trim value override register 3.                                       */
-  __IO uint32_t  OVERRIDE4;                         /*!< Trim value override register 4.                                       */
-  __I  uint32_t  RESERVED10[561];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_RADIO_Type;
-
-
-/* ================================================================================ */
-/* ================                      UART                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Universal Asynchronous Receiver/Transmitter. (UART)
-  */
-
-typedef struct {                                    /*!< UART Structure                                                        */
-  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver.                                                  */
-  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver.                                                   */
-  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter.                                               */
-  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter.                                                */
-  __I  uint32_t  RESERVED0[3];
-  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend UART.                                                         */
-  __I  uint32_t  RESERVED1[56];
-  __IO uint32_t  EVENTS_CTS;                        /*!< CTS activated.                                                        */
-  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS deactivated.                                                      */
-  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD.                                                 */
-  __I  uint32_t  RESERVED2[4];
-  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD.                                                   */
-  __I  uint32_t  RESERVED3;
-  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected.                                                       */
-  __I  uint32_t  RESERVED4[7];
-  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout.                                                     */
-  __I  uint32_t  RESERVED5[46];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for UART.                                                   */
-  __I  uint32_t  RESERVED6[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED7[93];
-  __IO uint32_t  ERRORSRC;                          /*!< Error source. Write error field to 1 to clear error.                  */
-  __I  uint32_t  RESERVED8[31];
-  __IO uint32_t  ENABLE;                            /*!< Enable UART and acquire IOs.                                          */
-  __I  uint32_t  RESERVED9;
-  __IO uint32_t  PSELRTS;                           /*!< Pin select for RTS.                                                   */
-  __IO uint32_t  PSELTXD;                           /*!< Pin select for TXD.                                                   */
-  __IO uint32_t  PSELCTS;                           /*!< Pin select for CTS.                                                   */
-  __IO uint32_t  PSELRXD;                           /*!< Pin select for RXD.                                                   */
-  __I  uint32_t  RXD;                               /*!< RXD register. On read action the buffer pointer is displaced.
-                                                         Once read the character is consumed. If read when no character
-                                                          available, the UART will stop working.                               */
-  __O  uint32_t  TXD;                               /*!< TXD register.                                                         */
-  __I  uint32_t  RESERVED10;
-  __IO uint32_t  BAUDRATE;                          /*!< UART Baudrate.                                                        */
-  __I  uint32_t  RESERVED11[17];
-  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control register.           */
-  __I  uint32_t  RESERVED12[675];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_UART_Type;
-
-
-/* ================================================================================ */
-/* ================                       SPI                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief SPI master 0. (SPI)
-  */
-
-typedef struct {                                    /*!< SPI Structure                                                         */
-  __I  uint32_t  RESERVED0[66];
-  __IO uint32_t  EVENTS_READY;                      /*!< TXD byte sent and RXD byte received.                                  */
-  __I  uint32_t  RESERVED1[126];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED2[125];
-  __IO uint32_t  ENABLE;                            /*!< Enable SPI.                                                           */
-  __I  uint32_t  RESERVED3;
-  __IO uint32_t  PSELSCK;                           /*!< Pin select for SCK.                                                   */
-  __IO uint32_t  PSELMOSI;                          /*!< Pin select for MOSI.                                                  */
-  __IO uint32_t  PSELMISO;                          /*!< Pin select for MISO.                                                  */
-  __I  uint32_t  RESERVED4;
-  __I  uint32_t  RXD;                               /*!< RX data.                                                              */
-  __IO uint32_t  TXD;                               /*!< TX data.                                                              */
-  __I  uint32_t  RESERVED5;
-  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */
-  __I  uint32_t  RESERVED6[11];
-  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
-  __I  uint32_t  RESERVED7[681];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_SPI_Type;
-
-
-/* ================================================================================ */
-/* ================                       TWI                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Two-wire interface master 0. (TWI)
-  */
-
-typedef struct {                                    /*!< TWI Structure                                                         */
-  __O  uint32_t  TASKS_STARTRX;                     /*!< Start 2-Wire master receive sequence.                                 */
-  __I  uint32_t  RESERVED0;
-  __O  uint32_t  TASKS_STARTTX;                     /*!< Start 2-Wire master transmit sequence.                                */
-  __I  uint32_t  RESERVED1[2];
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop 2-Wire transaction.                                              */
-  __I  uint32_t  RESERVED2;
-  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend 2-Wire transaction.                                           */
-  __O  uint32_t  TASKS_RESUME;                      /*!< Resume 2-Wire transaction.                                            */
-  __I  uint32_t  RESERVED3[56];
-  __IO uint32_t  EVENTS_STOPPED;                    /*!< Two-wire stopped.                                                     */
-  __IO uint32_t  EVENTS_RXDREADY;                   /*!< Two-wire ready to deliver new RXD byte received.                      */
-  __I  uint32_t  RESERVED4[4];
-  __IO uint32_t  EVENTS_TXDSENT;                    /*!< Two-wire finished sending last TXD byte.                              */
-  __I  uint32_t  RESERVED5;
-  __IO uint32_t  EVENTS_ERROR;                      /*!< Two-wire error detected.                                              */
-  __I  uint32_t  RESERVED6[4];
-  __IO uint32_t  EVENTS_BB;                         /*!< Two-wire byte boundary.                                               */
-  __I  uint32_t  RESERVED7[3];
-  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< Two-wire suspended.                                                   */
-  __I  uint32_t  RESERVED8[45];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for TWI.                                                    */
-  __I  uint32_t  RESERVED9[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED10[110];
-  __IO uint32_t  ERRORSRC;                          /*!< Two-wire error source. Write error field to 1 to clear error.         */
-  __I  uint32_t  RESERVED11[14];
-  __IO uint32_t  ENABLE;                            /*!< Enable two-wire master.                                               */
-  __I  uint32_t  RESERVED12;
-  __IO uint32_t  PSELSCL;                           /*!< Pin select for SCL.                                                   */
-  __IO uint32_t  PSELSDA;                           /*!< Pin select for SDA.                                                   */
-  __I  uint32_t  RESERVED13[2];
-  __I  uint32_t  RXD;                               /*!< RX data register.                                                     */
-  __IO uint32_t  TXD;                               /*!< TX data register.                                                     */
-  __I  uint32_t  RESERVED14;
-  __IO uint32_t  FREQUENCY;                         /*!< Two-wire frequency.                                                   */
-  __I  uint32_t  RESERVED15[24];
-  __IO uint32_t  ADDRESS;                           /*!< Address used in the two-wire transfer.                                */
-  __I  uint32_t  RESERVED16[668];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_TWI_Type;
-
-
-/* ================================================================================ */
-/* ================                      SPIS                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief SPI slave 1. (SPIS)
-  */
-
-typedef struct {                                    /*!< SPIS Structure                                                        */
-  __I  uint32_t  RESERVED0[9];
-  __O  uint32_t  TASKS_ACQUIRE;                     /*!< Acquire SPI semaphore.                                                */
-  __O  uint32_t  TASKS_RELEASE;                     /*!< Release SPI semaphore.                                                */
-  __I  uint32_t  RESERVED1[54];
-  __IO uint32_t  EVENTS_END;                        /*!< Granted transaction completed.                                        */
-  __I  uint32_t  RESERVED2[8];
-  __IO uint32_t  EVENTS_ACQUIRED;                   /*!< Semaphore acquired.                                                   */
-  __I  uint32_t  RESERVED3[53];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for SPIS.                                                   */
-  __I  uint32_t  RESERVED4[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED5[61];
-  __I  uint32_t  SEMSTAT;                           /*!< Semaphore status.                                                     */
-  __I  uint32_t  RESERVED6[15];
-  __IO uint32_t  STATUS;                            /*!< Status from last transaction.                                         */
-  __I  uint32_t  RESERVED7[47];
-  __IO uint32_t  ENABLE;                            /*!< Enable SPIS.                                                          */
-  __I  uint32_t  RESERVED8;
-  __IO uint32_t  PSELSCK;                           /*!< Pin select for SCK.                                                   */
-  __IO uint32_t  PSELMISO;                          /*!< Pin select for MISO.                                                  */
-  __IO uint32_t  PSELMOSI;                          /*!< Pin select for MOSI.                                                  */
-  __IO uint32_t  PSELCSN;                           /*!< Pin select for CSN.                                                   */
-  __I  uint32_t  RESERVED9[7];
-  __IO uint32_t  RXDPTR;                            /*!< RX data pointer.                                                      */
-  __IO uint32_t  MAXRX;                             /*!< Maximum number of bytes in the receive buffer.                        */
-  __I  uint32_t  AMOUNTRX;                          /*!< Number of bytes received in last granted transaction.                 */
-  __I  uint32_t  RESERVED10;
-  __IO uint32_t  TXDPTR;                            /*!< TX data pointer.                                                      */
-  __IO uint32_t  MAXTX;                             /*!< Maximum number of bytes in the transmit buffer.                       */
-  __I  uint32_t  AMOUNTTX;                          /*!< Number of bytes transmitted in last granted transaction.              */
-  __I  uint32_t  RESERVED11;
-  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
-  __I  uint32_t  RESERVED12;
-  __IO uint32_t  DEF;                               /*!< Default character.                                                    */
-  __I  uint32_t  RESERVED13[24];
-  __IO uint32_t  ORC;                               /*!< Over-read character.                                                  */
-  __I  uint32_t  RESERVED14[654];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_SPIS_Type;
-
-
-/* ================================================================================ */
-/* ================                     GPIOTE                     ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief GPIO tasks and events. (GPIOTE)
-  */
-
-typedef struct {                                    /*!< GPIOTE Structure                                                      */
-  __O  uint32_t  TASKS_OUT[4];                      /*!< Tasks asssociated with GPIOTE channels.                               */
-  __I  uint32_t  RESERVED0[60];
-  __IO uint32_t  EVENTS_IN[4];                      /*!< Tasks asssociated with GPIOTE channels.                               */
-  __I  uint32_t  RESERVED1[27];
-  __IO uint32_t  EVENTS_PORT;                       /*!< Event generated from multiple pins.                                   */
-  __I  uint32_t  RESERVED2[97];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[129];
-  __IO uint32_t  CONFIG[4];                         /*!< Channel configuration registers.                                      */
-  __I  uint32_t  RESERVED4[695];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_GPIOTE_Type;
-
-
-/* ================================================================================ */
-/* ================                       ADC                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Analog to digital converter. (ADC)
-  */
-
-typedef struct {                                    /*!< ADC Structure                                                         */
-  __O  uint32_t  TASKS_START;                       /*!< Start an ADC conversion.                                              */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop ADC.                                                             */
-  __I  uint32_t  RESERVED0[62];
-  __IO uint32_t  EVENTS_END;                        /*!< ADC conversion complete.                                              */
-  __I  uint32_t  RESERVED1[128];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED2[61];
-  __I  uint32_t  BUSY;                              /*!< ADC busy register.                                                    */
-  __I  uint32_t  RESERVED3[63];
-  __IO uint32_t  ENABLE;                            /*!< ADC enable.                                                           */
-  __IO uint32_t  CONFIG;                            /*!< ADC configuration register.                                           */
-  __I  uint32_t  RESULT;                            /*!< Result of ADC conversion.                                             */
-  __I  uint32_t  RESERVED4[700];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_ADC_Type;
-
-
-/* ================================================================================ */
-/* ================                      TIMER                     ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Timer 0. (TIMER)
-  */
-
-typedef struct {                                    /*!< TIMER Structure                                                       */
-  __O  uint32_t  TASKS_START;                       /*!< Start Timer.                                                          */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop Timer.                                                           */
-  __O  uint32_t  TASKS_COUNT;                       /*!< Increment Timer (In counter mode).                                    */
-  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear timer.                                                          */
-  __O  uint32_t  TASKS_SHUTDOWN;                    /*!< Shutdown timer.                                                       */
-  __I  uint32_t  RESERVED0[11];
-  __O  uint32_t  TASKS_CAPTURE[4];                  /*!< Capture Timer value to CC[n] registers.                               */
-  __I  uint32_t  RESERVED1[60];
-  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Compare event on CC[n] match.                                         */
-  __I  uint32_t  RESERVED2[44];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for Timer.                                                  */
-  __I  uint32_t  RESERVED3[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED4[126];
-  __IO uint32_t  MODE;                              /*!< Timer Mode selection.                                                 */
-  __IO uint32_t  BITMODE;                           /*!< Sets timer behaviour.                                                 */
-  __I  uint32_t  RESERVED5;
-  __IO uint32_t  PRESCALER;                         /*!< 4-bit prescaler to source clock frequency (max value 9). Source
-                                                         clock frequency is divided by 2^SCALE.                                */
-  __I  uint32_t  RESERVED6[11];
-  __IO uint32_t  CC[4];                             /*!< Capture/compare registers.                                            */
-  __I  uint32_t  RESERVED7[683];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_TIMER_Type;
-
-
-/* ================================================================================ */
-/* ================                       RTC                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Real time counter 0. (RTC)
-  */
-
-typedef struct {                                    /*!< RTC Structure                                                         */
-  __O  uint32_t  TASKS_START;                       /*!< Start RTC Counter.                                                    */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop RTC Counter.                                                     */
-  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear RTC Counter.                                                    */
-  __O  uint32_t  TASKS_TRIGOVRFLW;                  /*!< Set COUNTER to 0xFFFFFFF0.                                            */
-  __I  uint32_t  RESERVED0[60];
-  __IO uint32_t  EVENTS_TICK;                       /*!< Event on COUNTER increment.                                           */
-  __IO uint32_t  EVENTS_OVRFLW;                     /*!< Event on COUNTER overflow.                                            */
-  __I  uint32_t  RESERVED1[14];
-  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Compare event on CC[n] match.                                         */
-  __I  uint32_t  RESERVED2[109];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[13];
-  __IO uint32_t  EVTEN;                             /*!< Configures event enable routing to PPI for each RTC event.            */
-  __IO uint32_t  EVTENSET;                          /*!< Enable events routing to PPI. The reading of this register gives
-                                                         the value of EVTEN.                                                   */
-  __IO uint32_t  EVTENCLR;                          /*!< Disable events routing to PPI. The reading of this register
-                                                         gives the value of EVTEN.                                             */
-  __I  uint32_t  RESERVED4[110];
-  __I  uint32_t  COUNTER;                           /*!< Current COUNTER value.                                                */
-  __IO uint32_t  PRESCALER;                         /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
-                                                         Must be written when RTC is STOPed.                                   */
-  __I  uint32_t  RESERVED5[13];
-  __IO uint32_t  CC[4];                             /*!< Capture/compare registers.                                            */
-  __I  uint32_t  RESERVED6[683];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_RTC_Type;
-
-
-/* ================================================================================ */
-/* ================                      TEMP                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Temperature Sensor. (TEMP)
-  */
-
-typedef struct {                                    /*!< TEMP Structure                                                        */
-  __O  uint32_t  TASKS_START;                       /*!< Start temperature measurement.                                        */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop temperature measurement.                                         */
-  __I  uint32_t  RESERVED0[62];
-  __IO uint32_t  EVENTS_DATARDY;                    /*!< Temperature measurement complete, data ready event.                   */
-  __I  uint32_t  RESERVED1[128];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED2[127];
-  __I  int32_t   TEMP;                              /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision.   */
-  __I  uint32_t  RESERVED3[700];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_TEMP_Type;
-
-
-/* ================================================================================ */
-/* ================                       RNG                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Random Number Generator. (RNG)
-  */
-
-typedef struct {                                    /*!< RNG Structure                                                         */
-  __O  uint32_t  TASKS_START;                       /*!< Start the random number generator.                                    */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop the random number generator.                                     */
-  __I  uint32_t  RESERVED0[62];
-  __IO uint32_t  EVENTS_VALRDY;                     /*!< New random number generated and written to VALUE register.            */
-  __I  uint32_t  RESERVED1[63];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the RNG.                                                */
-  __I  uint32_t  RESERVED2[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register                                         */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register                                       */
-  __I  uint32_t  RESERVED3[126];
-  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
-  __I  uint32_t  VALUE;                             /*!< RNG random number.                                                    */
-  __I  uint32_t  RESERVED4[700];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_RNG_Type;
-
-
-/* ================================================================================ */
-/* ================                       ECB                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief AES ECB Mode Encryption. (ECB)
-  */
-
-typedef struct {                                    /*!< ECB Structure                                                         */
-  __O  uint32_t  TASKS_STARTECB;                    /*!< Start ECB block encrypt. If a crypto operation is running, this
-                                                         will not initiate a new encryption and the ERRORECB event will
-                                                          be triggered.                                                        */
-  __O  uint32_t  TASKS_STOPECB;                     /*!< Stop current ECB encryption. If a crypto operation is running,
-                                                         this will will trigger the ERRORECB event.                            */
-  __I  uint32_t  RESERVED0[62];
-  __IO uint32_t  EVENTS_ENDECB;                     /*!< ECB block encrypt complete.                                           */
-  __IO uint32_t  EVENTS_ERRORECB;                   /*!< ECB block encrypt aborted due to a STOPECB task or due to an
-                                                         error.                                                                */
-  __I  uint32_t  RESERVED1[127];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED2[126];
-  __IO uint32_t  ECBDATAPTR;                        /*!< ECB block encrypt memory pointer.                                     */
-  __I  uint32_t  RESERVED3[701];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_ECB_Type;
-
-
-/* ================================================================================ */
-/* ================                       AAR                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Accelerated Address Resolver. (AAR)
-  */
-
-typedef struct {                                    /*!< AAR Structure                                                         */
-  __O  uint32_t  TASKS_START;                       /*!< Start resolving addresses based on IRKs specified in the IRK
-                                                         data structure.                                                       */
-  __I  uint32_t  RESERVED0;
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop resolving addresses.                                             */
-  __I  uint32_t  RESERVED1[61];
-  __IO uint32_t  EVENTS_END;                        /*!< Address resolution procedure completed.                               */
-  __IO uint32_t  EVENTS_RESOLVED;                   /*!< Address resolved.                                                     */
-  __IO uint32_t  EVENTS_NOTRESOLVED;                /*!< Address not resolved.                                                 */
-  __I  uint32_t  RESERVED2[126];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[61];
-  __I  uint32_t  STATUS;                            /*!< Resolution status.                                                    */
-  __I  uint32_t  RESERVED4[63];
-  __IO uint32_t  ENABLE;                            /*!< Enable AAR.                                                           */
-  __IO uint32_t  NIRK;                              /*!< Number of Identity root Keys in the IRK data structure.               */
-  __IO uint32_t  IRKPTR;                            /*!< Pointer to the IRK data structure.                                    */
-  __I  uint32_t  RESERVED5;
-  __IO uint32_t  ADDRPTR;                           /*!< Pointer to the resolvable address (6 bytes).                          */
-  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to a "scratch" data area used for temporary storage
-                                                         during resolution. A minimum of 3 bytes must be reserved.             */
-  __I  uint32_t  RESERVED6[697];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_AAR_Type;
-
-
-/* ================================================================================ */
-/* ================                       CCM                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief AES CCM Mode Encryption. (CCM)
-  */
-
-typedef struct {                                    /*!< CCM Structure                                                         */
-  __O  uint32_t  TASKS_KSGEN;                       /*!< Start generation of key-stream. This operation will stop by
-                                                         itself when completed.                                                */
-  __O  uint32_t  TASKS_CRYPT;                       /*!< Start encrypt/decrypt. This operation will stop by itself when
-                                                         completed.                                                            */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop encrypt/decrypt.                                                 */
-  __I  uint32_t  RESERVED0[61];
-  __IO uint32_t  EVENTS_ENDKSGEN;                   /*!< Keystream generation completed.                                       */
-  __IO uint32_t  EVENTS_ENDCRYPT;                   /*!< Encrypt/decrypt completed.                                            */
-  __IO uint32_t  EVENTS_ERROR;                      /*!< Error happened.                                                       */
-  __I  uint32_t  RESERVED1[61];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the CCM.                                                */
-  __I  uint32_t  RESERVED2[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[61];
-  __I  uint32_t  MICSTATUS;                         /*!< CCM RX MIC check result.                                              */
-  __I  uint32_t  RESERVED4[63];
-  __IO uint32_t  ENABLE;                            /*!< CCM enable.                                                           */
-  __IO uint32_t  MODE;                              /*!< Operation mode.                                                       */
-  __IO uint32_t  CNFPTR;                            /*!< Pointer to a data structure holding AES key and NONCE vector.         */
-  __IO uint32_t  INPTR;                             /*!< Pointer to the input packet.                                          */
-  __IO uint32_t  OUTPTR;                            /*!< Pointer to the output packet.                                         */
-  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to a "scratch" data area used for temporary storage
-                                                         during resolution. A minimum of 43 bytes must be reserved.            */
-  __I  uint32_t  RESERVED5[697];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_CCM_Type;
-
-
-/* ================================================================================ */
-/* ================                       WDT                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Watchdog Timer. (WDT)
-  */
-
-typedef struct {                                    /*!< WDT Structure                                                         */
-  __O  uint32_t  TASKS_START;                       /*!< Start the watchdog.                                                   */
-  __I  uint32_t  RESERVED0[63];
-  __IO uint32_t  EVENTS_TIMEOUT;                    /*!< Watchdog timeout.                                                     */
-  __I  uint32_t  RESERVED1[128];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED2[61];
-  __I  uint32_t  RUNSTATUS;                         /*!< Watchdog running status.                                              */
-  __I  uint32_t  REQSTATUS;                         /*!< Request status.                                                       */
-  __I  uint32_t  RESERVED3[63];
-  __IO uint32_t  CRV;                               /*!< Counter reload value in number of 32kiHz clock cycles.                */
-  __IO uint32_t  RREN;                              /*!< Reload request enable.                                                */
-  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
-  __I  uint32_t  RESERVED4[60];
-  __O  uint32_t  RR[8];                             /*!< Reload requests registers.                                            */
-  __I  uint32_t  RESERVED5[631];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_WDT_Type;
-
-
-/* ================================================================================ */
-/* ================                      QDEC                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Rotary decoder. (QDEC)
-  */
-
-typedef struct {                                    /*!< QDEC Structure                                                        */
-  __O  uint32_t  TASKS_START;                       /*!< Start the quadrature decoder.                                         */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop the quadrature decoder.                                          */
-  __O  uint32_t  TASKS_READCLRACC;                  /*!< Transfers the content from ACC registers to ACCREAD registers,
-                                                         and clears the ACC registers.                                         */
-  __I  uint32_t  RESERVED0[61];
-  __IO uint32_t  EVENTS_SAMPLERDY;                  /*!< A new sample is written to the sample register.                       */
-  __IO uint32_t  EVENTS_REPORTRDY;                  /*!< REPORTPER number of samples accumulated in ACC register, and
-                                                         ACC register different than zero.                                     */
-  __IO uint32_t  EVENTS_ACCOF;                      /*!< ACC or ACCDBL register overflow.                                      */
-  __I  uint32_t  RESERVED1[61];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the QDEC.                                               */
-  __I  uint32_t  RESERVED2[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[125];
-  __IO uint32_t  ENABLE;                            /*!< Enable the QDEC.                                                      */
-  __IO uint32_t  LEDPOL;                            /*!< LED output pin polarity.                                              */
-  __IO uint32_t  SAMPLEPER;                         /*!< Sample period.                                                        */
-  __I  int32_t   SAMPLE;                            /*!< Motion sample value.                                                  */
-  __IO uint32_t  REPORTPER;                         /*!< Number of samples to generate an EVENT_REPORTRDY.                     */
-  __I  int32_t   ACC;                               /*!< Accumulated valid transitions register.                               */
-  __I  int32_t   ACCREAD;                           /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
-                                                         task.                                                                 */
-  __IO uint32_t  PSELLED;                           /*!< Pin select for LED output.                                            */
-  __IO uint32_t  PSELA;                             /*!< Pin select for phase A input.                                         */
-  __IO uint32_t  PSELB;                             /*!< Pin select for phase B input.                                         */
-  __IO uint32_t  DBFEN;                             /*!< Enable debouncer input filters.                                       */
-  __I  uint32_t  RESERVED4[5];
-  __IO uint32_t  LEDPRE;                            /*!< Time LED is switched ON before the sample.                            */
-  __I  uint32_t  ACCDBL;                            /*!< Accumulated double (error) transitions register.                      */
-  __I  uint32_t  ACCDBLREAD;                        /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
-                                                         task.                                                                 */
-  __I  uint32_t  RESERVED5[684];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_QDEC_Type;
-
-
-/* ================================================================================ */
-/* ================                     LPCOMP                     ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Low power comparator. (LPCOMP)
-  */
-
-typedef struct {                                    /*!< LPCOMP Structure                                                      */
-  __O  uint32_t  TASKS_START;                       /*!< Start the comparator.                                                 */
-  __O  uint32_t  TASKS_STOP;                        /*!< Stop the comparator.                                                  */
-  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value.                                              */
-  __I  uint32_t  RESERVED0[61];
-  __IO uint32_t  EVENTS_READY;                      /*!< LPCOMP is ready and output is valid.                                  */
-  __IO uint32_t  EVENTS_DOWN;                       /*!< Input voltage crossed the threshold going down.                       */
-  __IO uint32_t  EVENTS_UP;                         /*!< Input voltage crossed the threshold going up.                         */
-  __IO uint32_t  EVENTS_CROSS;                      /*!< Input voltage crossed the threshold in any direction.                 */
-  __I  uint32_t  RESERVED1[60];
-  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the LPCOMP.                                             */
-  __I  uint32_t  RESERVED2[64];
-  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
-  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
-  __I  uint32_t  RESERVED3[61];
-  __I  uint32_t  RESULT;                            /*!< Result of last compare.                                               */
-  __I  uint32_t  RESERVED4[63];
-  __IO uint32_t  ENABLE;                            /*!< Enable the LPCOMP.                                                    */
-  __IO uint32_t  PSEL;                              /*!< Input pin select.                                                     */
-  __IO uint32_t  REFSEL;                            /*!< Reference select.                                                     */
-  __IO uint32_t  EXTREFSEL;                         /*!< External reference select.                                            */
-  __I  uint32_t  RESERVED5[4];
-  __IO uint32_t  ANADETECT;                         /*!< Analog detect configuration.                                          */
-  __I  uint32_t  RESERVED6[694];
-  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
-} NRF_LPCOMP_Type;
-
-
-/* ================================================================================ */
-/* ================                       SWI                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief SW Interrupts. (SWI)
-  */
-
-typedef struct {                                    /*!< SWI Structure                                                         */
-  __I  uint32_t  SD_UNUSED;                            /*!< Unused.                                                               */
-} NRF_SWI_Type;
-
-
-/* ================================================================================ */
-/* ================                      NVMC                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Non Volatile Memory Controller. (NVMC)
-  */
-
-typedef struct {                                    /*!< NVMC Structure                                                        */
-  __I  uint32_t  RESERVED0[256];
-  __I  uint32_t  READY;                             /*!< Ready flag.                                                           */
-  __I  uint32_t  RESERVED1[64];
-  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
-  __IO uint32_t  ERASEPAGE;                         /*!< Register for erasing a non-protected non-volatile memory page.        */
-  __IO uint32_t  ERASEALL;                          /*!< Register for erasing all non-volatile user memory.                    */
-  __IO uint32_t  ERASEPROTECTEDPAGE;                /*!< Register for erasing a protected non-volatile memory page.            */
-  __IO uint32_t  ERASEUICR;                         /*!< Register for start erasing User Information Congfiguration Registers. */
-} NRF_NVMC_Type;
-
-
-/* ================================================================================ */
-/* ================                       PPI                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief PPI controller. (PPI)
-  */
-
-typedef struct {                                    /*!< PPI Structure                                                         */
-  PPI_TASKS_CHG_Type TASKS_CHG[4];                  /*!< Channel group tasks.                                                  */
-  __I  uint32_t  RESERVED0[312];
-  __IO uint32_t  CHEN;                              /*!< Channel enable.                                                       */
-  __IO uint32_t  CHENSET;                           /*!< Channel enable set.                                                   */
-  __IO uint32_t  CHENCLR;                           /*!< Channel enable clear.                                                 */
-  __I  uint32_t  RESERVED1;
-  PPI_CH_Type CH[16];                               /*!< PPI Channel.                                                          */
-  __I  uint32_t  RESERVED2[156];
-  __IO uint32_t  CHG[4];                            /*!< Channel group configuration.                                          */
-} NRF_PPI_Type;
-
-
-/* ================================================================================ */
-/* ================                      FICR                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief Factory Information Configuration. (FICR)
-  */
-
-typedef struct {                                    /*!< FICR Structure                                                        */
-  __I  uint32_t  RESERVED0[4];
-  __I  uint32_t  CODEPAGESIZE;                      /*!< Code memory page size in bytes.                                       */
-  __I  uint32_t  CODESIZE;                          /*!< Code memory size in pages.                                            */
-  __I  uint32_t  RESERVED1[4];
-  __I  uint32_t  CLENR0;                            /*!< Length of code region 0 in bytes.                                     */
-  __I  uint32_t  PPFC;                              /*!< Pre-programmed factory code present.                                  */
-  __I  uint32_t  RESERVED2;
-  __I  uint32_t  NUMRAMBLOCK;                       /*!< Number of individualy controllable RAM blocks.                        */
-  
-  union {
-    __I  uint32_t  SIZERAMBLOCK[4];                 /*!< Deprecated array of size of RAM block in bytes. This name is
-                                                         kept for backward compatinility purposes. Use SIZERAMBLOCKS
-                                                          instead.                                                             */
-    __I  uint32_t  SIZERAMBLOCKS;                   /*!< Size of RAM blocks in bytes.                                          */
-  };
-  __I  uint32_t  RESERVED3[5];
-  __I  uint32_t  CONFIGID;                          /*!< Configuration identifier.                                             */
-  __I  uint32_t  DEVICEID[2];                       /*!< Device identifier.                                                    */
-  __I  uint32_t  RESERVED4[6];
-  __I  uint32_t  ER[4];                             /*!< Encryption root.                                                      */
-  __I  uint32_t  IR[4];                             /*!< Identity root.                                                        */
-  __I  uint32_t  DEVICEADDRTYPE;                    /*!< Device address type.                                                  */
-  __I  uint32_t  DEVICEADDR[2];                     /*!< Device address.                                                       */
-  __I  uint32_t  OVERRIDEEN;                        /*!< Radio calibration override enable.                                    */
-  __I  uint32_t  NRF_1MBIT[5];                      /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
-                                                         mode.                                                                 */
-  __I  uint32_t  RESERVED5[10];
-  __I  uint32_t  BLE_1MBIT[5];                      /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
-                                                         mode.                                                                 */
-} NRF_FICR_Type;
-
-
-/* ================================================================================ */
-/* ================                      UICR                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief User Information Configuration. (UICR)
-  */
-
-typedef struct {                                    /*!< UICR Structure                                                        */
-  __IO uint32_t  CLENR0;                            /*!< Length of code region 0.                                              */
-  __IO uint32_t  RBPCONF;                           /*!< Readback protection configuration.                                    */
-  __IO uint32_t  XTALFREQ;                          /*!< Reset value for CLOCK XTALFREQ register.                              */
-  __I  uint32_t  RESERVED0;
-  __I  uint32_t  FWID;                              /*!< Firmware ID.                                                          */
-  __IO uint32_t  BOOTLOADERADDR;                    /*!< Bootloader start address.                                             */
-} NRF_UICR_Type;
-
-
-/* ================================================================================ */
-/* ================                      GPIO                      ================ */
-/* ================================================================================ */
-
-
-/**
-  * @brief General purpose input and output. (GPIO)
-  */
-
-typedef struct {                                    /*!< GPIO Structure                                                        */
-  __I  uint32_t  RESERVED0[321];
-  __IO uint32_t  OUT;                               /*!< Write GPIO port.                                                      */
-  __IO uint32_t  OUTSET;                            /*!< Set individual bits in GPIO port.                                     */
-  __IO uint32_t  OUTCLR;                            /*!< Clear individual bits in GPIO port.                                   */
-  __I  uint32_t  IN;                                /*!< Read GPIO port.                                                       */
-  __IO uint32_t  DIR;                               /*!< Direction of GPIO pins.                                               */
-  __IO uint32_t  DIRSET;                            /*!< DIR set register.                                                     */
-  __IO uint32_t  DIRCLR;                            /*!< DIR clear register.                                                   */
-  __I  uint32_t  RESERVED1[120];
-  __IO uint32_t  PIN_CNF[32];                       /*!< Configuration of GPIO pins.                                           */
-} NRF_GPIO_Type;
-
-
-/* --------------------  End of section using anonymous unions  ------------------- */
-#if defined(__CC_ARM)
-  #pragma pop
-#elif defined(__ICCARM__)
-  /* leave anonymous unions enabled */
-#elif defined(__GNUC__)
-  /* anonymous unions are enabled by default */
-#elif defined(__TMS470__)
-  /* anonymous unions are enabled by default */
-#elif defined(__TASKING__)
-  #pragma warning restore
-#else
-  #warning Not supported compiler type
-#endif
-
-
-
-
-/* ================================================================================ */
-/* ================              Peripheral memory map             ================ */
-/* ================================================================================ */
-
-#define NRF_POWER_BASE                  0x40000000UL
-#define NRF_CLOCK_BASE                  0x40000000UL
-#define NRF_MPU_BASE                    0x40000000UL
-#define NRF_PU_BASE                     0x40000000UL
-#define NRF_AMLI_BASE                   0x40000000UL
-#define NRF_RADIO_BASE                  0x40001000UL
-#define NRF_UART0_BASE                  0x40002000UL
-#define NRF_SPI0_BASE                   0x40003000UL
-#define NRF_TWI0_BASE                   0x40003000UL
-#define NRF_SPI1_BASE                   0x40004000UL
-#define NRF_TWI1_BASE                   0x40004000UL
-#define NRF_SPIS1_BASE                  0x40004000UL
-#define NRF_GPIOTE_BASE                 0x40006000UL
-#define NRF_ADC_BASE                    0x40007000UL
-#define NRF_TIMER0_BASE                 0x40008000UL
-#define NRF_TIMER1_BASE                 0x40009000UL
-#define NRF_TIMER2_BASE                 0x4000A000UL
-#define NRF_RTC0_BASE                   0x4000B000UL
-#define NRF_TEMP_BASE                   0x4000C000UL
-#define NRF_RNG_BASE                    0x4000D000UL
-#define NRF_ECB_BASE                    0x4000E000UL
-#define NRF_AAR_BASE                    0x4000F000UL
-#define NRF_CCM_BASE                    0x4000F000UL
-#define NRF_WDT_BASE                    0x40010000UL
-#define NRF_RTC1_BASE                   0x40011000UL
-#define NRF_QDEC_BASE                   0x40012000UL
-#define NRF_LPCOMP_BASE                 0x40013000UL
-#define NRF_SWI_BASE                    0x40014000UL
-#define NRF_NVMC_BASE                   0x4001E000UL
-#define NRF_PPI_BASE                    0x4001F000UL
-#define NRF_FICR_BASE                   0x10000000UL
-#define NRF_UICR_BASE                   0x10001000UL
-#define NRF_GPIO_BASE                   0x50000000UL
-
-
-/* ================================================================================ */
-/* ================             Peripheral declaration             ================ */
-/* ================================================================================ */
-
-#define NRF_POWER                       ((NRF_POWER_Type          *) NRF_POWER_BASE)
-#define NRF_CLOCK                       ((NRF_CLOCK_Type          *) NRF_CLOCK_BASE)
-#define NRF_MPU                         ((NRF_MPU_Type            *) NRF_MPU_BASE)
-#define NRF_PU                          ((NRF_PU_Type             *) NRF_PU_BASE)
-#define NRF_AMLI                        ((NRF_AMLI_Type           *) NRF_AMLI_BASE)
-#define NRF_RADIO                       ((NRF_RADIO_Type          *) NRF_RADIO_BASE)
-#define NRF_UART0                       ((NRF_UART_Type           *) NRF_UART0_BASE)
-#define NRF_SPI0                        ((NRF_SPI_Type            *) NRF_SPI0_BASE)
-#define NRF_TWI0                        ((NRF_TWI_Type            *) NRF_TWI0_BASE)
-#define NRF_SPI1                        ((NRF_SPI_Type            *) NRF_SPI1_BASE)
-#define NRF_TWI1                        ((NRF_TWI_Type            *) NRF_TWI1_BASE)
-#define NRF_SPIS1                       ((NRF_SPIS_Type           *) NRF_SPIS1_BASE)
-#define NRF_GPIOTE                      ((NRF_GPIOTE_Type         *) NRF_GPIOTE_BASE)
-#define NRF_ADC                         ((NRF_ADC_Type            *) NRF_ADC_BASE)
-#define NRF_TIMER0                      ((NRF_TIMER_Type          *) NRF_TIMER0_BASE)
-#define NRF_TIMER1                      ((NRF_TIMER_Type          *) NRF_TIMER1_BASE)
-#define NRF_TIMER2                      ((NRF_TIMER_Type          *) NRF_TIMER2_BASE)
-#define NRF_RTC0                        ((NRF_RTC_Type            *) NRF_RTC0_BASE)
-#define NRF_TEMP                        ((NRF_TEMP_Type           *) NRF_TEMP_BASE)
-#define NRF_RNG                         ((NRF_RNG_Type            *) NRF_RNG_BASE)
-#define NRF_ECB                         ((NRF_ECB_Type            *) NRF_ECB_BASE)
-#define NRF_AAR                         ((NRF_AAR_Type            *) NRF_AAR_BASE)
-#define NRF_CCM                         ((NRF_CCM_Type            *) NRF_CCM_BASE)
-#define NRF_WDT                         ((NRF_WDT_Type            *) NRF_WDT_BASE)
-#define NRF_RTC1                        ((NRF_RTC_Type            *) NRF_RTC1_BASE)
-#define NRF_QDEC                        ((NRF_QDEC_Type           *) NRF_QDEC_BASE)
-#define NRF_LPCOMP                      ((NRF_LPCOMP_Type         *) NRF_LPCOMP_BASE)
-#define NRF_SWI                         ((NRF_SWI_Type            *) NRF_SWI_BASE)
-#define NRF_NVMC                        ((NRF_NVMC_Type           *) NRF_NVMC_BASE)
-#define NRF_PPI                         ((NRF_PPI_Type            *) NRF_PPI_BASE)
-#define NRF_FICR                        ((NRF_FICR_Type           *) NRF_FICR_BASE)
-#define NRF_UICR                        ((NRF_UICR_Type           *) NRF_UICR_BASE)
-#define NRF_GPIO                        ((NRF_GPIO_Type           *) NRF_GPIO_BASE)
-
-
-/** @} */ /* End of group Device_Peripheral_Registers */
-/** @} */ /* End of group nRF51 */
-/** @} */ /* End of group Nordic Semiconductor */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif  /* nRF51_H */
-

bsp/nrf51822/Libraries/nrf51822/Include/nrf51_bitfields.h

@@ -1,6894 +0,0 @@
-/* Copyright (c) 2013, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- *   * Redistributions of source code must retain the above copyright notice, this
- *     list of conditions and the following disclaimer.
- *
- *   * Redistributions in binary form must reproduce the above copyright notice,
- *     this list of conditions and the following disclaimer in the documentation
- *     and/or other materials provided with the distribution.
- *
- *   * Neither the name of Nordic Semiconductor ASA nor the names of its
- *     contributors may be used to endorse or promote products derived from
- *     this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-#ifndef __NRF51_BITS_H
-#define __NRF51_BITS_H
-
-/*lint ++flb "Enter library region */
-
-#include <core_cm0.h>
-
-/* Peripheral: AAR */
-/* Description: Accelerated Address Resolver. */
-
-/* Register: AAR_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
-#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
-#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
-#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on RESOLVED event. */
-#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
-#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
-#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on END event. */
-#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
-#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: AAR_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
-#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
-#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
-#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on RESOLVED event. */
-#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
-#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
-#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on ENDKSGEN event. */
-#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
-#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: AAR_STATUS */
-/* Description: Resolution status. */
-
-/* Bits 3..0 : The IRK used last time an address was resolved. */
-#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
-#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
-
-/* Register: AAR_ENABLE */
-/* Description: Enable AAR. */
-
-/* Bits 1..0 : Enable AAR. */
-#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
-#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
-
-/* Register: AAR_NIRK */
-/* Description: Number of Identity root Keys in the IRK data structure. */
-
-/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
-#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
-#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
-
-/* Register: AAR_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: ADC */
-/* Description: Analog to digital converter. */
-
-/* Register: ADC_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 0 : Enable interrupt on END event. */
-#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
-#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: ADC_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 0 : Disable interrupt on END event. */
-#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
-#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: ADC_BUSY */
-/* Description: ADC busy register. */
-
-/* Bit 0 : ADC busy register. */
-#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
-#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
-#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
-#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
-
-/* Register: ADC_ENABLE */
-/* Description: ADC enable. */
-
-/* Bits 1..0 : ADC enable. */
-#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
-#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
-
-/* Register: ADC_CONFIG */
-/* Description: ADC configuration register. */
-
-/* Bits 17..16 : ADC external reference pin selection. */
-#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
-#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
-#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
-#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
-#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
-
-/* Bits 15..8 : ADC analog pin selection. */
-#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
-#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
-#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
-#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
-#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
-
-/* Bits 6..5 : ADC reference selection. */
-#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
-#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
-#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
-#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
-#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
-#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
-
-/* Bits 4..2 : ADC input selection. */
-#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
-#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
-#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
-#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
-#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
-#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
-#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
-
-/* Bits 1..0 : ADC resolution. */
-#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
-#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
-#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
-#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
-#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
-
-/* Register: ADC_RESULT */
-/* Description: Result of ADC conversion. */
-
-/* Bits 9..0 : Result of ADC conversion. */
-#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
-#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
-
-/* Register: ADC_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: AMLI */
-/* Description: AHB Multi-Layer Interface. */
-
-/* Register: AMLI_RAMPRI_CPU0 */
-/* Description: Configurable priority configuration register for CPU0. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_SPIS1 */
-/* Description: Configurable priority configuration register for SPIS1. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_RADIO */
-/* Description: Configurable priority configuration register for RADIO. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_ECB */
-/* Description: Configurable priority configuration register for ECB. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_CCM */
-/* Description: Configurable priority configuration register for CCM. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Register: AMLI_RAMPRI_AAR */
-/* Description: Configurable priority configuration register for AAR. */
-
-/* Bits 31..28 : Configuration field for RAM block 7. */
-#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
-#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 27..24 : Configuration field for RAM block 6. */
-#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
-#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 23..20 : Configuration field for RAM block 5. */
-#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
-#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 19..16 : Configuration field for RAM block 4. */
-#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
-#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 15..12 : Configuration field for RAM block 3. */
-#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
-#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 11..8 : Configuration field for RAM block 2. */
-#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
-#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 7..4 : Configuration field for RAM block 1. */
-#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
-#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Bits 3..0 : Configuration field for RAM block 0. */
-#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
-#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
-#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
-
-/* Peripheral: CCM */
-/* Description: AES CCM Mode Encryption. */
-
-/* Register: CCM_SHORTS */
-/* Description: Shortcuts for the CCM. */
-
-/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: CCM_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on ERROR event. */
-#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
-#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on ENDCRYPT event. */
-#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
-#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
-#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on ENDKSGEN event. */
-#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
-#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
-#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: CCM_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on ERROR event. */
-#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
-#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on ENDCRYPT event. */
-#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
-#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
-#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on ENDKSGEN event. */
-#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
-#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
-#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
-#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
-#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: CCM_MICSTATUS */
-/* Description: CCM RX MIC check result. */
-
-/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
-#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
-#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
-#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
-#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
-
-/* Register: CCM_ENABLE */
-/* Description: CCM enable. */
-
-/* Bits 1..0 : CCM enable. */
-#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
-#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
-
-/* Register: CCM_MODE */
-/* Description: Operation mode. */
-
-/* Bit 0 : CCM mode operation. */
-#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
-#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
-#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
-#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
-
-/* Register: CCM_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: CLOCK */
-/* Description: Clock control. */
-
-/* Register: CLOCK_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 4 : Enable interrupt on CTTO event. */
-#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
-#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
-#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 3 : Enable interrupt on DONE event. */
-#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
-#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
-#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: CLOCK_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 4 : Disable interrupt on CTTO event. */
-#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
-#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
-#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 3 : Disable interrupt on DONE event. */
-#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
-#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
-#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: CLOCK_HFCLKRUN */
-/* Description: Task HFCLKSTART trigger status. */
-
-/* Bit 0 : Task HFCLKSTART trigger status. */
-#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
-#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
-#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */
-#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */
-
-/* Register: CLOCK_HFCLKSTAT */
-/* Description: High frequency clock status. */
-
-/* Bit 16 : State for the HFCLK. */
-#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
-#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
-#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
-#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
-
-/* Bit 0 : Active clock source for the HF clock. */
-#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
-#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
-
-/* Register: CLOCK_LFCLKRUN */
-/* Description: Task LFCLKSTART triggered status. */
-
-/* Bit 0 : Task LFCLKSTART triggered status. */
-#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
-#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
-#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */
-#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */
-
-/* Register: CLOCK_LFCLKSTAT */
-/* Description: Low frequency clock status. */
-
-/* Bit 16 : State for the LF clock. */
-#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
-#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
-#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
-#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
-
-/* Bits 1..0 : Active clock source for the LF clock. */
-#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
-#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
-#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
-
-/* Register: CLOCK_LFCLKSRCCOPY */
-/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
-
-/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
-#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
-#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
-#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
-
-/* Register: CLOCK_LFCLKSRC */
-/* Description: Clock source for the LFCLK clock. */
-
-/* Bits 1..0 : Clock source. */
-#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
-#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
-#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
-
-/* Register: CLOCK_CTIV */
-/* Description: Calibration timer interval. */
-
-/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
-#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
-#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
-
-/* Register: CLOCK_XTALFREQ */
-/* Description: Crystal frequency. */
-
-/* Bits 7..0 : External Xtal frequency selection. */
-#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
-#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
-#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
-#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
-
-
-/* Peripheral: ECB */
-/* Description: AES ECB Mode Encryption. */
-
-/* Register: ECB_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 1 : Enable interrupt on ERRORECB event. */
-#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
-#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
-#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
-#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
-#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on ENDECB event. */
-#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
-#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
-#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
-#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
-#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: ECB_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 1 : Disable interrupt on ERRORECB event. */
-#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
-#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
-#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
-#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
-#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on ENDECB event. */
-#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
-#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
-#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
-#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
-#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: ECB_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: FICR */
-/* Description: Factory Information Configuration. */
-
-/* Register: FICR_RBD */
-/* Description: RBD. */
-
-/* Bits 31..0 : RBD. */
-#define FICR_RBD_RBD_Pos (0UL) /*!< Position of RBD field. */
-#define FICR_RBD_RBD_Msk (0xFFFFFFFFUL << FICR_RBD_RBD_Pos) /*!< Bit mask of RBD field. */
-#define FICR_RBD_RBD_NoRoyalty (0xFFFFFFFEUL) /*!< No royalty. */
-#define FICR_RBD_RBD_Royalty (0xFFFFFFFFUL) /*!< Royalty. */
-
-/* Register: FICR_PPFC */
-/* Description: Pre-programmed factory code present. */
-
-/* Bits 7..0 : Pre-programmed factory code present. */
-#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
-#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
-#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
-#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
-
-/* Register: FICR_CONFIGID */
-/* Description: Configuration identifier. */
-
-/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
-#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
-#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
-
-/* Bits 15..0 : Hardware Identification Number. */
-#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
-#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
-
-/* Register: FICR_DEVICEADDRTYPE */
-/* Description: Device address type. */
-
-/* Bit 0 : Device address type. */
-#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
-#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
-#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
-#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
-
-/* Register: FICR_OVERRIDEEN */
-/* Description: Radio calibration override enable. */
-
-/* Bit 3 : Override default values for BLE_1Mbit mode. */
-#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
-#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
-#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
-#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
-
-/* Bit 0 : Override default values for NRF_1Mbit mode. */
-#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */
-#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */
-#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
-#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
-
-
-/* Peripheral: GPIO */
-/* Description: General purpose input and output. */
-
-/* Register: GPIO_OUT */
-/* Description: Write GPIO port. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
-
-/* Register: GPIO_OUTSET */
-/* Description: Set individual bits in GPIO port. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
-
-/* Register: GPIO_OUTCLR */
-/* Description: Clear individual bits in GPIO port. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
-#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
-#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
-
-/* Register: GPIO_IN */
-/* Description: Read GPIO port. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
-#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
-
-/* Register: GPIO_DIR */
-/* Description: Direction of GPIO pins. */
-
-/* Bit 31 : Pin 31. */
-#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 30 : Pin 30. */
-#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 29 : Pin 29. */
-#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 28 : Pin 28. */
-#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 27 : Pin 27. */
-#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 26 : Pin 26. */
-#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 25 : Pin 25. */
-#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 24 : Pin 24. */
-#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 23 : Pin 23. */
-#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 22 : Pin 22. */
-#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 21 : Pin 21. */
-#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 20 : Pin 20. */
-#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 19 : Pin 19. */
-#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 18 : Pin 18. */
-#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 17 : Pin 17. */
-#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 16 : Pin 16. */
-#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 15 : Pin 15. */
-#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 14 : Pin 14. */
-#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 13 : Pin 13. */
-#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 12 : Pin 12. */
-#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 11 : Pin 11. */
-#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 10 : Pin 10. */
-#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 9 : Pin 9. */
-#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 8 : Pin 8. */
-#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 7 : Pin 7. */
-#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 6 : Pin 6. */
-#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 5 : Pin 5. */
-#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 4 : Pin 4. */
-#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 3 : Pin 3. */
-#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 2 : Pin 2. */
-#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 1 : Pin 1. */
-#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
-
-/* Bit 0 : Pin 0. */
-#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
-
-/* Register: GPIO_DIRSET */
-/* Description: DIR set register. */
-
-/* Bit 31 : Set as output pin 31. */
-#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 30 : Set as output pin 30. */
-#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 29 : Set as output pin 29. */
-#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 28 : Set as output pin 28. */
-#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 27 : Set as output pin 27. */
-#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 26 : Set as output pin 26. */
-#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 25 : Set as output pin 25. */
-#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 24 : Set as output pin 24. */
-#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 23 : Set as output pin 23. */
-#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 22 : Set as output pin 22. */
-#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 21 : Set as output pin 21. */
-#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 20 : Set as output pin 20. */
-#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 19 : Set as output pin 19. */
-#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 18 : Set as output pin 18. */
-#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 17 : Set as output pin 17. */
-#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 16 : Set as output pin 16. */
-#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 15 : Set as output pin 15. */
-#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 14 : Set as output pin 14. */
-#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 13 : Set as output pin 13. */
-#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 12 : Set as output pin 12. */
-#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 11 : Set as output pin 11. */
-#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 10 : Set as output pin 10. */
-#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 9 : Set as output pin 9. */
-#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 8 : Set as output pin 8. */
-#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 7 : Set as output pin 7. */
-#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 6 : Set as output pin 6. */
-#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 5 : Set as output pin 5. */
-#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 4 : Set as output pin 4. */
-#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 3 : Set as output pin 3. */
-#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 2 : Set as output pin 2. */
-#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 1 : Set as output pin 1. */
-#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
-
-/* Bit 0 : Set as output pin 0. */
-#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
-
-/* Register: GPIO_DIRCLR */
-/* Description: DIR clear register. */
-
-/* Bit 31 : Set as input pin 31. */
-#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
-#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
-#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 30 : Set as input pin 30. */
-#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
-#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
-#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 29 : Set as input pin 29. */
-#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
-#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
-#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 28 : Set as input pin 28. */
-#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
-#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
-#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 27 : Set as input pin 27. */
-#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
-#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
-#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 26 : Set as input pin 26. */
-#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
-#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
-#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 25 : Set as input pin 25. */
-#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
-#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
-#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 24 : Set as input pin 24. */
-#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
-#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
-#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 23 : Set as input pin 23. */
-#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
-#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
-#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 22 : Set as input pin 22. */
-#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
-#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
-#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 21 : Set as input pin 21. */
-#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
-#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
-#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 20 : Set as input pin 20. */
-#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
-#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
-#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 19 : Set as input pin 19. */
-#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
-#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
-#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 18 : Set as input pin 18. */
-#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
-#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
-#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 17 : Set as input pin 17. */
-#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
-#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
-#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 16 : Set as input pin 16. */
-#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
-#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
-#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 15 : Set as input pin 15. */
-#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
-#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
-#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 14 : Set as input pin 14. */
-#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
-#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
-#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 13 : Set as input pin 13. */
-#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
-#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
-#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 12 : Set as input pin 12. */
-#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
-#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
-#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 11 : Set as input pin 11. */
-#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
-#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
-#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 10 : Set as input pin 10. */
-#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
-#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
-#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 9 : Set as input pin 9. */
-#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
-#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
-#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 8 : Set as input pin 8. */
-#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
-#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
-#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 7 : Set as input pin 7. */
-#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
-#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
-#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 6 : Set as input pin 6. */
-#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
-#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
-#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 5 : Set as input pin 5. */
-#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
-#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
-#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 4 : Set as input pin 4. */
-#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
-#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
-#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 3 : Set as input pin 3. */
-#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
-#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
-#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 2 : Set as input pin 2. */
-#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
-#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
-#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 1 : Set as input pin 1. */
-#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
-#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
-#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
-
-/* Bit 0 : Set as input pin 0. */
-#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
-#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
-#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
-#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
-#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
-
-/* Register: GPIO_PIN_CNF */
-/* Description: Configuration of GPIO pins. */
-
-/* Bits 17..16 : Pin sensing mechanism. */
-#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
-#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
-#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
-#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
-#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
-
-/* Bits 10..8 : Drive configuration. */
-#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
-#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
-#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
-#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
-#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
-#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
-#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
-#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
-#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
-#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
-
-/* Bits 3..2 : Pull-up or -down configuration. */
-#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
-#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
-#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
-#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
-#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
-
-/* Bit 1 : Connect or disconnect input path. */
-#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
-#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
-#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
-#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
-
-/* Bit 0 : Pin direction. */
-#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
-#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
-#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
-#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
-
-
-/* Peripheral: GPIOTE */
-/* Description: GPIO tasks and events. */
-
-/* Register: GPIOTE_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 31 : Enable interrupt on PORT event. */
-#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
-#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
-#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 3 : Enable interrupt on IN[3] event. */
-#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
-#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
-#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on IN[2] event. */
-#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
-#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
-#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on IN[1] event. */
-#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
-#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
-#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on IN[0] event. */
-#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
-#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
-#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: GPIOTE_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 31 : Disable interrupt on PORT event. */
-#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
-#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
-#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 3 : Disable interrupt on IN[3] event. */
-#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
-#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
-#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on IN[2] event. */
-#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
-#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
-#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on IN[1] event. */
-#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
-#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
-#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on IN[0] event. */
-#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
-#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
-#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
-#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
-#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: GPIOTE_CONFIG */
-/* Description: Channel configuration registers. */
-
-/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
-#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
-#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
-#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
-#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
-
-/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
-#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
-#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
-#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
-#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
-#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
-
-/* Bits 12..8 : Pin select. */
-#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
-#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
-
-/* Bits 1..0 : Mode */
-#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
-#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
-#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
-#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
-#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
-
-/* Register: GPIOTE_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: LPCOMP */
-/* Description: Low power comparator. */
-
-/* Register: LPCOMP_SHORTS */
-/* Description: Shortcuts for the LPCOMP. */
-
-/* Bit 4 : Shortcut between CROSS event and STOP task. */
-#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
-#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
-#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 3 : Shortcut between UP event and STOP task. */
-#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
-#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
-#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 2 : Shortcut between DOWN event and STOP task. */
-#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
-#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
-#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 1 : Shortcut between RADY event and STOP task. */
-#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
-#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
-#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between READY event and SAMPLE task. */
-#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
-#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
-#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
-#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: LPCOMP_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 3 : Enable interrupt on CROSS event. */
-#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
-#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
-#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on UP event. */
-#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
-#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
-#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on DOWN event. */
-#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
-#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
-#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on READY event. */
-#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
-#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
-#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: LPCOMP_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 3 : Disable interrupt on CROSS event. */
-#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
-#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
-#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on UP event. */
-#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
-#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
-#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on DOWN event. */
-#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
-#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
-#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on READY event. */
-#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
-#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
-#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: LPCOMP_RESULT */
-/* Description: Result of last compare. */
-
-/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
-#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
-#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
-#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
-#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
-
-/* Register: LPCOMP_ENABLE */
-/* Description: Enable the LPCOMP. */
-
-/* Bits 1..0 : Enable or disable LPCOMP. */
-#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
-#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
-
-/* Register: LPCOMP_PSEL */
-/* Description: Input pin select. */
-
-/* Bits 2..0 : Analog input pin select. */
-#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
-#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
-#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
-#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
-
-/* Register: LPCOMP_REFSEL */
-/* Description: Reference select. */
-
-/* Bits 2..0 : Reference select. */
-#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
-#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
-#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */
-#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
-
-/* Register: LPCOMP_EXTREFSEL */
-/* Description: External reference select. */
-
-/* Bit 0 : External analog reference pin selection. */
-#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
-#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
-#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
-#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
-
-/* Register: LPCOMP_ANADETECT */
-/* Description: Analog detect configuration. */
-
-/* Bits 1..0 : Analog detect configuration. */
-#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
-#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
-#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
-#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
-#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
-
-/* Register: LPCOMP_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: MPU */
-/* Description: Memory Protection Unit. */
-
-/* Register: MPU_PERR0 */
-/* Description: Configuration of peripherals in mpu regions. */
-
-/* Bit 31 : PPI region configuration. */
-#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
-#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
-#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 30 : NVMC region configuration. */
-#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
-#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
-#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 19 : LPCOMP region configuration. */
-#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */
-#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
-#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 18 : QDEC region configuration. */
-#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
-#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
-#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 17 : RTC1 region configuration. */
-#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
-#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
-#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 16 : WDT region configuration. */
-#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
-#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
-#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 15 : CCM and AAR region configuration. */
-#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
-#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
-#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 14 : ECB region configuration. */
-#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
-#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
-#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 13 : RNG region configuration. */
-#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
-#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
-#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 12 : TEMP region configuration. */
-#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
-#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
-#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 11 : RTC0 region configuration. */
-#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
-#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
-#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 10 : TIMER2 region configuration. */
-#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
-#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
-#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 9 : TIMER1 region configuration. */
-#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
-#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
-#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 8 : TIMER0 region configuration. */
-#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
-#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
-#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 7 : ADC region configuration. */
-#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
-#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
-#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 6 : GPIOTE region configuration. */
-#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
-#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
-#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 4 : SPI1 and TWI1 region configuration. */
-#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
-#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
-#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 3 : SPI0 and TWI0 region configuration. */
-#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
-#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
-#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 2 : UART0 region configuration. */
-#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
-#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
-#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 1 : RADIO region configuration. */
-#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
-#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
-#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Bit 0 : POWER_CLOCK region configuration. */
-#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
-#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
-#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
-#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
-
-/* Register: MPU_PROTENSET0 */
-/* Description: Erase and write protection bit enable set register. */
-
-/* Bit 31 : Protection enable for region 31. */
-#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
-#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
-#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 30 : Protection enable for region 30. */
-#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
-#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
-#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 29 : Protection enable for region 29. */
-#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
-#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
-#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 28 : Protection enable for region 28. */
-#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
-#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
-#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 27 : Protection enable for region 27. */
-#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
-#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
-#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 26 : Protection enable for region 26. */
-#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
-#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
-#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 25 : Protection enable for region 25. */
-#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
-#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
-#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 24 : Protection enable for region 24. */
-#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
-#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
-#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 23 : Protection enable for region 23. */
-#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
-#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
-#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 22 : Protection enable for region 22. */
-#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
-#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
-#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 21 : Protection enable for region 21. */
-#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
-#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
-#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 20 : Protection enable for region 20. */
-#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
-#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
-#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 19 : Protection enable for region 19. */
-#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
-#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
-#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 18 : Protection enable for region 18. */
-#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
-#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
-#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 17 : Protection enable for region 17. */
-#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
-#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
-#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 16 : Protection enable for region 16. */
-#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
-#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
-#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 15 : Protection enable for region 15. */
-#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
-#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
-#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 14 : Protection enable for region 14. */
-#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
-#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
-#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 13 : Protection enable for region 13. */
-#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
-#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
-#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 12 : Protection enable for region 12. */
-#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
-#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
-#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 11 : Protection enable for region 11. */
-#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
-#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
-#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 10 : Protection enable for region 10. */
-#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
-#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
-#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 9 : Protection enable for region 9. */
-#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
-#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
-#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 8 : Protection enable for region 8. */
-#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
-#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
-#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 7 : Protection enable for region 7. */
-#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
-#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
-#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 6 : Protection enable for region 6. */
-#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
-#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
-#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 5 : Protection enable for region 5. */
-#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
-#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
-#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 4 : Protection enable for region 4. */
-#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
-#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
-#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 3 : Protection enable for region 3. */
-#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
-#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
-#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 2 : Protection enable for region 2. */
-#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
-#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
-#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 1 : Protection enable for region 1. */
-#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
-#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
-#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 0 : Protection enable for region 0. */
-#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
-#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
-#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
-
-/* Register: MPU_PROTENSET1 */
-/* Description: Erase and write protection bit enable set register. */
-
-/* Bit 31 : Protection enable for region 63. */
-#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
-#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
-#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 30 : Protection enable for region 62. */
-#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
-#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
-#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 29 : Protection enable for region 61. */
-#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
-#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
-#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 28 : Protection enable for region 60. */
-#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
-#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
-#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 27 : Protection enable for region 59. */
-#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
-#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
-#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 26 : Protection enable for region 58. */
-#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
-#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
-#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 25 : Protection enable for region 57. */
-#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
-#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
-#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 24 : Protection enable for region 56. */
-#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
-#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
-#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 23 : Protection enable for region 55. */
-#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
-#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
-#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 22 : Protection enable for region 54. */
-#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
-#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
-#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 21 : Protection enable for region 53. */
-#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
-#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
-#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 20 : Protection enable for region 52. */
-#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
-#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
-#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 19 : Protection enable for region 51. */
-#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
-#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
-#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 18 : Protection enable for region 50. */
-#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
-#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
-#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 17 : Protection enable for region 49. */
-#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
-#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
-#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 16 : Protection enable for region 48. */
-#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
-#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
-#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 15 : Protection enable for region 47. */
-#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
-#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
-#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 14 : Protection enable for region 46. */
-#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
-#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
-#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 13 : Protection enable for region 45. */
-#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
-#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
-#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 12 : Protection enable for region 44. */
-#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
-#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
-#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 11 : Protection enable for region 43. */
-#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
-#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
-#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 10 : Protection enable for region 42. */
-#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
-#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
-#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 9 : Protection enable for region 41. */
-#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
-#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
-#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 8 : Protection enable for region 40. */
-#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
-#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
-#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 7 : Protection enable for region 39. */
-#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
-#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
-#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 6 : Protection enable for region 38. */
-#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
-#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
-#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 5 : Protection enable for region 37. */
-#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
-#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
-#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 4 : Protection enable for region 36. */
-#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
-#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
-#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 3 : Protection enable for region 35. */
-#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
-#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
-#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 2 : Protection enable for region 34. */
-#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
-#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
-#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 1 : Protection enable for region 33. */
-#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
-#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
-#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
-
-/* Bit 0 : Protection enable for region 32. */
-#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
-#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
-#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
-#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
-#define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
-
-/* Register: MPU_DISABLEINDEBUG */
-/* Description: Disable erase and write protection mechanism in debug mode. */
-
-/* Bit 0 : Disable protection mechanism in debug mode. */
-#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
-#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
-#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
-#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
-
-/* Register: MPU_PROTBLOCKSIZE */
-/* Description: Erase and write protection block size. */
-
-/* Bits 1..0 : Erase and write protection block size. */
-#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */
-#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */
-#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */
-
-/* Register: MPU_ENRBDREG */
-/* Description: Enable or disable RBD. */
-
-/* Bit 0 : Enable or disable RBD. */
-#define MPU_ENRBDREG_ENRBDREG_Pos (0UL) /*!< Position of ENRBDREG field. */
-#define MPU_ENRBDREG_ENRBDREG_Msk (0x1UL << MPU_ENRBDREG_ENRBDREG_Pos) /*!< Bit mask of ENRBDREG field. */
-#define MPU_ENRBDREG_ENRBDREG_Disabled (0UL) /*!< RBD disabled. */
-#define MPU_ENRBDREG_ENRBDREG_Enabled (1UL) /*!< RBD enabled. */
-
-
-/* Peripheral: NVMC */
-/* Description: Non Volatile Memory Controller. */
-
-/* Register: NVMC_READY */
-/* Description: Ready flag. */
-
-/* Bit 0 : NVMC ready. */
-#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
-#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
-#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
-#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
-
-/* Register: NVMC_CONFIG */
-/* Description: Configuration register. */
-
-/* Bits 1..0 : Program write enable. */
-#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
-#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
-#define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
-#define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
-#define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
-
-/* Register: NVMC_ERASEALL */
-/* Description: Register for erasing all non-volatile user memory. */
-
-/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
-#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
-#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
-#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
-#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
-
-/* Register: NVMC_ERASEUICR */
-/* Description: Register for start erasing User Information Congfiguration Registers. */
-
-/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
-#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
-#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
-#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
-#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
-
-
-/* Peripheral: POWER */
-/* Description: Power Control. */
-
-/* Register: POWER_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on POFWARN event. */
-#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
-#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
-#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
-#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
-#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: POWER_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on POFWARN event. */
-#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
-#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
-#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
-#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
-#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: POWER_RESETREAS */
-/* Description: Reset reason. */
-
-/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
-#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
-#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
-
-/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
-#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
-#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
-
-/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
-#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
-#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
-
-/* Bit 3 : Reset from CPU lock-up detected. */
-#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
-#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
-
-/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
-#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
-#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
-
-/* Bit 1 : Reset from watchdog detected. */
-#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
-#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
-
-/* Bit 0 : Reset from pin-reset detected. */
-#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
-#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
-
-/* Register: POWER_RAMSTATUS */
-/* Description: Ram status register. */
-
-/* Bit 3 : RAM block 3 status. */
-#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
-#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
-#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */
-#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */
-
-/* Bit 2 : RAM block 2 status. */
-#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
-#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
-#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */
-#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
-
-/* Bit 1 : RAM block 1 status. */
-#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
-#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
-#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */
-#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */
-
-/* Bit 0 : RAM block 0 status. */
-#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
-#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
-#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */
-#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */
-
-/* Register: POWER_SYSTEMOFF */
-/* Description: System off register. */
-
-/* Bit 0 : Enter system off mode. */
-#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
-#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
-#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
-
-/* Register: POWER_POFCON */
-/* Description: Power failure configuration. */
-
-/* Bits 2..1 : Set threshold level. */
-#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
-#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
-#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
-#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
-#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
-#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
-
-/* Bit 0 : Power failure comparator enable. */
-#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
-#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
-#define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
-#define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
-
-/* Register: POWER_GPREGRET */
-/* Description: General purpose retention register. This register is a retained register. */
-
-/* Bits 7..0 : General purpose retention register. */
-#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
-#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
-
-/* Register: POWER_RAMON */
-/* Description: Ram on/off. */
-
-/* Bit 17 : RAM block 1 behaviour in OFF mode. */
-#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
-#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
-#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
-#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
-
-/* Bit 16 : RAM block 0 behaviour in OFF mode. */
-#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
-#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
-#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
-#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
-
-/* Bit 1 : RAM block 1 behaviour in ON mode. */
-#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
-#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
-#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
-#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
-
-/* Bit 0 : RAM block 0 behaviour in ON mode. */
-#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
-#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
-#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
-#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
-
-/* Register: POWER_RESET */
-/* Description: Pin reset functionality configuration register. This register is a retained register. */
-
-/* Bit 0 : Enable or disable pin reset in debug interface mode. */
-#define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
-#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
-#define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
-#define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
-
-/* Register: POWER_RAMONB */
-/* Description: Ram on/off. */
-
-/* Bit 17 : RAM block 3 behaviour in OFF mode. */
-#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
-#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
-#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
-#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
-
-/* Bit 16 : RAM block 2 behaviour in OFF mode. */
-#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
-#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
-#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
-#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
-
-/* Bit 1 : RAM block 3 behaviour in ON mode. */
-#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
-#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
-#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */
-#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
-
-/* Bit 0 : RAM block 2 behaviour in ON mode. */
-#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
-#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
-#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
-#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
-
-/* Register: POWER_DCDCEN */
-/* Description: DCDC converter enable configuration register. */
-
-/* Bit 0 : Enable DCDC converter. */
-#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
-#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
-#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
-#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
-
-/* Register: POWER_DCDCFORCE */
-/* Description: DCDC power-up force register. */
-
-/* Bit 1 : DCDC power-up force on. */
-#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */
-#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */
-#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */
-#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */
-
-/* Bit 0 : DCDC power-up force off. */
-#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
-#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
-#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */
-#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */
-
-
-/* Peripheral: PPI */
-/* Description: PPI controller. */
-
-/* Register: PPI_CHEN */
-/* Description: Channel enable. */
-
-/* Bit 31 : Enable PPI channel 31. */
-#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
-#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
-#define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 30 : Enable PPI channel 30. */
-#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
-#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
-#define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 29 : Enable PPI channel 29. */
-#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
-#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
-#define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 28 : Enable PPI channel 28. */
-#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
-#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
-#define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 27 : Enable PPI channel 27. */
-#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
-#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
-#define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 26 : Enable PPI channel 26. */
-#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
-#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
-#define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 25 : Enable PPI channel 25. */
-#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
-#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
-#define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 24 : Enable PPI channel 24. */
-#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
-#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
-#define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 23 : Enable PPI channel 23. */
-#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
-#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
-#define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 22 : Enable PPI channel 22. */
-#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
-#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
-#define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 21 : Enable PPI channel 21. */
-#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
-#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
-#define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 20 : Enable PPI channel 20. */
-#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
-#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
-#define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 15 : Enable PPI channel 15. */
-#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
-#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
-#define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 14 : Enable PPI channel 14. */
-#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
-#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
-#define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 13 : Enable PPI channel 13. */
-#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
-#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
-#define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 12 : Enable PPI channel 12. */
-#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
-#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
-#define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 11 : Enable PPI channel 11. */
-#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
-#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
-#define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 10 : Enable PPI channel 10. */
-#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
-#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
-#define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 9 : Enable PPI channel 9. */
-#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
-#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
-#define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 8 : Enable PPI channel 8. */
-#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
-#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
-#define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 7 : Enable PPI channel 7. */
-#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
-#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
-#define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 6 : Enable PPI channel 6. */
-#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
-#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
-#define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 5 : Enable PPI channel 5. */
-#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
-#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
-#define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 4 : Enable PPI channel 4. */
-#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
-#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
-#define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 3 : Enable PPI channel 3. */
-#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
-#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
-#define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
-#define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
-
-/* Bit 2 : Enable PPI channel 2. */
-#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
-#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
-#define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 1 : Enable PPI channel 1. */
-#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
-#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
-#define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
-
-/* Bit 0 : Enable PPI channel 0. */
-#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
-#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
-#define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
-
-/* Register: PPI_CHENSET */
-/* Description: Channel enable set. */
-
-/* Bit 31 : Enable PPI channel 31. */
-#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
-#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
-#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 30 : Enable PPI channel 30. */
-#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
-#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
-#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 29 : Enable PPI channel 29. */
-#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
-#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
-#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 28 : Enable PPI channel 28. */
-#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
-#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
-#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 27 : Enable PPI channel 27. */
-#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
-#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
-#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 26 : Enable PPI channel 26. */
-#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
-#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
-#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 25 : Enable PPI channel 25. */
-#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
-#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
-#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 24 : Enable PPI channel 24. */
-#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
-#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
-#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 23 : Enable PPI channel 23. */
-#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
-#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
-#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 22 : Enable PPI channel 22. */
-#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
-#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
-#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 21 : Enable PPI channel 21. */
-#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
-#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
-#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 20 : Enable PPI channel 20. */
-#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
-#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
-#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 15 : Enable PPI channel 15. */
-#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
-#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
-#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 14 : Enable PPI channel 14. */
-#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
-#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
-#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 13 : Enable PPI channel 13. */
-#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
-#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
-#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 12 : Enable PPI channel 12. */
-#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
-#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
-#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 11 : Enable PPI channel 11. */
-#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
-#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
-#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 10 : Enable PPI channel 10. */
-#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
-#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
-#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 9 : Enable PPI channel 9. */
-#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
-#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
-#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 8 : Enable PPI channel 8. */
-#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
-#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
-#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 7 : Enable PPI channel 7. */
-#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
-#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
-#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 6 : Enable PPI channel 6. */
-#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
-#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
-#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 5 : Enable PPI channel 5. */
-#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
-#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
-#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 4 : Enable PPI channel 4. */
-#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
-#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
-#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 3 : Enable PPI channel 3. */
-#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
-#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
-#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 2 : Enable PPI channel 2. */
-#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
-#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
-#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 1 : Enable PPI channel 1. */
-#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
-#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
-#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
-
-/* Bit 0 : Enable PPI channel 0. */
-#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
-#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
-#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
-
-/* Register: PPI_CHENCLR */
-/* Description: Channel enable clear. */
-
-/* Bit 31 : Disable PPI channel 31. */
-#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
-#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
-#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 30 : Disable PPI channel 30. */
-#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
-#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
-#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 29 : Disable PPI channel 29. */
-#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
-#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
-#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 28 : Disable PPI channel 28. */
-#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
-#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
-#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 27 : Disable PPI channel 27. */
-#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
-#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
-#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 26 : Disable PPI channel 26. */
-#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
-#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
-#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 25 : Disable PPI channel 25. */
-#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
-#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
-#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 24 : Disable PPI channel 24. */
-#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
-#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
-#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 23 : Disable PPI channel 23. */
-#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
-#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
-#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 22 : Disable PPI channel 22. */
-#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
-#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
-#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 21 : Disable PPI channel 21. */
-#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
-#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
-#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 20 : Disable PPI channel 20. */
-#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
-#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
-#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 15 : Disable PPI channel 15. */
-#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
-#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
-#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 14 : Disable PPI channel 14. */
-#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
-#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
-#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 13 : Disable PPI channel 13. */
-#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
-#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
-#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 12 : Disable PPI channel 12. */
-#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
-#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
-#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 11 : Disable PPI channel 11. */
-#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
-#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
-#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 10 : Disable PPI channel 10. */
-#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
-#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
-#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 9 : Disable PPI channel 9. */
-#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
-#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
-#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 8 : Disable PPI channel 8. */
-#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
-#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
-#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 7 : Disable PPI channel 7. */
-#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
-#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
-#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 6 : Disable PPI channel 6. */
-#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
-#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
-#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 5 : Disable PPI channel 5. */
-#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
-#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
-#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 4 : Disable PPI channel 4. */
-#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
-#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
-#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 3 : Disable PPI channel 3. */
-#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
-#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
-#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 2 : Disable PPI channel 2. */
-#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
-#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
-#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 1 : Disable PPI channel 1. */
-#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
-#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
-#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
-
-/* Bit 0 : Disable PPI channel 0. */
-#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
-#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
-#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
-#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
-#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
-
-/* Register: PPI_CHG */
-/* Description: Channel group configuration. */
-
-/* Bit 31 : Include CH31 in channel group. */
-#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
-#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
-#define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
-
-/* Bit 30 : Include CH30 in channel group. */
-#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
-#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
-#define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
-
-/* Bit 29 : Include CH29 in channel group. */
-#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
-#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
-#define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
-
-/* Bit 28 : Include CH28 in channel group. */
-#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
-#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
-#define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
-
-/* Bit 27 : Include CH27 in channel group. */
-#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
-#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
-#define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
-
-/* Bit 26 : Include CH26 in channel group. */
-#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
-#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
-#define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
-
-/* Bit 25 : Include CH25 in channel group. */
-#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
-#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
-#define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
-
-/* Bit 24 : Include CH24 in channel group. */
-#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
-#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
-#define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
-
-/* Bit 23 : Include CH23 in channel group. */
-#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
-#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
-#define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
-
-/* Bit 22 : Include CH22 in channel group. */
-#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
-#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
-#define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
-
-/* Bit 21 : Include CH21 in channel group. */
-#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
-#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
-#define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
-
-/* Bit 20 : Include CH20 in channel group. */
-#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
-#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
-#define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
-
-/* Bit 15 : Include CH15 in channel group. */
-#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
-#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
-#define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
-
-/* Bit 14 : Include CH14 in channel group. */
-#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
-#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
-#define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
-
-/* Bit 13 : Include CH13 in channel group. */
-#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
-#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
-#define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
-
-/* Bit 12 : Include CH12 in channel group. */
-#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
-#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
-#define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
-
-/* Bit 11 : Include CH11 in channel group. */
-#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
-#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
-#define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
-
-/* Bit 10 : Include CH10 in channel group. */
-#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
-#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
-#define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
-
-/* Bit 9 : Include CH9 in channel group. */
-#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
-#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
-#define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
-
-/* Bit 8 : Include CH8 in channel group. */
-#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
-#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
-#define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
-
-/* Bit 7 : Include CH7 in channel group. */
-#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
-#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
-#define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
-
-/* Bit 6 : Include CH6 in channel group. */
-#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
-#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
-#define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
-
-/* Bit 5 : Include CH5 in channel group. */
-#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
-#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
-#define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
-
-/* Bit 4 : Include CH4 in channel group. */
-#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
-#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
-#define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
-
-/* Bit 3 : Include CH3 in channel group. */
-#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
-#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
-#define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
-
-/* Bit 2 : Include CH2 in channel group. */
-#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
-#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
-#define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
-
-/* Bit 1 : Include CH1 in channel group. */
-#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
-#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
-#define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
-
-/* Bit 0 : Include CH0 in channel group. */
-#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
-#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
-#define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
-#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
-
-
-/* Peripheral: PU */
-/* Description: Patch unit. */
-
-/* Register: PU_PATCHADDR */
-/* Description: Relative address of patch instructions. */
-
-/* Bits 24..0 : Relative address of patch instructions. */
-#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */
-#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */
-
-/* Register: PU_PATCHEN */
-/* Description: Patch enable register. */
-
-/* Bit 7 : Patch 7 enabled. */
-#define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
-#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
-#define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 6 : Patch 6 enabled. */
-#define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
-#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
-#define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 5 : Patch 5 enabled. */
-#define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
-#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
-#define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 4 : Patch 4 enabled. */
-#define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
-#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
-#define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 3 : Patch 3 enabled. */
-#define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
-#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
-#define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 2 : Patch 2 enabled. */
-#define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
-#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
-#define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 1 : Patch 1 enabled. */
-#define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
-#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
-#define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */
-
-/* Bit 0 : Patch 0 enabled. */
-#define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
-#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
-#define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */
-
-/* Register: PU_PATCHENSET */
-/* Description: Patch enable register. */
-
-/* Bit 7 : Patch 7 enabled. */
-#define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
-#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
-#define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 6 : Patch 6 enabled. */
-#define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
-#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
-#define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 5 : Patch 5 enabled. */
-#define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
-#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
-#define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 4 : Patch 4 enabled. */
-#define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
-#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
-#define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 3 : Patch 3 enabled. */
-#define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
-#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
-#define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 2 : Patch 2 enabled. */
-#define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
-#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
-#define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 1 : Patch 1 enabled. */
-#define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
-#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
-#define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */
-
-/* Bit 0 : Patch 0 enabled. */
-#define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
-#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
-#define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */
-
-/* Register: PU_PATCHENCLR */
-/* Description: Patch disable register. */
-
-/* Bit 7 : Patch 7 enabled. */
-#define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
-#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
-#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 6 : Patch 6 enabled. */
-#define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
-#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
-#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 5 : Patch 5 enabled. */
-#define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
-#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
-#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 4 : Patch 4 enabled. */
-#define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
-#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
-#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 3 : Patch 3 enabled. */
-#define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
-#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
-#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 2 : Patch 2 enabled. */
-#define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
-#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
-#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 1 : Patch 1 enabled. */
-#define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
-#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
-#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */
-
-/* Bit 0 : Patch 0 enabled. */
-#define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
-#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
-#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */
-#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */
-#define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */
-
-
-/* Peripheral: QDEC */
-/* Description: Rotary decoder. */
-
-/* Register: QDEC_SHORTS */
-/* Description: Shortcuts for the QDEC. */
-
-/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
-#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
-#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
-#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
-#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
-#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
-#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
-#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: QDEC_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on ACCOF event. */
-#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
-#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
-#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on REPORTRDY event. */
-#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
-#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
-#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on SAMPLERDY event. */
-#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
-#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
-#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: QDEC_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on ACCOF event. */
-#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
-#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
-#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on REPORTRDY event. */
-#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
-#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
-#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on SAMPLERDY event. */
-#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
-#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
-#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: QDEC_ENABLE */
-/* Description: Enable the QDEC. */
-
-/* Bit 0 : Enable or disable QDEC. */
-#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
-#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
-
-/* Register: QDEC_LEDPOL */
-/* Description: LED output pin polarity. */
-
-/* Bit 0 : LED output pin polarity. */
-#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
-#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
-#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
-#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
-
-/* Register: QDEC_SAMPLEPER */
-/* Description: Sample period. */
-
-/* Bits 2..0 : Sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
-#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
-#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
-#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
-
-/* Register: QDEC_SAMPLE */
-/* Description: Motion sample value. */
-
-/* Bits 31..0 : Last sample taken in compliment to 2. */
-#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
-#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
-
-/* Register: QDEC_REPORTPER */
-/* Description: Number of samples to generate an EVENT_REPORTRDY. */
-
-/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
-#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
-#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
-#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
-#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
-
-/* Register: QDEC_DBFEN */
-/* Description: Enable debouncer input filters. */
-
-/* Bit 0 : Enable debounce input filters. */
-#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
-#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
-#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
-#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
-
-/* Register: QDEC_LEDPRE */
-/* Description: Time LED is switched ON before the sample. */
-
-/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
-#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
-#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
-
-/* Register: QDEC_ACCDBL */
-/* Description: Accumulated double (error) transitions register. */
-
-/* Bits 3..0 : Accumulated double (error) transitions. */
-#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
-#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
-
-/* Register: QDEC_ACCDBLREAD */
-/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
-
-/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
-#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
-#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
-
-/* Register: QDEC_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: RADIO */
-/* Description: The radio. */
-
-/* Register: RADIO_SHORTS */
-/* Description: Shortcuts for the radio. */
-
-/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
-#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
-#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
-#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
-#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
-#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
-#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 5 : Shortcut between END event and START task. */
-#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
-#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
-#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
-#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
-#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
-#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
-#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
-#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
-#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 2 : Shortcut between DISABLED event and TXEN task.  */
-#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
-#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
-#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 1 : Shortcut between END event and DISABLE task. */
-#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
-#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
-#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between READY event and START task. */
-#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
-#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
-#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
-#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: RADIO_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 10 : Enable interrupt on BCMATCH event. */
-#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
-#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
-#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 7 : Enable interrupt on RSSIEND event. */
-#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
-#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
-#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 6 : Enable interrupt on DEVMISS event. */
-#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
-#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
-#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 5 : Enable interrupt on DEVMATCH event. */
-#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
-#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
-#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 4 : Enable interrupt on DISABLED event. */
-#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
-#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
-#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 3 : Enable interrupt on END event. */
-#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
-#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on PAYLOAD event. */
-#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
-#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
-#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on ADDRESS event. */
-#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
-#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
-#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on READY event. */
-#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
-#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
-#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: RADIO_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 10 : Disable interrupt on BCMATCH event. */
-#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
-#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
-#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 7 : Disable interrupt on RSSIEND event. */
-#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
-#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
-#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 6 : Disable interrupt on DEVMISS event. */
-#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
-#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
-#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 5 : Disable interrupt on DEVMATCH event. */
-#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
-#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
-#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 4 : Disable interrupt on DISABLED event. */
-#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
-#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
-#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 3 : Disable interrupt on END event. */
-#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
-#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on PAYLOAD event. */
-#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
-#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
-#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on ADDRESS event. */
-#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
-#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
-#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on READY event. */
-#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
-#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
-#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: RADIO_CRCSTATUS */
-/* Description: CRC status of received packet. */
-
-/* Bit 0 : CRC status of received packet. */
-#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
-#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
-#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
-#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
-
-/* Register: RADIO_CD */
-/* Description: Carrier detect. */
-
-/* Bit 0 : Carrier detect. */
-#define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */
-#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */
-
-/* Register: RADIO_RXMATCH */
-/* Description: Received address. */
-
-/* Bits 2..0 : Logical address in which previous packet was received. */
-#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
-#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
-
-/* Register: RADIO_RXCRC */
-/* Description: Received CRC. */
-
-/* Bits 23..0 : CRC field of previously received packet. */
-#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
-#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
-
-/* Register: RADIO_DAI */
-/* Description: Device address match index. */
-
-/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
-#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
-#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
-
-/* Register: RADIO_FREQUENCY */
-/* Description: Frequency. */
-
-/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task.  */
-#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
-#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
-
-/* Register: RADIO_TXPOWER */
-/* Description: Output power. */
-
-/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
-#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
-#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
-#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
-#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
-#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
-
-/* Register: RADIO_MODE */
-/* Description: Data rate and modulation. */
-
-/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
-#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
-#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
-#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
-#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
-#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
-#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
-
-/* Register: RADIO_PCNF0 */
-/* Description: Packet configuration 0. */
-
-/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
-#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
-#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
-
-/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
-#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
-#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
-
-/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
-#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
-#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
-
-/* Register: RADIO_PCNF1 */
-/* Description: Packet configuration 1. */
-
-/* Bit 25 : Packet whitening enable. */
-#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
-#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
-#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
-#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
-
-/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
-#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
-#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
-#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
-#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
-
-/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
-#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
-#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
-
-/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
-#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
-#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
-
-/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
-#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
-#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
-
-/* Register: RADIO_PREFIX0 */
-/* Description: Prefixes bytes for logical addresses 0 to 3. */
-
-/* Bits 31..24 : Address prefix 3. Decision point: START task. */
-#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
-#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
-
-/* Bits 23..16 : Address prefix 2. Decision point: START task. */
-#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
-#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
-
-/* Bits 15..8 : Address prefix 1. Decision point: START task. */
-#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
-#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
-
-/* Bits 7..0 : Address prefix 0. Decision point: START task. */
-#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
-#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
-
-/* Register: RADIO_PREFIX1 */
-/* Description: Prefixes bytes for logical addresses 4 to 7. */
-
-/* Bits 31..24 : Address prefix 7. Decision point: START task. */
-#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
-#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
-
-/* Bits 23..16 : Address prefix 6. Decision point: START task. */
-#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
-#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
-
-/* Bits 15..8 : Address prefix 5. Decision point: START task. */
-#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
-#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
-
-/* Bits 7..0 : Address prefix 4. Decision point: START task. */
-#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
-#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
-
-/* Register: RADIO_TXADDRESS */
-/* Description: Transmit address select. */
-
-/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
-#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
-#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
-
-/* Register: RADIO_RXADDRESSES */
-/* Description: Receive address select. */
-
-/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
-#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
-#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
-#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
-#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
-#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
-#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
-#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
-#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
-#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
-#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
-#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
-#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
-#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
-#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
-
-/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
-#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
-#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
-#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
-#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
-
-/* Register: RADIO_CRCCNF */
-/* Description: CRC configuration. */
-
-/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
-#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
-#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
-#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
-#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
-
-/* Bits 1..0 : CRC length. Decision point: START task. */
-#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
-#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
-#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
-#define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
-#define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
-#define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
-
-/* Register: RADIO_CRCPOLY */
-/* Description: CRC polynomial. */
-
-/* Bits 23..0 : CRC polynomial. Decision point: START task. */
-#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
-#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
-
-/* Register: RADIO_CRCINIT */
-/* Description: CRC initial value. */
-
-/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
-#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
-#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
-
-/* Register: RADIO_TEST */
-/* Description: Test features enable register. */
-
-/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
-#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */
-#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */
-#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */
-#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */
-
-/* Bit 0 : Constant carrier. Decision point: TXEN task. */
-#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */
-#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */
-#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
-#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
-
-/* Register: RADIO_TIFS */
-/* Description: Inter Frame Spacing in microseconds. */
-
-/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
-#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
-#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
-
-/* Register: RADIO_RSSISAMPLE */
-/* Description: RSSI sample. */
-
-/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
-#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
-#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
-
-/* Register: RADIO_STATE */
-/* Description: Current radio state. */
-
-/* Bits 3..0 : Current radio state. */
-#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
-#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
-#define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
-#define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
-#define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
-#define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
-#define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
-#define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
-#define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
-#define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
-#define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
-
-/* Register: RADIO_DATAWHITEIV */
-/* Description: Data whitening initial value. */
-
-/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
-#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
-#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
-
-/* Register: RADIO_DAP */
-/* Description: Device address prefix. */
-
-/* Bits 15..0 : Device address prefix. */
-#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
-#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
-
-/* Register: RADIO_DACNF */
-/* Description: Device address match configuration. */
-
-/* Bit 15 : TxAdd for device address 7. */
-#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
-#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
-
-/* Bit 14 : TxAdd for device address 6. */
-#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
-#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
-
-/* Bit 13 : TxAdd for device address 5. */
-#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
-#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
-
-/* Bit 12 : TxAdd for device address 4. */
-#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
-#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
-
-/* Bit 11 : TxAdd for device address 3. */
-#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
-#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
-
-/* Bit 10 : TxAdd for device address 2. */
-#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
-#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
-
-/* Bit 9 : TxAdd for device address 1. */
-#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
-#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
-
-/* Bit 8 : TxAdd for device address 0. */
-#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
-#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
-
-/* Bit 7 : Enable or disable device address matching using device address 7. */
-#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
-#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
-#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 6 : Enable or disable device address matching using device address 6. */
-#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
-#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
-#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 5 : Enable or disable device address matching using device address 5. */
-#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
-#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
-#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 4 : Enable or disable device address matching using device address 4. */
-#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
-#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
-#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 3 : Enable or disable device address matching using device address 3. */
-#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
-#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
-#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 2 : Enable or disable device address matching using device address 2. */
-#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
-#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
-#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 1 : Enable or disable device address matching using device address 1. */
-#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
-#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
-#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
-
-/* Bit 0 : Enable or disable device address matching using device address 0. */
-#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
-#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
-#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
-#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
-
-/* Register: RADIO_OVERRIDE0 */
-/* Description: Trim value override register 0. */
-
-/* Bits 31..0 : Trim value override 0. */
-#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
-#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
-
-/* Register: RADIO_OVERRIDE1 */
-/* Description: Trim value override register 1. */
-
-/* Bits 31..0 : Trim value override 1. */
-#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
-#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
-
-/* Register: RADIO_OVERRIDE2 */
-/* Description: Trim value override register 2. */
-
-/* Bits 31..0 : Trim value override 2. */
-#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
-#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
-
-/* Register: RADIO_OVERRIDE3 */
-/* Description: Trim value override register 3. */
-
-/* Bits 31..0 : Trim value override 3. */
-#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
-#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
-
-/* Register: RADIO_OVERRIDE4 */
-/* Description: Trim value override register 4. */
-
-/* Bit 31 : Enable or disable override of default trim values. */
-#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
-#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
-#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
-
-/* Bits 27..0 : Trim value override 4. */
-#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
-#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
-
-/* Register: RADIO_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: RNG */
-/* Description: Random Number Generator. */
-
-/* Register: RNG_SHORTS */
-/* Description: Shortcuts for the RNG. */
-
-/* Bit 0 : Shortcut between VALRDY event and STOP task. */
-#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
-#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
-#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: RNG_INTENSET */
-/* Description: Interrupt enable set register */
-
-/* Bit 0 : Enable interrupt on VALRDY event. */
-#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
-#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
-#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: RNG_INTENCLR */
-/* Description: Interrupt enable clear register */
-
-/* Bit 0 : Disable interrupt on VALRDY event. */
-#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
-#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
-#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: RNG_CONFIG */
-/* Description: Configuration register. */
-
-/* Bit 0 : Digital error correction enable. */
-#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
-#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
-#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
-#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
-
-/* Register: RNG_VALUE */
-/* Description: RNG random number. */
-
-/* Bits 7..0 : Generated random number. */
-#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
-#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
-
-/* Register: RNG_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: RTC */
-/* Description: Real time counter 0. */
-
-/* Register: RTC_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 19 : Enable interrupt on COMPARE[3] event. */
-#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 18 : Enable interrupt on COMPARE[2] event. */
-#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 17 : Enable interrupt on COMPARE[1] event. */
-#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 16 : Enable interrupt on COMPARE[0] event. */
-#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on OVRFLW event. */
-#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on TICK event. */
-#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: RTC_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 19 : Disable interrupt on COMPARE[3] event. */
-#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 18 : Disable interrupt on COMPARE[2] event. */
-#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 17 : Disable interrupt on COMPARE[1] event. */
-#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 16 : Disable interrupt on COMPARE[0] event. */
-#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on OVRFLW event. */
-#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on TICK event. */
-#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
-#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
-#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: RTC_EVTEN */
-/* Description: Configures event enable routing to PPI for each RTC event. */
-
-/* Bit 19 : COMPARE[3] event enable. */
-#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 18 : COMPARE[2] event enable. */
-#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 17 : COMPARE[1] event enable. */
-#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 16 : COMPARE[0] event enable. */
-#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 1 : OVRFLW event enable. */
-#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
-
-/* Bit 0 : TICK event enable. */
-#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
-
-/* Register: RTC_EVTENSET */
-/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
-
-/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
-#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
-#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
-#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
-#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 1 : Enable routing to PPI of OVRFLW event. */
-#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
-
-/* Bit 0 : Enable routing to PPI of TICK event. */
-#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
-
-/* Register: RTC_EVTENCLR */
-/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
-
-/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
-#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
-#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
-#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
-#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 1 : Disable routing to PPI of OVRFLW event. */
-#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
-#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
-#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
-
-/* Bit 0 : Disable routing to PPI of TICK event. */
-#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
-#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
-#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
-#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
-#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
-
-/* Register: RTC_COUNTER */
-/* Description: Current COUNTER value. */
-
-/* Bits 23..0 : Counter value. */
-#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
-#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
-
-/* Register: RTC_PRESCALER */
-/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
-
-/* Bits 11..0 : RTC PRESCALER value. */
-#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
-#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
-
-/* Register: RTC_CC */
-/* Description: Capture/compare registers. */
-
-/* Bits 23..0 : Compare value. */
-#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
-#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
-
-/* Register: RTC_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: SPI */
-/* Description: SPI master 0. */
-
-/* Register: SPI_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 2 : Enable interrupt on READY event. */
-#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
-#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
-#define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: SPI_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 2 : Disable interrupt on READY event. */
-#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
-#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
-#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: SPI_ENABLE */
-/* Description: Enable SPI. */
-
-/* Bits 2..0 : Enable or disable SPI. */
-#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
-#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
-
-/* Register: SPI_RXD */
-/* Description: RX data. */
-
-/* Bits 7..0 : RX data from last transfer. */
-#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
-#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
-
-/* Register: SPI_TXD */
-/* Description: TX data. */
-
-/* Bits 7..0 : TX data for next transfer. */
-#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
-#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
-
-/* Register: SPI_FREQUENCY */
-/* Description: SPI frequency */
-
-/* Bits 31..0 : SPI data rate. */
-#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
-#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
-#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
-#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
-#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
-#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
-#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
-#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
-#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
-
-/* Register: SPI_CONFIG */
-/* Description: Configuration register. */
-
-/* Bit 2 : Serial clock (SCK) polarity. */
-#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
-#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
-#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
-#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
-
-/* Bit 1 : Serial clock (SCK) phase. */
-#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
-#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
-#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
-#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
-
-/* Bit 0 : Bit order. */
-#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
-#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
-#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
-#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
-
-/* Register: SPI_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: SPIS */
-/* Description: SPI slave 1. */
-
-/* Register: SPIS_SHORTS */
-/* Description: Shortcuts for SPIS. */
-
-/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
-#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
-#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
-#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
-#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: SPIS_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 10 : Enable interrupt on ACQUIRED event. */
-#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
-#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
-#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on END event. */
-#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
-#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: SPIS_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 10 : Disable interrupt on ACQUIRED event. */
-#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
-#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
-#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on END event. */
-#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
-#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
-#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
-#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: SPIS_SEMSTAT */
-/* Description: Semaphore status. */
-
-/* Bits 1..0 : Semaphore status. */
-#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
-#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
-#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
-#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
-#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
-#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
-
-/* Register: SPIS_STATUS */
-/* Description: Status from last transaction. */
-
-/* Bit 1 : RX buffer overflow detected, and prevented. */
-#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
-#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
-#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
-#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
-#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
-
-/* Bit 0 : TX buffer overread detected, and prevented. */
-#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
-#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
-#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
-#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
-#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
-
-/* Register: SPIS_ENABLE */
-/* Description: Enable SPIS. */
-
-/* Bits 2..0 : Enable or disable SPIS. */
-#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
-#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
-
-/* Register: SPIS_MAXRX */
-/* Description: Maximum number of bytes in the receive buffer. */
-
-/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
-#define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
-#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
-
-/* Register: SPIS_AMOUNTRX */
-/* Description: Number of bytes received in last granted transaction. */
-
-/* Bits 7..0 : Number of bytes received in last granted transaction. */
-#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
-#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
-
-/* Register: SPIS_MAXTX */
-/* Description: Maximum number of bytes in the transmit buffer. */
-
-/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
-#define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
-#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
-
-/* Register: SPIS_AMOUNTTX */
-/* Description: Number of bytes transmitted in last granted transaction. */
-
-/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
-#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
-#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
-
-/* Register: SPIS_CONFIG */
-/* Description: Configuration register. */
-
-/* Bit 2 : Serial clock (SCK) polarity. */
-#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
-#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
-#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
-#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
-
-/* Bit 1 : Serial clock (SCK) phase. */
-#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
-#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
-#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
-#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
-
-/* Bit 0 : Bit order. */
-#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
-#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
-#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
-#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
-
-/* Register: SPIS_DEF */
-/* Description: Default character. */
-
-/* Bits 7..0 : Default character. */
-#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
-#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
-
-/* Register: SPIS_ORC */
-/* Description: Over-read character. */
-
-/* Bits 7..0 : Over-read character. */
-#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
-#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
-
-/* Register: SPIS_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: TEMP */
-/* Description: Temperature Sensor. */
-
-/* Register: TEMP_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 0 : Enable interrupt on DATARDY event. */
-#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
-#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
-#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: TEMP_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 0 : Disable interrupt on DATARDY event. */
-#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
-#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
-#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: TEMP_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: TIMER */
-/* Description: Timer 0. */
-
-/* Register: TIMER_SHORTS */
-/* Description: Shortcuts for Timer. */
-
-/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
-#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
-#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
-#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
-#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
-#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
-#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
-#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
-#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
-#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
-#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
-#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
-#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
-#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
-#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
-#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
-#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
-#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
-#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
-#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
-#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
-#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
-#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
-#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
-#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
-#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: TIMER_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 19 : Enable interrupt on COMPARE[3] */
-#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 18 : Enable interrupt on COMPARE[2] */
-#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 17 : Enable interrupt on COMPARE[1] */
-#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 16 : Enable interrupt on COMPARE[0] */
-#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: TIMER_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 19 : Disable interrupt on COMPARE[3] */
-#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
-#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
-#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 18 : Disable interrupt on COMPARE[2] */
-#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
-#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
-#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 17 : Disable interrupt on COMPARE[1] */
-#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
-#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
-#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 16 : Disable interrupt on COMPARE[0] */
-#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
-#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
-#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
-#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
-#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: TIMER_MODE */
-/* Description: Timer Mode selection. */
-
-/* Bit 0 : Select Normal or Counter mode. */
-#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
-#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
-#define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
-#define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
-
-/* Register: TIMER_BITMODE */
-/* Description: Sets timer behaviour. */
-
-/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
-#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
-#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
-#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
-#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
-#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
-#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
-
-/* Register: TIMER_PRESCALER */
-/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
-
-/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
-#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
-#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
-
-/* Register: TIMER_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: TWI */
-/* Description: Two-wire interface master 0. */
-
-/* Register: TWI_SHORTS */
-/* Description: Shortcuts for TWI. */
-
-/* Bit 1 : Shortcut between BB event and the STOP task. */
-#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
-#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
-#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
-#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
-#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
-#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
-#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
-#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: TWI_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 18 : Enable interrupt on SUSPENDED event. */
-#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
-#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
-#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 14 : Enable interrupt on BB event. */
-#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
-#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
-#define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 9 : Enable interrupt on ERROR event. */
-#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
-#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 7 : Enable interrupt on TXDSENT event. */
-#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
-#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
-#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on READY event. */
-#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
-#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
-#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on STOPPED event. */
-#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
-#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
-#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: TWI_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 18 : Disable interrupt on SUSPENDED event. */
-#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
-#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
-#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 14 : Disable interrupt on BB event. */
-#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
-#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
-#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 9 : Disable interrupt on ERROR event. */
-#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
-#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 7 : Disable interrupt on TXDSENT event. */
-#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
-#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
-#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on RXDREADY event. */
-#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
-#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
-#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on STOPPED event. */
-#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
-#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
-#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
-#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
-#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: TWI_ERRORSRC */
-/* Description: Two-wire error source. Write error field to 1 to clear error. */
-
-/* Bit 2 : NACK received after sending a data byte. */
-#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
-#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
-#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
-#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
-#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
-
-/* Bit 1 : NACK received after sending the address. */
-#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
-#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
-#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
-#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
-#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
-
-/* Register: TWI_ENABLE */
-/* Description: Enable two-wire master. */
-
-/* Bits 2..0 : Enable or disable W2M */
-#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
-#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
-
-/* Register: TWI_RXD */
-/* Description: RX data register. */
-
-/* Bits 7..0 : RX data from last transfer. */
-#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
-#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
-
-/* Register: TWI_TXD */
-/* Description: TX data register. */
-
-/* Bits 7..0 : TX data for next transfer. */
-#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
-#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
-
-/* Register: TWI_FREQUENCY */
-/* Description: Two-wire frequency. */
-
-/* Bits 31..0 : Two-wire master clock frequency. */
-#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
-#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
-#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
-#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
-#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
-
-/* Register: TWI_ADDRESS */
-/* Description: Address used in the two-wire transfer. */
-
-/* Bits 6..0 : Two-wire address. */
-#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
-#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
-
-/* Register: TWI_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: UART */
-/* Description: Universal Asynchronous Receiver/Transmitter. */
-
-/* Register: UART_SHORTS */
-/* Description: Shortcuts for UART. */
-
-/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
-#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
-#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
-#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
-#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Bit 3 : Shortcut between CTS event and the STARTRX task. */
-#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
-#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
-#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
-#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
-
-/* Register: UART_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 17 : Enable interrupt on RXTO event. */
-#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
-#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
-#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 9 : Enable interrupt on ERROR event. */
-#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
-#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 7 : Enable interrupt on TXRDY event. */
-#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
-#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
-#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 2 : Enable interrupt on RXRDY event. */
-#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
-#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
-#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 1 : Enable interrupt on NCTS event. */
-#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
-#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
-#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Bit 0 : Enable interrupt on CTS event. */
-#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
-#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
-#define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: UART_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 17 : Disable interrupt on RXTO event. */
-#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
-#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
-#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 9 : Disable interrupt on ERROR event. */
-#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
-#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 7 : Disable interrupt on TXRDY event. */
-#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
-#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
-#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 2 : Disable interrupt on RXRDY event. */
-#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
-#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
-#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 1 : Disable interrupt on NCTS event. */
-#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
-#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
-#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Bit 0 : Disable interrupt on CTS event. */
-#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
-#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
-#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
-#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
-#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: UART_ERRORSRC */
-/* Description: Error source. Write error field to 1 to clear error. */
-
-/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
-#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
-#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
-#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
-#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
-#define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
-
-/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
-#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
-#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
-#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
-#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
-#define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
-
-/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
-#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
-#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
-#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
-#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
-#define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
-
-/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
-#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
-#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
-#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
-#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
-#define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
-
-/* Register: UART_ENABLE */
-/* Description: Enable UART and acquire IOs. */
-
-/* Bits 2..0 : Enable or disable UART and acquire IOs. */
-#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
-#define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
-
-/* Register: UART_RXD */
-/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consummed. If read when no character available, the UART will stop working. */
-
-/* Bits 7..0 : RX data from previous transfer. Double buffered. */
-#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
-#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
-
-/* Register: UART_TXD */
-/* Description: TXD register. */
-
-/* Bits 7..0 : TX data for transfer. */
-#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
-#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
-
-/* Register: UART_BAUDRATE */
-/* Description: UART Baudrate. */
-
-/* Bits 31..0 : UART baudrate. */
-#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
-#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
-#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */
-#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
-
-/* Register: UART_CONFIG */
-/* Description: Configuration of parity and hardware flow control register. */
-
-/* Bits 3..1 : Include parity bit. */
-#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
-#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
-#define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
-#define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
-
-/* Bit 0 : Hardware flow control. */
-#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
-#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
-#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
-#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
-
-/* Register: UART_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/* Peripheral: UICR */
-/* Description: User Information Configuration. */
-
-/* Register: UICR_RBPCONF */
-/* Description: Readback protection configuration. */
-
-/* Bits 15..8 : Readback protect all code in the device. */
-#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
-#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
-#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
-#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
-
-/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
-#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
-#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
-#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
-#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
-
-/* Register: UICR_XTALFREQ */
-/* Description: Reset value for CLOCK XTALFREQ register. */
-
-/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
-#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
-#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
-#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
-#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
-
-/* Register: UICR_FWID */
-/* Description: Firmware ID. */
-
-/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
-#define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
-#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
-
-
-/* Peripheral: WDT */
-/* Description: Watchdog Timer. */
-
-/* Register: WDT_INTENSET */
-/* Description: Interrupt enable set register. */
-
-/* Bit 0 : Enable interrupt on TIMEOUT event. */
-#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
-#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
-#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
-#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
-#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
-
-/* Register: WDT_INTENCLR */
-/* Description: Interrupt enable clear register. */
-
-/* Bit 0 : Disable interrupt on TIMEOUT event. */
-#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
-#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
-#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
-#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
-#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
-
-/* Register: WDT_RUNSTATUS */
-/* Description: Watchdog running status. */
-
-/* Bit 0 : Watchdog running status. */
-#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
-#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
-#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
-#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
-
-/* Register: WDT_REQSTATUS */
-/* Description: Request status. */
-
-/* Bit 7 : Request status for RR[7]. */
-#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
-#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
-#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
-
-/* Bit 6 : Request status for RR[6]. */
-#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
-#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
-#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
-
-/* Bit 5 : Request status for RR[5]. */
-#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
-#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
-#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
-
-/* Bit 4 : Request status for RR[4]. */
-#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
-#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
-#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
-
-/* Bit 3 : Request status for RR[3]. */
-#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
-#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
-#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
-
-/* Bit 2 : Request status for RR[2]. */
-#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
-#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
-#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
-
-/* Bit 1 : Request status for RR[1]. */
-#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
-#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
-#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
-
-/* Bit 0 : Request status for RR[0]. */
-#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
-#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
-#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
-#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
-
-/* Register: WDT_RREN */
-/* Description: Reload request enable. */
-
-/* Bit 7 : Enable or disable RR[7] register. */
-#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
-#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
-#define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
-#define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
-
-/* Bit 6 : Enable or disable RR[6] register. */
-#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
-#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
-#define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
-#define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
-
-/* Bit 5 : Enable or disable RR[5] register. */
-#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
-#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
-#define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
-#define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
-
-/* Bit 4 : Enable or disable RR[4] register. */
-#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
-#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
-#define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
-#define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
-
-/* Bit 3 : Enable or disable RR[3] register. */
-#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
-#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
-#define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
-#define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
-
-/* Bit 2 : Enable or disable RR[2] register. */
-#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
-#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
-#define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
-#define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
-
-/* Bit 1 : Enable or disable RR[1] register. */
-#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
-#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
-#define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
-#define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
-
-/* Bit 0 : Enable or disable RR[0] register. */
-#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
-#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
-#define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
-#define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
-
-/* Register: WDT_CONFIG */
-/* Description: Configuration register. */
-
-/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
-#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
-#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
-#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
-#define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
-
-/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
-#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
-#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
-#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
-#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
-
-/* Register: WDT_RR */
-/* Description: Reload requests registers. */
-
-/* Bits 31..0 : Reload register. */
-#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
-#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
-#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
-
-/* Register: WDT_POWER */
-/* Description: Peripheral power control. */
-
-/* Bit 0 : Peripheral power control. */
-#define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
-#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
-#define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
-#define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
-
-
-/*lint --flb "Leave library region" */
-#endif

bsp/nrf51822/Libraries/nrf51822/Include/nrf51_deprecated.h

@@ -1,446 +0,0 @@
-/*
-
-Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-1. Redistributions of source code must retain the above copyright notice, this
-   list of conditions and the following disclaimer.
-
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-
-3. Neither the name of Nordic Semiconductor ASA nor the names of its
-   contributors may be used to endorse or promote products derived from this
-   software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
-
-*/
-
-#ifndef NRF51_DEPRECATED_H
-#define NRF51_DEPRECATED_H
-
-/*lint ++flb "Enter library region */
-
-/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and 
- * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these
- * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead.
- */
-
-/* NVMC */
-/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */
-#define ERASEPROTECTEDPAGE   ERASEPCR0
-
- 
-/* LPCOMP */
-/* The interrupt ISR was renamed. Adding old name to the macros. */
-#define LPCOMP_COMP_IRQHandler          LPCOMP_IRQHandler
-#define LPCOMP_COMP_IRQn                LPCOMP_IRQn
-/* Corrected typo in RESULT register. */
-#define LPCOMP_RESULT_RESULT_Bellow     LPCOMP_RESULT_RESULT_Below
- 
- 
-/* MPU */
-/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */
-#define MPU_PERR0_LPCOMP_COMP_Pos           MPU_PERR0_LPCOMP_Pos
-#define MPU_PERR0_LPCOMP_COMP_Msk           MPU_PERR0_LPCOMP_Msk
-#define MPU_PERR0_LPCOMP_COMP_InRegion1     MPU_PERR0_LPCOMP_InRegion1
-#define MPU_PERR0_LPCOMP_COMP_InRegion0     MPU_PERR0_LPCOMP_InRegion0
- 
- 
-/* POWER */
-/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
-#define POWER_RAMON_OFFRAM3_Pos         (19UL)                                  
-#define POWER_RAMON_OFFRAM3_Msk         (0x1UL << POWER_RAMON_OFFRAM3_Pos)      
-#define POWER_RAMON_OFFRAM3_RAM3Off     (0UL)                                   
-#define POWER_RAMON_OFFRAM3_RAM3On      (1UL)                                   
-/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
-#define POWER_RAMON_OFFRAM2_Pos         (18UL)                                  
-#define POWER_RAMON_OFFRAM2_Msk         (0x1UL << POWER_RAMON_OFFRAM2_Pos)      
-#define POWER_RAMON_OFFRAM2_RAM2Off     (0UL)                                   
-#define POWER_RAMON_OFFRAM2_RAM2On      (1UL)                                  
-/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
-#define POWER_RAMON_ONRAM3_Pos          (3UL)                                  
-#define POWER_RAMON_ONRAM3_Msk          (0x1UL << POWER_RAMON_ONRAM3_Pos)      
-#define POWER_RAMON_ONRAM3_RAM3Off      (0UL)                                  
-#define POWER_RAMON_ONRAM3_RAM3On       (1UL)                                  
-/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
-#define POWER_RAMON_ONRAM2_Pos          (2UL)                                  
-#define POWER_RAMON_ONRAM2_Msk          (0x1UL << POWER_RAMON_ONRAM2_Pos)       
-#define POWER_RAMON_ONRAM2_RAM2Off      (0UL)                                  
-#define POWER_RAMON_ONRAM2_RAM2On       (1UL)                                 
-
- 
-/* RADIO */
-/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */
-#define RADIO_TXPOWER_TXPOWER_Neg40dBm  RADIO_TXPOWER_TXPOWER_Neg30dBm      
-/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
-#define RADIO_CRCCNF_SKIP_ADDR_Pos      RADIO_CRCCNF_SKIPADDR_Pos 
-#define RADIO_CRCCNF_SKIP_ADDR_Msk      RADIO_CRCCNF_SKIPADDR_Msk 
-#define RADIO_CRCCNF_SKIP_ADDR_Include  RADIO_CRCCNF_SKIPADDR_Include 
-#define RADIO_CRCCNF_SKIP_ADDR_Skip     RADIO_CRCCNF_SKIPADDR_Skip 
-/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */
-#define RADIO_TEST_PLL_LOCK_Pos         RADIO_TEST_PLLLOCK_Pos 
-#define RADIO_TEST_PLL_LOCK_Msk         RADIO_TEST_PLLLOCK_Msk 
-#define RADIO_TEST_PLL_LOCK_Disabled    RADIO_TEST_PLLLOCK_Disabled 
-#define RADIO_TEST_PLL_LOCK_Enabled     RADIO_TEST_PLLLOCK_Enabled 
-/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */
-#define RADIO_TEST_CONST_CARRIER_Pos        RADIO_TEST_CONSTCARRIER_Pos 
-#define RADIO_TEST_CONST_CARRIER_Msk        RADIO_TEST_CONSTCARRIER_Msk 
-#define RADIO_TEST_CONST_CARRIER_Disabled   RADIO_TEST_CONSTCARRIER_Disabled 
-#define RADIO_TEST_CONST_CARRIER_Enabled    RADIO_TEST_CONSTCARRIER_Enabled 
-
-
-/* FICR */
-/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */
-#define SIZERAMBLOCK0   SIZERAMBLOCKS                   
-#define SIZERAMBLOCK1   SIZERAMBLOCKS                   
-#define SIZERAMBLOCK2   SIZERAMBLOCK[2]                 /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
-#define SIZERAMBLOCK3   SIZERAMBLOCK[3]                 /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
-/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
-#define DEVICEID0       DEVICEID[0]                     
-#define DEVICEID1       DEVICEID[1]                     
-/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
-#define ER0             ER[0]                           
-#define ER1             ER[1]                          
-#define ER2             ER[2]                       
-#define ER3             ER[3]                      
-/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
-#define IR0             IR[0]                         
-#define IR1             IR[1]                         
-#define IR2             IR[2]                         
-#define IR3             IR[3]                          
-/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
-#define DEVICEADDR0     DEVICEADDR[0]                  
-#define DEVICEADDR1     DEVICEADDR[1]                  
-
-
-/* PPI */
-/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
-#define TASKS_CHG0EN     TASKS_CHG[0].EN                    
-#define TASKS_CHG0DIS    TASKS_CHG[0].DIS                  
-#define TASKS_CHG1EN     TASKS_CHG[1].EN                    
-#define TASKS_CHG1DIS    TASKS_CHG[1].DIS                  
-#define TASKS_CHG2EN     TASKS_CHG[2].EN                   
-#define TASKS_CHG2DIS    TASKS_CHG[2].DIS                  
-#define TASKS_CHG3EN     TASKS_CHG[3].EN                    
-#define TASKS_CHG3DIS    TASKS_CHG[3].DIS                  
-/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
-#define CH0_EEP          CH[0].EEP                          
-#define CH0_TEP          CH[0].TEP                          
-#define CH1_EEP          CH[1].EEP                         
-#define CH1_TEP          CH[1].TEP                         
-#define CH2_EEP          CH[2].EEP                          
-#define CH2_TEP          CH[2].TEP                         
-#define CH3_EEP          CH[3].EEP                          
-#define CH3_TEP          CH[3].TEP                         
-#define CH4_EEP          CH[4].EEP                         
-#define CH4_TEP          CH[4].TEP                         
-#define CH5_EEP          CH[5].EEP                          
-#define CH5_TEP          CH[5].TEP                          
-#define CH6_EEP          CH[6].EEP                          
-#define CH6_TEP          CH[6].TEP                         
-#define CH7_EEP          CH[7].EEP                          
-#define CH7_TEP          CH[7].TEP                          
-#define CH8_EEP          CH[8].EEP                         
-#define CH8_TEP          CH[8].TEP                          
-#define CH9_EEP          CH[9].EEP                          
-#define CH9_TEP          CH[9].TEP                          
-#define CH10_EEP         CH[10].EEP                         
-#define CH10_TEP         CH[10].TEP                         
-#define CH11_EEP         CH[11].EEP                         
-#define CH11_TEP         CH[11].TEP                         
-#define CH12_EEP         CH[12].EEP                         
-#define CH12_TEP         CH[12].TEP                         
-#define CH13_EEP         CH[13].EEP                         
-#define CH13_TEP         CH[13].TEP                         
-#define CH14_EEP         CH[14].EEP                         
-#define CH14_TEP         CH[14].TEP                         
-#define CH15_EEP         CH[15].EEP                         
-#define CH15_TEP         CH[15].TEP                        
-/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
-#define CHG0             CHG[0]                            
-#define CHG1             CHG[1]                            
-#define CHG2             CHG[2]                             
-#define CHG3             CHG[3]                           
-/* All bitfield macros for the CHGx registers therefore changed name. */
-#define PPI_CHG0_CH15_Pos       PPI_CHG_CH15_Pos            
-#define PPI_CHG0_CH15_Msk       PPI_CHG_CH15_Msk            
-#define PPI_CHG0_CH15_Excluded  PPI_CHG_CH15_Excluded       
-#define PPI_CHG0_CH15_Included  PPI_CHG_CH15_Included       
-#define PPI_CHG0_CH14_Pos       PPI_CHG_CH14_Pos            
-#define PPI_CHG0_CH14_Msk       PPI_CHG_CH14_Msk           
-#define PPI_CHG0_CH14_Excluded  PPI_CHG_CH14_Excluded       
-#define PPI_CHG0_CH14_Included  PPI_CHG_CH14_Included       
-#define PPI_CHG0_CH13_Pos       PPI_CHG_CH13_Pos            
-#define PPI_CHG0_CH13_Msk       PPI_CHG_CH13_Msk            
-#define PPI_CHG0_CH13_Excluded  PPI_CHG_CH13_Excluded      
-#define PPI_CHG0_CH13_Included  PPI_CHG_CH13_Included       
-#define PPI_CHG0_CH12_Pos       PPI_CHG_CH12_Pos            
-#define PPI_CHG0_CH12_Msk       PPI_CHG_CH12_Msk            
-#define PPI_CHG0_CH12_Excluded  PPI_CHG_CH12_Excluded       
-#define PPI_CHG0_CH12_Included  PPI_CHG_CH12_Included       
-#define PPI_CHG0_CH11_Pos       PPI_CHG_CH11_Pos            
-#define PPI_CHG0_CH11_Msk       PPI_CHG_CH11_Msk            
-#define PPI_CHG0_CH11_Excluded  PPI_CHG_CH11_Excluded       
-#define PPI_CHG0_CH11_Included  PPI_CHG_CH11_Included       
-#define PPI_CHG0_CH10_Pos       PPI_CHG_CH10_Pos            
-#define PPI_CHG0_CH10_Msk       PPI_CHG_CH10_Msk            
-#define PPI_CHG0_CH10_Excluded  PPI_CHG_CH10_Excluded       
-#define PPI_CHG0_CH10_Included  PPI_CHG_CH10_Included       
-#define PPI_CHG0_CH9_Pos        PPI_CHG_CH9_Pos             
-#define PPI_CHG0_CH9_Msk        PPI_CHG_CH9_Msk             
-#define PPI_CHG0_CH9_Excluded   PPI_CHG_CH9_Excluded        
-#define PPI_CHG0_CH9_Included   PPI_CHG_CH9_Included        
-#define PPI_CHG0_CH8_Pos        PPI_CHG_CH8_Pos             
-#define PPI_CHG0_CH8_Msk        PPI_CHG_CH8_Msk             
-#define PPI_CHG0_CH8_Excluded   PPI_CHG_CH8_Excluded        
-#define PPI_CHG0_CH8_Included   PPI_CHG_CH8_Included        
-#define PPI_CHG0_CH7_Pos        PPI_CHG_CH7_Pos             
-#define PPI_CHG0_CH7_Msk        PPI_CHG_CH7_Msk             
-#define PPI_CHG0_CH7_Excluded   PPI_CHG_CH7_Excluded        
-#define PPI_CHG0_CH7_Included   PPI_CHG_CH7_Included        
-#define PPI_CHG0_CH6_Pos        PPI_CHG_CH6_Pos             
-#define PPI_CHG0_CH6_Msk        PPI_CHG_CH6_Msk             
-#define PPI_CHG0_CH6_Excluded   PPI_CHG_CH6_Excluded        
-#define PPI_CHG0_CH6_Included   PPI_CHG_CH6_Included        
-#define PPI_CHG0_CH5_Pos        PPI_CHG_CH5_Pos             
-#define PPI_CHG0_CH5_Msk        PPI_CHG_CH5_Msk             
-#define PPI_CHG0_CH5_Excluded   PPI_CHG_CH5_Excluded       
-#define PPI_CHG0_CH5_Included   PPI_CHG_CH5_Included        
-#define PPI_CHG0_CH4_Pos        PPI_CHG_CH4_Pos             
-#define PPI_CHG0_CH4_Msk        PPI_CHG_CH4_Msk             
-#define PPI_CHG0_CH4_Excluded   PPI_CHG_CH4_Excluded       
-#define PPI_CHG0_CH4_Included   PPI_CHG_CH4_Included       
-#define PPI_CHG0_CH3_Pos        PPI_CHG_CH3_Pos             
-#define PPI_CHG0_CH3_Msk        PPI_CHG_CH3_Msk            
-#define PPI_CHG0_CH3_Excluded   PPI_CHG_CH3_Excluded        
-#define PPI_CHG0_CH3_Included   PPI_CHG_CH3_Included       
-#define PPI_CHG0_CH2_Pos        PPI_CHG_CH2_Pos            
-#define PPI_CHG0_CH2_Msk        PPI_CHG_CH2_Msk             
-#define PPI_CHG0_CH2_Excluded   PPI_CHG_CH2_Excluded       
-#define PPI_CHG0_CH2_Included   PPI_CHG_CH2_Included       
-#define PPI_CHG0_CH1_Pos        PPI_CHG_CH1_Pos            
-#define PPI_CHG0_CH1_Msk        PPI_CHG_CH1_Msk            
-#define PPI_CHG0_CH1_Excluded   PPI_CHG_CH1_Excluded        
-#define PPI_CHG0_CH1_Included   PPI_CHG_CH1_Included       
-#define PPI_CHG0_CH0_Pos        PPI_CHG_CH0_Pos            
-#define PPI_CHG0_CH0_Msk        PPI_CHG_CH0_Msk            
-#define PPI_CHG0_CH0_Excluded   PPI_CHG_CH0_Excluded        
-#define PPI_CHG0_CH0_Included   PPI_CHG_CH0_Included       
-#define PPI_CHG1_CH15_Pos       PPI_CHG_CH15_Pos           
-#define PPI_CHG1_CH15_Msk       PPI_CHG_CH15_Msk           
-#define PPI_CHG1_CH15_Excluded  PPI_CHG_CH15_Excluded       
-#define PPI_CHG1_CH15_Included  PPI_CHG_CH15_Included      
-#define PPI_CHG1_CH14_Pos       PPI_CHG_CH14_Pos           
-#define PPI_CHG1_CH14_Msk       PPI_CHG_CH14_Msk            
-#define PPI_CHG1_CH14_Excluded  PPI_CHG_CH14_Excluded      
-#define PPI_CHG1_CH14_Included  PPI_CHG_CH14_Included       
-#define PPI_CHG1_CH13_Pos       PPI_CHG_CH13_Pos           
-#define PPI_CHG1_CH13_Msk       PPI_CHG_CH13_Msk            
-#define PPI_CHG1_CH13_Excluded  PPI_CHG_CH13_Excluded      
-#define PPI_CHG1_CH13_Included  PPI_CHG_CH13_Included      
-#define PPI_CHG1_CH12_Pos       PPI_CHG_CH12_Pos            
-#define PPI_CHG1_CH12_Msk       PPI_CHG_CH12_Msk           
-#define PPI_CHG1_CH12_Excluded  PPI_CHG_CH12_Excluded      
-#define PPI_CHG1_CH12_Included  PPI_CHG_CH12_Included      
-#define PPI_CHG1_CH11_Pos       PPI_CHG_CH11_Pos            
-#define PPI_CHG1_CH11_Msk       PPI_CHG_CH11_Msk           
-#define PPI_CHG1_CH11_Excluded  PPI_CHG_CH11_Excluded      
-#define PPI_CHG1_CH11_Included  PPI_CHG_CH11_Included      
-#define PPI_CHG1_CH10_Pos       PPI_CHG_CH10_Pos           
-#define PPI_CHG1_CH10_Msk       PPI_CHG_CH10_Msk            
-#define PPI_CHG1_CH10_Excluded  PPI_CHG_CH10_Excluded      
-#define PPI_CHG1_CH10_Included  PPI_CHG_CH10_Included      
-#define PPI_CHG1_CH9_Pos        PPI_CHG_CH9_Pos            
-#define PPI_CHG1_CH9_Msk        PPI_CHG_CH9_Msk            
-#define PPI_CHG1_CH9_Excluded   PPI_CHG_CH9_Excluded       
-#define PPI_CHG1_CH9_Included   PPI_CHG_CH9_Included       
-#define PPI_CHG1_CH8_Pos        PPI_CHG_CH8_Pos            
-#define PPI_CHG1_CH8_Msk        PPI_CHG_CH8_Msk            
-#define PPI_CHG1_CH8_Excluded   PPI_CHG_CH8_Excluded       
-#define PPI_CHG1_CH8_Included   PPI_CHG_CH8_Included       
-#define PPI_CHG1_CH7_Pos        PPI_CHG_CH7_Pos             
-#define PPI_CHG1_CH7_Msk        PPI_CHG_CH7_Msk            
-#define PPI_CHG1_CH7_Excluded   PPI_CHG_CH7_Excluded        
-#define PPI_CHG1_CH7_Included   PPI_CHG_CH7_Included       
-#define PPI_CHG1_CH6_Pos        PPI_CHG_CH6_Pos             
-#define PPI_CHG1_CH6_Msk        PPI_CHG_CH6_Msk            
-#define PPI_CHG1_CH6_Excluded   PPI_CHG_CH6_Excluded       
-#define PPI_CHG1_CH6_Included   PPI_CHG_CH6_Included       
-#define PPI_CHG1_CH5_Pos        PPI_CHG_CH5_Pos             
-#define PPI_CHG1_CH5_Msk        PPI_CHG_CH5_Msk             
-#define PPI_CHG1_CH5_Excluded   PPI_CHG_CH5_Excluded       
-#define PPI_CHG1_CH5_Included   PPI_CHG_CH5_Included        
-#define PPI_CHG1_CH4_Pos        PPI_CHG_CH4_Pos             
-#define PPI_CHG1_CH4_Msk        PPI_CHG_CH4_Msk             
-#define PPI_CHG1_CH4_Excluded   PPI_CHG_CH4_Excluded        
-#define PPI_CHG1_CH4_Included   PPI_CHG_CH4_Included        
-#define PPI_CHG1_CH3_Pos        PPI_CHG_CH3_Pos            
-#define PPI_CHG1_CH3_Msk        PPI_CHG_CH3_Msk             
-#define PPI_CHG1_CH3_Excluded   PPI_CHG_CH3_Excluded        
-#define PPI_CHG1_CH3_Included   PPI_CHG_CH3_Included       
-#define PPI_CHG1_CH2_Pos        PPI_CHG_CH2_Pos            
-#define PPI_CHG1_CH2_Msk        PPI_CHG_CH2_Msk             
-#define PPI_CHG1_CH2_Excluded   PPI_CHG_CH2_Excluded        
-#define PPI_CHG1_CH2_Included   PPI_CHG_CH2_Included        
-#define PPI_CHG1_CH1_Pos        PPI_CHG_CH1_Pos             
-#define PPI_CHG1_CH1_Msk        PPI_CHG_CH1_Msk            
-#define PPI_CHG1_CH1_Excluded   PPI_CHG_CH1_Excluded        
-#define PPI_CHG1_CH1_Included   PPI_CHG_CH1_Included       
-#define PPI_CHG1_CH0_Pos        PPI_CHG_CH0_Pos             
-#define PPI_CHG1_CH0_Msk        PPI_CHG_CH0_Msk            
-#define PPI_CHG1_CH0_Excluded   PPI_CHG_CH0_Excluded       
-#define PPI_CHG1_CH0_Included   PPI_CHG_CH0_Included       
-#define PPI_CHG2_CH15_Pos       PPI_CHG_CH15_Pos           
-#define PPI_CHG2_CH15_Msk       PPI_CHG_CH15_Msk            
-#define PPI_CHG2_CH15_Excluded  PPI_CHG_CH15_Excluded      
-#define PPI_CHG2_CH15_Included  PPI_CHG_CH15_Included      
-#define PPI_CHG2_CH14_Pos       PPI_CHG_CH14_Pos           
-#define PPI_CHG2_CH14_Msk       PPI_CHG_CH14_Msk           
-#define PPI_CHG2_CH14_Excluded  PPI_CHG_CH14_Excluded       
-#define PPI_CHG2_CH14_Included  PPI_CHG_CH14_Included      
-#define PPI_CHG2_CH13_Pos       PPI_CHG_CH13_Pos           
-#define PPI_CHG2_CH13_Msk       PPI_CHG_CH13_Msk            
-#define PPI_CHG2_CH13_Excluded  PPI_CHG_CH13_Excluded       
-#define PPI_CHG2_CH13_Included  PPI_CHG_CH13_Included      
-#define PPI_CHG2_CH12_Pos       PPI_CHG_CH12_Pos            
-#define PPI_CHG2_CH12_Msk       PPI_CHG_CH12_Msk            
-#define PPI_CHG2_CH12_Excluded  PPI_CHG_CH12_Excluded      
-#define PPI_CHG2_CH12_Included  PPI_CHG_CH12_Included       
-#define PPI_CHG2_CH11_Pos       PPI_CHG_CH11_Pos           
-#define PPI_CHG2_CH11_Msk       PPI_CHG_CH11_Msk           
-#define PPI_CHG2_CH11_Excluded  PPI_CHG_CH11_Excluded       
-#define PPI_CHG2_CH11_Included  PPI_CHG_CH11_Included       
-#define PPI_CHG2_CH10_Pos       PPI_CHG_CH10_Pos            
-#define PPI_CHG2_CH10_Msk       PPI_CHG_CH10_Msk            
-#define PPI_CHG2_CH10_Excluded  PPI_CHG_CH10_Excluded      
-#define PPI_CHG2_CH10_Included  PPI_CHG_CH10_Included      
-#define PPI_CHG2_CH9_Pos        PPI_CHG_CH9_Pos            
-#define PPI_CHG2_CH9_Msk        PPI_CHG_CH9_Msk            
-#define PPI_CHG2_CH9_Excluded   PPI_CHG_CH9_Excluded        
-#define PPI_CHG2_CH9_Included   PPI_CHG_CH9_Included       
-#define PPI_CHG2_CH8_Pos        PPI_CHG_CH8_Pos            
-#define PPI_CHG2_CH8_Msk        PPI_CHG_CH8_Msk            
-#define PPI_CHG2_CH8_Excluded   PPI_CHG_CH8_Excluded       
-#define PPI_CHG2_CH8_Included   PPI_CHG_CH8_Included        
-#define PPI_CHG2_CH7_Pos        PPI_CHG_CH7_Pos            
-#define PPI_CHG2_CH7_Msk        PPI_CHG_CH7_Msk            
-#define PPI_CHG2_CH7_Excluded   PPI_CHG_CH7_Excluded       
-#define PPI_CHG2_CH7_Included   PPI_CHG_CH7_Included       
-#define PPI_CHG2_CH6_Pos        PPI_CHG_CH6_Pos            
-#define PPI_CHG2_CH6_Msk        PPI_CHG_CH6_Msk            
-#define PPI_CHG2_CH6_Excluded   PPI_CHG_CH6_Excluded       
-#define PPI_CHG2_CH6_Included   PPI_CHG_CH6_Included       
-#define PPI_CHG2_CH5_Pos        PPI_CHG_CH5_Pos            
-#define PPI_CHG2_CH5_Msk        PPI_CHG_CH5_Msk            
-#define PPI_CHG2_CH5_Excluded   PPI_CHG_CH5_Excluded       
-#define PPI_CHG2_CH5_Included   PPI_CHG_CH5_Included        
-#define PPI_CHG2_CH4_Pos        PPI_CHG_CH4_Pos             
-#define PPI_CHG2_CH4_Msk        PPI_CHG_CH4_Msk             
-#define PPI_CHG2_CH4_Excluded   PPI_CHG_CH4_Excluded        
-#define PPI_CHG2_CH4_Included   PPI_CHG_CH4_Included       
-#define PPI_CHG2_CH3_Pos        PPI_CHG_CH3_Pos            
-#define PPI_CHG2_CH3_Msk        PPI_CHG_CH3_Msk            
-#define PPI_CHG2_CH3_Excluded   PPI_CHG_CH3_Excluded       
-#define PPI_CHG2_CH3_Included   PPI_CHG_CH3_Included       
-#define PPI_CHG2_CH2_Pos        PPI_CHG_CH2_Pos            
-#define PPI_CHG2_CH2_Msk        PPI_CHG_CH2_Msk           
-#define PPI_CHG2_CH2_Excluded   PPI_CHG_CH2_Excluded       
-#define PPI_CHG2_CH2_Included   PPI_CHG_CH2_Included       
-#define PPI_CHG2_CH1_Pos        PPI_CHG_CH1_Pos             
-#define PPI_CHG2_CH1_Msk        PPI_CHG_CH1_Msk             
-#define PPI_CHG2_CH1_Excluded   PPI_CHG_CH1_Excluded       
-#define PPI_CHG2_CH1_Included   PPI_CHG_CH1_Included       
-#define PPI_CHG2_CH0_Pos        PPI_CHG_CH0_Pos            
-#define PPI_CHG2_CH0_Msk        PPI_CHG_CH0_Msk            
-#define PPI_CHG2_CH0_Excluded   PPI_CHG_CH0_Excluded       
-#define PPI_CHG2_CH0_Included   PPI_CHG_CH0_Included        
-#define PPI_CHG3_CH15_Pos       PPI_CHG_CH15_Pos           
-#define PPI_CHG3_CH15_Msk       PPI_CHG_CH15_Msk           
-#define PPI_CHG3_CH15_Excluded  PPI_CHG_CH15_Excluded     
-#define PPI_CHG3_CH15_Included  PPI_CHG_CH15_Included      
-#define PPI_CHG3_CH14_Pos       PPI_CHG_CH14_Pos          
-#define PPI_CHG3_CH14_Msk       PPI_CHG_CH14_Msk           
-#define PPI_CHG3_CH14_Excluded  PPI_CHG_CH14_Excluded      
-#define PPI_CHG3_CH14_Included  PPI_CHG_CH14_Included       
-#define PPI_CHG3_CH13_Pos       PPI_CHG_CH13_Pos           
-#define PPI_CHG3_CH13_Msk       PPI_CHG_CH13_Msk            
-#define PPI_CHG3_CH13_Excluded  PPI_CHG_CH13_Excluded      
-#define PPI_CHG3_CH13_Included  PPI_CHG_CH13_Included      
-#define PPI_CHG3_CH12_Pos       PPI_CHG_CH12_Pos            
-#define PPI_CHG3_CH12_Msk       PPI_CHG_CH12_Msk            
-#define PPI_CHG3_CH12_Excluded  PPI_CHG_CH12_Excluded       
-#define PPI_CHG3_CH12_Included  PPI_CHG_CH12_Included       
-#define PPI_CHG3_CH11_Pos       PPI_CHG_CH11_Pos            
-#define PPI_CHG3_CH11_Msk       PPI_CHG_CH11_Msk            
-#define PPI_CHG3_CH11_Excluded  PPI_CHG_CH11_Excluded      
-#define PPI_CHG3_CH11_Included  PPI_CHG_CH11_Included       
-#define PPI_CHG3_CH10_Pos       PPI_CHG_CH10_Pos            
-#define PPI_CHG3_CH10_Msk       PPI_CHG_CH10_Msk            
-#define PPI_CHG3_CH10_Excluded  PPI_CHG_CH10_Excluded      
-#define PPI_CHG3_CH10_Included  PPI_CHG_CH10_Included      
-#define PPI_CHG3_CH9_Pos        PPI_CHG_CH9_Pos            
-#define PPI_CHG3_CH9_Msk        PPI_CHG_CH9_Msk            
-#define PPI_CHG3_CH9_Excluded   PPI_CHG_CH9_Excluded       
-#define PPI_CHG3_CH9_Included   PPI_CHG_CH9_Included       
-#define PPI_CHG3_CH8_Pos        PPI_CHG_CH8_Pos            
-#define PPI_CHG3_CH8_Msk        PPI_CHG_CH8_Msk             
-#define PPI_CHG3_CH8_Excluded   PPI_CHG_CH8_Excluded       
-#define PPI_CHG3_CH8_Included   PPI_CHG_CH8_Included       
-#define PPI_CHG3_CH7_Pos        PPI_CHG_CH7_Pos             
-#define PPI_CHG3_CH7_Msk        PPI_CHG_CH7_Msk            
-#define PPI_CHG3_CH7_Excluded   PPI_CHG_CH7_Excluded        
-#define PPI_CHG3_CH7_Included   PPI_CHG_CH7_Included       
-#define PPI_CHG3_CH6_Pos        PPI_CHG_CH6_Pos             
-#define PPI_CHG3_CH6_Msk        PPI_CHG_CH6_Msk             
-#define PPI_CHG3_CH6_Excluded   PPI_CHG_CH6_Excluded       
-#define PPI_CHG3_CH6_Included   PPI_CHG_CH6_Included        
-#define PPI_CHG3_CH5_Pos        PPI_CHG_CH5_Pos             
-#define PPI_CHG3_CH5_Msk        PPI_CHG_CH5_Msk             
-#define PPI_CHG3_CH5_Excluded   PPI_CHG_CH5_Excluded        
-#define PPI_CHG3_CH5_Included   PPI_CHG_CH5_Included       
-#define PPI_CHG3_CH4_Pos        PPI_CHG_CH4_Pos             
-#define PPI_CHG3_CH4_Msk        PPI_CHG_CH4_Msk            
-#define PPI_CHG3_CH4_Excluded   PPI_CHG_CH4_Excluded        
-#define PPI_CHG3_CH4_Included   PPI_CHG_CH4_Included        
-#define PPI_CHG3_CH3_Pos        PPI_CHG_CH3_Pos             
-#define PPI_CHG3_CH3_Msk        PPI_CHG_CH3_Msk            
-#define PPI_CHG3_CH3_Excluded   PPI_CHG_CH3_Excluded        
-#define PPI_CHG3_CH3_Included   PPI_CHG_CH3_Included        
-#define PPI_CHG3_CH2_Pos        PPI_CHG_CH2_Pos             
-#define PPI_CHG3_CH2_Msk        PPI_CHG_CH2_Msk             
-#define PPI_CHG3_CH2_Excluded   PPI_CHG_CH2_Excluded        
-#define PPI_CHG3_CH2_Included   PPI_CHG_CH2_Included       
-#define PPI_CHG3_CH1_Pos        PPI_CHG_CH1_Pos             
-#define PPI_CHG3_CH1_Msk        PPI_CHG_CH1_Msk             
-#define PPI_CHG3_CH1_Excluded   PPI_CHG_CH1_Excluded        
-#define PPI_CHG3_CH1_Included   PPI_CHG_CH1_Included        
-#define PPI_CHG3_CH0_Pos        PPI_CHG_CH0_Pos             
-#define PPI_CHG3_CH0_Msk        PPI_CHG_CH0_Msk             
-#define PPI_CHG3_CH0_Excluded   PPI_CHG_CH0_Excluded        
-#define PPI_CHG3_CH0_Included   PPI_CHG_CH0_Included      
-
-/* SPIS */
-/* nRF51 devices do not have an SPIS0, only SPIS1. SPIS0_EASYDMA_MAXCNT_SIZE was therefore renamed. */
-#define SPIS0_EASYDMA_MAXCNT_SIZE SPIS1_EASYDMA_MAXCNT_SIZE  
-
-
-
-/*lint --flb "Leave library region" */
-
-#endif /* NRF51_DEPRECATED_H */
-

bsp/nrf51822/Libraries/nrf51822/Include/nrf_gpio.h

@@ -1,422 +0,0 @@
-#ifndef NRF_GPIO_H__
-#define NRF_GPIO_H__
-
-#include "nrf51.h"
-#include "nrf51_bitfields.h"
-
-/**
- * @defgroup nrf_gpio GPIO abstraction
- * @{
- * @ingroup nrf_drivers
- * @brief GPIO pin abstraction and port abstraction for reading and writing byte-wise to GPIO ports.
- *
- * Here, the GPIO ports are defined as follows:
- * - Port 0 -> pin 0-7
- * - Port 1 -> pin 8-15
- * - Port 2 -> pin 16-23
- * - Port 3 -> pin 24-31
- */
-
-/**
- * @enum nrf_gpio_port_dir_t
- * @brief Enumerator used for setting the direction of a GPIO port.
- */
-typedef enum
-{
-    NRF_GPIO_PORT_DIR_OUTPUT,       ///<  Output
-    NRF_GPIO_PORT_DIR_INPUT         ///<  Input
-} nrf_gpio_port_dir_t;
-
-/**
- * @enum nrf_gpio_pin_dir_t
- * Pin direction definitions.
- */
-typedef enum
-{
-    NRF_GPIO_PIN_DIR_INPUT,   ///< Input
-    NRF_GPIO_PIN_DIR_OUTPUT   ///< Output
-} nrf_gpio_pin_dir_t;
-
-/**
- * @enum nrf_gpio_port_select_t
- * @brief Enumerator used for selecting between port 0 - 3.
- */
-typedef enum
-{
-    NRF_GPIO_PORT_SELECT_PORT0 = 0,           ///<  Port 0 (GPIO pin 0-7)
-    NRF_GPIO_PORT_SELECT_PORT1,               ///<  Port 1 (GPIO pin 8-15)
-    NRF_GPIO_PORT_SELECT_PORT2,               ///<  Port 2 (GPIO pin 16-23)
-    NRF_GPIO_PORT_SELECT_PORT3,               ///<  Port 3 (GPIO pin 24-31)
-} nrf_gpio_port_select_t;
-
-/**
- * @enum nrf_gpio_pin_pull_t
- * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin configuration
- */
-typedef enum
-{
-    NRF_GPIO_PIN_NOPULL   = GPIO_PIN_CNF_PULL_Disabled,                 ///<  Pin pullup resistor disabled
-    NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown,                 ///<  Pin pulldown resistor enabled
-    NRF_GPIO_PIN_PULLUP   = GPIO_PIN_CNF_PULL_Pullup,                   ///<  Pin pullup resistor enabled
-} nrf_gpio_pin_pull_t;
-
-/**
- * @enum nrf_gpio_pin_sense_t
- * @brief Enumerator used for selecting the pin to sense high or low level on the pin input.
- */
-typedef enum
-{
-    NRF_GPIO_PIN_NOSENSE    = GPIO_PIN_CNF_SENSE_Disabled,              ///<  Pin sense level disabled.
-    NRF_GPIO_PIN_SENSE_LOW  = GPIO_PIN_CNF_SENSE_Low,                   ///<  Pin sense low level.
-    NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High,                  ///<  Pin sense high level.
-} nrf_gpio_pin_sense_t;
-
-/**
- * @brief Function for configuring the GPIO pin range as outputs with normal drive strength.
- *        This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
- *
- * @param pin_range_start specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
- *
- * @param pin_range_end specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
- *
- * @note For configuring only one pin as output use @ref nrf_gpio_cfg_output
- *       Sense capability on the pin is disabled, and input is disconnected from the buffer as the pins are configured as output.
- */
-static __INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end)
-{
-    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
-    for (; pin_range_start <= pin_range_end; pin_range_start++)
-    {
-        NRF_GPIO->PIN_CNF[pin_range_start] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
-                                        | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
-                                        | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
-                                        | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
-                                        | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
-    }
-}
-
-/**
- * @brief Function for configuring the GPIO pin range as inputs with given initial value set, hiding inner details.
- *        This function can be used to configure pin range as simple input.
- *
- * @param pin_range_start specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
- *
- * @param pin_range_end specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
- *
- * @param pull_config State of the pin range pull resistor (no pull, pulled down or pulled high)
- *
- * @note  For configuring only one pin as input use @ref nrf_gpio_cfg_input
- *        Sense capability on the pin is disabled, and input is connected to buffer so that the GPIO->IN register is readable
- */
-static __INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, uint32_t pin_range_end, nrf_gpio_pin_pull_t pull_config)
-{
-    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
-    for (; pin_range_start <= pin_range_end; pin_range_start++)
-    {
-        NRF_GPIO->PIN_CNF[pin_range_start] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
-                                        | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
-                                        | (pull_config << GPIO_PIN_CNF_PULL_Pos)
-                                        | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
-                                        | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
-    }
-}
-
-/**
- * @brief Function for configuring the given GPIO pin number as output with given initial value set, hiding inner details.
- *        This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
- *
- * @param pin_number specifies the pin number of gpio pin numbers to be configured (allowed values 0-30)
- *
- * @note  Sense capability on the pin is disabled, and input is disconnected from the buffer as the pins are configured as output.
- */
-static __INLINE void nrf_gpio_cfg_output(uint32_t pin_number)
-{
-    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
-    NRF_GPIO->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
-                                            | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
-                                            | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
-                                            | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos)
-                                            | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
-}
-
-/**
- * @brief Function for configuring the given GPIO pin number as input with given initial value set, hiding inner details.
- *        This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
- *
- * @param pin_number specifies the pin number of gpio pin numbers to be configured (allowed values 0-30)
- *
- * @param pull_config State of the pin range pull resistor (no pull, pulled down or pulled high)
- *
- * @note  Sense capability on the pin is disabled, and input is connected to buffer so that the GPIO->IN register is readable
- */
-static __INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config)
-{
-    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
-    NRF_GPIO->PIN_CNF[pin_number] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
-                                        | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
-                                        | (pull_config << GPIO_PIN_CNF_PULL_Pos)
-                                        | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
-                                        | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
-}
-
-/**
- * @brief Function for configuring the given GPIO pin number as input with given initial value set, hiding inner details.
- *        This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
- *        Sense capability on the pin is configurable, and input is connected to buffer so that the GPIO->IN register is readable.
- *
- * @param pin_number specifies the pin number of gpio pin numbers to be configured (allowed values 0-30).
- *
- * @param pull_config state of the pin pull resistor (no pull, pulled down or pulled high).
- *
- * @param sense_config sense level of the pin (no sense, sense low or sense high).
- */
-static __INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config, nrf_gpio_pin_sense_t sense_config)
-{
-    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
-    NRF_GPIO->PIN_CNF[pin_number] = (sense_config << GPIO_PIN_CNF_SENSE_Pos)
-                                        | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
-                                        | (pull_config << GPIO_PIN_CNF_PULL_Pos)
-                                        | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
-                                        | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
-}
-
-/**
- * @brief Function for setting the direction for a GPIO pin.
- *
- * @param pin_number specifies the pin number [0:31] for which to
- * set the direction.
- *
- * @param direction specifies the direction
- */
-static __INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction)
-{
-    if(direction == NRF_GPIO_PIN_DIR_INPUT)
-    {
-        NRF_GPIO->PIN_CNF[pin_number] =
-          (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
-        | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
-        | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
-        | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
-        | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
-    }
-    else
-    {
-        NRF_GPIO->DIRSET = (1UL << pin_number);
-    }
-}
-
-/**
- * @brief Function for setting a GPIO pin.
- *
- * Note that the pin must be configured as an output for this
- * function to have any effect.
- *
- * @param pin_number specifies the pin number [0:31] to
- * set.
- */
-static __INLINE void nrf_gpio_pin_set(uint32_t pin_number)
-{
-    NRF_GPIO->OUTSET = (1UL << pin_number);
-}
-
-/**
- * @brief Function for clearing a GPIO pin.
- *
- * Note that the pin must be configured as an output for this
- * function to have any effect.
- *
- * @param pin_number specifies the pin number [0:31] to
- * clear.
- */
-static __INLINE void nrf_gpio_pin_clear(uint32_t pin_number)
-{
-    NRF_GPIO->OUTCLR = (1UL << pin_number);
-}
-
-/**
- * @brief Function for toggling a GPIO pin.
- *
- * Note that the pin must be configured as an output for this
- * function to have any effect.
- *
- * @param pin_number specifies the pin number [0:31] to
- * toggle.
- */
-static __INLINE void nrf_gpio_pin_toggle(uint32_t pin_number)
-{
-    const uint32_t pin_bit   = 1UL << pin_number;
-    const uint32_t pin_state = ((NRF_GPIO->OUT >> pin_number) & 1UL);
-    
-    if (pin_state == 0)
-    {
-        // Current state low, set high.
-        NRF_GPIO->OUTSET = pin_bit;        
-    }
-    else
-    {
-        // Current state high, set low.    
-        NRF_GPIO->OUTCLR = pin_bit;       
-    }
-}
-
-/**
- * @brief Function for writing a value to a GPIO pin.
- *
- * Note that the pin must be configured as an output for this
- * function to have any effect.
- *
- * @param pin_number specifies the pin number [0:31] to
- * write.
- *
- * @param value specifies the value to be written to the pin.
- * @arg 0 clears the pin
- * @arg >=1 sets the pin.
- */
-static __INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value)
-{
-    if (value == 0)
-    {
-        nrf_gpio_pin_clear(pin_number);
-    }
-    else
-    {
-        nrf_gpio_pin_set(pin_number);
-    }
-}
-
-/**
- * @brief Function for reading the input level of a GPIO pin.
- *
- * Note that the pin must have input connected for the value
- * returned from this function to be valid.
- *
- * @param pin_number specifies the pin number [0:31] to
- * read.
- *
- * @return
- * @retval 0 if the pin input level is low.
- * @retval 1 if the pin input level is high.
- * @retval > 1 should never occur.
- */
-static __INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number)
-{
-    return  ((NRF_GPIO->IN >> pin_number) & 1UL);
-}
-
-/**
- * @brief Generic function for writing a single byte of a 32 bit word at a given
- * address.
- *
- * This function should not be called from outside the nrf_gpio
- * abstraction layer.
- *
- * @param word_address is the address of the word to be written.
- *
- * @param byte_no is the the word byte number (0-3) to be written.
- *
- * @param value is the value to be written to byte "byte_no" of word
- * at address "word_address"
- */
-static __INLINE void nrf_gpio_word_byte_write(volatile uint32_t * word_address, uint8_t byte_no, uint8_t value)
-{
-    *((volatile uint8_t*)(word_address) + byte_no) = value;
-}
-
-/**
- * @brief Generic function for reading a single byte of a 32 bit word at a given
- * address.
- *
- * This function should not be called from outside the nrf_gpio
- * abstraction layer.
- *
- * @param word_address is the address of the word to be read.
- *
- * @param byte_no is the the byte number (0-3) of the word to be read.
- *
- * @return byte "byte_no" of word at address "word_address".
- */
-static __INLINE uint8_t nrf_gpio_word_byte_read(const volatile uint32_t* word_address, uint8_t byte_no)
-{
-    return (*((const volatile uint8_t*)(word_address) + byte_no));
-}
-
-/**
- * @brief Function for setting the direction of a port.
- *
- * @param port is the port for which to set the direction.
- *
- * @param dir direction to be set for this port.
- */
-static __INLINE void nrf_gpio_port_dir_set(nrf_gpio_port_select_t port, nrf_gpio_port_dir_t dir)
-{
-    if (dir == NRF_GPIO_PORT_DIR_OUTPUT)
-    {
-        nrf_gpio_word_byte_write(&NRF_GPIO->DIRSET, port, 0xFF);
-    }
-    else
-    {
-        nrf_gpio_range_cfg_input(port*8, (port+1)*8-1, NRF_GPIO_PIN_NOPULL);
-    }
-}
-
-/**
- * @brief Function for reading a GPIO port.
- *
- * @param port is the port to read.
- *
- * @return the input value on this port.
- */
-static __INLINE uint8_t nrf_gpio_port_read(nrf_gpio_port_select_t port)
-{
-    return nrf_gpio_word_byte_read(&NRF_GPIO->IN, port);
-}
-
-/**
- * @brief Function for writing to a GPIO port.
- *
- * @param port is the port to write.
- *
- * @param value is the value to write to this port.
- *
- * @sa nrf_gpio_port_dir_set()
- */
-static __INLINE void nrf_gpio_port_write(nrf_gpio_port_select_t port, uint8_t value)
-{
-    nrf_gpio_word_byte_write(&NRF_GPIO->OUT, port, value);
-}
-
-/**
- * @brief Function for setting individual pins on GPIO port.
- *
- * @param port is the port for which to set the pins.
- *
- * @param set_mask is a mask specifying which pins to set. A bit
- * set to 1 indicates that the corresponding port pin shall be
- * set.
- *
- * @sa nrf_gpio_port_dir_set()
- */
-static __INLINE void nrf_gpio_port_set(nrf_gpio_port_select_t port, uint8_t set_mask)
-{
-    nrf_gpio_word_byte_write(&NRF_GPIO->OUTSET, port, set_mask);
-}
-
-/**
- * @brief Function for clearing individual pins on GPIO port.
- *
- * @param port is the port for which to clear the pins.
- *
- * @param clr_mask is a mask specifying which pins to clear. A bit
- * set to 1 indicates that the corresponding port pin shall be
- * cleared.
- *
- * @sa nrf_gpio_port_dir_set()
- */
-static __INLINE void nrf_gpio_port_clear(nrf_gpio_port_select_t port, uint8_t clr_mask)
-{
-    nrf_gpio_word_byte_write(&NRF_GPIO->OUTCLR, port, clr_mask);
-}
-
-/** @} */
-
-#endif

bsp/nrf51822/Libraries/nrf51822/Include/system_nrf51.h

@@ -1,61 +0,0 @@
-/*
-
-Copyright (c) 2009-2021 ARM Limited. All rights reserved.
-
-    SPDX-License-Identifier: Apache-2.0
-
-Licensed under the Apache License, Version 2.0 (the License); you may
-not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an AS IS BASIS, WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-NOTICE: This file has been modified by Nordic Semiconductor ASA.
-
-*/
-
-#ifndef SYSTEM_NRF51_H
-#define SYSTEM_NRF51_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-
-extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock)  */
-
-/**
- * Initialize the system
- *
- * @param  none
- * @return none
- *
- * @brief  Setup the microcontroller system.
- *         Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param  none
- * @return none
- *
- * @brief  Updates the SystemCoreClock with current core Clock
- *         retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* SYSTEM_NRF51_H */

bsp/nrf51822/Libraries/nrf51822/Source/templates/arm/arm_startup_nrf51.s

@@ -1,261 +0,0 @@
-; Copyright (c) 2009-2021 ARM Limited. All rights reserved.
-; 
-;     SPDX-License-Identifier: Apache-2.0
-; 
-; Licensed under the Apache License, Version 2.0 (the License); you may
-; not use this file except in compliance with the License.
-; You may obtain a copy of the License at
-; 
-;     www.apache.org/licenses/LICENSE-2.0
-; 
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an AS IS BASIS, WITHOUT
-; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-; 
-; NOTICE: This file has been modified by Nordic Semiconductor ASA.
-
-                IF :DEF: __STARTUP_CONFIG
-#ifdef  __STARTUP_CONFIG
-#include "startup_config.h"
-#ifndef __STARTUP_CONFIG_STACK_ALIGNEMENT
-#define __STARTUP_CONFIG_STACK_ALIGNEMENT 3
-#endif
-#endif
-                ENDIF
-
-                IF :DEF: __STARTUP_CONFIG
-Stack_Size      EQU __STARTUP_CONFIG_STACK_SIZE
-                ELIF :DEF: __STACK_SIZE
-Stack_Size      EQU __STACK_SIZE
-                ELSE
-Stack_Size      EQU 2048
-                ENDIF
-                
-                IF :DEF: __STARTUP_CONFIG
-Stack_Align     EQU __STARTUP_CONFIG_STACK_ALIGNEMENT
-                ELSE
-Stack_Align     EQU 3
-                ENDIF
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=Stack_Align
-Stack_Mem       SPACE   Stack_Size
-__initial_sp
-
-                IF :DEF: __STARTUP_CONFIG
-Heap_Size       EQU __STARTUP_CONFIG_HEAP_SIZE
-                ELIF :DEF: __HEAP_SIZE
-Heap_Size       EQU __HEAP_SIZE
-                ELSE
-Heap_Size       EQU 2048
-                ENDIF
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit
-
-                PRESERVE8
-                THUMB
-
-; Vector Table Mapped to Address 0 at Reset
-
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler
-                DCD     NMI_Handler
-                DCD     HardFault_Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler
-                DCD     SysTick_Handler
-
-                ; External Interrupts
-                DCD     POWER_CLOCK_IRQHandler
-                DCD     RADIO_IRQHandler
-                DCD     UART0_IRQHandler
-                DCD     SPI0_TWI0_IRQHandler
-                DCD     SPI1_TWI1_IRQHandler
-                DCD     0                         ; Reserved
-                DCD     GPIOTE_IRQHandler
-                DCD     ADC_IRQHandler
-                DCD     TIMER0_IRQHandler
-                DCD     TIMER1_IRQHandler
-                DCD     TIMER2_IRQHandler
-                DCD     RTC0_IRQHandler
-                DCD     TEMP_IRQHandler
-                DCD     RNG_IRQHandler
-                DCD     ECB_IRQHandler
-                DCD     CCM_AAR_IRQHandler
-                DCD     WDT_IRQHandler
-                DCD     RTC1_IRQHandler
-                DCD     QDEC_IRQHandler
-                DCD     LPCOMP_IRQHandler
-                DCD     SWI0_IRQHandler
-                DCD     SWI1_IRQHandler
-                DCD     SWI2_IRQHandler
-                DCD     SWI3_IRQHandler
-                DCD     SWI4_IRQHandler
-                DCD     SWI5_IRQHandler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-
-__Vectors_End
-
-__Vectors_Size  EQU     __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset Handler
-
-NRF_POWER_RAMON_ADDRESS              EQU   0x40000524  ; NRF_POWER->RAMON address
-NRF_POWER_RAMONB_ADDRESS             EQU   0x40000554  ; NRF_POWER->RAMONB address
-NRF_POWER_RAMONx_RAMxON_ONMODE_Msk   EQU   0x3         ; All RAM blocks on in onmode bit mask
-
-Reset_Handler   PROC
-                EXPORT  Reset_Handler             [WEAK]
-                IMPORT  SystemInit
-                IMPORT  __main
-
-                                MOVS    R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
-                
-                LDR     R0, =NRF_POWER_RAMON_ADDRESS
-                LDR     R2, [R0]
-                ORRS    R2, R2, R1
-                STR     R2, [R0]
-                
-                LDR     R0, =NRF_POWER_RAMONB_ADDRESS
-                LDR     R2, [R0]
-                ORRS    R2, R2, R1
-                STR     R2, [R0]
-
-                LDR     R0, =SystemInit
-                BLX     R0
-                LDR     R0, =__main
-                BX      R0
-                ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler               [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler            [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler           [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT   POWER_CLOCK_IRQHandler [WEAK]
-                EXPORT   RADIO_IRQHandler [WEAK]
-                EXPORT   UART0_IRQHandler [WEAK]
-                EXPORT   SPI0_TWI0_IRQHandler [WEAK]
-                EXPORT   SPI1_TWI1_IRQHandler [WEAK]
-                EXPORT   GPIOTE_IRQHandler [WEAK]
-                EXPORT   ADC_IRQHandler [WEAK]
-                EXPORT   TIMER0_IRQHandler [WEAK]
-                EXPORT   TIMER1_IRQHandler [WEAK]
-                EXPORT   TIMER2_IRQHandler [WEAK]
-                EXPORT   RTC0_IRQHandler [WEAK]
-                EXPORT   TEMP_IRQHandler [WEAK]
-                EXPORT   RNG_IRQHandler [WEAK]
-                EXPORT   ECB_IRQHandler [WEAK]
-                EXPORT   CCM_AAR_IRQHandler [WEAK]
-                EXPORT   WDT_IRQHandler [WEAK]
-                EXPORT   RTC1_IRQHandler [WEAK]
-                EXPORT   QDEC_IRQHandler [WEAK]
-                EXPORT   LPCOMP_IRQHandler [WEAK]
-                EXPORT   SWI0_IRQHandler [WEAK]
-                EXPORT   SWI1_IRQHandler [WEAK]
-                EXPORT   SWI2_IRQHandler [WEAK]
-                EXPORT   SWI3_IRQHandler [WEAK]
-                EXPORT   SWI4_IRQHandler [WEAK]
-                EXPORT   SWI5_IRQHandler [WEAK]
-POWER_CLOCK_IRQHandler
-RADIO_IRQHandler
-UART0_IRQHandler
-SPI0_TWI0_IRQHandler
-SPI1_TWI1_IRQHandler
-GPIOTE_IRQHandler
-ADC_IRQHandler
-TIMER0_IRQHandler
-TIMER1_IRQHandler
-TIMER2_IRQHandler
-RTC0_IRQHandler
-TEMP_IRQHandler
-RNG_IRQHandler
-ECB_IRQHandler
-CCM_AAR_IRQHandler
-WDT_IRQHandler
-RTC1_IRQHandler
-QDEC_IRQHandler
-LPCOMP_IRQHandler
-SWI0_IRQHandler
-SWI1_IRQHandler
-SWI2_IRQHandler
-SWI3_IRQHandler
-SWI4_IRQHandler
-SWI5_IRQHandler
-                B .
-                ENDP
-                ALIGN
-
-; User Initial Stack & Heap
-
-                IF      :DEF:__MICROLIB
-
-                EXPORT  __initial_sp
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-
-                ELSE
-
-                IMPORT  __use_two_region_memory
-                EXPORT  __user_initial_stackheap
-
-__user_initial_stackheap PROC
-
-                LDR     R0, = Heap_Mem
-                LDR     R1, = (Stack_Mem + Stack_Size)
-                LDR     R2, = (Heap_Mem + Heap_Size)
-                LDR     R3, = Stack_Mem
-                BX      LR
-                ENDP
-
-                ALIGN
-
-                ENDIF
-
-                END

bsp/nrf51822/Libraries/nrf51822/Source/templates/system_nrf51.c

@@ -1,89 +0,0 @@
-/*
-
-Copyright (c) 2009-2021 ARM Limited. All rights reserved.
-
-    SPDX-License-Identifier: Apache-2.0
-
-Licensed under the Apache License, Version 2.0 (the License); you may
-not use this file except in compliance with the License.
-You may obtain a copy of the License at
-
-    www.apache.org/licenses/LICENSE-2.0
-
-Unless required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an AS IS BASIS, WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-See the License for the specific language governing permissions and
-limitations under the License.
-
-NOTICE: This file has been modified by Nordic Semiconductor ASA.
-
-*/
-
-/* NOTE: Template files (including this one) are application specific and therefore expected to
-   be copied into the application project folder prior to its use! */
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "nrf.h"
-#include "nrf_erratas.h"
-#include "system_nrf51.h"
-
-/*lint ++flb "Enter library region" */
-
-
-#define __SYSTEM_CLOCK      (16000000UL)     /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */
-
-#if defined ( __CC_ARM )
-    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
-#elif defined ( __ICCARM__ )
-    __root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
-#elif defined   ( __GNUC__ )
-    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
-#endif
-
-void SystemCoreClockUpdate(void)
-{
-    SystemCoreClock = __SYSTEM_CLOCK;
-}
-
-void SystemInit(void)
-{
-    /* If desired, switch off the unused RAM to lower consumption by the use of RAMON register.
-       It can also be done in the application main() function. */
-
-    /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required
-       to enable the use of peripherals" found at Product Anomaly document for your device found at
-       https://infocenter.nordicsemi.com/index.jsp The side effect of executing these instructions in the devices
-       that do not need it is that the new peripherals in the second generation devices (LPCOMP for
-       example) will not be available. */
-    if (nrf51_errata_26())
-    {
-        *(uint32_t volatile *)0x40000504 = 0xC007FFDF;
-        *(uint32_t volatile *)0x40006C18 = 0x00008000;
-    }
-
-    /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG
-       register is incorrect" found at Product Anomaly document for your device found at
-       https://infocenter.nordicsemi.com/index.jsp There is no side effect of using these instruction if not needed. */
-    if (nrf51_errata_59())
-    {
-        NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos;
-    }
-
-    /* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices,
-       as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document
-       for your device found at https://infocenter.nordicsemi.com/index.jsp */
-    if (nrf51_errata_76()){
-        if (*(uint32_t volatile *)0x4006EC00 != 1){
-            *(uint32_t volatile *)0x4006EC00 = 0x9375;
-            while (*(uint32_t volatile *)0x4006EC00 != 1){
-            }
-        }
-        *(uint32_t volatile *)0x4006EC14 = 0xC0;
-    }
-
-    SystemCoreClockUpdate();
-}
-
-/*lint --flb "Leave library region" */

bsp/nrf51822/SConscript

@@ -1,14 +0,0 @@
-# for module compiling
-import os
-from building import *
-
-cwd  = GetCurrentDir()
-objs = []
-list = os.listdir(cwd)
-
-for d in list:
-    path = os.path.join(cwd, d)
-    if os.path.isfile(os.path.join(path, 'SConscript')):
-        objs = objs + SConscript(os.path.join(d, 'SConscript'))
-
-Return('objs')

bsp/nrf51822/SConstruct

@@ -1,35 +0,0 @@
-import os
-import sys
-import rtconfig
-
-if os.getenv('RTT_ROOT'):
-    RTT_ROOT = os.getenv('RTT_ROOT')
-else:
-    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
-
-sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
-from building import *
-
-TARGET = 'rtthread-stm32f0xx.' + rtconfig.TARGET_EXT
-
-DefaultEnvironment(tools=[])
-env = Environment(tools = ['mingw'],
-	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
-	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
-	AR = rtconfig.AR, ARFLAGS = '-rc',
-	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
-env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
-
-if rtconfig.PLATFORM == 'iar':
-	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
-	env.Replace(ARFLAGS = [''])
-	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
-
-Export('RTT_ROOT')
-Export('rtconfig')
-
-# prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
-
-# make a building
-DoBuilding(TARGET, objs)

bsp/nrf51822/applications/SConscript

@@ -1,11 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-cwd     = os.path.join(str(Dir('#')), 'applications')
-src	= Glob('*.c')
-CPPPATH = [cwd, str(Dir('#'))]
-
-group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')

bsp/nrf51822/applications/application.c

@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2015-03-01     Yangfs       the first version
- * 2015-03-27     Bernard      code cleanup.
- */
-
-/**
- * @addtogroup NRF51822
- */
-/*@{*/
-
-#include <rtthread.h>
-
-#ifdef RT_USING_FINSH
-#include <finsh.h>
-#include <shell.h>
-#endif
-
-int rt_application_init(void)
-{
-    /* Set finsh device */
-#ifdef RT_USING_FINSH
-    /* initialize finsh */
-    finsh_system_init();
-#endif
-    return 0;
-}
-
-
-/*@}*/

bsp/nrf51822/applications/startup.c

@@ -1,88 +0,0 @@
-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2015, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://openlab.rt-thread.com/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2015-03-01     Yangfs       the first version
- * 2015-03-27     Bernard      code cleanup.
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "board.h"
-
-/**
- * @addtogroup NRF51822
- */
-
-/*@{*/
-
-extern int  rt_application_init(void);
-
-#ifdef __CC_ARM
-extern int Image$$RW_IRAM1$$ZI$$Limit;
-#define NRF_HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
-#elif __ICCARM__
-#pragma section="HEAP"
-#define NRF_HEAP_BEGIN    (__segment_end("HEAP"))
-#else
-extern int __bss_end;
-#define NRF_HEAP_BEGIN    (&__bss_end)
-#endif
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-    /* init board */
-    rt_hw_board_init();
-
-    /* show version */
-    rt_show_version();
-
-    /* init timer system */
-    rt_system_timer_init();
-
-#ifdef RT_USING_HEAP
-    rt_system_heap_init((void*)NRF_HEAP_BEGIN, (void*)NRF_SRAM_END);
-#endif
-
-    /* init scheduler system */
-    rt_system_scheduler_init();
-
-    /* init application */
-    rt_application_init();
-
-    /* init timer thread */
-    rt_system_timer_thread_init();
-
-    /* init idle thread */
-    rt_thread_idle_init();
-
-    /* start scheduler */
-    rt_system_scheduler_start();
-
-    /* never reach here */
-    return ;
-}
-
-int main(void)
-{
-    /* disable interrupt first */
-    rt_hw_interrupt_disable();
-
-    /* startup RT-Thread RTOS */
-    rtthread_startup();
-
-    return 0;
-}
-
-/*@}*/

bsp/nrf51822/drivers/SConscript

@@ -1,13 +0,0 @@
-Import('RTT_ROOT')
-Import('rtconfig')
-from building import *
-
-# get current directory
-cwd = GetCurrentDir() 
-
-src	= Glob('*.c')
-CPPPATH = [cwd]
-
-group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')

bsp/nrf51822/drivers/board.c

@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include <nrf51.h>
-#include <nrf51_bitfields.h>
-
-#include "board.h"
-#include "uart.h"
-
-/**
- * @addtogroup NRF51822
- */
-
-/*@{*/
-#define LFCLK_FREQUENCY           (32768UL)                                 /**< LFCLK frequency in Hertz, constant. */
-#define RTC_FREQUENCY             (800UL)                                   /**< Required RTC working clock RTC_FREQUENCY Hertz. Changable. */
-#define COUNTER_PRESCALER         ((LFCLK_FREQUENCY / RTC_FREQUENCY) - 1)   /* f = LFCLK/(prescaler + 1) */
-
-
-/** @brief Function starting the internal LFCLK XTAL oscillator.
- */
-void lfclk_config(void)
-{
-    NRF_CLOCK->LFCLKSRC            = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos);
-    NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
-    NRF_CLOCK->TASKS_LFCLKSTART    = 1;
-    while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0)
-    {
-        //Do nothing.
-    }
-    NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
-}
-
-
-/** @brief Function for configuring the RTC with TICK to 100Hz.
- */
-void rtc_config(void)
-{
-    NVIC_EnableIRQ(RTC0_IRQn);                 // Enable Interrupt for the RTC in the core.
-    NRF_RTC0->PRESCALER = COUNTER_PRESCALER;   // Set prescaler to a TICK of RTC_FREQUENCY.
-
-    // Enable TICK event and TICK interrupt:
-    NRF_RTC0->EVTENSET = RTC_EVTENSET_TICK_Msk;
-    NRF_RTC0->INTENSET = RTC_INTENSET_TICK_Msk;
-}
-
-
-/** @brief: Function for handling the RTC0 interrupts.
- * Triggered on TICK and COMPARE0 match.
- */
-void RTC0_IRQHandler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-    if ((NRF_RTC0->EVENTS_TICK != 0) &&
-            ((NRF_RTC0->INTENSET & RTC_INTENSET_TICK_Msk) != 0))
-    {
-        NRF_RTC0->EVENTS_TICK = 0;
-
-        rt_tick_increase();  //This function will notify kernel there is one tick passed
-    }
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-
-/**
- * This function will initial NRF51822 board.
- */
-void rt_hw_board_init()
-{
-    //lfclk_config();
-    rtc_config();
-    NRF_RTC0->TASKS_START = 1;
-    /* Initial usart deriver, and set console device */
-    rt_hw_uart_init();
-
-#ifdef RT_USING_CONSOLE
-    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
-#endif
-}
-
-/*@}*/

bsp/nrf51822/drivers/board.h

@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- */
-
-#ifndef __BOARD_H__
-#define __BOARD_H__
-
-// <o> Internal SRAM memory size[Kbytes] <16 or 32>
-//  <i>Default: 16
-#define NRF_SRAM_BEGIN  (0x20000000)
-#define NRF_SRAM_SIZE   (16 * 1024)
-#define NRF_SRAM_END    (NRF_SRAM_BEGIN + NRF_SRAM_SIZE)
-//#endif
-
-
-void rt_hw_board_init(void);
-
-#endif

bsp/nrf51822/drivers/uart.c

@@ -1,197 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- */
-
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdio.h>
-
-#include <rthw.h>
-#include <rtdevice.h>
-
-#include "board.h"
-#include "uart.h"
-
-#include <nrf_gpio.h>
-
-#define UART_RX_BUFSZ 512
-rt_uint8_t rx_buffer[UART_RX_BUFSZ];
-
-struct nrf51822_uart
-{
-    struct rt_device parent;
-    struct rt_ringbuffer rx_rb;
-} uart_device;
-
-void UART0_IRQHandler(void)
-{
-    rt_ubase_t level;
-    struct nrf51822_uart* uart = &uart_device;
-
-    level = rt_hw_interrupt_disable();
-
-    // Wait for RXD data to be received
-    while (NRF_UART0->EVENTS_RXDRDY != 1) ;
-    NRF_UART0->EVENTS_RXDRDY = 0;
-
-    rt_hw_interrupt_enable(level);
-    /* [Handling the data received over UART] */
-    rt_ringbuffer_putchar_force(&(uart->rx_rb), (rt_uint8_t)NRF_UART0->RXD);
-
-    /* invoke callback */
-    if(uart->parent.rx_indicate != RT_NULL)
-    {
-        uart->parent.rx_indicate(&uart->parent, rt_ringbuffer_data_len(&uart->rx_rb));
-    }
-}
-
-
-static rt_err_t rt_uart_init (rt_device_t dev)
-{
-    /* UART Initialization and Enable */
-    /** @snippet [Configure UART RX and TX pin] */
-    nrf_gpio_cfg_output(TX_PIN_NUMBER);
-    nrf_gpio_cfg_input(RX_PIN_NUMBER, NRF_GPIO_PIN_NOPULL);
-
-    NRF_UART0->PSELTXD = TX_PIN_NUMBER;
-    NRF_UART0->PSELRXD = RX_PIN_NUMBER;
-    /** @snippet [Configure UART RX and TX pin] */
-    if (HWFC)
-    {
-        nrf_gpio_cfg_output(RTS_PIN_NUMBER);
-        nrf_gpio_cfg_input(CTS_PIN_NUMBER, NRF_GPIO_PIN_NOPULL);
-        NRF_UART0->PSELCTS = CTS_PIN_NUMBER;
-        NRF_UART0->PSELRTS = RTS_PIN_NUMBER;
-        NRF_UART0->CONFIG  = (UART_CONFIG_HWFC_Enabled << UART_CONFIG_HWFC_Pos);
-    }
-
-    NRF_UART0->BAUDRATE      = (UART_BAUDRATE_BAUDRATE_Baud115200 << UART_BAUDRATE_BAUDRATE_Pos);
-    NRF_UART0->ENABLE        = (UART_ENABLE_ENABLE_Enabled << UART_ENABLE_ENABLE_Pos);
-    NRF_UART0->TASKS_STARTTX = 1;
-    NRF_UART0->TASKS_STARTRX = 1;
-    NRF_UART0->EVENTS_RXDRDY = 0;
-
-    NRF_UART0->INTENSET = (UART_INTENSET_RXDRDY_Enabled << UART_INTENSET_RXDRDY_Pos);
-
-    NVIC_EnableIRQ(UART0_IRQn);
-
-    return RT_EOK;
-}
-
-static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
-{
-    RT_ASSERT(dev != RT_NULL);
-    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-    {
-        /* Enable the UART Interrupt */
-        NVIC_EnableIRQ(UART0_IRQn);
-    }
-
-    return RT_EOK;
-}
-
-static rt_err_t rt_uart_close(rt_device_t dev)
-{
-    RT_ASSERT(dev != RT_NULL);
-    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-    {
-        /* Disable the UART Interrupt */
-        NVIC_DisableIRQ(UART0_IRQn);
-    }
-
-    return RT_EOK;
-}
-
-static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
-    rt_size_t length;
-    struct nrf51822_uart *uart = (struct nrf51822_uart*)dev;
-    /* interrupt receive */
-    rt_base_t level;
-
-    RT_ASSERT(uart != RT_NULL);
-
-    /* disable interrupt */
-    level = rt_hw_interrupt_disable();
-    length = rt_ringbuffer_get(&(uart->rx_rb), buffer, size);
-    /* enable interrupt */
-    rt_hw_interrupt_enable(level);
-
-    return length;
-}
-
-static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
-    char *ptr;
-    ptr = (char*) buffer;
-
-    if (dev->open_flag & RT_DEVICE_FLAG_STREAM)
-    {
-        /* stream mode */
-        while (size)
-        {
-            if (*ptr == '\n')
-            {
-                NRF_UART0->TXD = (uint8_t)'\r';
-
-                // Wait for TXD data to be sent.
-                while (NRF_UART0->EVENTS_TXDRDY != 1) ;
-
-                NRF_UART0->EVENTS_TXDRDY = 0;
-            }
-
-            NRF_UART0->TXD = (uint8_t)(*ptr);
-
-            // Wait for TXD data to be sent.
-            while (NRF_UART0->EVENTS_TXDRDY != 1) ;
-
-            NRF_UART0->EVENTS_TXDRDY = 0;
-
-            ptr ++;
-            size --;
-        }
-    }
-    else
-    {
-        while ( size != 0 )
-        {
-            NRF_UART0->TXD = (uint8_t)(*ptr);
-
-            // Wait for TXD data to be sent.
-            while (NRF_UART0->EVENTS_TXDRDY != 1) ;
-
-            NRF_UART0->EVENTS_TXDRDY = 0;
-
-            ptr++;
-            size--;
-        }
-    }
-
-    return (rt_size_t) ptr - (rt_size_t) buffer;
-}
-
-void rt_hw_uart_init(void)
-{
-    struct nrf51822_uart* uart;
-
-    /* get uart device */
-    uart = &uart_device;
-
-    /* device initialization */
-    uart->parent.type = RT_Device_Class_Char;
-    rt_ringbuffer_init(&(uart->rx_rb), rx_buffer, sizeof(rx_buffer));
-
-    /* device interface */
-    uart->parent.init       = rt_uart_init;
-    uart->parent.open       = rt_uart_open;
-    uart->parent.close      = rt_uart_close;
-    uart->parent.read       = rt_uart_read;
-    uart->parent.write      = rt_uart_write;
-    uart->parent.control    = RT_NULL;
-    uart->parent.user_data  = RT_NULL;
-
-    rt_device_register(&uart->parent, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
-}

bsp/nrf51822/drivers/uart.h

@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- */
-
-#ifndef __UART_H__
-#define __UART_H__
-
-
-
-#define RX_PIN_NUMBER          25
-#define TX_PIN_NUMBER          24
-#define CTS_PIN_NUMBER         26
-#define RTS_PIN_NUMBER         27
-#define HWFC                   false
-
-
-void rt_hw_uart_init(void);
-
-#endif

bsp/nrf51822/project.uvopt

@@ -1,161 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
-
-  <SchemaVersion>1.0</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Extensions>
-    <cExt>*.c</cExt>
-    <aExt>*.s*; *.src; *.a*</aExt>
-    <oExt>*.obj</oExt>
-    <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
-    <pExt>*.plm</pExt>
-    <CppX>*.cpp</CppX>
-  </Extensions>
-
-  <DaveTm>
-    <dwLowDateTime>0</dwLowDateTime>
-    <dwHighDateTime>0</dwHighDateTime>
-  </DaveTm>
-
-  <Target>
-    <TargetName>rt-thread</TargetName>
-    <ToolsetNumber>0x4</ToolsetNumber>
-    <ToolsetName>ARM-ADS</ToolsetName>
-    <TargetOption>
-      <CLKADS>12000000</CLKADS>
-      <OPTTT>
-        <gFlags>1</gFlags>
-        <BeepAtEnd>1</BeepAtEnd>
-        <RunSim>0</RunSim>
-        <RunTarget>1</RunTarget>
-      </OPTTT>
-      <OPTHX>
-        <HexSelection>1</HexSelection>
-        <FlashByte>65535</FlashByte>
-        <HexRangeLowAddress>0</HexRangeLowAddress>
-        <HexRangeHighAddress>0</HexRangeHighAddress>
-        <HexOffset>0</HexOffset>
-      </OPTHX>
-      <OPTLEX>
-        <PageWidth>79</PageWidth>
-        <PageLength>66</PageLength>
-        <TabStop>8</TabStop>
-        <ListingPath>.\build\</ListingPath>
-      </OPTLEX>
-      <ListingPage>
-        <CreateCListing>1</CreateCListing>
-        <CreateAListing>1</CreateAListing>
-        <CreateLListing>1</CreateLListing>
-        <CreateIListing>0</CreateIListing>
-        <AsmCond>1</AsmCond>
-        <AsmSymb>1</AsmSymb>
-        <AsmXref>0</AsmXref>
-        <CCond>1</CCond>
-        <CCode>0</CCode>
-        <CListInc>0</CListInc>
-        <CSymb>0</CSymb>
-        <LinkerCodeListing>0</LinkerCodeListing>
-      </ListingPage>
-      <OPTXL>
-        <LMap>1</LMap>
-        <LComments>1</LComments>
-        <LGenerateSymbols>1</LGenerateSymbols>
-        <LLibSym>1</LLibSym>
-        <LLines>1</LLines>
-        <LLocSym>1</LLocSym>
-        <LPubSym>1</LPubSym>
-        <LXref>0</LXref>
-        <LExpSel>0</LExpSel>
-      </OPTXL>
-      <OPTFL>
-        <tvExp>0</tvExp>
-        <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>1</IsCurrentTarget>
-      </OPTFL>
-      <CpuCode>0</CpuCode>
-      <DebugOpt>
-        <uSim>0</uSim>
-        <uTrg>1</uTrg>
-        <sLdApp>1</sLdApp>
-        <sGomain>1</sGomain>
-        <sRbreak>1</sRbreak>
-        <sRwatch>1</sRwatch>
-        <sRmem>1</sRmem>
-        <sRfunc>1</sRfunc>
-        <sRbox>1</sRbox>
-        <tLdApp>1</tLdApp>
-        <tGomain>1</tGomain>
-        <tRbreak>1</tRbreak>
-        <tRwatch>1</tRwatch>
-        <tRmem>1</tRmem>
-        <tRfunc>0</tRfunc>
-        <tRbox>1</tRbox>
-        <tRtrace>0</tRtrace>
-        <sRSysVw>1</sRSysVw>
-        <tRSysVw>1</tRSysVw>
-        <sRunDeb>0</sRunDeb>
-        <sLrtime>0</sLrtime>
-        <nTsel>6</nTsel>
-        <sDll></sDll>
-        <sDllPa></sDllPa>
-        <sDlgDll></sDlgDll>
-        <sDlgPa></sDlgPa>
-        <sIfile></sIfile>
-        <tDll></tDll>
-        <tDllPa></tDllPa>
-        <tDlgDll></tDlgDll>
-        <tDlgPa></tDlgPa>
-        <tIfile></tIfile>
-        <pMon>Segger\JL2CM3.dll</pMon>
-      </DebugOpt>
-      <TargetDriverDllRegistry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>JL2CM3</Key>
-          <Name>-U480200710 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)</Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>UL2CM3</Key>
-          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm))</Name>
-        </SetRegEntry>
-      </TargetDriverDllRegistry>
-      <Breakpoint/>
-      <Tracepoint>
-        <THDelay>0</THDelay>
-      </Tracepoint>
-      <DebugFlag>
-        <trace>0</trace>
-        <periodic>0</periodic>
-        <aLwin>0</aLwin>
-        <aCover>0</aCover>
-        <aSer1>0</aSer1>
-        <aSer2>0</aSer2>
-        <aPa>0</aPa>
-        <viewmode>0</viewmode>
-        <vrSel>0</vrSel>
-        <aSym>0</aSym>
-        <aTbox>0</aTbox>
-        <AscS1>0</AscS1>
-        <AscS2>0</AscS2>
-        <AscS3>0</AscS3>
-        <aSer3>0</aSer3>
-        <eProf>0</eProf>
-        <aLa>0</aLa>
-        <aPa1>0</aPa1>
-        <AscS4>0</AscS4>
-        <aSer4>0</aSer4>
-        <StkLoc>0</StkLoc>
-        <TrcWin>0</TrcWin>
-        <newCpu>0</newCpu>
-        <uProt>0</uProt>
-      </DebugFlag>
-      <LintExecutable></LintExecutable>
-      <LintConfigFile></LintConfigFile>
-    </TargetOption>
-  </Target>
-
-</ProjectOpt>

bsp/nrf51822/project.uvoptx

@@ -1,640 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
-
-  <SchemaVersion>1.0</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Extensions>
-    <cExt>*.c</cExt>
-    <aExt>*.s*; *.src; *.a*</aExt>
-    <oExt>*.obj</oExt>
-    <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
-    <pExt>*.plm</pExt>
-    <CppX>*.cpp</CppX>
-    <nMigrate>0</nMigrate>
-  </Extensions>
-
-  <DaveTm>
-    <dwLowDateTime>0</dwLowDateTime>
-    <dwHighDateTime>0</dwHighDateTime>
-  </DaveTm>
-
-  <Target>
-    <TargetName>rt-thread</TargetName>
-    <ToolsetNumber>0x4</ToolsetNumber>
-    <ToolsetName>ARM-ADS</ToolsetName>
-    <TargetOption>
-      <CLKADS>12000000</CLKADS>
-      <OPTTT>
-        <gFlags>1</gFlags>
-        <BeepAtEnd>1</BeepAtEnd>
-        <RunSim>0</RunSim>
-        <RunTarget>1</RunTarget>
-        <RunAbUc>0</RunAbUc>
-      </OPTTT>
-      <OPTHX>
-        <HexSelection>1</HexSelection>
-        <FlashByte>65535</FlashByte>
-        <HexRangeLowAddress>0</HexRangeLowAddress>
-        <HexRangeHighAddress>0</HexRangeHighAddress>
-        <HexOffset>0</HexOffset>
-      </OPTHX>
-      <OPTLEX>
-        <PageWidth>79</PageWidth>
-        <PageLength>66</PageLength>
-        <TabStop>8</TabStop>
-        <ListingPath>.\build\</ListingPath>
-      </OPTLEX>
-      <ListingPage>
-        <CreateCListing>1</CreateCListing>
-        <CreateAListing>1</CreateAListing>
-        <CreateLListing>1</CreateLListing>
-        <CreateIListing>0</CreateIListing>
-        <AsmCond>1</AsmCond>
-        <AsmSymb>1</AsmSymb>
-        <AsmXref>0</AsmXref>
-        <CCond>1</CCond>
-        <CCode>0</CCode>
-        <CListInc>0</CListInc>
-        <CSymb>0</CSymb>
-        <LinkerCodeListing>0</LinkerCodeListing>
-      </ListingPage>
-      <OPTXL>
-        <LMap>1</LMap>
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bsp/nrf51822/project.uvprojx

@@ -1,592 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
-
-  <SchemaVersion>2.1</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Targets>
-    <Target>
-      <TargetName>rt-thread</TargetName>
-      <ToolsetNumber>0x4</ToolsetNumber>
-      <ToolsetName>ARM-ADS</ToolsetName>
-      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
-      <uAC6>0</uAC6>
-      <TargetOption>
-        <TargetCommonOption>
-          <Device>nRF51822_xxAA</Device>
-          <Vendor>Nordic Semiconductor</Vendor>
-          <PackID>NordicSemiconductor.nRF_DeviceFamilyPack.8.38.0</PackID>
-          <PackURL>http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/</PackURL>
-          <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x4000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
-          <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile></StartupFile>
-          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm))</FlashDriverDll>
-          <DeviceId>0</DeviceId>
-          <RegisterFile>$$Device:nRF51822_xxAA$Device\Include\nrf.h</RegisterFile>
-          <MemoryEnv></MemoryEnv>
-          <Cmp></Cmp>
-          <Asm></Asm>
-          <Linker></Linker>
-          <OHString></OHString>
-          <InfinionOptionDll></InfinionOptionDll>
-          <SLE66CMisc></SLE66CMisc>
-          <SLE66AMisc></SLE66AMisc>
-          <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>$$Device:nRF51822_xxAA$SVD\nrf51.xml</SFDFile>
-          <bCustSvd>0</bCustSvd>
-          <UseEnv>0</UseEnv>
-          <BinPath></BinPath>
-          <IncludePath></IncludePath>
-          <LibPath></LibPath>
-          <RegisterFilePath></RegisterFilePath>
-          <DBRegisterFilePath></DBRegisterFilePath>
-          <TargetStatus>
-            <Error>0</Error>
-            <ExitCodeStop>0</ExitCodeStop>
-            <ButtonStop>0</ButtonStop>
-            <NotGenerated>0</NotGenerated>
-            <InvalidFlash>1</InvalidFlash>
-          </TargetStatus>
-          <OutputDirectory>.\build\</OutputDirectory>
-          <OutputName>template</OutputName>
-          <CreateExecutable>1</CreateExecutable>
-          <CreateLib>0</CreateLib>
-          <CreateHexFile>0</CreateHexFile>
-          <DebugInformation>1</DebugInformation>
-          <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\build\</ListingPath>
-          <HexFormatSelection>1</HexFormatSelection>
-          <Merge32K>0</Merge32K>
-          <CreateBatchFile>0</CreateBatchFile>
-          <BeforeCompile>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopU1X>0</nStopU1X>
-            <nStopU2X>0</nStopU2X>
-          </BeforeCompile>
-          <BeforeMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopB1X>0</nStopB1X>
-            <nStopB2X>0</nStopB2X>
-          </BeforeMake>
-          <AfterMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopA1X>0</nStopA1X>
-            <nStopA2X>0</nStopA2X>
-          </AfterMake>
-          <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString></SVCSIdString>
-        </TargetCommonOption>
-        <CommonProperty>
-          <UseCPPCompiler>0</UseCPPCompiler>
-          <RVCTCodeConst>0</RVCTCodeConst>
-          <RVCTZI>0</RVCTZI>
-          <RVCTOtherData>0</RVCTOtherData>
-          <ModuleSelection>0</ModuleSelection>
-          <IncludeInBuild>1</IncludeInBuild>
-          <AlwaysBuild>0</AlwaysBuild>
-          <GenerateAssemblyFile>0</GenerateAssemblyFile>
-          <AssembleAssemblyFile>0</AssembleAssemblyFile>
-          <PublicsOnly>0</PublicsOnly>
-          <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument></CustomArgument>
-          <IncludeLibraryModules></IncludeLibraryModules>
-          <ComprImg>1</ComprImg>
-        </CommonProperty>
-        <DllOption>
-          <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments> </SimDllArguments>
-          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
-          <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments> </TargetDllArguments>
-          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
-        </DllOption>
-        <DebugOption>
-          <OPTHX>
-            <HexSelection>1</HexSelection>
-            <HexRangeLowAddress>0</HexRangeLowAddress>
-            <HexRangeHighAddress>0</HexRangeHighAddress>
-            <HexOffset>0</HexOffset>
-            <Oh166RecLen>16</Oh166RecLen>
-          </OPTHX>
-        </DebugOption>
-        <Utilities>
-          <Flash1>
-            <UseTargetDll>1</UseTargetDll>
-            <UseExternalTool>0</UseExternalTool>
-            <RunIndependent>0</RunIndependent>
-            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
-            <Capability>1</Capability>
-            <DriverSelection>4096</DriverSelection>
-          </Flash1>
-          <bUseTDR>1</bUseTDR>
-          <Flash2>BIN\UL2CM3.DLL</Flash2>
-          <Flash3>"" ()</Flash3>
-          <Flash4></Flash4>
-          <pFcarmOut></pFcarmOut>
-          <pFcarmGrp></pFcarmGrp>
-          <pFcArmRoot></pFcArmRoot>
-          <FcArmLst>0</FcArmLst>
-        </Utilities>
-        <TargetArmAds>
-          <ArmAdsMisc>
-            <GenerateListings>0</GenerateListings>
-            <asHll>1</asHll>
-            <asAsm>1</asAsm>
-            <asMacX>1</asMacX>
-            <asSyms>1</asSyms>
-            <asFals>1</asFals>
-            <asDbgD>1</asDbgD>
-            <asForm>1</asForm>
-            <ldLst>0</ldLst>
-            <ldmm>1</ldmm>
-            <ldXref>1</ldXref>
-            <BigEnd>0</BigEnd>
-            <AdsALst>1</AdsALst>
-            <AdsACrf>1</AdsACrf>
-            <AdsANop>0</AdsANop>
-            <AdsANot>0</AdsANot>
-            <AdsLLst>1</AdsLLst>
-            <AdsLmap>1</AdsLmap>
-            <AdsLcgr>1</AdsLcgr>
-            <AdsLsym>1</AdsLsym>
-            <AdsLszi>1</AdsLszi>
-            <AdsLtoi>1</AdsLtoi>
-            <AdsLsun>1</AdsLsun>
-            <AdsLven>1</AdsLven>
-            <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
-            <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M0"</AdsCpuType>
-            <RvctDeviceName></RvctDeviceName>
-            <mOS>0</mOS>
-            <uocRom>0</uocRom>
-            <uocRam>0</uocRam>
-            <hadIROM>1</hadIROM>
-            <hadIRAM>1</hadIRAM>
-            <hadXRAM>0</hadXRAM>
-            <uocXRam>0</uocXRam>
-            <RvdsVP>0</RvdsVP>
-            <RvdsMve>0</RvdsMve>
-            <hadIRAM2>0</hadIRAM2>
-            <hadIROM2>0</hadIROM2>
-            <StupSel>8</StupSel>
-            <useUlib>0</useUlib>
-            <EndSel>0</EndSel>
-            <uLtcg>0</uLtcg>
-            <nSecure>0</nSecure>
-            <RoSelD>3</RoSelD>
-            <RwSelD>3</RwSelD>
-            <CodeSel>0</CodeSel>
-            <OptFeed>0</OptFeed>
-            <NoZi1>0</NoZi1>
-            <NoZi2>0</NoZi2>
-            <NoZi3>0</NoZi3>
-            <NoZi4>0</NoZi4>
-            <NoZi5>0</NoZi5>
-            <Ro1Chk>0</Ro1Chk>
-            <Ro2Chk>0</Ro2Chk>
-            <Ro3Chk>0</Ro3Chk>
-            <Ir1Chk>1</Ir1Chk>
-            <Ir2Chk>0</Ir2Chk>
-            <Ra1Chk>0</Ra1Chk>
-            <Ra2Chk>0</Ra2Chk>
-            <Ra3Chk>0</Ra3Chk>
-            <Im1Chk>1</Im1Chk>
-            <Im2Chk>0</Im2Chk>
-            <OnChipMemories>
-              <Ocm1>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm1>
-              <Ocm2>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm2>
-              <Ocm3>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm3>
-              <Ocm4>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm4>
-              <Ocm5>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm5>
-              <Ocm6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm6>
-              <IRAM>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x4000</Size>
-              </IRAM>
-              <IROM>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x40000</Size>
-              </IROM>
-              <XRAM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </XRAM>
-              <OCR_RVCT1>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT1>
-              <OCR_RVCT2>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT2>
-              <OCR_RVCT3>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT3>
-              <OCR_RVCT4>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x40000</Size>
-              </OCR_RVCT4>
-              <OCR_RVCT5>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT5>
-              <OCR_RVCT6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT6>
-              <OCR_RVCT7>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT7>
-              <OCR_RVCT8>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT8>
-              <OCR_RVCT9>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x4000</Size>
-              </OCR_RVCT9>
-              <OCR_RVCT10>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT10>
-            </OnChipMemories>
-            <RvctStartVector></RvctStartVector>
-          </ArmAdsMisc>
-          <Cads>
-            <interw>1</interw>
-            <Optim>1</Optim>
-            <oTime>0</oTime>
-            <SplitLS>0</SplitLS>
-            <OneElfS>1</OneElfS>
-            <Strict>0</Strict>
-            <EnumInt>0</EnumInt>
-            <PlainCh>0</PlainCh>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <wLevel>0</wLevel>
-            <uThumb>0</uThumb>
-            <uSurpInc>0</uSurpInc>
-            <uC99>0</uC99>
-            <uGnu>0</uGnu>
-            <useXO>0</useXO>
-            <v6Lang>1</v6Lang>
-            <v6LangP>1</v6LangP>
-            <vShortEn>1</vShortEn>
-            <vShortWch>1</vShortWch>
-            <v6Lto>0</v6Lto>
-            <v6WtE>0</v6WtE>
-            <v6Rtti>0</v6Rtti>
-            <VariousControls>
-              <MiscControls>--c99</MiscControls>
-              <Define>NRF51, __RTTHREAD__, USE_STDPERIPH_DRIVER</Define>
-              <Undefine></Undefine>
-              <IncludePath>applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m0;..\..\components\drivers\include;drivers;Libraries\CMSIS\Include;Libraries\nrf51822\Include;..\..\components\finsh;.;..\..\include</IncludePath>
-            </VariousControls>
-          </Cads>
-          <Aads>
-            <interw>1</interw>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <thumb>0</thumb>
-            <SplitLS>0</SplitLS>
-            <SwStkChk>0</SwStkChk>
-            <NoWarn>0</NoWarn>
-            <uSurpInc>0</uSurpInc>
-            <useXO>0</useXO>
-            <uClangAs>0</uClangAs>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Aads>
-          <LDads>
-            <umfTarg>1</umfTarg>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <noStLib>0</noStLib>
-            <RepFail>1</RepFail>
-            <useFile>0</useFile>
-            <TextAddressRange>0x08000000</TextAddressRange>
-            <DataAddressRange>0x20000000</DataAddressRange>
-            <pXoBase></pXoBase>
-            <ScatterFile></ScatterFile>
-            <IncludeLibs></IncludeLibs>
-            <IncludeLibsPath></IncludeLibsPath>
-            <Misc></Misc>
-            <LinkerInputFile></LinkerInputFile>
-            <DisabledWarnings></DisabledWarnings>
-          </LDads>
-        </TargetArmAds>
-      </TargetOption>
-      <Groups>
-        <Group>
-          <GroupName>Applications</GroupName>
-          <Files>
-            <File>
-              <FileName>startup.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>applications\startup.c</FilePath>
-            </File>
-            <File>
-              <FileName>application.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>applications\application.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>CPU</GroupName>
-          <Files>
-            <File>
-              <FileName>div0.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
-            </File>
-            <File>
-              <FileName>showmem.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
-            </File>
-            <File>
-              <FileName>backtrace.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
-            </File>
-            <File>
-              <FileName>cpuport.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\libcpu\arm\cortex-m0\cpuport.c</FilePath>
-            </File>
-            <File>
-              <FileName>context_rvds.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\libcpu\arm\cortex-m0\context_rvds.S</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>DeviceDrivers</GroupName>
-          <Files>
-            <File>
-              <FileName>dataqueue.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
-            </File>
-            <File>
-              <FileName>workqueue.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\workqueue.c</FilePath>
-            </File>
-            <File>
-              <FileName>ringblk_buf.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath>
-            </File>
-            <File>
-              <FileName>completion.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\completion.c</FilePath>
-            </File>
-            <File>
-              <FileName>pipe.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
-            </File>
-            <File>
-              <FileName>ringbuffer.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
-            </File>
-            <File>
-              <FileName>waitqueue.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\drivers\src\waitqueue.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>Drivers</GroupName>
-          <Files>
-            <File>
-              <FileName>board.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>drivers\board.c</FilePath>
-            </File>
-            <File>
-              <FileName>uart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>drivers\uart.c</FilePath>
-            </File>
-            <File>
-              <FileName>system_nrf51.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>Libraries\nrf51822\Source\templates\system_nrf51.c</FilePath>
-            </File>
-            <File>
-              <FileName>arm_startup_nrf51.s</FileName>
-              <FileType>2</FileType>
-              <FilePath>Libraries\nrf51822\Source\templates\arm\arm_startup_nrf51.s</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>finsh</GroupName>
-          <Files>
-            <File>
-              <FileName>shell.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\shell.c</FilePath>
-            </File>
-            <File>
-              <FileName>msh.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\msh.c</FilePath>
-            </File>
-            <File>
-              <FileName>cmd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\components\finsh\cmd.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>Kernel</GroupName>
-          <Files>
-            <File>
-              <FileName>kservice.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\kservice.c</FilePath>
-            </File>
-            <File>
-              <FileName>device.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\device.c</FilePath>
-            </File>
-            <File>
-              <FileName>components.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\components.c</FilePath>
-            </File>
-            <File>
-              <FileName>thread.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\thread.c</FilePath>
-            </File>
-            <File>
-              <FileName>object.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\object.c</FilePath>
-            </File>
-            <File>
-              <FileName>idle.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\idle.c</FilePath>
-            </File>
-            <File>
-              <FileName>mem.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\mem.c</FilePath>
-            </File>
-            <File>
-              <FileName>ipc.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\ipc.c</FilePath>
-            </File>
-            <File>
-              <FileName>irq.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\irq.c</FilePath>
-            </File>
-            <File>
-              <FileName>timer.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\timer.c</FilePath>
-            </File>
-            <File>
-              <FileName>clock.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\clock.c</FilePath>
-            </File>
-            <File>
-              <FileName>scheduler.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\scheduler.c</FilePath>
-            </File>
-            <File>
-              <FileName>mempool.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\src\mempool.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-      </Groups>
-    </Target>
-  </Targets>
-
-  <RTE>
-    <apis/>
-    <components/>
-    <files/>
-  </RTE>
-
-</Project>

bsp/nrf51822/rtconfig.h

@@ -1,96 +0,0 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-/* RT_NAME_MAX*/
-#define RT_NAME_MAX    6
-
-/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE   4
-
-/* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX  8
-
-/* Tick per Second */
-#define RT_TICK_PER_SECOND  100
-
-/* SECTION: RT_DEBUG */
-/* Thread Debug */
-#define RT_DEBUG
-#define RT_DEBUG_COLOR
-//#define RT_DEBUG_INIT 1
-#define RT_USING_OVERFLOW_CHECK
-
-/* Using Hook */
-#define RT_USING_HOOK
-
-#define IDLE_THREAD_STACK_SIZE  512
-
-/* Using Software Timer */
-/* #define RT_USING_TIMER_SOFT */
-#define RT_TIMER_THREAD_PRIO        4
-#define RT_TIMER_THREAD_STACK_SIZE  512
-#define RT_TIMER_TICK_PER_SECOND    100
-
-/* SECTION: IPC */
-/* Using Semaphore*/
-#define RT_USING_SEMAPHORE
-
-/* Using Mutex */
-#define RT_USING_MUTEX
-
-/* Using Event */
-/* #define RT_USING_EVENT */
-
-/* Using MailBox */
-#define RT_USING_MAILBOX
-
-/* Using Message Queue */
-/* #define RT_USING_MESSAGEQUEUE */
-
-/* SECTION: Memory Management */
-/* Using Memory Pool Management*/
-#define RT_USING_MEMPOOL
-
-/* Using Dynamic Heap Management */
-#define RT_USING_HEAP
-
-/* Using Small MM */
-#define RT_USING_SMALL_MEM
-#define RT_USING_TINY_SIZE
-
-// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
-//#define RT_USING_COMPONENTS_INIT
-
-/* SECTION: Device System */
-/* Using Device System */
-#define RT_USING_DEVICE
-// <bool name="RT_USING_DEVICE_IPC" description="Using device communication" default="true" />
-#define RT_USING_DEVICE_IPC
-// <bool name="RT_USING_SERIAL" description="Using Serial" default="true" />
-//#define RT_USING_SERIAL
-#define RT_SERIAL_USING_DMA
-
-/* SECTION: Console options */
-#define RT_USING_CONSOLE
-/* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE  128
-// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart1" />
-#define RT_CONSOLE_DEVICE_NAME      "uart0"
-
-
-
-/* SECTION: finsh, a C-Express shell */
-#define RT_USING_FINSH
-/* configure finsh parameters */
-#define FINSH_THREAD_PRIORITY 6
-#define FINSH_THREAD_STACK_SIZE 512
-#define FINSH_HISTORY_LINES 1
-/* Using symbol table */
-#define FINSH_USING_SYMTAB
-#define FINSH_USING_DESCRIPTION
-
-#define FINSH_USING_MSH
-#define FINSH_USING_MSH_ONLY
-
-#endif

bsp/nrf51822/rtconfig.py

@@ -1,83 +0,0 @@
-import os
-
-# toolchains options
-ARCH='arm'
-CPU='cortex-m0'
-CROSS_TOOL='keil'
-
-if os.getenv('RTT_CC'):
-	CROSS_TOOL = os.getenv('RTT_CC')
-
-# cross_tool provides the cross compiler
-# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
-if  CROSS_TOOL == 'gcc':
-	PLATFORM 	= 'gcc'
-	EXEC_PATH 	= 'C:/Program Files/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin'
-elif CROSS_TOOL == 'keil':
-	PLATFORM 	= 'armcc'
-	EXEC_PATH 	= 'C:/Keil_v5'
-elif CROSS_TOOL == 'iar':
-    print('================ERROR============================')
-    print('Not support iar yet!')
-    print('=================================================')
-    exit(0)
-
-if os.getenv('RTT_EXEC_PATH'):
-	EXEC_PATH = os.getenv('RTT_EXEC_PATH')
-
-BUILD = 'debug'
-NRF_TYPE = 'NRF51822'
-
-if PLATFORM == 'gcc':
-    # toolchains
-    PREFIX = 'arm-none-eabi-'
-    CC = PREFIX + 'gcc'
-    AS = PREFIX + 'gcc'
-    AR = PREFIX + 'ar'
-    LINK = PREFIX + 'gcc'
-    TARGET_EXT = 'elf'
-    SIZE = PREFIX + 'size'
-    OBJDUMP = PREFIX + 'objdump'
-    OBJCPY = PREFIX + 'objcopy'
-
-    DEVICE = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections'
-    CFLAGS = DEVICE 
-    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
-    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-nrf51822.map,-cref,-u,Reset_Handler -T nrf51822_rom.ld'
-
-    CPATH = ''
-    LPATH = ''
-
-    if BUILD == 'debug':
-        CFLAGS += ' -O0 -gdwarf-2'
-        AFLAGS += ' -gdwarf-2'
-    else:
-        CFLAGS += ' -O2'
-
-    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
-
-elif PLATFORM == 'armcc':
-    # toolchains
-    CC = 'armcc'
-    AS = 'armasm'
-    AR = 'armar'
-    LINK = 'armlink'
-    TARGET_EXT = 'axf'
-
-    DEVICE = ' --device DARMSTM'
-    CFLAGS = DEVICE + ' --apcs=interwork'
-    AFLAGS = DEVICE
-    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter nrf51822_rom.sct'
-
-    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' 
-    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
-
-    EXEC_PATH += '/arm/bin40/'
-
-    if BUILD == 'debug':
-        CFLAGS += ' -g -O0'
-        AFLAGS += ' -g'
-    else:
-        CFLAGS += ' -O2'
-
-    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'

bsp/nrf51822/template.uvopt

@@ -1,161 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
-
-  <SchemaVersion>1.0</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Extensions>
-    <cExt>*.c</cExt>
-    <aExt>*.s*; *.src; *.a*</aExt>
-    <oExt>*.obj</oExt>
-    <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
-    <pExt>*.plm</pExt>
-    <CppX>*.cpp</CppX>
-  </Extensions>
-
-  <DaveTm>
-    <dwLowDateTime>0</dwLowDateTime>
-    <dwHighDateTime>0</dwHighDateTime>
-  </DaveTm>
-
-  <Target>
-    <TargetName>rt-thread</TargetName>
-    <ToolsetNumber>0x4</ToolsetNumber>
-    <ToolsetName>ARM-ADS</ToolsetName>
-    <TargetOption>
-      <CLKADS>12000000</CLKADS>
-      <OPTTT>
-        <gFlags>1</gFlags>
-        <BeepAtEnd>1</BeepAtEnd>
-        <RunSim>0</RunSim>
-        <RunTarget>1</RunTarget>
-      </OPTTT>
-      <OPTHX>
-        <HexSelection>1</HexSelection>
-        <FlashByte>65535</FlashByte>
-        <HexRangeLowAddress>0</HexRangeLowAddress>
-        <HexRangeHighAddress>0</HexRangeHighAddress>
-        <HexOffset>0</HexOffset>
-      </OPTHX>
-      <OPTLEX>
-        <PageWidth>79</PageWidth>
-        <PageLength>66</PageLength>
-        <TabStop>8</TabStop>
-        <ListingPath>.\build\</ListingPath>
-      </OPTLEX>
-      <ListingPage>
-        <CreateCListing>1</CreateCListing>
-        <CreateAListing>1</CreateAListing>
-        <CreateLListing>1</CreateLListing>
-        <CreateIListing>0</CreateIListing>
-        <AsmCond>1</AsmCond>
-        <AsmSymb>1</AsmSymb>
-        <AsmXref>0</AsmXref>
-        <CCond>1</CCond>
-        <CCode>0</CCode>
-        <CListInc>0</CListInc>
-        <CSymb>0</CSymb>
-        <LinkerCodeListing>0</LinkerCodeListing>
-      </ListingPage>
-      <OPTXL>
-        <LMap>1</LMap>
-        <LComments>1</LComments>
-        <LGenerateSymbols>1</LGenerateSymbols>
-        <LLibSym>1</LLibSym>
-        <LLines>1</LLines>
-        <LLocSym>1</LLocSym>
-        <LPubSym>1</LPubSym>
-        <LXref>0</LXref>
-        <LExpSel>0</LExpSel>
-      </OPTXL>
-      <OPTFL>
-        <tvExp>0</tvExp>
-        <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>1</IsCurrentTarget>
-      </OPTFL>
-      <CpuCode>0</CpuCode>
-      <DebugOpt>
-        <uSim>0</uSim>
-        <uTrg>1</uTrg>
-        <sLdApp>1</sLdApp>
-        <sGomain>1</sGomain>
-        <sRbreak>1</sRbreak>
-        <sRwatch>1</sRwatch>
-        <sRmem>1</sRmem>
-        <sRfunc>1</sRfunc>
-        <sRbox>1</sRbox>
-        <tLdApp>1</tLdApp>
-        <tGomain>1</tGomain>
-        <tRbreak>1</tRbreak>
-        <tRwatch>1</tRwatch>
-        <tRmem>1</tRmem>
-        <tRfunc>0</tRfunc>
-        <tRbox>1</tRbox>
-        <tRtrace>0</tRtrace>
-        <sRSysVw>1</sRSysVw>
-        <tRSysVw>1</tRSysVw>
-        <sRunDeb>0</sRunDeb>
-        <sLrtime>0</sLrtime>
-        <nTsel>6</nTsel>
-        <sDll></sDll>
-        <sDllPa></sDllPa>
-        <sDlgDll></sDlgDll>
-        <sDlgPa></sDlgPa>
-        <sIfile></sIfile>
-        <tDll></tDll>
-        <tDllPa></tDllPa>
-        <tDlgDll></tDlgDll>
-        <tDlgPa></tDlgPa>
-        <tIfile></tIfile>
-        <pMon>Segger\JL2CM3.dll</pMon>
-      </DebugOpt>
-      <TargetDriverDllRegistry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>JL2CM3</Key>
-          <Name>-U480200710 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)</Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>UL2CM3</Key>
-          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm))</Name>
-        </SetRegEntry>
-      </TargetDriverDllRegistry>
-      <Breakpoint/>
-      <Tracepoint>
-        <THDelay>0</THDelay>
-      </Tracepoint>
-      <DebugFlag>
-        <trace>0</trace>
-        <periodic>0</periodic>
-        <aLwin>0</aLwin>
-        <aCover>0</aCover>
-        <aSer1>0</aSer1>
-        <aSer2>0</aSer2>
-        <aPa>0</aPa>
-        <viewmode>0</viewmode>
-        <vrSel>0</vrSel>
-        <aSym>0</aSym>
-        <aTbox>0</aTbox>
-        <AscS1>0</AscS1>
-        <AscS2>0</AscS2>
-        <AscS3>0</AscS3>
-        <aSer3>0</aSer3>
-        <eProf>0</eProf>
-        <aLa>0</aLa>
-        <aPa1>0</aPa1>
-        <AscS4>0</AscS4>
-        <aSer4>0</aSer4>
-        <StkLoc>0</StkLoc>
-        <TrcWin>0</TrcWin>
-        <newCpu>0</newCpu>
-        <uProt>0</uProt>
-      </DebugFlag>
-      <LintExecutable></LintExecutable>
-      <LintConfigFile></LintConfigFile>
-    </TargetOption>
-  </Target>
-
-</ProjectOpt>

bsp/nrf51822/template.uvoptx

@@ -1,177 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
-
-  <SchemaVersion>1.0</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Extensions>
-    <cExt>*.c</cExt>
-    <aExt>*.s*; *.src; *.a*</aExt>
-    <oExt>*.obj</oExt>
-    <lExt>*.lib</lExt>
-    <tExt>*.txt; *.h; *.inc</tExt>
-    <pExt>*.plm</pExt>
-    <CppX>*.cpp</CppX>
-    <nMigrate>0</nMigrate>
-  </Extensions>
-
-  <DaveTm>
-    <dwLowDateTime>0</dwLowDateTime>
-    <dwHighDateTime>0</dwHighDateTime>
-  </DaveTm>
-
-  <Target>
-    <TargetName>rt-thread</TargetName>
-    <ToolsetNumber>0x4</ToolsetNumber>
-    <ToolsetName>ARM-ADS</ToolsetName>
-    <TargetOption>
-      <CLKADS>12000000</CLKADS>
-      <OPTTT>
-        <gFlags>1</gFlags>
-        <BeepAtEnd>1</BeepAtEnd>
-        <RunSim>0</RunSim>
-        <RunTarget>1</RunTarget>
-        <RunAbUc>0</RunAbUc>
-      </OPTTT>
-      <OPTHX>
-        <HexSelection>1</HexSelection>
-        <FlashByte>65535</FlashByte>
-        <HexRangeLowAddress>0</HexRangeLowAddress>
-        <HexRangeHighAddress>0</HexRangeHighAddress>
-        <HexOffset>0</HexOffset>
-      </OPTHX>
-      <OPTLEX>
-        <PageWidth>79</PageWidth>
-        <PageLength>66</PageLength>
-        <TabStop>8</TabStop>
-        <ListingPath>.\build\</ListingPath>
-      </OPTLEX>
-      <ListingPage>
-        <CreateCListing>1</CreateCListing>
-        <CreateAListing>1</CreateAListing>
-        <CreateLListing>1</CreateLListing>
-        <CreateIListing>0</CreateIListing>
-        <AsmCond>1</AsmCond>
-        <AsmSymb>1</AsmSymb>
-        <AsmXref>0</AsmXref>
-        <CCond>1</CCond>
-        <CCode>0</CCode>
-        <CListInc>0</CListInc>
-        <CSymb>0</CSymb>
-        <LinkerCodeListing>0</LinkerCodeListing>
-      </ListingPage>
-      <OPTXL>
-        <LMap>1</LMap>
-        <LComments>1</LComments>
-        <LGenerateSymbols>1</LGenerateSymbols>
-        <LLibSym>1</LLibSym>
-        <LLines>1</LLines>
-        <LLocSym>1</LLocSym>
-        <LPubSym>1</LPubSym>
-        <LXref>0</LXref>
-        <LExpSel>0</LExpSel>
-      </OPTXL>
-      <OPTFL>
-        <tvExp>0</tvExp>
-        <tvExpOptDlg>0</tvExpOptDlg>
-        <IsCurrentTarget>1</IsCurrentTarget>
-      </OPTFL>
-      <CpuCode>5</CpuCode>
-      <DebugOpt>
-        <uSim>0</uSim>
-        <uTrg>1</uTrg>
-        <sLdApp>1</sLdApp>
-        <sGomain>1</sGomain>
-        <sRbreak>1</sRbreak>
-        <sRwatch>1</sRwatch>
-        <sRmem>1</sRmem>
-        <sRfunc>1</sRfunc>
-        <sRbox>1</sRbox>
-        <tLdApp>1</tLdApp>
-        <tGomain>1</tGomain>
-        <tRbreak>1</tRbreak>
-        <tRwatch>1</tRwatch>
-        <tRmem>1</tRmem>
-        <tRfunc>0</tRfunc>
-        <tRbox>1</tRbox>
-        <tRtrace>0</tRtrace>
-        <sRSysVw>1</sRSysVw>
-        <tRSysVw>1</tRSysVw>
-        <sRunDeb>0</sRunDeb>
-        <sLrtime>0</sLrtime>
-        <bEvRecOn>1</bEvRecOn>
-        <bSchkAxf>0</bSchkAxf>
-        <bTchkAxf>0</bTchkAxf>
-        <nTsel>4</nTsel>
-        <sDll></sDll>
-        <sDllPa></sDllPa>
-        <sDlgDll></sDlgDll>
-        <sDlgPa></sDlgPa>
-        <sIfile></sIfile>
-        <tDll></tDll>
-        <tDllPa></tDllPa>
-        <tDlgDll></tDlgDll>
-        <tDlgPa></tDlgPa>
-        <tIfile></tIfile>
-        <pMon>Segger\JL2CM3.dll</pMon>
-      </DebugOpt>
-      <TargetDriverDllRegistry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>JL2CM3</Key>
-          <Name>-U480200710 -O78 -S0 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx.flm -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm)</Name>
-        </SetRegEntry>
-        <SetRegEntry>
-          <Number>0</Number>
-          <Key>UL2CM3</Key>
-          <Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm))</Name>
-        </SetRegEntry>
-      </TargetDriverDllRegistry>
-      <Breakpoint/>
-      <Tracepoint>
-        <THDelay>0</THDelay>
-      </Tracepoint>
-      <DebugFlag>
-        <trace>0</trace>
-        <periodic>0</periodic>
-        <aLwin>0</aLwin>
-        <aCover>0</aCover>
-        <aSer1>0</aSer1>
-        <aSer2>0</aSer2>
-        <aPa>0</aPa>
-        <viewmode>0</viewmode>
-        <vrSel>0</vrSel>
-        <aSym>0</aSym>
-        <aTbox>0</aTbox>
-        <AscS1>0</AscS1>
-        <AscS2>0</AscS2>
-        <AscS3>0</AscS3>
-        <aSer3>0</aSer3>
-        <eProf>0</eProf>
-        <aLa>0</aLa>
-        <aPa1>0</aPa1>
-        <AscS4>0</AscS4>
-        <aSer4>0</aSer4>
-        <StkLoc>0</StkLoc>
-        <TrcWin>0</TrcWin>
-        <newCpu>0</newCpu>
-        <uProt>0</uProt>
-      </DebugFlag>
-      <LintExecutable></LintExecutable>
-      <LintConfigFile></LintConfigFile>
-      <bLintAuto>0</bLintAuto>
-      <bAutoGenD>0</bAutoGenD>
-      <LntExFlags>0</LntExFlags>
-      <pMisraName></pMisraName>
-      <pszMrule></pszMrule>
-      <pSingCmds></pSingCmds>
-      <pMultCmds></pMultCmds>
-      <pMisraNamep></pMisraNamep>
-      <pszMrulep></pszMrulep>
-      <pSingCmdsp></pSingCmdsp>
-      <pMultCmdsp></pMultCmdsp>
-    </TargetOption>
-  </Target>
-
-</ProjectOpt>

bsp/nrf51822/template.uvprojx

@@ -1,424 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
-
-  <SchemaVersion>2.1</SchemaVersion>
-
-  <Header>### uVision Project, (C) Keil Software</Header>
-
-  <Targets>
-    <Target>
-      <TargetName>rt-thread</TargetName>
-      <ToolsetNumber>0x4</ToolsetNumber>
-      <ToolsetName>ARM-ADS</ToolsetName>
-      <uAC6>0</uAC6>
-      <TargetOption>
-        <TargetCommonOption>
-          <Device>nRF51822_xxAA</Device>
-          <Vendor>Nordic Semiconductor</Vendor>
-          <PackID>NordicSemiconductor.nRF_DeviceFamilyPack.8.38.0</PackID>
-          <PackURL>http://developer.nordicsemi.com/nRF5_SDK/pieces/nRF_DeviceFamilyPack/</PackURL>
-          <Cpu>IROM(0x00000000,0x40000) IRAM(0x20000000,0x4000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
-          <FlashUtilSpec></FlashUtilSpec>
-          <StartupFile></StartupFile>
-          <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0nrf51xxx -FS00 -FL0200000 -FP0($$Device:nRF51822_xxAA$Flash\nrf51xxx.flm))</FlashDriverDll>
-          <DeviceId>0</DeviceId>
-          <RegisterFile>$$Device:nRF51822_xxAA$Device\Include\nrf.h</RegisterFile>
-          <MemoryEnv></MemoryEnv>
-          <Cmp></Cmp>
-          <Asm></Asm>
-          <Linker></Linker>
-          <OHString></OHString>
-          <InfinionOptionDll></InfinionOptionDll>
-          <SLE66CMisc></SLE66CMisc>
-          <SLE66AMisc></SLE66AMisc>
-          <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>$$Device:nRF51822_xxAA$SVD\nrf51.xml</SFDFile>
-          <bCustSvd>0</bCustSvd>
-          <UseEnv>0</UseEnv>
-          <BinPath></BinPath>
-          <IncludePath></IncludePath>
-          <LibPath></LibPath>
-          <RegisterFilePath></RegisterFilePath>
-          <DBRegisterFilePath></DBRegisterFilePath>
-          <TargetStatus>
-            <Error>0</Error>
-            <ExitCodeStop>0</ExitCodeStop>
-            <ButtonStop>0</ButtonStop>
-            <NotGenerated>0</NotGenerated>
-            <InvalidFlash>1</InvalidFlash>
-          </TargetStatus>
-          <OutputDirectory>.\build\</OutputDirectory>
-          <OutputName>template</OutputName>
-          <CreateExecutable>1</CreateExecutable>
-          <CreateLib>0</CreateLib>
-          <CreateHexFile>0</CreateHexFile>
-          <DebugInformation>1</DebugInformation>
-          <BrowseInformation>1</BrowseInformation>
-          <ListingPath>.\build\</ListingPath>
-          <HexFormatSelection>1</HexFormatSelection>
-          <Merge32K>0</Merge32K>
-          <CreateBatchFile>0</CreateBatchFile>
-          <BeforeCompile>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopU1X>0</nStopU1X>
-            <nStopU2X>0</nStopU2X>
-          </BeforeCompile>
-          <BeforeMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopB1X>0</nStopB1X>
-            <nStopB2X>0</nStopB2X>
-          </BeforeMake>
-          <AfterMake>
-            <RunUserProg1>0</RunUserProg1>
-            <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name></UserProg1Name>
-            <UserProg2Name></UserProg2Name>
-            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
-            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
-            <nStopA1X>0</nStopA1X>
-            <nStopA2X>0</nStopA2X>
-          </AfterMake>
-          <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString></SVCSIdString>
-        </TargetCommonOption>
-        <CommonProperty>
-          <UseCPPCompiler>0</UseCPPCompiler>
-          <RVCTCodeConst>0</RVCTCodeConst>
-          <RVCTZI>0</RVCTZI>
-          <RVCTOtherData>0</RVCTOtherData>
-          <ModuleSelection>0</ModuleSelection>
-          <IncludeInBuild>1</IncludeInBuild>
-          <AlwaysBuild>0</AlwaysBuild>
-          <GenerateAssemblyFile>0</GenerateAssemblyFile>
-          <AssembleAssemblyFile>0</AssembleAssemblyFile>
-          <PublicsOnly>0</PublicsOnly>
-          <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument></CustomArgument>
-          <IncludeLibraryModules></IncludeLibraryModules>
-          <ComprImg>1</ComprImg>
-        </CommonProperty>
-        <DllOption>
-          <SimDllName>SARMCM3.DLL</SimDllName>
-          <SimDllArguments> </SimDllArguments>
-          <SimDlgDll>DARMCM1.DLL</SimDlgDll>
-          <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
-          <TargetDllName>SARMCM3.DLL</TargetDllName>
-          <TargetDllArguments> </TargetDllArguments>
-          <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
-          <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
-        </DllOption>
-        <DebugOption>
-          <OPTHX>
-            <HexSelection>1</HexSelection>
-            <HexRangeLowAddress>0</HexRangeLowAddress>
-            <HexRangeHighAddress>0</HexRangeHighAddress>
-            <HexOffset>0</HexOffset>
-            <Oh166RecLen>16</Oh166RecLen>
-          </OPTHX>
-          <Simulator>
-            <UseSimulator>0</UseSimulator>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>1</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-            <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
-            <RestoreSysVw>1</RestoreSysVw>
-          </Simulator>
-          <Target>
-            <UseTarget>1</UseTarget>
-            <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
-            <RunToMain>1</RunToMain>
-            <RestoreBreakpoints>1</RestoreBreakpoints>
-            <RestoreWatchpoints>1</RestoreWatchpoints>
-            <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
-            <RestoreFunctions>0</RestoreFunctions>
-            <RestoreToolbox>1</RestoreToolbox>
-            <RestoreTracepoints>0</RestoreTracepoints>
-            <RestoreSysVw>1</RestoreSysVw>
-          </Target>
-          <RunDebugAfterBuild>0</RunDebugAfterBuild>
-          <TargetSelection>4</TargetSelection>
-          <SimDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-          </SimDlls>
-          <TargetDlls>
-            <CpuDll></CpuDll>
-            <CpuDllArguments></CpuDllArguments>
-            <PeripheralDll></PeripheralDll>
-            <PeripheralDllArguments></PeripheralDllArguments>
-            <InitializationFile></InitializationFile>
-            <Driver>Segger\JL2CM3.dll</Driver>
-          </TargetDlls>
-        </DebugOption>
-        <Utilities>
-          <Flash1>
-            <UseTargetDll>1</UseTargetDll>
-            <UseExternalTool>0</UseExternalTool>
-            <RunIndependent>0</RunIndependent>
-            <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
-            <Capability>1</Capability>
-            <DriverSelection>4096</DriverSelection>
-          </Flash1>
-          <bUseTDR>1</bUseTDR>
-          <Flash2>BIN\UL2CM3.DLL</Flash2>
-          <Flash3>"" ()</Flash3>
-          <Flash4></Flash4>
-          <pFcarmOut></pFcarmOut>
-          <pFcarmGrp></pFcarmGrp>
-          <pFcArmRoot></pFcArmRoot>
-          <FcArmLst>0</FcArmLst>
-        </Utilities>
-        <TargetArmAds>
-          <ArmAdsMisc>
-            <GenerateListings>0</GenerateListings>
-            <asHll>1</asHll>
-            <asAsm>1</asAsm>
-            <asMacX>1</asMacX>
-            <asSyms>1</asSyms>
-            <asFals>1</asFals>
-            <asDbgD>1</asDbgD>
-            <asForm>1</asForm>
-            <ldLst>0</ldLst>
-            <ldmm>1</ldmm>
-            <ldXref>1</ldXref>
-            <BigEnd>0</BigEnd>
-            <AdsALst>1</AdsALst>
-            <AdsACrf>1</AdsACrf>
-            <AdsANop>0</AdsANop>
-            <AdsANot>0</AdsANot>
-            <AdsLLst>1</AdsLLst>
-            <AdsLmap>1</AdsLmap>
-            <AdsLcgr>1</AdsLcgr>
-            <AdsLsym>1</AdsLsym>
-            <AdsLszi>1</AdsLszi>
-            <AdsLtoi>1</AdsLtoi>
-            <AdsLsun>1</AdsLsun>
-            <AdsLven>1</AdsLven>
-            <AdsLsxf>1</AdsLsxf>
-            <RvctClst>0</RvctClst>
-            <GenPPlst>0</GenPPlst>
-            <AdsCpuType>"Cortex-M0"</AdsCpuType>
-            <RvctDeviceName></RvctDeviceName>
-            <mOS>0</mOS>
-            <uocRom>0</uocRom>
-            <uocRam>0</uocRam>
-            <hadIROM>1</hadIROM>
-            <hadIRAM>1</hadIRAM>
-            <hadXRAM>0</hadXRAM>
-            <uocXRam>0</uocXRam>
-            <RvdsVP>0</RvdsVP>
-            <RvdsMve>0</RvdsMve>
-            <hadIRAM2>0</hadIRAM2>
-            <hadIROM2>0</hadIROM2>
-            <StupSel>8</StupSel>
-            <useUlib>0</useUlib>
-            <EndSel>0</EndSel>
-            <uLtcg>0</uLtcg>
-            <nSecure>0</nSecure>
-            <RoSelD>3</RoSelD>
-            <RwSelD>3</RwSelD>
-            <CodeSel>0</CodeSel>
-            <OptFeed>0</OptFeed>
-            <NoZi1>0</NoZi1>
-            <NoZi2>0</NoZi2>
-            <NoZi3>0</NoZi3>
-            <NoZi4>0</NoZi4>
-            <NoZi5>0</NoZi5>
-            <Ro1Chk>0</Ro1Chk>
-            <Ro2Chk>0</Ro2Chk>
-            <Ro3Chk>0</Ro3Chk>
-            <Ir1Chk>1</Ir1Chk>
-            <Ir2Chk>0</Ir2Chk>
-            <Ra1Chk>0</Ra1Chk>
-            <Ra2Chk>0</Ra2Chk>
-            <Ra3Chk>0</Ra3Chk>
-            <Im1Chk>1</Im1Chk>
-            <Im2Chk>0</Im2Chk>
-            <OnChipMemories>
-              <Ocm1>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm1>
-              <Ocm2>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm2>
-              <Ocm3>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm3>
-              <Ocm4>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm4>
-              <Ocm5>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm5>
-              <Ocm6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </Ocm6>
-              <IRAM>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x4000</Size>
-              </IRAM>
-              <IROM>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x40000</Size>
-              </IROM>
-              <XRAM>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </XRAM>
-              <OCR_RVCT1>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT1>
-              <OCR_RVCT2>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT2>
-              <OCR_RVCT3>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT3>
-              <OCR_RVCT4>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x40000</Size>
-              </OCR_RVCT4>
-              <OCR_RVCT5>
-                <Type>1</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT5>
-              <OCR_RVCT6>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT6>
-              <OCR_RVCT7>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT7>
-              <OCR_RVCT8>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT8>
-              <OCR_RVCT9>
-                <Type>0</Type>
-                <StartAddress>0x20000000</StartAddress>
-                <Size>0x4000</Size>
-              </OCR_RVCT9>
-              <OCR_RVCT10>
-                <Type>0</Type>
-                <StartAddress>0x0</StartAddress>
-                <Size>0x0</Size>
-              </OCR_RVCT10>
-            </OnChipMemories>
-            <RvctStartVector></RvctStartVector>
-          </ArmAdsMisc>
-          <Cads>
-            <interw>1</interw>
-            <Optim>1</Optim>
-            <oTime>0</oTime>
-            <SplitLS>0</SplitLS>
-            <OneElfS>1</OneElfS>
-            <Strict>0</Strict>
-            <EnumInt>0</EnumInt>
-            <PlainCh>0</PlainCh>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <wLevel>0</wLevel>
-            <uThumb>0</uThumb>
-            <uSurpInc>0</uSurpInc>
-            <uC99>0</uC99>
-            <uGnu>0</uGnu>
-            <useXO>0</useXO>
-            <v6Lang>1</v6Lang>
-            <v6LangP>1</v6LangP>
-            <vShortEn>1</vShortEn>
-            <vShortWch>1</vShortWch>
-            <v6Lto>0</v6Lto>
-            <v6WtE>0</v6WtE>
-            <v6Rtti>0</v6Rtti>
-            <VariousControls>
-              <MiscControls>--c99</MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Cads>
-          <Aads>
-            <interw>1</interw>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <thumb>0</thumb>
-            <SplitLS>0</SplitLS>
-            <SwStkChk>0</SwStkChk>
-            <NoWarn>0</NoWarn>
-            <uSurpInc>0</uSurpInc>
-            <useXO>0</useXO>
-            <uClangAs>0</uClangAs>
-            <VariousControls>
-              <MiscControls></MiscControls>
-              <Define></Define>
-              <Undefine></Undefine>
-              <IncludePath></IncludePath>
-            </VariousControls>
-          </Aads>
-          <LDads>
-            <umfTarg>1</umfTarg>
-            <Ropi>0</Ropi>
-            <Rwpi>0</Rwpi>
-            <noStLib>0</noStLib>
-            <RepFail>1</RepFail>
-            <useFile>0</useFile>
-            <TextAddressRange>0x08000000</TextAddressRange>
-            <DataAddressRange>0x20000000</DataAddressRange>
-            <pXoBase></pXoBase>
-            <ScatterFile></ScatterFile>
-            <IncludeLibs></IncludeLibs>
-            <IncludeLibsPath></IncludeLibsPath>
-            <Misc></Misc>
-            <LinkerInputFile></LinkerInputFile>
-            <DisabledWarnings></DisabledWarnings>
-          </LDads>
-        </TargetArmAds>
-      </TargetOption>
-    </Target>
-  </Targets>
-
-</Project>