bsp: nxp/mcxn947: Updated SDK to release v2.16.000

Signed-off-by: Yilin Sun <imi415@imi.moe>

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core0_features.h

@@ -1,15 +1,13 @@
 /*
 ** ###################################################################
 **     Version:             rev. 1.0, 2021-08-03
-**     Build:               b230131
+**     Build:               b240410
 **
 **     Abstract:
 **         Chip specific module features.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
-**     All rights reserved.
-**
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
@@ -31,22 +29,20 @@
 #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1)
 /* @brief CACHE64_POLSEL availability on the SoC. */
 #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1)
+/* @brief CDOG availability on the SoC. */
+#define FSL_FEATURE_SOC_CDOG_COUNT (2)
 /* @brief CMC availability on the SoC. */
 #define FSL_FEATURE_SOC_CMC_COUNT (1)
 /* @brief CRC availability on the SoC. */
 #define FSL_FEATURE_SOC_CRC_COUNT (1)
 /* @brief CTIMER availability on the SoC. */
 #define FSL_FEATURE_SOC_CTIMER_COUNT (5)
-/* @brief CDOG availability on the SoC. */
-#define FSL_FEATURE_SOC_CDOG_COUNT (2)
 /* @brief EDMA availability on the SoC. */
 #define FSL_FEATURE_SOC_EDMA_COUNT (2)
 /* @brief EIM availability on the SoC. */
 #define FSL_FEATURE_SOC_EIM_COUNT (1)
 /* @brief EMVSIM availability on the SoC. */
 #define FSL_FEATURE_SOC_EMVSIM_COUNT (2)
-/* @brief ENC availability on the SoC. */
-#define FSL_FEATURE_SOC_ENC_COUNT (2)
 /* @brief EVTG availability on the SoC. */
 #define FSL_FEATURE_SOC_EVTG_COUNT (1)
 /* @brief EWM availability on the SoC. */
@@ -65,12 +61,16 @@
 #define FSL_FEATURE_SOC_GPIO_COUNT (12)
 /* @brief SPC availability on the SoC. */
 #define FSL_FEATURE_SOC_SPC_COUNT (1)
+/* @brief HPDAC availability on the SoC. */
+#define FSL_FEATURE_SOC_HPDAC_COUNT (1)
 /* @brief I3C availability on the SoC. */
 #define FSL_FEATURE_SOC_I3C_COUNT (2)
 /* @brief I2S availability on the SoC. */
 #define FSL_FEATURE_SOC_I2S_COUNT (2)
 /* @brief INPUTMUX availability on the SoC. */
 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief ITRC availability on the SoC. */
+#define FSL_FEATURE_SOC_ITRC_COUNT (1)
 /* @brief LPADC availability on the SoC. */
 #define FSL_FEATURE_SOC_LPADC_COUNT (2)
 /* @brief LPCMP availability on the SoC. */
@@ -101,6 +101,8 @@
 #define FSL_FEATURE_SOC_PDM_COUNT (1)
 /* @brief PINT availability on the SoC. */
 #define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief PKC availability on the SoC. */
+#define FSL_FEATURE_SOC_PKC_COUNT (1)
 /* @brief POWERQUAD availability on the SoC. */
 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
 /* @brief PORT availability on the SoC. */
@@ -109,20 +111,24 @@
 #define FSL_FEATURE_SOC_PWM_COUNT (2)
 /* @brief PUF availability on the SoC. */
 #define FSL_FEATURE_SOC_PUF_COUNT (4)
+/* @brief QDC availability on the SoC. */
+#define FSL_FEATURE_SOC_QDC_COUNT (2)
 /* @brief RTC availability on the SoC. */
-#define FSL_FEATURE_SOC_RTC_COUNT (2)
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
 /* @brief SCG availability on the SoC. */
 #define FSL_FEATURE_SOC_SCG_COUNT (1)
 /* @brief SCT availability on the SoC. */
 #define FSL_FEATURE_SOC_SCT_COUNT (1)
 /* @brief SEMA42 availability on the SoC. */
 #define FSL_FEATURE_SOC_SEMA42_COUNT (1)
+/* @brief SINC availability on the SoC. */
+#define FSL_FEATURE_SOC_SINC_COUNT (1)
 /* @brief SMARTDMA availability on the SoC. */
 #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1)
 /* @brief SYSCON availability on the SoC. */
 #define FSL_FEATURE_SOC_SYSCON_COUNT (1)
-/* @brief TRNG availability on the SoC. */
-#define FSL_FEATURE_SOC_TRNG_COUNT (1)
+/* @brief SYSPM availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSPM_COUNT (2)
 /* @brief TSI availability on the SoC. */
 #define FSL_FEATURE_SOC_TSI_COUNT (1)
 /* @brief USB availability on the SoC. */
@@ -178,6 +184,8 @@
 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
 /* @brief Has offset trim (register OFSTRIM). */
 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
+/* @brief OFSTRIM availability on the SoC. */
+#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2)
 /* @brief Has Trigger status register. */
 #define FSL_FEATURE_LPADC_HAS_TSTAT (1)
 /* @brief Has power select (bitfield CFG[PWRSEL]). */
@@ -192,6 +200,28 @@
 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
 /* @brief Conversion averaged bitfiled width. */
 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4)
+/* @brief Has B side channels. */
+#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1)
+/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1)
+/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1)
+/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1)
+/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1)
+/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */
+#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1)
+/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */
+#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1)
+/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1)
+/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1)
+/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1)
+/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */
+#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2)
 /* @brief Temperature sensor parameter A (slope). */
 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U)
 /* @brief Temperature sensor parameter B (offset). */
@@ -212,6 +242,8 @@
 
 /* FLEXCAN module features */
 
+/* @brief Has more than 64 MBs. */
+#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0)
 /* @brief Message buffer size */
 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32)
 /* @brief Has doze mode support (register bit field MCR[DOZE]). */
@@ -232,18 +264,13 @@
 #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
 /* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
 #define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1)
-/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a
- * specific moment during the arbitration process). */
+/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
-/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be
- * transmitted in a specific moment during the arbitration process). */
+/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0)
-/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus
- * when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle
- * state). */
+/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0)
-/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode
- * are entered during a Bus-Off state). */
+/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0)
 /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
 #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1)
@@ -263,6 +290,8 @@
 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32)
 /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */
 #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1)
+/* @brief FlexCAN maximum data rate. */
+#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (10000000)
 
 /* CDOG module features */
 
@@ -271,10 +300,31 @@
 
 /* CMC module features */
 
+/* @brief Has SRAM_DIS register */
+#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1)
+/* @brief Has BSR register */
+#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1)
 /* @brief Has RSTCNT register */
-#define FSL_FEATURE_CMC_HAS_RSTCNT_REGISTER (1)
-/* @brief Does not have SRAMCTL register */
-#define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1)
+#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1)
+/* @brief Has BLR register */
+#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1)
+/* @brief Has no bitfield FLASHWAKE in FLASHCR register */
+#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1)
+
+/* LPCMP module features */
+
+/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1)
+/* @brief Has IER RRF_IE bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1)
+/* @brief Has CSR RRF bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1)
+/* @brief Has Round Robin mode (related to existence of registers RRCR0). */
+#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1)
+/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */
+#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1)
+/* @brief Has no CCR0 CMP_STOP_EN bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (1)
 
 /* SYSPM module features */
 
@@ -282,6 +332,8 @@
 #define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0)
 /* @brief Temperature sensor parameter B (offset). */
 #define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0)
+/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */
+#define FSL_FEATURE_SYSPM_PMCR_COUNT (1)
 
 /* CTIMER module features */
 
@@ -295,6 +347,8 @@
 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)
 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
+/* @brief CTIMER Has register MSR */
+#define FSL_FEATURE_CTIMER_HAS_MSR (1)
 
 /* LPDAC module features */
 
@@ -310,59 +364,87 @@
 #define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3)
 /* @brief Has internal reference current options. */
 #define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1)
+/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */
+#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1)
 
 /* EDMA module features */
 
-/* @brief Total number of DMA channels on all modules. */
-#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (16)
-/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid
- * only for eDMA modules.) */
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
+/* @brief If 8 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief If 16 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
 /* @brief Has DMA_Error interrupt vector. */
 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
-/* @brief Has register access permission. */
-#define FSL_FEATURE_HAVE_DMA_CONTROL_REGISTER_ACCESS_PERMISSION (1)
-/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
-#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
+/* @brief If 64 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0)
+/* @brief whether has prot register */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0)
+/* @brief If 128 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0)
+/* @brief whether has MP channel mux */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0)
+/* @brief If 128 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0)
 /* @brief If channel clock controlled independently */
 #define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1)
-/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference
- * instance) */
+/* @brief Has register CH_CSR. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1)
+/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */
 #define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16)
+/* @brief Has channel mux */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1)
 /* @brief Has no register bit fields MP_CSR[EBW]. */
 #define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1)
-/* @brief If dma has channel mux */
-#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1)
+/* @brief Instance has channel mux */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1)
 /* @brief If dma has common clock gate */
 #define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0)
+/* @brief Has register CH_SBR. */
+#define FSL_FEATURE_EDMA_HAS_SBR (1)
 /* @brief If dma channel IRQ support parameter */
 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0)
 /* @brief Has no register bit fields CH_SBR[ATTR]. */
 #define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1)
-/* @brief If 8 bytes transfer supported. */
-#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
-/* @brief If 16 bytes transfer supported. */
-#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
-/* @brief If 64 bytes transfer supported. */
-#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1)
-
-/* DMA_TCD module features */
-
-/* @brief Has no supervisor access bit (CR). */
-#define FSL_FEATURE_DMA_TCD_HAS_NO_CR_SUP (1)
-/* @brief Has no oscillator enable bit (CR). */
-#define FSL_FEATURE_DMA_TCD_HAS_NO_CR_OSCE (1)
-
-/* ENC module features */
-
-/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */
-#define FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT (0)
-/* @brief Has register CTRL3. */
-#define FSL_FEATURE_ENC_HAS_CTRL3 (1)
-/* @brief Has register LASTEDGE or LASTEDGEH. */
-#define FSL_FEATURE_ENC_HAS_LASTEDGE (1)
-/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */
-#define FSL_FEATURE_ENC_HAS_POSDPER (1)
+/* @brief NBYTES must be multiple of 8 when using scatter gather. */
+#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0)
+/* @brief Has register bit field CH_CSR[SWAP]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0)
+/* @brief NBYTES must be multiple of 8 when using scatter gather. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0)
+/* @brief Instance has register bit field CH_CSR[SWAP]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0)
+/* @brief Has register bit fields MP_CSR[GMRC]. */
+#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1)
+/* @brief Has register bit field CH_SBR[INSTR]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0)
+/* @brief Instance has register bit field CH_SBR[INSTR]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0)
+/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE  (0)
+/* @brief Instance has register CH_MATTR. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0)
+/* @brief Has register bit field CH_CSR[SIGNEXT]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0)
+/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0)
+/* @brief Has register bit field TCD_CSR[BWC]. */
+#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1)
+/* @brief Instance has register bit field TCD_CSR[BWC]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1)
+/* @brief Has register bit fields TCD_CSR[TMC]. */
+#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0)
+/* @brief Instance has register bit fields TCD_CSR[TMC]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0)
+/* @brief Has no register bit fields CH_SBR[SEC]. */
+#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0)
+/* @brief edma5 has different tcd type. */
+#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0)
+/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16)
 
 /* EVTG module features */
 
@@ -375,6 +457,8 @@
 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */
 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
+/* @brief Has pin input output related registers */
+#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1)
 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
@@ -391,6 +475,8 @@
 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003)
 /* @brief Reset value of the FLEXIO_PARAM register */
 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808)
+/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */
+#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3)
 
 /* FLEXSPI module features */
 
@@ -404,6 +490,8 @@
 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0)
 /* @brief FlexSPI DMA needs multiple DES to transfer */
 #define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1)
+/* @brief FlexSPI AHB RX buffer size (byte) */
+#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048)
 
 /* GPIO module features */
 
@@ -421,7 +509,7 @@
 /* I3C module features */
 
 /* @brief Has TERM bitfile in MERRWARN register. */
-#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0)
+#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1)
 /* @brief SOC has no reset driver. */
 #define FSL_FEATURE_I3C_HAS_NO_RESET (0)
 /* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */
@@ -429,6 +517,13 @@
 /* @brief Register SCONFIG do not have IDRAND bitfield. */
 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0)
 
+/* INPUTMUX module features */
+
+/* @brief Inputmux has DMA Request Enable */
+#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1)
+/* @brief Inputmux has channel mux control */
+#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0)
+
 /* INTM module features */
 
 /* @brief Up to 4 programmable interrupt monitors */
@@ -449,6 +544,10 @@
 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
 /* @brief Has CCR1 (related to existence of registers CCR1). */
 #define FSL_FEATURE_LPSPI_HAS_CCR1 (1)
+/* @brief Has no PCSCFG bit in CFGR1 register */
+#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0)
+/* @brief Has no WIDTH bits in TCR register */
+#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0)
 
 /* LPTMR module features */
 
@@ -458,15 +557,20 @@
 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1)
 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1)
+/* @brief Do not has prescaler clock source 0. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0)
 /* @brief Do not has prescaler clock source 1. */
 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0)
+/* @brief Do not has prescaler clock source 2. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0)
+/* @brief Do not has prescaler clock source 3. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0)
 
 /* LPUART module features */
 
 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
-/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the
- * registers are 32-bit wide). */
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
@@ -486,8 +590,7 @@
 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
 /* @brief Baud rate fine adjustment is available. */
 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
-/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR],
- * BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
 /* @brief Baud rate oversampling is available. */
 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
@@ -499,13 +602,11 @@
 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8)
 /* @brief Supports two match addresses to filter incoming frames. */
 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
-/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are
- * 32-bit wide). */
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
-/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit
- * wide). */
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
@@ -552,7 +653,7 @@
 /* MRT module features */
 
 /* @brief number of channels. */
-#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS  (4)
 
 /* OPAMP module features */
 
@@ -569,7 +670,7 @@
 /* @brief Opamp has OPAMP_CTR TRIGMD bit */
 #define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (1)
 /* @brief OPAMP support reference buffer */
-#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U)
+#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1)
 
 /* PDM module features */
 
@@ -580,7 +681,7 @@
 /* @brief PDM FIFO WIDTH Size */
 #define FSL_FEATURE_PDM_FIFO_WIDTH (4)
 /* @brief PDM FIFO DEPTH Size */
-#define FSL_FEATURE_PDM_FIFO_DEPTH (8)
+#define FSL_FEATURE_PDM_FIFO_DEPTH (16)
 /* @brief PDM has RANGE_CTRL register */
 #define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1)
 /* @brief PDM Has Low Frequency */
@@ -591,6 +692,10 @@
 #define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1)
 /* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */
 #define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1)
+/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */
+#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0)
+/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */
+#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0)
 /* @brief PDM Has DC_OUT_CTRL */
 #define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1)
 /* @brief PDM Has Fixed DC CTRL VALUE. */
@@ -642,6 +747,8 @@
 #define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1)
 /* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */
 #define FSL_FEATURE_PORT_SUPPORT_EFT (1)
+/* @brief Function 0 is GPIO. */
+#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0)
 /* @brief Has drive strength control (register bit PCR[DSE]). */
 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
 /* @brief Defines width of PCR[MUX] field. */
@@ -661,6 +768,13 @@
 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
 
+/* PUF module features */
+
+/* @brief Puf Activation Code Address. */
+#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304)
+/* @brief Puf Activation Code Size. */
+#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000)
+
 /* PWM module features */
 
 /* @brief If (e)FlexPWM has module A channels (outputs). */
@@ -674,11 +788,34 @@
 /* @brief If (e)FlexPWM has mux trigger source select bit field. */
 #define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1)
 /* @brief Number of submodules in each (e)FlexPWM module. */
-#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
+#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4)
 /* @brief Number of fault channel in each (e)FlexPWM module. */
 #define FSL_FEATURE_PWM_FAULT_CH_COUNT (1)
 /* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */
 #define FSL_FEATURE_PWM_HAS_NO_WAITEN (1)
+/* @brief If (e)FlexPWM has phase delay feature. */
+#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1)
+/* @brief If (e)FlexPWM has input filter capture feature. */
+#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1)
+/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */
+#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1)
+/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */
+#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1)
+/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */
+#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1)
+
+/* QDC module features */
+
+/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */
+#define FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT (0)
+/* @brief Has register CTRL3. */
+#define FSL_FEATURE_QDC_HAS_CTRL3 (1)
+/* @brief Has register LASTEDGE or LASTEDGEH. */
+#define FSL_FEATURE_QDC_HAS_LASTEDGE (1)
+/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */
+#define FSL_FEATURE_QDC_HAS_POSDPER (1)
+/* @brief Has bitfiled FILT[FILT_PRSC]. */
+#define FSL_FEATURE_QDC_HAS_FILT_PRSC (1)
 
 /* RTC module features */
 
@@ -696,7 +833,7 @@
 #define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1)
 /* @brief Has CLKO_DIS bitfile in CTRL register. */
 #define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1)
-/* @brief Has Tamper in RTC. */
+/* @brief Has No Tamper in RTC. */
 #define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1)
 /* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */
 #define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1)
@@ -711,31 +848,26 @@
 
 /* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */
 #define FSL_FEATURE_SAI_HAS_FIFO (1)
-/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW],
- * RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
+/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
 #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8)
 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2)
-/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ],
- * RMR[RWM]). */
+/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
-/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR],
- * TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
+/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
-/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK],
- * RCR4[FPACK]). */
+/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
-/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields
- * TCR4[FCONT], RCR4[FCONT]). */
+/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
-/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning
- * flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
+/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
-/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE],
- * RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
+/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
+/* @brief Interrupt source number */
+#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1)
 /* @brief Has register of MCR. */
 #define FSL_FEATURE_SAI_HAS_MCR (1)
 /* @brief Has bit field MICS of the MCR register. */
@@ -748,6 +880,8 @@
 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1)
 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1)
+/* @brief Support synchronous with another SAI. */
+#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1)
 
 /* SCT module features */
 
@@ -765,20 +899,45 @@
 /* @brief Gate counts */
 #define FSL_FEATURE_SEMA42_GATE_COUNT (16)
 
+/* SINC module features */
+
+/* @brief SINC channel count. */
+#define FSL_FEATURE_SINC_CHANNEL_COUNT (5)
+/* @brief SINC CACFR register has bitfield ADMASEL. */
+#define FSL_FEATURE_SINC_CACFR_HAS_ADMASEL (1)
+/* @brief SINC CACFR register has no bitfield PTMUX. */
+#define FSL_FEATURE_SINC_CACFR_HAS_NO_PTMUX (1)
+
 /* SPC module features */
 
-/* @brief Has 2P4G power domain. */
-#define FSL_FEATURE_SPC_HAS_2P4G_POWER_DOMAIN (1)
-/* @brief Has SPC_CFG. */
-#define FSL_FEATURE_SPC_HAS_CFG_REGISTER (0)
-/* @brief Has core ldo vdd driver strength (register bit ACTIVE_CFG[CORELDO_VDD_DS]). */
+/* @brief Has DCDC */
+#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1)
+/* @brief Has SYS LDO */
+#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1)
+/* @brief Has IOVDD_LVDF */
+#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1)
+/* @brief Has COREVDD_HVDF */
+#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1)
+/* @brief Has CORELDO_VDD_DS */
 #define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1)
-/* @brief Has bias enable (register bit LP_CFG[WBIAS_EN]). */
-#define FSL_FEATURE_SPC_HAS_WBIAS_EN (0)
-/* @brief Set CORELDO_VDD_LVL to 0 then regulate to Under Drive Voltage (0.95v). */
-#define FSL_FEATURE_SPC_LDO_VOLTAGE_LEVEL_DECREASE (0)
-/* @brief Set DCDC_VDD_LVL to 0 then regulate to Low Under Voltage (1.25v). */
-#define FSL_FEATURE_SPC_DCDC_VOLTAGE_LEVEL_DECREASE (0)
+/* @brief Has LPBUFF_EN */
+#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1)
+/* @brief Has COREVDD_IVS_EN */
+#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1)
+/* @brief Has SWITCH_STATE */
+#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0)
+/* @brief Has SRAMRETLDO */
+#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0)
+/* @brief Has CFG register */
+#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0)
+/* @brief Has SRAMLDO_DPD_ON */
+#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0)
+/* @brief Has CNTRL register */
+#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1)
+/* @brief Has DPDOWN_PULLDOWN_DISABLE */
+#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1)
+/* @brief Has BLEED_EN */
+#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1)
 
 /* SYSCON module features */
 
@@ -795,28 +954,24 @@
 /* @brief Powerlib API is different with other series devices.. */
 #define FSL_FEATURE_POWERLIB_EXTEND (1)
 
-/* TRNG module features */
-
-/* @brief TRNG does not support SCR4L. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L (1)
-/* @brief TRNG does not support SCR5L. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L (1)
-/* @brief TRNG does not support SCR6L. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L (1)
-/* @brief TRNG does not support PKRMAX. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX (1)
-/* @brief TRNG does not support SAMP mode. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE (1)
-/* @brief TRNG does not support ACC. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1)
-/* @brief TRNG does not support SBLIM. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM (1)
-/* @brief TRNG supports reset control. */
-#define FSL_FEATURE_TRNG_HAS_RSTCTL (1)
-/* @brief TRNG does not support FOR_CLK mode. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE (1)
-/* @brief TRNG has two oscillators. */
-#define FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS (1)
+/* TRDC module features */
+
+/* @brief Process master count. */
+#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2)
+/* @brief TRDC instance has PID configuration or not. */
+#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0)
+/* @brief TRDC instance has MBC. */
+#define FSL_FEATURE_TRDC_HAS_MBC (1)
+/* @brief TRDC instance has MRC. */
+#define FSL_FEATURE_TRDC_HAS_MRC (0)
+/* @brief TRDC instance has TRDC_CR. */
+#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0)
+/* @brief TRDC instance has MDA_Wx_y_DFMT. */
+#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0)
+/* @brief TRDC instance has TRDC_FDID. */
+#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0)
+/* @brief TRDC instance has TRDC_FLW_CTL. */
+#define FSL_FEATURE_TRDC_HAS_FLW (0)
 
 /* TSI module features */
 
@@ -894,12 +1049,33 @@
 #define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1)
 /* @brief Has no VSELECT bit in VEND_SPEC register */
 #define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1)
+/* @brief Has no VS18 bit in HOST_CTRL_CAP register */
+#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0)
 
 /* UTICK module features */
 
 /* @brief UTICK does not support PD configure. */
 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
 
+/* VBAT module features */
+
+/* @brief Has STATUS register */
+#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1)
+/* @brief Has TAMPER register */
+#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1)
+/* @brief Has BANDGAP register */
+#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1)
+/* @brief Has LDOCTL register */
+#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1)
+/* @brief Has OSCCTL register */
+#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1)
+/* @brief Has SWICTL register */
+#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1)
+/* @brief Has CLKMON register */
+#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0)
+/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */
+#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0)
+
 /* WWDT module features */
 
 /* @brief Has no RESET register. */
@@ -908,3 +1084,4 @@
 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
 
 #endif /* _MCXN947_cm33_core0_FEATURES_H_ */
+

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/MCXN947_cm33_core1_features.h

@@ -1,15 +1,13 @@
 /*
 ** ###################################################################
 **     Version:             rev. 1.0, 2021-08-03
-**     Build:               b230131
+**     Build:               b240410
 **
 **     Abstract:
 **         Chip specific module features.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
-**     All rights reserved.
-**
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
@@ -31,22 +29,20 @@
 #define FSL_FEATURE_SOC_CACHE64_CTRL_COUNT (1)
 /* @brief CACHE64_POLSEL availability on the SoC. */
 #define FSL_FEATURE_SOC_CACHE64_POLSEL_COUNT (1)
+/* @brief CDOG availability on the SoC. */
+#define FSL_FEATURE_SOC_CDOG_COUNT (2)
 /* @brief CMC availability on the SoC. */
 #define FSL_FEATURE_SOC_CMC_COUNT (1)
 /* @brief CRC availability on the SoC. */
 #define FSL_FEATURE_SOC_CRC_COUNT (1)
 /* @brief CTIMER availability on the SoC. */
 #define FSL_FEATURE_SOC_CTIMER_COUNT (5)
-/* @brief CDOG availability on the SoC. */
-#define FSL_FEATURE_SOC_CDOG_COUNT (2)
 /* @brief EDMA availability on the SoC. */
 #define FSL_FEATURE_SOC_EDMA_COUNT (2)
 /* @brief EIM availability on the SoC. */
 #define FSL_FEATURE_SOC_EIM_COUNT (1)
 /* @brief EMVSIM availability on the SoC. */
 #define FSL_FEATURE_SOC_EMVSIM_COUNT (2)
-/* @brief ENC availability on the SoC. */
-#define FSL_FEATURE_SOC_ENC_COUNT (2)
 /* @brief EVTG availability on the SoC. */
 #define FSL_FEATURE_SOC_EVTG_COUNT (1)
 /* @brief EWM availability on the SoC. */
@@ -65,12 +61,16 @@
 #define FSL_FEATURE_SOC_GPIO_COUNT (12)
 /* @brief SPC availability on the SoC. */
 #define FSL_FEATURE_SOC_SPC_COUNT (1)
+/* @brief HPDAC availability on the SoC. */
+#define FSL_FEATURE_SOC_HPDAC_COUNT (1)
 /* @brief I3C availability on the SoC. */
 #define FSL_FEATURE_SOC_I3C_COUNT (2)
 /* @brief I2S availability on the SoC. */
 #define FSL_FEATURE_SOC_I2S_COUNT (2)
 /* @brief INPUTMUX availability on the SoC. */
 #define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief ITRC availability on the SoC. */
+#define FSL_FEATURE_SOC_ITRC_COUNT (1)
 /* @brief LPADC availability on the SoC. */
 #define FSL_FEATURE_SOC_LPADC_COUNT (2)
 /* @brief LPCMP availability on the SoC. */
@@ -101,6 +101,8 @@
 #define FSL_FEATURE_SOC_PDM_COUNT (1)
 /* @brief PINT availability on the SoC. */
 #define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief PKC availability on the SoC. */
+#define FSL_FEATURE_SOC_PKC_COUNT (1)
 /* @brief POWERQUAD availability on the SoC. */
 #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
 /* @brief PORT availability on the SoC. */
@@ -109,20 +111,24 @@
 #define FSL_FEATURE_SOC_PWM_COUNT (2)
 /* @brief PUF availability on the SoC. */
 #define FSL_FEATURE_SOC_PUF_COUNT (4)
+/* @brief QDC availability on the SoC. */
+#define FSL_FEATURE_SOC_QDC_COUNT (2)
 /* @brief RTC availability on the SoC. */
-#define FSL_FEATURE_SOC_RTC_COUNT (2)
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
 /* @brief SCG availability on the SoC. */
 #define FSL_FEATURE_SOC_SCG_COUNT (1)
 /* @brief SCT availability on the SoC. */
 #define FSL_FEATURE_SOC_SCT_COUNT (1)
 /* @brief SEMA42 availability on the SoC. */
 #define FSL_FEATURE_SOC_SEMA42_COUNT (1)
+/* @brief SINC availability on the SoC. */
+#define FSL_FEATURE_SOC_SINC_COUNT (1)
 /* @brief SMARTDMA availability on the SoC. */
 #define FSL_FEATURE_SOC_SMARTDMA_COUNT (1)
 /* @brief SYSCON availability on the SoC. */
 #define FSL_FEATURE_SOC_SYSCON_COUNT (1)
-/* @brief TRNG availability on the SoC. */
-#define FSL_FEATURE_SOC_TRNG_COUNT (1)
+/* @brief SYSPM availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSPM_COUNT (2)
 /* @brief TSI availability on the SoC. */
 #define FSL_FEATURE_SOC_TSI_COUNT (1)
 /* @brief USB availability on the SoC. */
@@ -178,6 +184,8 @@
 #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
 /* @brief Has offset trim (register OFSTRIM). */
 #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
+/* @brief OFSTRIM availability on the SoC. */
+#define FSL_FEATURE_LPADC_OFSTRIM_COUNT (2)
 /* @brief Has Trigger status register. */
 #define FSL_FEATURE_LPADC_HAS_TSTAT (1)
 /* @brief Has power select (bitfield CFG[PWRSEL]). */
@@ -192,6 +200,28 @@
 #define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0)
 /* @brief Conversion averaged bitfiled width. */
 #define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (4)
+/* @brief Has B side channels. */
+#define FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS (1)
+/* @brief Indicate whether the LPADC STAT register has trigger exception interrupt function (bitfield STAT[TEXC_INT]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_TEXC_INT (1)
+/* @brief Indicate whether the LPADC STAT register has trigger completion interrupt function (bitfield STAT[TCOMP_INT]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_TCOMP_INT (1)
+/* @brief Indicate whether the LPADC STAT register has calibration ready function (bitfield STAT[CAL_RDY]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_CAL_RDY (1)
+/* @brief Indicate whether the LPADC STAT register has ADC active function (bitfield STAT[ADC_ACTIVE]). */
+#define FSL_FEATURE_LPADC_HAS_STAT_ADC_ACTIVE (1)
+/* @brief Indicate whether the LPADC IE register has trigger exception interrupt enable function (bitfield IE[TEXC_IE]). */
+#define FSL_FEATURE_LPADC_HAS_IE_TEXC_IE (1)
+/* @brief Indicate whether the LPADC IE register has trigger completion interrupt enable function (bitfield IE[TCOMP_IE]). */
+#define FSL_FEATURE_LPADC_HAS_IE_TCOMP_IE (1)
+/* @brief Indicate whether the LPADC CFG register has trigger resume/restart enable function (bitfield CFG[TRES]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_TRES (1)
+/* @brief Indicate whether the LPADC CFG register has trigger command resume/restart enable function (bitfield CFG[TCMDRES]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_TCMDRES (1)
+/* @brief Indicate whether the LPADC CFG register has high priority trigger exception disable function (bitfield CFG[HPT_EXDI]). */
+#define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1)
+/* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */
+#define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2)
 /* @brief Temperature sensor parameter A (slope). */
 #define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (783U)
 /* @brief Temperature sensor parameter B (offset). */
@@ -212,6 +242,8 @@
 
 /* FLEXCAN module features */
 
+/* @brief Has more than 64 MBs. */
+#define FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB (0)
 /* @brief Message buffer size */
 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (32)
 /* @brief Has doze mode support (register bit field MCR[DOZE]). */
@@ -232,18 +264,13 @@
 #define FSL_FEATURE_FLEXCAN_SUPPORT_ENGINE_CLK_SEL_REMOVE (1)
 /* @brief Instance remove CAN Engine Clock Source Selection from unsupported part. */
 #define FSL_FEATURE_FLEXCAN_INSTANCE_SUPPORT_ENGINE_CLK_SEL_REMOVEn(x) (1)
-/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a
- * specific moment during the arbitration process). */
+/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
-/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be
- * transmitted in a specific moment during the arbitration process). */
+/* @brief Is affected by errata with ID 5829 (FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process). */
 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5829 (0)
-/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus
- * when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle
- * state). */
+/* @brief Is affected by errata with ID 6032 (FlexCAN: A frame with wrong ID or payload is transmitted into the CAN bus when the Message Buffer under transmission is either aborted or deactivated while the CAN bus is in the Bus Idle state). */
 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_6032 (0)
-/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode
- * are entered during a Bus-Off state). */
+/* @brief Is affected by errata with ID 9595 (FlexCAN: Corrupt frame possible if the Freeze Mode or the Low-Power Mode are entered during a Bus-Off state). */
 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_9595 (0)
 /* @brief Has CAN with Flexible Data rate (CAN FD) protocol. */
 #define FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE (1)
@@ -263,6 +290,8 @@
 #define FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO_FILTER_MAX_NUMBER (32)
 /* @brief Does not support Supervisor Mode (bitfield MCR[SUPV]. */
 #define FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT (1)
+/* @brief FlexCAN maximum data rate. */
+#define FSL_FEATURE_FLEXCAN_MAX_CANFD_BITRATE (10000000)
 
 /* CDOG module features */
 
@@ -271,10 +300,31 @@
 
 /* CMC module features */
 
+/* @brief Has SRAM_DIS register */
+#define FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG (1)
+/* @brief Has BSR register */
+#define FSL_FEATURE_MCX_CMC_HAS_BSR_REG (1)
 /* @brief Has RSTCNT register */
-#define FSL_FEATURE_CMC_HAS_RSTCNT_REGISTER (1)
-/* @brief Does not have SRAMCTL register */
-#define FSL_FEATURE_CMC_HAS_NO_SRAMCTL_REGISTER (1)
+#define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1)
+/* @brief Has BLR register */
+#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1)
+/* @brief Has no bitfield FLASHWAKE in FLASHCR register */
+#define FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE (1)
+
+/* LPCMP module features */
+
+/* @brief Has CCR1 FUNC_CLK_SEL bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL (1)
+/* @brief Has IER RRF_IE bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_IER_RRF_IE (1)
+/* @brief Has CSR RRF bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_CSR_RRF (1)
+/* @brief Has Round Robin mode (related to existence of registers RRCR0). */
+#define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1)
+/* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */
+#define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1)
+/* @brief Has no CCR0 CMP_STOP_EN bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (1)
 
 /* SYSPM module features */
 
@@ -282,6 +332,8 @@
 #define FSL_FEATURE_SYSPM_HAS_PMCR_DCIFSH (0)
 /* @brief Temperature sensor parameter B (offset). */
 #define FSL_FEATURE_SYSPM_HAS_PMCR_RICTR (0)
+/* @brief Number of PMCR registers signals number of performance monitors available in single SYSPM instance. */
+#define FSL_FEATURE_SYSPM_PMCR_COUNT (1)
 
 /* CTIMER module features */
 
@@ -295,6 +347,8 @@
 #define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0)
 /* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */
 #define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1)
+/* @brief CTIMER Has register MSR */
+#define FSL_FEATURE_CTIMER_HAS_MSR (1)
 
 /* LPDAC module features */
 
@@ -310,59 +364,87 @@
 #define FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC (3)
 /* @brief Has internal reference current options. */
 #define FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT (1)
+/* @brief Support Period trigger mode DAC (bitfield IER[PTGCOCO_IE]). */
+#define FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE (1)
 
 /* EDMA module features */
 
-/* @brief Total number of DMA channels on all modules. */
-#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (16)
-/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid
- * only for eDMA modules.) */
+/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
+/* @brief If 8 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
+/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
+/* @brief If 16 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
 /* @brief Has DMA_Error interrupt vector. */
 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
-/* @brief Has register access permission. */
-#define FSL_FEATURE_HAVE_DMA_CONTROL_REGISTER_ACCESS_PERMISSION (1)
-/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
-#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
+/* @brief If 64 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (0)
+/* @brief whether has prot register */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0)
+/* @brief If 128 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (0)
+/* @brief whether has MP channel mux */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0)
+/* @brief If 128 bytes transfer supported. */
+#define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (0)
 /* @brief If channel clock controlled independently */
 #define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1)
-/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference
- * instance) */
+/* @brief Has register CH_CSR. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1)
+/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */
 #define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (16)
+/* @brief Has channel mux */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1)
 /* @brief Has no register bit fields MP_CSR[EBW]. */
 #define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1)
-/* @brief If dma has channel mux */
-#define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1)
+/* @brief Instance has channel mux */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1)
 /* @brief If dma has common clock gate */
 #define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0)
+/* @brief Has register CH_SBR. */
+#define FSL_FEATURE_EDMA_HAS_SBR (1)
 /* @brief If dma channel IRQ support parameter */
 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0)
 /* @brief Has no register bit fields CH_SBR[ATTR]. */
 #define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1)
-/* @brief If 8 bytes transfer supported. */
-#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (1)
-/* @brief If 16 bytes transfer supported. */
-#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
-/* @brief If 64 bytes transfer supported. */
-#define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1)
-
-/* DMA_TCD module features */
-
-/* @brief Has no supervisor access bit (CR). */
-#define FSL_FEATURE_DMA_TCD_HAS_NO_CR_SUP (1)
-/* @brief Has no oscillator enable bit (CR). */
-#define FSL_FEATURE_DMA_TCD_HAS_NO_CR_OSCE (1)
-
-/* ENC module features */
-
-/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */
-#define FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT (0)
-/* @brief Has register CTRL3. */
-#define FSL_FEATURE_ENC_HAS_CTRL3 (1)
-/* @brief Has register LASTEDGE or LASTEDGEH. */
-#define FSL_FEATURE_ENC_HAS_LASTEDGE (1)
-/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */
-#define FSL_FEATURE_ENC_HAS_POSDPER (1)
+/* @brief NBYTES must be multiple of 8 when using scatter gather. */
+#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0)
+/* @brief Has register bit field CH_CSR[SWAP]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0)
+/* @brief NBYTES must be multiple of 8 when using scatter gather. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0)
+/* @brief Instance has register bit field CH_CSR[SWAP]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0)
+/* @brief Has register bit fields MP_CSR[GMRC]. */
+#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1)
+/* @brief Has register bit field CH_SBR[INSTR]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0)
+/* @brief Instance has register bit field CH_SBR[INSTR]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(x) (0)
+/* @brief Has register bit fields CH_MATTR[WCACHE], CH_MATTR[RCACHE]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMORY_ATTRIBUTE  (0)
+/* @brief Instance has register CH_MATTR. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(x) (0)
+/* @brief Has register bit field CH_CSR[SIGNEXT]. */
+#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION (0)
+/* @brief Instance Has register bit field CH_CSR[SIGNEXT]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SIGN_EXTENSIONn(x) (0)
+/* @brief Has register bit field TCD_CSR[BWC]. */
+#define FSL_FEATURE_EDMA_HAS_BANDWIDTH (1)
+/* @brief Instance has register bit field TCD_CSR[BWC]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_BANDWIDTHn(x) (1)
+/* @brief Has register bit fields TCD_CSR[TMC]. */
+#define FSL_FEATURE_EDMA_HAS_TRANSFER_MODE (0)
+/* @brief Instance has register bit fields TCD_CSR[TMC]. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0)
+/* @brief Has no register bit fields CH_SBR[SEC]. */
+#define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (0)
+/* @brief edma5 has different tcd type. */
+#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0)
+/* @brief Number of DMA channels with asynchronous request capability. (Valid only for eDMA modules.) */
+#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (16)
 
 /* EVTG module features */
 
@@ -375,6 +457,8 @@
 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */
 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
+/* @brief Has pin input output related registers */
+#define FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER (1)
 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
@@ -391,6 +475,8 @@
 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x2010003)
 /* @brief Reset value of the FLEXIO_PARAM register */
 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x8200808)
+/* @brief Represent the bit width of the TIMDCE field (FLEXIO_TIMCFGLn[TIMDEC]) */
+#define FSL_FEATURE_FLEXIO_TIMCFG_TIMDCE_FIELD_WIDTH (3)
 
 /* FLEXSPI module features */
 
@@ -404,6 +490,8 @@
 #define FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_ATDFEN (0)
 /* @brief FlexSPI DMA needs multiple DES to transfer */
 #define FSL_FEATURE_FLEXSPI_DMA_MULTIPLE_DES (1)
+/* @brief FlexSPI AHB RX buffer size (byte) */
+#define FSL_FEATURE_FLEXSPI_AHB_RX_BUFFER_SIZEn(x) (2048)
 
 /* GPIO module features */
 
@@ -421,7 +509,7 @@
 /* I3C module features */
 
 /* @brief Has TERM bitfile in MERRWARN register. */
-#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (0)
+#define FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM (1)
 /* @brief SOC has no reset driver. */
 #define FSL_FEATURE_I3C_HAS_NO_RESET (0)
 /* @brief Use fixed BAMATCH count, do not provide editable BAMATCH. */
@@ -429,6 +517,13 @@
 /* @brief Register SCONFIG do not have IDRAND bitfield. */
 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (0)
 
+/* INPUTMUX module features */
+
+/* @brief Inputmux has DMA Request Enable */
+#define FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA (1)
+/* @brief Inputmux has channel mux control */
+#define FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX (0)
+
 /* INTM module features */
 
 /* @brief Up to 4 programmable interrupt monitors */
@@ -449,6 +544,10 @@
 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
 /* @brief Has CCR1 (related to existence of registers CCR1). */
 #define FSL_FEATURE_LPSPI_HAS_CCR1 (1)
+/* @brief Has no PCSCFG bit in CFGR1 register */
+#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0)
+/* @brief Has no WIDTH bits in TCR register */
+#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0)
 
 /* LPTMR module features */
 
@@ -458,15 +557,20 @@
 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1)
 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1)
+/* @brief Do not has prescaler clock source 0. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0)
 /* @brief Do not has prescaler clock source 1. */
 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0)
+/* @brief Do not has prescaler clock source 2. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0)
+/* @brief Do not has prescaler clock source 3. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0)
 
 /* LPUART module features */
 
 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
-/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the
- * registers are 32-bit wide). */
+/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
@@ -486,8 +590,7 @@
 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1)
 /* @brief Baud rate fine adjustment is available. */
 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
-/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR],
- * BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
+/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
 /* @brief Baud rate oversampling is available. */
 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
@@ -499,13 +602,11 @@
 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (8)
 /* @brief Supports two match addresses to filter incoming frames. */
 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
-/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are
- * 32-bit wide). */
+/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
-/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit
- * wide). */
+/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
@@ -552,7 +653,7 @@
 /* MRT module features */
 
 /* @brief number of channels. */
-#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS  (4)
 
 /* OPAMP module features */
 
@@ -569,7 +670,7 @@
 /* @brief Opamp has OPAMP_CTR TRIGMD bit */
 #define FSL_FEATURE_OPAMP_HAS_OPAMP_CTR_TRIGMD (1)
 /* @brief OPAMP support reference buffer */
-#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1U)
+#define FSL_FEATURE_OPAMP_HAS_SUPPORT_REFERENCE_BUFFER (1)
 
 /* PDM module features */
 
@@ -580,7 +681,7 @@
 /* @brief PDM FIFO WIDTH Size */
 #define FSL_FEATURE_PDM_FIFO_WIDTH (4)
 /* @brief PDM FIFO DEPTH Size */
-#define FSL_FEATURE_PDM_FIFO_DEPTH (8)
+#define FSL_FEATURE_PDM_FIFO_DEPTH (16)
 /* @brief PDM has RANGE_CTRL register */
 #define FSL_FEATURE_PDM_HAS_RANGE_CTRL (1)
 /* @brief PDM Has Low Frequency */
@@ -591,6 +692,10 @@
 #define FSL_FEATURE_PDM_HAS_NO_MINIMUM_CLKDIV (1)
 /* @brief PDM Has no FIR_RDY Bitfield In PDM STAT Register */
 #define FSL_FEATURE_PDM_HAS_NO_FIR_RDY (1)
+/* @brief PDM Has no DOZEN Bitfield In PDM CTRL_1 Register */
+#define FSL_FEATURE_PDM_HAS_NO_DOZEN (0)
+/* @brief PDM Has DEC_BYPASS Bitfield In PDM CTRL_2 Register */
+#define FSL_FEATURE_PDM_HAS_DECIMATION_FILTER_BYPASS (0)
 /* @brief PDM Has DC_OUT_CTRL */
 #define FSL_FEATURE_PDM_HAS_DC_OUT_CTRL (1)
 /* @brief PDM Has Fixed DC CTRL VALUE. */
@@ -642,6 +747,8 @@
 #define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1)
 /* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */
 #define FSL_FEATURE_PORT_SUPPORT_EFT (1)
+/* @brief Function 0 is GPIO. */
+#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0)
 /* @brief Has drive strength control (register bit PCR[DSE]). */
 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
 /* @brief Defines width of PCR[MUX] field. */
@@ -661,6 +768,13 @@
 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
 
+/* PUF module features */
+
+/* @brief Puf Activation Code Address. */
+#define FSL_FEATURE_PUF_ACTIVATION_CODE_ADDRESS (17826304)
+/* @brief Puf Activation Code Size. */
+#define FSL_FEATURE_PUF_ACTIVATION_CODE_SIZE (1000)
+
 /* PWM module features */
 
 /* @brief If (e)FlexPWM has module A channels (outputs). */
@@ -674,11 +788,34 @@
 /* @brief If (e)FlexPWM has mux trigger source select bit field. */
 #define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1)
 /* @brief Number of submodules in each (e)FlexPWM module. */
-#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
+#define FSL_FEATURE_PWM_SUBMODULE_COUNT (4)
 /* @brief Number of fault channel in each (e)FlexPWM module. */
 #define FSL_FEATURE_PWM_FAULT_CH_COUNT (1)
 /* @brief (e)FlexPWM has no WAITEN Bitfield In CTRL2 Register. */
 #define FSL_FEATURE_PWM_HAS_NO_WAITEN (1)
+/* @brief If (e)FlexPWM has phase delay feature. */
+#define FSL_FEATURE_PWM_HAS_PHASE_DELAY (1)
+/* @brief If (e)FlexPWM has input filter capture feature. */
+#define FSL_FEATURE_PWM_HAS_INPUT_FILTER_CAPTURE (1)
+/* @brief If (e)FlexPWM has module capture functionality on A channels (inputs). */
+#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELA (1)
+/* @brief If (e)FlexPWM has module capture functionality on B channels (inputs). */
+#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELB (1)
+/* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */
+#define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1)
+
+/* QDC module features */
+
+/* @brief Has no simultaneous PHASEA and PHASEB change interrupt (register bit field CTRL2[SABIE] and CTRL2[SABIRQ]). */
+#define FSL_FEATURE_QDC_HAS_NO_CTRL2_SAB_INT (0)
+/* @brief Has register CTRL3. */
+#define FSL_FEATURE_QDC_HAS_CTRL3 (1)
+/* @brief Has register LASTEDGE or LASTEDGEH. */
+#define FSL_FEATURE_QDC_HAS_LASTEDGE (1)
+/* @brief Has register POSDPERBFR, POSDPERH, or POSDPER. */
+#define FSL_FEATURE_QDC_HAS_POSDPER (1)
+/* @brief Has bitfiled FILT[FILT_PRSC]. */
+#define FSL_FEATURE_QDC_HAS_FILT_PRSC (1)
 
 /* RTC module features */
 
@@ -696,7 +833,7 @@
 #define FSL_FEATURE_RTC_HAS_CLOCK_SELECT (1)
 /* @brief Has CLKO_DIS bitfile in CTRL register. */
 #define FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE (1)
-/* @brief Has Tamper in RTC. */
+/* @brief Has No Tamper in RTC. */
 #define FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE (1)
 /* @brief Has CPU_LOW_VOLT bitfile in STATUS register. */
 #define FSL_FEATURE_RTC_HAS_NO_CPU_LOW_VOLT_FLAG (1)
@@ -711,31 +848,26 @@
 
 /* @brief SAI has FIFO in this soc (register bit fields TCR1[TFW]. */
 #define FSL_FEATURE_SAI_HAS_FIFO (1)
-/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW],
- * RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
+/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
 #define FSL_FEATURE_SAI_FIFO_COUNTn(x) (8)
 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2)
-/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ],
- * RMR[RWM]). */
+/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
-/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR],
- * TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
+/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
-/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK],
- * RCR4[FPACK]). */
+/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
-/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields
- * TCR4[FCONT], RCR4[FCONT]). */
+/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
-/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning
- * flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
+/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
-/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE],
- * RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
+/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (0)
+/* @brief Interrupt source number */
+#define FSL_FEATURE_SAI_INT_SOURCE_NUM (1)
 /* @brief Has register of MCR. */
 #define FSL_FEATURE_SAI_HAS_MCR (1)
 /* @brief Has bit field MICS of the MCR register. */
@@ -748,6 +880,8 @@
 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (1)
 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1)
+/* @brief Support synchronous with another SAI. */
+#define FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI (1)
 
 /* SCT module features */
 
@@ -765,20 +899,45 @@
 /* @brief Gate counts */
 #define FSL_FEATURE_SEMA42_GATE_COUNT (16)
 
+/* SINC module features */
+
+/* @brief SINC channel count. */
+#define FSL_FEATURE_SINC_CHANNEL_COUNT (5)
+/* @brief SINC CACFR register has bitfield ADMASEL. */
+#define FSL_FEATURE_SINC_CACFR_HAS_ADMASEL (1)
+/* @brief SINC CACFR register has no bitfield PTMUX. */
+#define FSL_FEATURE_SINC_CACFR_HAS_NO_PTMUX (1)
+
 /* SPC module features */
 
-/* @brief Has 2P4G power domain. */
-#define FSL_FEATURE_SPC_HAS_2P4G_POWER_DOMAIN (1)
-/* @brief Has SPC_CFG. */
-#define FSL_FEATURE_SPC_HAS_CFG_REGISTER (0)
-/* @brief Has core ldo vdd driver strength (register bit ACTIVE_CFG[CORELDO_VDD_DS]). */
+/* @brief Has DCDC */
+#define FSL_FEATURE_MCX_SPC_HAS_DCDC (1)
+/* @brief Has SYS LDO */
+#define FSL_FEATURE_MCX_SPC_HAS_SYS_LDO (1)
+/* @brief Has IOVDD_LVDF */
+#define FSL_FEATURE_MCX_SPC_HAS_IOVDD_VD (1)
+/* @brief Has COREVDD_HVDF */
+#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_HVD (1)
+/* @brief Has CORELDO_VDD_DS */
 #define FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS (1)
-/* @brief Has bias enable (register bit LP_CFG[WBIAS_EN]). */
-#define FSL_FEATURE_SPC_HAS_WBIAS_EN (0)
-/* @brief Set CORELDO_VDD_LVL to 0 then regulate to Under Drive Voltage (0.95v). */
-#define FSL_FEATURE_SPC_LDO_VOLTAGE_LEVEL_DECREASE (0)
-/* @brief Set DCDC_VDD_LVL to 0 then regulate to Low Under Voltage (1.25v). */
-#define FSL_FEATURE_SPC_DCDC_VOLTAGE_LEVEL_DECREASE (0)
+/* @brief Has LPBUFF_EN */
+#define FSL_FEATURE_MCX_SPC_HAS_LPBUFF_EN_BIT (1)
+/* @brief Has COREVDD_IVS_EN */
+#define FSL_FEATURE_MCX_SPC_HAS_COREVDD_IVS_EN_BIT (1)
+/* @brief Has SWITCH_STATE */
+#define FSL_FEATURE_MCX_SPC_HAS_SWITCH_STATE_BIT (0)
+/* @brief Has SRAMRETLDO */
+#define FSL_FEATURE_MCX_SPC_HAS_SRAMRETLDO_REG (0)
+/* @brief Has CFG register */
+#define FSL_FEATURE_MCX_SPC_HAS_CFG_REG (0)
+/* @brief Has SRAMLDO_DPD_ON */
+#define FSL_FEATURE_MCX_SPC_HAS_SRAMLDO_DPD_ON_BIT (0)
+/* @brief Has CNTRL register */
+#define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (1)
+/* @brief Has DPDOWN_PULLDOWN_DISABLE */
+#define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (1)
+/* @brief Has BLEED_EN */
+#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (1)
 
 /* SYSCON module features */
 
@@ -795,28 +954,24 @@
 /* @brief Powerlib API is different with other series devices.. */
 #define FSL_FEATURE_POWERLIB_EXTEND (1)
 
-/* TRNG module features */
-
-/* @brief TRNG does not support SCR4L. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR4L (1)
-/* @brief TRNG does not support SCR5L. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR5L (1)
-/* @brief TRNG does not support SCR6L. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SCR6L (1)
-/* @brief TRNG does not support PKRMAX. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_PKRMAX (1)
-/* @brief TRNG does not support SAMP mode. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_SAMP_MODE (1)
-/* @brief TRNG does not support ACC. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_ACC (1)
-/* @brief TRNG does not support SBLIM. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_SBLIM (1)
-/* @brief TRNG supports reset control. */
-#define FSL_FEATURE_TRNG_HAS_RSTCTL (1)
-/* @brief TRNG does not support FOR_CLK mode. */
-#define FSL_FEATURE_TRNG_HAS_NO_TRNG_MCTL_FOR_CLK_MODE (1)
-/* @brief TRNG has two oscillators. */
-#define FSL_FEATURE_TRNG_HAS_DUAL_OSCILATORS (1)
+/* TRDC module features */
+
+/* @brief Process master count. */
+#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2)
+/* @brief TRDC instance has PID configuration or not. */
+#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0)
+/* @brief TRDC instance has MBC. */
+#define FSL_FEATURE_TRDC_HAS_MBC (1)
+/* @brief TRDC instance has MRC. */
+#define FSL_FEATURE_TRDC_HAS_MRC (0)
+/* @brief TRDC instance has TRDC_CR. */
+#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0)
+/* @brief TRDC instance has MDA_Wx_y_DFMT. */
+#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0)
+/* @brief TRDC instance has TRDC_FDID. */
+#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0)
+/* @brief TRDC instance has TRDC_FLW_CTL. */
+#define FSL_FEATURE_TRDC_HAS_FLW (0)
 
 /* TSI module features */
 
@@ -894,12 +1049,33 @@
 #define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1)
 /* @brief Has no VSELECT bit in VEND_SPEC register */
 #define FSL_FEATURE_USDHC_HAS_NO_VOLTAGE_SELECT (1)
+/* @brief Has no VS18 bit in HOST_CTRL_CAP register */
+#define FSL_FEATURE_USDHC_HAS_NO_VS18 (0)
 
 /* UTICK module features */
 
 /* @brief UTICK does not support PD configure. */
 #define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
 
+/* VBAT module features */
+
+/* @brief Has STATUS register */
+#define FSL_FEATURE_MCX_VBAT_HAS_STATUS_REG (1)
+/* @brief Has TAMPER register */
+#define FSL_FEATURE_MCX_VBAT_HAS_TAMPER_REG (1)
+/* @brief Has BANDGAP register */
+#define FSL_FEATURE_MCX_VBAT_HAS_BANDGAP_TIMER (1)
+/* @brief Has LDOCTL register */
+#define FSL_FEATURE_MCX_VBAT_HAS_LDOCTL_REG (1)
+/* @brief Has OSCCTL register */
+#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTL_REG (1)
+/* @brief Has SWICTL register */
+#define FSL_FEATURE_MCX_VBAT_HAS_SWICTL_REG (1)
+/* @brief Has CLKMON register */
+#define FSL_FEATURE_MCX_VBAT_HAS_CLKMON_REG (0)
+/* @brief Has FINE_AMP_GAIN bitfield in register OSCCTLA */
+#define FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT (0)
+
 /* WWDT module features */
 
 /* @brief Has no RESET register. */
@@ -908,3 +1084,4 @@
 #define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
 
 #endif /* _MCXN947_cm33_core1_FEATURES_H_ */
+

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core0.S

@@ -2,15 +2,13 @@
 /*  @file:    startup_MCXN947_cm33_core0.s                                   */
 /*  @purpose: CMSIS Cortex-M33 Core Device Startup File                      */
 /*            MCXN947_cm33_core0                                             */
-/*  @version: 1.0                                                            */
-/*  @date:    2022-10-1                                                      */
-/*  @build:   b230131                                                        */
+/*  @version: 2.0                                                            */
+/*  @date:    2023-2-1                                                       */
+/*  @build:   b240410                                                        */
 /* ------------------------------------------------------------------------- */
 /*                                                                           */
 /* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
-/* Copyright 2016-2023 NXP                                                   */
-/* All rights reserved.                                                      */
-/*                                                                           */
+/* Copyright 2016-2024 NXP                                                   */
 /* SPDX-License-Identifier: BSD-3-Clause                                     */
 /*****************************************************************************/
 /* Version: GCC for ARM Embedded Processors                                  */
@@ -165,14 +163,14 @@ __Vectors:
     .long   FLEXPWM1_SUBMODULE1_IRQHandler                  /* FlexPWM1 Submodule 1 capture/compare/reload interrupt*/
     .long   FLEXPWM1_SUBMODULE2_IRQHandler                  /* FlexPWM1 Submodule 2 capture/compare/reload interrupt*/
     .long   FLEXPWM1_SUBMODULE3_IRQHandler                  /* FlexPWM1 Submodule 3 capture/compare/reload interrupt*/
-    .long   ENC0_COMPARE_IRQHandler                         /* ENC0_Compare interrupt*/
-    .long   ENC0_HOME_IRQHandler                            /* ENC0_Home interrupt*/
-    .long   ENC0_WDG_SAB_IRQHandler                         /* ENC0_WDG_IRQ/SAB interrupt*/
-    .long   ENC0_IDX_IRQHandler                             /* ENC0_IDX interrupt*/
-    .long   ENC1_COMPARE_IRQHandler                         /* ENC1_Compare interrupt*/
-    .long   ENC1_HOME_IRQHandler                            /* ENC1_Home interrupt*/
-    .long   ENC1_WDG_SAB_IRQHandler                         /* ENC1_WDG_IRQ/SAB interrupt*/
-    .long   ENC1_IDX_IRQHandler                             /* ENC1_IDX interrupt*/
+    .long   QDC0_COMPARE_IRQHandler                         /* QDC0_Compare interrupt*/
+    .long   QDC0_HOME_IRQHandler                            /* QDC0_Home interrupt*/
+    .long   QDC0_WDG_SAB_IRQHandler                         /* QDC0_WDG_IRQ/SAB interrupt*/
+    .long   QDC0_IDX_IRQHandler                             /* QDC0_IDX interrupt*/
+    .long   QDC1_COMPARE_IRQHandler                         /* QDC1_Compare interrupt*/
+    .long   QDC1_HOME_IRQHandler                            /* QDC1_Home interrupt*/
+    .long   QDC1_WDG_SAB_IRQHandler                         /* QDC1_WDG_IRQ/SAB interrupt*/
+    .long   QDC1_IDX_IRQHandler                             /* QDC1_IDX interrupt*/
     .long   ITRC0_IRQHandler                                /* Intrusion and Tamper Response Controller interrupt*/
     .long   BSP32_IRQHandler                                /* CoolFlux BSP32 interrupt*/
     .long   ELS_ERR_IRQHandler                              /* ELS error interrupt*/
@@ -191,8 +189,8 @@ __Vectors:
     .long   WUU_IRQHandler                                  /* Wake Up Unit interrupt*/
     .long   PORT_EFT_IRQHandler                             /* PORT0~5 EFT interrupt*/
     .long   ETB0_IRQHandler                                 /* ETB counter expires interrupt*/
-    .long   SM3_IRQHandler                                  /* Secure Generic Interface (SGI) SAFO interrupt */
-    .long   TRNG0_IRQHandler                                /* True Random Number Generator interrupt*/
+    .long   Reserved166_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved167_IRQHandler                          /* Reserved interrupt*/
     .long   WWDT0_IRQHandler                                /* Windowed Watchdog Timer 0 interrupt*/
     .long   WWDT1_IRQHandler                                /* Windowed Watchdog Timer 1 interrupt*/
     .long   CMC0_IRQHandler                                 /* Core Mode Controller interrupt*/
@@ -1399,75 +1397,75 @@ FLEXPWM1_SUBMODULE3_IRQHandler:
 
     .align 1
     .thumb_func
-    .weak ENC0_COMPARE_IRQHandler
-    .type ENC0_COMPARE_IRQHandler, %function
-ENC0_COMPARE_IRQHandler:
-    ldr   r0,=ENC0_COMPARE_DriverIRQHandler
+    .weak QDC0_COMPARE_IRQHandler
+    .type QDC0_COMPARE_IRQHandler, %function
+QDC0_COMPARE_IRQHandler:
+    ldr   r0,=QDC0_COMPARE_DriverIRQHandler
     bx    r0
-    .size ENC0_COMPARE_IRQHandler, . - ENC0_COMPARE_IRQHandler
+    .size QDC0_COMPARE_IRQHandler, . - QDC0_COMPARE_IRQHandler
 
     .align 1
     .thumb_func
-    .weak ENC0_HOME_IRQHandler
-    .type ENC0_HOME_IRQHandler, %function
-ENC0_HOME_IRQHandler:
-    ldr   r0,=ENC0_HOME_DriverIRQHandler
+    .weak QDC0_HOME_IRQHandler
+    .type QDC0_HOME_IRQHandler, %function
+QDC0_HOME_IRQHandler:
+    ldr   r0,=QDC0_HOME_DriverIRQHandler
     bx    r0
-    .size ENC0_HOME_IRQHandler, . - ENC0_HOME_IRQHandler
+    .size QDC0_HOME_IRQHandler, . - QDC0_HOME_IRQHandler
 
     .align 1
     .thumb_func
-    .weak ENC0_WDG_SAB_IRQHandler
-    .type ENC0_WDG_SAB_IRQHandler, %function
-ENC0_WDG_SAB_IRQHandler:
-    ldr   r0,=ENC0_WDG_SAB_DriverIRQHandler
+    .weak QDC0_WDG_SAB_IRQHandler
+    .type QDC0_WDG_SAB_IRQHandler, %function
+QDC0_WDG_SAB_IRQHandler:
+    ldr   r0,=QDC0_WDG_SAB_DriverIRQHandler
     bx    r0
-    .size ENC0_WDG_SAB_IRQHandler, . - ENC0_WDG_SAB_IRQHandler
+    .size QDC0_WDG_SAB_IRQHandler, . - QDC0_WDG_SAB_IRQHandler
 
     .align 1
     .thumb_func
-    .weak ENC0_IDX_IRQHandler
-    .type ENC0_IDX_IRQHandler, %function
-ENC0_IDX_IRQHandler:
-    ldr   r0,=ENC0_IDX_DriverIRQHandler
+    .weak QDC0_IDX_IRQHandler
+    .type QDC0_IDX_IRQHandler, %function
+QDC0_IDX_IRQHandler:
+    ldr   r0,=QDC0_IDX_DriverIRQHandler
     bx    r0
-    .size ENC0_IDX_IRQHandler, . - ENC0_IDX_IRQHandler
+    .size QDC0_IDX_IRQHandler, . - QDC0_IDX_IRQHandler
 
     .align 1
     .thumb_func
-    .weak ENC1_COMPARE_IRQHandler
-    .type ENC1_COMPARE_IRQHandler, %function
-ENC1_COMPARE_IRQHandler:
-    ldr   r0,=ENC1_COMPARE_DriverIRQHandler
+    .weak QDC1_COMPARE_IRQHandler
+    .type QDC1_COMPARE_IRQHandler, %function
+QDC1_COMPARE_IRQHandler:
+    ldr   r0,=QDC1_COMPARE_DriverIRQHandler
     bx    r0
-    .size ENC1_COMPARE_IRQHandler, . - ENC1_COMPARE_IRQHandler
+    .size QDC1_COMPARE_IRQHandler, . - QDC1_COMPARE_IRQHandler
 
     .align 1
     .thumb_func
-    .weak ENC1_HOME_IRQHandler
-    .type ENC1_HOME_IRQHandler, %function
-ENC1_HOME_IRQHandler:
-    ldr   r0,=ENC1_HOME_DriverIRQHandler
+    .weak QDC1_HOME_IRQHandler
+    .type QDC1_HOME_IRQHandler, %function
+QDC1_HOME_IRQHandler:
+    ldr   r0,=QDC1_HOME_DriverIRQHandler
     bx    r0
-    .size ENC1_HOME_IRQHandler, . - ENC1_HOME_IRQHandler
+    .size QDC1_HOME_IRQHandler, . - QDC1_HOME_IRQHandler
 
     .align 1
     .thumb_func
-    .weak ENC1_WDG_SAB_IRQHandler
-    .type ENC1_WDG_SAB_IRQHandler, %function
-ENC1_WDG_SAB_IRQHandler:
-    ldr   r0,=ENC1_WDG_SAB_DriverIRQHandler
+    .weak QDC1_WDG_SAB_IRQHandler
+    .type QDC1_WDG_SAB_IRQHandler, %function
+QDC1_WDG_SAB_IRQHandler:
+    ldr   r0,=QDC1_WDG_SAB_DriverIRQHandler
     bx    r0
-    .size ENC1_WDG_SAB_IRQHandler, . - ENC1_WDG_SAB_IRQHandler
+    .size QDC1_WDG_SAB_IRQHandler, . - QDC1_WDG_SAB_IRQHandler
 
     .align 1
     .thumb_func
-    .weak ENC1_IDX_IRQHandler
-    .type ENC1_IDX_IRQHandler, %function
-ENC1_IDX_IRQHandler:
-    ldr   r0,=ENC1_IDX_DriverIRQHandler
+    .weak QDC1_IDX_IRQHandler
+    .type QDC1_IDX_IRQHandler, %function
+QDC1_IDX_IRQHandler:
+    ldr   r0,=QDC1_IDX_DriverIRQHandler
     bx    r0
-    .size ENC1_IDX_IRQHandler, . - ENC1_IDX_IRQHandler
+    .size QDC1_IDX_IRQHandler, . - QDC1_IDX_IRQHandler
 
     .align 1
     .thumb_func
@@ -1633,21 +1631,21 @@ ETB0_IRQHandler:
 
     .align 1
     .thumb_func
-    .weak SM3_IRQHandler
-    .type SM3_IRQHandler, %function
-SM3_IRQHandler:
-    ldr   r0,=SM3_DriverIRQHandler
+    .weak Reserved166_IRQHandler
+    .type Reserved166_IRQHandler, %function
+Reserved166_IRQHandler:
+    ldr   r0,=Reserved166_DriverIRQHandler
     bx    r0
-    .size SM3_IRQHandler, . - SM3_IRQHandler
+    .size Reserved166_IRQHandler, . - Reserved166_IRQHandler
 
     .align 1
     .thumb_func
-    .weak TRNG0_IRQHandler
-    .type TRNG0_IRQHandler, %function
-TRNG0_IRQHandler:
-    ldr   r0,=TRNG0_DriverIRQHandler
+    .weak Reserved167_IRQHandler
+    .type Reserved167_IRQHandler, %function
+Reserved167_IRQHandler:
+    ldr   r0,=Reserved167_DriverIRQHandler
     bx    r0
-    .size TRNG0_IRQHandler, . - TRNG0_IRQHandler
+    .size Reserved167_IRQHandler, . - Reserved167_IRQHandler
 
     .align 1
     .thumb_func
@@ -1824,14 +1822,14 @@ CTI0_IRQHandler:
     def_irq_handler    FLEXPWM1_SUBMODULE1_DriverIRQHandler
     def_irq_handler    FLEXPWM1_SUBMODULE2_DriverIRQHandler
     def_irq_handler    FLEXPWM1_SUBMODULE3_DriverIRQHandler
-    def_irq_handler    ENC0_COMPARE_DriverIRQHandler
-    def_irq_handler    ENC0_HOME_DriverIRQHandler
-    def_irq_handler    ENC0_WDG_SAB_DriverIRQHandler
-    def_irq_handler    ENC0_IDX_DriverIRQHandler
-    def_irq_handler    ENC1_COMPARE_DriverIRQHandler
-    def_irq_handler    ENC1_HOME_DriverIRQHandler
-    def_irq_handler    ENC1_WDG_SAB_DriverIRQHandler
-    def_irq_handler    ENC1_IDX_DriverIRQHandler
+    def_irq_handler    QDC0_COMPARE_DriverIRQHandler
+    def_irq_handler    QDC0_HOME_DriverIRQHandler
+    def_irq_handler    QDC0_WDG_SAB_DriverIRQHandler
+    def_irq_handler    QDC0_IDX_DriverIRQHandler
+    def_irq_handler    QDC1_COMPARE_DriverIRQHandler
+    def_irq_handler    QDC1_HOME_DriverIRQHandler
+    def_irq_handler    QDC1_WDG_SAB_DriverIRQHandler
+    def_irq_handler    QDC1_IDX_DriverIRQHandler
     def_irq_handler    ITRC0_DriverIRQHandler
     def_irq_handler    BSP32_DriverIRQHandler
     def_irq_handler    ELS_ERR_DriverIRQHandler
@@ -1850,8 +1848,8 @@ CTI0_IRQHandler:
     def_irq_handler    WUU_DriverIRQHandler
     def_irq_handler    PORT_EFT_DriverIRQHandler
     def_irq_handler    ETB0_DriverIRQHandler
-    def_irq_handler    SM3_DriverIRQHandler
-    def_irq_handler    TRNG0_DriverIRQHandler
+    def_irq_handler    Reserved166_DriverIRQHandler
+    def_irq_handler    Reserved167_DriverIRQHandler
     def_irq_handler    WWDT0_DriverIRQHandler
     def_irq_handler    WWDT1_DriverIRQHandler
     def_irq_handler    CMC0_DriverIRQHandler

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/arm/startup_MCXN947_cm33_core1.S

@@ -2,15 +2,13 @@
 /*  @file:    startup_MCXN947_cm33_core1.s                                   */
 /*  @purpose: CMSIS Cortex-M33 Core Device Startup File                      */
 /*            MCXN947_cm33_core1                                             */
-/*  @version: 1.0                                                            */
-/*  @date:    2022-10-1                                                      */
-/*  @build:   b230131                                                        */
+/*  @version: 2.0                                                            */
+/*  @date:    2023-2-1                                                       */
+/*  @build:   b240410                                                        */
 /* ------------------------------------------------------------------------- */
 /*                                                                           */
 /* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
-/* Copyright 2016-2023 NXP                                                   */
-/* All rights reserved.                                                      */
-/*                                                                           */
+/* Copyright 2016-2024 NXP                                                   */
 /* SPDX-License-Identifier: BSD-3-Clause                                     */
 /*****************************************************************************/
 /* Version: GCC for ARM Embedded Processors                                  */
@@ -165,14 +163,14 @@ __Vectors:
     .long   FLEXPWM1_SUBMODULE1_IRQHandler                  /* FlexPWM1 Submodule 1 capture/compare/reload interrupt*/
     .long   FLEXPWM1_SUBMODULE2_IRQHandler                  /* FlexPWM1 Submodule 2 capture/compare/reload interrupt*/
     .long   FLEXPWM1_SUBMODULE3_IRQHandler                  /* FlexPWM1 Submodule 3 capture/compare/reload interrupt*/
-    .long   ENC0_COMPARE_IRQHandler                         /* ENC0_Compare interrupt*/
-    .long   ENC0_HOME_IRQHandler                            /* ENC0_Home interrupt*/
-    .long   ENC0_WDG_SAB_IRQHandler                         /* ENC0_WDG_IRQ/SAB interrupt*/
-    .long   ENC0_IDX_IRQHandler                             /* ENC0_IDX interrupt*/
-    .long   ENC1_COMPARE_IRQHandler                         /* ENC1_Compare interrupt*/
-    .long   ENC1_HOME_IRQHandler                            /* ENC1_Home interrupt*/
-    .long   ENC1_WDG_SAB_IRQHandler                         /* ENC1_WDG_IRQ/SAB interrupt*/
-    .long   ENC1_IDX_IRQHandler                             /* ENC1_IDX interrupt*/
+    .long   QDC0_COMPARE_IRQHandler                         /* QDC0_Compare interrupt*/
+    .long   QDC0_HOME_IRQHandler                            /* QDC0_Home interrupt*/
+    .long   QDC0_WDG_SAB_IRQHandler                         /* QDC0_WDG_IRQ/SAB interrupt*/
+    .long   QDC0_IDX_IRQHandler                             /* QDC0_IDX interrupt*/
+    .long   QDC1_COMPARE_IRQHandler                         /* QDC1_Compare interrupt*/
+    .long   QDC1_HOME_IRQHandler                            /* QDC1_Home interrupt*/
+    .long   QDC1_WDG_SAB_IRQHandler                         /* QDC1_WDG_IRQ/SAB interrupt*/
+    .long   QDC1_IDX_IRQHandler                             /* QDC1_IDX interrupt*/
     .long   ITRC0_IRQHandler                                /* Intrusion and Tamper Response Controller interrupt*/
     .long   BSP32_IRQHandler                                /* CoolFlux BSP32 interrupt*/
     .long   ELS_ERR_IRQHandler                              /* ELS error interrupt*/
@@ -191,8 +189,8 @@ __Vectors:
     .long   WUU_IRQHandler                                  /* Wake Up Unit interrupt*/
     .long   PORT_EFT_IRQHandler                             /* PORT0~5 EFT interrupt*/
     .long   ETB0_IRQHandler                                 /* ETB counter expires interrupt*/
-    .long   SM3_IRQHandler                                  /* Secure Generic Interface (SGI) SAFO interrupt */
-    .long   TRNG0_IRQHandler                                /* True Random Number Generator interrupt*/
+    .long   Reserved166_IRQHandler                          /* Reserved interrupt*/
+    .long   Reserved167_IRQHandler                          /* Reserved interrupt*/
     .long   WWDT0_IRQHandler                                /* Windowed Watchdog Timer 0 interrupt*/
     .long   WWDT1_IRQHandler                                /* Windowed Watchdog Timer 1 interrupt*/
     .long   CMC0_IRQHandler                                 /* Core Mode Controller interrupt*/
@@ -1391,75 +1389,75 @@ FLEXPWM1_SUBMODULE3_IRQHandler:
 
     .align 1
     .thumb_func
-    .weak ENC0_COMPARE_IRQHandler
-    .type ENC0_COMPARE_IRQHandler, %function
-ENC0_COMPARE_IRQHandler:
-    ldr   r0,=ENC0_COMPARE_DriverIRQHandler
+    .weak QDC0_COMPARE_IRQHandler
+    .type QDC0_COMPARE_IRQHandler, %function
+QDC0_COMPARE_IRQHandler:
+    ldr   r0,=QDC0_COMPARE_DriverIRQHandler
     bx    r0
-    .size ENC0_COMPARE_IRQHandler, . - ENC0_COMPARE_IRQHandler
+    .size QDC0_COMPARE_IRQHandler, . - QDC0_COMPARE_IRQHandler
 
     .align 1
     .thumb_func
-    .weak ENC0_HOME_IRQHandler
-    .type ENC0_HOME_IRQHandler, %function
-ENC0_HOME_IRQHandler:
-    ldr   r0,=ENC0_HOME_DriverIRQHandler
+    .weak QDC0_HOME_IRQHandler
+    .type QDC0_HOME_IRQHandler, %function
+QDC0_HOME_IRQHandler:
+    ldr   r0,=QDC0_HOME_DriverIRQHandler
     bx    r0
-    .size ENC0_HOME_IRQHandler, . - ENC0_HOME_IRQHandler
+    .size QDC0_HOME_IRQHandler, . - QDC0_HOME_IRQHandler
 
     .align 1
     .thumb_func
-    .weak ENC0_WDG_SAB_IRQHandler
-    .type ENC0_WDG_SAB_IRQHandler, %function
-ENC0_WDG_SAB_IRQHandler:
-    ldr   r0,=ENC0_WDG_SAB_DriverIRQHandler
+    .weak QDC0_WDG_SAB_IRQHandler
+    .type QDC0_WDG_SAB_IRQHandler, %function
+QDC0_WDG_SAB_IRQHandler:
+    ldr   r0,=QDC0_WDG_SAB_DriverIRQHandler
     bx    r0
-    .size ENC0_WDG_SAB_IRQHandler, . - ENC0_WDG_SAB_IRQHandler
+    .size QDC0_WDG_SAB_IRQHandler, . - QDC0_WDG_SAB_IRQHandler
 
     .align 1
     .thumb_func
-    .weak ENC0_IDX_IRQHandler
-    .type ENC0_IDX_IRQHandler, %function
-ENC0_IDX_IRQHandler:
-    ldr   r0,=ENC0_IDX_DriverIRQHandler
+    .weak QDC0_IDX_IRQHandler
+    .type QDC0_IDX_IRQHandler, %function
+QDC0_IDX_IRQHandler:
+    ldr   r0,=QDC0_IDX_DriverIRQHandler
     bx    r0
-    .size ENC0_IDX_IRQHandler, . - ENC0_IDX_IRQHandler
+    .size QDC0_IDX_IRQHandler, . - QDC0_IDX_IRQHandler
 
     .align 1
     .thumb_func
-    .weak ENC1_COMPARE_IRQHandler
-    .type ENC1_COMPARE_IRQHandler, %function
-ENC1_COMPARE_IRQHandler:
-    ldr   r0,=ENC1_COMPARE_DriverIRQHandler
+    .weak QDC1_COMPARE_IRQHandler
+    .type QDC1_COMPARE_IRQHandler, %function
+QDC1_COMPARE_IRQHandler:
+    ldr   r0,=QDC1_COMPARE_DriverIRQHandler
     bx    r0
-    .size ENC1_COMPARE_IRQHandler, . - ENC1_COMPARE_IRQHandler
+    .size QDC1_COMPARE_IRQHandler, . - QDC1_COMPARE_IRQHandler
 
     .align 1
     .thumb_func
-    .weak ENC1_HOME_IRQHandler
-    .type ENC1_HOME_IRQHandler, %function
-ENC1_HOME_IRQHandler:
-    ldr   r0,=ENC1_HOME_DriverIRQHandler
+    .weak QDC1_HOME_IRQHandler
+    .type QDC1_HOME_IRQHandler, %function
+QDC1_HOME_IRQHandler:
+    ldr   r0,=QDC1_HOME_DriverIRQHandler
     bx    r0
-    .size ENC1_HOME_IRQHandler, . - ENC1_HOME_IRQHandler
+    .size QDC1_HOME_IRQHandler, . - QDC1_HOME_IRQHandler
 
     .align 1
     .thumb_func
-    .weak ENC1_WDG_SAB_IRQHandler
-    .type ENC1_WDG_SAB_IRQHandler, %function
-ENC1_WDG_SAB_IRQHandler:
-    ldr   r0,=ENC1_WDG_SAB_DriverIRQHandler
+    .weak QDC1_WDG_SAB_IRQHandler
+    .type QDC1_WDG_SAB_IRQHandler, %function
+QDC1_WDG_SAB_IRQHandler:
+    ldr   r0,=QDC1_WDG_SAB_DriverIRQHandler
     bx    r0
-    .size ENC1_WDG_SAB_IRQHandler, . - ENC1_WDG_SAB_IRQHandler
+    .size QDC1_WDG_SAB_IRQHandler, . - QDC1_WDG_SAB_IRQHandler
 
     .align 1
     .thumb_func
-    .weak ENC1_IDX_IRQHandler
-    .type ENC1_IDX_IRQHandler, %function
-ENC1_IDX_IRQHandler:
-    ldr   r0,=ENC1_IDX_DriverIRQHandler
+    .weak QDC1_IDX_IRQHandler
+    .type QDC1_IDX_IRQHandler, %function
+QDC1_IDX_IRQHandler:
+    ldr   r0,=QDC1_IDX_DriverIRQHandler
     bx    r0
-    .size ENC1_IDX_IRQHandler, . - ENC1_IDX_IRQHandler
+    .size QDC1_IDX_IRQHandler, . - QDC1_IDX_IRQHandler
 
     .align 1
     .thumb_func
@@ -1625,21 +1623,21 @@ ETB0_IRQHandler:
 
     .align 1
     .thumb_func
-    .weak SM3_IRQHandler
-    .type SM3_IRQHandler, %function
-SM3_IRQHandler:
-    ldr   r0,=SM3_DriverIRQHandler
+    .weak Reserved166_IRQHandler
+    .type Reserved166_IRQHandler, %function
+Reserved166_IRQHandler:
+    ldr   r0,=Reserved166_DriverIRQHandler
     bx    r0
-    .size SM3_IRQHandler, . - SM3_IRQHandler
+    .size Reserved166_IRQHandler, . - Reserved166_IRQHandler
 
     .align 1
     .thumb_func
-    .weak TRNG0_IRQHandler
-    .type TRNG0_IRQHandler, %function
-TRNG0_IRQHandler:
-    ldr   r0,=TRNG0_DriverIRQHandler
+    .weak Reserved167_IRQHandler
+    .type Reserved167_IRQHandler, %function
+Reserved167_IRQHandler:
+    ldr   r0,=Reserved167_DriverIRQHandler
     bx    r0
-    .size TRNG0_IRQHandler, . - TRNG0_IRQHandler
+    .size Reserved167_IRQHandler, . - Reserved167_IRQHandler
 
     .align 1
     .thumb_func
@@ -1816,14 +1814,14 @@ CTI0_IRQHandler:
     def_irq_handler    FLEXPWM1_SUBMODULE1_DriverIRQHandler
     def_irq_handler    FLEXPWM1_SUBMODULE2_DriverIRQHandler
     def_irq_handler    FLEXPWM1_SUBMODULE3_DriverIRQHandler
-    def_irq_handler    ENC0_COMPARE_DriverIRQHandler
-    def_irq_handler    ENC0_HOME_DriverIRQHandler
-    def_irq_handler    ENC0_WDG_SAB_DriverIRQHandler
-    def_irq_handler    ENC0_IDX_DriverIRQHandler
-    def_irq_handler    ENC1_COMPARE_DriverIRQHandler
-    def_irq_handler    ENC1_HOME_DriverIRQHandler
-    def_irq_handler    ENC1_WDG_SAB_DriverIRQHandler
-    def_irq_handler    ENC1_IDX_DriverIRQHandler
+    def_irq_handler    QDC0_COMPARE_DriverIRQHandler
+    def_irq_handler    QDC0_HOME_DriverIRQHandler
+    def_irq_handler    QDC0_WDG_SAB_DriverIRQHandler
+    def_irq_handler    QDC0_IDX_DriverIRQHandler
+    def_irq_handler    QDC1_COMPARE_DriverIRQHandler
+    def_irq_handler    QDC1_HOME_DriverIRQHandler
+    def_irq_handler    QDC1_WDG_SAB_DriverIRQHandler
+    def_irq_handler    QDC1_IDX_DriverIRQHandler
     def_irq_handler    ITRC0_DriverIRQHandler
     def_irq_handler    BSP32_DriverIRQHandler
     def_irq_handler    ELS_ERR_DriverIRQHandler
@@ -1842,8 +1840,8 @@ CTI0_IRQHandler:
     def_irq_handler    WUU_DriverIRQHandler
     def_irq_handler    PORT_EFT_DriverIRQHandler
     def_irq_handler    ETB0_DriverIRQHandler
-    def_irq_handler    SM3_DriverIRQHandler
-    def_irq_handler    TRNG0_DriverIRQHandler
+    def_irq_handler    Reserved166_DriverIRQHandler
+    def_irq_handler    Reserved167_DriverIRQHandler
     def_irq_handler    WWDT0_DriverIRQHandler
     def_irq_handler    WWDT1_DriverIRQHandler
     def_irq_handler    CMC0_DriverIRQHandler

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2021, 2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -205,7 +205,7 @@ void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base)
  * brief Invalidates cache by range.
  *
  * param address The physical address of cache.
- * param size_byte size of the memory to be invalidated.
+ * param size_byte size of the memory to be invalidated, should be larger than 0.
  * note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE".
  * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
  * startAddr is not aligned. For the size_byte, application should make sure the
@@ -213,36 +213,39 @@ void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base)
  */
 void CACHE64_InvalidateCacheByRange(uint32_t address, uint32_t size_byte)
 {
-    uint32_t endAddr = address + size_byte - 0x01U;
-    uint32_t pccReg  = 0;
-    /* Align address to cache line size. */
-    uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
-    uint32_t instance  = CACHE64_GetInstanceByAddr(address);
-    uint32_t endLim;
-    CACHE64_CTRL_Type *base;
-
-    if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
+    if (size_byte > 0UL)
     {
-        return;
-    }
-    base    = s_cache64ctrlBases[instance];
-    endLim  = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
-    endAddr = endAddr > endLim ? endLim : endAddr;
-
-    /* Set the invalidate by line command and use the physical address. */
-    pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CLCR_LADSEL_MASK;
-    base->CLCR = pccReg;
+        uint32_t endAddr = address + size_byte - 0x01U;
+        uint32_t pccReg  = 0;
+        /* Align address to cache line size. */
+        uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
+        uint32_t instance  = CACHE64_GetInstanceByAddr(address);
+        uint32_t endLim;
+        CACHE64_CTRL_Type *base;
+
+        if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
+        {
+            return;
+        }
+        base    = s_cache64ctrlBases[instance];
+        endLim  = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
+        endAddr = endAddr > endLim ? endLim : endAddr;
 
-    while (startAddr < endAddr)
-    {
-        /* Set the address and initiate the command. */
-        base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
+        /* Set the invalidate by line command and use the physical address. */
+        pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(1) | CACHE64_CTRL_CLCR_LADSEL_MASK;
+        base->CLCR = pccReg;
 
-        /* Wait until the cache command completes. */
-        while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
+        while (startAddr < endAddr)
         {
+            /* Set the address and initiate the command. */
+            base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
+
+            /* Wait until the cache command completes. */
+            while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
+            {
+            }
+            startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
         }
-        startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
     }
 }
 
@@ -268,7 +271,7 @@ void CACHE64_CleanCache(CACHE64_CTRL_Type *base)
  * brief Cleans cache by range.
  *
  * param address The physical address of cache.
- * param size_byte size of the memory to be cleaned.
+ * param size_byte size of the memory to be cleaned, should be larger than 0.
  * note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
  * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
  * startAddr is not aligned. For the size_byte, application should make sure the
@@ -276,36 +279,39 @@ void CACHE64_CleanCache(CACHE64_CTRL_Type *base)
  */
 void CACHE64_CleanCacheByRange(uint32_t address, uint32_t size_byte)
 {
-    uint32_t endAddr = address + size_byte - 0x01U;
-    uint32_t pccReg  = 0;
-    /* Align address to cache line size. */
-    uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
-    uint32_t instance  = CACHE64_GetInstanceByAddr(address);
-    uint32_t endLim;
-    CACHE64_CTRL_Type *base;
-
-    if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
+    if (size_byte > 0UL)
     {
-        return;
-    }
-    base    = s_cache64ctrlBases[instance];
-    endLim  = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
-    endAddr = endAddr > endLim ? endLim : endAddr;
-
-    /* Set the push by line command. */
-    pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CLCR_LADSEL_MASK;
-    base->CLCR = pccReg;
+        uint32_t endAddr = address + size_byte - 0x01U;
+        uint32_t pccReg  = 0;
+        /* Align address to cache line size. */
+        uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
+        uint32_t instance  = CACHE64_GetInstanceByAddr(address);
+        uint32_t endLim;
+        CACHE64_CTRL_Type *base;
+
+        if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
+        {
+            return;
+        }
+        base    = s_cache64ctrlBases[instance];
+        endLim  = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
+        endAddr = endAddr > endLim ? endLim : endAddr;
 
-    while (startAddr < endAddr)
-    {
-        /* Set the address and initiate the command. */
-        base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
+        /* Set the push by line command. */
+        pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(2) | CACHE64_CTRL_CLCR_LADSEL_MASK;
+        base->CLCR = pccReg;
 
-        /* Wait until the cache command completes. */
-        while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
+        while (startAddr < endAddr)
         {
+            /* Set the address and initiate the command. */
+            base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
+
+            /* Wait until the cache command completes. */
+            while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
+            {
+            }
+            startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
         }
-        startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
     }
 }
 
@@ -333,7 +339,7 @@ void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base)
  * brief Cleans and invalidate cache by range.
  *
  * param address The physical address of cache.
- * param size_byte size of the memory to be Cleaned and Invalidated.
+ * param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0.
  * note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
  * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
  * startAddr is not aligned. For the size_byte, application should make sure the
@@ -341,36 +347,39 @@ void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base)
  */
 void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte)
 {
-    uint32_t endAddr = address + size_byte - 0x01U;
-    uint32_t pccReg  = 0;
-    /* Align address to cache line size. */
-    uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
-    uint32_t instance  = CACHE64_GetInstanceByAddr(address);
-    uint32_t endLim;
-    CACHE64_CTRL_Type *base;
-
-    if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
+    if (size_byte > 0UL)
     {
-        return;
-    }
-    base    = s_cache64ctrlBases[instance];
-    endLim  = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
-    endAddr = endAddr > endLim ? endLim : endAddr;
-
-    /* Set the push by line command. */
-    pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CLCR_LADSEL_MASK;
-    base->CLCR = pccReg;
+        uint32_t endAddr = address + size_byte - 0x01U;
+        uint32_t pccReg  = 0;
+        /* Align address to cache line size. */
+        uint32_t startAddr = address & ~((uint32_t)CACHE64_LINESIZE_BYTE - 1U);
+        uint32_t instance  = CACHE64_GetInstanceByAddr(address);
+        uint32_t endLim;
+        CACHE64_CTRL_Type *base;
+
+        if (instance >= ARRAY_SIZE(s_cache64ctrlBases))
+        {
+            return;
+        }
+        base    = s_cache64ctrlBases[instance];
+        endLim  = s_cache64PhymemBases[instance] + s_cache64PhymemSizes[instance] - 0x01U;
+        endAddr = endAddr > endLim ? endLim : endAddr;
 
-    while (startAddr < endAddr)
-    {
-        /* Set the address and initiate the command. */
-        base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
+        /* Set the push by line command. */
+        pccReg = (base->CLCR & ~CACHE64_CTRL_CLCR_LCMD_MASK) | CACHE64_CTRL_CLCR_LCMD(3) | CACHE64_CTRL_CLCR_LADSEL_MASK;
+        base->CLCR = pccReg;
 
-        /* Wait until the cache command completes. */
-        while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
+        while (startAddr < endAddr)
         {
+            /* Set the address and initiate the command. */
+            base->CSAR = (startAddr & CACHE64_CTRL_CSAR_PHYADDR_MASK) | CACHE64_CTRL_CSAR_LGO_MASK;
+
+            /* Wait until the cache command completes. */
+            while ((base->CSAR & CACHE64_CTRL_CSAR_LGO_MASK) != 0x00U)
+            {
+            }
+            startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
         }
-        startAddr += (uint32_t)CACHE64_LINESIZE_BYTE;
     }
 }
 

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache.h

@@ -1,12 +1,12 @@
 /*
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2021, 2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_CACHE_H_
-#define _FSL_CACHE_H_
+#ifndef FSL_CACHE_H_
+#define FSL_CACHE_H_
 
 #include "fsl_common.h"
 
@@ -20,10 +20,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief cache driver version. */
-#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 6))
-/*@}*/
+#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 7))
+/*! @} */
 
 /*! @brief cache line size. */
 #define CACHE64_LINESIZE_BYTE (FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE)
@@ -138,7 +138,7 @@ void CACHE64_InvalidateCache(CACHE64_CTRL_Type *base);
  * @brief Invalidates cache by range.
  *
  * @param address The physical address of cache.
- * @param size_byte size of the memory to be invalidated.
+ * @param size_byte size of the memory to be invalidated, should be larger than 0.
  * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
  * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
  * startAddr is not aligned. For the size_byte, application should make sure the
@@ -158,7 +158,7 @@ void CACHE64_CleanCache(CACHE64_CTRL_Type *base);
  * @brief Cleans cache by range.
  *
  * @param address The physical address of cache.
- * @param size_byte size of the memory to be cleaned.
+ * @param size_byte size of the memory to be cleaned, should be larger than 0.
  * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
  * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
  * startAddr is not aligned. For the size_byte, application should make sure the
@@ -178,7 +178,7 @@ void CACHE64_CleanInvalidateCache(CACHE64_CTRL_Type *base);
  * @brief Cleans and invalidate cache by range.
  *
  * @param address The physical address of cache.
- * @param size_byte size of the memory to be Cleaned and Invalidated.
+ * @param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0.
  * @note Address and size should be aligned to "CACHE64_LINESIZE_BYTE".
  * The startAddr here will be forced to align to CACHE64_LINESIZE_BYTE if
  * startAddr is not aligned. For the size_byte, application should make sure the
@@ -198,7 +198,7 @@ void CACHE64_CleanInvalidateCacheByRange(uint32_t address, uint32_t size_byte);
 void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable);
 #endif
 
-/*@}*/
+/*! @} */
 
 /*!
  * @name Unified Cache Control for all caches
@@ -209,7 +209,7 @@ void CACHE64_EnableWriteBuffer(CACHE64_CTRL_Type *base, bool enable);
  * @brief Invalidates instruction cache by range.
  *
  * @param address The physical address.
- * @param size_byte size of the memory to be invalidated.
+ * @param size_byte size of the memory to be invalidated, should be larger than 0.
  * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
  * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
  * size if startAddr is not aligned. For the size_byte, application should make sure the
@@ -224,7 +224,7 @@ static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte
  * @brief Invalidates data cache by range.
  *
  * @param address The physical address.
- * @param size_byte size of the memory to be invalidated.
+ * @param size_byte size of the memory to be invalidated, should be larger than 0.
  * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
  * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
  * size if startAddr is not aligned. For the size_byte, application should make sure the
@@ -239,7 +239,7 @@ static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte
  * @brief Clean data cache by range.
  *
  * @param address The physical address.
- * @param size_byte size of the memory to be cleaned.
+ * @param size_byte size of the memory to be cleaned, should be larger than 0.
  * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
  * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
  * size if startAddr is not aligned. For the size_byte, application should make sure the
@@ -254,7 +254,7 @@ static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
  * @brief Cleans and Invalidates data cache by range.
  *
  * @param address The physical address.
- * @param size_byte size of the memory to be Cleaned and Invalidated.
+ * @param size_byte size of the memory to be Cleaned and Invalidated, should be larger than 0.
  * @note Address and size should be aligned to CACHE64_LINESIZE_BYTE due to the cache operation unit
  * FSL_FEATURE_CACHE64_CTRL_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
  * size if startAddr is not aligned. For the size_byte, application should make sure the
@@ -265,7 +265,7 @@ static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size
     CACHE64_CleanInvalidateCacheByRange(address, size_byte);
 }
 
-/*@}*/
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -273,4 +273,4 @@ static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size
 
 /*! @}*/
 
-#endif /* _FSL_CACHE_H_*/
+#endif /* FSL_CACHE_H_*/

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cache_lpcac.h

@@ -1,11 +1,11 @@
 /*
- * Copyright 2021-2022 NXP
+ * Copyright 2021-2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_CACHE_LPCAC_H_
-#define _FSL_CACHE_LPCAC_H_
+#ifndef FSL_CACHE_LPCAC_H_
+#define FSL_CACHE_LPCAC_H_
 
 #include "fsl_common.h"
 
@@ -21,7 +21,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief cache driver version */
-#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+#define FSL_CACHE_LPCAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
 /*@}*/
 /*******************************************************************************
  * API
@@ -60,7 +60,7 @@ static inline void L1CACHE_DisableCodeCache(void)
  */
 static inline void L1CACHE_InvalidateCodeCache(void)
 {
-    SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK;
+    SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK;
 }
 
 /*!
@@ -181,4 +181,4 @@ static inline void L1CACHE_DisableXOMControl(void)
 
 /*! @}*/
 
-#endif /* _FSL_CACHE_LPCAC_H_*/
+#endif /* FSL_CACHE_LPCAC_H_*/

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.c

@@ -24,6 +24,14 @@
 static const IRQn_Type s_CdogIrqs[] = CDOG_IRQS;
 #endif /* CDOG_IRQS */
 
+#ifdef CDOG_CLOCKS
+static const clock_ip_name_t s_CdogClocks[] = CDOG_CLOCKS;
+#endif /* CDOG_CLOCKS */
+
+#ifdef CDOG_BASE_PTRS
+static const CDOG_Type* s_cdogBases[] = CDOG_BASE_PTRS;
+#endif /* CDOG_BASE_PTRS */
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -31,50 +39,24 @@ static const IRQn_Type s_CdogIrqs[] = CDOG_IRQS;
 /*******************************************************************************
  * Code
  ******************************************************************************/
-#if defined(CDOG)
-/*!
- * Weak implementation of CDOG IRQ, should be re-defined by user when using CDOG IRQ
- */
-__WEAK void CDOG_DriverIRQHandler(void)
-{
-    /*    NVIC_DisableIRQ(CDOG_IRQn);
-     *    CDOG_Stop(CDOG, s_start);
-     *    CDOG->FLAGS = 0x0U;
-     *    CDOG_Start(CDOG, 0xFFFFFFU, s_start);
-     *    NVIC_EnableIRQ(CDOG_IRQn);
-     */
-}
-#endif
 
-#if defined(CDOG0)
-/*!
- * Weak implementation of CDOG0 IRQ, should be re-defined by user when using CDOG IRQ
- */
-__WEAK void CDOG0_DriverIRQHandler(void)
+static uint32_t CDOG_GetInstance(CDOG_Type *base)
 {
-    /*    NVIC_DisableIRQ(CDOG0_IRQn);
-     *    CDOG_Stop(CDOG0, s_start);
-     *    CDOG0->FLAGS = 0x0U;
-     *    CDOG_Start(CDOG0, 0xFFFFFFU, s_start);
-     *    NVIC_EnableIRQ(CDOG0_IRQn);
-     */
-}
-#endif
-
-#if defined(CDOG1)
-/*!
- * Weak implementation of CDOG1 IRQ, should be re-defined by user when using CDOG IRQ
- */
-__WEAK void CDOG1_DriverIRQHandler(void)
-{
-    /*    NVIC_DisableIRQ(CDOG1_IRQn);
-     *    CDOG_Stop(CDOG1, s_start);
-     *    CDOG1->FLAGS = 0x0U;
-     *    CDOG_Start(CDOG1, 0xFFFFFFU, s_start);
-     *    NVIC_EnableIRQ(CDOG1_IRQn);
-     */
-}
-#endif
+    uint32_t instance;
+ 
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_cdogBases); instance++)
+    {
+        if (s_cdogBases[instance] == base)
+        {
+            break;
+        }
+    }
+ 
+    assert(instance < ARRAY_SIZE(s_cdogBases));
+ 
+    return instance;
+} 
 
 /*!
  * brief Sets the default configuration of CDOG
@@ -256,7 +238,13 @@ void CDOG_Sub256(CDOG_Type *base)
  */
 void CDOG_Check(CDOG_Type *base, uint32_t check)
 {
+#if defined(FLS_FEATURE_CDOG_USE_RESTART)
     base->RESTART = check;
+#else
+    base->STOP = check;
+    base->RELOAD = base->RELOAD;
+    base->START= check;
+#endif
 }
 
 /*!
@@ -295,7 +283,7 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
     /* Ungate clock to CDOG engine and reset it */
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 #ifdef CDOG_CLOCKS
-    CLOCK_EnableClock(kCLOCK_Cdog);
+    CLOCK_EnableClock(s_CdogClocks[CDOG_GetInstance(base)]);
 #endif /* CDOG_CLOCKS */
 #endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
@@ -322,6 +310,25 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
     }
     else
     {
+/* load default values for CDOG->CONTROL before flags clear */
+#if defined(FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF) && (FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF > 0)
+        cdog_config_t default_conf;
+
+        /* Initialize CDOG */
+        CDOG_GetDefaultConfig(&default_conf);
+
+        /* Write default value to CDOG->CONTROL*/
+        base->CONTROL = 
+            CDOG_CONTROL_TIMEOUT_CTRL(default_conf.timeout) |       /* Action if the timeout event is triggered  */
+            CDOG_CONTROL_MISCOMPARE_CTRL(default_conf.miscompare) | /* Action if the miscompare error event is triggered  */
+            CDOG_CONTROL_SEQUENCE_CTRL(default_conf.sequence) |     /* Action if the sequence error event is triggered  */
+            CDOG_CONTROL_STATE_CTRL(default_conf.state) |           /* Action if the state error event is triggered  */
+            CDOG_CONTROL_ADDRESS_CTRL(default_conf.address) |       /* Action if the address error event is triggered */
+            CDOG_CONTROL_IRQ_PAUSE(default_conf.irq_pause) |        /* Pause running during interrupts setup */
+            CDOG_CONTROL_DEBUG_HALT_CTRL(default_conf.debug_halt) | /* Halt CDOG timer during debug */
+            CDOG_CONTROL_LOCK_CTRL(default_conf.lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */
+#endif /* FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF */
+
         base->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) |
                       CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) |
                       CDOG_FLAGS_POR_FLAG(0U);
@@ -338,11 +345,8 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
         CDOG_CONTROL_LOCK_CTRL(conf->lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */
 
 #if defined(CDOG_IRQS)
-    /* Enable peripheral IRQs, if defined in array */
-    for (uint32_t i = 0; i < ARRAY_SIZE(s_CdogIrqs); i++)
-    {
-        NVIC_EnableIRQ(s_CdogIrqs[i]);
-    }
+    /* Enable peripheral IRQ */
+    NVIC_EnableIRQ(s_CdogIrqs[CDOG_GetInstance(base)]);
 #endif /* CDOG_IRQS */
 
     return kStatus_Success;
@@ -358,11 +362,8 @@ status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
 void CDOG_Deinit(CDOG_Type *base)
 {
 #if defined(CDOG_IRQS)
-    /* Enable peripheral IRQs, if defined in array */
-    for (uint32_t i = 0; i < ARRAY_SIZE(s_CdogIrqs); i++)
-    {
-        NVIC_DisableIRQ(s_CdogIrqs[i]);
-    }
+    /* Disable peripheral IRQ */
+    NVIC_DisableIRQ(s_CdogIrqs[CDOG_GetInstance(base)]);
 #endif /* CDOG_IRQS */
 
 #if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET)
@@ -371,7 +372,7 @@ void CDOG_Deinit(CDOG_Type *base)
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 #ifdef CDOG_CLOCKS
-    CLOCK_DisableClock(kCLOCK_Cdog);
+    CLOCK_DisableClock(s_CdogClocks[CDOG_GetInstance(base)]);
 #endif /* CDOG_CLOCKS */
 #endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cdog.h

@@ -4,8 +4,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_CDOG_H_
-#define _FSL_CDOG_H_
+#ifndef FSL_CDOG_H_
+#define FSL_CDOG_H_
 
 #include "fsl_common.h"
 
@@ -21,10 +21,13 @@
  *******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
-/*! @brief Defines CDOG driver version 2.1.2.
+/*! @{ */
+/*! @brief Defines CDOG driver version 2.1.3.
  *
  * Change log:
+ * - Version 2.1.3
+ *   - Re-design multiple instance IRQs and Clocks
+ *   - Add fix for RESTART command errata
  * - Version 2.1.2
  *   - Support multiple IRQs
  *   - Fix default CONTROL values
@@ -39,8 +42,8 @@
  * - Version 2.0.0
  *   - initial version
  */
-#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
-/*@}*/
+#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
+/*! @} */
 
 typedef struct
 {
@@ -139,17 +142,6 @@ typedef uint32_t secure_counter_t;
 /*******************************************************************************
  * API
  *******************************************************************************/
-#if defined(CDOG)
-extern void CDOG_DriverIRQHandler(void);
-#endif
-
-#if defined(CDOG0)
-extern void CDOG0_DriverIRQHandler(void);
-#endif
-
-#if defined(CDOG1)
-extern void CDOG1_DriverIRQHandler(void);
-#endif
 
 #if defined(__cplusplus)
 extern "C" {
@@ -334,4 +326,4 @@ uint32_t CDOG_ReadPersistent(CDOG_Type *base);
 
 /*! @}*/ /* end of group cdog */
 
-#endif /* _FSL_CDOG_H_ */
+#endif /* FSL_CDOG_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_clock.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022, NXP
+ * Copyright 2022-2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -207,6 +207,13 @@ status_t CLOCK_SetupExtClocking(uint32_t iFreq)
         return (status_t)kStatus_SCG_Busy;
     }
 
+    /* If sosc is used by PLL and PLL is used by system, return error. */
+    if ((((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->APLLCSR & SCG_APLLCSR_APLLSEL_MASK) != 0U)) ||
+        (((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK) != 0U)))
+    {
+        return (status_t)kStatus_SCG_Busy;
+    }
+
     /* If configure register is locked, return error. */
     if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U)
     {
@@ -238,6 +245,83 @@ status_t CLOCK_SetupExtClocking(uint32_t iFreq)
     return kStatus_Success;
 }
 
+/**
+ * @brief   Initialize the external reference clock to given frequency.
+ * @param   iFreq   : Desired frequency (must be equal to exact rate in Hz)
+ * @return  returns success or fail status.
+ */
+status_t CLOCK_SetupExtRefClocking(uint32_t iFreq)
+{
+    uint8_t range = 0U;
+
+    if ((iFreq >= 16000000U) && (iFreq < 20000000U))
+    {
+        range = 0U;
+    }
+    else if ((iFreq >= 20000000U) && (iFreq < 30000000U))
+    {
+        range = 1U;
+    }
+    else if ((iFreq >= 30000000U) && (iFreq < 50000000U))
+    {
+        range = 2U;
+    }
+    else if ((iFreq >= 50000000U) && (iFreq < 66000000U))
+    {
+        range = 3U;
+    }
+    else
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If clock is used by system, return error. */
+    if ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCSEL_MASK) != 0U)
+    {
+        return (status_t)kStatus_SCG_Busy;
+    }
+
+    /* If sosc is used by PLL and PLL is used by system, return error. */
+    if ((((SCG0->APLLCTRL & SCG_APLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->APLLCSR & SCG_APLLCSR_APLLSEL_MASK) != 0U)) ||
+        (((SCG0->SPLLCTRL & SCG_SPLLCTRL_SOURCE_MASK) == 0u) && ((SCG0->SPLLCSR & SCG_SPLLCSR_SPLLSEL_MASK) != 0U)))
+    {
+        return (status_t)kStatus_SCG_Busy;
+    }
+
+    /* If configure register is locked, return error. */
+    if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U)
+    {
+        return kStatus_ReadOnly;
+    }
+
+    /* De-initializes the SCG SOSC */
+    SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
+
+    /* Enable LDO */
+    SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
+
+    /* Select SOSC source (external reference clock)*/
+    SCG0->SOSCCFG &= ~SCG_SOSCCFG_EREFS_MASK;
+
+    /*Configure SOSC range */
+    SCG0->SOSCCFG |= SCG_SOSCCFG_RANGE(range);
+
+    /* Unlock SOSCCSR */
+    SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK;
+
+    /* Enable SOSC clock monitor and Enable SOSC */
+    SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK);
+
+    /* Wait for SOSC clock to be valid. */
+    while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U)
+    {
+    }
+
+    s_Ext_Clk_Freq = iFreq;
+
+    return kStatus_Success;
+}
+
 /**
  * @brief   Initialize the OSC 32K.
  * @param   id   : OSC 32 kHz output clock to specified modules
@@ -250,8 +334,8 @@ status_t CLOCK_SetupOsc32KClocking(uint32_t id)
 
     VBAT0->OSCCTLA =
         (VBAT0->OSCCTLA & ~(VBAT_OSCCTLA_MODE_EN_MASK | VBAT_OSCCTLA_CAP_SEL_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK)) |
-        VBAT_OSCCTLA_MODE_EN(0x2) | VBAT_OSCCTLA_OSC_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK;
-    VBAT0->OSCCTLB = VBAT_OSCCTLB_INVERSE(0xDFF7E);
+        VBAT_OSCCTLA_MODE_EN(0x0) | VBAT_OSCCTLA_CAP_SEL_EN_MASK | VBAT_OSCCTLA_OSC_EN_MASK;
+    VBAT0->OSCCTLB = VBAT_OSCCTLB_INVERSE(0xFFF7E);
     /* Wait for STATUSA[OSC_RDY] to set. */
     while ((VBAT0->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0U)
     {
@@ -309,11 +393,11 @@ status_t CLOCK_FROHFTrimConfig(firc_trim_config_t config)
 
     if (kSCG_FircTrimNonUpdate == config.trimMode)
     {
-        //SCG0->FIRCSTAT = SCG_FIRCSTAT_TRIMFINE(config.trimFine);
+        SCG0->FIRCSTAT = SCG_FIRCSTAT_TRIMFINE(config.trimFine);
     }
 
     /* Set trim mode. */
-  //  SCG0->FIRCCSR = (uint32_t)config.trimMode;
+    SCG0->FIRCCSR = (uint32_t)config.trimMode;
 
     if ((SCG0->FIRCCSR & SCG_FIRCCSR_FIRCERR_MASK) == SCG_FIRCCSR_FIRCERR_MASK)
     {
@@ -444,6 +528,89 @@ void CLOCK_SetPll1MonitorMode(scg_pll1_monitor_mode_t mode)
     SCG0->SPLLCSR = reg;
 }
 
+/*!
+ * @brief	Set the additional number of wait-states added to account for the ratio of system clock period to flash access
+ * time during full speed power mode.
+ * @param	system_freq_hz	: Input frequency
+ * @param	mode	        : Active run mode (voltage level).
+ * @return	success or fail status
+ */
+status_t CLOCK_SetFLASHAccessCyclesForFreq(uint32_t system_freq_hz, run_mode_t mode)
+{
+    uint32_t num_wait_states_added = 3UL; /* Default 3 additional wait states */
+    switch ((uint32_t)mode)
+    {
+        case (uint32_t)kMD_Mode:
+        {
+            if (system_freq_hz > 50000000U)
+            {
+                return kStatus_Fail;
+            }
+            if (system_freq_hz > 24000000U)
+            {
+                num_wait_states_added = 1U;
+            }
+            else
+            {
+                num_wait_states_added = 0U;
+            }
+            break;
+        }
+        case (uint32_t)kSD_Mode:
+        {
+            if (system_freq_hz > 100000000U)
+            {
+                return kStatus_Fail;
+            }
+            if (system_freq_hz > 64000000U)
+            {
+                num_wait_states_added = 2U;
+            }
+            else if (system_freq_hz > 36000000U)
+            {
+                num_wait_states_added = 1U;
+            }
+            else
+            {
+                num_wait_states_added = 0U;
+            }
+            break;
+        }
+        case (uint32_t)kOD_Mode:
+        {
+            if (system_freq_hz > 150000000U)
+            {
+                return kStatus_Fail;
+            }
+            if (system_freq_hz > 100000000U)
+            {
+                num_wait_states_added = 3U;
+            }
+            else if (system_freq_hz > 64000000U)
+            {
+                num_wait_states_added = 2U;
+            }
+            else if (system_freq_hz > 36000000U)
+            {
+                num_wait_states_added = 1U;
+            }
+            else
+            {
+                num_wait_states_added = 0U;
+            }
+            break;
+        }
+        default:
+            num_wait_states_added = 0U;
+            break;
+    }
+
+    /* additional wait-states are added */
+    FMU0->FCTRL = (FMU0->FCTRL & 0xFFFFFFF0UL) | (num_wait_states_added & 0xFUL);
+
+    return kStatus_Success;
+}
+
 /*!
  * @brief Config 32k Crystal Oscillator.
  *
@@ -677,11 +844,14 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName)
 
     switch (clockName)
     {
+        case kCLOCK_MainClk:
+            freq = CLOCK_GetMainClkFreq();
+            break;
         case kCLOCK_CoreSysClk:
             freq = CLOCK_GetCoreSysClkFreq();
             break;
         case kCLOCK_BusClk:
-            freq = CLOCK_GetCoreSysClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
+            freq = CLOCK_GetCoreSysClkFreq();
             break;
         case kCLOCK_SystickClk0:
             freq = CLOCK_GetSystickClkFreq(0U);
@@ -735,10 +905,10 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName)
             freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToMain);
             break;
         case kCLOCK_Pll0Out:
-            freq = CLOCK_GetPll1OutFreq();
+            freq = CLOCK_GetPll0OutFreq();
             break;
         case kCLOCK_Pll1Out:
-            freq = CLOCK_GetPll0OutFreq();
+            freq = CLOCK_GetPll1OutFreq();
             break;
         case kCLOCK_UsbPllOut:
             // freq = CLOCK_GetPll0OutFreq();
@@ -1568,6 +1738,9 @@ uint32_t CLOCK_GetWdtClkFreq(uint32_t id)
             case 2U:
                 freq = CLOCK_GetClk1MFreq();
                 break;
+            case 3U:
+                freq = CLOCK_GetClk1MFreq();
+                break;
             default:
                 freq = 0U;
                 break;
@@ -2037,7 +2210,7 @@ pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup)
     /* Unlock SPLLLOCK_CNFG register */
     SCG0->TRIM_LOCK = 0x5a5a0001;
 
-    /* Configure lock time of APLL stable, value = 500μs/x+300, where x is the period of clk_ref (clk_in/N). */
+    /* Configure lock time of APLL stable, value = 500μs/x+300, where x is the period of clk_ref (clk_in/N). */
     inRate = CLOCK_GetPLL1InClockRate();
     prediv = findPll1PreDiv();
     /* Adjust input clock */
@@ -2160,10 +2333,10 @@ static uint32_t CLOCK_GetOsc32KFreq(uint32_t id)
 }
 
 /* Get MAIN Clk */
-/*! brief  Return Frequency of Core System
- *  return Frequency of Core System
+/*! @brief  Return Frequency of main
+ *  @return Frequency of the main
  */
-uint32_t CLOCK_GetCoreSysClkFreq(void)
+uint32_t CLOCK_GetMainClkFreq(void)
 {
     uint32_t freq = 0U;
 
@@ -2198,6 +2371,19 @@ uint32_t CLOCK_GetCoreSysClkFreq(void)
     return freq;
 }
 
+/* Get cpu Clk */
+/*! brief  Return Frequency of Core System
+ *  return Frequency of Core System
+ */
+uint32_t CLOCK_GetCoreSysClkFreq(void)
+{
+    uint32_t freq = 0U;
+
+    freq = CLOCK_GetMainClkFreq() / ((SYSCON->AHBCLKDIV & 0xffU) + 1U);
+
+    return freq;
+}
+
 /* Get Systick Clk */
 /*! brief  Return Frequency of SystickClock
  *  return Frequency of Systick Clock
@@ -2209,7 +2395,7 @@ static uint32_t CLOCK_GetSystickClkFreq(uint32_t id)
     switch ((id == 0U) ? SYSCON->SYSTICKCLKSEL0 : SYSCON->SYSTICKCLKSEL1)
     {
         case 0U:
-            freq = CLOCK_GetCoreSysClkFreq() / (((SYSCON->SYSTICKCLKDIV[id]) & 0xffU) + 1U);
+            freq = CLOCK_GetMainClkFreq() / (((SYSCON->SYSTICKCLKDIV[id]) & 0xffU) + 1U);
             break;
         case 1U:
             freq = CLOCK_GetClk1MFreq();
@@ -2236,7 +2422,7 @@ static uint32_t CLOCK_GetClockOutClkFreq(void)
     switch (SYSCON->CLKOUTSEL)
     {
         case 0U:
-            freq = CLOCK_GetCoreSysClkFreq();
+            freq = CLOCK_GetMainClkFreq();
             break;
         case 1U:
             freq = CLOCK_GetPll0OutFreq();
@@ -2276,12 +2462,12 @@ static uint32_t CLOCK_GetLposcFreq(void)
 
     switch ((RTC0->CTRL & RTC_CTRL_CLK_SEL_MASK) >> RTC_CTRL_CLK_SEL_SHIFT)
     {
+        case 0U:
+            freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVbat);
+            break;
         case 1U:
             freq = CLOCK_GetOsc32KFreq((uint32_t)kCLOCK_Osc32kToVbat);
             break;
-        case 2U:
-            freq = CLOCK_GetClk16KFreq((uint32_t)kCLOCK_Clk16KToVbat);
-            break;
         default:
             freq = 0U;
             break;
@@ -2928,3 +3114,23 @@ bool CLOCK_EnableUsbhsClock(void)
     }
     return true;
 }
+
+/**
+ * @brief   FIRC Auto Trim With SOF.
+ * @return  returns success or fail status.
+ */
+status_t CLOCK_FIRCAutoTrimWithSOF(void)
+{
+    /* System OSC Clock Monitor is disabled */
+    CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable);
+
+    firc_trim_config_t fircAutoTrimConfig = {
+        .trimMode = kSCG_FircTrimUpdate,  /* FIRC trim is enabled and trim value update is enabled */
+        .trimSrc  = kSCG_FircTrimSrcUsb0, /* Trim source is USB0 start of frame (1kHz) */
+        .trimDiv  = 1U,                   /* Divided value */
+        .trimCoar = 0U,                   /* Trim value, see Reference Manual for more information */
+        .trimFine = 0U,                   /* Trim value, see Reference Manual for more information */
+    };
+
+    return CLOCK_FROHFTrimConfig(fircAutoTrimConfig);
+}

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 NXP
+ * Copyright 2022-2024 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -107,6 +107,7 @@ void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config)
     base->RPC = reg;
 }
 
+#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG)
 /*!
  * brief Power off the selected system SRAM always.
  *
@@ -119,10 +120,11 @@ void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config)
  */
 void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask)
 {
-    uint32_t reg = base->SRAMDIS[0];
+    uint32_t reg       = base->SRAMDIS[0];
+    uint32_t maskToSet = mask & ((uint32_t)kCMC_AllSramArrays);
 
-    reg &= ~CMC_SRAMDIS_DIS_MASK;
-    reg |= CMC_SRAMDIS_DIS(mask);
+    reg &= ~((uint32_t)kCMC_AllSramArrays);
+    reg |= CMC_SRAMDIS_DIS(maskToSet);
     base->SRAMDIS[0] = reg;
 }
 
@@ -137,13 +139,36 @@ void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask)
  */
 void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)
 {
-    uint32_t reg = base->SRAMRET[0];
+    uint32_t reg       = base->SRAMRET[0];
+    uint32_t maskToSet = mask & ((uint32_t)kCMC_AllSramArrays);
 
-    reg &= ~CMC_SRAMRET_RET_MASK;
-    reg |= CMC_SRAMRET_RET(mask);
+    reg &= ~((uint32_t)kCMC_AllSramArrays);
+    reg |= CMC_SRAMRET_RET(maskToSet);
     base->SRAMRET[0] = reg;
 }
+#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
 
+#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE)
+/*!
+ * brief Configs the low power mode of the on-chip flash memory.
+ *
+ * This function configs the low power mode of the on-chip flash memory.
+ *
+ * param base CMC peripheral base address.
+ * param doze true: Flash is disabled while core is sleeping
+ *             false: No effect.
+ * param disable true: Flash memory is placed in low power state.
+ *                false: No effect.
+ */
+void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable)
+{
+    uint32_t reg = 0UL;
+
+    reg |= (disable ? CMC_FLASHCR_FLASHDIS(1U) : CMC_FLASHCR_FLASHDIS(0U)) |
+           (doze ? CMC_FLASHCR_FLASHDOZE(1U) : CMC_FLASHCR_FLASHDOZE(0U));
+    base->FLASHCR = reg;
+}
+#else
 /*!
  * brief Configs the low power mode of the on-chip flash memory.
  *
@@ -169,6 +194,7 @@ void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable)
            (wake ? CMC_FLASHCR_FLASHWAKE(1U) : CMC_FLASHCR_FLASHWAKE(0U));
     base->FLASHCR = reg;
 }
+#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */
 
 /*!
  * brief Prepares to enter stop modes.
@@ -233,8 +259,11 @@ void CMC_GlobalEnterLowPowerMode(CMC_Type *base, cmc_low_power_mode_t lowPowerMo
 void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *config)
 {
     assert(config != NULL);
+
+#if (CMC_PMCTRL_COUNT > 1U)
     /* The WAKE domain must never be configured to a lower power mode compared with main power mode. */
     assert(config->wake_domain <= config->main_domain);
+#endif /* (CMC_PMCTRL_COUNT > 1U) */
 
     if (config->clock_mode < kCMC_GateAllSystemClocksEnterLowPowerMode)
     {
@@ -243,7 +272,9 @@ void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *conf
         CMC_SetClockMode(base, config->clock_mode);
 
         CMC_SetMAINPowerMode(base, kCMC_ActiveOrSleepMode);
+#if (CMC_PMCTRL_COUNT > 1U)
         CMC_SetWAKEPowerMode(base, kCMC_ActiveOrSleepMode);
+#endif /* (CMC_PMCTRL_COUNT > 1U) */
 
         /* Before executing WFI instruction read back the last register to
          * ensure all registers writes have completed. */
@@ -258,16 +289,22 @@ void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *conf
         /* Note: unlock the register if this API will be reinvoked later. */
         CMC_SetClockMode(base, kCMC_GateAllSystemClocksEnterLowPowerMode);
         CMC_SetMAINPowerMode(base, config->main_domain);
+#if (CMC_PMCTRL_COUNT > 1U)
         CMC_SetWAKEPowerMode(base, config->wake_domain);
+#endif  /* (CMC_PMCTRL_COUNT > 1U) */
 
         /* Before execute WFI instruction read back the last register to
          * ensure all registers writes have completed. */
+#if (CMC_PMCTRL_COUNT > 1U)
         if ((CMC_GetWAKEPowerMode(base) == config->wake_domain) && (CMC_GetMAINPowerMode(base) == config->main_domain))
         {
+#endif /* (CMC_PMCTRL_COUNT > 1U) */
             SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
             __DSB();
             __WFI();
             __ISB();
+#if (CMC_PMCTRL_COUNT > 1U)
         }
+#endif /* (CMC_PMCTRL_COUNT > 1U) */
     }
 }

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_cmc.h

@@ -1,11 +1,11 @@
 /*
- * Copyright 2022 NXP
+ * Copyright 2022-2024 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_CMC_H_
-#define _FSL_CMC_H_
+#ifndef FSL_CMC_H_
+#define FSL_CMC_H_
 #include "fsl_common.h"
 
 /*!
@@ -17,8 +17,8 @@
  ******************************************************************************/
 /*! @name Driver version */
 /*@{*/
-/*! @brief CMC driver version 2.0.0. */
-#define FSL_CMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief CMC driver version 2.2.2. */
+#define FSL_CMC_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
 /* @} */
 
 /*!
@@ -34,6 +34,8 @@ enum _cmc_power_mode_protection
 
 /*!
  * @brief Wake up sources from the previous low power mode entry.
+ *
+ * @note #kCMC_WakeupFromUsbFs, #kCMC_WakeupFromITRC, #kCMC_WakeupFromCpu1 are not supported in MCXA family.
  */
 enum _cmc_wakeup_sources
 {
@@ -59,14 +61,25 @@ enum _cmc_system_reset_interrupt_enable
                                                                                     Reset interrupt enable. */
     kCMC_WindowedWatchdog0ResetInterruptEnable = CMC_SRIE_WWDT0_MASK,          /*!< Windowed Watchdog 0 reset
                                                                                  interrupt enable. */
-    kCMC_SoftwareResetInterruptEnable          = CMC_SRIE_SW_MASK,             /*!< Software Reset interrupt enable. */
-    kCMC_LockupResetInterruptEnable            = CMC_SRIE_LOCKUP_MASK,         /*!< Lockup Reset interrupt enable. */
-    kCMC_Cpu1ResetInterruptEnable              = CMC_SRIE_CPU1_MASK,           /*!< CPU1 Reset interrupt enable. */
-    kCMC_VBATResetInterruptEnable              = CMC_SRIE_VBAT_MASK,           /*!< VBAT reset interrupt enable. */
+    kCMC_SoftwareResetInterruptEnable = CMC_SRIE_SW_MASK,                      /*!< Software Reset interrupt enable. */
+    kCMC_LockupResetInterruptEnable   = CMC_SRIE_LOCKUP_MASK,                  /*!< Lockup Reset interrupt enable. */
+#if defined(CMC_SRIE_CPU1_MASK)
+    kCMC_Cpu1ResetInterruptEnable = CMC_SRIE_CPU1_MASK,                        /*!< CPU1 Reset interrupt enable. */
+#endif                                                                         /* CMC_SRIE_CPU1_MASK */
+#if defined(CMC_SRIE_ADVC_MASK)
+    kCMC_AdvcResetInterruptEnable = CMC_SRIE_ADVC_MASK,                        /*!< ADVC Reset interrupt enable. */
+#endif                                                                         /* CMC_SRIE_ADVC_MASK */
+#if defined(CMC_SRIE_VBAT_MASK)
+    kCMC_VBATResetInterruptEnable = CMC_SRIE_VBAT_MASK,                        /*!< VBAT reset interrupt enable. */
+#endif                                                                         /* CMC_SRIE_VBAT_MASK */
+#if defined(CMC_SRIE_WWDT1_MASK)
     kCMC_WindowedWatchdog1ResetInterruptEnable = CMC_SRIE_WWDT1_MASK,          /*!< Windowed Watchdog 1 reset
                                                                                      interrupt enable. */
+#endif                                                                         /* CMC_SRIE_WWDT1_MASK */
     kCMC_CodeWatchDog0ResetInterruptEnable = CMC_SRIE_CDOG0_MASK, /*!< Code watchdog 0 reset interrupt enable. */
+#if defined(CMC_SRIE_CDOG1_MASK)
     kCMC_CodeWatchDog1ResetInterruptEnable = CMC_SRIE_CDOG1_MASK, /*!< Code watchdog 1 reset interrupt enable. */
+#endif                                                            /* CMC_SRIE_CDOG1_MASK */
 };
 
 /*!
@@ -81,13 +94,25 @@ enum _cmc_system_reset_interrupt_flag
     kCMC_WindowedWatchdog0ResetInterruptFlag = CMC_SRIF_WWDT0_MASK,  /*!< Windowned Watchdog 0 Reset interrupt flag. */
     kCMC_SoftwareResetInterruptFlag          = CMC_SRIF_SW_MASK,     /*!< Software Reset interrupt flag. */
     kCMC_LockupResetInterruptFlag            = CMC_SRIF_LOCKUP_MASK, /*!< Lock up Reset interrupt flag. */
-    kCMC_Cpu1ResetInterruptFlag              = CMC_SRIF_CPU1_MASK,   /*!< CPU1 Reset interrupt flag. */
-    kCMC_VbatResetInterruptFlag              = CMC_SRIF_VBAT_MASK,   /*!< VBAT system reset interrupt flag. */
+#if defined(CMC_SRIF_CPU1_MASK)
+    kCMC_Cpu1ResetInterruptFlag = CMC_SRIF_CPU1_MASK,                /*!< CPU1 Reset interrupt flag. */
+#endif                                                               /* CMC_SRIF_CPU1_MASK */
+#if defined(CMC_SRIF_ADVC_MASK)
+    kCMC_AdvcResetInterruptFlag = CMC_SRIF_ADVC_MASK,                /*!< ADVC Reset interrupt flag. */
+#endif                                                               /* CMC_SRIF_ADVC_MASK */
+#if defined(CMC_SRIF_VBAT_MASK)
+    kCMC_VbatResetInterruptFlag = CMC_SRIF_VBAT_MASK,                /*!< VBAT system reset interrupt flag. */
+#endif                                                               /* CMC_SRIF_VBAT_MASK */
+#if defined(CMC_SRIF_WWDT1_MASK)
     kCMC_WindowedWatchdog1ResetInterruptFlag = CMC_SRIF_WWDT1_MASK,  /*!< Windowned Watchdog 1 Reset interrupt flag. */
-    kCMC_CodeWatchdog0ResetInterruptFlag     = CMC_SRIF_CDOG0_MASK,  /*!< Code watchdog0 reset interrupt flag. */
-    kCMC_CodeWatchdog1ResetInterruptFlag     = CMC_SRIF_CDOG1_MASK,  /*!< Code watchdog1 reset interrupt flag. */
+#endif                                                               /* CMC_SRIF_WWDT1_MASK */
+    kCMC_CodeWatchdog0ResetInterruptFlag = CMC_SRIF_CDOG0_MASK,      /*!< Code watchdog0 reset interrupt flag. */
+#if defined(CMC_SRIF_CDOG1_MASK)
+    kCMC_CodeWatchdog1ResetInterruptFlag = CMC_SRIF_CDOG1_MASK,      /*!< Code watchdog1 reset interrupt flag. */
+#endif                                                               /* CMC_SRIF_CDOG1_MASK */
 };
 
+#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG)
 /*!
  * @brief CMC System SRAM arrays low power mode enable enumeration.
  */
@@ -114,7 +139,13 @@ enum _cmc_system_sram_arrays
     kCMC_PQ                  = 1UL << 27UL, /*!< Used to control PQ. */
     kCMC_CAN0_CAN1_ENET_USB1 = 1UL << 28UL, /*!< Used to control CAN0, CAN1, ENET, USB1. */
     kCMC_FlexSPI             = 1UL << 29UL, /*!< Used to control FlexSPI. */
+
+    kCMC_AllSramArrays = (kCMC_RAMX0 | kCMC_RAMX1 | kCMC_RAMX2 | kCMC_RAMB | kCMC_RAMC0 | kCMC_RAMC1 | kCMC_RAMD0 |
+                          kCMC_RAMD1 | kCMC_RAME0 | kCMC_RAME1 | kCMC_RAMF0 | kCMC_RAMF1 | kCMC_RAMG0_RAMG1 |
+                          kCMC_RAMG2_RAMG3 | kCMC_RAMH0_RAMH1 | kCMC_LPCAC | kCMC_DMA0_DMA1_PKC | kCMC_USB0 | kCMC_PQ |
+                          kCMC_CAN0_CAN1_ENET_USB1 | kCMC_FlexSPI), /*!< Mask of all System SRAM arrays. */
 };
+#endif                                                              /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
 
 /*!
  * @brief System reset sources enumeration.
@@ -137,14 +168,29 @@ enum _cmc_system_reset_sources
     kCMC_WindowedWatchdog0Reset = CMC_SRS_WWDT0_MASK, /*!< The reset caused by the Windowed WatchDog 0 timeout. */
     kCMC_SoftwareReset          = CMC_SRS_SW_MASK,    /*!< The reset caused by a software reset request. */
     kCMC_LockUoReset = CMC_SRS_LOCKUP_MASK, /*!< The reset caused by the ARM core indication of a LOCKUP event. */
-    kCMC_Cpu1Reset   = CMC_SRS_CPU1_MASK,   /*!< The reset caused by a CPU1 system reset. */
-    kCMC_VbatReset   = CMC_SRS_VBAT_MASK,   /*!< The reset caused by a VBAT POR. */
+#if defined(CMC_SRS_CPU1_MASK)
+    kCMC_Cpu1Reset = CMC_SRS_CPU1_MASK,     /*!< The reset caused by a CPU1 system reset. */
+#endif                                      /* CMC_SRS_CPU1_MASK */
+#if defined(CMC_SRS_ADVC_MASK)
+    kCMC_AdvcReset = CMC_SRS_ADVC_MASK,     /*!< The reset caused by ADVC critical reset.  */
+#endif                                      /* CMC_SRS_ADVC_MASK */
+#if defined(CMC_SRS_VBAT_MASK)
+    kCMC_VbatReset = CMC_SRS_VBAT_MASK,     /*!< The reset caused by a VBAT POR. */
+#endif                                      /* CMC_SRS_VBAT_MASK */
+#if defined(CMC_SRS_WWDT1_MASK)
     kCMC_WindowedWatchdog1Reset = CMC_SRS_WWDT1_MASK,  /*!< The reset caused by the Windowed WatchDog 1 timeout. */
-    kCMC_CodeWatchDog0Reset     = CMC_SRS_CDOG0_MASK,  /*!< The reset caused by the code watchdog0 fault. */
-    kCMC_CodeWatchDog1Reset     = CMC_SRS_CDOG1_MASK,  /*!< The reset caused by the code watchdog1 fault. */
-    kCMC_JTAGSystemReset        = CMC_SRS_JTAG_MASK,   /*!< The reset caused by a JTAG system reset request. */
+#endif                                                 /* CMC_SRS_WWDT1_MASK */
+    kCMC_CodeWatchDog0Reset = CMC_SRS_CDOG0_MASK,      /*!< The reset caused by the code watchdog0 fault. */
+#if defined(CMC_SRS_CDOG1_MASK)
+    kCMC_CodeWatchDog1Reset = CMC_SRS_CDOG1_MASK,      /*!< The reset caused by the code watchdog1 fault. */
+#endif                                                 /* CMC_SRS_CDOG1_MASK */
+    kCMC_JTAGSystemReset = CMC_SRS_JTAG_MASK,          /*!< The reset caused by a JTAG system reset request. */
+#if defined(CMC_SRS_SECVIO_MASK)
     kCMC_SecurityViolationReset = CMC_SRS_SECVIO_MASK, /*!< The reset caused by a Security Violation logic. */
-    kCMC_TapmerReset            = CMC_SRS_TAMPER_MASK, /*!< The reset caused by the tamper detection logic. */
+#endif                                                 /* CMC_SRS_SECVIO_MASK */
+#if defined(CMC_SRS_TAMPER_MASK)
+    kCMC_TapmerReset = CMC_SRS_TAMPER_MASK,            /*!< The reset caused by the tamper detection logic. */
+#endif                                                 /* CMC_SRS_TAMPER_MASK */
 };
 
 /*!
@@ -197,7 +243,9 @@ typedef struct _cmc_power_domain_config
 {
     cmc_clock_mode_t clock_mode;      /*!< Clock mode for each power domain. */
     cmc_low_power_mode_t main_domain; /*!< The low power mode of the MAIN power domain. */
+#if (CMC_PMCTRL_COUNT > 1U)
     cmc_low_power_mode_t wake_domain; /*!< The low power mode of the WAKE power domain. */
+#endif                                /* (CMC_PMCTRL_COUNT > 1U) */
 } cmc_power_domain_config_t;
 
 /*******************************************************************************
@@ -335,8 +383,9 @@ static inline void CMC_ClearStickySystemResetStatus(CMC_Type *base, uint32_t mas
     base->SSRS = mask;
 }
 
+#if (defined(FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG) && FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG)
 /*!
- * @brief Gets the number of reset sequences completed since the last WAKE Cold Reset.
+ * @brief Gets the number of reset sequences completed since the last Cold Reset.
  *
  * @param base CMC peripheral base address.
  * @return The number of reset sequences.
@@ -345,6 +394,7 @@ static inline uint8_t CMC_GetResetCount(CMC_Type *base)
 {
     return (uint8_t)(base->RSTCNT & CMC_RSTCNT_COUNT_MASK);
 }
+#endif /* FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG */
 
 /* @} */
 
@@ -422,6 +472,7 @@ static inline cmc_low_power_mode_t CMC_GetMAINPowerMode(CMC_Type *base)
     return (cmc_low_power_mode_t)(uint32_t)(base->PMCTRL[0] & CMC_PMCTRL_LPMODE_MASK);
 }
 
+#if (CMC_PMCTRL_COUNT > 1U)
 /*!
  * @brief Configure entry into low power mode for the WAKE Power domain.
  *
@@ -451,6 +502,7 @@ static inline cmc_low_power_mode_t CMC_GetWAKEPowerMode(CMC_Type *base)
 {
     return (cmc_low_power_mode_t)(uint32_t)(base->PMCTRL[1] & CMC_PMCTRL_LPMODE_MASK);
 }
+#endif /* CMC_PMCTRL_COUNT > 1U */
 
 /* @} */
 
@@ -626,6 +678,7 @@ static inline void CMC_ForceBootConfiguration(CMC_Type *base, bool assert)
  * @{
  */
 
+#if (defined(FSL_FEATURE_MCX_CMC_HAS_BSR_REG) && FSL_FEATURE_MCX_CMC_HAS_BSR_REG)
 /*!
  * @brief Gets the status information written by the BootROM.
  *
@@ -649,7 +702,9 @@ static inline void CMC_SetBootRomStatus(CMC_Type *base, uint32_t statValue)
 {
     base->BSR = CMC_BSR_STAT(statValue);
 }
+#endif /* FSL_FEATURE_MCX_CMC_HAS_BSR_REG */
 
+#if (defined(FSL_FEATURE_MCX_CMC_HAS_BLR_REG) && FSL_FEATURE_MCX_CMC_HAS_BLR_REG)
 /*!
  * @brief Check if BootROM status and lock registers is writtable.
  *
@@ -682,9 +737,11 @@ static inline void CMC_UnlockBootRomStatusWritten(CMC_Type *base)
 {
     base->BLR = CMC_BLR_LOCK(0x2U);
 }
+#endif /* FSL_FEATURE_MCX_CMC_HAS_BLR_REG */
 
 /* @} */
 
+#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG)
 /*!
  * @name System SRAM Configuration.
  * @{
@@ -693,10 +750,12 @@ static inline void CMC_UnlockBootRomStatusWritten(CMC_Type *base)
 /*!
  * @brief Power off the selected system SRAM always.
  *
- * This function power off the selected system SRAM always. The SRAM arrays should
+ * @note This function power off the selected system SRAM always. The SRAM arrays should
  * not be accessed while they are shut down. SRAM array contents are not retained
  * if they are powered off.
  *
+ * @note Once invoked, the previous settings will be overwritten.
+ *
  * @param base CMC peripheral base address.
  * @param mask Bitmap of the SRAM arrays to be powered off all modes.
  *             See @ref _cmc_system_sram_arrays for details.
@@ -707,6 +766,8 @@ void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask);
 /*!
  * @brief Power on SRAM during all mode.
  *
+ * @note Once invoked, the previous settings will be overwritten.
+ *
  * @param base CMC peripheral base address.
  * @param mask Bitmap of the SRAM arrays to be powered on all modes.
  *             See @ref _cmc_system_sram_arrays for details.
@@ -747,11 +808,27 @@ static inline void CMC_PowerOnSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)
 }
 
 /* @} */
+#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
 
 /*!
  * @name Flash Low Power Mode configuration.
  * @{
  */
+
+#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE)
+/*!
+ * @brief Configs the low power mode of the on-chip flash memory.
+ *
+ * This function configs the low power mode of the on-chip flash memory.
+ *
+ * @param base CMC peripheral base address.
+ * @param doze true: Flash is disabled while core is sleeping
+ *             false: No effect.
+ * @param disable true: Flash memory is placed in low power state.
+ *                false: No effect.
+ */
+void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable);
+#else
 /*!
  * @brief Configs the low power mode of the on-chip flash memory.
  *
@@ -766,7 +843,7 @@ static inline void CMC_PowerOnSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)
  *                false: No effect.
  */
 void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable);
-
+#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */
 /* @} */
 
 /*!
@@ -849,4 +926,4 @@ void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *conf
 #endif /* __cplusplus */
 
 /*! @}*/
-#endif /* _FSL_CMC_H_ */
+#endif /* FSL_CMC_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_COMMON_H_
-#define _FSL_COMMON_H_
+#ifndef FSL_COMMON_H_
+#define FSL_COMMON_H_
 
 #include <assert.h>
 #include <stdbool.h>
@@ -57,12 +57,13 @@
 #define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix))
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief common driver version. */
-#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
-/*@}*/
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
+/*! @} */
 
-/* Debug console type definition. */
+/*! @name Debug console type definition. */
+/*! @{ */
 #define DEBUG_CONSOLE_DEVICE_TYPE_NONE       0U  /*!< No debug console.             */
 #define DEBUG_CONSOLE_DEVICE_TYPE_UART       1U  /*!< Debug console based on UART.   */
 #define DEBUG_CONSOLE_DEVICE_TYPE_LPUART     2U  /*!< Debug console based on LPUART. */
@@ -74,6 +75,7 @@
 #define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U  /*!< Debug console based on LPC_USART. */
 #define DEBUG_CONSOLE_DEVICE_TYPE_SWO        9U  /*!< Debug console based on SWO. */
 #define DEBUG_CONSOLE_DEVICE_TYPE_QSCI       10U /*!< Debug console based on QSCI. */
+/*! @} */
 
 /*! @brief Status group numbers. */
 enum _status_groups
@@ -156,6 +158,9 @@ enum _status_groups
     kStatusGroup_PUF                   = 105, /*!< Group number for PUF status codes. */
     kStatusGroup_TOUCH_PANEL           = 106, /*!< Group number for touch panel status codes */
     kStatusGroup_VBAT                  = 107, /*!< Group number for VBAT status codes */
+    kStatusGroup_XSPI                  = 108, /*!< Group number for XSPI status codes */
+    kStatusGroup_PNGDEC                = 109, /*!< Group number for PNGDEC status codes */
+    kStatusGroup_JPEGDEC               = 110, /*!< Group number for JPEGDEC status codes */
 
     kStatusGroup_HAL_GPIO       = 121, /*!< Group number for HAL GPIO status codes. */
     kStatusGroup_HAL_UART       = 122, /*!< Group number for HAL UART status codes. */
@@ -166,6 +171,7 @@ enum _status_groups
     kStatusGroup_HAL_PWM        = 127, /*!< Group number for HAL PWM status codes. */
     kStatusGroup_HAL_RNG        = 128, /*!< Group number for HAL RNG status codes. */
     kStatusGroup_HAL_I2S        = 129, /*!< Group number for HAL I2S status codes. */
+    kStatusGroup_HAL_ADC_SENSOR = 130, /*!< Group number for HAL ADC SENSOR status codes. */
     kStatusGroup_TIMERMANAGER   = 135, /*!< Group number for TiMER MANAGER status codes. */
     kStatusGroup_SERIALMANAGER  = 136, /*!< Group number for SERIAL MANAGER status codes. */
     kStatusGroup_LED            = 137, /*!< Group number for LED status codes. */
@@ -188,15 +194,18 @@ enum _status_groups
     kStatusGroup_LOG            = 154, /*!< Group number for LOG status codes. */
     kStatusGroup_I3CBUS         = 155, /*!< Group number for I3CBUS status codes. */
     kStatusGroup_QSCI           = 156, /*!< Group number for QSCI status codes. */
-    kStatusGroup_SNT            = 157, /*!< Group number for SNT status codes. */
+    kStatusGroup_ELEMU          = 157, /*!< Group number for ELEMU status codes. */
     kStatusGroup_QUEUEDSPI      = 158, /*!< Group number for QSPI status codes. */
     kStatusGroup_POWER_MANAGER  = 159, /*!< Group number for POWER_MANAGER status codes. */
     kStatusGroup_IPED           = 160, /*!< Group number for IPED status codes. */
     kStatusGroup_ELS_PKC        = 161, /*!< Group number for ELS PKC status codes. */
-    kStatusGroup_HOSTIF         = 162, /*!< Group number for HOSTIF status codes. */
-    kStatusGroup_CLIF           = 163, /*!< Group number for CLIF status codes. */
-    kStatusGroup_BMA            = 164, /*!< Group number for BMA status codes. */
-    kStatusGroup_NETC           = 165, /*!< Group number for NETC status codes. */
+    kStatusGroup_CSS_PKC        = 162, /*!< Group number for CSS PKC status codes. */
+    kStatusGroup_HOSTIF         = 163, /*!< Group number for HOSTIF status codes. */
+    kStatusGroup_CLIF           = 164, /*!< Group number for CLIF status codes. */
+    kStatusGroup_BMA            = 165, /*!< Group number for BMA status codes. */
+    kStatusGroup_NETC           = 166, /*!< Group number for NETC status codes. */
+    kStatusGroup_ELE            = 167, /*!< Group number for ELE status codes. */
+    kStatusGroup_GLIKEY         = 168, /*!< Group number for GLIKEY status codes. */
 };
 
 /*! \public
@@ -220,48 +229,66 @@ enum
 /*! @brief Type used for all status and error return values. */
 typedef int32_t status_t;
 
+#ifdef __ZEPHYR__
+#include <zephyr/sys/util.h>
+#else
 /*!
  * @name Min/max macros
  * @{
  */
 #if !defined(MIN)
+/*! Computes the minimum of \a a and \a b. */
 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
 #endif
 
 #if !defined(MAX)
+/*! Computes the maximum of \a a and \a b. */
 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
 #endif
-/* @} */
+/*! @} */
 
 /*! @brief Computes the number of elements in an array. */
 #if !defined(ARRAY_SIZE)
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 #endif
+#endif /* __ZEPHYR__ */
 
 /*! @name UINT16_MAX/UINT32_MAX value */
-/* @{ */
+/*! @{ */
 #if !defined(UINT16_MAX)
+/*! Max value of uint16_t type. */
 #define UINT16_MAX ((uint16_t)-1)
 #endif
 
 #if !defined(UINT32_MAX)
+/*! Max value of uint32_t type. */
 #define UINT32_MAX ((uint32_t)-1)
 #endif
-/* @} */
+/*! @} */
 
-/*! @name Suppress fallthrough warning macro */
-/* For switch case code block, if case section ends without "break;" statement, there wil be
- fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
- To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
- case section which misses "break;"statement.
+/*! Macro to get upper 32 bits of a 64-bit value */
+#if !defined(UINT64_H)
+#define UINT64_H(X)        ((uint32_t)((((uint64_t) (X)) >> 32U) & 0x0FFFFFFFFULL))
+#endif
+
+/*! Macro to get lower 32 bits of a 64-bit value */
+#if !defined(UINT64_L)
+#define UINT64_L(X)        ((uint32_t)(((uint64_t) (X)) & 0x0FFFFFFFFULL))
+#endif
+
+/*!
+ * @def SUPPRESS_FALL_THROUGH_WARNING()
+ *
+ * For switch case code block, if case section ends without "break;" statement, there wil be
+ * fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
+ * To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
+ * case section which misses "break;"statement.
  */
-/* @{ */
 #if defined(__GNUC__) && !defined(__ARMCC_VERSION)
 #define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough))
 #else
 #define SUPPRESS_FALL_THROUGH_WARNING()
 #endif
-/* @} */
 
 /*******************************************************************************
  * API
@@ -309,10 +336,10 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
 
 #if (defined(__DSC__) && defined(__CW__))
 #include "fsl_common_dsc.h"
-#elif defined(__XCC__)
+#elif defined(__XTENSA__)
 #include "fsl_common_dsp.h"
 #else
 #include "fsl_common_arm.h"
 #endif
 
-#endif /* _FSL_COMMON_H_ */
+#endif /* FSL_COMMON_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2021, 2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -25,11 +25,11 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
     extern uint32_t Image$$VECTOR_ROM$$Base[];
     extern uint32_t Image$$VECTOR_RAM$$Base[];
-    extern uint32_t Image$$RW_m_data$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$ZI$$Limit[];
 
 #define __VECTOR_TABLE          Image$$VECTOR_ROM$$Base
 #define __VECTOR_RAM            Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base))
 #elif defined(__ICCARM__)
     extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
     extern uint32_t __VECTOR_TABLE[];
@@ -159,11 +159,11 @@ static void DelayLoop(uint32_t count)
 {
     __ASM volatile("    MOV    X0, %0" : : "r"(count));
     __ASM volatile(
-        "loop:                          \n"
+        "loop%=:                        \n"
         "    SUB    X0, X0, #1          \n"
         "    CMP    X0, #0              \n"
 
-        "    BNE    loop                \n"
+        "    BNE    loop%=              \n"
         :
         :
         : "r0");
@@ -176,7 +176,7 @@ static void DelayLoop(uint32_t count)
 {
     __ASM volatile("    MOV    R0, %0" : : "r"(count));
     __ASM volatile(
-        "loop:                          \n"
+        "loop%=:                        \n"
 #if defined(__GNUC__) && !defined(__ARMCC_VERSION)
         "    SUB    R0, R0, #1          \n"
 #else
@@ -184,7 +184,7 @@ static void DelayLoop(uint32_t count)
 #endif
         "    CMP    R0, #0              \n"
 
-        "    BNE    loop                \n"
+        "    BNE    loop%=              \n"
         :
         :
         : "r0");
@@ -232,13 +232,21 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
         {
         }
 #else
+#if defined(__CORTEX_Axx) && ((__CORTEX_Axx == 53) || (__CORTEX_Axx == 55))
+        /*
+         * Cortex-A53/A55 execution throughput:
+         *  - SUB/CMP: 2 instructions per cycle
+         *  - BNE:     1 instruction per cycle
+         * So, each loop takes 2 CPU cycles.
+         */
+        count = count / 2U;
+#elif (__CORTEX_M == 7)
         /* Divide value may be different in various environment to ensure delay is precise.
          * Every loop count includes three instructions, due to Cortex-M7 sometimes executes
          * two instructions in one period, through test here set divide 1.5. Other M cores use
          * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
          * not matter because other instructions outside while loop is enough to fill the time.
          */
-#if (__CORTEX_M == 7)
         count = count / 3U * 2U;
 #else
         count = count / 4U;

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_common_arm.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_COMMON_ARM_H_
-#define _FSL_COMMON_ARM_H_
+#ifndef FSL_COMMON_ARM_H_
+#define FSL_COMMON_ARM_H_
 
 /*
  * For CMSIS pack RTE.
@@ -28,13 +28,7 @@
  * These macros are used for atomic access, such as read-modify-write
  * to the peripheral registers.
  *
- * - SDK_ATOMIC_LOCAL_ADD
- * - SDK_ATOMIC_LOCAL_SET
- * - SDK_ATOMIC_LOCAL_CLEAR
- * - SDK_ATOMIC_LOCAL_TOGGLE
- * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET
- *
- * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr
+ * Take @ref SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr
  * means the address of the peripheral register or variable you want to modify
  * atomically, the parameter @c clearBits is the bits to clear, the parameter
  * @c setBits it the bits to set.
@@ -59,6 +53,27 @@
  * @{
  */
 
+/*!
+ * @def SDK_ATOMIC_LOCAL_ADD(addr, val)
+ * Add value \a val from the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_SUB(addr, val)
+ * Subtract value \a val to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_SET(addr, bits)
+ * Set the bits specifiled by \a bits to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_CLEAR(addr, bits)
+ * Clear the bits specifiled by \a bits to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)
+ * Toggle the bits specifiled by \a bits to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)
+ * For the variable at address \a address, clear the bits specifiled by \a clearBits
+ * and set the bits specifiled by \a setBits.
+ */
+
 /* clang-format off */
 #if ((defined(__ARM_ARCH_7M__     ) && (__ARM_ARCH_7M__      == 1)) || \
      (defined(__ARM_ARCH_7EM__    ) && (__ARM_ARCH_7EM__     == 1)) || \
@@ -220,6 +235,12 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
          ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \
                                      _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val))))
 
+#define SDK_ATOMIC_LOCAL_SUB(addr, val)                                                                                        \
+    ((1UL == sizeof(*(addr))) ?                                                                                                \
+         _SDK_AtomicLocalSub1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) :                               \
+         ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSub2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \
+                                     _SDK_AtomicLocalSub4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val))))
+
 #define SDK_ATOMIC_LOCAL_SET(addr, bits)                                                                                        \
     ((1UL == sizeof(*(addr))) ?                                                                                                 \
          _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) :                               \
@@ -255,7 +276,16 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
         s_atomicOldInt = DisableGlobalIRQ(); \
         *(addr) += (val);                    \
         EnableGlobalIRQ(s_atomicOldInt);     \
-    } while (0)
+    } while (false)
+
+#define SDK_ATOMIC_LOCAL_SUB(addr, val)      \
+    do                                       \
+    {                                        \
+        uint32_t s_atomicOldInt;             \
+        s_atomicOldInt = DisableGlobalIRQ(); \
+        *(addr) -= (val);                    \
+        EnableGlobalIRQ(s_atomicOldInt);     \
+    } while (false)
 
 #define SDK_ATOMIC_LOCAL_SET(addr, bits)     \
     do                                       \
@@ -264,7 +294,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
         s_atomicOldInt = DisableGlobalIRQ(); \
         *(addr) |= (bits);                   \
         EnableGlobalIRQ(s_atomicOldInt);     \
-    } while (0)
+    } while (false)
 
 #define SDK_ATOMIC_LOCAL_CLEAR(addr, bits)   \
     do                                       \
@@ -273,7 +303,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
         s_atomicOldInt = DisableGlobalIRQ(); \
         *(addr) &= ~(bits);                  \
         EnableGlobalIRQ(s_atomicOldInt);     \
-    } while (0)
+    } while (false)
 
 #define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)  \
     do                                       \
@@ -282,7 +312,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
         s_atomicOldInt = DisableGlobalIRQ(); \
         *(addr) ^= (bits);                   \
         EnableGlobalIRQ(s_atomicOldInt);     \
-    } while (0)
+    } while (false)
 
 #define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
     do                                                           \
@@ -291,13 +321,13 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
         s_atomicOldInt = DisableGlobalIRQ();                     \
         *(addr)        = (*(addr) & ~(clearBits)) | (setBits);   \
         EnableGlobalIRQ(s_atomicOldInt);                         \
-    } while (0)
+    } while (false)
 
 #endif
-/* @} */
+/*! @} */
 
 /*! @name Timer utilities */
-/* @{ */
+/*! @{ */
 /*! Macro to convert a microsecond period to raw count value */
 #define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
 /*! Macro to convert a raw count value to microsecond */
@@ -307,7 +337,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
 #define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U)
 /*! Macro to convert a raw count value to millisecond */
 #define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz))
-/* @} */
+/*! @} */
 
 /*! @name ISR exit barrier
  * @{
@@ -324,10 +354,10 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
 #define SDK_ISR_EXIT_BARRIER
 #endif
 
-/* @} */
+/*! @} */
 
 /*! @name Alignment variable definition macros */
-/* @{ */
+/*! @{ */
 #if (defined(__ICCARM__))
 /*
  * Workaround to disable MISRA C message suppress warnings for IAR compiler.
@@ -341,7 +371,7 @@ _Pragma("diag_suppress=Pm120")
 #elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
 /*! Macro to define a variable with alignbytes alignment */
 #define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
-#elif defined(__GNUC__)
+#elif defined(__GNUC__) || defined(DOXYGEN_OUTPUT)
 /*! Macro to define a variable with alignbytes alignment */
 #define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
 #else
@@ -360,15 +390,37 @@ _Pragma("diag_suppress=Pm120")
 /*! Macro to change a value to a given size aligned value */
 #define SDK_SIZEALIGN(var, alignbytes) \
     ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
-/* @} */
+/*! @} */
 
-/*! @name Non-cacheable region definition macros */
-/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
- * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable
- * variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them,
+/*!
+ * @name Non-cacheable region definition macros
+ *
+ * For initialized non-zero non-cacheable variables, please use "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them. For zero-inited non-cacheable
+ * variables, please use "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them,
  * these zero-inited variables will be initialized to zero in system startup.
+ *
+ * @note For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ *
+ * @{
+ */
+
+/*!
+ * @def AT_NONCACHEABLE_SECTION(var)
+ * Define a variable \a var, and place it in non-cacheable section.
+ *
+ * @def AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)
+ * Define a variable \a var, and place it in non-cacheable section, the start address
+ * of the variable is aligned to \a alignbytes.
+ *
+ * @def AT_NONCACHEABLE_SECTION_INIT(var)
+ * Define a variable \a var with initial value, and place it in non-cacheable section.
+ *
+ * @def AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes)
+ * Define a variable \a var with initial value, and place it in non-cacheable section,
+ * the start address of the variable is aligned to \a alignbytes.
  */
-/* @{ */
 
 #if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \
      defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
@@ -394,7 +446,7 @@ _Pragma("diag_suppress=Pm120")
     __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
 #endif
 
-#elif (defined(__GNUC__))
+#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
 /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
  * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
  */
@@ -417,12 +469,24 @@ _Pragma("diag_suppress=Pm120")
 
 #endif
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Time sensitive region
  * @{
  */
+
+/*!
+ * @def AT_QUICKACCESS_SECTION_CODE(func)
+ * Place function in a section which can be accessed quickly by core.
+ *
+ * @def AT_QUICKACCESS_SECTION_DATA(var)
+ * Place data in a section which can be accessed quickly by core.
+ *
+ * @def AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes)
+ * Place data in a section which can be accessed quickly by core, and the variable
+ * address is set to align with \a alignbytes.
+ */
 #if (defined(__ICCARM__))
 #define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
 #define AT_QUICKACCESS_SECTION_DATA(var)  var @"DataQuickAccess"
@@ -433,7 +497,7 @@ _Pragma("diag_suppress=Pm120")
 #define AT_QUICKACCESS_SECTION_DATA(var)  __attribute__((section("DataQuickAccess"))) var
 #define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
     __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var
-#elif (defined(__GNUC__))
+#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
 #define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
 #define AT_QUICKACCESS_SECTION_DATA(var)  __attribute__((section("DataQuickAccess"))) var
 #define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
@@ -441,18 +505,25 @@ _Pragma("diag_suppress=Pm120")
 #else
 #error Toolchain not supported.
 #endif /* defined(__ICCARM__) */
+/*! @} */
 
-/*! @name Ram Function */
+/*!
+ * @name Ram Function
+ * @{
+ *
+ * @def RAMFUNCTION_SECTION_CODE(func)
+ * Place function in ram.
+ */
 #if (defined(__ICCARM__))
 #define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
 #elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
 #define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
-#elif (defined(__GNUC__))
+#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
 #define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
 #else
 #error Toolchain not supported.
 #endif /* defined(__ICCARM__) */
-/* @} */
+/*! @} */
 
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
         void DefaultISR(void);
@@ -824,4 +895,4 @@ uint32_t MSDK_GetCpuCycleCount(void);
 
 /*! @} */
 
-#endif /* _FSL_COMMON_ARM_H_ */
+#endif /* FSL_COMMON_ARM_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.c

@@ -40,6 +40,10 @@
 /*< Default is resutl type is final checksum */
 #endif /* CRC_DRIVER_USE_CRC16_CCIT_FALSE_AS_DEFAULT */
 
+#if defined(CRC_RSTS)
+#define CRC_RESETS_ARRAY CRC_RSTS
+#endif
+
 /*! @brief CRC type of transpose of read write data */
 typedef enum _crc_transpose_type
 {
@@ -65,9 +69,49 @@ typedef struct _crc_module_config
     crc_bits_t crcBits;                  /*!< Selects 16- or 32- bit CRC protocol. */
 } crc_module_config_t;
 
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(CRC_RESETS_ARRAY)
+/*!
+ * @brief Get instance number for CRC module.
+ *
+ * @param base CRC peripheral base address
+ */
+static uint32_t CRC_GetInstance(CRC_Type *base);
+#endif
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if defined(CRC_RESETS_ARRAY)
+static CRC_Type *const s_crcBases[] = CRC_BASE_PTRS;
+
+/* Reset array */
+static const reset_ip_name_t s_crcResets[] = CRC_RESETS_ARRAY;
+#endif
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
+#if defined(CRC_RESETS_ARRAY)
+static uint32_t CRC_GetInstance(CRC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_crcBases); instance++)
+    {
+        if (s_crcBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_crcBases));
+
+    return instance;
+}
+#endif
 
 /*!
  * @brief Returns transpose type for CRC protocol reflect in parameter.
@@ -191,6 +235,11 @@ void CRC_Init(CRC_Type *base, const crc_config_t *config)
     /* ungate clock */
     CLOCK_EnableClock(kCLOCK_Crc0);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(CRC_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_crcResets[CRC_GetInstance(base)]);
+#endif
+
     /* configure CRC module and write the seed */
     if (config->crcResult == kCrcFinalChecksum)
     {

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_crc.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_CRC_H_
-#define _FSL_CRC_H_
+#ifndef FSL_CRC_H_
+#define FSL_CRC_H_
 
 #include "fsl_common.h"
 
@@ -21,13 +21,16 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
-/*! @brief CRC driver version. Version 2.0.3.
+/*! @{ */
+/*! @brief CRC driver version. Version 2.0.4.
  *
- * Current version: 2.0.3
+ * Current version: 2.0.4
  *
  * Change log:
  *
+ * - Version 2.0.4
+ *   - Release peripheral from reset if necessary in init function.
+ * 
  * - Version 2.0.3
  *   - Fix MISRA issues
  *
@@ -37,8 +40,8 @@
  * - Version 2.0.1
  *   - move DATA and DATALL macro definition from header file to source file
  */
-#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
-/*@}*/
+#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*! @} */
 
 #ifndef CRC_DRIVER_CUSTOM_DEFAULTS
 /*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */
@@ -175,4 +178,4 @@ uint16_t CRC_Get16bitResult(CRC_Type *base);
  *@}
  */
 
-#endif /* _FSL_CRC_H_ */
+#endif /* FSL_CRC_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.c

@@ -575,3 +575,30 @@ void CTIMER4_DriverIRQHandler(void)
     SDK_ISR_EXIT_BARRIER;
 }
 #endif
+
+#if defined(CTIMER5)
+void CTIMER5_DriverIRQHandler(void);
+void CTIMER5_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(5);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(CTIMER6)
+void CTIMER6_DriverIRQHandler(void);
+void CTIMER6_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(6);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(CTIMER7)
+void CTIMER7_DriverIRQHandler(void);
+void CTIMER7_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(7);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ctimer.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_CTIMER_H_
-#define _FSL_CTIMER_H_
+#ifndef FSL_CTIMER_H_
+#define FSL_CTIMER_H_
 
 #include "fsl_common.h"
 
@@ -22,9 +22,9 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 #define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1 */
-/*@}*/
+/*! @} */
 
 /*! @brief List of Timer capture channels */
 typedef enum _ctimer_capture_channel
@@ -679,4 +679,4 @@ static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match
 
 /*! @}*/
 
-#endif /* _FSL_CTIMER_H_ */
+#endif /* FSL_CTIMER_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.c

@@ -8,11 +8,20 @@
 
 #include "fsl_dac.h"
 
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
 /* Component ID definition, used by tools. */
 #ifndef FSL_COMPONENT_ID
 #define FSL_COMPONENT_ID "platform.drivers.dac_1"
 #endif
 
+#if defined(DAC_RSTS)
+#define DAC_RESETS_ARRAY DAC_RSTS
+#elif defined(DAC_RSTS_N)
+#define DAC_RESETS_ARRAY DAC_RSTS_N
+#endif
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -34,6 +43,11 @@ static LPDAC_Type *const s_dacBases[] = LPDAC_BASE_PTRS;
 static const clock_ip_name_t s_dacClocks[] = LPDAC_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
+#if defined(DAC_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_dacResets[] = DAC_RESETS_ARRAY;
+#endif
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -74,6 +88,10 @@ void DAC_Init(LPDAC_Type *base, const dac_config_t *config)
     CLOCK_EnableClock(s_dacClocks[DAC_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
+#if defined(DAC_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_dacResets[DAC_GetInstance(base)]);
+#endif
+
     /* Reset the logic. */
     DAC_SetReset(base, kDAC_ResetLogic);
     DAC_ClearReset(base, kDAC_ResetLogic);

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_DAC_H_
-#define _FSL_DAC_H_
+#ifndef FSL_DAC_H_
+#define FSL_DAC_H_
 
 #include "fsl_common.h"
 
@@ -23,10 +23,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
-/*! @brief DAC driver version 2.1.1. */
-#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
-/*@}*/
+/*! @{ */
+/*! @brief DAC driver version 2.1.2. */
+#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
+/*! @} */
 
 /*!
  * @brief DAC reset control.
@@ -293,7 +293,7 @@ static inline void DAC_Enable(LPDAC_Type *base, bool enable)
     }
 }
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Interrupts
@@ -322,7 +322,7 @@ static inline void DAC_DisableInterrupts(LPDAC_Type *base, uint32_t mask)
     base->IER &= ~mask;
 }
 
-/* @} */
+/*! @} */
 
 /*!
  * @name DMA control
@@ -348,7 +348,7 @@ static inline void DAC_EnableDMA(LPDAC_Type *base, uint32_t mask, bool enable)
     }
 }
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Status flags
@@ -377,7 +377,7 @@ static inline void DAC_ClearStatusFlags(LPDAC_Type *base, uint32_t flags)
     base->FSR = flags;
 }
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Functional feature
@@ -430,7 +430,7 @@ static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base)
     base->TCR = LPDAC_TCR_SWTRG_MASK;
 }
 
-/* @} */
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -439,4 +439,4 @@ static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base)
 /*!
  * @}
  */
-#endif /* _FSL_DAC12_H_ */
+#endif /* FSL_DAC12_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_dac14.h

@@ -5,8 +5,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_DAC14_H_
-#define _FSL_DAC14_H_
+#ifndef FSL_DAC14_H_
+#define FSL_DAC14_H_
 
 #include "fsl_common.h"
 
@@ -22,10 +22,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief DAC14 driver version 2.0.0. */
 #define FSL_DAC14_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
+/*! @} */
 
 /*!
  * @brief DAC14 interrupts enumeration.
@@ -209,7 +209,7 @@ static inline void DAC14_AbortPeriodTriggerConvSequence(HPDAC_Type *base)
 {
     base->GCR &= ~HPDAC_GCR_PTGEN_MASK;
 }
-/* @} */
+/*! @} */
 
 /*!
  * @name DAC Control Interface
@@ -233,7 +233,7 @@ static inline void DAC14_Enable(HPDAC_Type *base, bool enable)
         base->GCR &= ~HPDAC_GCR_DACEN_MASK;
     }
 }
-/* @} */
+/*! @} */
 
 /*!
  * @name Swing Back Mode Control Interface
@@ -256,7 +256,7 @@ static inline void DAC14_EnableSwingBackMode(HPDAC_Type *base, bool enable)
         base->GCR &= ~HPDAC_GCR_SWMD_MASK;
     }
 }
-/* @} */
+/*! @} */
 
 /*!
  * @name FIFO Mode Control Interface
@@ -279,7 +279,7 @@ static inline void DAC14_EnableFIFOMode(HPDAC_Type *base, bool enable)
         base->GCR &= ~HPDAC_GCR_FIFOEN_MASK;
     }
 }
-/* @} */
+/*! @} */
 
 /*!
  * @name Interrupts
@@ -306,7 +306,7 @@ static inline void DAC14_DisableInterrupts(HPDAC_Type *base, uint32_t mask)
 {
     base->IER &= ~mask;
 }
-/* @} */
+/*! @} */
 
 /*!
  * @name DMA Control Interface
@@ -330,7 +330,7 @@ static inline void DAC14_EnableDMA(HPDAC_Type *base, uint32_t mask, bool enable)
         base->DER &= ~mask;
     }
 }
-/* @} */
+/*! @} */
 
 /*!
  * @name Status
@@ -357,7 +357,7 @@ static inline void DAC14_ClearStatusFlags(HPDAC_Type *base, uint32_t flags)
 {
     base->FSR = flags;
 }
-/* @} */
+/*! @} */
 
 /*!
  * @name Functional Feature
@@ -407,7 +407,7 @@ static inline void DAC14_DoSoftwareTrigger(HPDAC_Type *base)
 {
     base->TCR = HPDAC_TCR_SWTRG_MASK;
 }
-/* @} */
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -416,4 +416,4 @@ static inline void DAC14_DoSoftwareTrigger(HPDAC_Type *base)
 /*!
  * @}
  */
-#endif /* _FSL_DAC14_H_ */
+#endif /* FSL_DAC14_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_core.h

@@ -4,8 +4,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_EDMA_CORE_H_
-#define _FSL_EDMA_CORE_H_
+#ifndef FSL_EDMA_CORE_H_
+#define FSL_EDMA_CORE_H_
 
 #include "fsl_edma_soc.h"
 
@@ -17,163 +17,209 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
-#if defined(FSL_EDMA_SOC_IP_DMA3) && defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA3 && FSL_EDMA_SOC_IP_DMA4
-#define DMA_CSR_INTMAJOR_MASK          DMA_TCD_CSR_INTMAJOR_MASK
-#define DMA_CSR_INTHALF_MASK           DMA_TCD_CSR_INTHALF_MASK
-#define DMA_CSR_DREQ_MASK              DMA_TCD_CSR_DREQ_MASK
-#define DMA_CSR_ESG_MASK               DMA_TCD_CSR_ESG_MASK
-#define DMA_CSR_START_MASK             DMA_TCD_CSR_START_MASK
-#define DMA_CITER_ELINKNO_CITER_MASK   DMA_TCD_CITER_ELINKNO_CITER_MASK
-#define DMA_BITER_ELINKNO_BITER_MASK   DMA_TCD_BITER_ELINKNO_BITER_MASK
-#define DMA_CITER_ELINKNO_CITER_SHIFT  DMA_TCD_CITER_ELINKNO_CITER_SHIFT
-#define DMA_CITER_ELINKYES_CITER_MASK  DMA_TCD_CITER_ELINKYES_CITER_MASK
-#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT
-#define DMA_ATTR_SMOD_MASK             DMA_TCD_ATTR_SMOD_MASK
-#define DMA_ATTR_DMOD_MASK             DMA_TCD_ATTR_DMOD_MASK
-#define DMA_CITER_ELINKNO_ELINK_MASK   DMA_TCD_CITER_ELINKNO_ELINK_MASK
-#define DMA_CSR_MAJORELINK_MASK        DMA_TCD_CSR_MAJORELINK_MASK
-#define DMA_BITER_ELINKYES_ELINK_MASK  DMA_TCD_BITER_ELINKYES_ELINK_MASK
-#define DMA_CITER_ELINKYES_ELINK_MASK  DMA_TCD_CITER_ELINKYES_ELINK_MASK
-#define DMA_CSR_MAJORLINKCH_MASK       DMA_TCD_CSR_MAJORLINKCH_MASK
-#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK
-#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK
-#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK
-#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK
-#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK
-#define DMA_NBYTES_MLOFFNO_NBYTES_MASK DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK
-#define DMA_ATTR_DMOD(x)               DMA_TCD_ATTR_DMOD(x)
-#define DMA_ATTR_SMOD(X)               DMA_TCD_ATTR_SMOD(X)
-#define DMA_BITER_ELINKYES_LINKCH(x)   DMA_TCD_BITER_ELINKYES_LINKCH(x)
-#define DMA_CITER_ELINKYES_LINKCH(x)   DMA_TCD_CITER_ELINKYES_LINKCH(x)
-#define DMA_NBYTES_MLOFFYES_MLOFF(x)   DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)
-#define DMA_NBYTES_MLOFFYES_DMLOE(x)   DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)
-#define DMA_NBYTES_MLOFFYES_SMLOE(x)   DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)
-#define DMA_NBYTES_MLOFFNO_NBYTES(x)   DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)
-#define DMA_NBYTES_MLOFFYES_NBYTES(x)  DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)
-#define DMA_ATTR_DSIZE(x)              DMA_TCD_ATTR_DSIZE(x)
-#define DMA_ATTR_SSIZE(x)              DMA_TCD_ATTR_SSIZE(x)
-#define DMA_CSR_DREQ(x)                DMA_TCD_CSR_DREQ(x)
-#define DMA_CSR_MAJORLINKCH(x)         DMA_TCD_CSR_MAJORLINKCH(x)
-#define DMA_CH_MATTR_WCACHE(x)         DMA4_CH_MATTR_WCACHE(x)
-#define DMA_CH_MATTR_RCACHE(x)         DMA4_CH_MATTR_RCACHE(x)
-#define DMA_CH_CSR_SIGNEXT_MASK        DMA4_CH_CSR_SIGNEXT_MASK
-#define DMA_CH_CSR_SIGNEXT_SHIFT       DMA4_CH_CSR_SIGNEXT_SHIFT
-#define DMA_CH_CSR_SWAP_MASK           DMA4_CH_CSR_SWAP_MASK
-#define DMA_CH_CSR_SWAP_SHIFT          DMA4_CH_CSR_SWAP_SHIFT
-#define DMA_CH_SBR_INSTR_MASK          DMA4_CH_SBR_INSTR_MASK
-#define DMA_CH_SBR_INSTR_SHIFT         DMA4_CH_SBR_INSTR_SHIFT
-#define DMA_CH_MUX_SOURCE(x)           DMA4_CH_MUX_SRC(x)
-#elif defined(FSL_EDMA_SOC_IP_DMA3) && FSL_EDMA_SOC_IP_DMA3 && \
-    (!defined(FSL_EDMA_SOC_IP_DMA4) || (defined(FSL_EDMA_SOC_IP_DMA4) && !FSL_EDMA_SOC_IP_DMA4))
-#define DMA_CSR_INTMAJOR_MASK          DMA_TCD_CSR_INTMAJOR_MASK
-#define DMA_CSR_INTHALF_MASK           DMA_TCD_CSR_INTHALF_MASK
-#define DMA_CSR_DREQ_MASK              DMA_TCD_CSR_DREQ_MASK
-#define DMA_CSR_ESG_MASK               DMA_TCD_CSR_ESG_MASK
-#define DMA_CSR_START_MASK             DMA_TCD_CSR_START_MASK
-#define DMA_CITER_ELINKNO_CITER_MASK   DMA_TCD_CITER_ELINKNO_CITER_MASK
-#define DMA_BITER_ELINKNO_BITER_MASK   DMA_TCD_BITER_ELINKNO_BITER_MASK
-#define DMA_CITER_ELINKNO_CITER_SHIFT  DMA_TCD_CITER_ELINKNO_CITER_SHIFT
-#define DMA_CITER_ELINKYES_CITER_MASK  DMA_TCD_CITER_ELINKYES_CITER_MASK
-#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT
-#define DMA_ATTR_SMOD_MASK             DMA_TCD_ATTR_SMOD_MASK
-#define DMA_ATTR_DMOD_MASK             DMA_TCD_ATTR_DMOD_MASK
-#define DMA_CITER_ELINKNO_ELINK_MASK   DMA_TCD_CITER_ELINKNO_ELINK_MASK
-#define DMA_CSR_MAJORELINK_MASK        DMA_TCD_CSR_MAJORELINK_MASK
-#define DMA_BITER_ELINKYES_ELINK_MASK  DMA_TCD_BITER_ELINKYES_ELINK_MASK
-#define DMA_CITER_ELINKYES_ELINK_MASK  DMA_TCD_CITER_ELINKYES_ELINK_MASK
-#define DMA_CSR_MAJORLINKCH_MASK       DMA_TCD_CSR_MAJORLINKCH_MASK
-#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK
-#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK
-#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK
-#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK
-#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK
-#define DMA_ATTR_DMOD(x)               DMA_TCD_ATTR_DMOD(x)
-#define DMA_ATTR_SMOD(X)               DMA_TCD_ATTR_SMOD(X)
-#define DMA_BITER_ELINKYES_LINKCH(x)   DMA_TCD_BITER_ELINKYES_LINKCH(x)
-#define DMA_CITER_ELINKYES_LINKCH(x)   DMA_TCD_CITER_ELINKYES_LINKCH(x)
-#define DMA_NBYTES_MLOFFYES_MLOFF(x)   DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)
-#define DMA_NBYTES_MLOFFYES_DMLOE(x)   DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)
-#define DMA_NBYTES_MLOFFYES_SMLOE(x)   DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)
-#define DMA_NBYTES_MLOFFNO_NBYTES(x)   DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)
-#define DMA_NBYTES_MLOFFYES_NBYTES(x)  DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)
-#define DMA_ATTR_DSIZE(x)              DMA_TCD_ATTR_DSIZE(x)
-#define DMA_ATTR_SSIZE(x)              DMA_TCD_ATTR_SSIZE(x)
-#define DMA_CSR_DREQ(x)                DMA_TCD_CSR_DREQ(x)
-#define DMA_CSR_MAJORLINKCH(x)         DMA_TCD_CSR_MAJORLINKCH(x)
-#define DMA_CH_MUX_SOURCE(x)           DMA_CH_MUX_SRC(x)
-#elif defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA4 && \
-    (!defined(FSL_EDMA_SOC_IP_DMA3) || (defined(FSL_EDMA_SOC_IP_DMA3) && !FSL_EDMA_SOC_IP_DMA3))
-#define DMA_CSR_INTMAJOR_MASK          DMA4_CSR_INTMAJOR_MASK
-#define DMA_CSR_INTHALF_MASK           DMA4_CSR_INTHALF_MASK
-#define DMA_CSR_DREQ_MASK              DMA4_CSR_DREQ_MASK
-#define DMA_CSR_ESG_MASK               DMA4_CSR_ESG_MASK
-#define DMA_CSR_START_MASK             DMA4_CSR_START_MASK
-#define DMA_CITER_ELINKNO_CITER_MASK   DMA4_CITER_ELINKNO_CITER_MASK
-#define DMA_BITER_ELINKNO_BITER_MASK   DMA4_BITER_ELINKNO_BITER_MASK
-#define DMA_CITER_ELINKNO_CITER_SHIFT  DMA4_CITER_ELINKNO_CITER_SHIFT
-#define DMA_CITER_ELINKYES_CITER_MASK  DMA4_CITER_ELINKYES_CITER_MASK
-#define DMA_CITER_ELINKYES_CITER_SHIFT DMA4_CITER_ELINKYES_CITER_SHIFT
-#define DMA_ATTR_SMOD_MASK             DMA4_ATTR_SMOD_MASK
-#define DMA_ATTR_DMOD_MASK             DMA4_ATTR_DMOD_MASK
-#define DMA_CITER_ELINKNO_ELINK_MASK   DMA4_CITER_ELINKNO_ELINK_MASK
-#define DMA_CSR_MAJORELINK_MASK        DMA4_CSR_MAJORELINK_MASK
-#define DMA_BITER_ELINKYES_ELINK_MASK  DMA4_BITER_ELINKYES_ELINK_MASK
-#define DMA_CITER_ELINKYES_ELINK_MASK  DMA4_CITER_ELINKYES_ELINK_MASK
-#define DMA_CSR_MAJORLINKCH_MASK       DMA4_CSR_MAJORLINKCH_MASK
-#define DMA_BITER_ELINKYES_LINKCH_MASK DMA4_BITER_ELINKYES_LINKCH_MASK
-#define DMA_CITER_ELINKYES_LINKCH_MASK DMA4_CITER_ELINKYES_LINKCH_MASK
-#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA4_NBYTES_MLOFFYES_MLOFF_MASK
-#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA4_NBYTES_MLOFFYES_DMLOE_MASK
-#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA4_NBYTES_MLOFFYES_SMLOE_MASK
-#define DMA_ATTR_DMOD(x)               DMA4_ATTR_DMOD(x)
-#define DMA_ATTR_SMOD(X)               DMA4_ATTR_SMOD(X)
-#define DMA_BITER_ELINKYES_LINKCH(x)   DMA4_BITER_ELINKYES_LINKCH(x)
-#define DMA_CITER_ELINKYES_LINKCH(x)   DMA4_CITER_ELINKYES_LINKCH(x)
-#define DMA_NBYTES_MLOFFYES_MLOFF(x)   DMA4_NBYTES_MLOFFYES_MLOFF(x)
-#define DMA_NBYTES_MLOFFYES_DMLOE(x)   DMA4_NBYTES_MLOFFYES_DMLOE(x)
-#define DMA_NBYTES_MLOFFYES_SMLOE(x)   DMA4_NBYTES_MLOFFYES_SMLOE(x)
-#define DMA_NBYTES_MLOFFNO_NBYTES(x)   DMA4_NBYTES_MLOFFNO_NBYTES(x)
-#define DMA_NBYTES_MLOFFYES_NBYTES(x)  DMA4_NBYTES_MLOFFYES_NBYTES(x)
-#define DMA_ATTR_DSIZE(x)              DMA4_ATTR_DSIZE(x)
-#define DMA_ATTR_SSIZE(x)              DMA4_ATTR_SSIZE(x)
-#define DMA_CSR_DREQ(x)                DMA4_CSR_DREQ(x)
-#define DMA_CSR_MAJORLINKCH(x)         DMA4_CSR_MAJORLINKCH(x)
-#define DMA_CH_MATTR_WCACHE(x)         DMA4_CH_MATTR_WCACHE(x)
-#define DMA_CH_MATTR_RCACHE(x)         DMA4_CH_MATTR_RCACHE(x)
-#define DMA_CH_CSR_SIGNEXT_MASK        DMA4_CH_CSR_SIGNEXT_MASK
-#define DMA_CH_CSR_SIGNEXT_SHIFT       DMA4_CH_CSR_SIGNEXT_SHIFT
-#define DMA_CH_CSR_SWAP_MASK           DMA4_CH_CSR_SWAP_MASK
-#define DMA_CH_CSR_SWAP_SHIFT          DMA4_CH_CSR_SWAP_SHIFT
-#define DMA_CH_SBR_INSTR_MASK          DMA4_CH_SBR_INSTR_MASK
-#define DMA_CH_SBR_INSTR_SHIFT         DMA4_CH_SBR_INSTR_SHIFT
-#define DMA_CH_MUX_SOURCE(x)           DMA4_CH_MUX_SRC(x)
-#define DMA_CH_CSR_DONE_MASK           DMA4_CH_CSR_DONE_MASK
-#define DMA_CH_CSR_ERQ_MASK            DMA4_CH_CSR_ERQ_MASK
-#elif defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA
-/*! intentional empty */
+#define DMA_CSR_INTMAJOR_MASK          (0x2U)
+#define DMA_CSR_INTHALF_MASK           (0x4U)
+#define DMA_CSR_DREQ_MASK              (0x8U)
+#define DMA_CSR_ESG_MASK               (0x10U)
+#define DMA_CSR_BWC_MASK               (0xC000U)
+#define DMA_CSR_BWC(x)                 (((uint16_t)(((uint16_t)(x)) << (14U))) & (0xC000U))
+#define DMA_CSR_START_MASK             (0x1U)
+#define DMA_CITER_ELINKNO_CITER_MASK   (0x7FFFU)
+#define DMA_BITER_ELINKNO_BITER_MASK   (0x7FFFU)
+#define DMA_CITER_ELINKNO_CITER_SHIFT  (0U)
+#define DMA_CITER_ELINKYES_CITER_MASK  (0x1FFU)
+#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
+#define DMA_ATTR_SMOD_MASK             (0xF800U)
+#define DMA_ATTR_DMOD_MASK             (0xF8U)
+#define DMA_CITER_ELINKNO_ELINK_MASK   (0x8000U)
+#define DMA_CSR_MAJORELINK_MASK        (0x20U)
+#define DMA_BITER_ELINKYES_ELINK_MASK  (0x8000U)
+#define DMA_CITER_ELINKYES_ELINK_MASK  (0x8000U)
+#define DMA_CSR_MAJORLINKCH_MASK       (0x1F00U)
+#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
+#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
+#define DMA_ATTR_DMOD(x)               (((uint16_t)(((uint16_t)(x)) << (3U))) & (0xF8U))
+#define DMA_ATTR_SMOD(x)               (((uint16_t)(((uint16_t)(x)) << (11U))) & (0xF800U))
+#define DMA_BITER_ELINKYES_LINKCH(x)   (((uint16_t)(((uint16_t)(x)) << (9U))) & (0x3E00U))
+#define DMA_CITER_ELINKYES_LINKCH(x)   (((uint16_t)(((uint16_t)(x)) << (9U))) & (0x3E00U))
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)   (((uint32_t)(((uint32_t)(x)) << (10U))) & (0x3FFFFC00U))
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)   (((uint32_t)(((uint32_t)(x)) << (30U))) & (0x40000000U))
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)   (((uint32_t)(((uint32_t)(x)) << (31U))) & (0x80000000U))
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)   (((uint32_t)(((uint32_t)(x)) << (0U))) & (0x3FFFFFFFU))
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)  (((uint32_t)(((uint32_t)(x)) << (0U))) & (0x3FFU))
+#define DMA_ATTR_DSIZE(x)              (((uint16_t)(((uint16_t)(x)) << (0U))) & (0x7U))
+#define DMA_ATTR_SSIZE(x)              (((uint16_t)(((uint16_t)(x)) << (8U))) & (0x700U))
+#define DMA_CSR_DREQ(x)                (((uint16_t)(((uint16_t)(x)) << (3U))) & (0x8U))
+#define DMA_CSR_MAJORLINKCH(x)         (((uint16_t)(((uint16_t)(x)) << (8U))) & (0x1F00U))
+#define DMA_CH_MATTR_WCACHE(x)         (((uint16_t)(((uint16_t)(x)) << (4U))) & (0xF0U))
+#define DMA_CH_MATTR_RCACHE(x)         (((uint16_t)(((uint16_t)(x)) << (0U))) & (0xFU))
+#define DMA_CH_CSR_SIGNEXT_MASK        (0x3F0000U)
+#define DMA_CH_CSR_SIGNEXT_SHIFT       (16U)
+#define DMA_CH_CSR_SWAP_MASK           (0xF000U)
+#define DMA_CH_CSR_SWAP_SHIFT          (12U)
+#define DMA_CH_SBR_INSTR_MASK          (0x2000U)
+#define DMA_CH_SBR_INSTR_SHIFT         (13U)
+#define DMA_CH_MUX_SOURCE(x)           (((uint32_t)(((uint32_t)(x)) << (0U))) & (0xFFU))
+
+/*! @brief DMA error flag */
+#if defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA
+#define DMA_ERR_DBE_FLAG     DMA_ES_DBE_MASK
+#define DMA_ERR_SBE_FLAG     DMA_ES_SBE_MASK
+#define DMA_ERR_SGE_FLAG     DMA_ES_SGE_MASK
+#define DMA_ERR_NCE_FLAG     DMA_ES_NCE_MASK
+#define DMA_ERR_DOE_FLAG     DMA_ES_DOE_MASK
+#define DMA_ERR_DAE_FLAG     DMA_ES_DAE_MASK
+#define DMA_ERR_SOE_FLAG     DMA_ES_SOE_MASK
+#define DMA_ERR_SAE_FLAG     DMA_ES_SAE_MASK
+#define DMA_ERR_ERRCHAN_FLAG DMA_ES_ERRCHN_MASK
+#define DMA_ERR_CPE_FLAG     DMA_ES_CPE_MASK
+#define DMA_ERR_ECX_FLAG     DMA_ES_ECX_MASK
+#if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1)
+#define DMA_ERR_GPE_FLAG DMA_ES_GPE_MASK
 #endif
+#define DMA_ERR_FLAG DMA_ES_VLD_MASK
+
+/*! @brief get/clear DONE status*/
+#define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_BASE(base)->CDNE = (uint8_t)channel)
+#define DMA_GET_DONE_STATUS(base, channel) \
+    ((EDMA_TCD_BASE(base, channel)->CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT)
+/*! @brief enable/disable error interrupt*/
+#define DMA_ENABLE_ERROR_INT(base, channel)  (base->EEI |= ((uint32_t)0x1U << channel))
+#define DMA_DISABLE_ERROR_INT(base, channel) (base->EEI &= (~((uint32_t)0x1U << channel)))
+/*! @brief get/clear error status*/
+#define DMA_GET_ERROR_STATUS(base, channel)   (((uint32_t)EDMA_BASE(base)->ERR >> channel) & 0x1U)
+#define DMA_CLEAR_ERROR_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CERR = (uint8_t)channel)
+/*! @brief get/clear int status*/
+#define DMA_GET_INT_STATUS(base, channel)   ((((uint32_t)EDMA_BASE(base)->INT >> channel) & 0x1U))
+#define DMA_CLEAR_INT_STATUS(base, channel) ((uint32_t)EDMA_BASE(base)->CINT = (uint8_t)channel)
+
+#else
+
+#define DMA_ERR_DBE_FLAG                     DMA_MP_ES_DBE_MASK
+#define DMA_ERR_SBE_FLAG                     DMA_MP_ES_SBE_MASK
+#define DMA_ERR_SGE_FLAG                     DMA_MP_ES_SGE_MASK
+#define DMA_ERR_NCE_FLAG                     DMA_MP_ES_NCE_MASK
+#define DMA_ERR_DOE_FLAG                     DMA_MP_ES_DOE_MASK
+#define DMA_ERR_DAE_FLAG                     DMA_MP_ES_DAE_MASK
+#define DMA_ERR_SOE_FLAG                     DMA_MP_ES_SOE_MASK
+#define DMA_ERR_SAE_FLAG                     DMA_MP_ES_SAE_MASK
+#define DMA_ERR_ERRCHAN_FLAG                 DMA_MP_ES_ERRCHN_MASK
+#define DMA_ERR_ECX_FLAG                     DMA_MP_ES_ECX_MASK
+#define DMA_ERR_FLAG                         DMA_MP_ES_VLD_MASK
+
+/*! @brief get/clear DONE bit*/
+#define DMA_CLEAR_DONE_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_DONE_MASK)
+#define DMA_GET_DONE_STATUS(base, channel) \
+    ((EDMA_CHANNEL_BASE(base, channel)->CH_CSR & DMA_CH_CSR_DONE_MASK) >> DMA_CH_CSR_DONE_SHIFT)
+/*! @brief enable/disable error interupt*/
+#define DMA_ENABLE_ERROR_INT(base, channel)   (EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_EEI_MASK)
+#define DMA_DISABLE_ERROR_INT(base, channel)  (EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_EEI_MASK)
+/*! @brief get/clear error status*/
+#define DMA_CLEAR_ERROR_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_ES |= DMA_CH_ES_ERR_MASK)
+#define DMA_GET_ERROR_STATUS(base, channel) \
+    (((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_ES >> DMA_CH_ES_ERR_SHIFT) & 0x1U)
+/*! @brief get/clear INT status*/
+#define DMA_CLEAR_INT_STATUS(base, channel) (EDMA_CHANNEL_BASE(base, channel)->CH_INT = DMA_CH_INT_INT_MASK)
+#define DMA_GET_INT_STATUS(base, channel)   ((((uint32_t)EDMA_CHANNEL_BASE(base, channel)->CH_INT) & 0x1U))
+#endif /*FSL_EDMA_SOC_IP_EDMA*/
+
+/*! @brief enable/dsiable MAJOR/HALF INT*/
+#define DMA_ENABLE_MAJOR_INT(base, channel) \
+    (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTMAJOR_MASK)
+#define DMA_ENABLE_HALF_INT(base, channel) \
+    (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTHALF_MASK)
+#define DMA_DISABLE_MAJOR_INT(base, channel) \
+    (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK)
+#define DMA_DISABLE_HALF_INT(base, channel) \
+    (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTHALF_MASK)
+
+/*!@brief EDMA tcd align size */
+#define EDMA_TCD_ALIGN_SIZE (32U)
 
 /*!@brief edma core channel struture definition */
 typedef struct _edma_core_mp
 {
     __IO uint32_t MP_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
     __IO uint32_t MP_ES;  /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
+    union
+    {
+        struct
+        {
+            __IO uint32_t MP_INT_LOW;   /**< Channel Control and Status, array offset: 0x10008, array step: 0x10000 */
+            __I uint32_t MP_INT_HIGH;   /**< Channel Control and Status, array offset: 0x1000C, array step: 0x10000 */
+            __I uint32_t MP_HRS_LOW;    /**< Channel Control and Status, array offset: 0x10010, array step: 0x10000 */
+            __I uint32_t MP_HRS_HIGH;   /**< Channel Control and Status, array offset: 0x10014, array step: 0x10000 */
+            uint8_t RESERVED_0[8];
+            __IO uint32_t MP_STOPCH;    /**< Channel Control and Status, array offset: 0x10020, array step: 0x10000 */
+            uint8_t RESERVED_1[12];
+            __I uint32_t MP_SSR_LOW;    /**< Channel Control and Status, array offset: 0x10030, array step: 0x10000 */
+            __I uint32_t MP_SSR_HIGH;   /**< Channel Control and Status, array offset: 0x10034, array step: 0x10000 */
+            uint8_t RESERVED_2[200];
+            __IO uint32_t CH_GRPRI[64]; /**< Channel Control and Status, array offset: 0x10100, array step: 0x10000 */
+            __IO uint32_t CH_MUX[64];   /**< Channel Control and Status, array offset: 0x10200, array step: 0x10000 */
+            uint8_t RESERVED_3[256];
+            __IO uint32_t CH_PROT[64];  /**< Channel Control and Status, array offset: 0x10400, array step: 0x10000 */
+        } EDMA5_REG;
+    } MP_REGS;
 } edma_core_mp_t;
 
 /*!@brief edma core channel struture definition */
 typedef struct _edma_core_channel
 {
-    __IO uint32_t CH_CSR;   /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
-    __IO uint32_t CH_ES;    /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
-    __IO uint32_t CH_INT;   /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */
-    __IO uint32_t CH_SBR;   /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */
-    __IO uint32_t CH_PRI;   /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */
-    __IO uint32_t CH_MUX;   /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */
-    __IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */
+    __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
+    __IO uint32_t CH_ES;  /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
+    __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */
+    __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */
+    __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */
+    union
+    {
+        struct
+        {
+            __IO uint8_t RESERVED_1[4];
+            __IO uint32_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */
+        } EDMA5_REG;
+        struct
+        {
+            __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */
+            __IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */
+        } EDMA4_REG;
+    } CH_REGS;
 } edma_core_channel_t;
 
-/*!@brief edma core TCD struture definition */
-typedef struct _edma_core_tcd
+/*! @brief eDMA tcd flag type */
+typedef enum _edma_tcd_type
+{
+    kEDMA_EDMA4Flag = 0x0U, /*!< Data access for eDMA4 transfers. */
+    kEDMA_EDMA5Flag = 0x1U, /*!< Instruction access for eDMA4 transfers. */
+} edma_tcd_type_t;
+
+/*!@brief edma5 core TCD struture definition */
+typedef struct _edma5_core_tcd
+{
+    __IO uint32_t SADDR;          /*!< SADDR register, used to save source address */
+    __IO uint32_t SADDR_HIGH;     /*!< SADDR HIGH register, used to save source address */
+    __IO uint16_t SOFF;           /*!< SOFF register, save offset bytes every transfer */
+    __IO uint16_t ATTR;           /*!< ATTR register, source/destination transfer size and modulo */
+    __IO uint32_t NBYTES;         /*!< Nbytes register, minor loop length in bytes */
+    __IO uint32_t SLAST;          /*!< SLAST register */
+    __IO uint32_t SLAST_SDA_HIGH; /*!< SLAST SDA HIGH register */
+    __IO uint32_t DADDR;          /*!< DADDR register, used for destination address */
+    __IO uint32_t DADDR_HIGH;     /*!< DADDR HIGH register, used for destination address */
+    __IO uint32_t DLAST_SGA;      /*!< DLASTSGA register, next tcd address used in scatter-gather mode */
+    __IO uint32_t DLAST_SGA_HIGH; /*!< DLASTSGA HIGH register, next tcd address used in scatter-gather mode */
+    __IO uint16_t DOFF;           /*!< DOFF register, used for destination offset */
+    __IO uint16_t CITER;          /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/
+    __IO uint16_t CSR;            /*!< CSR register, for TCD control status */
+    __IO uint16_t BITER;          /*!< BITER register, begin minor loop count. */
+    uint8_t RESERVED[16];         /*!< Aligned 64 bytes */
+} edma5_core_tcd_t;
+
+/*!@brief edma4 core TCD struture definition */
+typedef struct _edma4_core_tcd
 {
     __IO uint32_t SADDR;     /*!< SADDR register, used to save source address */
     __IO uint16_t SOFF;      /*!< SOFF register, save offset bytes every transfer */
@@ -186,6 +232,18 @@ typedef struct _edma_core_tcd
     __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */
     __IO uint16_t CSR;       /*!< CSR register, for TCD control status */
     __IO uint16_t BITER;     /*!< BITER register, begin minor loop count. */
+} edma4_core_tcd_t;
+
+/*!@brief edma core TCD struture definition */
+typedef struct _edma_core_tcd
+{
+    union
+    {
+        edma4_core_tcd_t edma4_tcd;
+#if defined FSL_EDMA_SOC_IP_DMA5 && FSL_EDMA_SOC_IP_DMA5
+        edma5_core_tcd_t edma5_tcd;
+#endif /* FSL_EDMA_SOC_IP_DMA5 */
+    } TCD_REGS;
 } edma_core_tcd_t;
 
 /*!@brief EDMA typedef */
@@ -195,12 +253,91 @@ typedef void EDMA_Type;
 
 /*!@brief EDMA base address convert macro */
 #define EDMA_BASE(base)
-#define EDMA_CHANNEL_BASE(base, channel) \
-    ((edma_core_channel_t *)((uint32_t)base + EDMA_CHANNEL_OFFSET + channel * EDMA_CHANNEL_ARRAY_STEP(base)))
-#define EDMA_TCD_BASE(base, channel) \
-    ((edma_core_tcd_t *)((uint32_t)base + EDMA_CHANNEL_OFFSET + channel * EDMA_CHANNEL_ARRAY_STEP(base) + 0x20U))
-#define EDMA_MP_BASE(base) ((edma_core_mp_t *)((uint32_t)base))
+#define EDMA_CHANNEL_BASE(base, channel)                                          \
+    ((edma_core_channel_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \
+                             (channel)*EDMA_CHANNEL_ARRAY_STEP(base)))
+#define EDMA_TCD_BASE(base, channel)                                          \
+    ((edma_core_tcd_t *)((uint32_t)(uint32_t *)(base) + EDMA_CHANNEL_OFFSET + \
+                         (channel)*EDMA_CHANNEL_ARRAY_STEP(base) + 0x20U))
+#define EDMA_MP_BASE(base) ((edma_core_mp_t *)((uint32_t)(uint32_t *)(base)))
+
+/*!@brief EDMA TCD type macro */
+#if defined FSL_FEATURE_EDMA_TCD_TYPEn
+#define EDMA_TCD_TYPE(x) FSL_FEATURE_EDMA_TCD_TYPEn(x)
+#else
+#define EDMA_TCD_TYPE(x) (0)
+#endif
+
+#if defined FSL_EDMA_SOC_IP_DMA5 && FSL_EDMA_SOC_IP_DMA5
+/*!@brief EDMA TCD address convert macro */
+#define EDMA_TCD_SADDR(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SADDR)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SADDR))))
+
+#define EDMA_TCD_SOFF(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SOFF)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SOFF))))
+
+#define EDMA_TCD_ATTR(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->ATTR)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->ATTR))))
+
+#define EDMA_TCD_NBYTES(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->NBYTES)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->NBYTES))))
+
+#define EDMA_TCD_SLAST(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SLAST)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SLAST))))
+
+#define EDMA_TCD_DADDR(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DADDR)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DADDR))))
+
+#define EDMA_TCD_DOFF(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DOFF)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DOFF))))
+
+#define EDMA_TCD_CITER(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CITER)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->CITER))))
+
+#define EDMA_TCD_DLAST_SGA(tcd, flag)                                         \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ?                         \
+           (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DLAST_SGA)) : \
+           (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DLAST_SGA))))
+
+#define EDMA_TCD_CSR(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->CSR))))
+
+#define EDMA_TCD_BITER(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->BITER)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->BITER))))
+#else
+/*!@brief EDMA TCD address convert macro */
+#define EDMA_TCD_SADDR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SADDR)
+
+#define EDMA_TCD_SOFF(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SOFF)
+
+#define EDMA_TCD_ATTR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->ATTR)
+
+#define EDMA_TCD_NBYTES(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->NBYTES)
+
+#define EDMA_TCD_SLAST(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SLAST)
+
+#define EDMA_TCD_DADDR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DADDR)
+
+#define EDMA_TCD_DOFF(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DOFF)
+
+#define EDMA_TCD_CITER(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CITER)
+
+#define EDMA_TCD_DLAST_SGA(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DLAST_SGA)
+
+#define EDMA_TCD_CSR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR)
 
+#define EDMA_TCD_BITER(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->BITER)
+#endif /* FSL_EDMA_SOC_IP_DMA5 */
 /*******************************************************************************
  * API
  ******************************************************************************/
@@ -217,4 +354,4 @@ extern "C" {
  * @}
  */
 
-#endif /* _FSL_EDMA_CORE_H_ */
+#endif /* FSL_EDMA_CORE_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_edma_soc.h

@@ -45,151 +45,6 @@
         }                                                                                                           \
     }
 
-/*!@brief dma request source */
-typedef enum _dma_request_source
-{
-    kDmaRequestDisabled                        = 0U,           /**< DSisabled*/
-    kDmaRequestMuxFlexSpi0Rx                   = 1 | 0x100U,   /**< FlexSPI0 Receive event */
-    kDmaRequestMuxFlexSpi0Tx                   = 2 | 0x100U,   /**< FlexSPI0 Transmit event */
-    kDmaRequestMuxPinInt0                      = 3 | 0x100U,   /**< PinInt0 */
-    kDmaRequestMuxPinInt1                      = 4 | 0x100U,   /**< PinInt1 */
-    kDmaRequestMuxPinInt2                      = 5 | 0x100U,   /**< PinInt2 */
-    kDmaRequestMuxPinInt3                      = 6 | 0x100U,   /**< PinInt3 */
-    kDmaRequestMuxCtimer0M0                    = 7 | 0x100U,   /**< Ctimer0_M0 */
-    kDmaRequestMuxCtimer0M1                    = 8 | 0x100U,   /**< Ctimer0_M1 */
-    kDmaRequestMuxCtimer1M0                    = 9 | 0x100U,   /**< Ctimer1_M0 */
-    kDmaRequestMuxCtimer1M1                    = 10 | 0x100U,  /**< Ctimer1_M1 */
-    kDmaRequestMuxCtimer2M0                    = 11 | 0x100U,  /**< Ctimer2_M0 */
-    kDmaRequestMuxCtimer2M1                    = 12 | 0x100U,  /**< Ctimer2_M1 */
-    kDmaRequestMuxCtimer3M0                    = 13 | 0x100U,  /**< Ctimer3_M0 */
-    kDmaRequestMuxCtimer3M1                    = 14 | 0x100U,  /**< Ctimer3_M1 */
-    kDmaRequestMuxCtimer4M0                    = 15 | 0x100U,  /**< Ctimer4_M0 */
-    kDmaRequestMuxCtimer5M1                    = 16 | 0x100U,  /**< Ctimer4_M1 */
-    kDmaRequestMuxWuu0                         = 17 | 0x100U,  /**< Wake up event */
-    kDmaRequestMuxMicfil0FifoRequest           = 18 | 0x100U,  /**< MICFIL0 FIFO_request */
-    kDmaRequestMuxSct0Dma0                     = 19 | 0x100U,  /**< SCT0 DMA0 */
-    kDmaRequestMuxSct0Dma1                     = 20 | 0x100U,  /**< SCT0 DMA1 */
-    kDmaRequestMuxAdc0FifoARequest             = 21 | 0x100U,  /**< ADC0 FIFO A request */
-    kDmaRequestMuxAdc0FifoBRequest             = 22 | 0x100U,  /**< ADC0 FIFO B request */
-    kDmaRequestMuxAdc1FifoARequest             = 23 | 0x100U,  /**< ADC1 FIFO A request */
-    kDmaRequestMuxAdc1FifoBRequest             = 24 | 0x100U,  /**< ADC1 FIFO B request */
-    kDmaRequestMuxDac0FifoRequest              = 25 | 0x100U,  /**< DAC0 FIFO_request */
-    kDmaRequestMuxDac1FifoRequest              = 26 | 0x100U,  /**< DAC1 FIFO_request */
-    kDmaRequestMuxHpDac0FifoRequest            = 27 | 0x100U,  /**< HP DAC0 FIFO_request */
-    kDmaRequestMuxHsCmp0DmaRequest             = 28 | 0x100U,  /**< HS CMP0 DMA_request */
-    kDmaRequestMuxHsCmp1DmaRequest             = 29 | 0x100U,  /**< HS CMP0 DMA_request */
-    kDmaRequestMuxHsCmp2DmaRequest             = 30 | 0x100U,  /**< HS CMP0 DMA_request */
-    kDmaRequestMuxEvtg0Out0A                   = 31 | 0x100U,  /**< EVTG0 OUT0A */
-    kDmaRequestMuxEvtg0Out0B                   = 32 | 0x100U,  /**< EVTG0 OUT0B */
-    kDmaRequestMuxEvtg0Out1A                   = 33 | 0x100U,  /**< EVTG0 OUT1A */
-    kDmaRequestMuxEvtg0Out1B                   = 34 | 0x100U,  /**< EVTG0 OUT1B */
-    kDmaRequestMuxEvtg0Out2A                   = 35 | 0x100U,  /**< EVTG0 OUT2A */
-    kDmaRequestMuxEvtg0Out2B                   = 36 | 0x100U,  /**< EVTG0 OUT2B */
-    kDmaRequestMuxEvtg0Out3A                   = 37 | 0x100U,  /**< EVTG0 OUT3A */
-    kDmaRequestMuxEvtg0Out3B                   = 38 | 0x100U,  /**< EVTG0 OUT3B */
-    kDmaRequestMuxFlexPwm0ReqCapt0             = 39 | 0x100U,  /**< FlexPWM0 Req_capt0 */
-    kDmaRequestMuxFlexPwm0ReqCapt1             = 40 | 0x100U,  /**< FlexPWM0 Req_capt1 */
-    kDmaRequestMuxFlexPwm0ReqCapt2             = 41 | 0x100U,  /**< FlexPWM0 Req_capt2 */
-    kDmaRequestMuxFlexPwm0ReqCapt3             = 42 | 0x100U,  /**< FlexPWM0 Req_capt3 */
-    kDmaRequestMuxFlexPwm0ReqVal0              = 43 | 0x100U,  /**< FlexPWM0 Req_val0 */
-    kDmaRequestMuxFlexPwm0ReqVal1              = 44 | 0x100U,  /**< FlexPWM0 Req_val1 */
-    kDmaRequestMuxFlexPwm0ReqVal2              = 45 | 0x100U,  /**< FlexPWM0 Req_val2 */
-    kDmaRequestMuxFlexPwm0ReqVal3              = 46 | 0x100U,  /**< FlexPWM0 Req_val3 */
-    kDmaRequestMuxFlexPwm1ReqCapt0             = 47 | 0x100U,  /**< FlexPWM1 Req_capt0 */
-    kDmaRequestMuxFlexPwm1ReqCapt1             = 48 | 0x100U,  /**< FlexPWM1 Req_capt1 */
-    kDmaRequestMuxFlexPwm1ReqCapt2             = 49 | 0x100U,  /**< FlexPWM1 Req_capt2 */
-    kDmaRequestMuxFlexPwm1ReqCapt3             = 50 | 0x100U,  /**< FlexPWM1 Req_capt3 */
-    kDmaRequestMuxFlexPwm1ReqVal0              = 51 | 0x100U,  /**< FlexPWM1 Req_val0 */
-    kDmaRequestMuxFlexPwm1ReqVal1              = 52 | 0x100U,  /**< FlexPWM1 Req_val1 */
-    kDmaRequestMuxFlexPwm1ReqVal2              = 53 | 0x100U,  /**< FlexPWM1 Req_val2 */
-    kDmaRequestMuxFlexPwm1ReqVal3              = 54 | 0x100U,  /**< FlexPWM1 Req_val3 */
-    kDmaRequestMuxItrc0TmprOut0                = 55 | 0x100U,  /**< ITRC0 TMPR_OUT0 */
-    kDmaRequestMuxItrc0TmprOut1                = 56 | 0x100U,  /**< ITRC0 TMPR_OUT1 */
-    kDmaRequestMuxLptmr0                       = 57 | 0x100U,  /**< LPTMR0 Counter match event */
-    kDmaRequestMuxLptmr1                       = 58 | 0x100U,  /**< LPTMR1 Counter match event */
-    kDmaRequestMuxFlexCan0DmaRequest           = 59 | 0x100U,  /**< FlexCAN0 DMA request */
-    kDmaRequestMuxFlexCan1DmaRequest           = 60 | 0x100U,  /**< FlexCAN1 DMA request */
-    kDmaRequestMuxFlexIO0ShiftRegister0Request = 61 | 0x100U,  /**< FlexIO0 Shift Register 0 request */
-    kDmaRequestMuxFlexIO0ShiftRegister1Request = 62 | 0x100U,  /**< FlexIO0 Shift Register 1 request */
-    kDmaRequestMuxFlexIO0ShiftRegister2Request = 63 | 0x100U,  /**< FlexIO0 Shift Register 2 request */
-    kDmaRequestMuxFlexIO0ShiftRegister3Request = 64 | 0x100U,  /**< FlexIO0 Shift Register 3 request */
-    kDmaRequestMuxFlexIO0ShiftRegister4Request = 65 | 0x100U,  /**< FlexIO0 Shift Register 4 request */
-    kDmaRequestMuxFlexIO0ShiftRegister5Request = 66 | 0x100U,  /**< FlexIO0 Shift Register 5 request */
-    kDmaRequestMuxFlexIO0ShiftRegister6Request = 67 | 0x100U,  /**< FlexIO0 Shift Register 6 request */
-    kDmaRequestMuxFlexIO0ShiftRegister7Request = 68 | 0x100U,  /**< FlexIO0 Shift Register 7 request */
-    kDmaRequestMuxLpFlexcomm0Rx                = 69 | 0x100U,  /**< LP_FLEXCOMM0 Receive request */
-    kDmaRequestMuxLpFlexcomm0Tx                = 70 | 0x100U,  /**< LP_FLEXCOMM0 Transmit request */
-    kDmaRequestMuxLpFlexcomm1Rx                = 71 | 0x100U,  /**< LP_FLEXCOMM1 Receive request */
-    kDmaRequestMuxLpFlexcomm1Tx                = 72 | 0x100U,  /**< LP_FLEXCOMM1 Transmit request */
-    kDmaRequestMuxLpFlexcomm2Rx                = 73 | 0x100U,  /**< LP_FLEXCOMM2 Receive request */
-    kDmaRequestMuxLpFlexcomm2Tx                = 74 | 0x100U,  /**< LP_FLEXCOMM2 Transmit request */
-    kDmaRequestMuxLpFlexcomm3Rx                = 75 | 0x100U,  /**< LP_FLEXCOMM3 Receive request */
-    kDmaRequestMuxLpFlexcomm3Tx                = 76 | 0x100U,  /**< LP_FLEXCOMM3 Transmit request */
-    kDmaRequestMuxLpFlexcomm4Rx                = 77 | 0x100U,  /**< LP_FLEXCOMM4 Receive request */
-    kDmaRequestMuxLpFlexcomm4Tx                = 78 | 0x100U,  /**< LP_FLEXCOMM4 Transmit request */
-    kDmaRequestMuxLpFlexcomm5Rx                = 79 | 0x100U,  /**< LP_FLEXCOMM5 Receive request */
-    kDmaRequestMuxLpFlexcomm5Tx                = 80 | 0x100U,  /**< LP_FLEXCOMM5 Transmit request */
-    kDmaRequestMuxLpFlexcomm6Rx                = 81 | 0x100U,  /**< LP_FLEXCOMM6 Receive request */
-    kDmaRequestMuxLpFlexcomm6Tx                = 82 | 0x100U,  /**< LP_FLEXCOMM6 Transmit request */
-    kDmaRequestMuxLpFlexcomm7Rx                = 83 | 0x100U,  /**< LP_FLEXCOMM7 Receive request */
-    kDmaRequestMuxLpFlexcomm7Tx                = 84 | 0x100U,  /**< LP_FLEXCOMM7 Transmit request */
-    kDmaRequestMuxLpFlexcomm8Rx                = 85 | 0x100U,  /**< LP_FLEXCOMM8 Receive request */
-    kDmaRequestMuxLpFlexcomm8Tx                = 86 | 0x100U,  /**< LP_FLEXCOMM8 Transmit request */
-    kDmaRequestMuxLpFlexcomm9Rx                = 87 | 0x100U,  /**< LP_FLEXCOMM9 Receive request */
-    kDmaRequestMuxLpFlexcomm9Tx                = 88 | 0x100U,  /**< LP_FLEXCOMM9 Transmit request */
-    kDmaRequestMuxESpi0Ch0                     = 89 | 0x100U,  /**< eSPI0 channel 0 */
-    kDmaRequestMuxESpi0Ch1                     = 90 | 0x100U,  /**< eSPI0 channel 1 */
-    kDmaRequestMuxEmvSim0Rx                    = 91 | 0x100U,  /**< EMVSIM0 Receive request */
-    kDmaRequestMuxEmvSim0Tx                    = 92 | 0x100U,  /**< EMVSIM0 Transmit request */
-    kDmaRequestMuxEmvSim1Rx                    = 93 | 0x100U,  /**< EMVSIM1 Receive request */
-    kDmaRequestMuxEmvSim1Tx                    = 94 | 0x100U,  /**< EMVSIM1 Transmit request */
-    kDmaRequestMuxI3c0Rx                       = 95 | 0x100U,  /**< I3C0 Receive request */
-    kDmaRequestMuxI3c0Tx                       = 96 | 0x100U,  /**< I3C0 Transmit request */
-    kDmaRequestMuxI3c1Rx                       = 97 | 0x100U,  /**< I3C0 Receive request */
-    kDmaRequestMuxI3c1Tx                       = 98 | 0x100U,  /**< I3C0 Transmit request */
-    kDmaRequestMuxSai0Rx                       = 99 | 0x100U,  /**< SAI0 Receive request */
-    kDmaRequestMuxSai0Tx                       = 100 | 0x100U, /**< SAI0 Receive request */
-    kDmaRequestMuxSai1Rx                       = 101 | 0x100U, /**< SAI1 Receive request */
-    kDmaRequestMuxSai1Tx                       = 102 | 0x100U, /**< SAI1 Receive request */
-    kDmaRequestMuxSinc0IpdReqSincAlt0          = 103 | 0x100U, /**< SINC0 ipd_req_sinc[0] or ipd_req_alt [0] */
-    kDmaRequestMuxSinc0IpdReqSincAlt1          = 104 | 0x100U, /**< SINC0 ipd_req_sinc[1] or ipd_req_alt [1] */
-    kDmaRequestMuxSinc0IpdReqSincAlt2          = 105 | 0x100U, /**< SINC0 ipd_req_sinc[2] or ipd_req_alt [2] */
-    kDmaRequestMuxSinc0IpdReqSincAlt3          = 106 | 0x100U, /**< SINC0 ipd_req_sinc[3] or ipd_req_alt [3] */
-    kDmaRequestMuxSinc0IpdReqSincAlt4          = 107 | 0x100U, /**< SINC0 ipd_req_sinc[4] or ipd_req_alt [4] */
-    kDmaRequestMuxGpio0PinEventRequest0        = 108 | 0x100U, /**< GPIO0 Pin event request 0 */
-    kDmaRequestMuxGpio0PinEventRequest1        = 109 | 0x100U, /**< GPIO0 Pin event request 1 */
-    kDmaRequestMuxGpio1PinEventRequest0        = 110 | 0x100U, /**< GPIO1 Pin event request 0 */
-    kDmaRequestMuxGpio1PinEventRequest1        = 111 | 0x100U, /**< GPIO1 Pin event request 1 */
-    kDmaRequestMuxGpio2PinEventRequest0        = 112 | 0x100U, /**< GPIO2 Pin event request 0 */
-    kDmaRequestMuxGpio2PinEventRequest1        = 113 | 0x100U, /**< GPIO2 Pin event request 1 */
-    kDmaRequestMuxGpio3PinEventRequest0        = 114 | 0x100U, /**< GPIO3 Pin event request 0 */
-    kDmaRequestMuxGpio3PinEventRequest1        = 115 | 0x100U, /**< GPIO3 Pin event request 1 */
-    kDmaRequestMuxGpio4PinEventRequest0        = 116 | 0x100U, /**< GPIO4 Pin event request 0 */
-    kDmaRequestMuxGpio4PinEventRequest1        = 117 | 0x100U, /**< GPIO4 Pin event request 1 */
-    kDmaRequestMuxGpio5PinEventRequest0        = 118 | 0x100U, /**< GPIO5 Pin event request 0 */
-    kDmaRequestMuxGpio5PinEventRequest1        = 119 | 0x100U, /**< GPIO5 Pin event request 1 */
-    kDmaRequestMuxTsi0EndOfScan                = 120 | 0x100U, /**< TSI0 End of Scan */
-    kDmaRequestMuxTsi0OutOfRange               = 121 | 0x100U, /**< TSI0 Out of Range */
-} dma_request_source_t;
-
-/*!< Verify dma base and request source */
-#define EDMA_CHANNEL_HAS_REQUEST_SOURCE(base, source) ((source)&0x100U)
-
-#define FSL_FEATURE_EDMA_MODULE_CHANNEL(base)                (16U)
-#define FSL_FEATURE_EDMA_MODULE_MAX_CHANNEL                  (16)
-#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION    (1)
-#define FSL_FEATURE_EDMA_HAS_CONTINUOUS_LINK_MODE            (0)
-#define FSL_FEATURE_EDMA_MODULE_COUNT                        (2)
-#define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG                  (1)
-#define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE               (0)
-#define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE             (0)
-#define FSL_FEATURE_EDMA_HAS_CHANNEL_MEMRORY_ATTRIBUTE       (0)
-#define FSL_FEATURE_EDMA_HAS_CHANNEL_SIGN_EXTENSION          (0)
-#define FSL_FEATURE_EDMA_MODULE_SUPPORT_MATTR(base)          (0U)
-#define FSL_FEATURE_EDMA_MODULE_SUPPORT_SIGN_EXTENSION(base) (0U)
-#define FSL_FEATURE_EDMA_MODULE_SUPPORT_SWAP(base)           (0U)
-#define FSL_FEATURE_EDMA_MODULE_SUPPORT_INSTR(base)          (0U)
-
 /*!@brief EDMA base address convert macro */
 #define EDMA_CHANNEL_OFFSET           0x1000U
 #define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U)

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.c

@@ -82,44 +82,52 @@ void EIM_Deinit(EIM_Type *base)
 
 void EIM_InjectCheckBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask)
 {
-    switch (channel)
+    switch ((uint8_t)channel)
     {
-        case kEIM_MemoryChannelRAMX:
+        case 0U:
             base->EICHD0_WORD0 = EIM_EICHD0_WORD0_CHKBIT_MASK(mask);
             break;
-
-        case kEIM_MemoryChannelRAMA:
+#ifdef EIM_EICHEN_EICH1EN_MASK
+        case 1U:
             base->EICHD1_WORD0 = EIM_EICHD1_WORD0_CHKBIT_MASK(mask);
             break;
+#endif
 
-        case kEIM_MemoryChannelRAMB:
+#ifdef EIM_EICHEN_EICH2EN_MASK
+        case 2U:
             base->EICHD2_WORD0 = EIM_EICHD2_WORD0_CHKBIT_MASK(mask);
             break;
-
-        case kEIM_MemoryChannelRAMC:
+#endif
+#ifdef EIM_EICHEN_EICH3EN_MASK
+        case 3U:
             base->EICHD3_WORD0 = EIM_EICHD3_WORD0_CHKBIT_MASK(mask);
             break;
-
-        case kEIM_MemoryChannelRAMD:
+#endif
+#ifdef EIM_EICHEN_EICH4EN_MASK
+        case 4U:
             base->EICHD4_WORD0 = EIM_EICHD4_WORD0_CHKBIT_MASK(mask);
             break;
-
-        case kEIM_MemoryChannelRAME:
+#endif
+#ifdef EIM_EICHEN_EICH5EN_MASK
+        case 5U:
             base->EICHD5_WORD0 = EIM_EICHD5_WORD0_CHKBIT_MASK(mask);
             break;
-
-        case kEIM_MemoryChannelRAMF:
+#endif
+#ifdef EIM_EICHEN_EICH6EN_MASK
+        case 6U:
             base->EICHD6_WORD0 = EIM_EICHD6_WORD0_CHKBIT_MASK(mask);
             break;
-
-        case kEIM_MemoryChannelLPCACRAM:
+#endif
+#ifdef EIM_EICHEN_EICH7EN_MASK
+        case 7U:
             base->EICHD7_WORD0 = EIM_EICHD7_WORD0_CHKBIT_MASK(mask);
             break;
-
-        case kEIM_MemoryChannelPKCRAM:
+#endif
+#ifdef EIM_EICHEN_EICH8EN_MASK
+        case 8U:
             base->EICHD8_WORD0 = EIM_EICHD8_WORD0_CHKBIT_MASK(mask);
             break;
-
+#endif
         default:
             assert(NULL);
             break;
@@ -130,53 +138,60 @@ uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel)
 {
     uint8_t mask = 0x00U;
 
-    switch (channel)
+    switch ((uint8_t)channel)
     {
-        case kEIM_MemoryChannelRAMX:
+        case 0U:
             mask = (uint8_t)((base->EICHD0_WORD0 & EIM_EICHD0_WORD0_CHKBIT_MASK_MASK) >>
                              EIM_EICHD0_WORD0_CHKBIT_MASK_SHIFT);
             break;
-
-        case kEIM_MemoryChannelRAMA:
+#ifdef EIM_EICHEN_EICH1EN_MASK
+        case 1U:
             mask = (uint8_t)((base->EICHD1_WORD0 & EIM_EICHD1_WORD0_CHKBIT_MASK_MASK) >>
                              EIM_EICHD1_WORD0_CHKBIT_MASK_SHIFT);
             break;
-
-        case kEIM_MemoryChannelRAMB:
+#endif
+#ifdef EIM_EICHEN_EICH2EN_MASK
+        case 2U:
             mask = (uint8_t)((base->EICHD2_WORD0 & EIM_EICHD2_WORD0_CHKBIT_MASK_MASK) >>
                              EIM_EICHD2_WORD0_CHKBIT_MASK_SHIFT);
             break;
-
-        case kEIM_MemoryChannelRAMC:
+#endif
+#ifdef EIM_EICHEN_EICH3EN_MASK
+        case 3U:
             mask = (uint8_t)((base->EICHD3_WORD0 & EIM_EICHD3_WORD0_CHKBIT_MASK_MASK) >>
                              EIM_EICHD3_WORD0_CHKBIT_MASK_SHIFT);
             break;
-
-        case kEIM_MemoryChannelRAMD:
+#endif
+#ifdef EIM_EICHEN_EICH4EN_MASK
+        case 4U:
             mask = (uint8_t)((base->EICHD4_WORD0 & EIM_EICHD4_WORD0_CHKBIT_MASK_MASK) >>
                              EIM_EICHD4_WORD0_CHKBIT_MASK_SHIFT);
             break;
-
-        case kEIM_MemoryChannelRAME:
+#endif
+#ifdef EIM_EICHEN_EICH5EN_MASK
+        case 5U:
             mask = (uint8_t)((base->EICHD5_WORD0 & EIM_EICHD5_WORD0_CHKBIT_MASK_MASK) >>
                              EIM_EICHD5_WORD0_CHKBIT_MASK_SHIFT);
             break;
-
-        case kEIM_MemoryChannelRAMF:
+#endif
+#ifdef EIM_EICHEN_EICH6EN_MASK
+        case 6U:
             mask = (uint8_t)((base->EICHD6_WORD0 & EIM_EICHD6_WORD0_CHKBIT_MASK_MASK) >>
                              EIM_EICHD6_WORD0_CHKBIT_MASK_SHIFT);
             break;
-
-        case kEIM_MemoryChannelLPCACRAM:
+#endif
+#ifdef EIM_EICHEN_EICH7EN_MASK
+        case 7U:
             mask = (uint8_t)((base->EICHD7_WORD0 & EIM_EICHD7_WORD0_CHKBIT_MASK_MASK) >>
                              EIM_EICHD7_WORD0_CHKBIT_MASK_SHIFT);
             break;
-
-        case kEIM_MemoryChannelPKCRAM:
+#endif
+#ifdef EIM_EICHEN_EICH8EN_MASK
+        case 8U:
             mask = (uint8_t)((base->EICHD8_WORD0 & EIM_EICHD8_WORD0_CHKBIT_MASK_MASK) >>
                              EIM_EICHD8_WORD0_CHKBIT_MASK_SHIFT);
             break;
-
+#endif
         default:
             assert(NULL);
             break;
@@ -187,44 +202,51 @@ uint8_t EIM_GetCheckBitMask(EIM_Type *base, eim_memory_channel_t channel)
 
 void EIM_InjectDataBitError(EIM_Type *base, eim_memory_channel_t channel, uint8_t mask)
 {
-    switch (channel)
+    switch ((uint8_t)channel)
     {
-        case kEIM_MemoryChannelRAMX:
+        case 0U:
             base->EICHD0_WORD1 = mask;
             break;
-
-        case kEIM_MemoryChannelRAMA:
+#ifdef EIM_EICHEN_EICH1EN_MASK
+        case 1U:
             base->EICHD1_WORD1 = mask;
             break;
-
-        case kEIM_MemoryChannelRAMB:
+#endif
+#ifdef EIM_EICHEN_EICH2EN_MASK
+        case 2U:
             base->EICHD2_WORD1 = mask;
             break;
-
+#endif
+#ifdef EIM_EICHEN_EICH3EN_MASK
         case kEIM_MemoryChannelRAMC:
             base->EICHD3_WORD1 = mask;
             break;
-
+#endif
+#ifdef EIM_EICHEN_EICH4EN_MASK
         case kEIM_MemoryChannelRAMD:
             base->EICHD4_WORD1 = mask;
             break;
-
+#endif
+#ifdef EIM_EICHEN_EICH5EN_MASK
         case kEIM_MemoryChannelRAME:
             base->EICHD5_WORD1 = mask;
             break;
-
+#endif
+#ifdef EIM_EICHEN_EICH6EN_MASK
         case kEIM_MemoryChannelRAMF:
             base->EICHD6_WORD1 = mask;
             break;
-
+#endif
+#ifdef EIM_EICHEN_EICH7EN_MASK
         case kEIM_MemoryChannelLPCACRAM:
             base->EICHD7_WORD1 = mask;
             break;
-
+#endif
+#ifdef EIM_EICHEN_EICH8EN_MASK
         case kEIM_MemoryChannelPKCRAM:
             base->EICHD8_WORD1 = mask;
             break;
-
+#endif
         default:
             assert(NULL);
             break;
@@ -235,44 +257,52 @@ uint32_t EIM_GetDataBitMask(EIM_Type *base, eim_memory_channel_t channel)
 {
     uint32_t mask = 0x00U;
 
-    switch (channel)
+    switch ((uint8_t)channel)
     {
-        case kEIM_MemoryChannelRAMX:
+        case 0U:
             mask = (base->EICHD0_WORD0 & EIM_EICHD0_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD0_WORD1_B0_3DATA_MASK_SHIFT;
             break;
 
-        case kEIM_MemoryChannelRAMA:
+#ifdef EIM_EICHEN_EICH1EN_MASK
+        case 1U:
             mask = (base->EICHD1_WORD0 & EIM_EICHD1_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD1_WORD1_B0_3DATA_MASK_SHIFT;
             break;
-
-        case kEIM_MemoryChannelRAMB:
+#endif
+#ifdef EIM_EICHEN_EICH2EN_MASK
+        case 2U:
             mask = (base->EICHD2_WORD0 & EIM_EICHD2_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD2_WORD1_B0_3DATA_MASK_SHIFT;
             break;
-
-        case kEIM_MemoryChannelRAMC:
+#endif
+#ifdef EIM_EICHEN_EICH3EN_MASK
+        case 3U:
             mask = (base->EICHD3_WORD0 & EIM_EICHD3_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD3_WORD1_B0_3DATA_MASK_SHIFT;
             break;
-
-        case kEIM_MemoryChannelRAMD:
+#endif
+#ifdef EIM_EICHEN_EICH4EN_MASK
+        case 4U:
             mask = (base->EICHD4_WORD0 & EIM_EICHD4_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD4_WORD1_B0_3DATA_MASK_SHIFT;
             break;
-
-        case kEIM_MemoryChannelRAME:
+#endif
+#ifdef EIM_EICHEN_EICH5EN_MASK
+        case 5U:
             mask = (base->EICHD5_WORD0 & EIM_EICHD5_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD5_WORD1_B0_3DATA_MASK_SHIFT;
             break;
-
-        case kEIM_MemoryChannelRAMF:
+#endif
+#ifdef EIM_EICHEN_EICH6EN_MASK
+        case 6U:
             mask = (base->EICHD6_WORD0 & EIM_EICHD6_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD6_WORD1_B0_3DATA_MASK_SHIFT;
             break;
-
-        case kEIM_MemoryChannelLPCACRAM:
+#endif
+#ifdef EIM_EICHEN_EICH7EN_MASK
+        case 7U:
             mask = (base->EICHD7_WORD0 & EIM_EICHD7_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD7_WORD1_B0_3DATA_MASK_SHIFT;
             break;
-
-        case kEIM_MemoryChannelPKCRAM:
+#endif
+#ifdef EIM_EICHEN_EICH8EN_MASK
+        case 8U:
             mask = (base->EICHD8_WORD1 & EIM_EICHD8_WORD1_B0_3DATA_MASK_MASK) >> EIM_EICHD8_WORD1_B0_3DATA_MASK_SHIFT;
             break;
-
+#endif
         default:
             assert(NULL);
             break;

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_eim.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_EIM_H_
-#define _FSL_EIM_H_
+#ifndef FSL_EIM_H_
+#define FSL_EIM_H_
 
 #include "fsl_common.h"
 
@@ -21,10 +21,10 @@
  *****************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief Driver version. */
-#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
-/*@}*/
+#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
+/*! @} */
 
 /*******************************************************************************
  * APIs
@@ -47,7 +47,7 @@ void EIM_Init(EIM_Type *base);
  */
 void EIM_Deinit(EIM_Type *base);
 
-/* @} */
+/*! @} */
 
 /*!
  * @name functional

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enc.c

@@ -1,625 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include "fsl_enc.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/* Component ID definition, used by tools. */
-#ifndef FSL_COMPONENT_ID
-#define FSL_COMPONENT_ID "platform.drivers.enc"
-#endif
-
-#define ENC_CTRL_W1C_FLAGS (ENC_CTRL_HIRQ_MASK | ENC_CTRL_XIRQ_MASK | ENC_CTRL_DIRQ_MASK | ENC_CTRL_CMPIRQ_MASK)
-#if (defined(FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT)
-#define ENC_CTRL2_W1C_FLAGS (ENC_CTRL2_ROIRQ_MASK | ENC_CTRL2_RUIRQ_MASK)
-#else
-#define ENC_CTRL2_W1C_FLAGS (ENC_CTRL2_SABIRQ_MASK | ENC_CTRL2_ROIRQ_MASK | ENC_CTRL2_RUIRQ_MASK)
-#endif
-
-/*******************************************************************************
- * Prototypes
- ******************************************************************************/
-/*!
- * @brief Get instance number for ENC module.
- *
- * @param base ENC peripheral base address
- */
-static uint32_t ENC_GetInstance(ENC_Type *base);
-
-/*******************************************************************************
- * Variables
- ******************************************************************************/
-/*! @brief Pointers to ENC bases for each instance. */
-static ENC_Type *const s_encBases[] = ENC_BASE_PTRS;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief Pointers to ENC clocks for each instance. */
-static const clock_ip_name_t s_encClocks[] = ENC_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-static uint32_t ENC_GetInstance(ENC_Type *base)
-{
-    uint32_t instance;
-
-    /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < ARRAY_SIZE(s_encBases); instance++)
-    {
-        if (s_encBases[instance] == base)
-        {
-            break;
-        }
-    }
-
-    assert(instance < ARRAY_SIZE(s_encBases));
-
-    return instance;
-}
-
-/*!
- * brief Initialization for the ENC module.
- *
- * This function is to make the initialization for the ENC module. It should be called firstly before any operation to
- * the ENC with the operations like:
- *  - Enable the clock for ENC module.
- *  - Configure the ENC's working attributes.
- *
- * param base   ENC peripheral base address.
- * param config Pointer to configuration structure. See to "enc_config_t".
- */
-void ENC_Init(ENC_Type *base, const enc_config_t *config)
-{
-    assert(NULL != config);
-
-    uint16_t tmp16;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Enable the clock. */
-    CLOCK_EnableClock(s_encClocks[ENC_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-    /* ENC_CTRL. */
-    tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_HIP_MASK | ENC_CTRL_HNE_MASK | ENC_CTRL_REV_MASK |
-                                      ENC_CTRL_PH1_MASK | ENC_CTRL_XIP_MASK | ENC_CTRL_XNE_MASK | ENC_CTRL_WDE_MASK));
-    /* For HOME trigger. */
-    if (kENC_HOMETriggerDisabled != config->HOMETriggerMode)
-    {
-        tmp16 |= ENC_CTRL_HIP_MASK;
-        if (kENC_HOMETriggerOnFallingEdge == config->HOMETriggerMode)
-        {
-            tmp16 |= ENC_CTRL_HNE_MASK;
-        }
-    }
-    /* For encoder work mode. */
-    if (config->enableReverseDirection)
-    {
-        tmp16 |= ENC_CTRL_REV_MASK;
-    }
-    if (kENC_DecoderWorkAsSignalPhaseCountMode == config->decoderWorkMode)
-    {
-        tmp16 |= ENC_CTRL_PH1_MASK;
-    }
-    /* For INDEX trigger. */
-    if (kENC_INDEXTriggerDisabled != config->INDEXTriggerMode)
-    {
-        tmp16 |= ENC_CTRL_XIP_MASK;
-        if (kENC_INDEXTriggerOnFallingEdge == config->INDEXTriggerMode)
-        {
-            tmp16 |= ENC_CTRL_XNE_MASK;
-        }
-    }
-    /* Watchdog. */
-    if (config->enableWatchdog)
-    {
-        tmp16 |= ENC_CTRL_WDE_MASK;
-        base->WTR = config->watchdogTimeoutValue; /* WDOG can be only available when the feature is enabled. */
-    }
-    base->CTRL = tmp16;
-
-    /* ENC_FILT. */
-    base->FILT = ENC_FILT_FILT_CNT(config->filterCount) | ENC_FILT_FILT_PER(config->filterSamplePeriod);
-
-    /* ENC_CTRL2. */
-    tmp16 = base->CTRL2 & (uint16_t)(~(ENC_CTRL2_W1C_FLAGS | ENC_CTRL2_OUTCTL_MASK | ENC_CTRL2_REVMOD_MASK |
-                                       ENC_CTRL2_MOD_MASK | ENC_CTRL2_UPDPOS_MASK | ENC_CTRL2_UPDHLD_MASK));
-    if (kENC_POSMATCHOnReadingAnyPositionCounter == config->positionMatchMode)
-    {
-        tmp16 |= ENC_CTRL2_OUTCTL_MASK;
-    }
-    if (kENC_RevolutionCountOnRollOverModulus == config->revolutionCountCondition)
-    {
-        tmp16 |= ENC_CTRL2_REVMOD_MASK;
-    }
-    if (config->enableModuloCountMode)
-    {
-        tmp16 |= ENC_CTRL2_MOD_MASK;
-        /* Set modulus value. */
-        base->UMOD = (uint16_t)(config->positionModulusValue >> 16U); /* Upper 16 bits. */
-        base->LMOD = (uint16_t)(config->positionModulusValue);        /* Lower 16 bits. */
-    }
-    if (config->enableTRIGGERClearPositionCounter)
-    {
-        tmp16 |= ENC_CTRL2_UPDPOS_MASK;
-    }
-    if (config->enableTRIGGERClearHoldPositionCounter)
-    {
-        tmp16 |= ENC_CTRL2_UPDHLD_MASK;
-    }
-    base->CTRL2 = tmp16;
-
-#if (defined(FSL_FEATURE_ENC_HAS_CTRL3) && FSL_FEATURE_ENC_HAS_CTRL3)
-    /* ENC_CTRL3. */
-    tmp16 = base->CTRL3 & (uint16_t)(~(ENC_CTRL3_PMEN_MASK | ENC_CTRL3_PRSC_MASK));
-    if (config->enablePeriodMeasurementFunction)
-    {
-        tmp16 |= ENC_CTRL3_PMEN_MASK;
-        /* Set prescaler value. */
-        tmp16 |= ((uint16_t)config->prescalerValue << ENC_CTRL3_PRSC_SHIFT);
-    }
-    base->CTRL3 = tmp16;
-#endif
-
-    /* ENC_UCOMP & ENC_LCOMP. */
-    base->UCOMP = (uint16_t)(config->positionCompareValue >> 16U); /* Upper 16 bits. */
-    base->LCOMP = (uint16_t)(config->positionCompareValue);        /* Lower 16 bits. */
-
-    /* ENC_UINIT & ENC_LINIT. */
-    base->UINIT = (uint16_t)(config->positionInitialValue >> 16U); /* Upper 16 bits. */
-    base->LINIT = (uint16_t)(config->positionInitialValue);        /* Lower 16 bits. */
-}
-
-/*!
- * brief De-initialization for the ENC module.
- *
- * This function is to make the de-initialization for the ENC module. It could be called when ENC is no longer used with
- * the operations like:
- *  - Disable the clock for ENC module.
- *
- * param base ENC peripheral base address.
- */
-void ENC_Deinit(ENC_Type *base)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Disable the clock. */
-    CLOCK_DisableClock(s_encClocks[ENC_GetInstance(base)]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
-
-/*!
- * brief Get an available pre-defined settings for ENC's configuration.
- *
- * This function initializes the ENC configuration structure with an available settings, the default value are:
- * code
- *   config->enableReverseDirection                = false;
- *   config->decoderWorkMode                       = kENC_DecoderWorkAsNormalMode;
- *   config->HOMETriggerMode                       = kENC_HOMETriggerDisabled;
- *   config->INDEXTriggerMode                      = kENC_INDEXTriggerDisabled;
- *   config->enableTRIGGERClearPositionCounter     = false;
- *   config->enableTRIGGERClearHoldPositionCounter = false;
- *   config->enableWatchdog                        = false;
- *   config->watchdogTimeoutValue                  = 0U;
- *   config->filterCount                           = 0U;
- *   config->filterSamplePeriod                    = 0U;
- *   config->positionMatchMode                     = kENC_POSMATCHOnPositionCounterEqualToComapreValue;
- *   config->positionCompareValue                  = 0xFFFFFFFFU;
- *   config->revolutionCountCondition              = kENC_RevolutionCountOnINDEXPulse;
- *   config->enableModuloCountMode                 = false;
- *   config->positionModulusValue                  = 0U;
- *   config->positionInitialValue                  = 0U;
- *   config->prescalerValue                        = kENC_ClockDiv1;
- *   config->enablePeriodMeasurementFunction       = true;
- * endcode
- * param config Pointer to a variable of configuration structure. See to "enc_config_t".
- */
-void ENC_GetDefaultConfig(enc_config_t *config)
-{
-    assert(NULL != config);
-
-    /* Initializes the configure structure to zero. */
-    (void)memset(config, 0, sizeof(*config));
-
-    config->enableReverseDirection                = false;
-    config->decoderWorkMode                       = kENC_DecoderWorkAsNormalMode;
-    config->HOMETriggerMode                       = kENC_HOMETriggerDisabled;
-    config->INDEXTriggerMode                      = kENC_INDEXTriggerDisabled;
-    config->enableTRIGGERClearPositionCounter     = false;
-    config->enableTRIGGERClearHoldPositionCounter = false;
-    config->enableWatchdog                        = false;
-    config->watchdogTimeoutValue                  = 0U;
-    config->filterCount                           = 0U;
-    config->filterSamplePeriod                    = 0U;
-    config->positionMatchMode                     = kENC_POSMATCHOnPositionCounterEqualToComapreValue;
-    config->positionCompareValue                  = 0xFFFFFFFFU;
-    config->revolutionCountCondition              = kENC_RevolutionCountOnINDEXPulse;
-    config->enableModuloCountMode                 = false;
-    config->positionModulusValue                  = 0U;
-    config->positionInitialValue                  = 0U;
-#if (defined(FSL_FEATURE_ENC_HAS_CTRL3) && FSL_FEATURE_ENC_HAS_CTRL3)
-    config->prescalerValue                  = kENC_ClockDiv1;
-    config->enablePeriodMeasurementFunction = true;
-#endif
-}
-
-/*!
- * brief Load the initial position value to position counter.
- *
- * This function is to transfer the initial position value (UINIT and LINIT) contents to position counter (UPOS and
- * LPOS), so that to provide the consistent operation the position counter registers.
- *
- * param base ENC peripheral base address.
- */
-void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base)
-{
-    uint16_t tmp16 = base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS);
-
-    tmp16 |= ENC_CTRL_SWIP_MASK; /* Write 1 to trigger the command for loading initial position value. */
-    base->CTRL = tmp16;
-}
-
-/*!
- * brief Enable and configure the self test function.
- *
- * This function is to enable and configuration the self test function. It controls and sets the frequency of a
- * quadrature signal generator. It provides a quadrature test signal to the inputs of the quadrature decoder module.
- * It is a factory test feature; however, it may be useful to customers' software development and testing.
- *
- * param base   ENC peripheral base address.
- * param config Pointer to configuration structure. See to "enc_self_test_config_t". Pass "NULL" to disable.
- */
-void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config)
-{
-    uint16_t tmp16 = 0U;
-
-    if (NULL == config) /* Pass "NULL" to disable the feature. */
-    {
-        tmp16 = 0U;
-    }
-    else
-    {
-        tmp16 = ENC_TST_TEN_MASK | ENC_TST_TCE_MASK | ENC_TST_TEST_PERIOD(config->signalPeriod) |
-                ENC_TST_TEST_COUNT(config->signalCount);
-        if (kENC_SelfTestDirectionNegative == config->signalDirection)
-        {
-            tmp16 |= ENC_TST_QDN_MASK;
-        }
-    }
-
-    base->TST = tmp16;
-}
-
-/*!
- * brief Enable watchdog for ENC module.
- *
- * param base ENC peripheral base address
- * param enable Enables or disables the watchdog
- */
-void ENC_EnableWatchdog(ENC_Type *base, bool enable)
-{
-    uint16_t tmp16 = base->CTRL & (uint16_t)(~(ENC_CTRL_W1C_FLAGS | ENC_CTRL_WDE_MASK));
-
-    if (enable)
-    {
-        tmp16 |= ENC_CTRL_WDE_MASK;
-    }
-    base->CTRL = tmp16;
-}
-
-/*!
- * brief  Get the status flags.
- *
- * param  base ENC peripheral base address.
- *
- * return      Mask value of status flags. For available mask, see to "_enc_status_flags".
- */
-uint32_t ENC_GetStatusFlags(ENC_Type *base)
-{
-    uint32_t ret32 = 0U;
-
-    /* ENC_CTRL. */
-    if (0U != (ENC_CTRL_HIRQ_MASK & base->CTRL))
-    {
-        ret32 |= (uint32_t)kENC_HOMETransitionFlag;
-    }
-    if (0U != (ENC_CTRL_XIRQ_MASK & base->CTRL))
-    {
-        ret32 |= (uint32_t)kENC_INDEXPulseFlag;
-    }
-    if (0U != (ENC_CTRL_DIRQ_MASK & base->CTRL))
-    {
-        ret32 |= (uint32_t)kENC_WatchdogTimeoutFlag;
-    }
-    if (0U != (ENC_CTRL_CMPIRQ_MASK & base->CTRL))
-    {
-        ret32 |= (uint32_t)kENC_PositionCompareFlag;
-    }
-
-    /* ENC_CTRL2. */
-#if !(defined(FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT)
-    if (0U != (ENC_CTRL2_SABIRQ_MASK & base->CTRL2))
-    {
-        ret32 |= (uint32_t)kENC_SimultBothPhaseChangeFlag;
-    }
-#endif
-    if (0U != (ENC_CTRL2_ROIRQ_MASK & base->CTRL2))
-    {
-        ret32 |= (uint32_t)kENC_PositionRollOverFlag;
-    }
-    if (0U != (ENC_CTRL2_RUIRQ_MASK & base->CTRL2))
-    {
-        ret32 |= (uint32_t)kENC_PositionRollUnderFlag;
-    }
-    if (0U != (ENC_CTRL2_DIR_MASK & base->CTRL2))
-    {
-        ret32 |= (uint32_t)kENC_LastCountDirectionFlag;
-    }
-
-    return ret32;
-}
-
-/*!
- * brief Clear the status flags.
- *
- * param base ENC peripheral base address.
- * param mask Mask value of status flags to be cleared. For available mask, see to "_enc_status_flags".
- */
-void ENC_ClearStatusFlags(ENC_Type *base, uint32_t mask)
-{
-    uint32_t tmp16 = 0U;
-
-    /* ENC_CTRL. */
-    if (0U != ((uint32_t)kENC_HOMETransitionFlag & mask))
-    {
-        tmp16 |= ENC_CTRL_HIRQ_MASK;
-    }
-    if (0U != ((uint32_t)kENC_INDEXPulseFlag & mask))
-    {
-        tmp16 |= ENC_CTRL_XIRQ_MASK;
-    }
-    if (0U != ((uint32_t)kENC_WatchdogTimeoutFlag & mask))
-    {
-        tmp16 |= ENC_CTRL_DIRQ_MASK;
-    }
-    if (0U != ((uint32_t)kENC_PositionCompareFlag & mask))
-    {
-        tmp16 |= ENC_CTRL_CMPIRQ_MASK;
-    }
-    if (0U != tmp16)
-    {
-        base->CTRL = (uint16_t)(((uint32_t)base->CTRL & (~ENC_CTRL_W1C_FLAGS)) | tmp16);
-    }
-
-    /* ENC_CTRL2. */
-    tmp16 = 0U;
-#if !(defined(FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT)
-    if (0U != ((uint32_t)kENC_SimultBothPhaseChangeFlag & mask))
-    {
-        tmp16 |= ENC_CTRL2_SABIRQ_MASK;
-    }
-#endif
-    if (0U != ((uint32_t)kENC_PositionRollOverFlag & mask))
-    {
-        tmp16 |= ENC_CTRL2_ROIRQ_MASK;
-    }
-    if (0U != ((uint32_t)kENC_PositionRollUnderFlag & mask))
-    {
-        tmp16 |= ENC_CTRL2_RUIRQ_MASK;
-    }
-    if (0U != tmp16)
-    {
-        base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~ENC_CTRL2_W1C_FLAGS)) | tmp16);
-    }
-}
-
-/*!
- * brief Enable the interrupts.
- *
- * param base ENC peripheral base address.
- * param mask Mask value of interrupts to be enabled. For available mask, see to "_enc_interrupt_enable".
- */
-void ENC_EnableInterrupts(ENC_Type *base, uint32_t mask)
-{
-    uint32_t tmp16 = 0U;
-
-    /* ENC_CTRL. */
-    if (0U != ((uint32_t)kENC_HOMETransitionInterruptEnable & mask))
-    {
-        tmp16 |= ENC_CTRL_HIE_MASK;
-    }
-    if (0U != ((uint32_t)kENC_INDEXPulseInterruptEnable & mask))
-    {
-        tmp16 |= ENC_CTRL_XIE_MASK;
-    }
-    if (0U != ((uint32_t)kENC_WatchdogTimeoutInterruptEnable & mask))
-    {
-        tmp16 |= ENC_CTRL_DIE_MASK;
-    }
-    if (0U != ((uint32_t)kENC_PositionCompareInerruptEnable & mask))
-    {
-        tmp16 |= ENC_CTRL_CMPIE_MASK;
-    }
-    if (tmp16 != 0U)
-    {
-        base->CTRL = (uint16_t)(((uint32_t)base->CTRL & (~ENC_CTRL_W1C_FLAGS)) | tmp16);
-    }
-    /* ENC_CTRL2. */
-    tmp16 = 0U;
-#if !(defined(FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT)
-    if (0U != ((uint32_t)kENC_SimultBothPhaseChangeInterruptEnable & mask))
-    {
-        tmp16 |= ENC_CTRL2_SABIE_MASK;
-    }
-#endif
-    if (0U != ((uint32_t)kENC_PositionRollOverInterruptEnable & mask))
-    {
-        tmp16 |= ENC_CTRL2_ROIE_MASK;
-    }
-    if (0U != ((uint32_t)kENC_PositionRollUnderInterruptEnable & mask))
-    {
-        tmp16 |= ENC_CTRL2_RUIE_MASK;
-    }
-    if (tmp16 != 0U)
-    {
-        base->CTRL2 = (uint16_t)(((uint32_t)base->CTRL2 & (~ENC_CTRL2_W1C_FLAGS)) | tmp16);
-    }
-}
-
-/*!
- * brief Disable the interrupts.
- *
- * param base ENC peripheral base address.
- * param mask Mask value of interrupts to be disabled. For available mask, see to "_enc_interrupt_enable".
- */
-void ENC_DisableInterrupts(ENC_Type *base, uint32_t mask)
-{
-    uint16_t tmp16 = 0U;
-
-    /* ENC_CTRL. */
-    if (0U != ((uint32_t)kENC_HOMETransitionInterruptEnable & mask))
-    {
-        tmp16 |= ENC_CTRL_HIE_MASK;
-    }
-    if (0U != ((uint32_t)kENC_INDEXPulseInterruptEnable & mask))
-    {
-        tmp16 |= ENC_CTRL_XIE_MASK;
-    }
-    if (0U != ((uint32_t)kENC_WatchdogTimeoutInterruptEnable & mask))
-    {
-        tmp16 |= ENC_CTRL_DIE_MASK;
-    }
-    if (0U != ((uint32_t)kENC_PositionCompareInerruptEnable & mask))
-    {
-        tmp16 |= ENC_CTRL_CMPIE_MASK;
-    }
-    if (0U != tmp16)
-    {
-        base->CTRL = (uint16_t)(base->CTRL & (uint16_t)(~ENC_CTRL_W1C_FLAGS)) & (uint16_t)(~tmp16);
-    }
-    /* ENC_CTRL2. */
-    tmp16 = 0U;
-#if !(defined(FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT)
-    if (0U != ((uint32_t)kENC_SimultBothPhaseChangeInterruptEnable & mask))
-    {
-        tmp16 |= ENC_CTRL2_SABIE_MASK;
-    }
-#endif
-    if (0U != ((uint32_t)kENC_PositionRollOverInterruptEnable & mask))
-    {
-        tmp16 |= ENC_CTRL2_ROIE_MASK;
-    }
-    if (0U != ((uint32_t)kENC_PositionRollUnderInterruptEnable & mask))
-    {
-        tmp16 |= ENC_CTRL2_RUIE_MASK;
-    }
-    if (tmp16 != 0U)
-    {
-        base->CTRL2 = (uint16_t)(base->CTRL2 & (uint16_t)(~ENC_CTRL2_W1C_FLAGS)) & (uint16_t)(~tmp16);
-    }
-}
-
-/*!
- * brief  Get the enabled interrupts' flags.
- *
- * param  base ENC peripheral base address.
- *
- * return      Mask value of enabled interrupts.
- */
-uint32_t ENC_GetEnabledInterrupts(ENC_Type *base)
-{
-    uint32_t ret32 = 0U;
-
-    /* ENC_CTRL. */
-    if (0U != (ENC_CTRL_HIE_MASK & base->CTRL))
-    {
-        ret32 |= (uint32_t)kENC_HOMETransitionInterruptEnable;
-    }
-    if (0U != (ENC_CTRL_XIE_MASK & base->CTRL))
-    {
-        ret32 |= (uint32_t)kENC_INDEXPulseInterruptEnable;
-    }
-    if (0U != (ENC_CTRL_DIE_MASK & base->CTRL))
-    {
-        ret32 |= (uint32_t)kENC_WatchdogTimeoutInterruptEnable;
-    }
-    if (0U != (ENC_CTRL_CMPIE_MASK & base->CTRL))
-    {
-        ret32 |= (uint32_t)kENC_PositionCompareInerruptEnable;
-    }
-    /* ENC_CTRL2. */
-#if !(defined(FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT) && FSL_FEATURE_ENC_HAS_NO_CTRL2_SAB_INT)
-    if (0U != (ENC_CTRL2_SABIE_MASK & base->CTRL2))
-    {
-        ret32 |= (uint32_t)kENC_SimultBothPhaseChangeInterruptEnable;
-    }
-#endif
-    if (0U != (ENC_CTRL2_ROIE_MASK & base->CTRL2))
-    {
-        ret32 |= (uint32_t)kENC_PositionRollOverInterruptEnable;
-    }
-    if (0U != (ENC_CTRL2_RUIE_MASK & base->CTRL2))
-    {
-        ret32 |= (uint32_t)kENC_PositionRollUnderInterruptEnable;
-    }
-    return ret32;
-}
-
-/*!
- * brief Set initial position value for ENC module.
- *
- * param base ENC peripheral base address
- * param value Positive initial value
- */
-void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value)
-{
-    base->UINIT = (uint16_t)(value >> 16U); /* Set upper 16 bits. */
-    base->LINIT = (uint16_t)(value);        /* Set lower 16 bits. */
-}
-
-/*!
- * brief  Get the current position counter's value.
- *
- * param  base ENC peripheral base address.
- *
- * return     Current position counter's value.
- */
-uint32_t ENC_GetPositionValue(ENC_Type *base)
-{
-    uint32_t ret32;
-
-    ret32 = base->UPOS; /* Get upper 16 bits and make a snapshot. */
-    ret32 <<= 16U;
-    ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */
-
-    return ret32;
-}
-
-/*!
- * brief  Get the hold position counter's value.
- *
- * When any of the counter registers is read, the contents of each counter register is written to the corresponding hold
- * register. Taking a snapshot of the counters' values provides a consistent view of a system position and a velocity to
- * be attained.
- *
- * param  base ENC peripheral base address.
- *
- * return      Hold position counter's value.
- */
-uint32_t ENC_GetHoldPositionValue(ENC_Type *base)
-{
-    uint32_t ret32;
-
-    ret32 = base->UPOSH; /* Get upper 16 bits and make a snapshot. */
-    ret32 <<= 16U;
-    ret32 |= base->LPOSH; /* Get lower 16 bits from hold register. */
-
-    return ret32;
-}

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.c

@@ -1,9 +1,10 @@
 /*
- * Copyright 2022 NXP
+ * Copyright 2022-2024 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
+#include <math.h>
 #include "fsl_enet.h"
 
 /*******************************************************************************
@@ -41,7 +42,7 @@
 #define ENET_HEAD_AVBTYPE_OFFSET (16)
 
 /*! @brief Binary rollover mode count convert */
-#define ENET_BINARY_ROLLOVER_SCALE(x) (uint32_t)((uint64_t)(x)*46566U / 100000U)
+#define ENET_BINARY_ROLLOVER_SCALE(x) (uint32_t)((uint64_t)(x) * 46566U / 100000U)
 
 /*******************************************************************************
  * Prototypes
@@ -302,7 +303,8 @@ static void ENET_SetMacControl(ENET_Type *base, const enet_config_t *config, uin
     /* Set the speed and duplex. */
     reg = ENET_MAC_CONFIGURATION_ECRSFD_MASK | ENET_MAC_CONFIGURATION_PS_MASK |
           ENET_MAC_CONFIGURATION_DM(config->miiDuplex) | ENET_MAC_CONFIGURATION_FES(config->miiSpeed) |
-          ENET_MAC_CONFIGURATION_S2KP(!((config->specialControl & (uint16_t)kENET_8023AS2KPacket) == 0U));
+          ENET_MAC_CONFIGURATION_S2KP((config->specialControl & (uint16_t)kENET_8023AS2KPacket) != 0U) |
+          ENET_MAC_CONFIGURATION_IPC((config->specialControl & (uint16_t)kENET_RxChecksumOffloadEnable) != 0U);
     if (config->miiDuplex == kENET_MiiHalfDuplex)
     {
         reg |= ENET_MAC_CONFIGURATION_IPG(ENET_HALFDUPLEX_DEFAULTIPG);
@@ -751,7 +753,7 @@ void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask)
             base->DMA_CH[index].DMA_CHX_INT_EN = interrupt;
         }
     }
-    interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET;
+    interrupt = mask >> ENET_MACINT_ENUM_OFFSET;
     if (interrupt != 0U)
     {
         /* MAC interrupt */
@@ -829,7 +831,7 @@ void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask)
             base->DMA_CH[index].DMA_CHX_INT_EN &= ~interrupt;
         }
     }
-    interrupt = interrupt >> ENET_MACINT_ENUM_OFFSET;
+    interrupt = mask >> ENET_MACINT_ENUM_OFFSET;
     if (interrupt != 0U)
     {
         /* MAC interrupt */
@@ -867,6 +869,8 @@ void ENET_CreateHandler(ENET_Type *base,
     uint8_t count                    = 0;
     uint8_t rxIntEnable              = 0;
     enet_buffer_config_t *buffConfig = bufferConfig;
+    uint32_t txFifoSize;
+    uint32_t pbl;
 
     /* Store transfer parameters in handle pointer. */
     (void)memset(handle, 0, sizeof(enet_handle_t));
@@ -901,10 +905,24 @@ void ENET_CreateHandler(ENET_Type *base,
 
         /* Check if the Rx interrrupt is enabled. */
         rxIntEnable |= (uint8_t)(uint32_t)(base->DMA_CH[count].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK);
+
+        /* Calculate the reserved space for Tx in certain cases. */
+        if (0U != (base->MTL_QUEUE[count].MTL_TXQX_OP_MODE & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK))
+        {
+            pbl = (base->DMA_CH[count].DMA_CHX_TX_CTRL & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK) >>
+                  ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT;
+            pbl = ((base->DMA_CH[count].DMA_CHX_CTRL & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK) != 0U) ? (8U * pbl) : pbl;
+            txFifoSize                     = (uint32_t)pow((double)2,
+                                                           (double)(uint32_t)(((base->MAC_HW_FEAT[1] & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK) >>
+                                                           ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT) +
+                                                          7U));
+            handle->txLenLimitation[count] = txFifoSize - (pbl + 6U) * (32U / 8U);
+        }
+
         buffConfig++;
     }
 
-    handle->rxintEnable = (rxIntEnable != 0U) ? true : false;
+    handle->rxintEnable = (rxIntEnable != 0U);
 
     /* Save the handle pointer in the global variables. */
     s_ENETHandle[ENET_GetInstance(base)] = handle;
@@ -1135,6 +1153,127 @@ void ENET_EnterPowerDown(ENET_Type *base, uint32_t *wakeFilter)
     base->MAC_CONFIGURATION |= ENET_MAC_CONFIGURATION_RE_MASK;
 }
 
+/*!
+ * brief Set VLAN control.
+ *
+ * param base  ENET peripheral base address.
+ * param control  VLAN control configuration.
+ */
+status_t ENET_SetVlanCtrl(ENET_Type *base, enet_vlan_ctrl_t *control)
+{
+    uint32_t vl = (((uint32_t)control->rxVlanTag.pcp) << 13U) | (((uint32_t)control->rxVlanTag.dei) << 12U) |
+                  (uint32_t)control->rxVlanTag.vid;
+    uint32_t vlanCtrl;
+
+    if ((control->innerVlanFilterMatch) && (!control->doubleVlanEnable))
+    {
+        return kStatus_Fail;
+    }
+
+    vlanCtrl = ENET_MAC_VLAN_TAG_CTRL_VL(vl) | ENET_MAC_VLAN_TAG_CTRL_ETV(control->vidComparison) |
+               ENET_MAC_VLAN_TAG_CTRL_VTIM(control->vlanInverseMatch) |
+               ENET_MAC_VLAN_TAG_CTRL_ESVL(control->svlanEnable) |
+               ENET_MAC_VLAN_TAG_CTRL_DOVLTC(control->disableVlanTypeCheck) |
+               ENET_MAC_VLAN_TAG_CTRL_EVLS(control->rxOuterVlanStrip) |
+               ENET_MAC_VLAN_TAG_CTRL_EIVLS(control->rxInnerVlanStrip) |
+               ENET_MAC_VLAN_TAG_CTRL_EDVLP(control->doubleVlanEnable) |
+               ENET_MAC_VLAN_TAG_CTRL_ERIVLT(control->innerVlanFilterMatch) |
+               ENET_MAC_VLAN_TAG_CTRL_EVLRXS(control->outerTagInRxStatus) |
+               ENET_MAC_VLAN_TAG_CTRL_EIVLRXS(control->innerTagInRxStatus);
+
+    if (control->rxVlanTag.tpid == kENET_StanSvlan)
+    {
+        vlanCtrl |= ENET_MAC_VLAN_TAG_CTRL_ERSVLM_MASK;
+    }
+    base->MAC_VLAN_TAG_CTRL = vlanCtrl;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Set Tx outer VLAN configuration.
+ *
+ * param base  ENET peripheral base address.
+ * param config  Tx VLAN operation configuration.
+ * param channel  The channel to apply this configuration.
+ */
+status_t ENET_SetTxOuterVlan(ENET_Type *base, enet_vlan_tx_config_t *config, enet_vlan_tx_channel_t channel)
+{
+    uint32_t vlt =
+        (((uint32_t)config->tag.pcp) << 13U) | (((uint32_t)config->tag.dei) << 12U) | (uint32_t)config->tag.vid;
+    uint32_t vlanConfig = ENET_MAC_VLAN_INCL_VLTI(config->txDescVlan) | ENET_MAC_VLAN_INCL_CSVL(config->tag.tpid) |
+                          ENET_MAC_VLAN_INCL_VLC(config->ops) | ENET_MAC_VLAN_INCL_VLT(vlt);
+
+    if ((config->tag.tpid == kENET_StanSvlan) && ((base->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_ESVL_MASK) == 0U))
+    {
+        return kStatus_Fail;
+    }
+
+    if (config->ops != kENET_NoOps)
+    {
+        vlanConfig |= ENET_MAC_VLAN_INCL_VLP(1);
+    }
+
+    if (channel != kENET_VlanTagAllChannels)
+    {
+        while ((base->MAC_VLAN_INCL & ENET_MAC_VLAN_INCL_BUSY_MASK) != 0U)
+        {
+        }
+
+        /* Clear and status ans reset the power down. */
+        base->MAC_VLAN_INCL |=
+            ENET_MAC_VLAN_INCL_CBTI_MASK | ENET_MAC_VLAN_INCL_RDWR_MASK | ENET_MAC_VLAN_INCL_ADDR(channel) | vlanConfig;
+
+        while ((base->MAC_VLAN_INCL & ENET_MAC_VLAN_INCL_BUSY_MASK) != 0U)
+        {
+        }
+
+        /* Clear set channel bits. */
+        base->MAC_VLAN_INCL &= ~(ENET_MAC_VLAN_INCL_RDWR_MASK | ENET_MAC_VLAN_INCL_CBTI_MASK);
+    }
+    else
+    {
+        base->MAC_VLAN_INCL = vlanConfig;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Set Tx inner VLAN configuration.
+ *
+ * param base  ENET peripheral base address.
+ * param config  Tx VLAN operation configuration.
+ */
+status_t ENET_SetTxInnerVlan(ENET_Type *base, enet_vlan_tx_config_t *config)
+{
+    uint32_t vlt =
+        (((uint32_t)config->tag.pcp) << 13U) | (((uint32_t)config->tag.dei) << 12U) | (uint32_t)config->tag.vid;
+    uint32_t vlanConfig = ENET_MAC_INNER_VLAN_INCL_VLTI(config->txDescVlan) |
+                          ENET_MAC_INNER_VLAN_INCL_CSVL(config->tag.tpid) | ENET_MAC_INNER_VLAN_INCL_VLC(config->ops) |
+                          ENET_MAC_INNER_VLAN_INCL_VLT(vlt);
+
+    /* S-VLAN should be enabled first. */
+    if ((config->tag.tpid == kENET_StanSvlan) && ((base->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_ESVL_MASK) == 0U))
+    {
+        return kStatus_Fail;
+    }
+
+    /* Double VLAN should be enabled first for inner VLAN. */
+    if ((base->MAC_VLAN_TAG_CTRL & ENET_MAC_VLAN_TAG_CTRL_EDVLP_MASK) == 0U)
+    {
+        return kStatus_Fail;
+    }
+
+    if (config->ops != kENET_NoOps)
+    {
+        vlanConfig |= ENET_MAC_INNER_VLAN_INCL_VLP(1);
+    }
+    base->MAC_INNER_VLAN_INCL = vlanConfig;
+
+    return kStatus_Success;
+}
+
 /*!
  * brief Gets the size of the read frame.
  * This function gets a received frame size from the ENET buffer descriptors.
@@ -1551,7 +1690,6 @@ void ENET_RxBufferFreeAll(ENET_Type *base, enet_handle_t *handle)
 
 static inline void ENET_GetRxFrameErr(enet_rx_bd_struct_t *rxDesc, enet_rx_frame_error_t *rxFrameError)
 {
-    uint32_t rdes3 = rxDesc->rdes3;
     union _frame_error
     {
         uint32_t data;
@@ -1559,9 +1697,8 @@ static inline void ENET_GetRxFrameErr(enet_rx_bd_struct_t *rxDesc, enet_rx_frame
     };
     union _frame_error error;
 
-    (void)memset((void *)&error.frameError, 0, sizeof(enet_rx_frame_error_t));
-
-    error.data = ENET_FRAME_RX_ERROR_BITS(rdes3);
+    error.data    = ENET_FRAME_RX_ERROR_BITS(rxDesc->rdes3);
+    *rxFrameError = error.frameError;
 }
 
 static void ENET_DropFrame(ENET_Type *base, enet_handle_t *handle, uint8_t channel)
@@ -1573,23 +1710,29 @@ static void ENET_DropFrame(ENET_Type *base, enet_handle_t *handle, uint8_t chann
     bool tsAvailable   = false;
     uint32_t buff1Addr = 0;
     uint32_t buff2Addr = 0;
+    uint32_t rdes1;
 #endif /* ENET_PTP1588FEATURE_REQUIRED */
+    uint32_t rdes3;
 
     /* Not check DMA ownership here, assume there's at least one valid frame left in BD ring */
     do
     {
         /* Update the BD to idle status. */
         rxDesc = &rxBdRing->rxBdBase[rxBdRing->rxGenIdx];
+#ifdef ENET_PTP1588FEATURE_REQUIRED
+        rdes1 = rxDesc->rdes1;
+#endif
+        rdes3 = rxDesc->rdes3;
         ENET_UpdateRxDescriptor(rxDesc, NULL, NULL, handle->rxintEnable, handle->doubleBuffEnable);
         rxBdRing->rxGenIdx = ENET_IncreaseIndex(rxBdRing->rxGenIdx, rxBdRing->rxRingLen);
 
         /* Find the last buffer descriptor for the frame. */
-        if ((rxDesc->rdes3 & ENET_RXDESCRIP_WR_LD_MASK) != 0U)
+        if ((rdes3 & ENET_RXDESCRIP_WR_LD_MASK) != 0U)
         {
 #ifdef ENET_PTP1588FEATURE_REQUIRED
-            if ((rxDesc->rdes3 & ENET_RXDESCRIP_WR_RS1V_MASK) != 0U)
+            if ((rdes3 & ENET_RXDESCRIP_WR_RS1V_MASK) != 0U)
             {
-                if ((rxDesc->rdes1 & ENET_RXDESCRIP_WR_PTPTSA_MASK) != 0U)
+                if ((rdes1 & ENET_RXDESCRIP_WR_PTPTSA_MASK) != 0U)
                 {
                     tsAvailable = true;
                 }
@@ -1631,10 +1774,7 @@ static void ENET_DropFrame(ENET_Type *base, enet_handle_t *handle, uint8_t chann
  * this function, driver will allocate new buffers for the BDs whose buffers have been taken by application.
  * note This function will drop current frame and update related BDs as available for DMA if new buffers allocating
  * fails. Application must provide a memory pool including at least BD number + 1 buffers(+2 if enable double buffer)
- * to make this function work normally. If user calls this function in Rx interrupt handler, be careful that this
- * function makes Rx BD ready with allocating new buffer(normal) or updating current BD(out of memory). If there's
- * always new Rx frame input, Rx interrupt will be triggered forever. Application need to disable Rx interrupt according
- * to specific design in this case.
+ * to make this function work normally.
  *
  * param base   ENET peripheral base address.
  * param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
@@ -1739,17 +1879,16 @@ status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_s
 
             if (rxFrame->totLen - offset > (uint16_t)rxBdRing->rxBuffSizeAlign)
             {
+                /* Here must be double buffer. */
+                assert(handle->doubleBuffEnable);
+
                 buff1Len = (uint16_t)rxBdRing->rxBuffSizeAlign;
-                if (handle->doubleBuffEnable)
-                {
-                    buff2Len = rxFrame->totLen - offset - (uint16_t)rxBdRing->rxBuffSizeAlign - ENET_FCS_LEN;
-                }
+                buff2Len = rxFrame->totLen - offset - (uint16_t)rxBdRing->rxBuffSizeAlign;
             }
             else
             {
-                buff1Len = rxFrame->totLen - offset - ENET_FCS_LEN;
+                buff1Len = rxFrame->totLen - offset;
             }
-            rxFrame->totLen -= ENET_FCS_LEN;
         }
         else
         {
@@ -1896,7 +2035,7 @@ status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_s
             /* Free the incomplete frame buffers. */
             while (index-- != 0U)
             {
-                handle->rxBuffFree(base, &rxFrame->rxBuffArray[index].buffer, handle->userData, channel);
+                handle->rxBuffFree(base, rxFrame->rxBuffArray[index].buffer, handle->userData, channel);
             }
 
             /* Update all left BDs of this frame from current index. */
@@ -1907,6 +2046,27 @@ status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_s
         }
     } while (!isLastBuff);
 
+    /* Remove 4 bytes FCS. */
+    if (result == kStatus_Success)
+    {
+        /* Find the last 4 bytes in the linked buffers and remove these FCS data. */
+        buff1Len = rxFrame->rxBuffArray[--index].length;
+        if (buff1Len > ENET_FCS_LEN)
+        {
+            rxFrame->rxBuffArray[index].length -= ENET_FCS_LEN;
+        }
+        else
+        {
+            rxFrame->rxBuffArray[index].length = 0;
+            handle->rxBuffFree(base, rxFrame->rxBuffArray[index].buffer, handle->userData, channel);
+            if (buff1Len < ENET_FCS_LEN)
+            {
+                rxFrame->rxBuffArray[--index].length -= (ENET_FCS_LEN - buff1Len);
+            }
+        }
+        rxFrame->totLen -= ENET_FCS_LEN;
+    }
+
     return result;
 }
 
@@ -1977,6 +2137,58 @@ void ENET_SetupTxDescriptor(enet_tx_bd_struct_t *txDesc,
     txDesc->tdes3 = control;
 }
 
+/*!
+ * brief Configure a given Tx descriptor.
+ *  This function is a low level functional API to setup or prepare
+ *  a given Tx descriptor.
+ *
+ * param txDesc  The given Tx descriptor.
+ * param config The Tx descriptor configuration.
+ *
+ * note This must be called after all the ENET initilization.
+ * And should be called when the ENET receive/transmit is required.
+ * Transmit buffers are 'zero-copy' buffers, so the buffer must remain in
+ * memory until the packet has been fully transmitted. The buffers
+ * should be free or requeued in the transmit interrupt irq handler.
+ */
+static void ENET_ConfigTxDescriptor(enet_tx_bd_struct_t *txDesc, enet_tx_bd_config_struct_t *config)
+{
+    uint32_t control                = ENET_TXDESCRIP_RD_BL1(config->bytes1) | ENET_TXDESCRIP_RD_BL2(config->bytes2);
+    enet_tx_offload_t txOffloadMode = kENET_TxOffloadDisable;
+
+    if ((config->flag == kENET_FirstFlagOnly) || (config->flag == kENET_FirstLastFlag))
+    {
+        if (config->tsEnable)
+        {
+            control |= ENET_TXDESCRIP_RD_TTSE_MASK;
+        }
+        else
+        {
+            control &= ~ENET_TXDESCRIP_RD_TTSE_MASK;
+        }
+        txOffloadMode = config->txOffloadOps;
+    }
+
+    if (config->intEnable)
+    {
+        control |= ENET_TXDESCRIP_RD_IOC_MASK;
+    }
+    else
+    {
+        control &= ~ENET_TXDESCRIP_RD_IOC_MASK;
+    }
+
+    /* Preare the descriptor for transmit. */
+    txDesc->tdes0 = (uint32_t)(uint32_t *)config->buffer1;
+    txDesc->tdes1 = (uint32_t)(uint32_t *)config->buffer2;
+    txDesc->tdes2 = control;
+
+    control = ENET_TXDESCRIP_RD_SLOT(config->slotNum) | ENET_TXDESCRIP_RD_FL(config->framelen) |
+              ENET_TXDESCRIP_RD_CIC(txOffloadMode) | ENET_TXDESCRIP_RD_LDFD(config->flag) | ENET_TXDESCRIP_RD_OWN_MASK;
+
+    txDesc->tdes3 = control;
+}
+
 /*!
  * brief Reclaim Tx descriptors.
  *  This function is used to update the Tx descriptor status and
@@ -2090,6 +2302,15 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, enet_tx_frame_st
         return kStatus_ENET_TxFrameOverLen;
     }
 
+    /* Check Tx FIFO whether can store enough frame data. */
+    if (0U != handle->txLenLimitation[channel])
+    {
+        if (frameLen > handle->txLenLimitation[channel])
+        {
+            return kStatus_ENET_TxFrameOverLen;
+        }
+    }
+
     /* Check whether the available BD number is enough for Tx data buffer. */
     if (txFrame->txBuffNum > (((uint32_t)txBdRing->txRingLen - (uint32_t)txBdRing->txDescUsed) * 2U))
     {
@@ -2116,22 +2337,32 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, enet_tx_frame_st
             descFlag = (leftBuffNum > 2U) ? kENET_MiddleFlag : kENET_LastFlagOnly;
         }
 
+        enet_tx_bd_config_struct_t txDescConfig = {0};
+
+        txDescConfig.framelen     = frameLen;
+        txDescConfig.intEnable    = (bool)txFrame->txConfig.intEnable;
+        txDescConfig.tsEnable     = (bool)txFrame->txConfig.tsEnable;
+        txDescConfig.txOffloadOps = txFrame->txConfig.txOffloadOps;
+        txDescConfig.flag         = descFlag;
+        txDescConfig.slotNum      = txFrame->txConfig.slotNum;
+
         /* Fill the descriptor. */
+        txDescConfig.buffer1 = txBuff[index].buffer;
+        txDescConfig.bytes1  = txBuff[index].length;
         if (leftBuffNum < 2U)
         {
-            ENET_SetupTxDescriptor(txDesc, txBuff[index].buffer, txBuff[index].length, NULL, 0, frameLen,
-                                   (bool)txFrame->txConfig.intEnable, (bool)txFrame->txConfig.tsEnable, descFlag,
-                                   txFrame->txConfig.slotNum);
+            txDescConfig.buffer2 = NULL;
+            txDescConfig.bytes2  = 0;
             leftBuffNum--;
         }
         else
         {
-            ENET_SetupTxDescriptor(txDesc, txBuff[index].buffer, txBuff[index].length, txBuff[index + 1U].buffer,
-                                   txBuff[index + 1U].length, frameLen, (bool)txFrame->txConfig.intEnable,
-                                   (bool)txFrame->txConfig.tsEnable, descFlag, txFrame->txConfig.slotNum);
+            txDescConfig.buffer2 = txBuff[index + 1U].buffer;
+            txDescConfig.bytes2  = txBuff[index + 1U].length;
             index += 2U;
             leftBuffNum -= 2U;
         }
+        ENET_ConfigTxDescriptor(txDesc, &txDescConfig);
 
         /* Increase the index. */
         txBdRing->txGenIdx = ENET_IncreaseIndex(txBdRing->txGenIdx, txBdRing->txRingLen);

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_enet.h

@@ -1,10 +1,10 @@
 /*
- * Copyright 2022 NXP
+ * Copyright 2022-2024 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_ENET_H_
-#define _FSL_ENET_H_
+#ifndef FSL_ENET_H_
+#define FSL_ENET_H_
 
 #include "fsl_common.h"
 
@@ -20,7 +20,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief Defines the driver version. */
-#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
 /*@}*/
 
 /*! @name Control and status region bit masks of the receive buffer descriptor. */
@@ -58,19 +58,19 @@
 /*! @brief Defines for read format. */
 #define ENET_TXDESCRIP_RD_BL1_MASK  (0x3fffU)
 #define ENET_TXDESCRIP_RD_BL2_MASK  (ENET_TXDESCRIP_RD_BL1_MASK << 16)
-#define ENET_TXDESCRIP_RD_BL1(n)    ((uint32_t)(n)&ENET_TXDESCRIP_RD_BL1_MASK)
-#define ENET_TXDESCRIP_RD_BL2(n)    (((uint32_t)(n)&ENET_TXDESCRIP_RD_BL1_MASK) << 16)
+#define ENET_TXDESCRIP_RD_BL1(n)    ((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK)
+#define ENET_TXDESCRIP_RD_BL2(n)    (((uint32_t)(n) & ENET_TXDESCRIP_RD_BL1_MASK) << 16)
 #define ENET_TXDESCRIP_RD_TTSE_MASK (1UL << 30)
 #define ENET_TXDESCRIP_RD_IOC_MASK  (1UL << 31)
 
 #define ENET_TXDESCRIP_RD_FL_MASK   (0x7FFFU)
-#define ENET_TXDESCRIP_RD_FL(n)     ((uint32_t)(n)&ENET_TXDESCRIP_RD_FL_MASK)
-#define ENET_TXDESCRIP_RD_CIC(n)    (((uint32_t)(n)&0x3U) << 16)
+#define ENET_TXDESCRIP_RD_FL(n)     ((uint32_t)(n) & ENET_TXDESCRIP_RD_FL_MASK)
+#define ENET_TXDESCRIP_RD_CIC(n)    (((uint32_t)(n) & 0x3U) << 16)
 #define ENET_TXDESCRIP_RD_TSE_MASK  (1UL << 18)
-#define ENET_TXDESCRIP_RD_SLOT(n)   (((uint32_t)(n)&0x0fU) << 19)
-#define ENET_TXDESCRIP_RD_SAIC(n)   (((uint32_t)(n)&0x07U) << 23)
-#define ENET_TXDESCRIP_RD_CPC(n)    (((uint32_t)(n)&0x03U) << 26)
-#define ENET_TXDESCRIP_RD_LDFD(n)   (((uint32_t)(n)&0x03U) << 28)
+#define ENET_TXDESCRIP_RD_SLOT(n)   (((uint32_t)(n) & 0x0fU) << 19)
+#define ENET_TXDESCRIP_RD_SAIC(n)   (((uint32_t)(n) & 0x07U) << 23)
+#define ENET_TXDESCRIP_RD_CPC(n)    (((uint32_t)(n) & 0x03U) << 26)
+#define ENET_TXDESCRIP_RD_LDFD(n)   (((uint32_t)(n) & 0x03U) << 28)
 #define ENET_TXDESCRIP_RD_LD_MASK   (1UL << 28)
 #define ENET_TXDESCRIP_RD_FD_MASK   (1UL << 29)
 #define ENET_TXDESCRIP_RD_CTXT_MASK (1UL << 30)
@@ -198,11 +198,12 @@ typedef enum _enet_special_config
     /**************************MTL************************************/
     kENET_StoreAndForward = 0x0002U, /*!< The Rx/Tx store and forward enable. */
     /***********************MAC****************************************/
-    kENET_PromiscuousEnable  = 0x0004U, /*!< The promiscuous enabled. */
-    kENET_FlowControlEnable  = 0x0008U, /*!< The flow control enabled. */
-    kENET_BroadCastRxDisable = 0x0010U, /*!< The broadcast disabled. */
-    kENET_MulticastAllEnable = 0x0020U, /*!< All multicast are passed. */
-    kENET_8023AS2KPacket     = 0x0040U  /*!< 8023as support for 2K packets. */
+    kENET_PromiscuousEnable       = 0x0004U, /*!< The promiscuous enabled. */
+    kENET_FlowControlEnable       = 0x0008U, /*!< The flow control enabled. */
+    kENET_BroadCastRxDisable      = 0x0010U, /*!< The broadcast disabled. */
+    kENET_MulticastAllEnable      = 0x0020U, /*!< All multicast are passed. */
+    kENET_8023AS2KPacket          = 0x0040U, /*!< 8023as support for 2K packets. */
+    kENET_RxChecksumOffloadEnable = 0x0080U, /*!< The Rx checksum offload enabled. */
 } enet_special_config_t;
 
 /*! @brief List of DMA interrupts supported by the ENET interrupt. This
@@ -282,6 +283,48 @@ typedef enum _enet_ptp_event_type
     kENET_PtpGnrlPort     = 320U  /*!< PTP general port number. */
 } enet_ptp_event_type_t;
 
+/*! @brief Define the Tx checksum offload options. */
+typedef enum _enet_tx_offload
+{
+    kENET_TxOffloadDisable             = 0U, /*!< Disable Tx checksum offload. */
+    kENET_TxOffloadIPHeader            = 1U, /*!< Enable IP header checksum calculation and insertion. */
+    kENET_TxOffloadIPHeaderPlusPayload = 2U, /*!< Enable IP header and payload checksum calculation and insertion. */
+    kENET_TxOffloadAll = 3U, /*!< Enable IP header, payload and pseudo header checksum calculation and insertion. */
+} enet_tx_offload_t;
+
+/*! @brief Ethernet VLAN Tag protocol identifiers. */
+typedef enum _enet_vlan_tpid
+{
+    kENET_StanCvlan = 0x0U, /*!< C-VLAN 0x8100. */
+    kENET_StanSvlan,        /*!< S-VLAN 0x88A8. */
+} enet_vlan_tpid_t;
+
+/*! @brief Ethernet VLAN operations. */
+typedef enum _enet_vlan_ops
+{
+    kENET_NoOps = 0x0U, /*!< Not do anything. */
+    kENET_VlanRemove,   /*!< Remove VLAN Tag. */
+    kENET_VlanInsert,   /*!< Insert VLAN Tag. */
+    kENET_VlanReplace,  /*!< Replace VLAN Tag. */
+} enet_vlan_ops_t;
+
+/*! @brief Ethernet VLAN strip setting. */
+typedef enum _enet_vlan_strip
+{
+    kENET_VlanNotStrip = 0x0U, /*!< Not strip frame. */
+    kENET_VlanFilterPassStrip, /*!< Strip if VLAN filter passes. */
+    kENET_VlanFilterFailStrip, /*!< Strip if VLAN filter fails. */
+    kENET_VlanAlwaysStrip,     /*!< Always strip. */
+} enet_vlan_strip_t;
+
+/*! @brief Ethernet VLAN Tx channels. */
+typedef enum _enet_vlan_tx_channel
+{
+    kENET_VlanTagAllChannels = 0xFFU, /*!< VLAN tag is inserted for every packets transmitted by the MAC. */
+    kENET_VlanTagChannel0    = 0x0U,  /*!< VLAN tag is inserted for the frames transmitted by channel 0. */
+    kENET_VlanTagChannel1,            /*!< VLAN tag is inserted for the frames transmitted by channel 1. */
+} enet_vlan_tx_channel_t;
+
 /*! @brief Defines the receive descriptor structure
  *  It has the read-format and write-back format structures. They both
  *  have the same size with different region definition. So we define
@@ -314,6 +357,21 @@ typedef struct _enet_tx_bd_struct
     __IO uint32_t tdes3; /*!< Transmit descriptor 3 */
 } enet_tx_bd_struct_t;
 
+/*! @brief Defines the Tx BD configuration structure. */
+typedef struct _enet_tx_bd_config_struct
+{
+    void *buffer1;                  /*!< The first buffer address in the descriptor. */
+    uint32_t bytes1;                /*!< The bytes in the fist buffer. */
+    void *buffer2;                  /*!< The second buffer address in the descriptor. */
+    uint32_t bytes2;                /*!< The bytes in the second buffer. */
+    uint32_t framelen;              /*!< The length of the frame to be transmitted. */
+    bool intEnable;                 /*!< Interrupt enable flag. */
+    bool tsEnable;                  /*!< The timestamp enable. */
+    enet_tx_offload_t txOffloadOps; /*!< The Tx checksum offload option, only vaild for Queue 0. */
+    enet_desc_flag_t flag;          /*!< The flag of this tx desciriptor, see "enet_qos_desc_flag". */
+    uint8_t slotNum;                /*!< The slot number used for AV mode only. */
+} enet_tx_bd_config_struct_t;
+
 #ifdef ENET_PTP1588FEATURE_REQUIRED
 /*! @brief Defines the ENET PTP configuration structure. */
 typedef struct _enet_ptp_config
@@ -322,7 +380,7 @@ typedef struct _enet_ptp_config
     bool ptp1588V2Enable;               /*!< ptp 1588 version 2 is used. */
     enet_ts_rollover_type_t tsRollover; /*!< 1588 time nanosecond rollover. */
 } enet_ptp_config_t;
-#endif /* ENET_PTP1588FEATURE_REQUIRED */
+#endif                                  /* ENET_PTP1588FEATURE_REQUIRED */
 
 /*! @brief Defines the ENET PTP time stamp structure. */
 typedef struct _enet_ptp_time
@@ -472,6 +530,7 @@ struct _enet_handle
     enet_tx_dirty_ring_t txDirtyRing[ENET_RING_NUM_MAX]; /*!< Transmit dirty buffers addresses.  */
     uint32_t *rxBufferStartAddr[ENET_RING_NUM_MAX];      /*!< The Init-Rx buffers used for reinit corrupted BD due to
                                                             write-back operation. */
+    uint32_t txLenLimitation[ENET_RING_NUM_MAX];         /*!< Tx frame length limitation. */
     enet_callback_t callback;                            /*!< Callback function. */
     void *userData;                                      /*!< Callback function parameter.*/
     enet_rx_alloc_callback_t rxBuffAlloc; /*!< Callback to alloc memory, must be provided for zero-copy Rx. */
@@ -513,9 +572,10 @@ typedef struct _enet_rx_frame_struct
 
 typedef struct _enet_tx_config_struct
 {
-    uint8_t intEnable : 1; /*!< Enable interrupt every time one BD is completed. */
-    uint8_t tsEnable : 1;  /*!< Transmit timestamp enable. */
-    uint8_t slotNum : 4;   /*!< Slot number control bits in AV mode. */
+    uint8_t intEnable : 1;          /*!< Enable interrupt every time one BD is completed. */
+    uint8_t tsEnable : 1;           /*!< Transmit timestamp enable. */
+    uint8_t slotNum : 4;            /*!< Slot number control bits in AV mode. */
+    enet_tx_offload_t txOffloadOps; /*!< Tx checksum offload option. */
 } enet_tx_config_struct_t;
 
 typedef struct _enet_tx_frame_struct
@@ -526,6 +586,39 @@ typedef struct _enet_tx_frame_struct
     void *context;                     /*!< Driver reclaims and gives it in Tx over callback. */
 } enet_tx_frame_struct_t;
 
+/*! @brief Ethernet VLAN Tag. */
+typedef struct _enet_vlan_tag
+{
+    enet_vlan_tpid_t tpid; /*!< VLAN TPID. */
+    uint16_t pcp : 3;      /*!< VLAN Priority. */
+    uint16_t dei : 1;      /*!< Drop Eligible indicator. */
+    uint16_t vid : 12;     /*!< VLAN Identifier. */
+} enet_vlan_tag_t;
+
+/*! @brief Ethernet VLAN configuration for Tx. */
+typedef struct _enet_vlan_tx_config
+{
+    bool txDescVlan;     /*!< Use VLAN configuration in Tx descriptor. */
+    enet_vlan_tag_t tag; /*!< VLAN Tag. */
+    enet_vlan_ops_t ops; /*!< VLAN operations. */
+} enet_vlan_tx_config_t;
+
+/*! @brief Ethernet VLAN control. */
+typedef struct _enet_vlan_ctrl
+{
+    bool svlanEnable : 1;          /*!< The MAC transmitter and receiver consider the S-VLAN packets. */
+    bool vlanInverseMatch : 1;     /*!< True: Marks frames without matching as match, False: Marks matched frames. */
+    bool vidComparison : 1;        /*!< Only takes VLAN VID as match. */
+    bool disableVlanTypeCheck : 1; /*!< Not check C-VLAN and S-VLAN. */
+    bool doubleVlanEnable : 1;     /*!< Enable the inner VLAN operations. */
+    bool innerVlanFilterMatch : 1; /*!< Takes Inner VLAN as match. */
+    bool outerTagInRxStatus : 1;   /*!< Set outer VLAN in Rx Status. */
+    bool innerTagInRxStatus : 1;   /*!< Set inner VLAN in Rx Status. */
+    enet_vlan_tag_t rxVlanTag;     /*!< VLAN tag for Rx match. */
+    enet_vlan_strip_t rxOuterVlanStrip; /*!< Outer VLAN Rx strip operation. */
+    enet_vlan_strip_t rxInnerVlanStrip; /*!< Inner VLAN Rx strip operation. */
+} enet_vlan_ctrl_t;
+
 /* Typedef for interrupt handler. */
 typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle);
 
@@ -853,6 +946,31 @@ static inline void ENET_ExitPowerDown(ENET_Type *base)
     base->MAC_CONFIGURATION |= ENET_MAC_CONFIGURATION_TE_MASK;
 }
 
+/*!
+ * @brief Set VLAN control.
+ *
+ * @param base  ENET peripheral base address.
+ * @param control  VLAN control configuration.
+ */
+status_t ENET_SetVlanCtrl(ENET_Type *base, enet_vlan_ctrl_t *control);
+
+/*!
+ * @brief Set Tx outer VLAN configuration.
+ *
+ * @param base  ENET peripheral base address.
+ * @param config  Tx VLAN operation configuration.
+ * @param channel  The channel to apply this configuration.
+ */
+status_t ENET_SetTxOuterVlan(ENET_Type *base, enet_vlan_tx_config_t *config, enet_vlan_tx_channel_t channel);
+
+/*!
+ * @brief Set Tx inner VLAN configuration.
+ *
+ * @param base  ENET peripheral base address.
+ * @param config  Tx VLAN operation configuration.
+ */
+status_t ENET_SetTxInnerVlan(ENET_Type *base, enet_vlan_tx_config_t *config);
+
 /* @} */
 
 /*!
@@ -1169,10 +1287,7 @@ status_t ENET_ReadFrame(ENET_Type *base,
  * this function, driver will allocate new buffers for the BDs whose buffers have been taken by application.
  * @note This function will drop current frame and update related BDs as available for DMA if new buffers allocating
  * fails. Application must provide a memory pool including at least BD number + 1 buffers(+2 if enable double buffer)
- * to make this function work normally. If user calls this function in Rx interrupt handler, be careful that this
- * function makes Rx BD ready with allocating new buffer(normal) or updating current BD(out of memory). If there's
- * always new Rx frame input, Rx interrupt will be triggered forever. Application need to disable Rx interrupt according
- * to specific design in this case.
+ * to make this function work normally.
  *
  * @param base   ENET peripheral base address.
  * @param handle The ENET handler pointer. This is the same handler pointer used in the ENET_Init.
@@ -1302,4 +1417,4 @@ void ENET_Ptp1588GetTimer(ENET_Type *base, uint64_t *second, uint32_t *nanosecon
 
 /*! @}*/
 
-#endif /* _FSL_ENET_H_ */
+#endif /* FSL_ENET_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_erm.c

@@ -65,9 +65,13 @@ void ERM_Init(ERM_Type *base)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     base->CR0 = 0x00U;
+#ifdef ERM_CR1_ENCIE8_MASK
     base->CR1 = 0x00U;
+#endif
     base->SR0 = 0xFFFFFFFFU;
+#ifdef ERM_SR1_SBC8_MASK
     base->SR1 = 0xFFFFFFFFU;
+#endif
 }
 
 /*!
@@ -86,66 +90,41 @@ uint32_t ERM_GetMemoryErrorAddr(ERM_Type *base, erm_memory_channel_t channel)
 {
     uint32_t absoluteErrorAddress = 0x00U;
 
-    switch (channel)
+    switch ((uint8_t)channel)
     {
-        case kERM_MemoryChannelRAMX:
-            /* Total RAMX size: 96KB
-                     RAMX0: 32KB(0x04000000 ~ 0x04007FFF)
-                     RAMX1: 32KB(0x04008000 ~ 0x0400FFFF)
-                     RAMX2: 32KB(0x04100000 ~ 0x04017FFF)
-             */
+        case 0U:
             absoluteErrorAddress = base->EAR0;
             break;
-
-        case kERM_MemoryChannelRAMA:
-            /* Total RAMA size: 32KB
-                     RAMA0: 8KB(0x20000000 ~ 0x20001FFF)
-                     RAMA1: 8KB(0x20002000 ~ 0x20003FFF)
-                     RAMA2: 8KB(0x20004000 ~ 0x20005FFF)
-                     RAMA3: 8KB(0x20006000 ~ 0x20007FFF)
-             */
+#ifdef ERM_EAR1_EAR_MASK
+        case 1U:
             absoluteErrorAddress = base->EAR1;
             break;
-
-        case kERM_MemoryChannelRAMB:
-            /* Total RAMB size: 32KB
-                     RAMB0: 32KB(0x20008000 ~ 0x2000FFFF)
-             */
+#endif
+#ifdef ERM_EAR2_EAR_MASK
+        case 2U:
             absoluteErrorAddress = base->EAR2;
             break;
-
-        case kERM_MemoryChannelRAMC:
-            /* Total RAMC size: 64KB
-                     RAMC0: 32KB(0x20010000 ~ 0x20017FFF)
-                     RAMC0: 32KB(0x20018000 ~ 0x2001FFFF)
-             */
+#endif
+#ifdef ERM_EAR3_EAR_MASK
+        case 3U:
             absoluteErrorAddress = base->EAR3;
             break;
-
-        case kERM_MemoryChannelRAMD:
-            /* Total RAMD size: 64KB
-                     RAMD0: 32KB(0x20020000 ~ 0x20027FFF)
-                     RAMD0: 32KB(0x20028000 ~ 0x2002FFFF)
-             */
+#endif
+#ifdef ERM_EAR4_EAR_MASK
+        case 4U:
             absoluteErrorAddress = base->EAR4;
             break;
-
-        case kERM_MemoryChannelRAME:
-            /* Total RAME size: 64KB
-                     RAME0: 32KB(0x20030000 ~ 0x20037FFF)
-                     RAME0: 32KB(0x20038000 ~ 0x2003FFFF)
-             */
+#endif
+#ifdef ERM_EAR5_EAR_MASK
+        case 5U:
             absoluteErrorAddress = base->EAR5;
             break;
-
-        case kERM_MemoryChannelRAMF:
-            /* Total RAMF size: 64KB
-                     RAMF0: 32KB(0x20040000 ~ 0x20047FFF)
-                     RAMF0: 32KB(0x20048000 ~ 0x2004FFFF)
-             */
+#endif
+#ifdef ERM_EAR6_EAR_MASK
+        case 6U:
             absoluteErrorAddress = base->EAR6;
             break;
-
+#endif
         default:
             assert(NULL);
             break;
@@ -158,48 +137,56 @@ uint32_t ERM_GetSyndrome(ERM_Type *base, erm_memory_channel_t channel)
 {
     uint32_t syndrome = 0x00U;
 
-    switch (channel)
+    switch ((uint8_t)channel)
     {
-        case kERM_MemoryChannelRAMX:
+        case 0U:
             syndrome = (base->SYN0 & ERM_SYN0_SYNDROME_MASK) >> ERM_SYN0_SYNDROME_SHIFT;
             break;
-
-        case kERM_MemoryChannelRAMA:
+#ifdef ERM_SYN1_SYNDROME_MASK
+        case 1U:
             syndrome = (base->SYN1 & ERM_SYN1_SYNDROME_MASK) >> ERM_SYN1_SYNDROME_SHIFT;
             break;
-
-        case kERM_MemoryChannelRAMB:
+#endif
+#ifdef ERM_SYN2_SYNDROME_MASK
+        case 2U:
             syndrome = (base->SYN2 & ERM_SYN2_SYNDROME_MASK) >> ERM_SYN2_SYNDROME_SHIFT;
             break;
-
-        case kERM_MemoryChannelRAMC:
+#endif
+#ifdef ERM_SYN3_SYNDROME_MASK
+        case 3U:
             syndrome = (base->SYN3 & ERM_SYN3_SYNDROME_MASK) >> ERM_SYN3_SYNDROME_SHIFT;
             break;
-
-        case kERM_MemoryChannelRAMD:
+#endif
+#ifdef ERM_SYN4_SYNDROME_MASK
+        case 4U:
             syndrome = (base->SYN4 & ERM_SYN4_SYNDROME_MASK) >> ERM_SYN4_SYNDROME_SHIFT;
             break;
-
-        case kERM_MemoryChannelRAME:
+#endif
+#ifdef ERM_SYN5_SYNDROME_MASK
+        case 5U:
             syndrome = (base->SYN5 & ERM_SYN5_SYNDROME_MASK) >> ERM_SYN5_SYNDROME_SHIFT;
             break;
-
-        case kERM_MemoryChannelRAMF:
+#endif
+#ifdef ERM_SYN6_SYNDROME_MASK
+        case 6U:
             syndrome = (base->SYN6 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN6_SYNDROME_SHIFT;
             break;
-
-        case kERM_MemoryChannelLPCACRAM:
-            assert(NULL);
+#endif
+#ifdef ERM_SYN7_SYNDROME_MASK
+        case 7U:
+            syndrome = (base->SYN7 & ERM_SYN6_SYNDROME_MASK) >> ERM_SYN7_SYNDROME_SHIFT;
             break;
-
-        case kERM_MemoryChannelPKCRAM:
+#endif
+#ifdef ERM_SYN8_SYNDROME_MASK
+        case 8U:
             syndrome = (base->SYN8 & ERM_SYN8_SYNDROME_MASK) >> ERM_SYN8_SYNDROME_SHIFT;
             break;
-
-        case kERM_MemoryChannelFLASH:
-            assert(NULL);
+#endif
+#ifdef ERM_SYN9_SYNDROME_MASK
+        case 8U:
+            syndrome = (base->SYN9 & ERM_SYN9_SYNDROME_MASK) >> ERM_SYN9_SYNDROME_SHIFT;
             break;
-
+#endif
         default:
             assert(NULL);
             break;
@@ -212,48 +199,56 @@ uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel)
 {
     uint32_t count = 0x00U;
 
-    switch (channel)
+    switch ((uint8_t)channel)
     {
-        case kERM_MemoryChannelRAMX:
+        case 0U:
             count = (base->CORR_ERR_CNT0 & ERM_CORR_ERR_CNT0_COUNT_MASK) >> ERM_CORR_ERR_CNT0_COUNT_SHIFT;
             break;
-
-        case kERM_MemoryChannelRAMA:
+#ifdef ERM_CORR_ERR_CNT1_COUNT_MASK
+        case 1U:
             count = (base->CORR_ERR_CNT1 & ERM_CORR_ERR_CNT1_COUNT_MASK) >> ERM_CORR_ERR_CNT1_COUNT_SHIFT;
             break;
-
-        case kERM_MemoryChannelRAMB:
+#endif
+#ifdef ERM_CORR_ERR_CNT2_COUNT_MASK
+        case 2U:
             count = (base->CORR_ERR_CNT2 & ERM_CORR_ERR_CNT2_COUNT_MASK) >> ERM_CORR_ERR_CNT2_COUNT_SHIFT;
             break;
-
-        case kERM_MemoryChannelRAMC:
+#endif
+#ifdef ERM_CORR_ERR_CNT3_COUNT_MASK
+        case 3U:
             count = (base->CORR_ERR_CNT3 & ERM_CORR_ERR_CNT3_COUNT_MASK) >> ERM_CORR_ERR_CNT3_COUNT_SHIFT;
             break;
-
-        case kERM_MemoryChannelRAMD:
+#endif
+#ifdef ERM_CORR_ERR_CNT4_COUNT_MASK
+        case 4U:
             count = (base->CORR_ERR_CNT4 & ERM_CORR_ERR_CNT4_COUNT_MASK) >> ERM_CORR_ERR_CNT4_COUNT_SHIFT;
             break;
-
-        case kERM_MemoryChannelRAME:
+#endif
+#ifdef ERM_CORR_ERR_CNT5_COUNT_MASK
+        case 5U:
             count = (base->CORR_ERR_CNT5 & ERM_CORR_ERR_CNT5_COUNT_MASK) >> ERM_CORR_ERR_CNT5_COUNT_SHIFT;
             break;
-
-        case kERM_MemoryChannelRAMF:
+#endif
+#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK
+        case 6U:
             count = (base->CORR_ERR_CNT6 & ERM_CORR_ERR_CNT6_COUNT_MASK) >> ERM_CORR_ERR_CNT6_COUNT_SHIFT;
             break;
-
-        case kERM_MemoryChannelLPCACRAM:
+#endif
+#ifdef ERM_CORR_ERR_CNT7_COUNT_MASK
+        case 7U:
             count = (base->CORR_ERR_CNT7 & ERM_CORR_ERR_CNT7_COUNT_MASK) >> ERM_CORR_ERR_CNT7_COUNT_SHIFT;
             break;
-
-        case kERM_MemoryChannelPKCRAM:
+#endif
+#ifdef ERM_CORR_ERR_CNT8_COUNT_MASK
+        case 8U:
             count = (base->CORR_ERR_CNT8 & ERM_CORR_ERR_CNT8_COUNT_MASK) >> ERM_CORR_ERR_CNT8_COUNT_SHIFT;
             break;
-
-        case kERM_MemoryChannelFLASH:
+#endif
+#ifdef ERM_CORR_ERR_CNT9_COUNT_MASK
+        case 9U:
             count = (base->CORR_ERR_CNT9 & ERM_CORR_ERR_CNT9_COUNT_MASK) >> ERM_CORR_ERR_CNT9_COUNT_SHIFT;
             break;
-
+#endif
         default:
             assert(NULL);
             break;
@@ -264,48 +259,57 @@ uint32_t ERM_GetErrorCount(ERM_Type *base, erm_memory_channel_t channel)
 
 void ERM_ResetErrorCount(ERM_Type *base, erm_memory_channel_t channel)
 {
-    switch (channel)
+    switch ((uint8_t)channel)
     {
-        case kERM_MemoryChannelRAMX:
+        case 0U:
             base->CORR_ERR_CNT0 = 0x00U;
             break;
 
-        case kERM_MemoryChannelRAMA:
+#ifdef ERM_CORR_ERR_CNT1_COUNT_MASK
+        case 1U:
             base->CORR_ERR_CNT1 = 0x00U;
             break;
-
-        case kERM_MemoryChannelRAMB:
+#endif
+#ifdef ERM_CORR_ERR_CNT2_COUNT_MASK
+        case 2U:
             base->CORR_ERR_CNT2 = 0x00U;
             break;
-
-        case kERM_MemoryChannelRAMC:
+#endif
+#ifdef ERM_CORR_ERR_CNT3_COUNT_MASK
+        case 3U:
             base->CORR_ERR_CNT3 = 0x00U;
             break;
-
-        case kERM_MemoryChannelRAMD:
+#endif
+#ifdef ERM_CORR_ERR_CNT4_COUNT_MASK
+        case 4U:
             base->CORR_ERR_CNT4 = 0x00U;
             break;
-
-        case kERM_MemoryChannelRAME:
+#endif
+#ifdef ERM_CORR_ERR_CNT5_COUNT_MASK
+        case 5U:
             base->CORR_ERR_CNT5 = 0x00U;
             break;
-
-        case kERM_MemoryChannelRAMF:
+#endif
+#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK
+        case 6U:
             base->CORR_ERR_CNT6 = 0x00U;
             break;
-
-        case kERM_MemoryChannelLPCACRAM:
+#endif
+#ifdef ERM_CORR_ERR_CNT6_COUNT_MASK
+        case 7U:
             base->CORR_ERR_CNT7 = 0x00U;
             break;
-
-        case kERM_MemoryChannelPKCRAM:
+#endif
+#ifdef ERM_CORR_ERR_CNT8_COUNT_MASK
+        case 8U:
             base->CORR_ERR_CNT8 = 0x00U;
             break;
-
-        case kERM_MemoryChannelFLASH:
+#endif
+#ifdef ERM_CORR_ERR_CNT9_COUNT_MASK
+        case 9U:
             base->CORR_ERR_CNT9 = 0x00U;
             break;
-
+#endif
         default:
             assert(NULL);
             break;

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_erm.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_ERM_H_
-#define _FSL_ERM_H_
+#ifndef FSL_ERM_H_
+#define FSL_ERM_H_
 
 #include "fsl_common.h"
 
@@ -21,10 +21,10 @@
  *****************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief Driver version. */
-#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
-/*@}*/
+#define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
+/*! @} */
 
 /*!
  * @brief ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable.
@@ -78,7 +78,7 @@ void ERM_Init(ERM_Type *base);
  */
 void ERM_Deinit(ERM_Type *base);
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Interrupt
@@ -101,12 +101,14 @@ static inline void ERM_EnableInterrupts(ERM_Type *base, erm_memory_channel_t cha
         base->CR0 =
             (temp & ~(0x0CUL << ((0x07U - (uint32_t)channel) * 4U))) | (mask << ((0x07U - (uint32_t)channel) * 4U));
     }
+#ifdef ERM_CR1_ESCIE8_MASK
     else
     {
         temp      = base->CR1;
         base->CR1 = (temp & ~(0x0CUL << ((0x07U + 0x08U - (uint32_t)channel) * 4U))) |
                     (mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U));
     }
+#endif
 }
 
 /*!
@@ -123,10 +125,12 @@ static inline void ERM_DisableInterrupts(ERM_Type *base, erm_memory_channel_t ch
     {
         base->CR0 &= ~(mask << ((0x07U - (uint32_t)channel) * 4U));
     }
+#ifdef ERM_CR1_ESCIE8_MASK
     else
     {
         base->CR1 &= ~(mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U));
     }
+#endif
 }
 
 /*!
@@ -141,10 +145,16 @@ static inline uint32_t ERM_GetInterruptStatus(ERM_Type *base, erm_memory_channel
     {
         return ((base->SR0 & (uint32_t)kERM_AllIntsFlag) >> (0x07U - (uint32_t)channel) * 4U);
     }
+#ifdef ERM_SR1_SBC8_MASK
     else
     {
         return ((base->SR1 & (uint32_t)kERM_AllIntsFlag) >> ((0x07U + 0x08U - (uint32_t)channel) * 4U));
     }
+#else
+    {
+        return 0;
+    }
+#endif
 }
 
 /*!
@@ -159,13 +169,15 @@ static inline void ERM_ClearInterruptStatus(ERM_Type *base, erm_memory_channel_t
     {
         base->SR0 = mask << ((0x07U - (uint32_t)channel) * 4U);
     }
+#ifdef ERM_SR1_SBC8_MASK
     else
     {
         base->SR1 = mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U);
     }
+#endif
 }
 
-/* @} */
+/*! @} */
 
 /*!
  * @name functional

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_evtg.h

@@ -5,8 +5,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_EVTG_H_
-#define _FSL_EVTG_H_
+#ifndef FSL_EVTG_H_
+#define FSL_EVTG_H_
 
 #include "fsl_common.h"
 
@@ -20,10 +20,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief EVTG driver version. */
 #define FSL_EVTG_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
-/*@}*/
+/*! @} */
 
 /*! @brief EVTG instance index. */
 typedef enum _evtg_index
@@ -247,7 +247,7 @@ static inline void EVTG_ForceFlipflopInitOutput(EVTG_Type *base,
                                                 evtg_index_t evtgIndex,
                                                 evtg_flipflop_init_output_t flipflopInitOutputValue)
 {
-    base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL &= (~EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK);
+    base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL &= (~(uint16_t)EVTG_EVTG_INST_EVTG_CTRL_FF_INIT_MASK);
     base->EVTG_INST[(uint8_t)evtgIndex].EVTG_CTRL |=
         EVTG_EVTG_INST_EVTG_CTRL_FF_INIT((uint16_t)flipflopInitOutputValue);
     /* INIT_EN bit should be set after FF_INIT is set. */
@@ -284,20 +284,20 @@ static inline void EVTG_SetProductTermInput(EVTG_Type *base,
         if ((productTerm == kEVTG_ProductTerm0) || (productTerm == kEVTG_ProductTerm1))
         {
             base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 &=
-                (~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
+                (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
             base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT01 |=
-                (((uint16_t)(((uint16_t)(input))
-                             << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) &
-                 (3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
+                ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U +
+                                          (((3U - (uint8_t)productTerm) % 2U) * 8U))) &
+                 (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
         }
         else
         {
             base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 &=
-                (~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
+                (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
             base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI0_BFT23 |=
-                (((uint16_t)(((uint16_t)(input))
-                             << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) &
-                 (3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
+                ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U +
+                                          (((3U - (uint8_t)productTerm) % 2U) * 8U))) &
+                 (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
         }
     }
     else if (kEVTG_AOI1 == aoiIndex)
@@ -305,20 +305,20 @@ static inline void EVTG_SetProductTermInput(EVTG_Type *base,
         if ((productTerm == kEVTG_ProductTerm0) || (productTerm == kEVTG_ProductTerm1))
         {
             base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 &=
-                (~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
+                (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
             base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT01 |=
-                (((uint16_t)(((uint16_t)(input))
-                             << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) &
-                 (3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
+                ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U +
+                                          (((3U - (uint8_t)productTerm) % 2U) * 8U))) &
+                 (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
         }
         else
         {
             base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 &=
-                (~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
+                (uint16_t)(~(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
             base->EVTG_INST[(uint8_t)evtgIndex].EVTG_AOI1_BFT23 |=
-                (((uint16_t)(((uint16_t)(input))
-                             << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U)))) &
-                 (3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
+                ((((uint16_t)(input)) << ((3U - ((uint8_t)inputIndex)) * 2U +
+                                          (((3U - (uint8_t)productTerm) % 2U) * 8U))) &
+                 (uint16_t)(3UL << ((3U - ((uint8_t)inputIndex)) * 2U + (((3U - (uint8_t)productTerm) % 2U) * 8U))));
         }
     }
     else
@@ -352,4 +352,4 @@ void EVTG_ConfigAOIProductTerm(EVTG_Type *base,
 
 /*! @} */
 
-#endif /* _FSL_EVTG_H_ */
+#endif /* FSL_EVTG_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_ewm.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_EWM_H_
-#define _FSL_EWM_H_
+#ifndef FSL_EWM_H_
+#define FSL_EWM_H_
 
 #include "fsl_common.h"
 
@@ -20,10 +20,10 @@
  *******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief EWM driver version 2.0.3. */
 #define FSL_EWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
-/*@}*/
+/*! @} */
 
 /*! @brief Describes EWM clock source. */
 #if defined(FSL_FEATURE_EWM_HAS_CLOCK_SELECT) && FSL_FEATURE_EWM_HAS_CLOCK_SELECT
@@ -141,7 +141,7 @@ void EWM_Deinit(EWM_Type *base);
  */
 void EWM_GetDefaultConfig(ewm_config_t *config);
 
-/* @} */
+/*! @} */
 
 /*!
  * @name EWM functional Operation
@@ -207,7 +207,7 @@ static inline uint32_t EWM_GetStatusFlags(EWM_Type *base)
  */
 void EWM_Refresh(EWM_Type *base);
 
-/*@}*/
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -215,4 +215,4 @@ void EWM_Refresh(EWM_Type *base);
 
 /*! @}*/
 
-#endif /* _FSL_EWM_H_ */
+#endif /* FSL_EWM_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan.h

@@ -1,12 +1,12 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2022 NXP
+ * Copyright 2016-2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_FLEXCAN_H_
-#define _FSL_FLEXCAN_H_
+#ifndef FSL_FLEXCAN_H_
+#define FSL_FLEXCAN_H_
 
 #include "fsl_common.h"
 
@@ -20,10 +20,10 @@
  *****************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief FlexCAN driver version. */
-#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 9, 2))
-/*@}*/
+#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 11, 6))
+/*! @} */
 
 #if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT)
 /* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert.  */
@@ -231,7 +231,7 @@
 #endif
 /*! @brief FlexCAN Enhanced Rx FIFO base address helper macro. */
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
-#define E_RX_FIFO(base) ((uint32_t)(base) + 0x2000U)
+#define E_RX_FIFO(base) ((uintptr_t)(base) + 0x2000U)
 #else
 #define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG (0U)
 #endif
@@ -339,7 +339,7 @@ enum _flexcan_fd_frame_length
     kFLEXCAN_12BperFrame,       /*!< Frame contains 12 valid data bytes. */
     kFLEXCAN_16BperFrame,       /*!< Frame contains 16 valid data bytes. */
     kFLEXCAN_20BperFrame,       /*!< Frame contains 20 valid data bytes. */
-    kFLEXCAN_24Bperrame,        /*!< Frame contains 24 valid data bytes. */
+    kFLEXCAN_24BperFrame,       /*!< Frame contains 24 valid data bytes. */
     kFLEXCAN_32BperFrame,       /*!< Frame contains 32 valid data bytes. */
     kFLEXCAN_48BperFrame,       /*!< Frame contains 48 valid data bytes. */
     kFLEXCAN_64BperFrame,       /*!< Frame contains 64 valid data bytes. */
@@ -1025,6 +1025,22 @@ extern "C" {
  * @{
  */
 
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+/*!
+ * @brief Determine whether the FlexCAN instance support CAN FD mode at run time.
+ *
+ * @note Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part
+ *      name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not.
+ *      If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be
+ *      executed first, and then call this API and use the return to value determines whether to supports CAN FD mode,
+ *      if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @return return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode.
+ */
+bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base);
+#endif
+
 /*!
  * @brief Enter FlexCAN Freeze Mode.
  *
@@ -1185,7 +1201,7 @@ void FLEXCAN_Deinit(CAN_Type *base);
  */
 void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig);
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Configuration.
@@ -1394,7 +1410,7 @@ void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_f
  */
 void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig);
 #endif
-/* @} */
+/*! @} */
 
 /*!
  * @name Status
@@ -1518,6 +1534,29 @@ static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask)
 #endif
 }
 
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
+/*!
+ * @brief Gets the FlexCAN High 64 Message Buffer interrupt flags.
+ *
+ * Valid only if the number of available MBs exceeds 64.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param mask The ORed FlexCAN Message Buffer mask.
+ * @return The status of given Message Buffers.
+ */
+static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)
+{
+    uint64_t tempflag = 0U;
+#if defined(CAN_IFLAG3_BUF95TO64_MASK)
+    tempflag |= (uint64_t)base->IFLAG3;
+#endif
+#if defined(CAN_IFLAG4_BUF127TO96_MASK)
+    tempflag |= (uint64_t)base->IFLAG4;
+#endif
+    return (tempflag & mask);
+}
+#endif
+
 /*!
  * @brief Clears the FlexCAN Message Buffer interrupt flags.
  *
@@ -1540,6 +1579,26 @@ static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask)
 #endif
 }
 
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
+/*!
+ * @brief Clears the FlexCAN High 64 Message Buffer interrupt flags.
+ *
+ * Valid only if the number of available MBs exceeds 64.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param mask The ORed FlexCAN Message Buffer mask.
+ */
+static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)
+{
+#if defined(CAN_IFLAG3_BUF95TO64_MASK)
+    base->IFLAG3 = (uint32_t)(mask & 0xFFFFFFFFU);
+#endif
+#if defined(CAN_IFLAG4_BUF127TO96_MASK)
+    base->IFLAG4 = (uint32_t)(mask >> 32U);
+#endif
+}
+#endif
+
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
 /*!
  * @brief Gets the FlexCAN Memory Error Report registers status.
@@ -1582,7 +1641,7 @@ static inline uint32_t FLEXCAN_GetEnhancedFifoDataCount(CAN_Type *base)
     return (base->ERFSR & CAN_ERFSR_ERFEL_MASK);
 }
 #endif
-/* @} */
+/*! @} */
 
 /*!
  * @name Interrupts
@@ -1606,6 +1665,8 @@ static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask)
 static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
 #endif
 {
+    uint32_t primask = DisableGlobalIRQ();
+
     /* Solve Self Wake Up interrupt. */
     base->MCR |= (uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable);
 
@@ -1636,6 +1697,8 @@ static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
     base->CTRL1 |=
         (uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
                            (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
+
+    EnableGlobalIRQ(primask);
 }
 
 /*!
@@ -1654,6 +1717,8 @@ static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask)
 static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
 #endif
 {
+    uint32_t primask = DisableGlobalIRQ();
+
     /* Solve Wake Up Interrupt. */
     base->MCR &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable);
 
@@ -1684,6 +1749,8 @@ static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
     base->CTRL1 &=
         ~(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
                             (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
+
+    EnableGlobalIRQ(primask);
 }
 
 /*!
@@ -1700,13 +1767,39 @@ static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask)
 static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask)
 #endif
 {
+    uint32_t primask = DisableGlobalIRQ();
+
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
     base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU);
     base->IMASK2 |= (uint32_t)(mask >> 32);
 #else
     base->IMASK1 |= mask;
 #endif
+    EnableGlobalIRQ(primask);
+}
+
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
+/*!
+ * @brief Enables FlexCAN high 64 Message Buffer interrupts.
+ *
+ * Valid only if the number of available MBs exceeds 64.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param mask The ORed FlexCAN Message Buffer mask.
+ */
+static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)
+{
+    uint32_t primask = DisableGlobalIRQ();
+
+#if defined(CAN_IMASK3_BUF95TO64M_MASK)
+    base->IMASK3 |= (uint32_t)(mask & 0xFFFFFFFFU);
+#endif
+#if defined(CAN_IMASK4_BUF127TO96_MASK)
+    base->IMASK4 |= (uint32_t)(mask >> 32U);
+#endif
+    EnableGlobalIRQ(primask);
 }
+#endif
 
 /*!
  * @brief Disables FlexCAN Message Buffer interrupts.
@@ -1722,15 +1815,41 @@ static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask)
 static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask)
 #endif
 {
+    uint32_t primask = DisableGlobalIRQ();
+
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
     base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU));
     base->IMASK2 &= ~((uint32_t)(mask >> 32));
 #else
     base->IMASK1 &= ~mask;
 #endif
+    EnableGlobalIRQ(primask);
+}
+
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
+/*!
+ * @brief Disables FlexCAN high 64 Message Buffer interrupts.
+ *
+ * Valid only if the number of available MBs exceeds 64.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param mask The ORed FlexCAN Message Buffer mask.
+ */
+static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)
+{
+    uint32_t primask = DisableGlobalIRQ();
+
+#if defined(CAN_IMASK3_BUF95TO64M_MASK)
+    base->IMASK3 &= ~((uint32_t)(mask & 0xFFFFFFFFU));
+#endif
+#if defined(CAN_IMASK4_BUF127TO96_MASK)
+    base->IMASK4 &= ~((uint32_t)(mask >> 32U));
+#endif
+    EnableGlobalIRQ(primask);
 }
+#endif
 
-/* @} */
+/*! @} */
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA)
 /*!
@@ -1761,7 +1880,7 @@ static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)
     return (uintptr_t) & (base->MB[0].CS);
 }
 
-/* @} */
+/*! @} */
 #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */
 
 /*!
@@ -1907,7 +2026,7 @@ status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame
  */
 status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame);
 #endif
-/* @} */
+/*! @} */
 
 /*!
  * @name Transactional
@@ -2230,7 +2349,7 @@ void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *
  */
 void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle);
 
-/* @} */
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -2238,4 +2357,4 @@ void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle);
 
 /*! @}*/
 
-#endif /* _FSL_FLEXCAN_H_ */
+#endif /* FSL_FLEXCAN_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan_edma.c

@@ -0,0 +1,381 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexcan_edma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcan_edma"
+#endif
+
+/*<! Structure definition for flexcan_edma_private_handle_t. The structure is private. */
+typedef struct _flexcan_edma_private_handle
+{
+    CAN_Type *base;
+    flexcan_edma_handle_t *handle;
+} flexcan_edma_private_handle_t;
+
+/* FlexCAN EDMA transfer handle. */
+enum _flexcan_edma_tansfer_state
+{
+    KFLEXCAN_RxFifoIdle = 0U, /* Rx Fifo idle. */
+    KFLEXCAN_RxFifoBusy = 1U, /* Rx Fifo busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* Array of FlexCAN peripheral base address. */
+static CAN_Type *const s_flexcanBases[] = CAN_BASE_PTRS;
+
+/* Private handle only used for internally. */
+static flexcan_edma_private_handle_t s_flexcanEdmaPrivateHandle[ARRAY_SIZE(s_flexcanBases)];
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief FlexCAN EDMA receive finished callback function.
+ *
+ * This function is called when FlexCAN Rx FIFO EDMA receive finished.
+ * It disables the FlexCAN Rx FIFO EDMA request and sends
+ * @ref kStatus_FLEXCAN_RxFifoIdle to FlexCAN EDMA callback.
+ *
+ * @param handle The EDMA handle.
+ * @param param Callback function parameter.
+ */
+static void FLEXCAN_ReceiveFifoEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void FLEXCAN_ReceiveFifoEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds)
+{
+    handle = handle;
+    tcds   = tcds;
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
+    flexcan_fd_frame_t *framefd;
+    uint32_t idHitIndex;
+#endif
+    flexcan_edma_private_handle_t *flexcanPrivateHandle = (flexcan_edma_private_handle_t *)param;
+
+    /*
+     * $Branch Coverage Justification$
+     * (!transferDone) not covered. Unable to simulate DMA transfer error.
+     */
+    if (transferDone)
+    {
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
+        if (0U != (flexcanPrivateHandle->base->ERFCR & CAN_ERFCR_ERFEN_MASK))
+        {
+            framefd = flexcanPrivateHandle->handle->framefd;
+            for (uint32_t i = 0; i < flexcanPrivateHandle->handle->frameNum; i++)
+            {
+                /* Enhanced Rx FIFO ID HIT offset is changed dynamically according to data length code (DLC) . */
+                idHitIndex     = (DLC_LENGTH_DECODE(framefd->length) + 3U) / 4U;
+                framefd->idhit = framefd->dataWord[idHitIndex];
+                /* Clear the unused frame data. */
+                for (uint32_t j = idHitIndex; j < 16U; j++)
+                {
+                    framefd->dataWord[j] = 0x0U;
+                }
+                framefd++;
+            }
+        }
+#endif
+        /* Disable transfer. */
+        FLEXCAN_TransferAbortReceiveFifoEDMA(flexcanPrivateHandle->base, flexcanPrivateHandle->handle);
+
+        if (NULL != flexcanPrivateHandle->handle->callback)
+        {
+            flexcanPrivateHandle->handle->callback(flexcanPrivateHandle->base, flexcanPrivateHandle->handle,
+                                                   kStatus_FLEXCAN_RxFifoIdle, flexcanPrivateHandle->handle->userData);
+        }
+    }
+}
+
+/*!
+ * brief Initializes the FlexCAN handle, which is used in transactional functions.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle Pointer to flexcan_edma_handle_t structure.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ * param rxFifoEdmaHandle User-requested DMA handle for Rx FIFO DMA transfer.
+ */
+void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base,
+                                      flexcan_edma_handle_t *handle,
+                                      flexcan_edma_transfer_callback_t callback,
+                                      void *userData,
+                                      edma_handle_t *rxFifoEdmaHandle)
+{
+    assert(NULL != handle);
+
+    uint32_t instance                           = FLEXCAN_GetInstance(base);
+    s_flexcanEdmaPrivateHandle[instance].base   = base;
+    s_flexcanEdmaPrivateHandle[instance].handle = handle;
+
+    (void)memset(handle, 0, sizeof(flexcan_edma_handle_t));
+
+    handle->rxFifoState      = (uint8_t)KFLEXCAN_RxFifoIdle;
+    handle->rxFifoEdmaHandle = rxFifoEdmaHandle;
+
+    /* Register Callback. */
+    handle->callback = callback;
+    handle->userData = userData;
+
+    /* Configure Legacy/Enhanced Rx FIFO DMA callback. */
+    EDMA_SetCallback(handle->rxFifoEdmaHandle, FLEXCAN_ReceiveFifoEDMACallback, &s_flexcanEdmaPrivateHandle[instance]);
+}
+
+/*!
+ * brief Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO.
+ *
+ * This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO.
+ *
+ * param base FlexCAN peripheral base address.
+ * param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
+ * param pEdmaConfig The user configuration structure of type edma_transfer_t.
+ *
+ */
+void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base,
+                                        flexcan_fifo_transfer_t *pFifoXfer,
+                                        edma_transfer_config_t *pEdmaConfig)
+{
+    assert(NULL != pFifoXfer);
+    assert(NULL != pFifoXfer->frame);
+    assert(NULL != pEdmaConfig);
+
+    flexcan_frame_t *fifoAddr = (flexcan_frame_t *)FLEXCAN_GetRxFifoHeadAddr(base);
+
+#if (defined(FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER) && FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER)
+    EDMA_PrepareTransfer(pEdmaConfig, (void *)fifoAddr, sizeof(flexcan_frame_t), (void *)pFifoXfer->frame,
+                         sizeof(uint32_t), sizeof(flexcan_frame_t), sizeof(flexcan_frame_t) * pFifoXfer->frameNum,
+                         kEDMA_PeripheralToMemory);
+#else
+    /* The Data Size of FLEXCAN Legacy RX FIFO output port is 16 Bytes, but lots of chips not support 16Bytes width DMA
+     * transfer. These chips always support 4Byte width memory transfer, so we need prepare Memory to Memory mode by 4
+     * Bytes width mode.
+     */
+    EDMA_PrepareTransfer(pEdmaConfig, (void *)fifoAddr, 4U, (void *)pFifoXfer->frame, sizeof(uint32_t),
+                         sizeof(flexcan_frame_t), sizeof(flexcan_frame_t) * pFifoXfer->frameNum, kEDMA_MemoryToMemory);
+#endif
+}
+
+/*!
+ * brief Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA.
+ *
+ * This function to Update edma transfer confiugration and Start eDMA transfer
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle Pointer to flexcan_edma_handle_t structure.
+ * param pEdmaConfig The user configuration structure of type edma_transfer_t.
+ * retval kStatus_Success if succeed, others failed.
+ * retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
+ */
+status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base,
+                                             flexcan_edma_handle_t *handle,
+                                             edma_transfer_config_t *pEdmaConfig)
+{
+    assert(NULL != handle->rxFifoEdmaHandle);
+    assert(NULL != pEdmaConfig);
+    status_t status;
+
+    /* If previous Rx FIFO receive not finished. */
+    if ((uint8_t)KFLEXCAN_RxFifoBusy == handle->rxFifoState)
+    {
+        status = kStatus_FLEXCAN_RxFifoBusy;
+    }
+    else
+    {
+        handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoBusy;
+
+        /* Enable FlexCAN Rx FIFO EDMA. */
+        FLEXCAN_EnableRxFifoDMA(base, true);
+
+        /* Submit configuration. */
+        (void)EDMA_SubmitTransfer(handle->rxFifoEdmaHandle, (const edma_transfer_config_t *)pEdmaConfig);
+        EDMA_SetModulo(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, kEDMA_Modulo16bytes,
+                       kEDMA_ModuloDisable);
+        /* Start transfer. */
+        EDMA_StartTransfer(handle->rxFifoEdmaHandle);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+
+/*!
+ * brief Receives the CAN Messages from the Legacy Rx FIFO using eDMA.
+ *
+ * This function receives the CAN Message using eDMA. This is a non-blocking function, which returns
+ * right away. After the CAN Message is received, the receive callback function is called.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle Pointer to flexcan_edma_handle_t structure.
+ * param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
+ * retval kStatus_Success if succeed, others failed.
+ * retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
+ */
+status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base,
+                                         flexcan_edma_handle_t *handle,
+                                         flexcan_fifo_transfer_t *pFifoXfer)
+{
+    assert(NULL != handle->rxFifoEdmaHandle);
+    assert(NULL != pFifoXfer->frame);
+
+    edma_transfer_config_t dmaXferConfig = {0};
+    status_t status;
+
+    handle->frameNum = pFifoXfer->frameNum;
+    /* Prepare transfer. */
+    FLEXCAN_PrepareTransfConfiguration(base, pFifoXfer, &dmaXferConfig);
+
+    /* Submit configuration and start edma transfer. */
+    status = FLEXCAN_StartTransferDatafromRxFIFO(base, handle, &dmaXferConfig);
+
+    return status;
+}
+
+/*!
+ * brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle FlexCAN handle pointer.
+ * param count Number of CAN messages receive so far by the non-blocking transaction.
+ * retval kStatus_InvalidArgument count is Invalid.
+ * retval kStatus_Success Successfully return the count.
+ */
+
+status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count)
+{
+    assert(NULL != handle);
+
+    status_t result = kStatus_Success;
+
+    if (handle->rxFifoState == (uint32_t)KFLEXCAN_RxFifoIdle)
+    {
+        result = kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->frameNum -
+                 EDMA_GetRemainingMajorLoopCount(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel);
+    }
+
+    return result;
+}
+
+/*!
+ * brief Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.
+ *
+ * This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle Pointer to flexcan_edma_handle_t structure.
+ */
+void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle)
+{
+    assert(NULL != handle->rxFifoEdmaHandle);
+
+    /* Stop transfer. */
+    EDMA_AbortTransfer(handle->rxFifoEdmaHandle);
+
+    handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoIdle;
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
+    handle->framefd = NULL;
+#endif
+    handle->frameNum = 0U;
+    /* Disable FlexCAN Legacy/Enhanced Rx FIFO EDMA. */
+    FLEXCAN_EnableRxFifoDMA(base, false);
+}
+
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
+/*!
+ * brief Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA.
+ *
+ * This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns
+ * right away. After the CAN Message is received, the receive callback function is called.
+ *
+ * param base FlexCAN peripheral base address.
+ * param handle Pointer to flexcan_edma_handle_t structure.
+ * param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
+ * retval kStatus_Success if succeed, others failed.
+ * retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
+ * retval kStatus_InvalidArgument  The watermark configuration is invalid, the watermark need be set to
+                                    1 to do successfully EDMA transfer with this API.
+ */
+status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base,
+                                                 flexcan_edma_handle_t *handle,
+                                                 flexcan_fifo_transfer_t *pFifoXfer)
+{
+    assert(NULL != handle->rxFifoEdmaHandle);
+    assert(NULL != pFifoXfer->framefd);
+
+    edma_transfer_config_t dmaXferConfig;
+    edma_minor_offset_config_t dmaMinorOffsetConfig;
+    status_t status;
+    flexcan_fd_frame_t *fifoAddr = (flexcan_fd_frame_t *)E_RX_FIFO(base);
+    uint32_t perReadWords        = ((base->ERFCR & CAN_ERFCR_DMALW_MASK) >> CAN_ERFCR_DMALW_SHIFT) + 1U;
+    uint32_t watermark           = ((base->ERFCR & CAN_ERFCR_ERFWM_MASK) >> CAN_ERFCR_ERFWM_SHIFT) + 1U;
+
+    /* If previous Rx FIFO receive not finished. */
+    if ((uint8_t)KFLEXCAN_RxFifoBusy == handle->rxFifoState)
+    {
+        status = kStatus_FLEXCAN_RxFifoBusy;
+    }
+    else
+    {
+        handle->frameNum = pFifoXfer->frameNum;
+        handle->framefd  = pFifoXfer->framefd;
+        /*!< To reduce the complexity of DMA software configuration, need to set watermark to 1 to make that each DMA
+           request read once Rx FIFO. Because a DMA transfer cannot be dynamically changed, Number of words read per
+           transfer (ERFCR[DMALW] + 1) should be programmed so that the Enhanced Rx FIFO element can store the largest
+           CAN message present on the CAN bus. */
+        if ((watermark != 1U) || ((sizeof(uint32_t) * perReadWords) != sizeof(flexcan_fd_frame_t)))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        /* Prepare transfer. */
+        EDMA_PrepareTransfer(
+            &dmaXferConfig, (void *)fifoAddr, sizeof(uint32_t), (void *)pFifoXfer->framefd, sizeof(uint32_t),
+            sizeof(uint32_t) * perReadWords,                    /* minor loop bytes : 4* perReadWords */
+            sizeof(uint32_t) * perReadWords * handle->frameNum, /* major loop counts : handle->frameNum */
+            kEDMA_MemoryToMemory);
+        /* Submit configuration. */
+        (void)EDMA_SubmitTransfer(handle->rxFifoEdmaHandle, &dmaXferConfig);
+
+        dmaMinorOffsetConfig.enableDestMinorOffset = false;
+        dmaMinorOffsetConfig.enableSrcMinorOffset  = true;
+        dmaMinorOffsetConfig.minorOffset           = 128U - sizeof(uint32_t) * perReadWords;
+        EDMA_SetMinorOffsetConfig(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel,
+                                  &dmaMinorOffsetConfig);
+
+        EDMA_SetModulo(handle->rxFifoEdmaHandle->base, handle->rxFifoEdmaHandle->channel, kEDMA_Modulo128bytes,
+                       kEDMA_ModuloDisable);
+
+        handle->rxFifoState = (uint8_t)KFLEXCAN_RxFifoBusy;
+
+        /* Enable FlexCAN Rx FIFO EDMA. */
+        FLEXCAN_EnableRxFifoDMA(base, true);
+        /* Start transfer. */
+        EDMA_StartTransfer(handle->rxFifoEdmaHandle);
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+#endif

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexcan_edma.h

@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_FLEXCAN_EDMA_H_
+#define FSL_FLEXCAN_EDMA_H_
+
+#include "fsl_flexcan.h"
+#include "fsl_edma.h"
+
+/*!
+ * @addtogroup flexcan_edma_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief FlexCAN EDMA driver version. */
+#define FSL_FLEXCAN_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 11, 3))
+/*! @} */
+
+/* Forward declaration of the handle typedef. */
+typedef struct _flexcan_edma_handle flexcan_edma_handle_t;
+
+/*! @brief FlexCAN transfer callback function. */
+typedef void (*flexcan_edma_transfer_callback_t)(CAN_Type *base,
+                                                 flexcan_edma_handle_t *handle,
+                                                 status_t status,
+                                                 void *userData);
+
+/*!
+ * @brief FlexCAN eDMA handle
+ */
+struct _flexcan_edma_handle
+{
+    flexcan_edma_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                            /*!< FlexCAN callback function parameter.*/
+    edma_handle_t *rxFifoEdmaHandle;           /*!< The EDMA handler for Rx FIFO. */
+    volatile uint8_t rxFifoState;              /*!< Rx FIFO transfer state. */
+    size_t frameNum;                           /*!< The number of messages that need to be received. */
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
+    flexcan_fd_frame_t *framefd; /*!< Point to the buffer of CAN Message to be received from Enhanced Rx FIFO. */
+#endif
+};
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name eDMA transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FlexCAN handle, which is used in transactional functions.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param handle Pointer to flexcan_edma_handle_t structure.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ * @param rxFifoEdmaHandle User-requested DMA handle for Rx FIFO DMA transfer.
+ */
+void FLEXCAN_TransferCreateHandleEDMA(CAN_Type *base,
+                                      flexcan_edma_handle_t *handle,
+                                      flexcan_edma_transfer_callback_t callback,
+                                      void *userData,
+                                      edma_handle_t *rxFifoEdmaHandle);
+
+/*!
+ * @brief Prepares the eDMA transfer configuration for FLEXCAN Legacy RX FIFO.
+ *
+ * This function prepares the eDMA transfer configuration structure according to FLEXCAN Legacy RX FIFO.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
+ * @param pEdmaConfig The user configuration structure of type edma_transfer_t.
+ *
+ */
+void FLEXCAN_PrepareTransfConfiguration(CAN_Type *base,
+                                        flexcan_fifo_transfer_t *pFifoXfer,
+                                        edma_transfer_config_t *pEdmaConfig);
+
+/*!
+ * @brief Start Transfer Data from the FLEXCAN Legacy Rx FIFO using eDMA.
+ *
+ * This function to Update edma transfer confiugration and Start eDMA transfer
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param handle Pointer to flexcan_edma_handle_t structure.
+ * @param pEdmaConfig The user configuration structure of type edma_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
+ */
+status_t FLEXCAN_StartTransferDatafromRxFIFO(CAN_Type *base,
+                                             flexcan_edma_handle_t *handle,
+                                             edma_transfer_config_t *pEdmaConfig);
+
+/*!
+ * @brief Receives the CAN Message from the Legacy Rx FIFO using eDMA.
+ *
+ * This function receives the CAN Message using eDMA. This is a non-blocking function, which returns
+ * right away. After the CAN Message is received, the receive callback function is called.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param handle Pointer to flexcan_edma_handle_t structure.
+ * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
+ */
+status_t FLEXCAN_TransferReceiveFifoEDMA(CAN_Type *base,
+                                         flexcan_edma_handle_t *handle,
+                                         flexcan_fifo_transfer_t *pFifoXfer);
+/*!
+ * @brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param handle FlexCAN handle pointer.
+ * @param count Number of CAN messages receive so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+
+status_t FLEXCAN_TransferGetReceiveFifoCountEMDA(CAN_Type *base, flexcan_edma_handle_t *handle, size_t *count);
+/*!
+ * @brief Aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.
+ *
+ * This function aborts the receive Legacy/Enhanced Rx FIFO process which used eDMA.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param handle Pointer to flexcan_edma_handle_t structure.
+ */
+void FLEXCAN_TransferAbortReceiveFifoEDMA(CAN_Type *base, flexcan_edma_handle_t *handle);
+
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
+/*!
+ * @brief Receives the CAN FD Message from the Enhanced Rx FIFO using eDMA.
+ *
+ * This function receives the CAN FD Message using eDMA. This is a non-blocking function, which returns
+ * right away. After the CAN Message is received, the receive callback function is called.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param handle Pointer to flexcan_edma_handle_t structure.
+ * @param pFifoXfer FlexCAN Rx FIFO EDMA transfer structure, see #flexcan_fifo_transfer_t.
+ * @retval kStatus_Success if succeed, others failed.
+ * @retval kStatus_FLEXCAN_RxFifoBusy Previous transfer ongoing.
+ */
+status_t FLEXCAN_TransferReceiveEnhancedFifoEDMA(CAN_Type *base,
+                                                 flexcan_edma_handle_t *handle,
+                                                 flexcan_fifo_transfer_t *pFifoXfer);
+/*!
+ * @brief Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param handle FlexCAN handle pointer.
+ * @param count Number of CAN messages receive so far by the non-blocking transaction.
+ * @retval kStatus_InvalidArgument count is Invalid.
+ * @retval kStatus_Success Successfully return the count.
+ */
+
+static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCountEMDA(CAN_Type *base,
+                                                                       flexcan_edma_handle_t *handle,
+                                                                       size_t *count)
+{
+    return FLEXCAN_TransferGetReceiveFifoCountEMDA(base, handle, count);
+}
+#endif
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FLEXCAN_EDMA_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio.c

@@ -20,6 +20,12 @@
 /*< @brief user configurable flexio handle count. */
 #define FLEXIO_HANDLE_COUNT 2
 
+#if defined(FLEXIO_RSTS)
+#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS
+#elif defined(FLEXIO_RSTS_N)
+#define FLEXIO_RESETS_ARRAY FLEXIO_RSTS_N
+#endif
+
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -43,6 +49,11 @@ static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT];
 /* FlexIO common IRQ Handler. */
 static void FLEXIO_CommonIRQHandler(void);
 
+#if defined(FLEXIO_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_flexioResets[] = FLEXIO_RESETS_ARRAY;
+#endif
+
 /*******************************************************************************
  * Codes
  ******************************************************************************/
@@ -96,6 +107,10 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig)
     CLOCK_EnableClock(s_flexioClocks[FLEXIO_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
+#if defined(FLEXIO_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_flexioResets[FLEXIO_GetInstance(base)]);
+#endif
+
     FLEXIO_Reset(base);
 
     ctrlReg = base->CTRL;
@@ -396,6 +411,69 @@ static void FLEXIO_CommonIRQHandler(void)
     SDK_ISR_EXIT_BARRIER;
 }
 
+#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER
+/*!
+ * brief Configure a FLEXIO pin used by the board.
+ *
+ * To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file.
+ * Then, call the FLEXIO_SetPinConfig() function.
+ *
+ * This is an example to define an input pin or an output pin configuration.
+ * code
+ * Define a digital input pin configuration,
+ * flexio_gpio_config_t config =
+ * {
+ *   kFLEXIO_DigitalInput,
+ *   0U,
+ *   kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable,
+ * }
+ * Define a digital output pin configuration,
+ * flexio_gpio_config_t config =
+ * {
+ *   kFLEXIO_DigitalOutput,
+ *   0U,
+ *   0U
+ * }
+ * endcode
+ * param base   FlexIO peripheral base address
+ * param pin    FLEXIO pin number.
+ * param config FLEXIO pin configuration pointer.
+ */
+void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config)
+{
+    assert(NULL != config);
+    IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
+
+    if (config->pinDirection == kFLEXIO_DigitalInput)
+    {
+        base->PINOUTE &= ~(1UL << pin);
+        if (0U != (config->inputConfig & (uint8_t)kFLEXIO_InputInterruptEnable))
+        {
+            base->PINIEN = 1UL << pin;
+            /* Clear pending NVIC IRQ before enable NVIC IRQ. */
+            NVIC_ClearPendingIRQ(flexio_irqs[FLEXIO_GetInstance(base)]);
+            /* Enable interrupt in NVIC. */
+            (void)EnableIRQ(flexio_irqs[FLEXIO_GetInstance(base)]);
+        }
+        
+        if (0U != (config->inputConfig & (uint8_t)kFLEXIO_FlagRisingEdgeEnable))
+        {
+            base->PINREN = 1UL << pin;
+        }
+        
+        if (0U != (config->inputConfig & (uint8_t)kFLEXIO_FlagFallingEdgeEnable))
+        {
+            base->PINFEN = 1UL << pin;
+        }
+    }
+    else
+    {
+        FLEXIO_EnablePinOutput(base, pin);
+        FLEXIO_PinWrite(base, pin, config->outputLogic);
+    }
+}
+#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/
+
 void FLEXIO_DriverIRQHandler(void);
 void FLEXIO_DriverIRQHandler(void)
 {

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_FLEXIO_H_
-#define _FSL_FLEXIO_H_
+#ifndef FSL_FLEXIO_H_
+#define FSL_FLEXIO_H_
 
 #include "fsl_common.h"
 
@@ -20,10 +20,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief FlexIO driver version. */
-#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
-/*@}*/
+#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
+/*! @} */
 
 /*! @brief Calculate FlexIO timer trigger.*/
 #define FLEXIO_TIMER_TRIGGER_SEL_PININPUT(x)   ((uint32_t)(x) << 1U)
@@ -294,6 +294,38 @@ typedef struct _flexio_shifter_config
     flexio_shifter_start_bit_t shifterStart;   /*!< Shifter START bit. */
 } flexio_shifter_config_t;
 
+#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER
+/*! @brief FLEXIO gpio direction definition */
+typedef enum _flexio_gpio_direction
+{
+    kFLEXIO_DigitalInput  = 0U, /*!< Set current pin as digital input*/
+    kFLEXIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} flexio_gpio_direction_t;
+
+/*! @brief FLEXIO gpio input config */
+typedef enum _flexio_pin_input_config
+{
+    kFLEXIO_InputInterruptDisabled = 0x0U, /*!< Interrupt request is disabled. */
+    kFLEXIO_InputInterruptEnable   = 0x1U, /*!< Interrupt request is enable. */
+    kFLEXIO_FlagRisingEdgeEnable   = 0x2U, /*!< Input pin flag on rising edge. */
+    kFLEXIO_FlagFallingEdgeEnable  = 0x4U, /*!< Input pin flag on falling edge. */
+} flexio_pin_input_config_t;
+
+/*!
+ * @brief The FLEXIO pin configuration structure.
+ *
+ * Each pin can only be configured as either an output pin or an input pin at a time.
+ * If configured as an input pin, use inputConfig param.
+ * If configured as an output pin, use outputLogic.
+ */
+typedef struct _flexio_gpio_config
+{
+    flexio_gpio_direction_t pinDirection; /*!< FLEXIO pin direction, input or output */
+    uint8_t outputLogic;                  /*!< Set a default output logic, which has no use in input */
+    uint8_t inputConfig;                  /*!< Set an input config */
+} flexio_gpio_config_t;
+#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/
+
 /*! @brief typedef for FlexIO simulated driver interrupt handler.*/
 typedef void (*flexio_isr_t)(void *base, void *handle);
 
@@ -370,7 +402,7 @@ void FLEXIO_Deinit(FLEXIO_Type *base);
  */
 uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
 
-/* @} */
+/*! @} */
 
 /*!
  * @name FlexIO Basic Operation
@@ -490,6 +522,7 @@ void FLEXIO_SetTimerConfig(FLEXIO_Type *base, uint8_t index, const flexio_timer_
  * @brief This function set the value of the prescaler on flexio channels
  *
  * @param base       Pointer to the FlexIO simulated peripheral type.
+ * @param index      Timer index
  * @param clocksource  Set clock value
  */
 static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_timer_decrement_source_t clocksource)
@@ -503,7 +536,7 @@ static inline void FLEXIO_SetClockMode(FLEXIO_Type *base, uint8_t index, flexio_
     base->TIMCFG[index] = reg;
 }
 
-/* @} */
+/*! @} */
 
 /*!
  * @name FlexIO Interrupt Operation
@@ -588,7 +621,7 @@ static inline void FLEXIO_DisableTimerStatusInterrupts(FLEXIO_Type *base, uint32
     base->TIMIEN &= ~mask;
 }
 
-/* @} */
+/*! @} */
 
 /*!
  * @name FlexIO Status Operation
@@ -667,7 +700,7 @@ static inline void FLEXIO_ClearTimerStatusFlags(FLEXIO_Type *base, uint32_t mask
     base->TIMSTAT = mask;
 }
 
-/* @} */
+/*! @} */
 
 /*!
  * @name FlexIO DMA Operation
@@ -725,11 +758,160 @@ status_t FLEXIO_RegisterHandleIRQ(void *base, void *handle, flexio_isr_t isr);
  * @retval kStatus_OutOfRange The FlexIO type/handle/ISR table out of range.
  */
 status_t FLEXIO_UnregisterHandleIRQ(void *base);
-/* @} */
+/*! @} */
+
+#if defined(FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER) && FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER
+
+/*!
+ * @brief Configure a FLEXIO pin used by the board.
+ *
+ * To Config the FLEXIO PIN, define a pin configuration, as either input or output, in the user file.
+ * Then, call the FLEXIO_SetPinConfig() function.
+ *
+ * This is an example to define an input pin or an output pin configuration.
+ * @code
+ * Define a digital input pin configuration,
+ * flexio_gpio_config_t config =
+ * {
+ *   kFLEXIO_DigitalInput,
+ *   0U,
+ *   kFLEXIO_FlagRisingEdgeEnable | kFLEXIO_InputInterruptEnable,
+ * }
+ * Define a digital output pin configuration,
+ * flexio_gpio_config_t config =
+ * {
+ *   kFLEXIO_DigitalOutput,
+ *   0U,
+ *   0U
+ * }
+ * @endcode
+ * @param base   FlexIO peripheral base address
+ * @param pin    FLEXIO pin number.
+ * @param config FLEXIO pin configuration pointer.
+ */
+void FLEXIO_SetPinConfig(FLEXIO_Type *base, uint32_t pin, flexio_gpio_config_t *config);
+
+/*!
+ * @name GPIO Output Operations
+ * @{
+ */
+
+/*!
+ * @brief Sets the output level of the multiple FLEXIO pins to the logic 0.
+ *
+ * @param base   FlexIO peripheral base address
+ * @param mask   FLEXIO pin number mask
+ */
+static inline void FLEXIO_ClearPortOutput(FLEXIO_Type *base, uint32_t mask)
+{
+    base->PINOUTCLR = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple FLEXIO pins to the logic 1.
+ *
+ * @param base   FlexIO peripheral base address
+ * @param mask   FLEXIO pin number mask
+ */
+static inline void FLEXIO_SetPortOutput(FLEXIO_Type *base, uint32_t mask)
+{
+    base->PINOUTSET = mask;
+}
+
+/*!
+ * @brief Reverses the current output logic of the multiple FLEXIO pins.
+ *
+ * @param base   FlexIO peripheral base address
+ * @param mask   FLEXIO pin number mask
+ */
+static inline void FLEXIO_TogglePortOutput(FLEXIO_Type *base, uint32_t mask)
+{
+    base->PINOUTTOG = mask;
+}
+
+/*!
+ * @brief Sets the output level of the FLEXIO pins to the logic 1 or 0.
+ *
+ * @param base    FlexIO peripheral base address
+ * @param pin     FLEXIO pin number.
+ * @param output  FLEXIO pin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void FLEXIO_PinWrite(FLEXIO_Type *base, uint32_t pin, uint8_t output)
+{
+    if (output == 0U)
+    {
+        FLEXIO_ClearPortOutput(base, 1UL << pin);
+    }
+    else
+    {
+        FLEXIO_SetPortOutput(base, 1UL << pin);
+    }
+}
+
+/*!
+ * @brief Enables the FLEXIO output pin function.
+ *
+ * @param base   FlexIO peripheral base address
+ * @param pin    FLEXIO pin number.
+ */
+static inline void FLEXIO_EnablePinOutput(FLEXIO_Type *base, uint32_t pin)
+{
+    base->PINOUTE |= (1UL << pin);
+}
+/*! @} */
+
+/*!
+ * @name FLEXIO PIN Input Operations
+ * @{
+ */
+
+/*!
+ * @brief  Reads the current input value of the FLEXIO pin.
+ *
+ * @param base   FlexIO peripheral base address
+ * @param pin    FLEXIO pin number.
+ * @retval FLEXIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t FLEXIO_PinRead(FLEXIO_Type *base, uint32_t pin)
+{
+    return (((base->PIN) >> pin) & 0x01U);
+}
+
+/*!
+ * @brief Gets the FLEXIO input pin status.
+ *
+ * @param base   FlexIO peripheral base address
+ * @param pin    FLEXIO pin number.
+ * @retval FLEXIO port input status
+ *        - 0: corresponding pin input capture no status.
+ *        - 1: corresponding pin input capture rising or falling edge.
+ */
+static inline uint32_t FLEXIO_GetPinStatus(FLEXIO_Type *base, uint32_t pin)
+{
+    return (((base->PINSTAT) >> pin) & 0x01U);
+}
+
+/*!
+ * @brief Clears the multiple FLEXIO input pins status.
+ *
+ * @param base   FlexIO peripheral base address
+ * @param mask   FLEXIO pin number mask
+ */
+static inline void FLEXIO_ClearPortStatus(FLEXIO_Type *base, uint32_t mask)
+{
+    base->PINSTAT = mask;
+}
+/*! @} */
+
+#endif /*FSL_FEATURE_FLEXIO_HAS_PIN_REGISTER*/
 
 #if defined(__cplusplus)
 }
 #endif /*_cplusplus*/
-/*@}*/
+/*! @} */
 
-#endif /*_FSL_FLEXIO_H_*/
+#endif /*FSL_FLEXIO_H_*/

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_i2c_master.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_FLEXIO_I2C_MASTER_H_
-#define _FSL_FLEXIO_I2C_MASTER_H_
+#ifndef FSL_FLEXIO_I2C_MASTER_H_
+#define FSL_FLEXIO_I2C_MASTER_H_
 
 #include "fsl_common.h"
 #include "fsl_flexio.h"
@@ -21,9 +21,9 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 #define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
-/*@}*/
+/*! @} */
 
 /*! @brief Retry times for waiting flag. */
 #ifndef I2C_RETRY_TIMES
@@ -207,7 +207,7 @@ static inline void FLEXIO_I2C_MasterEnable(FLEXIO_I2C_Type *base, bool enable)
     }
 }
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Status
@@ -235,7 +235,7 @@ uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base);
 
 void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask);
 
-/*@}*/
+/*! @} */
 
 /*!
  * @name Interrupts
@@ -260,7 +260,7 @@ void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask);
  */
 void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask);
 
-/*@}*/
+/*! @} */
 
 /*!
  * @name Bus Operations
@@ -402,7 +402,7 @@ status_t FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, u
  * @return status of status_t.
  */
 status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer);
-/*@}*/
+/*! @} */
 
 /*Transactional APIs*/
 
@@ -475,11 +475,11 @@ void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_han
  */
 void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle);
 
-/*@}*/
+/*! @} */
 
 #if defined(__cplusplus)
 }
 #endif /*_cplusplus*/
-/*@}*/
+/*! @} */
 
-#endif /*_FSL_FLEXIO_I2C_MASTER_H_*/
+#endif /*FSL_FLEXIO_I2C_MASTER_H_*/

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021, 2022 NXP
+ * Copyright 2016-2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -117,7 +117,7 @@ void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config)
  * brief Set desired baud rate.
  *
  * param base Pointer to the FLEXIO_MCULCD_Type structure.
- * param baudRate_Bps Desired baud rate.
+ * param baudRate_Bps Desired baud rate in bit-per-second for all data lines combined.
  * param srcClock_Hz FLEXIO clock frequency in Hz.
  * retval kStatus_Success Set successfully.
  * retval kStatus_InvalidArgument Could not set the baud rate.
@@ -125,12 +125,13 @@ void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config)
 status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
 {
     uint32_t baudRateDiv;
+    uint32_t baudRatePerDataLine;
     uint32_t timerCompare;
     status_t status;
-    uint8_t  baudRatio;
 
-    baudRatio = (FLEXIO_MCULCD_DATA_BUS_WIDTH == 16) ? 2 : 1;
-    baudRateDiv = (srcClock_Hz + 1) / (baudRate_Bps * baudRatio);
+    baudRatePerDataLine = baudRate_Bps / (uint32_t)FLEXIO_MCULCD_DATA_BUS_WIDTH;
+
+    baudRateDiv = (srcClock_Hz + baudRatePerDataLine) / (baudRatePerDataLine * 2U);
 
     if ((0U == baudRateDiv) || (baudRateDiv > (FLEXIO_BAUDRATE_DIV_MASK + 1U)))
     {
@@ -138,6 +139,8 @@ status_t FLEXIO_MCULCD_SetBaudRate(FLEXIO_MCULCD_Type *base, uint32_t baudRate_B
     }
     else
     {
+        baudRateDiv--;
+
         timerCompare = base->flexioBase->TIMCMP[base->timerIndex];
 
         timerCompare = (timerCompare & ~FLEXIO_BAUDRATE_DIV_MASK) | baudRateDiv;
@@ -296,7 +299,7 @@ uint32_t FLEXIO_MCULCD_ReadData(FLEXIO_MCULCD_Type *base)
 }
 
 /*!
- * brief Configures the FLEXIO MCULCD to multiple beats write mode.
+ * brief Configures the FLEXIO MCULCD to single beats write mode.
  *
  * At the begining multiple beats write operation, the FLEXIO MCULCD is configured to
  * multiple beats write mode using this function. After write operation, the configuration
@@ -315,7 +318,7 @@ void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base)
      */
 
     uint32_t timerCompare;
-    uint32_t tempValue;
+    uint32_t timerControl;
 
     /* Enable the TX Shifter output. */
     base->flexioBase->SHIFTCFG[base->txShifterStartIndex] =
@@ -343,27 +346,23 @@ void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base)
         FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled) |
         FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled);
 
-    /* FlexIO bug workaround, see RM register description. */
-
-    tempValue =
-    base->flexioBase->TIMCTL[base->timerIndex] =
-        FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterStartIndex)) |
-        FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) |
-        FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData) |
-        FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) |
-        FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) |
-        FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit);
-
-    base->flexioBase->TIMCTL[base->timerIndex] = tempValue;
-
-    tempValue &= ~(FLEXIO_TIMCTL_PINCFG_MASK);
-    tempValue |= FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput);
-
-    base->flexioBase->TIMCTL[base->timerIndex] = tempValue;
+    /* When initially configure the timer pin as output, the pin may be driven low causing glitch on bus.
+       Configure the pin as bidirection output first then perform a subsequent write to change to output to avoid the
+       issue. */
+    timerControl = FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterStartIndex)) |
+                   FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) |
+                   FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) |
+                   FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData) |
+                   FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) |
+                   FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit);
+
+    base->flexioBase->TIMCTL[base->timerIndex] = timerControl;
+    timerControl = (timerControl & ~FLEXIO_TIMCTL_PINCFG_MASK) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput);
+    base->flexioBase->TIMCTL[base->timerIndex] = timerControl;
 }
 
 /*!
- * brief Clear the FLEXIO MCULCD multiple beats write mode configuration.
+ * brief Clear the FLEXIO MCULCD single beats write mode configuration.
  *
  * Clear the write configuration set by ref FLEXIO_MCULCD_SetSingleBeatWriteConfig.
  *
@@ -374,12 +373,10 @@ void FLEXIO_MCULCD_SetSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base)
 void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base)
 {
     /* Disable the timer. */
-    uint32_t tempValue = base->flexioBase->TIMCTL[base->timerIndex];
-
-    tempValue &= ~(FLEXIO_TIMCTL_PINCFG_MASK);
-    tempValue |= FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData);
-
-    base->flexioBase->TIMCTL[base->timerIndex] = tempValue;
+    /* Set to bidirection output first then set to disable to avoid glitch on bus. */
+    base->flexioBase->TIMCTL[base->timerIndex] =
+        (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) |
+        FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData);
     base->flexioBase->TIMCTL[base->timerIndex] = 0U;
     base->flexioBase->TIMCFG[base->timerIndex] = 0U;
     /* Clear the timer flag. */
@@ -392,7 +389,7 @@ void FLEXIO_MCULCD_ClearSingleBeatWriteConfig(FLEXIO_MCULCD_Type *base)
 }
 
 /*!
- * brief Configures the FLEXIO MCULCD to multiple beats read mode.
+ * brief Configures the FLEXIO MCULCD to single beats read mode.
  *
  * At the begining or multiple beats read operation, the FLEXIO MCULCD is configured
  * to multiple beats read mode using this function. After read operation, the configuration
@@ -461,7 +458,7 @@ void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base)
 }
 
 /*!
- * brief Clear the FLEXIO MCULCD multiple beats read mode configuration.
+ * brief Clear the FLEXIO MCULCD single beats read mode configuration.
  *
  * Clear the read configuration set by ref FLEXIO_MCULCD_SetSingleBeatReadConfig.
  *
@@ -472,6 +469,10 @@ void FLEXIO_MCULCD_SetSingleBeatReadConfig(FLEXIO_MCULCD_Type *base)
 void FLEXIO_MCULCD_ClearSingleBeatReadConfig(FLEXIO_MCULCD_Type *base)
 {
     /* Disable the timer. */
+    /* Set to bidirection output first then set to disable to avoid glitch on bus. */
+    base->flexioBase->TIMCTL[base->timerIndex] =
+        (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) |
+        FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData);
     base->flexioBase->TIMCTL[base->timerIndex] = 0U;
     base->flexioBase->TIMCFG[base->timerIndex] = 0U;
     /* Clear the timer flag. */
@@ -503,6 +504,7 @@ void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base)
      */
 
     uint32_t timerCompare;
+    uint32_t timerControl;
     uint8_t beats;
     uint8_t i;
 
@@ -548,12 +550,19 @@ void FLEXIO_MCULCD_SetMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base)
         FLEXIO_TIMCFG_TIMENA(kFLEXIO_TimerEnableOnTriggerHigh) | FLEXIO_TIMCFG_TSTOP(kFLEXIO_TimerStopBitDisabled) |
         FLEXIO_TIMCFG_TSTART(kFLEXIO_TimerStartBitDisabled);
 
-    base->flexioBase->TIMCTL[base->timerIndex] =
-        FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterEndIndex)) |
-        FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) |
-        FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput) |
-        FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) |
-        FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit);
+    /* When initially configure the timer pin as output, the pin may be driven low causing glitch on bus.
+       Configure the pin as bidirection output first then perform a subsequent write to change to output to avoid the
+       issue. */
+    timerControl = FLEXIO_TIMCTL_TRGSEL(FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->txShifterEndIndex)) |
+                   FLEXIO_TIMCTL_TRGPOL(kFLEXIO_TimerTriggerPolarityActiveLow) |
+                   FLEXIO_TIMCTL_TRGSRC(kFLEXIO_TimerTriggerSourceInternal) |
+                   FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData) |
+                   FLEXIO_TIMCTL_PINSEL(base->ENWRPinIndex) | FLEXIO_TIMCTL_PINPOL(kFLEXIO_PinActiveLow) |
+                   FLEXIO_TIMCTL_TIMOD(kFLEXIO_TimerModeDual8BitBaudBit);
+
+    base->flexioBase->TIMCTL[base->timerIndex] = timerControl;
+    timerControl = (timerControl & ~FLEXIO_TIMCTL_PINCFG_MASK) | FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigOutput);
+    base->flexioBase->TIMCTL[base->timerIndex] = timerControl;
 }
 
 /*!
@@ -571,6 +580,10 @@ void FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(FLEXIO_MCULCD_Type *base)
     uint32_t statusFlags = 0U;
 
     /* Disable the timer. */
+    /* Set to bidirection output first then set to disable to avoid glitch on bus. */
+    base->flexioBase->TIMCTL[base->timerIndex] =
+        (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) |
+        FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData);
     base->flexioBase->TIMCTL[base->timerIndex] = 0U;
     base->flexioBase->TIMCFG[base->timerIndex] = 0U;
     /* Clear the timer flag. */
@@ -688,6 +701,10 @@ void FLEXIO_MCULCD_ClearMultiBeatsReadConfig(FLEXIO_MCULCD_Type *base)
     uint32_t statusFlags = 0U;
 
     /* Disable the timer. */
+    /* Set to bidirection output first then set to disable to avoid glitch on bus. */
+    base->flexioBase->TIMCTL[base->timerIndex] =
+        (base->flexioBase->TIMCTL[base->timerIndex] & ~FLEXIO_TIMCTL_PINCFG_MASK) |
+        FLEXIO_TIMCTL_PINCFG(kFLEXIO_PinConfigBidirectionOutputData);
     base->flexioBase->TIMCTL[base->timerIndex] = 0U;
     base->flexioBase->TIMCFG[base->timerIndex] = 0U;
     /* Clear the timer flag. */
@@ -975,7 +992,10 @@ void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_tran
 {
     FLEXIO_MCULCD_StartTransfer(base);
 
-    FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
+    if (!xfer->dataOnly)
+    {
+        FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
+    }
 
     if (xfer->dataSize > 0U)
     {
@@ -1076,8 +1096,11 @@ status_t FLEXIO_MCULCD_TransferNonBlocking(FLEXIO_MCULCD_Type *base,
     /* Assert the nCS. */
     FLEXIO_MCULCD_StartTransfer(base);
 
-    /* Send the command. */
-    FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
+    if (!xfer->dataOnly)
+    {
+        /* Send the command. */
+        FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
+    }
 
     /* If transfer count is 0 (only to send command), return directly. */
     if (0U == xfer->dataSize)
@@ -1308,4 +1331,4 @@ void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle)
             statusFlags = FLEXIO_MCULCD_GetStatusFlags(flexioLcdMcuBase);
         }
     }
-}
+}

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd.h

@@ -1,13 +1,13 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021, 2022 NXP
+ * Copyright 2016-2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_FLEXIO_MCULCD_H_
-#define _FSL_FLEXIO_MCULCD_H_
+#ifndef FSL_FLEXIO_MCULCD_H_
+#define FSL_FLEXIO_MCULCD_H_
 
 #include "fsl_common.h"
 #include "fsl_flexio.h"
@@ -22,10 +22,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief FlexIO MCULCD driver version. */
-#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 0, 7))
-/*@}*/
+#define FSL_FLEXIO_MCULCD_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @} */
 
 #ifndef FLEXIO_MCULCD_WAIT_COMPLETE_TIME
 /*!
@@ -129,7 +129,7 @@ typedef struct _flexio_mculcd_config
     bool enableFastAccess; /*!< Enable/disable fast access to FlexIO registers,
                            fast access requires the FlexIO clock to be at least
                            twice the frequency of the bus clock. */
-    uint32_t baudRate_Bps; /*!< Baud rate in Bps. */
+    uint32_t baudRate_Bps; /*!< Baud rate in bit-per-second for all data lines combined. */
 } flexio_mculcd_config_t;
 
 /*! @brief Transfer mode.*/
@@ -144,11 +144,12 @@ typedef enum _flexio_mculcd_transfer_mode
 typedef struct _flexio_mculcd_transfer
 {
     uint32_t command;                   /*!< Command to send. */
-    flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */
     uint32_t dataAddrOrSameValue;       /*!< When sending the same value for many times,
                                            this is the value to send. When writing or reading array,
                                            this is the address of the data array. */
     size_t dataSize;                    /*!< How many bytes to transfer. */
+    flexio_mculcd_transfer_mode_t mode; /*!< Transfer mode. */
+    bool dataOnly;                      /*!< Send data only when tx without the command. */
 } flexio_mculcd_transfer_t;
 
 /*! @brief typedef for flexio_mculcd_handle_t in advance. */
@@ -229,7 +230,7 @@ void FLEXIO_MCULCD_Deinit(FLEXIO_MCULCD_Type *base);
  */
 void FLEXIO_MCULCD_GetDefaultConfig(flexio_mculcd_config_t *config);
 
-/*@}*/
+/*! @} */
 
 /*!
  * @name Status
@@ -257,7 +258,7 @@ uint32_t FLEXIO_MCULCD_GetStatusFlags(FLEXIO_MCULCD_Type *base);
  */
 void FLEXIO_MCULCD_ClearStatusFlags(FLEXIO_MCULCD_Type *base, uint32_t mask);
 
-/*@}*/
+/*! @} */
 
 /*!
  * @name Interrupts
@@ -286,7 +287,7 @@ void FLEXIO_MCULCD_EnableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask);
  */
 void FLEXIO_MCULCD_DisableInterrupts(FLEXIO_MCULCD_Type *base, uint32_t mask);
 
-/*@}*/
+/*! @} */
 
 /*!
  * @name DMA Control
@@ -343,7 +344,7 @@ static inline uint32_t FLEXIO_MCULCD_GetRxDataRegisterAddress(FLEXIO_MCULCD_Type
     return (uint32_t) & (base->flexioBase->SHIFTBUF[base->rxShifterStartIndex]);
 }
 
-/*@}*/
+/*! @} */
 
 /*!
  * @name Bus Operations
@@ -354,7 +355,7 @@ static inline uint32_t FLEXIO_MCULCD_GetRxDataRegisterAddress(FLEXIO_MCULCD_Type
  * @brief Set desired baud rate.
  *
  * @param base Pointer to the FLEXIO_MCULCD_Type structure.
- * @param baudRate_Bps Desired baud rate.
+ * @param baudRate_Bps Desired baud rate in bit-per-second for all data lines combined.
  * @param srcClock_Hz FLEXIO clock frequency in Hz.
  * @retval kStatus_Success Set successfully.
  * @retval kStatus_InvalidArgument Could not set the baud rate.
@@ -602,7 +603,7 @@ void FLEXIO_MCULCD_WriteSameValueBlocking(FLEXIO_MCULCD_Type *base, uint32_t sam
  * @param xfer pointer to flexio_mculcd_transfer_t structure.
  */
 void FLEXIO_MCULCD_TransferBlocking(FLEXIO_MCULCD_Type *base, flexio_mculcd_transfer_t *xfer);
-/*@}*/
+/*! @} */
 
 /*!
  * @name Transactional
@@ -675,11 +676,11 @@ status_t FLEXIO_MCULCD_TransferGetCount(FLEXIO_MCULCD_Type *base, flexio_mculcd_
  */
 void FLEXIO_MCULCD_TransferHandleIRQ(void *base, void *handle);
 
-/*@}*/
+/*! @} */
 
 #if defined(__cplusplus)
 }
 #endif /*_cplusplus*/
-/*@}*/
+/*! @} */
 
-#endif /*_FSL_FLEXIO_MCULCD_H_*/
+#endif /*FSL_FLEXIO_MCULCD_H_*/

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2019,2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -460,8 +460,12 @@ status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base,
         /* Setup DMA to transfer data.  */
         /* Assert the nCS. */
         FLEXIO_MCULCD_StartTransfer(base);
-        /* Send the command. */
-        FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
+
+        if (!xfer->dataOnly)
+        {
+            /* Send the command. */
+            FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
+        }
 
         /* Setup the DMA configuration. */
         FLEXIO_MCULCD_EDMAConfig(base, handle);
@@ -494,102 +498,6 @@ status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base,
     return kStatus_Success;
 }
 
-/*!
- * brief Performs a non-blocking FlexIO MCULCD data write using eDMA.
- *
- * This function returns immediately after transfer initiates. To check whether
- * the transfer is completed, user could:
- * 1. Use the transfer completed callback;
- * 2. Polling function ref FLEXIO_MCULCD_GetTransferCountEDMA
- *
- * param base pointer to FLEXIO_MCULCD_Type structure.
- * param handle pointer to flexio_mculcd_edma_handle_t structure to store the
- * transfer state.
- * param data Pointer to data.
- * param size Size(in bytes) of the data
- * retval kStatus_Success Successfully start a transfer.
- * retval kStatus_InvalidArgument Input argument is invalid.
- * retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
- * transfer.
- */
-status_t FLEXIO_MCULCD_WriteDataEDMA(FLEXIO_MCULCD_Type *base,
-                                    flexio_mculcd_edma_handle_t *handle,
-                                    const void *data, size_t size)
-{
-    assert(NULL != handle);
-    assert(NULL != data);
-
-    /*
-     * The data transfer mechanism:
-     *
-     * Read:
-     * Assume the data length is Lr = (n1 * minorLoopBytes + n2), where
-     * n2 < minorLoopBytes.
-     * If (n1 <= 1), then all data are sent using blocking method.
-     * If (n1 > 1), then the beginning ((n1-1) * minorLoopBytes) are read
-     * using DMA, the left (minorLoopBytes + n2) are read using blocking method.
-     *
-     * Write:
-     * Assume the data length is Lw = (n1 * minorLoopBytes + n2), where
-     * n2 < minorLoopBytes.
-     * If (n1 = 0), then all data are sent using blocking method.
-     * If (n1 >= 1), then the beginning (n1 * minorLoopBytes) are sent
-     * using DMA, the left n2 are sent using blocking method.
-     */
-
-    /* Check if the device is busy. */
-    if ((uint32_t)kFLEXIO_MCULCD_StateIdle != handle->state)
-    {
-        return kStatus_FLEXIO_MCULCD_Busy;
-    }
-
-    /* Set the state in handle. */
-    handle->minorLoopBytes = handle->txShifterNum * 4UL;
-    handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteArray;
-
-    /*
-     * For TX, if data is less than one minor loop, then use polling method.
-     * For RX, if data is less than two minor loop, then use polling method.
-     */
-    if (size < handle->minorLoopBytes)
-    {
-        FLEXIO_MCULCD_WriteDataArrayBlocking(base, data, size);
-
-        handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle;
-
-        /* Callback to inform upper layer. */
-        if (NULL != handle->completionCallback)
-        {
-            handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData);
-        }
-    }
-    else
-    {
-        handle->dataCount           = size;
-        handle->remainingCount      = size;
-        handle->dataAddrOrSameValue = (uint32_t)data;
-
-        /* Setup DMA to transfer data.  */
-        /* Assert the nCS. */
-        FLEXIO_MCULCD_StartTransfer(base);
-
-        /* Setup the DMA configuration. */
-        FLEXIO_MCULCD_EDMAConfig(base, handle);
-
-        /* Start the transfer. */
-        /* For 6800, de-assert the RDWR pin. */
-        if (kFLEXIO_MCULCD_6800 == base->busType)
-        {
-            base->setRDWRPin(false);
-        }
-        FLEXIO_MCULCD_SetMultiBeatsWriteConfig(base);
-        FLEXIO_MCULCD_EnableTxDMA(base, true);
-        EDMA_StartTransfer(handle->txDmaHandle);
-    }
-
-    return kStatus_Success;
-}
-
 /*!
  * brief Aborts a FlexIO MCULCD transfer using eDMA.
  *

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_edma.h

@@ -1,13 +1,13 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2020 NXP
+ * Copyright 2016-2020,2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_FLEXIO_MCULCD_EDMA_H_
-#define _FSL_FLEXIO_MCULCD_EDMA_H_
+#ifndef FSL_FLEXIO_MCULCD_EDMA_H_
+#define FSL_FLEXIO_MCULCD_EDMA_H_
 
 #include "fsl_edma.h"
 #include "fsl_flexio_mculcd.h"
@@ -21,10 +21,10 @@
  * Definitions
  ******************************************************************************/
 
-/*@{*/
+/*! @{ */
 /*! @brief FlexIO MCULCD EDMA driver version. */
-#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
-/*@}*/
+#define FSL_FLEXIO_MCULCD_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
+/*! @} */
 
 /*! @brief  typedef for flexio_mculcd_edma_handle_t in advance. */
 typedef struct _flexio_mculcd_edma_handle flexio_mculcd_edma_handle_t;
@@ -119,27 +119,6 @@ status_t FLEXIO_MCULCD_TransferCreateHandleEDMA(FLEXIO_MCULCD_Type *base,
 status_t FLEXIO_MCULCD_TransferEDMA(FLEXIO_MCULCD_Type *base,
                                     flexio_mculcd_edma_handle_t *handle,
                                     flexio_mculcd_transfer_t *xfer);
-/*!
- * brief Performs a non-blocking FlexIO MCULCD data write using eDMA.
- *
- * This function returns immediately after transfer initiates. To check whether
- * the transfer is completed, user could:
- * 1. Use the transfer completed callback;
- * 2. Polling function ref FLEXIO_MCULCD_GetTransferCountEDMA
- *
- * param base pointer to FLEXIO_MCULCD_Type structure.
- * param handle pointer to flexio_mculcd_edma_handle_t structure to store the
- * transfer state.
- * param data Pointer to data.
- * param size Size(in bytes) of the data
- * retval kStatus_Success Successfully start a transfer.
- * retval kStatus_InvalidArgument Input argument is invalid.
- * retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
- * transfer.
- */
-status_t FLEXIO_MCULCD_WriteDataEDMA(FLEXIO_MCULCD_Type *base,
-                                    flexio_mculcd_edma_handle_t *handle,
-                                    const void *data, size_t size);
 
 /*!
  * @brief Aborts a FlexIO MCULCD transfer using eDMA.
@@ -171,4 +150,4 @@ status_t FLEXIO_MCULCD_TransferGetCountEDMA(FLEXIO_MCULCD_Type *base,
 /*!
  * @}
  */
-#endif /* _FSL_FLEXIO_MCULCD_EDMA_H_ */
+#endif /* FSL_FLEXIO_MCULCD_EDMA_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_smartdma.c

@@ -0,0 +1,407 @@
+/*
+ * Copyright 2019-2021,2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_flexio_mculcd_smartdma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_mculcd_smartdma"
+#endif
+
+#define FLEXIO_MCULCD_SMARTDMA_TX_START_SHIFTER 0U
+#define FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER   7U
+#define FLEXIO_MCULCD_SMARTDMA_TX_SHIFTER_NUM \
+    (FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER - FLEXIO_MCULCD_SMARTDMA_TX_START_SHIFTER + 1)
+
+enum _MCULCD_transfer_state
+{
+    kFLEXIO_MCULCD_StateIdle,           /*!< No transfer in progress. */
+    kFLEXIO_MCULCD_StateReadArray,      /*!< Reading array in progress. */
+    kFLEXIO_MCULCD_StateWriteArray,     /*!< Writing array in progress. */
+    kFLEXIO_MCULCD_StateWriteSameValue, /*!< Writing the same value in progress.
+                                         */
+};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*!
+ * @brief Get the TX chunk size.
+ *
+ * The SMARTDMA TX transfer memory must be 4Byte aligned, the transfer size must
+ * be multiple of 64Byte. So the transfer data is devided in to three part:
+ * part1 + part2 + part3.
+ * The part2 is transfered using SMARTDMA, it should be 4Byte aligned, multiple
+ * of 64Byte.
+ * The part1 and part3 are transfered using blocking method, each of them is
+ * less than 64Byte, and total of them is less than (64 + 4) bytes.
+ *
+ * This function gets the size of each part.
+ *
+ * @param totalLen The total TX size in byte.
+ * @param startAddr The start address of the TX data.
+ * @param part1Len Length of the part 1 in byte.
+ * @param part2Len Length of the part 2 in byte.
+ * @param part3Len Length of the part 3 in byte.
+ */
+static void FLEXIO_MCULCD_SMARTDMA_GetTxChunkLen(
+    uint32_t totalLen, uint32_t startAddr, uint32_t *part1Len, uint32_t *part2Len, uint32_t *part3Len);
+
+/*!
+ * @brief Convert RGB565 to RGB888.
+ *
+ * @param rgb565 Input RGB565.
+ * @param pixelCount Pixel count.
+ * @param rgb888 Output RGB888.
+ */
+static void FLEXIO_MCULCD_RGB656ToRGB888(const uint16_t *rgb565, uint32_t pixelCount, uint8_t *rgb888);
+
+/*!
+ * @brief Callback function registered to SMARTDMA driver.
+ */
+static void FLEXIO_MCULCD_SMARTDMA_Callback(void *param);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void FLEXIO_MCULCD_SMARTDMA_GetTxChunkLen(
+    uint32_t totalLen, uint32_t startAddr, uint32_t *part1Len, uint32_t *part2Len, uint32_t *part3Len)
+{
+    if (totalLen < FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN)
+    {
+        *part1Len = totalLen;
+        *part2Len = 0;
+        *part3Len = 0;
+    }
+    else
+    {
+        *part3Len = (startAddr + totalLen) & (FLEXIO_MCULCD_SMARTDMA_TX_ADDR_ALIGN - 1U);
+        *part2Len = ((uint32_t)(totalLen - *part3Len)) & (~(FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN - 1U));
+
+        if (FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN > *part2Len)
+        {
+            *part1Len = totalLen;
+            *part2Len = 0;
+            *part3Len = 0;
+        }
+        else
+        {
+            *part1Len = totalLen - *part2Len - *part3Len;
+        }
+    }
+}
+
+static void FLEXIO_MCULCD_RGB656ToRGB888(const uint16_t *rgb565, uint32_t pixelCount, uint8_t *rgb888)
+{
+    while ((pixelCount--) != 0U)
+    {
+        *rgb888 = (uint8_t)(((*rgb565) & 0x001FU) << 3U);
+        rgb888++;
+        *rgb888 = (uint8_t)(((*rgb565) & 0x07E0U) >> 3U);
+        rgb888++;
+        *rgb888 = (uint8_t)(((*rgb565) & 0xF800U) >> 8U);
+        rgb888++;
+
+        rgb565++;
+    }
+}
+
+/*!
+ * brief Initializes the FLEXO MCULCD master SMARTDMA handle.
+ *
+ * This function initializes the FLEXO MCULCD master SMARTDMA handle which can be
+ * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD
+ * instance, call this API once to get the initialized handle.
+ *
+ * param base Pointer to FLEXIO_MCULCD_Type structure.
+ * param handle Pointer to flexio_mculcd_smartdma_handle_t structure to store the
+ * transfer state.
+ * param config Pointer to the configuration.
+ * param callback MCULCD transfer complete callback, NULL means no callback.
+ * param userData callback function parameter.
+ * retval kStatus_Success Successfully create the handle.
+ */
+status_t FLEXIO_MCULCD_TransferCreateHandleSMARTDMA(FLEXIO_MCULCD_Type *base,
+                                                    flexio_mculcd_smartdma_handle_t *handle,
+                                                    const flexio_mculcd_smartdma_config_t *config,
+                                                    flexio_mculcd_smartdma_transfer_callback_t callback,
+                                                    void *userData)
+{
+    assert(handle != NULL);
+
+    /* The SMARTDMA firmware only support TX using shifter 0 to shifter 7 */
+    if (base->txShifterStartIndex != FLEXIO_MCULCD_SMARTDMA_TX_START_SHIFTER)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    if (base->txShifterEndIndex != FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Zero the handle. */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    if (NULL == config)
+    {
+        handle->smartdmaApi = (uint8_t)kSMARTDMA_FlexIO_DMA;
+    }
+    else
+    {
+        if (config->inputPixelFormat == config->outputPixelFormat)
+        {
+            handle->smartdmaApi = (uint8_t)kSMARTDMA_FlexIO_DMA;
+        }
+        else if (((config->inputPixelFormat == kFLEXIO_MCULCD_RGB565) &&
+                  (config->outputPixelFormat == kFLEXIO_MCULCD_RGB888)) ||
+                 ((config->inputPixelFormat == kFLEXIO_MCULCD_BGR565) &&
+                  (config->outputPixelFormat == kFLEXIO_MCULCD_BGR888)))
+        {
+            handle->smartdmaApi      = (uint8_t)kSMARTDMA_FlexIO_DMA_RGB565To888;
+            handle->needColorConvert = true;
+        }
+        else
+        {
+            return kStatus_InvalidArgument;
+        }
+    }
+
+    /* Initialize the state. */
+    handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle;
+
+    /* Register callback and userData. */
+    handle->completionCallback = callback;
+    handle->userData           = userData;
+    handle->base               = base;
+
+    SMARTDMA_InstallFirmware(SMARTDMA_DISPLAY_MEM_ADDR, s_smartdmaDisplayFirmware, SMARTDMA_DISPLAY_FIRMWARE_SIZE);
+
+    SMARTDMA_InstallCallback(FLEXIO_MCULCD_SMARTDMA_Callback, handle);
+
+    /* The shifter interrupt is used by the SMARTDMA. */
+    FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, (1UL << FLEXIO_MCULCD_SMARTDMA_TX_END_SHIFTER));
+
+#if (defined(SMARTDMA_USE_FLEXIO_SHIFTER_DMA) && SMARTDMA_USE_FLEXIO_SHIFTER_DMA)
+    FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL, true);
+#endif
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Performs a non-blocking FlexIO MCULCD transfer using SMARTDMA.
+ *
+ * This function returns immediately after transfer initiates. Use the callback
+ * function to check whether the transfer is completed.
+ *
+ * param base pointer to FLEXIO_MCULCD_Type structure.
+ * param handle pointer to flexio_mculcd_smartdma_handle_t structure to store the
+ * transfer state.
+ * param xfer Pointer to FlexIO MCULCD transfer structure.
+ * retval kStatus_Success Successfully start a transfer.
+ * retval kStatus_InvalidArgument Input argument is invalid.
+ * retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
+ * transfer.
+ */
+status_t FLEXIO_MCULCD_TransferSMARTDMA(FLEXIO_MCULCD_Type *base,
+                                        flexio_mculcd_smartdma_handle_t *handle,
+                                        flexio_mculcd_transfer_t *xfer)
+{
+    assert(handle != NULL);
+    assert(xfer != NULL);
+
+    uint32_t part1Len, part2Len, part3Len;
+
+    /* Check if the device is busy. */
+    if ((uint32_t)kFLEXIO_MCULCD_StateIdle != handle->state)
+    {
+        return kStatus_FLEXIO_MCULCD_Busy;
+    }
+
+    /* Only support write array. */
+    if (kFLEXIO_MCULCD_WriteArray != xfer->mode)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    FLEXIO_MCULCD_SMARTDMA_GetTxChunkLen(xfer->dataSize, xfer->dataAddrOrSameValue, &part1Len, &part2Len, &part3Len);
+
+    handle->state = (uint32_t)kFLEXIO_MCULCD_StateWriteArray;
+
+    /* Start transfer. */
+    handle->remainingCount      = xfer->dataSize;
+    handle->dataCount           = xfer->dataSize;
+    handle->dataAddrOrSameValue = xfer->dataAddrOrSameValue;
+
+    /* Assert the nCS. */
+    FLEXIO_MCULCD_StartTransfer(base);
+
+    if (!xfer->dataOnly)
+    {
+        /* Send the command. */
+        FLEXIO_MCULCD_WriteCommandBlocking(base, xfer->command);
+    }
+
+    if (part1Len > 0U)
+    {
+        if (handle->needColorConvert)
+        {
+            FLEXIO_MCULCD_RGB656ToRGB888((uint16_t *)xfer->dataAddrOrSameValue, part1Len >> 1U,
+                                         handle->blockingXferBuffer);
+            FLEXIO_MCULCD_WriteDataArrayBlocking(base, handle->blockingXferBuffer, (part1Len >> 1U) * 3U);
+        }
+        else
+        {
+            FLEXIO_MCULCD_WriteDataArrayBlocking(base, (void *)(uint8_t *)xfer->dataAddrOrSameValue, (size_t)part1Len);
+        }
+        handle->remainingCount -= part1Len;
+        handle->dataAddrOrSameValue += part1Len;
+    }
+
+    if (0U == part2Len)
+    {
+        /* In this case, all data are sent out as part 1. Only notify upper layer here. */
+        FLEXIO_MCULCD_StopTransfer(base);
+        handle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle;
+
+        /* Callback to inform upper layer. */
+        if (NULL != handle->completionCallback)
+        {
+            handle->completionCallback(base, handle, kStatus_FLEXIO_MCULCD_Idle, handle->userData);
+        }
+    }
+    else
+    {
+        /* For 6800, de-assert the RDWR pin. */
+        if (kFLEXIO_MCULCD_6800 == base->busType)
+        {
+            base->setRDWRPin(false);
+        }
+
+        FLEXIO_MCULCD_SetMultiBeatsWriteConfig(base);
+
+        /* Save the part 3 information. */
+        handle->dataCountUsingEzh = part2Len;
+        handle->dataAddrOrSameValue += part2Len;
+
+        /* The part 3 is transfered using blocking method in ISR, convert the color
+           to save time in ISR. */
+        if ((0U != part3Len) && (handle->needColorConvert))
+        {
+            FLEXIO_MCULCD_RGB656ToRGB888((uint16_t *)xfer->dataAddrOrSameValue, part3Len >> 1U,
+                                         handle->blockingXferBuffer);
+        }
+
+        handle->smartdmaParam.p_buffer       = (uint32_t *)(xfer->dataAddrOrSameValue + part1Len);
+        handle->smartdmaParam.buffersize     = part2Len;
+        handle->smartdmaParam.smartdma_stack = handle->smartdmaStack;
+
+        SMARTDMA_Reset();
+        SMARTDMA_Boot(handle->smartdmaApi, &(handle->smartdmaParam), 0);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts a FlexIO MCULCD transfer using SMARTDMA.
+ *
+ * param base pointer to FLEXIO_MCULCD_Type structure.
+ * param handle FlexIO MCULCD SMARTDMA handle pointer.
+ */
+void FLEXIO_MCULCD_TransferAbortSMARTDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_smartdma_handle_t *handle)
+{
+    assert(handle != NULL);
+
+    SMARTDMA_Reset();
+
+    /* Set the handle state. */
+    handle->state     = (uint32_t)kFLEXIO_MCULCD_StateIdle;
+    handle->dataCount = 0;
+}
+
+/*!
+ * brief Gets the remaining bytes for FlexIO MCULCD SMARTDMA transfer.
+ *
+ * param base pointer to FLEXIO_MCULCD_Type structure.
+ * param handle FlexIO MCULCD SMARTDMA handle pointer.
+ * param count Number of count transferred so far by the SMARTDMA transaction.
+ * retval kStatus_Success Get the transferred count Successfully.
+ * retval kStatus_NoTransferInProgress No transfer in process.
+ */
+status_t FLEXIO_MCULCD_TransferGetCountSMARTDMA(FLEXIO_MCULCD_Type *base,
+                                                flexio_mculcd_smartdma_handle_t *handle,
+                                                size_t *count)
+{
+    assert(handle != NULL);
+    assert(count != NULL);
+
+    uint32_t state = handle->state;
+
+    if ((uint32_t)kFLEXIO_MCULCD_StateIdle == state)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+    else
+    {
+        *count = handle->dataCount - handle->remainingCount;
+    }
+
+    return kStatus_Success;
+}
+
+static void FLEXIO_MCULCD_SMARTDMA_Callback(void *param)
+{
+    flexio_mculcd_smartdma_handle_t *flexioMculcdSmartDmaHandle = (flexio_mculcd_smartdma_handle_t *)param;
+
+    FLEXIO_MCULCD_Type *flexioLcdMcuBase = flexioMculcdSmartDmaHandle->base;
+
+    FLEXIO_MCULCD_WaitTransmitComplete();
+
+    /* Disable the TX shifter and the timer. */
+    FLEXIO_MCULCD_ClearMultiBeatsWriteConfig(flexioLcdMcuBase);
+
+    flexioMculcdSmartDmaHandle->remainingCount -= flexioMculcdSmartDmaHandle->dataCountUsingEzh;
+
+    /* Send the part 3 */
+    if (0U != flexioMculcdSmartDmaHandle->remainingCount)
+    {
+        if (flexioMculcdSmartDmaHandle->needColorConvert)
+        {
+            FLEXIO_MCULCD_WriteDataArrayBlocking(flexioLcdMcuBase, flexioMculcdSmartDmaHandle->blockingXferBuffer,
+                                                 (flexioMculcdSmartDmaHandle->remainingCount >> 1U) * 3U);
+        }
+        else
+        {
+            FLEXIO_MCULCD_WriteDataArrayBlocking(flexioLcdMcuBase,
+                                                 (void *)(uint8_t *)flexioMculcdSmartDmaHandle->dataAddrOrSameValue,
+                                                 flexioMculcdSmartDmaHandle->remainingCount);
+        }
+    }
+
+    flexioMculcdSmartDmaHandle->remainingCount = 0;
+    FLEXIO_MCULCD_StopTransfer(flexioLcdMcuBase);
+    flexioMculcdSmartDmaHandle->state = (uint32_t)kFLEXIO_MCULCD_StateIdle;
+
+    /* Callback to inform upper layer. */
+    if (NULL != flexioMculcdSmartDmaHandle->completionCallback)
+    {
+        flexioMculcdSmartDmaHandle->completionCallback(flexioLcdMcuBase, flexioMculcdSmartDmaHandle,
+                                                       kStatus_FLEXIO_MCULCD_Idle,
+                                                       flexioMculcdSmartDmaHandle->userData);
+    }
+}

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_mculcd_smartdma.h

@@ -0,0 +1,158 @@
+/*
+ * Copyright 2019,2021,2023 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_FLEXIO_MCULCD_SMARTDMA_H_
+#define FSL_FLEXIO_MCULCD_SMARTDMA_H_
+
+#include "fsl_smartdma.h"
+#include "fsl_flexio_mculcd.h"
+
+/*!
+ * @addtogroup flexio_smartdma_mculcd
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*@{*/
+/*! @brief FlexIO MCULCD SMARTDMA driver version. */
+#define FSL_FLEXIO_MCULCD_SMARTDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*@}*/
+
+/*! @brief SMARTDMA transfer size should be multiple of 64 bytes. */
+#define FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN 64U
+
+/*! @brief SMARTDMA transfer memory address should be 4 byte aligned. */
+#define FLEXIO_MCULCD_SMARTDMA_TX_ADDR_ALIGN 4U
+
+/*! @brief  typedef for flexio_mculcd_smartdma_handle_t in advance. */
+typedef struct _flexio_mculcd_smartdma_handle flexio_mculcd_smartdma_handle_t;
+
+/*! @brief FlexIO MCULCD master callback for transfer complete.
+ *
+ * When transfer finished, the callback function is called and returns the
+ * @p status as kStatus_FLEXIO_MCULCD_Idle.
+ */
+typedef void (*flexio_mculcd_smartdma_transfer_callback_t)(FLEXIO_MCULCD_Type *base,
+                                                           flexio_mculcd_smartdma_handle_t *handle,
+                                                           status_t status,
+                                                           void *userData);
+
+/*! @brief FlexIO MCULCD SMARTDMA transfer handle, users should not touch the
+ * content of the handle.*/
+struct _flexio_mculcd_smartdma_handle
+{
+    FLEXIO_MCULCD_Type *base;       /*!< Pointer to the FLEXIO_MCULCD_Type. */
+    size_t dataCount;               /*!< Total count to be transferred. */
+    uint32_t dataAddrOrSameValue;   /*!< When sending the same value for many times,
+                                       this is the value to send. When writing or reading array,
+                                       this is the address of the data array. */
+    size_t dataCountUsingEzh;       /*!< Data transfered using SMARTDMA. */
+    volatile size_t remainingCount; /*!< Remaining count to transfer. */
+    volatile uint32_t state;        /*!< FlexIO MCULCD driver internal state. */
+    uint8_t smartdmaApi;            /*!< The SMARTDMA API used during transfer. */
+    bool needColorConvert;          /*!< Need color convert or not. */
+    uint8_t blockingXferBuffer[FLEXIO_MCULCD_SMARTDMA_TX_LEN_ALIGN * 3 /
+                               2];                                 /*!< Used for blocking method color space convet. */
+    flexio_mculcd_smartdma_transfer_callback_t completionCallback; /*!< Callback for MCULCD SMARTDMA transfer */
+    void *userData;                                                /*!< User Data for MCULCD SMARTDMA callback */
+    smartdma_flexio_mculcd_param_t smartdmaParam;                  /*!< SMARTDMA function parameters. */
+    uint32_t smartdmaStack[1];                                     /*!< SMARTDMA function stack. */
+};
+
+/*! @brief FlexIO MCULCD SMARTDMA configuration. */
+typedef struct _flexio_mculcd_smartdma_config
+{
+    flexio_mculcd_pixel_format_t inputPixelFormat;  /*!< The pixel format in the frame buffer. */
+    flexio_mculcd_pixel_format_t outputPixelFormat; /*!< The pixel format on the 8080/68k bus. */
+} flexio_mculcd_smartdma_config_t;
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name SMARTDMA Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the FLEXO MCULCD master SMARTDMA handle.
+ *
+ * This function initializes the FLEXO MCULCD master SMARTDMA handle which can be
+ * used for other FLEXO MCULCD transactional APIs. For a specified FLEXO MCULCD
+ * instance, call this API once to get the initialized handle.
+ *
+ * @param base Pointer to FLEXIO_MCULCD_Type structure.
+ * @param handle Pointer to flexio_mculcd_smartdma_handle_t structure to store the
+ * transfer state.
+ * @param config Pointer to the configuration.
+ * @param callback MCULCD transfer complete callback, NULL means no callback.
+ * @param userData callback function parameter.
+ * @retval kStatus_Success Successfully create the handle.
+ */
+status_t FLEXIO_MCULCD_TransferCreateHandleSMARTDMA(FLEXIO_MCULCD_Type *base,
+                                                    flexio_mculcd_smartdma_handle_t *handle,
+                                                    const flexio_mculcd_smartdma_config_t *config,
+                                                    flexio_mculcd_smartdma_transfer_callback_t callback,
+                                                    void *userData);
+
+/*!
+ * @brief Performs a non-blocking FlexIO MCULCD transfer using SMARTDMA.
+ *
+ * This function returns immediately after transfer initiates. Use the callback
+ * function to check whether the transfer is completed.
+ *
+ * @param base pointer to FLEXIO_MCULCD_Type structure.
+ * @param handle pointer to flexio_mculcd_smartdma_handle_t structure to store the
+ * transfer state.
+ * @param xfer Pointer to FlexIO MCULCD transfer structure.
+ * @retval kStatus_Success Successfully start a transfer.
+ * @retval kStatus_InvalidArgument Input argument is invalid.
+ * @retval kStatus_FLEXIO_MCULCD_Busy FlexIO MCULCD is not idle, it is running another
+ * transfer.
+ */
+status_t FLEXIO_MCULCD_TransferSMARTDMA(FLEXIO_MCULCD_Type *base,
+                                        flexio_mculcd_smartdma_handle_t *handle,
+                                        flexio_mculcd_transfer_t *xfer);
+
+/*!
+ * @brief Aborts a FlexIO MCULCD transfer using SMARTDMA.
+ *
+ * @param base pointer to FLEXIO_MCULCD_Type structure.
+ * @param handle FlexIO MCULCD SMARTDMA handle pointer.
+ */
+void FLEXIO_MCULCD_TransferAbortSMARTDMA(FLEXIO_MCULCD_Type *base, flexio_mculcd_smartdma_handle_t *handle);
+
+/*!
+ * @brief Gets the remaining bytes for FlexIO MCULCD SMARTDMA transfer.
+ *
+ * @param base pointer to FLEXIO_MCULCD_Type structure.
+ * @param handle FlexIO MCULCD SMARTDMA handle pointer.
+ * @param count Number of count transferred so far by the SMARTDMA transaction.
+ * @retval kStatus_Success Get the transferred count Successfully.
+ * @retval kStatus_NoTransferInProgress No transfer in process.
+ */
+status_t FLEXIO_MCULCD_TransferGetCountSMARTDMA(FLEXIO_MCULCD_Type *base,
+                                                flexio_mculcd_smartdma_handle_t *handle,
+                                                size_t *count);
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* FSL_FLEXIO_MCULCD_SMARTDMA_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi.c

@@ -1229,7 +1229,12 @@ status_t FLEXIO_SPI_MasterTransferNonBlocking(FLEXIO_SPI_Type *base,
 
     /* Enable transmit and receive interrupt to handle rx. */
     FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_RxFullInterruptEnable);
-
+    
+    if ((xfer->flags & (uint8_t)kFLEXIO_SPI_csContinuous) != 0U)
+    {
+        FLEXIO_SPI_EnableInterrupts(base, (uint32_t)kFLEXIO_SPI_TxEmptyInterruptEnable);
+    }
+    
     return kStatus_Success;
 }
 
@@ -1307,8 +1312,15 @@ void FLEXIO_SPI_MasterTransferHandleIRQ(void *spiType, void *spiHandle)
     base   = (FLEXIO_SPI_Type *)spiType;
     status = FLEXIO_SPI_GetStatusFlags(base);
 
+    /* Receive interrupt. */
+    if ((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) == 0U)
+    {
+        FLEXIO_SPI_TransferSendTransaction(base, handle);
+        return;
+    }
+
     /* Handle rx. */
-    if (((status & (uint32_t)kFLEXIO_SPI_RxBufferFullFlag) != 0U) && (handle->rxRemainingBytes != 0U))
+    if (handle->rxRemainingBytes != 0U)
     {
         FLEXIO_SPI_TransferReceiveTransaction(base, handle);
     }

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_FLEXIO_SPI_H_
-#define _FSL_FLEXIO_SPI_H_
+#ifndef FSL_FLEXIO_SPI_H_
+#define FSL_FLEXIO_SPI_H_
 
 #include "fsl_common.h"
 #include "fsl_flexio.h"
@@ -22,14 +22,14 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief FlexIO SPI driver version. */
-#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
-/*@}*/
+#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 4))
+/*! @} */
 
 #ifndef FLEXIO_SPI_DUMMYDATA
 /*! @brief FlexIO SPI dummy transfer data, the data is sent while txData is NULL. */
-#define FLEXIO_SPI_DUMMYDATA (0xFFFFFFFFU)
+#define FLEXIO_SPI_DUMMYDATA (0x00U)
 #endif
 
 /*! @brief Retry times for waiting flag. */
@@ -152,7 +152,7 @@ typedef struct _flexio_spi_slave_config
 /*! @brief Define FlexIO SPI transfer structure. */
 typedef struct _flexio_spi_transfer
 {
-    uint8_t *txData; /*!< Send buffer. */
+    const uint8_t *txData; /*!< Send buffer. */
     uint8_t *rxData; /*!< Receive buffer. */
     size_t dataSize; /*!< Transfer bytes. */
     uint8_t flags;   /*!< FlexIO SPI control flag, MSB first  or LSB first. */
@@ -179,7 +179,7 @@ typedef void (*flexio_spi_slave_transfer_callback_t)(FLEXIO_SPI_Type *base,
 /*! @brief Define FlexIO SPI handle structure. */
 struct _flexio_spi_master_handle
 {
-    uint8_t *txData;                                /*!< Transfer buffer. */
+    const uint8_t *txData;                          /*!< Transfer buffer. */
     uint8_t *rxData;                                /*!< Receive buffer. */
     size_t transferSize;                            /*!< Total bytes to be transferred. */
     volatile size_t txRemainingBytes;               /*!< Send data remaining in bytes. */
@@ -323,7 +323,7 @@ void FLEXIO_SPI_SlaveDeinit(FLEXIO_SPI_Type *base);
 */
 void FLEXIO_SPI_SlaveGetDefaultConfig(flexio_spi_slave_config_t *slaveConfig);
 
-/*@}*/
+/*! @} */
 
 /*!
  * @name Status
@@ -353,7 +353,7 @@ uint32_t FLEXIO_SPI_GetStatusFlags(FLEXIO_SPI_Type *base);
 
 void FLEXIO_SPI_ClearStatusFlags(FLEXIO_SPI_Type *base, uint32_t mask);
 
-/*@}*/
+/*! @} */
 
 /*!
  * @name Interrupts
@@ -384,7 +384,7 @@ void FLEXIO_SPI_EnableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask);
  */
 void FLEXIO_SPI_DisableInterrupts(FLEXIO_SPI_Type *base, uint32_t mask);
 
-/*@}*/
+/*! @} */
 
 /*!
  * @name DMA Control
@@ -447,7 +447,7 @@ static inline uint32_t FLEXIO_SPI_GetRxDataRegisterAddress(FLEXIO_SPI_Type *base
     }
 }
 
-/*@}*/
+/*! @} */
 
 /*!
  * @name Bus Operations
@@ -548,7 +548,6 @@ status_t FLEXIO_SPI_WriteBlocking(FLEXIO_SPI_Type *base,
  * @param direction Shift direction of MSB first or LSB first.
  * @param buffer The buffer to store the received bytes.
  * @param size The number of data bytes to be received.
- * @param direction Shift direction of MSB first or LSB first.
  * @retval kStatus_Success Successfully create the handle.
  * @retval kStatus_FLEXIO_SPI_Timeout The transfer timed out and was aborted.
  */
@@ -575,7 +574,7 @@ status_t FLEXIO_SPI_MasterTransferBlocking(FLEXIO_SPI_Type *base, flexio_spi_tra
  * @param base Pointer to the FLEXIO_SPI_Type structure.
  */
 void FLEXIO_SPI_FlushShifters(FLEXIO_SPI_Type *base);
-/*@}*/
+/*! @} */
 
 /*Transactional APIs*/
 
@@ -709,11 +708,11 @@ static inline status_t FLEXIO_SPI_SlaveTransferGetCount(FLEXIO_SPI_Type *base,
  */
 void FLEXIO_SPI_SlaveTransferHandleIRQ(void *spiType, void *spiHandle);
 
-/*@}*/
+/*! @} */
 
 #if defined(__cplusplus)
 }
 #endif /*_cplusplus*/
-/*@}*/
+/*! @} */
 
-#endif /*_FSL_FLEXIO_SPI_H_*/
+#endif /*FSL_FLEXIO_SPI_H_*/

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_spi_edma.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_FLEXIO_SPI_EDMA_H_
-#define _FSL_FLEXIO_SPI_EDMA_H_
+#ifndef FSL_FLEXIO_SPI_EDMA_H_
+#define FSL_FLEXIO_SPI_EDMA_H_
 
 #include "fsl_flexio_spi.h"
 #include "fsl_edma.h"
@@ -21,10 +21,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief FlexIO SPI EDMA driver version. */
 #define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
-/*@}*/
+/*! @} */
 
 /*! @brief  typedef for flexio_spi_master_edma_handle_t in advance. */
 typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t;

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart.c

@@ -1007,3 +1007,17 @@ void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle)
         }
     }
 }
+
+/*!
+ * brief Flush tx/rx shifters.
+ *
+ * param base Pointer to the FLEXIO_UART_Type structure.
+ */
+void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base)
+{
+    /* Disable then re-enable to flush the tx shifter. */
+    base->flexioBase->SHIFTCTL[base->shifterIndex[0]] &= ~FLEXIO_SHIFTCTL_SMOD_MASK;
+    base->flexioBase->SHIFTCTL[base->shifterIndex[0]] |= FLEXIO_SHIFTCTL_SMOD(kFLEXIO_ShifterModeTransmit);
+    /* Read to flush the rx shifter. */
+    (void)base->flexioBase->SHIFTBUF[base->shifterIndex[1]];
+}

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_FLEXIO_UART_H_
-#define _FSL_FLEXIO_UART_H_
+#ifndef FSL_FLEXIO_UART_H_
+#define FSL_FLEXIO_UART_H_
 
 #include "fsl_common.h"
 #include "fsl_flexio.h"
@@ -22,10 +22,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief FlexIO UART driver version. */
-#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
-/*@}*/
+#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
+/*! @} */
 
 /*! @brief Retry times for waiting flag. */
 #ifndef UART_RETRY_TIMES
@@ -208,7 +208,7 @@ void FLEXIO_UART_Deinit(FLEXIO_UART_Type *base);
 */
 void FLEXIO_UART_GetDefaultConfig(flexio_uart_config_t *userConfig);
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Status
@@ -237,7 +237,7 @@ uint32_t FLEXIO_UART_GetStatusFlags(FLEXIO_UART_Type *base);
 
 void FLEXIO_UART_ClearStatusFlags(FLEXIO_UART_Type *base, uint32_t mask);
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Interrupts
@@ -264,7 +264,7 @@ void FLEXIO_UART_EnableInterrupts(FLEXIO_UART_Type *base, uint32_t mask);
  */
 void FLEXIO_UART_DisableInterrupts(FLEXIO_UART_Type *base, uint32_t mask);
 
-/* @} */
+/*! @} */
 
 /*!
  * @name DMA Control
@@ -323,7 +323,7 @@ static inline void FLEXIO_UART_EnableRxDMA(FLEXIO_UART_Type *base, bool enable)
     FLEXIO_EnableShifterStatusDMA(base->flexioBase, 1UL << base->shifterIndex[1], enable);
 }
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Bus Operations
@@ -399,7 +399,7 @@ status_t FLEXIO_UART_WriteBlocking(FLEXIO_UART_Type *base, const uint8_t *txData
  */
 status_t FLEXIO_UART_ReadBlocking(FLEXIO_UART_Type *base, uint8_t *rxData, size_t rxSize);
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Transactional
@@ -571,11 +571,18 @@ status_t FLEXIO_UART_TransferGetReceiveCount(FLEXIO_UART_Type *base, flexio_uart
  */
 void FLEXIO_UART_TransferHandleIRQ(void *uartType, void *uartHandle);
 
-/*@}*/
+/*!
+ * @brief Flush tx/rx shifters.
+ *
+ * @param base Pointer to the FLEXIO_UART_Type structure.
+ */
+void FLEXIO_UART_FlushShifters(FLEXIO_UART_Type *base);
+
+/*! @} */
 
 #if defined(__cplusplus)
 }
 #endif /*_cplusplus*/
-/*@}*/
+/*! @} */
 
-#endif /*_FSL_FLEXIO_UART_H_*/
+#endif /*FSL_FLEXIO_UART_H_*/

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexio_uart_edma.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_FLEXIO_UART_EDMA_H_
-#define _FSL_FLEXIO_UART_EDMA_H_
+#ifndef FSL_FLEXIO_UART_EDMA_H_
+#define FSL_FLEXIO_UART_EDMA_H_
 
 #include "fsl_flexio_uart.h"
 #include "fsl_edma.h"
@@ -21,10 +21,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief FlexIO UART EDMA driver version. */
 #define FSL_FLEXIO_UART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
-/*@}*/
+/*! @} */
 
 /* Forward declaration of the handle typedef. */
 typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t;
@@ -167,7 +167,7 @@ status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
                                                  flexio_uart_edma_handle_t *handle,
                                                  size_t *count);
 
-/*@}*/
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -175,4 +175,4 @@ status_t FLEXIO_UART_TransferGetReceiveCountEDMA(FLEXIO_UART_Type *base,
 
 /*! @}*/
 
-#endif /* _FSL_UART_EDMA_H_ */
+#endif /* FSL_UART_EDMA_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2022 NXP
+ * Copyright 2016-2022, 2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -118,7 +118,7 @@ static flexspi_isr_t s_flexspiIsr;
 static void FLEXSPI_Memset(void *src, uint8_t value, size_t length)
 {
     assert(src != NULL);
-    uint8_t *p = src;
+    uint8_t *p = (uint8_t *)src;
 
     for (uint32_t i = 0U; i < length; i++)
     {
@@ -192,6 +192,9 @@ static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t
             /* DLLEN = 1, SLVDLYTARGET = 0xF, */
             flexspiDllValue = FLEXSPI_DLLCR_DLLEN(1) | FLEXSPI_DLLCR_SLVDLYTARGET(0x0F);
 #endif
+#if (defined(FSL_FEATURE_FLEXSPI_HAS_REFPHASEGAP) && FSL_FEATURE_FLEXSPI_HAS_REFPHASEGAP)
+            flexspiDllValue |= FLEXSPI_DLLCR_REFPHASEGAP(2U);
+#endif /* FSL_FEATURE_FLEXSPI_HAS_REFPHASEGAP */
         }
         else
         {
@@ -235,10 +238,6 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)
 
         /* Clear the flags. */
         FLEXSPI_ClearInterruptStatusFlags(base, status);
-
-        /* Reset fifos. These flags clear automatically. */
-        base->IPTXFCR |= FLEXSPI_IPTXFCR_CLRIPTXF_MASK;
-        base->IPRXFCR |= FLEXSPI_IPRXFCR_CLRIPRXF_MASK;
     }
 
     return result;
@@ -712,7 +711,7 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)
         }
 
         /* Push a watermark level data into IP TX FIFO. */
-        base->INTR |= (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag;
+        base->INTR = (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag;
     }
 
     return result;
@@ -819,7 +818,7 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint8_t *buffer, size_t size)
         }
 
         /* Pop out a watermark level datas from IP RX FIFO. */
-        base->INTR |= (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
+        base->INTR = (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
     }
 
     return result;
@@ -843,8 +842,8 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
     base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK;
 
     /* Clear former pending status before start this transfer. */
-    base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
-                  FLEXSPI_INTR_IPCMDGE_MASK;
+    base->INTR = FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
+                 FLEXSPI_INTR_IPCMDGE_MASK | FLEXSPI_INTR_IPCMDDONE_MASK;
 
     /* Configure base address. */
     base->IPCR0 = xfer->deviceAddress;
@@ -880,12 +879,13 @@ status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)
         /* Empty else. */
     }
 
-    /* Wait for bus to be idle before changing flash configuration. */
-    while (!FLEXSPI_GetBusIdleStatus(base))
+    /* Wait until the IP command execution finishes */
+    while (0UL == (base->INTR & FLEXSPI_INTR_IPCMDDONE_MASK))
     {
     }
 
-    if (xfer->cmdType == kFLEXSPI_Command)
+    /* Unless there is an error status already set, capture the latest one */
+    if (result == kStatus_Success)
     {
         result = FLEXSPI_CheckAndClearError(base, base->INTR);
     }
@@ -966,8 +966,8 @@ status_t FLEXSPI_TransferNonBlocking(FLEXSPI_Type *base, flexspi_handle_t *handl
         base->FLSHCR2[xfer->port] |= FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK;
 
         /* Clear former pending status before start this transfer. */
-        base->INTR |= FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
-                      FLEXSPI_INTR_IPCMDGE_MASK;
+        base->INTR = FLEXSPI_INTR_AHBCMDERR_MASK | FLEXSPI_INTR_IPCMDERR_MASK | FLEXSPI_INTR_AHBCMDGE_MASK |
+                     FLEXSPI_INTR_IPCMDGE_MASK | FLEXSPI_INTR_IPCMDDONE_MASK;
 
         /* Configure base address. */
         base->IPCR0 = xfer->deviceAddress;
@@ -1067,7 +1067,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
     uint32_t intEnableStatus;
     uint32_t txWatermark;
     uint32_t rxWatermark;
-    uint8_t i = 0;
+    uint32_t i = 0;
 
     status          = base->INTR;
     intEnableStatus = base->INTEN;
@@ -1130,12 +1130,12 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
                     handle->dataSize = 0;
                 }
                 /* Pop out a watermark level data from IP RX FIFO. */
-                base->INTR |= (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
+                base->INTR = (uint32_t)kFLEXSPI_IpRxFifoWatermarkAvailableFlag;
             }
 
             if (0U != (status & (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag))
             {
-                base->INTR |= (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag;
+                base->INTR = (uint32_t)kFLEXSPI_IpCommandExecutionDoneFlag;
 
                 FLEXSPI_TransferAbort(base, handle);
 
@@ -1192,7 +1192,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
                     }
 
                     /* Push a watermark level data into IP TX FIFO. */
-                    base->INTR |= (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag;
+                    base->INTR = (uint32_t)kFLEXSPI_IpTxFifoWatermarkEmptyFlag;
                 }
             }
             else
@@ -1233,6 +1233,14 @@ void FLEXSPI1_DriverIRQHandler(void)
     SDK_ISR_EXIT_BARRIER;
 }
 #endif
+#if defined(FLEXSPI2)
+void FLEXSPI2_DriverIRQHandler(void);
+void FLEXSPI2_DriverIRQHandler(void)
+{
+    s_flexspiIsr(FLEXSPI2, s_flexspiHandle[2]);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
 
 #if defined(LSIO__FLEXSPI0)
 void LSIO_OCTASPI0_INT_DriverIRQHandler(void);

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi.h

@@ -1,13 +1,13 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2022 NXP
+ * Copyright 2016-2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef __FSL_FLEXSPI_H_
-#define __FSL_FLEXSPI_H_
+#ifndef FSL_FLEXSPI_H_
+#define FSL_FLEXSPI_H_
 
 #include <stddef.h>
 #include "fsl_device_registers.h"
@@ -23,10 +23,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief FLEXSPI driver version. */
-#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
-/*@}*/
+#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 6, 0))
+/*! @} */
 
 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
 
@@ -242,8 +242,10 @@ typedef struct _flexspi_config
 #if defined(FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF) && FSL_FEATURE_FLEXSPI_SUPPORT_RXCLKSRC_DIFF
     bool rxSampleClockDiff; /*!< Sample Clock source or source_b selection for Flash Reading. */
 #endif
-    bool enableSckBDiffOpt;      /*!< Enable/disable SCKB pad use as SCKA differential clock
-                                  output, when enable, Port B flash access is not available. */
+#if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR2_SCKBDIFFOPT)
+    bool enableSckBDiffOpt; /*!< Enable/disable SCKB pad use as SCKA differential clock
+                             output, when enable, Port B flash access is not available. */
+#endif
     bool enableSameConfigForAll; /*!< Enable/disable same configuration for all connected devices
                                   when enabled, same configuration in FLASHA1CRx is applied to all. */
     uint16_t seqTimeoutCycle;    /*!< Timeout wait cycle for command sequence execution,
@@ -452,7 +454,7 @@ static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)
     }
 }
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Interrupts
@@ -480,10 +482,10 @@ static inline void FLEXSPI_DisableInterrupts(FLEXSPI_Type *base, uint32_t mask)
     base->INTEN &= ~mask;
 }
 
-/* @} */
+/*! @} */
 
 /*! @name DMA control */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Enables or disables FLEXSPI IP Tx FIFO DMA requests.
@@ -543,10 +545,10 @@ static inline uint32_t FLEXSPI_GetRxFifoAddress(FLEXSPI_Type *base)
     return (uint32_t)&base->RFDR[0];
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name FIFO control */
-/*@{*/
+/*! @{ */
 
 /*! @brief Clears the FLEXSPI IP FIFO logic.
  *
@@ -587,7 +589,7 @@ static inline void FLEXSPI_GetFifoCounts(FLEXSPI_Type *base, size_t *txCount, si
     }
 }
 
-/*@}*/
+/*! @} */
 
 /*!
  * @name Status
@@ -612,7 +614,7 @@ static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base)
  */
 static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)
 {
-    base->INTR |= mask;
+    base->INTR = mask;
 }
 
 #if !((defined(FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN)) && (FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN))
@@ -685,7 +687,7 @@ static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)
 {
     return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK));
 }
-/*@}*/
+/*! @} */
 
 /*!
  * @name Bus Operations
@@ -737,6 +739,22 @@ static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable
 }
 #endif
 
+#if (defined(FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT) && FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT)
+/*!
+ * @brief Set AHB Memory-Mapped Flash base address.
+ * 
+ * @note The length of base address may be different for differnt instance, please refer to the reference manual.
+ * @note This function should be called when FLEXSPI is in stop mode.
+ * 
+ * @param base FLEXSPI peripheral base address.
+ * @param address AHB Memory-Mapped Flash base address.
+ */
+static inline void FLEXSPI_SetAHBFlashBaseAddress(FLEXSPI_Type *base, uint8_t address)
+{
+    base->AHBCR = (base->AHBCR & (~FLEXSPI_AHBCR_AFLASHBASE_MASK)) | FLEXSPI_AHBCR_AFLASHBASE(address);
+}
+#endif /* (defined(FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT) && FSL_FEATURE_FLEXSPI_HAS_AHBCR_AFLASHBASE_BIT) */
+
 /*! @brief Updates the LUT table.
  *
  * @param base FLEXSPI peripheral base address.
@@ -879,6 +897,6 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle);
 #if defined(__cplusplus)
 }
 #endif /*_cplusplus. */
-/*@}*/
+/*! @} */
 
-#endif /* __FSL_FLEXSPI_H_ */
+#endif /* FSL_FLEXSPI_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi_edma.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2021-2022 NXP
+ * Copyright 2021-2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -288,7 +288,7 @@ status_t FLEXSPI_TransferEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle,
 
         /* Submit transfer. */
         (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
-        EDMA_SetModulo(handle->txDmaHandle->base, handle->txDmaHandle->channel, (edma_modulo_t)power,
+        EDMA_SetModulo(handle->rxDmaHandle->base, handle->rxDmaHandle->channel, (edma_modulo_t)power,
                        kEDMA_ModuloDisable);
         EDMA_SetCallback(handle->rxDmaHandle, FLEXSPI_TransferEDMACallback, &s_edmaPrivateHandle[instance]);
         EDMA_StartTransfer(handle->rxDmaHandle);

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_flexspi_edma.h

@@ -1,12 +1,12 @@
 /*
- * Copyright 2021-2022 NXP
+ * Copyright 2021-2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_FLEXSPI_EDMA_H_
-#define _FSL_FLEXSPI_EDMA_H_
+#ifndef FSL_FLEXSPI_EDMA_H_
+#define FSL_FLEXSPI_EDMA_H_
 
 #include "fsl_flexspi.h"
 #include "fsl_edma.h"
@@ -21,10 +21,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief FLEXSPI EDMA driver. */
-#define FSL_FLEXSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
+#define FSL_FLEXSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! @} */
 
 typedef struct _flexspi_edma_handle flexspi_edma_handle_t;
 
@@ -135,12 +135,12 @@ void FLEXSPI_TransferAbortEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle
  */
 status_t FLEXSPI_TransferGetTransferCountEDMA(FLEXSPI_Type *base, flexspi_edma_handle_t *handle, size_t *count);
 
-/* @} */
+/*! @} */
 
 #if defined(__cplusplus)
 }
 #endif
 
-/* @} */
+/*! @} */
 
-#endif /* _FSL_FLEXSPI_EDMA_H_ */
+#endif /* FSL_FLEXSPI_EDMA_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_freqme.c

@@ -15,6 +15,10 @@
 #define FSL_COMPONENT_ID "platform.drivers.lpc_freqme"
 #endif
 
+#if defined(FREQME_RSTS_N)
+#define FREQME_RESETS_ARRAY FREQME_RSTS_N
+#endif
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -31,6 +35,10 @@ static FREQME_Type *const s_freqmeBases[] = FREQME_BASE_PTRS;
 static const clock_ip_name_t s_freqmeClocks[] = FREQME_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
+#if defined(FREQME_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_freqmeResets[] = FREQME_RESETS_ARRAY;
+#endif
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -69,12 +77,16 @@ void FREQME_Init(FREQME_Type *base, const freq_measure_config_t *config)
     CLOCK_EnableClock(s_freqmeClocks[FREQME_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
+#if defined(FREQME_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_freqmeResets[FREQME_GetInstance(base)]);
+#endif
+
     if (config->startMeasurement)
     {
         tmp32 |= FREQME_CTRL_W_MEASURE_IN_PROGRESS_MASK;
     }
-    tmp32 |=
-        FREQME_CTRL_W_CONTINUOUS_MODE_EN(config->enableContinuousMode) | FREQME_CTRL_W_PULSE_MODE(config->operateMode);
+    tmp32 |= FREQME_CTRL_W_CONTINUOUS_MODE_EN(config->enableContinuousMode) |
+             FREQME_CTRL_W_PULSE_MODE(config->operateMode);
     if (config->operateMode == kFREQME_FreqMeasurementMode)
     {
         tmp32 |= FREQME_CTRL_W_REF_SCALE(config->operateModeAttribute.refClkScaleFactor);

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_freqme.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_FREQME_
-#define _FSL_FREQME_
+#ifndef FSL_FREQME_H_
+#define FSL_FREQME_H_
 
 #include "fsl_common.h"
 
@@ -19,10 +19,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
-/*! @brief FREQME driver version 2.0.0. */
-#define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
-/*@}*/
+/*! @{ */
+/*! @brief FREQME driver version 2.1.2. */
+#define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
+/*! @} */
 
 /*!
  * @brief The enumeration of interrupt status flags.
@@ -51,10 +51,10 @@ enum _freqme_interrupt_status_flags
  */
 enum _freqme_interrupt_enable
 {
-    kFREQME_UnderflowInterruptEnable = FREQME_CTRL_W_LT_MIN_INT_EN_MASK,   /*!< Enable interrupt when the result is
-                                                                                     less than minimum value. */
-    kFREQME_OverflowInterruptEnable = FREQME_CTRL_W_GT_MAX_INT_EN_MASK,    /*!< Enable interrupt when the result is
-                                                                                     greater than maximum value. */
+    kFREQME_UnderflowInterruptEnable = FREQME_CTRL_W_LT_MIN_INT_EN_MASK, /*!< Enable interrupt when the result is
+                                                                                   less than minimum value. */
+    kFREQME_OverflowInterruptEnable = FREQME_CTRL_W_GT_MAX_INT_EN_MASK,  /*!< Enable interrupt when the result is
+                                                                                   greater than maximum value. */
     kFREQME_ReadyInterruptEnable = FREQME_CTRL_W_RESULT_READY_INT_EN_MASK, /*!< Enable interrupt when a
                                                                                  measurement completes and the result
                                                                                  is ready. */
@@ -223,8 +223,8 @@ static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_
     uint32_t tmp32;
 
     tmp32 = base->CTRLSTAT;
-    tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_MODE_MASK | FREQME_CTRLSTAT_GT_MAX_STAT_MASK |
-               FREQME_CTRLSTAT_RESULT_READY_STAT_MASK);
+    tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_MODE_MASK |
+               FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK);
     if (operateMode == kFREOME_PulseWidthMeasurementMode)
     {
         tmp32 |= FREQME_CTRL_W_PULSE_MODE_MASK;
@@ -243,6 +243,7 @@ static inline void FREQME_SetOperateMode(FREQME_Type *base, freqme_operate_mode_
 static inline bool FREQME_CheckOperateMode(FREQME_Type *base)
 {
     return (bool)((base->CTRLSTAT & FREQME_CTRLSTAT_PULSE_MODE_MASK) != 0UL);
+
 }
 
 /*!
@@ -275,7 +276,7 @@ static inline void FREQME_SetMaxExpectedValue(FREQME_Type *base, uint32_t maxVal
  */
 
 /*!
- * @brief Calculate the frequency of selected target clock。
+ * @brief Calculate the frequency of selected target clock。
  *
  * @note The formula: Ftarget = (RESULT - 2) * Freference / 2 ^ REF_SCALE.
  *
@@ -317,8 +318,8 @@ static inline void FREQME_SetPulsePolarity(FREQME_Type *base, freqme_pulse_polar
     uint32_t tmp32;
 
     tmp32 = base->CTRLSTAT;
-    tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_POL_MASK | FREQME_CTRLSTAT_GT_MAX_STAT_MASK |
-               FREQME_CTRLSTAT_RESULT_READY_STAT_MASK);
+    tmp32 &= ~(FREQME_CTRLSTAT_LT_MIN_STAT_MASK | FREQME_CTRLSTAT_PULSE_POL_MASK |
+               FREQME_CTRLSTAT_GT_MAX_STAT_MASK | FREQME_CTRLSTAT_RESULT_READY_STAT_MASK);
 
     if (pulsePolarity != kFREQME_PulseHighPeriod)
     {
@@ -437,4 +438,4 @@ static inline void FREQME_DisableInterrupts(FREQME_Type *base, uint32_t masks)
 /*!
  * @}
  */
-#endif /* __FSL_FREQME_H__ */
+#endif /* FSL_FREQME_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gdet.c

@@ -141,7 +141,7 @@ status_t GDET_ReconfigureVoltageMode(GDET_Type *base, gdet_core_voltage_t voltag
     uint32_t tmp0   = 0;
     status_t status = kStatus_Fail;
 
-    if (voltage != (kGDET_MidVoltage || kGDET_NormalVoltage || kGDET_OverDriveVoltage))
+    if ((voltage != kGDET_MidVoltage) && (voltage != kGDET_NormalVoltage) && (voltage != kGDET_OverDriveVoltage))
     {
         return kStatus_InvalidArgument;
     }

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gdet.h

@@ -4,8 +4,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_GDET_H_
-#define _FSL_GDET_H_
+#ifndef FSL_GDET_H_
+#define FSL_GDET_H_
 
 #include "fsl_common.h"
 
@@ -21,7 +21,7 @@
  *******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief Defines GDET driver version 2.0.0.
  *
  * Change log:
@@ -29,7 +29,7 @@
  *   - initial version
  */
 #define FSL_GDET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
+/*! @} */
 
 /*!
  * @brief GDET Core Voltage.
@@ -37,12 +37,12 @@
  * These constants are used to define core voltage argument to be used with
  * GDET_ReconfigureVoltageMode().
  */
-typedef enum _gdet_core_voltage
-{
-    kGDET_MidVoltage       = 0U, /*!< Mid Voltage (1.0V) */
-    kGDET_NormalVoltage    = 1U, /*!< Normal Voltage (1.1V) */
-    kGDET_OverDriveVoltage = 2U, /*!< Over Drive Voltage (1.2V) */
-} gdet_core_voltage_t;
+
+typedef uint32_t gdet_core_voltage_t;
+#define kGDET_MidVoltage       ((gdet_core_voltage_t)0x0u) /*!< Mid Voltage (1.0V) */
+#define kGDET_NormalVoltage    ((gdet_core_voltage_t)0x1u) /*!< Normal Voltage (1.1V) */
+#define kGDET_OverDriveVoltage ((gdet_core_voltage_t)0x2u) /*!< Over Drive Voltage (1.2V) */
+
 /*******************************************************************************
  * API
  *******************************************************************************/
@@ -109,8 +109,8 @@ status_t GDET_ReconfigureVoltageMode(GDET_Type *base, gdet_core_voltage_t voltag
 
 #if defined(__cplusplus)
 }
-#endif /* __cplusplus */
+#endif   /* __cplusplus */
 
 /*! @}*/ /* end of group gdet */
 
-#endif /* _FSL_GDET_H_ */
+#endif   /* FSL_GDET_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gpio.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2019, 2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -8,18 +8,30 @@
 
 #include "fsl_gpio.h"
 
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
 /* Component ID definition, used by tools. */
 #ifndef FSL_COMPONENT_ID
 #define FSL_COMPONENT_ID "platform.drivers.gpio"
 #endif
 
+#if defined(GPIO_RSTS)
+#define GPIO_RESETS_ARRAY GPIO_RSTS
+#endif
+
 /*******************************************************************************
  * Variables
  ******************************************************************************/
 
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
 static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
 static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+#else
+#if defined(GPIO_RESETS_ARRAY)
+static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+#endif
 #endif
 
 #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
@@ -35,10 +47,16 @@ static const clock_ip_name_t s_fgpioClockName[] = FGPIO_CLOCKS;
 
 #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
 
+#if defined(GPIO_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_gpioResets[] = GPIO_RESETS_ARRAY;
+#endif
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
 /*!
  * @brief Gets the GPIO instance according to the GPIO base
  *
@@ -50,7 +68,8 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base);
 /*******************************************************************************
  * Code
  ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT) || defined(GPIO_RESETS_ARRAY)
 static uint32_t GPIO_GetInstance(GPIO_Type *base)
 {
     uint32_t instance;
@@ -99,6 +118,10 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config
 {
     assert(NULL != config);
 
+#if defined(GPIO_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_gpioResets[GPIO_GetInstance(base)]);
+#endif
+
     if (config->pinDirection == kGPIO_DigitalInput)
     {
         base->PDDR &= GPIO_FIT_REG(~(1UL << pin));
@@ -119,7 +142,8 @@ void GPIO_GetVersionInfo(GPIO_Type *base, gpio_version_info_t *info)
 }
 #endif /* FSL_FEATURE_GPIO_HAS_VERSION_INFO_REGISTER */
 
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
 /*!
  * brief Reads the GPIO port interrupt status flag.
  *
@@ -183,7 +207,8 @@ uint8_t GPIO_PinGetInterruptFlag(GPIO_Type *base, uint32_t pin)
 }
 #endif /* FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
 
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
 /*!
  * brief Clears multiple GPIO pin interrupt status flags.
  *
@@ -262,13 +287,15 @@ void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribut
 /*******************************************************************************
  * Variables
  ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
 static FGPIO_Type *const s_fgpioBases[] = FGPIO_BASE_PTRS;
 #endif
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
 /*!
  * @brief Gets the FGPIO instance according to the GPIO base
  *
@@ -280,7 +307,8 @@ static uint32_t FGPIO_GetInstance(FGPIO_Type *base);
 /*******************************************************************************
  * Code
  ******************************************************************************/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
 static uint32_t FGPIO_GetInstance(FGPIO_Type *base)
 {
     uint32_t instance;
@@ -356,7 +384,8 @@ void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *conf
         base->PDDR |= (1UL << pin);
     }
 }
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
 /*!
  * brief Reads the FGPIO port interrupt status flag.
  *

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_gpio.h

@@ -1,13 +1,13 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_GPIO_H_
-#define _FSL_GPIO_H_
+#ifndef FSL_GPIO_H_
+#define FSL_GPIO_H_
 
 #include "fsl_common.h"
 
@@ -21,10 +21,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief GPIO driver version. */
-#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 1))
-/*@}*/
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 3))
+/*! @} */
 
 #if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U)
 #define GPIO_FIT_REG(value) \
@@ -79,7 +79,8 @@ typedef struct _gpio_pin_config
     uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
 } gpio_pin_config_t;
 
-#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+#if (defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) || \
+     !(defined(FSL_FEATURE_SOC_PORT_COUNT))
 /*! @brief Configures the interrupt generation condition. */
 typedef enum _gpio_interrupt_config
 {
@@ -104,8 +105,8 @@ typedef enum _gpio_interrupt_config
 /*! @brief Configures the selection of interrupt/DMA request/trigger output. */
 typedef enum _gpio_interrupt_selection
 {
-    kGPIO_InterruptOutput0  = 0x0U,  /*!< Interrupt/DMA request/trigger output 0. */
-    kGPIO_InterruptOutput1  = 0x1U,  /*!< Interrupt/DMA request/trigger output 1. */
+    kGPIO_InterruptOutput0 = 0x0U, /*!< Interrupt/DMA request/trigger output 0. */
+    kGPIO_InterruptOutput1 = 0x1U, /*!< Interrupt/DMA request/trigger output 1. */
 } gpio_interrupt_selection_t;
 #endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT */
 
@@ -146,7 +147,7 @@ extern "C" {
  */
 
 /*! @name GPIO Configuration */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Initializes a GPIO pin used by the board.
@@ -311,10 +312,10 @@ static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask)
 }
 #endif /* FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL */
 
-/*@}*/
+/*! @} */
 
 /*! @name GPIO Output Operations */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
@@ -393,10 +394,10 @@ static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)
 #endif
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name GPIO Input Operations */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Reads the current input value of the GPIO port.
@@ -412,11 +413,12 @@ static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
     return (((uint32_t)(base->PDIR) >> pin) & 0x01UL);
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name GPIO Interrupt */
-/*@{*/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+/*! @{ */
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
 /*!
  * @brief Reads the GPIO port interrupt status flag.
  *
@@ -602,7 +604,7 @@ static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t
 void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
 #endif
 
-/*@}*/
+/*! @} */
 /*! @} */
 
 /*!
@@ -621,7 +623,7 @@ void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribut
 #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
 
 /*! @name FGPIO Configuration */
-/*@{*/
+/*! @{ */
 
 #if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
 /*!
@@ -662,10 +664,10 @@ void FGPIO_PortInit(FGPIO_Type *base);
  */
 void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
 
-/*@}*/
+/*! @} */
 
 /*! @name FGPIO Output Operations */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
@@ -720,10 +722,10 @@ static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask)
 {
     base->PTOR = mask;
 }
-/*@}*/
+/*! @} */
 
 /*! @name FGPIO Input Operations */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Reads the current input value of the FGPIO port.
@@ -738,11 +740,12 @@ static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin)
 {
     return (((base->PDIR) >> pin) & 0x01U);
 }
-/*@}*/
+/*! @} */
 
 /*! @name FGPIO Interrupt */
-/*@{*/
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+/*! @{ */
+#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
+    defined(FSL_FEATURE_SOC_PORT_COUNT)
 
 /*!
  * @brief Reads the FGPIO port interrupt status flag.
@@ -781,7 +784,7 @@ void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask);
 void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
 #endif /* FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER */
 
-/*@}*/
+/*! @} */
 
 #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
 
@@ -793,4 +796,4 @@ void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attrib
  * @}
  */
 
-#endif /* _FSL_GPIO_H_*/
+#endif /* FSL_GPIO_H_*/

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c.c

@@ -1,6 +1,5 @@
 /*
- * Copyright 2018-2022 NXP
- * All rights reserved.
+ * Copyright 2018-2024 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -432,7 +431,7 @@ status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status)
     return result;
 }
 
-static status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle)
+status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle)
 {
     status_t result = kStatus_Success;
     uint32_t status, errStatus;
@@ -768,8 +767,10 @@ void I3C_GetDefaultConfig(i3c_config_t *config)
     config->baudRate_Hz.i2cBaud          = 400000U;
     config->baudRate_Hz.i3cPushPullBaud  = 12500000U;
     config->baudRate_Hz.i3cOpenDrainBaud = 2500000U;
-    config->masterDynamicAddress         = 0x0AU;    /* Default master dynamic address. */
-    config->slowClock_Hz                 = 1000000U; /* Default slow timer clock 1MHz. */
+    config->masterDynamicAddress         = 0x0AU; /* Default master dynamic address. */
+#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH)
+    config->slowClock_Hz                 = 0; /* Not update the Soc default setting. */
+#endif
     config->enableSlave                  = true;
     config->vendorID                     = 0x11BU;
 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND)
@@ -796,7 +797,10 @@ void I3C_GetDefaultConfig(i3c_config_t *config)
  */
 void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) || \
+    !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET)
     uint32_t instance = I3C_GetInstance(base);
+#endif
     uint32_t configValue;
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -819,14 +823,30 @@ void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_H
                     I3C_MCONFIG_HKEEP(config->hKeep) | I3C_MCONFIG_ODSTOP(config->enableOpenDrainStop) |
                     I3C_MCONFIG_ODHPP(config->enableOpenDrainHigh);
 
+#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY
+    base->MCONFIG_EXT = I3C_MCONFIG_EXT_I3C_CAS_DEL(config->startSclDelay) | I3C_MCONFIG_EXT_I3C_CASR_DEL(config->restartSclDelay);
+#endif
+
     I3C_MasterSetWatermarks(base, kI3C_TxTriggerUntilOneLessThanFull, kI3C_RxTriggerOnNotEmpty, true, true);
 
     I3C_MasterSetBaudRate(base, &config->baudRate_Hz, sourceClock_Hz);
 
 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH)
+    assert((config->slowClock_Hz >= 1000000U) || (config->slowClock_Hz == 0U));
+
     uint8_t matchCount;
-    /* Caculate bus available condition match value for current slow clock, count value provides 1us.*/
-    matchCount = (uint8_t)(config->slowClock_Hz / 1000000UL);
+    /* Set as (slowClk(MHz) - 1) to generate 1us clock cycle. Controller uses it to count 100us timeout. Target uses it as IBI request to drive SDA low.
+       Note: Use BAMATCH = 1 to generate 1us clock cycle if slow clock is 1MHz. The value of 0 would not give a correct match indication. */
+    if (config->slowClock_Hz != 0U)
+    {
+        matchCount = (uint8_t)(config->slowClock_Hz / 1000000UL) - 1U;
+        matchCount = (matchCount == 0U) ? 1U : matchCount;
+    }
+    else
+    {
+        /* BAMATCH has default value based on Soc default slow clock after reset, using this default value when slowClock_Hz is 0. */
+        matchCount = (uint8_t)((base->SCONFIG & I3C_SCONFIG_BAMATCH_MASK) >> I3C_SCONFIG_BAMATCH_SHIFT);
+    }
 #endif
 
     configValue = base->SCONFIG;
@@ -905,6 +925,8 @@ void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_H
  */
 void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig)
 {
+    (void)memset(masterConfig, 0, sizeof(*masterConfig));
+
     masterConfig->enableMaster                 = kI3C_MasterOn;
     masterConfig->disableTimeout               = false;
     masterConfig->hKeep                        = kI3C_MasterHighKeeperNone;
@@ -929,7 +951,11 @@ void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig)
  */
 void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) || \
+    !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET)
     uint32_t instance = I3C_GetInstance(base);
+#endif
+
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate the clock. */
     CLOCK_EnableClock(kI3cClocks[instance]);
@@ -943,9 +969,33 @@ void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uin
                     I3C_MCONFIG_HKEEP(masterConfig->hKeep) | I3C_MCONFIG_ODSTOP(masterConfig->enableOpenDrainStop) |
                     I3C_MCONFIG_ODHPP(masterConfig->enableOpenDrainHigh);
 
+#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY
+    base->MCONFIG_EXT = I3C_MCONFIG_EXT_I3C_CAS_DEL(masterConfig->startSclDelay) | I3C_MCONFIG_EXT_I3C_CASR_DEL(masterConfig->restartSclDelay);
+#endif
+
     I3C_MasterSetWatermarks(base, kI3C_TxTriggerUntilOneLessThanFull, kI3C_RxTriggerOnNotEmpty, true, true);
 
     I3C_MasterSetBaudRate(base, &masterConfig->baudRate_Hz, sourceClock_Hz);
+
+#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH)
+    assert((masterConfig->slowClock_Hz >= 1000000U) || (masterConfig->slowClock_Hz == 0U));
+
+    uint32_t configValue;
+    uint8_t matchCount;
+
+    /* BAMATCH has default value based on Soc default slow clock after reset, using this default value when slowClock_Hz is 0. */
+    if (masterConfig->slowClock_Hz != 0U)
+    {
+        /* Set as (slowClk(MHz) - 1) to generate 1us clock cycle for 100us timeout. Note: Use BAMATCH = 1 to generate 1us clock cycle
+           if slow clock is 1MHz. The value of 0 would not give a correct match indication. */
+        matchCount = (uint8_t)(masterConfig->slowClock_Hz / 1000000UL) - 1U;
+        matchCount = (matchCount == 0U) ? 1U : matchCount;
+
+        configValue = base->SCONFIG & I3C_SCONFIG_BAMATCH_MASK;
+        configValue |= I3C_SCONFIG_BAMATCH(matchCount);
+        base->SCONFIG = configValue;
+    }
+#endif
 }
 
 /*!
@@ -1126,8 +1176,8 @@ void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz,
 }
 
 /*!
- * brief Sends a START signal and slave address on the I2C/I3C bus.
- *
+ * brief Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified
+ * in the call.
  * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure
  * that another master is not occupying the bus. Then a START signal is transmitted, followed by the
  * 7-bit address specified in the a address parameter. Note that this function does not actually wait
@@ -1138,10 +1188,12 @@ void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz,
  * param address 7-bit slave device address, in bits [6:0].
  * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set
  *      the R/w bit (bit 0) in the transmitted slave address.
+ * param rxSize Read terminate size for the followed read transfer, limit to 255 bytes.
  * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO.
  * retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
  */
-status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir)
+status_t I3C_MasterStartWithRxSize(
+    I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize)
 {
     i3c_master_state_t masterState = I3C_MasterGetState(base);
     bool checkDdrState             = (type == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true;
@@ -1150,43 +1202,35 @@ status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i
         return kStatus_I3C_Busy;
     }
 
-    return I3C_MasterRepeatedStart(base, type, address, dir);
+    return I3C_MasterRepeatedStartWithRxSize(base, type, address, dir, rxSize);
 }
 
 /*!
- * brief Sends a repeated START signal and slave address on the I2C/I3C bus.
- *
- * This function is used to send a Repeated START signal when a transfer is already in progress. Like
- * I3C_MasterStart(), it also sends the specified 7-bit address.
+ * brief Sends a START signal and slave address on the I2C/I3C bus.
  *
- * note This function exists primarily to maintain compatible APIs between I3C and I2C drivers,
- *      as well as to better document the intent of code that uses these APIs.
+ * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure
+ * that another master is not occupying the bus. Then a START signal is transmitted, followed by the
+ * 7-bit address specified in the a address parameter. Note that this function does not actually wait
+ * until the START and address are successfully sent on the bus before returning.
  *
  * param base The I3C peripheral base address.
  * param type The bus type to use in this transaction.
  * param address 7-bit slave device address, in bits [6:0].
  * param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set
  *      the R/w bit (bit 0) in the transmitted slave address.
- * param rxSize if dir is #kI3C_Read, this assigns bytes to read. Otherwise set to 0.
- * retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO.
+ * retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO.
+ * retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
  */
-status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir)
+status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir)
 {
-    uint32_t mctrlVal;
-
-    /* Clear all flags. */
-    I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags);
-
-    /* Issue start command. */
-    mctrlVal = base->MCTRL;
-    mctrlVal &= ~(I3C_MCTRL_TYPE_MASK | I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_ADDR_MASK |
-                  I3C_MCTRL_RDTERM_MASK);
-    mctrlVal |= I3C_MCTRL_TYPE(type) | I3C_MCTRL_REQUEST(kI3C_RequestEmitStartAddr) | I3C_MCTRL_DIR(dir) |
-                I3C_MCTRL_ADDR(address);
-
-    base->MCTRL = mctrlVal;
+    i3c_master_state_t masterState = I3C_MasterGetState(base);
+    bool checkDdrState             = (type == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true;
+    if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState)
+    {
+        return kStatus_I3C_Busy;
+    }
 
-    return kStatus_Success;
+    return I3C_MasterStartWithRxSize(base, type, address, dir, 0);
 }
 
 /*!
@@ -1218,6 +1262,21 @@ status_t I3C_MasterRepeatedStartWithRxSize(
     /* Clear all flags. */
     I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags);
 
+#if defined(FSL_FEATURE_I3C_HAS_ERRATA_051617) && (FSL_FEATURE_I3C_HAS_ERRATA_051617)
+    /* ERRATA051617: When used as I2C controller generates repeated START randomly before the STOP under PVT condition.
+    This issue is caused by a glitch at the output of an internal clock MUX. The glitch when generates acts as a clock
+    pulse which causes the SDA line to fall early during SCL high period and creates the unintended Repeated START before
+    actual STOP. */
+    if (type == kI3C_TypeI2C)
+    {
+        base->MCONFIG |= I3C_MCONFIG_SKEW(1);
+    }
+    else
+    {
+        base->MCONFIG &= ~I3C_MCONFIG_SKEW_MASK;
+    }
+#endif
+
     /* Issue start command. */
     mctrlVal = base->MCTRL;
     mctrlVal &= ~(I3C_MCTRL_TYPE_MASK | I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_ADDR_MASK |
@@ -1332,9 +1391,10 @@ void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule)
  */
 status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags)
 {
-    status_t result = kStatus_Success;
+    status_t result   = kStatus_Success;
+    bool isRxAutoTerm = ((flags & (uint32_t)kI3C_TransferRxAutoTermFlag) != 0UL);
+    bool completed    = false;
     uint32_t status;
-    bool completed = false;
     uint8_t *buf;
 
     assert(NULL != rxBuff);
@@ -1382,6 +1442,7 @@ status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t
                     if (I3C_MasterGetState(base) == kI3C_MasterStateDdr)
                     {
                         I3C_MasterEmitRequest(base, kI3C_RequestForceExit);
+                        result = I3C_MasterWaitForCtrlDone(base, false);
                     }
                     else
                     {
@@ -1400,9 +1461,12 @@ status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t
         {
             *buf++ = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK);
             rxSize--;
-            if (rxSize == 1U)
+            if ((flags & (uint32_t)kI3C_TransferDisableRxTermFlag) == 0UL)
             {
-                base->MCTRL |= I3C_MCTRL_RDTERM(1U);
+                if ((!isRxAutoTerm) && (rxSize == 1U))
+                {
+                    base->MCTRL |= I3C_MCTRL_RDTERM(1U);
+                }
             }
         }
     }
@@ -1497,6 +1561,7 @@ status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint3
         if (I3C_MasterGetState(base) == kI3C_MasterStateDdr)
         {
             I3C_MasterEmitRequest(base, kI3C_RequestForceExit);
+            result = I3C_MasterWaitForCtrlDone(base, false);
         }
         else
         {
@@ -1525,15 +1590,19 @@ status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base,
                                                uint32_t count,
                                                i3c_master_daa_baudrate_t *daaBaudRate)
 {
-    status_t result = kStatus_Success;
-    uint32_t status;
-    uint32_t errStatus;
-    uint32_t masterConfig;
+    assert(addressList != NULL);
+    assert(count != 0U);
+
+    status_t result       = kStatus_Success;
+    uint8_t rxBuffer[8]   = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU};
+    uint32_t masterConfig = 0;
+    uint32_t devCount     = 0;
+    uint8_t rxSize        = 0;
+    bool mctrlDone        = false;
     i3c_baudrate_hz_t baudRate_Hz;
+    uint32_t errStatus;
+    uint32_t status;
     size_t rxCount;
-    uint8_t rxBuffer[8] = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU};
-    uint8_t rxSize      = 0;
-    uint32_t devCount   = 0;
 
     /* Return an error if the bus is already in use not by us. */
     result = I3C_CheckForBusyBus(base);
@@ -1566,66 +1635,81 @@ status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base,
 
     do
     {
-        do
+        status = I3C_MasterGetStatusFlags(base);
+
+        /* Check for error flags. */
+        errStatus = I3C_MasterGetErrorStatusFlags(base);
+        result    = I3C_MasterCheckAndClearError(base, errStatus);
+        if (kStatus_Success != result)
+        {
+            break;
+        }
+
+        if ((!mctrlDone) || (rxSize < 8U))
         {
-            status = I3C_MasterGetStatusFlags(base);
             I3C_MasterGetFifoCounts(base, &rxCount, NULL);
 
-            /* Check for error flags. */
-            errStatus = I3C_MasterGetErrorStatusFlags(base);
-            result    = I3C_MasterCheckAndClearError(base, errStatus);
-            if (kStatus_Success != result)
+            if (rxCount != 0U)
             {
-                if (daaBaudRate != NULL)
-                {
-                    base->MCONFIG = masterConfig;
-                }
-                return result;
+                rxBuffer[rxSize++] = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK);
             }
 
-            if ((0UL != (status & (uint32_t)kI3C_MasterRxReadyFlag)) && (rxCount != 0U))
+            if ((status & (uint32_t)kI3C_MasterControlDoneFlag) != 0U)
             {
-                rxBuffer[rxSize++] = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK);
+                I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag);
+                mctrlDone = true;
             }
-        } while ((status & (uint32_t)kI3C_MasterControlDoneFlag) != (uint32_t)kI3C_MasterControlDoneFlag);
-
-        I3C_MasterClearStatusFlags(base, (uint32_t)kI3C_MasterControlDoneFlag);
-
-        if ((I3C_MasterGetState(base) == kI3C_MasterStateDaa) &&
-            (0UL != (I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterBetweenFlag)))
+        }
+        else if ((I3C_MasterGetState(base) == kI3C_MasterStateDaa) &&
+                 (0UL != (I3C_MasterGetStatusFlags(base) & (uint32_t)kI3C_MasterBetweenFlag)))
         {
-            rxSize = 0;
-            if ((devCount > (count - 1UL)) || ((devCount + 1UL) > I3C_MAX_DEVCNT))
+            if (((devCount + 1UL) > count) || ((devCount + 1UL) > I3C_MAX_DEVCNT))
             {
-                if (daaBaudRate != NULL)
-                {
-                    base->MCONFIG = masterConfig;
-                }
-                return kStatus_I3C_SlaveCountExceed;
+                result = kStatus_I3C_SlaveCountExceed;
+                break;
             }
 
+            /* Assign the dynamic address from address list. */
             devList[devCount].dynamicAddr = *addressList++;
-            devList[devCount].vendorID    = (((uint16_t)rxBuffer[0] << 8U | (uint16_t)rxBuffer[1]) & 0xFFFEU) >> 1U;
-            devList[devCount].partNumber  = ((uint32_t)rxBuffer[2] << 24U | (uint32_t)rxBuffer[3] << 16U |
-                                            (uint32_t)rxBuffer[4] << 8U | (uint32_t)rxBuffer[5]);
-            devList[devCount].bcr         = rxBuffer[6];
-            devList[devCount].dcr         = rxBuffer[7];
             base->MWDATAB                 = devList[devCount].dynamicAddr;
+
             /* Emit process DAA again. */
             I3C_MasterEmitRequest(base, kI3C_RequestProcessDAA);
+
+            devList[devCount].vendorID   = (((uint16_t)rxBuffer[0] << 8U | (uint16_t)rxBuffer[1]) & 0xFFFEU) >> 1U;
+            devList[devCount].partNumber = ((uint32_t)rxBuffer[2] << 24U | (uint32_t)rxBuffer[3] << 16U |
+                                            (uint32_t)rxBuffer[4] << 8U | (uint32_t)rxBuffer[5]);
+            devList[devCount].bcr        = rxBuffer[6];
+            devList[devCount].dcr        = rxBuffer[7];
             devCount++;
             usedDevCount++;
+
+            /* Ready to handle next device. */
+            mctrlDone = false;
+            rxSize    = 0;
+        }
+        else
+        {
+            /* Intentional empty */
         }
     } while ((status & (uint32_t)kI3C_MasterCompleteFlag) != (uint32_t)kI3C_MasterCompleteFlag);
 
+    /* Master stops DAA if slave device number exceeds the prepared address number. */
+    if (result == kStatus_I3C_SlaveCountExceed)
+    {
+        /* Send the STOP signal */
+        base->MCTRL = (base->MCTRL & ~(I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_RDTERM_MASK)) |
+                      I3C_MCTRL_REQUEST(kI3C_RequestEmitStop);
+    }
+
     /* Set back initial baud rate after DAA is over. */
     if (daaBaudRate != NULL)
     {
         base->MCONFIG = masterConfig;
     }
 
-    I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags);
     /* Clear all flags. */
+    I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags);
     I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags);
 
     /* Enable I3C IRQ sources while we configure stuff. */
@@ -1718,6 +1802,7 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans
     i3c_direction_t direction      = transfer->direction;
     i3c_master_state_t masterState = I3C_MasterGetState(base);
     bool checkDdrState             = false;
+    i3c_rx_term_ops_t rxTermOps;
 
     /* Return an error if the bus is already in use not by us. */
     checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true;
@@ -1740,14 +1825,81 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans
         direction = (0UL != transfer->subaddressSize) ? kI3C_Write : transfer->direction;
     }
 
+    /* True: Set Rx termination bytes at start point, False: Set Rx termination one bytes in advance. */
+    if ((transfer->flags & (uint32_t)kI3C_TransferDisableRxTermFlag) != 0U)
+    {
+        rxTermOps = kI3C_RxTermDisable;
+    }
+    else if (transfer->dataSize <= 255U)
+    {
+        rxTermOps = kI3C_RxAutoTerm;
+    }
+    else
+    {
+        rxTermOps = kI3C_RxTermLastByte;
+    }
+
+    if (0UL != (transfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr))
+    {
+        if (0UL != (transfer->flags & (uint32_t)kI3C_TransferNoStartFlag))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        if (0UL != (transfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        /* Issue 0x7E as start. */
+        result = I3C_MasterStart(base, transfer->busType, 0x7E, kI3C_Write);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+
+        result = I3C_MasterWaitForCtrlDone(base, false);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+    }
+
     if (0UL == (transfer->flags & (uint32_t)kI3C_TransferNoStartFlag))
     {
-        result = I3C_MasterStart(base, transfer->busType, transfer->slaveAddress, direction);
+        if ((direction == kI3C_Read) && (rxTermOps == kI3C_RxAutoTerm))
+        {
+            result = I3C_MasterStartWithRxSize(base, transfer->busType, transfer->slaveAddress, direction,
+                                               (uint8_t)transfer->dataSize);
+        }
+        else
+        {
+            result = I3C_MasterStart(base, transfer->busType, transfer->slaveAddress, direction);
+        }
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+
+        result = I3C_MasterWaitForCtrlDone(base, false);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+
         if (true == I3C_MasterTransferNoStartFlag(base, transfer))
         {
             return kStatus_I3C_IBIWon;
         }
     }
+    else
+    {
+        if ((direction == kI3C_Read) && (rxTermOps != kI3C_RxTermDisable))
+        {
+            /* Can't set Rx termination more than one bytes in advance without START. */
+            rxTermOps = kI3C_RxTermLastByte;
+        }
+    }
 
     /* Subaddress, MSB first. */
     if (0U != transfer->subaddressSize)
@@ -1782,15 +1934,39 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans
         /* Need to send repeated start if switching directions to read. */
         if ((transfer->busType != kI3C_TypeI3CDdr) && (0UL != transfer->dataSize) && (transfer->direction == kI3C_Read))
         {
-            result = I3C_MasterRepeatedStart(base, transfer->busType, transfer->slaveAddress, kI3C_Read);
+            if (rxTermOps == kI3C_RxAutoTerm)
+            {
+                result = I3C_MasterRepeatedStartWithRxSize(base, transfer->busType, transfer->slaveAddress, kI3C_Read,
+                                                           (uint8_t)transfer->dataSize);
+            }
+            else
+            {
+                result = I3C_MasterRepeatedStart(base, transfer->busType, transfer->slaveAddress, kI3C_Read);
+            }
+
             if (kStatus_Success != result)
             {
                 I3C_MasterClearFlagsAndEnableIRQ(base);
                 return result;
             }
+
+            result = I3C_MasterWaitForCtrlDone(base, false);
+            if (result != kStatus_Success)
+            {
+                return result;
+            }
         }
     }
 
+    if (rxTermOps == kI3C_RxAutoTerm)
+    {
+        transfer->flags |= (uint32_t)kI3C_TransferRxAutoTermFlag;
+    }
+    else
+    {
+        transfer->flags &= ~(uint32_t)kI3C_TransferRxAutoTermFlag;
+    }
+
     /* Transmit data. */
     if ((transfer->direction == kI3C_Write) && (transfer->dataSize > 0UL))
     {
@@ -1800,10 +1976,6 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans
     /* Receive Data. */
     else if ((transfer->direction == kI3C_Read) && (transfer->dataSize > 0UL))
     {
-        if (transfer->dataSize == 1U)
-        {
-            base->MCTRL |= I3C_MCTRL_RDTERM(1U);
-        }
         result = I3C_MasterReceive(base, transfer->data, transfer->dataSize, transfer->flags);
     }
     else
@@ -1952,14 +2124,21 @@ static void I3C_TransferStateMachineSendCommandState(I3C_Type *base,
         {
             base->MWDATABE = (uint8_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize));
 
-            if (0UL == handle->transfer.dataSize)
+            if (handle->transfer.busType != kI3C_TypeI3CDdr)
             {
-                handle->state = (uint8_t)kWaitForCompletionState;
+                if (0UL == handle->transfer.dataSize)
+                {
+                    handle->state = (uint8_t)kWaitForCompletionState;
+                }
+                else
+                {
+                    /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */
+                    handle->state = (uint8_t)kWaitRepeatedStartCompleteState;
+                }
             }
             else
             {
-                /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */
-                handle->state = (uint8_t)kWaitRepeatedStartCompleteState;
+                handle->state = (uint8_t)kTransferDataState;
             }
         }
         else
@@ -1988,7 +2167,7 @@ static void I3C_TransferStateMachineWaitRepeatedStartCompleteState(I3C_Type *bas
 
         if (handle->remainingBytes < 256U)
         {
-            handle->isReadTerm = true;
+            handle->rxTermOps = (handle->rxTermOps == kI3C_RxTermDisable) ? handle->rxTermOps : kI3C_RxAutoTerm;
             stateParams->result =
                 I3C_MasterRepeatedStartWithRxSize(base, handle->transfer.busType, handle->transfer.slaveAddress,
                                                   kI3C_Read, (uint8_t)handle->remainingBytes);
@@ -2057,11 +2236,10 @@ static void I3C_TransferStateMachineTransferDataState(I3C_Type *base,
         /* Move to stop when the transfer is done. */
         if (--handle->remainingBytes == 0UL)
         {
-            handle->isReadTerm = false;
-            handle->state      = (uint8_t)kWaitForCompletionState;
+            handle->state = (uint8_t)kWaitForCompletionState;
         }
 
-        if (!handle->isReadTerm && (handle->remainingBytes == 1UL))
+        if ((handle->rxTermOps == kI3C_RxTermLastByte) && (handle->remainingBytes == 1UL))
         {
             base->MCTRL |= I3C_MCTRL_RDTERM(1UL);
         }
@@ -2218,6 +2396,32 @@ static status_t I3C_InitTransferStateMachine(I3C_Type *base, i3c_master_handle_t
         direction = (0UL != xfer->subaddressSize) ? kI3C_Write : xfer->direction;
     }
 
+    if (0UL != (xfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr))
+    {
+        if (0UL != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        if (0UL != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        /* Issue 0x7E as start. */
+        result = I3C_MasterStart(base, xfer->busType, 0x7E, kI3C_Write);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+
+        result = I3C_MasterWaitForCtrlDone(base, false);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+    }
+
     /* Handle no start option. */
     if (0U != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag))
     {
@@ -2256,14 +2460,18 @@ static status_t I3C_InitTransferStateMachine(I3C_Type *base, i3c_master_handle_t
     {
         handle->state = (uint8_t)kSendCommandState;
     }
-    else
+    else if (xfer->dataSize != 0U)
     {
         handle->state = (uint8_t)kTransferDataState;
     }
+    else
+    {
+        handle->state = (uint8_t)kStopState;
+    }
 
     if ((handle->remainingBytes < 256U) && (direction == kI3C_Read))
     {
-        handle->isReadTerm = true;
+        handle->rxTermOps = (handle->rxTermOps == kI3C_RxTermDisable) ? handle->rxTermOps : kI3C_RxAutoTerm;
         base->MCTRL |= I3C_MCTRL_RDTERM(handle->remainingBytes);
     }
 
@@ -2318,6 +2526,19 @@ status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *hand
     /* Reset fifos. These flags clear automatically. */
     base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK;
 
+    if ((transfer->flags & (uint32_t)kI3C_TransferDisableRxTermFlag) != 0U)
+    {
+        handle->rxTermOps = kI3C_RxTermDisable;
+    }
+    else if (transfer->dataSize <= 255U)
+    {
+        handle->rxTermOps = kI3C_RxAutoTerm;
+    }
+    else
+    {
+        handle->rxTermOps = kI3C_RxTermLastByte;
+    }
+
     /* Generate commands to send. */
     (void)I3C_InitTransferStateMachine(base, handle);
 
@@ -2425,14 +2646,14 @@ void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle)
  * note This function does not need to be called unless you are reimplementing the
  *  nonblocking API's interrupt handler routines to add special functionality.
  * param base The I3C peripheral base address.
- * param handle Pointer to the I3C master driver handle.
+ * param intHandle Pointer to the I3C master driver handle.
  */
 void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle)
 {
-    bool isDone;
+    i3c_master_handle_t *handle = (i3c_master_handle_t *)intHandle;
     status_t result;
+    bool isDone;
 
-    i3c_master_handle_t *handle = (i3c_master_handle_t *)intHandle;
     /* Don't do anything if we don't have a valid handle. */
     if (NULL == handle)
     {
@@ -2498,7 +2719,9 @@ void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig)
     (void)memset(slaveConfig, 0, sizeof(*slaveConfig));
 
     slaveConfig->enableSlave = true;
+#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ)
     slaveConfig->isHotJoin   = false;
+#endif
     slaveConfig->vendorID    = 0x11BU;
 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND)
     slaveConfig->enableRandomPart = false;
@@ -2529,14 +2752,19 @@ void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig)
  * param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of
  * defaults that you can override.
  * param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values.
+ * If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless.
  */
 void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz)
 {
     assert(NULL != slaveConfig);
-    assert(0UL != slowClock_Hz);
+    assert((slowClock_Hz >= 1000000U) || (slowClock_Hz == 0U));
 
     uint32_t configValue;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) || \
+    !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET)
     uint32_t instance = I3C_GetInstance(base);
+#endif
+
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate the clock. */
     CLOCK_EnableClock(kI3cClocks[instance]);
@@ -2549,8 +2777,18 @@ void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32
 
 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH)
     uint8_t matchCount;
-    /* Caculate bus available condition match value for current slow clock, count value provides 1us.*/
-    matchCount = (uint8_t)(slowClock_Hz / 1000000UL);
+    /* Set as (slowClk(MHz) - 1) to generate 1us clock cycle for IBI request to drive SDA low. Note: Use BAMATCH = 1 to
+       generate 1us clock cycle if slow clock is 1MHz. The value of 0 would not give a correct match indication. */
+    if (slowClock_Hz != 0U)
+    {
+        matchCount = (uint8_t)(slowClock_Hz / 1000000UL) - 1U;
+        matchCount = (matchCount == 0U) ? 1U : matchCount;
+    }
+    else
+    {
+        /* BAMATCH has default value based on Soc default slow clock after reset, using this default value when slowClock_Hz is 0. */
+        matchCount = (uint8_t)((base->SCONFIG & I3C_SCONFIG_BAMATCH_MASK) >> I3C_SCONFIG_BAMATCH_SHIFT);
+    }
 #endif
 
     configValue = base->SCONFIG;
@@ -2605,10 +2843,12 @@ void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32
     base->SMAXLIMITS |=
         (I3C_SMAXLIMITS_MAXRD(slaveConfig->maxReadLength) | I3C_SMAXLIMITS_MAXWR(slaveConfig->maxWriteLength));
 
+#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ)
     if (slaveConfig->isHotJoin)
     {
         I3C_SlaveRequestEvent(base, kI3C_SlaveEventHotJoinReq);
     }
+#endif
     base->SCONFIG = configValue;
 }
 
@@ -2670,6 +2910,7 @@ i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base)
     return returnCode;
 }
 
+#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ)
 /*!
  * brief I3C slave request event.
  *
@@ -2689,10 +2930,11 @@ void I3C_SlaveRequestEvent(I3C_Type *base, i3c_slave_event_t event)
 
 /*!
  * brief I3C slave request event.
+ * deprecated Do not use this function. It has been superseded by @ref I3C_SlaveRequestIBIWithData.
  *
  * param base The I3C peripheral base address.
  * param data IBI data
- * param dataSize IBI data length
+ * param dataSize IBI data size.
  */
 void I3C_SlaveRequestIBIWithSingleData(I3C_Type *base, uint8_t data, size_t dataSize)
 {
@@ -2705,24 +2947,64 @@ void I3C_SlaveRequestIBIWithSingleData(I3C_Type *base, uint8_t data, size_t data
 }
 
 /*!
- * brief I3C slave request event.
+ * brief I3C slave request IBI event with data payload(mandatory and extended).
  *
  * param base The I3C peripheral base address.
- * param data IBI data pointer
- * param dataSize IBI data length
+ * param data Pointer to IBI data to be sent in the request.
+ * param dataSize IBI data size.
  */
-void I3C_SlaveRequestIBIWithData(I3C_Type *base, i3c_slave_handle_t *handle, uint8_t *data, size_t dataSize)
+void I3C_SlaveRequestIBIWithData(I3C_Type *base, uint8_t *data, size_t dataSize)
 {
-    uint32_t ctrlValue = base->SCTRL;
+    assert((dataSize > 0U) && (dataSize <= 8U));
 
-    ctrlValue &= ~(I3C_SCTRL_EVENT_MASK | I3C_SCTRL_IBIDATA_MASK);
-    ctrlValue |= I3C_SCTRL_EVENT(1U) | I3C_SCTRL_IBIDATA(*data);
+    uint32_t ctrlValue;
+
+#if (defined(I3C_IBIEXT1_MAX_MASK) && I3C_IBIEXT1_MAX_MASK)
+    if (dataSize > 1U)
+    {
+        ctrlValue = I3C_IBIEXT1_EXT1(data[1]);
+        if (dataSize > 2U)
+        {
+            ctrlValue |= I3C_IBIEXT1_EXT2(data[2]);
+        }
+        if (dataSize > 3U)
+        {
+            ctrlValue |= I3C_IBIEXT1_EXT3(data[3]);
+        }
+        ctrlValue |= I3C_IBIEXT1_CNT(dataSize - 1U);
+        base->IBIEXT1 = ctrlValue;
+    }
 
-    handle->ibiData     = &data[1];
-    handle->ibiDataSize = dataSize - 1U;
+    if (dataSize > 4U)
+    {
+        ctrlValue = I3C_IBIEXT2_EXT4(data[4]);
+        if (dataSize > 5U)
+        {
+            ctrlValue |= I3C_IBIEXT2_EXT5(data[5]);
+        }
+        if (dataSize > 6U)
+        {
+            ctrlValue |= I3C_IBIEXT2_EXT6(data[6]);
+        }
+        if (dataSize > 7U)
+        {
+            ctrlValue |= I3C_IBIEXT2_EXT7(data[7]);
+        }
+        base->IBIEXT2 = ctrlValue;
+    }
+#endif
 
+    ctrlValue = base->SCTRL;
+#if (defined(I3C_IBIEXT1_MAX_MASK) && I3C_IBIEXT1_MAX_MASK)
+    ctrlValue &= ~(I3C_SCTRL_EVENT_MASK | I3C_SCTRL_IBIDATA_MASK | I3C_SCTRL_EXTDATA_MASK);
+    ctrlValue |= I3C_SCTRL_EVENT(1U) | I3C_SCTRL_IBIDATA(data[0]) | I3C_SCTRL_EXTDATA(dataSize > 1U);
+#else
+    ctrlValue &= ~(I3C_SCTRL_EVENT_MASK | I3C_SCTRL_IBIDATA_MASK);
+    ctrlValue |= I3C_SCTRL_EVENT(1U) | I3C_SCTRL_IBIDATA(data[0]);
+#endif
     base->SCTRL = ctrlValue;
 }
+#endif /* !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) */
 
 /*!
  * brief Performs a polling send transfer on the I3C bus.
@@ -3013,20 +3295,6 @@ static void I3C_SlaveTransferHandleBusStart(I3C_Type *base, i3c_slave_transfer_t
 static void I3C_SlaveTransferHandleEventSent(I3C_Type *base, i3c_slave_handle_t *handle, i3c_slave_transfer_t *xfer)
 {
     xfer->event = (uint32_t)kI3C_SlaveRequestSentEvent;
-    if (handle->ibiData != NULL)
-    {
-        size_t count = 0U;
-        while (count < handle->ibiDataSize)
-        {
-            base->SCTRL = (base->SCTRL & ~I3C_SCTRL_IBIDATA_MASK) | I3C_SCTRL_IBIDATA(handle->ibiData[count]) |
-                          I3C_SCTRL_EVENT(1U);
-            count++;
-        }
-    }
-
-    /* Reset IBI data buffer. */
-    handle->ibiData = NULL;
-
     if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback))
     {
         handle->callback(base, xfer, handle->userData);
@@ -3051,7 +3319,7 @@ static void I3C_SlaveTransferHandleBusStop(I3C_Type *base,
     I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag);
     stateParams->pendingInts &= ~(uint32_t)kI3C_SlaveTxReadyFlag;
     base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK;
-    if (handle->isBusy == true)
+    if (handle->isBusy)
     {
         handle->transfer.event            = (uint32_t)kI3C_SlaveCompletionEvent;
         handle->transfer.completionStatus = kStatus_Success;
@@ -3102,6 +3370,7 @@ static void I3C_SlaveTransferHandleTxReady(I3C_Type *base,
         if (0UL != (stateParams->flags & (uint32_t)kI3C_SlaveBusHDRModeFlag))
         {
             handle->transfer.event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent;
+            handle->isBusy = true;
         }
         if (NULL != handle->callback)
         {
@@ -3148,6 +3417,7 @@ static void I3C_SlaveTransferHandleRxReady(I3C_Type *base,
         if (0UL != (stateParams->flags & (uint32_t)kI3C_SlaveBusHDRModeFlag))
         {
             handle->transfer.event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent;
+            handle->isBusy = true;
         }
         if (NULL != handle->callback)
         {
@@ -3170,7 +3440,7 @@ static void I3C_SlaveTransferHandleRxReady(I3C_Type *base,
  * note This function does not need to be called unless you are reimplementing the
  *  non blocking API's interrupt handler routines to add special functionality.
  * param base The I3C peripheral base address.
- * param handle Pointer to #i3c_slave_handle_t structure which stores the transfer state.
+ * param intHandle Pointer to #i3c_slave_handle_t structure which stores the transfer state.
  */
 void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle)
 {
@@ -3291,3 +3561,12 @@ void I3C2_DriverIRQHandler(void)
     I3C_CommonIRQHandler(I3C2, 2);
 }
 #endif
+
+#if defined(I3C3)
+/* Implementation of I3C3 handler named in startup code. */
+void I3C3_DriverIRQHandler(void);
+void I3C3_DriverIRQHandler(void)
+{
+    I3C_CommonIRQHandler(I3C3, 3);
+}
+#endif

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c.h

@@ -1,11 +1,10 @@
 /*
- * Copyright 2018-2022 NXP
- * All rights reserved.
+ * Copyright 2018-2024 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_I3C_H_
-#define _FSL_I3C_H_
+#ifndef FSL_I3C_H_
+#define FSL_I3C_H_
 
 #include "fsl_common.h"
 
@@ -19,10 +18,10 @@
  */
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief I3C driver version */
-#define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 8, 1))
-/*@}*/
+#define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 12, 0))
+/*! @} */
 
 /*! @brief Timeout times for waiting flag. */
 #ifndef I3C_RETRY_TIMES
@@ -255,6 +254,23 @@ typedef enum _i3c_rx_trigger_level
     kI3C_RxTriggerUntilThreeQuarterOrMore = 3U, /*!< Trigger on 3/4 full or more. */
 } i3c_rx_trigger_level_t;
 
+/*! @brief I3C master read termination operations. */
+typedef enum _i3c_rx_term_ops
+{
+    kI3C_RxTermDisable = 0U, /*!< Master doesn't terminate read, used for CCC transfer. */
+    kI3C_RxAutoTerm = 1U,  /*!< Master auto terminate read after receiving specified bytes(<=255). */
+    kI3C_RxTermLastByte = 2U,  /*!< Master terminates read at any time after START, no length limitation. */
+} i3c_rx_term_ops_t;
+
+/*! @brief I3C start SCL delay options. */
+typedef enum _i3c_start_scl_delay
+{
+    kI3C_NoDelay = 0U, /*!< No delay. */
+    kI3C_IncreaseSclHalfPeriod = 1U, /*!< Increases SCL clock period by 1/2. */
+    kI3C_IncreaseSclOnePeriod = 2U, /*!< Increases SCL clock period by 1. */
+    kI3C_IncreaseSclOneAndHalfPeriod = 3U, /*!< Increases SCL clock period by 1 1/2 */
+} i3c_start_scl_delay_t;
+
 /*! @brief Structure with setting master IBI rules and slave registry. */
 typedef struct _i3c_register_ibi_addr
 {
@@ -295,6 +311,13 @@ typedef struct _i3c_master_config
     bool enableOpenDrainStop;         /*!< Whether to emit open-drain speed STOP. */
     bool enableOpenDrainHigh;         /*!< Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. */
     i3c_baudrate_hz_t baudRate_Hz;    /*!< Desired baud rate settings. */
+#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH)
+    uint32_t slowClock_Hz;            /*!< Slow clock frequency. */
+#endif
+#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY
+    i3c_start_scl_delay_t startSclDelay; /*!< I3C SCL delay after START. */
+    i3c_start_scl_delay_t restartSclDelay; /*!< I3C SCL delay after Repeated START. */
+#endif
 } i3c_master_config_t;
 
 /* Forward declaration of the transfer descriptor and handle typedefs. */
@@ -327,6 +350,10 @@ enum _i3c_master_transfer_flags
     kI3C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */
     kI3C_TransferNoStopFlag        = 0x04U, /*!< Don't send a stop condition. */
     kI3C_TransferWordsFlag         = 0x08U, /*!< Transfer in words, else transfer in bytes. */
+    kI3C_TransferDisableRxTermFlag = 0x10U, /*!< Disable Rx termination. Note: It's for I3C CCC transfer. */
+    kI3C_TransferRxAutoTermFlag =
+        0x20U, /*!< Set Rx auto-termination. Note: It's adaptive based on Rx size(<=255 bytes) except in I3C_MasterReceive. */
+    kI3C_TransferStartWithBroadcastAddr = 0x40U, /*!< Start transfer with 0x7E, then read/write data with device address. */
 };
 
 /*!
@@ -356,7 +383,7 @@ struct _i3c_master_handle
 {
     uint8_t state;                           /*!< Transfer state machine current state. */
     uint32_t remainingBytes;                 /*!< Remaining byte count in current state. */
-    bool isReadTerm;                         /*!< Is readterm configured. */
+    i3c_rx_term_ops_t rxTermOps;             /*!< Read termination operation. */
     i3c_master_transfer_t transfer;          /*!< Copy of the current transfer info. */
     uint8_t ibiAddress;                      /*!< Slave address which request IBI. */
     uint8_t *ibiBuff;                        /*!< Pointer to IBI buffer to keep ibi bytes. */
@@ -487,7 +514,9 @@ typedef enum _i3c_slave_activity_state
 typedef struct _i3c_slave_config
 {
     bool enableSlave;   /*!< Whether to enable slave. */
+#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ)
     bool isHotJoin;     /*!< Whether to enable slave hotjoin before enable slave. */
+#endif
     uint8_t staticAddr; /*!< Static address. */
     uint16_t vendorID;  /*!< Device vendor ID(manufacture ID). */
 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND)
@@ -578,8 +607,6 @@ struct _i3c_slave_handle
     uint32_t transferredCount;              /*!< Count of bytes transferred. */
     i3c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */
     void *userData;                         /*!< Callback parameter passed to callback. */
-    uint8_t *ibiData;                       /*!< IBI data buffer */
-    size_t ibiDataSize;                     /*!< IBI data size */
     uint8_t txFifoSize;                     /*!< Tx Fifo size */
 };
 
@@ -609,8 +636,14 @@ typedef struct _i3c_config
     bool enableOpenDrainStop;         /*!< Whether to emit open-drain speed STOP. */
     bool enableOpenDrainHigh;         /*!< Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. */
     i3c_baudrate_hz_t baudRate_Hz;    /*!< Desired baud rate settings. */
+#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY
+    i3c_start_scl_delay_t startSclDelay; /*!< I3C SCL delay after START. */
+    i3c_start_scl_delay_t restartSclDelay; /*!< I3C SCL delay after Repeated START. */
+#endif
     uint8_t masterDynamicAddress;     /*!< Main master dynamic address configuration. */
+#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH)
     uint32_t slowClock_Hz;            /*!< Slow clock frequency for time control. */
+#endif
     uint32_t maxWriteLength;          /*!< Maximum write length. */
     uint32_t maxReadLength;           /*!< Maximum read length. */
     bool enableSlave;                 /*!< Whether to enable slave. */
@@ -725,7 +758,7 @@ void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_H
  */
 
 /*! @name Initialization and deinitialization */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Provides a default configuration for the I3C master peripheral.
@@ -775,6 +808,9 @@ void I3C_MasterDeinit(I3C_Type *base);
 /* Not static so it can be used from fsl_i3c_dma.c. */
 status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status);
 
+/* Not static so it can be used from fsl_i3c_dma.c. */
+status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle);
+
 /* Not static so it can be used from fsl_i3c_dma.c. */
 status_t I3C_CheckForBusyBus(I3C_Type *base);
 
@@ -789,10 +825,10 @@ static inline void I3C_MasterEnable(I3C_Type *base, i3c_master_enable_t enable)
     base->MCONFIG = (base->MCONFIG & ~I3C_MCONFIG_MSTENA_MASK) | I3C_MCONFIG_MSTENA(enable);
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Status */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Gets the I3C master status flags.
@@ -876,10 +912,10 @@ static inline void I3C_MasterClearErrorStatusFlags(I3C_Type *base, uint32_t stat
  */
 i3c_master_state_t I3C_MasterGetState(I3C_Type *base);
 
-/*@}*/
+/*! @} */
 
 /*! @name Interrupts */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Enables the I3C master interrupt requests.
@@ -935,10 +971,10 @@ static inline uint32_t I3C_MasterGetPendingInterrupts(I3C_Type *base)
     return base->MINTMASKED;
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name DMA control */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Enables or disables I3C master DMA requests.
@@ -981,10 +1017,10 @@ static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width
     return (uint32_t)((width == 2U) ? &base->MRDATAH : &base->MRDATAB);
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name FIFO control */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Sets the watermarks for I3C master FIFOs.
@@ -1025,10 +1061,10 @@ static inline void I3C_MasterGetFifoCounts(I3C_Type *base, size_t *rxCount, size
     }
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Bus operations */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Sets the I3C bus frequency for master transactions.
@@ -1057,11 +1093,12 @@ static inline bool I3C_MasterGetBusIdleState(I3C_Type *base)
 }
 
 /*!
- * @brief Sends a START signal and slave address on the I2C/I3C bus.
+ * @brief Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified
+ * in the call.
  *
  * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure
  * that another master is not occupying the bus. Then a START signal is transmitted, followed by the
- * 7-bit address specified in the @a address parameter. Note that this function does not actually wait
+ * 7-bit address specified in the a address parameter. Note that this function does not actually wait
  * until the START and address are successfully sent on the bus before returning.
  *
  * @param base The I3C peripheral base address.
@@ -1069,28 +1106,30 @@ static inline bool I3C_MasterGetBusIdleState(I3C_Type *base)
  * @param address 7-bit slave device address, in bits [6:0].
  * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set
  *      the R/w bit (bit 0) in the transmitted slave address.
+ * @param rxSize Read terminate size for the followed read transfer, limit to 255 bytes.
  * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO.
  * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
  */
-status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir);
+status_t I3C_MasterStartWithRxSize(
+    I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize);
 
 /*!
- * @brief Sends a repeated START signal and slave address on the I2C/I3C bus.
- *
- * This function is used to send a Repeated START signal when a transfer is already in progress. Like
- * I3C_MasterStart(), it also sends the specified 7-bit address.
+ * @brief Sends a START signal and slave address on the I2C/I3C bus.
  *
- * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers,
- *      as well as to better document the intent of code that uses these APIs.
+ * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure
+ * that another master is not occupying the bus. Then a START signal is transmitted, followed by the
+ * 7-bit address specified in the @a address parameter. Note that this function does not actually wait
+ * until the START and address are successfully sent on the bus before returning.
  *
  * @param base The I3C peripheral base address.
  * @param type The bus type to use in this transaction.
  * @param address 7-bit slave device address, in bits [6:0].
  * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set
  *      the R/w bit (bit 0) in the transmitted slave address.
- * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO.
+ * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO.
+ * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
  */
-status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir);
+status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir);
 
 /*!
  * @brief Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified
@@ -1116,6 +1155,30 @@ status_t I3C_MasterRepeatedStart(I3C_Type *base, i3c_bus_type_t type, uint8_t ad
 status_t I3C_MasterRepeatedStartWithRxSize(
     I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize);
 
+/*!
+ * @brief Sends a repeated START signal and slave address on the I2C/I3C bus.
+ *
+ * This function is used to send a Repeated START signal when a transfer is already in progress. Like
+ * I3C_MasterStart(), it also sends the specified 7-bit address.
+ *
+ * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers,
+ *      as well as to better document the intent of code that uses these APIs.
+ *
+ * @param base The I3C peripheral base address.
+ * @param type The bus type to use in this transaction.
+ * @param address 7-bit slave device address, in bits [6:0].
+ * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set
+ *      the R/w bit (bit 0) in the transmitted slave address.
+ * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO.
+ */
+static inline status_t I3C_MasterRepeatedStart(I3C_Type *base,
+                                               i3c_bus_type_t type,
+                                               uint8_t address,
+                                               i3c_direction_t dir)
+{
+    return I3C_MasterRepeatedStartWithRxSize(base, type, address, dir, 0);
+}
+
 /*!
  * @brief Performs a polling send transfer on the I2C/I3C bus.
  *
@@ -1294,10 +1357,10 @@ i3c_device_info_t *I3C_MasterGetDeviceListAfterDAA(I3C_Type *base, uint8_t *coun
  */
 status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer);
 
-/*@}*/
+/*! @} */
 
 /*! @name Non-blocking */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Creates a new handle for the I3C master non-blocking APIs.
@@ -1356,21 +1419,21 @@ status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle,
  */
 void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle);
 
-/*@}*/
+/*! @} */
 
 /*! @name IRQ handler */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Reusable routine to handle master interrupts.
  * @note This function does not need to be called unless you are reimplementing the
  *  nonblocking API's interrupt handler routines to add special functionality.
  * @param base The I3C peripheral base address.
- * @param handle Pointer to the I3C master driver handle.
+ * @param intHandle Pointer to the I3C master driver handle.
  */
 void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle);
 
-/*@}*/
+/*! @} */
 
 /*! @} */
 
@@ -1380,7 +1443,7 @@ void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle);
  */
 
 /*! @name Initialization and deinitialization */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Provides a default configuration for the I3C slave peripheral.
@@ -1407,6 +1470,7 @@ void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig);
  * @param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of
  * defaults that you can override.
  * @param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values.
+ * If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless.
  */
 void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz);
 
@@ -1430,10 +1494,10 @@ static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable)
     base->SCONFIG = (base->SCONFIG & ~I3C_SCONFIG_SLVENA_MASK) | I3C_SCONFIG_SLVENA(isEnable);
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Status */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Gets the I3C slave status flags.
@@ -1514,10 +1578,10 @@ i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base);
 
 /* Not static so it can be used from fsl_i3c_dma.c. */
 status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status);
-/*@}*/
+/*! @} */
 
 /*! @name Interrupts */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Enables the I3C slave interrupt requests.
@@ -1593,10 +1657,10 @@ static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base)
     return base->SINTMASKED;
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name DMA control */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Enables or disables I3C slave DMA requests.
@@ -1639,10 +1703,10 @@ static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width)
     return (uint32_t)((width == 2U) ? &base->SRDATAH : &base->SRDATAB);
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name FIFO control */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Sets the watermarks for I3C slave FIFOs.
@@ -1683,11 +1747,12 @@ static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_
     }
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Bus operations */
-/*@{*/
+/*! @{ */
 
+#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ)
 /*!
  * @brief I3C slave request event.
  *
@@ -1695,6 +1760,7 @@ static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_
  * @param event I3C slave event of type #i3c_slave_event_t
  */
 void I3C_SlaveRequestEvent(I3C_Type *base, i3c_slave_event_t event);
+#endif
 
 /*!
  * @brief Performs a polling send transfer on the I3C bus.
@@ -1716,10 +1782,10 @@ status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize);
  */
 status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize);
 
-/*@}*/
+/*! @} */
 
 /*! @name Slave non-blocking */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Creates a new handle for the I3C slave non-blocking APIs.
@@ -1789,42 +1855,45 @@ status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, s
  */
 void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle);
 
-/*@}*/
+/*! @} */
 
 /*! @name Slave IRQ handler */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Reusable routine to handle slave interrupts.
  * @note This function does not need to be called unless you are reimplementing the
  *  non blocking API's interrupt handler routines to add special functionality.
  * @param base The I3C peripheral base address.
- * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state.
+ * @param intHandle Pointer to struct: _i3c_slave_handle structure which stores the transfer state.
  */
 void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle);
 
+#if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ)
 /*!
- * @brief I3C slave request IBI event with multiple data payload.
+ * @brief I3C slave request IBI event with data payload(mandatory and extended).
  *
  * @param base The I3C peripheral base address.
- * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state.
  * @param data Pointer to IBI data to be sent in the request.
  * @param dataSize IBI data size.
  */
-void I3C_SlaveRequestIBIWithData(I3C_Type *base, i3c_slave_handle_t *handle, uint8_t *data, size_t dataSize);
+void I3C_SlaveRequestIBIWithData(I3C_Type *base, uint8_t *data, size_t dataSize);
 
 /*!
  * @brief I3C slave request IBI event with single data.
+ * @deprecated Do not use this function. It has been superseded by @ref I3C_SlaveRequestIBIWithData.
  *
  * @param base The I3C peripheral base address.
  * @param data IBI data to be sent in the request.
  * @param dataSize IBI data size.
  */
 void I3C_SlaveRequestIBIWithSingleData(I3C_Type *base, uint8_t data, size_t dataSize);
-/*@}*/
+#endif /* !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) */
+
+/*! @} */
 /*! @} */
 #if defined(__cplusplus)
 }
 #endif
 
-#endif /* _FSL_I3C_H_ */
+#endif /* FSL_I3C_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c_edma.c

@@ -0,0 +1,1057 @@
+/*
+ * Copyright 2022-2023 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_i3c_edma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.i3c_edma"
+#endif
+
+/*! @brief States for the state machine used by transactional APIs. */
+enum _i3c_edma_transfer_states
+{
+    kIdleState = 0,
+    kIBIWonState,
+    kSlaveStartState,
+    kSendCommandState,
+    kWaitRepeatedStartCompleteState,
+    kTransmitDataState,
+    kReceiveDataState,
+    kStopState,
+    kWaitForCompletionState,
+    kAddressMatchState,
+};
+
+/*! @brief Common sets of flags used by the driver. */
+enum _i3c_edma_flag_constants
+{
+    /*! All flags which are cleared by the driver upon starting a transfer. */
+    kMasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag |
+                        kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag,
+
+    /*! IRQ sources enabled by the non-blocking transactional API. */
+    kMasterDMAIrqFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag |
+                         kI3C_MasterArbitrationWonFlag | kI3C_MasterErrorFlag | kI3C_MasterSlave2MasterFlag,
+
+    /*! Errors to check for. */
+    kMasterErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag |
+#if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM)
+                        kI3C_MasterErrorTermFlag |
+#endif
+                        kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag |
+                        kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag |
+                        kI3C_MasterErrorTimeoutFlag,
+    /*! All flags which are cleared by the driver upon starting a transfer. */
+    kSlaveClearFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag,
+
+    /*! IRQ sources enabled by the non-blocking transactional API. */
+    kSlaveDMAIrqFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag |
+                        kI3C_SlaveBusStopFlag | /*kI3C_SlaveRxReadyFlag |*/
+                        kI3C_SlaveDynamicAddrChangedFlag | kI3C_SlaveReceivedCCCFlag | kI3C_SlaveErrorFlag |
+                        kI3C_SlaveHDRCommandMatchFlag | kI3C_SlaveCCCHandledFlag | kI3C_SlaveEventSentFlag,
+
+    /*! Errors to check for. */
+    kSlaveErrorFlags = kI3C_SlaveErrorOverrunFlag | kI3C_SlaveErrorUnderrunFlag | kI3C_SlaveErrorUnderrunNakFlag |
+                       kI3C_SlaveErrorTermFlag | kI3C_SlaveErrorInvalidStartFlag | kI3C_SlaveErrorSdrParityFlag |
+                       kI3C_SlaveErrorHdrParityFlag | kI3C_SlaveErrorHdrCRCFlag | kI3C_SlaveErrorS0S1Flag |
+                       kI3C_SlaveErrorOverreadFlag | kI3C_SlaveErrorOverwriteFlag,
+};
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Array to map I3C instance number to base pointer. */
+static I3C_Type *const kI3cBases[] = I3C_BASE_PTRS;
+
+/*! @brief Array to store the END byte of I3C teransfer. */
+static uint8_t i3cEndByte[ARRAY_SIZE(kI3cBases)] = {0};
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+static void I3C_MasterRunEDMATransfer(
+    I3C_Type *base, i3c_master_edma_handle_t *handle, void *data, size_t dataSize, i3c_direction_t direction);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static void I3C_MasterTransferEDMACallbackRx(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds)
+{
+    i3c_master_edma_handle_t *i3cHandle = (i3c_master_edma_handle_t *)param;
+
+    if (transferDone)
+    {
+        /* Terminate following data if present. */
+        i3cHandle->base->MCTRL |= I3C_MCTRL_RDTERM(1U);
+
+#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086)
+        if (i3cHandle->transfer.dataSize > 1U)
+        {
+            size_t rxCount;
+            /* Read out the last byte data. */
+            do
+            {
+                I3C_MasterGetFifoCounts(i3cHandle->base, &rxCount, NULL);
+            } while (rxCount == 0U);
+            *(uint8_t *)((uint32_t)(uint32_t *)i3cHandle->transfer.data + i3cHandle->transfer.dataSize - 1U) =
+                (uint8_t)i3cHandle->base->MRDATAB;
+        }
+#endif
+
+        /* Disable I3C Rx DMA. */
+        i3cHandle->base->MDATACTRL &= ~I3C_MDMACTRL_DMAFB_MASK;
+    }
+}
+
+static void I3C_MasterTransferEDMACallbackTx(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds)
+{
+    i3c_master_edma_handle_t *i3cHandle = (i3c_master_edma_handle_t *)param;
+    uint32_t instance;
+
+    if (transferDone)
+    {
+        /* Disable I3C Tx DMA. */
+        i3cHandle->base->MDATACTRL &= ~I3C_MDMACTRL_DMATB_MASK;
+
+        if (i3cHandle->transferCount != 1U)
+        {
+            instance = I3C_GetInstance(i3cHandle->base);
+            /* Ensure there's space in the Tx FIFO. */
+            while ((i3cHandle->base->MDATACTRL & I3C_MDATACTRL_TXFULL_MASK) != 0U)
+            {
+            }
+            i3cHandle->base->MWDATABE = i3cEndByte[instance];
+        }
+    }
+}
+/*!
+ * brief Prepares the transfer state machine and fills in the command buffer.
+ * param handle Master nonblocking driver handle.
+ */
+static status_t I3C_MasterInitTransferStateMachineEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle)
+{
+    i3c_master_transfer_t *xfer = &handle->transfer;
+    status_t result             = kStatus_Success;
+    i3c_direction_t direction   = xfer->direction;
+
+    /* Calculate command count and put into command buffer. */
+    handle->subaddressCount = 0U;
+    if (xfer->subaddressSize != 0U)
+    {
+        for (uint32_t i = xfer->subaddressSize; i > 0U; i--)
+        {
+            handle->subaddressBuffer[handle->subaddressCount++] = (uint8_t)((xfer->subaddress) >> (8U * (i - 1U)));
+        }
+    }
+
+    /* Start condition shall be ommited, switch directly to next phase */
+    if (xfer->dataSize == 0U)
+    {
+        handle->state = (uint8_t)kStopState;
+    }
+
+    if (0UL != (xfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr))
+    {
+        if (0UL != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        if (0UL != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        /* Issue 0x7E as start. */
+        result = I3C_MasterStart(base, xfer->busType, 0x7E, kI3C_Write);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+
+        result = I3C_MasterWaitForCtrlDone(base, false);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+    }
+
+    /* Handle no start option. */
+    if (0U != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag))
+    {
+        /* No need to send start flag, directly go to send command or data */
+        if (xfer->subaddressSize > 0UL)
+        {
+            handle->state = (uint8_t)kSendCommandState;
+        }
+        else
+        {
+            if (direction == kI3C_Write)
+            {
+                /* Next state, send data. */
+                handle->state = (uint8_t)kTransmitDataState;
+            }
+            else
+            {
+                /* Only support write with no stop signal. */
+                return kStatus_InvalidArgument;
+            }
+        }
+    }
+    else
+    {
+        if (xfer->subaddressSize != 0U)
+        {
+            handle->state = (uint8_t)kSendCommandState;
+        }
+        else
+        {
+            if (handle->transfer.direction == kI3C_Write)
+            {
+                handle->state = (uint8_t)kTransmitDataState;
+            }
+            else if (handle->transfer.direction == kI3C_Read)
+            {
+                handle->state = (uint8_t)kReceiveDataState;
+            }
+            else
+            {
+                return kStatus_InvalidArgument;
+            }
+        }
+
+        if (handle->transfer.direction == kI3C_Read)
+        {
+            I3C_MasterRunEDMATransfer(base, handle, xfer->data, xfer->dataSize, kI3C_Read);
+        }
+
+        if (handle->state != (uint8_t)kStopState)
+        {
+            /* If repeated start is requested, send repeated start. */
+            if (0U != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag))
+            {
+                result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, direction);
+            }
+            else /* For normal transfer, send start. */
+            {
+                result = I3C_MasterStart(base, xfer->busType, xfer->slaveAddress, direction);
+            }
+        }
+    }
+
+    I3C_MasterTransferEDMAHandleIRQ(base, handle);
+    return result;
+}
+
+static void I3C_MasterRunEDMATransfer(
+    I3C_Type *base, i3c_master_edma_handle_t *handle, void *data, size_t dataSize, i3c_direction_t direction)
+{
+    bool isEnableTxDMA = false;
+    bool isEnableRxDMA = false;
+    edma_transfer_config_t xferConfig;
+    uint32_t instance;
+    uint32_t address;
+    uint32_t width;
+
+    handle->transferCount = dataSize;
+
+    switch (direction)
+    {
+        case kI3C_Write:
+            if (dataSize != 1U)
+            {
+                address = (uint32_t)&base->MWDATAB1;
+                /* Cause controller sends command and data with same interface, need special buffer to store the END byte. */
+                instance = I3C_GetInstance(base);
+                i3cEndByte[instance] = *(uint8_t *)((uint32_t)(uint32_t *)data + dataSize - 1U);
+                dataSize--;
+            }
+            else
+            {
+                address = (uint32_t)&base->MWDATABE;
+            }
+            EDMA_PrepareTransfer(&xferConfig, data, sizeof(uint8_t), (uint32_t *)address, sizeof(uint8_t), 1, dataSize,
+                                 kEDMA_MemoryToPeripheral);
+            (void)EDMA_SubmitTransfer(handle->txDmaHandle, &xferConfig);
+            EDMA_StartTransfer(handle->txDmaHandle);
+            isEnableTxDMA = true;
+            width         = 1U;
+            break;
+
+        case kI3C_Read:
+#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086)
+            /* ERRATA052086: Soc integration issue results in target misses the last DMA request to copy the
+            last one byte from controler when transmission data size is > 1 byte. Resolution: Triggering DMA
+            interrupt one byte in advance, then receive the last one byte data after DMA transmission finishes. */
+            if (dataSize > 1U)
+            {
+                dataSize--;
+            }
+#endif
+            address = (uint32_t)&base->MRDATAB;
+            EDMA_PrepareTransfer(&xferConfig, (uint32_t *)address, sizeof(uint8_t), data, sizeof(uint8_t), 1, dataSize,
+                                 kEDMA_PeripheralToMemory);
+            (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig);
+            EDMA_StartTransfer(handle->rxDmaHandle);
+            isEnableRxDMA = true;
+            width         = 1U;
+            break;
+
+        default:
+            /* This should never happen */
+            assert(false);
+            break;
+    }
+
+    I3C_MasterEnableDMA(base, isEnableTxDMA, isEnableRxDMA, width);
+}
+
+static status_t I3C_MasterRunTransferStateMachineEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, bool *isDone)
+{
+    uint32_t status;
+    uint32_t errStatus;
+    status_t result = kStatus_Success;
+    i3c_master_transfer_t *xfer;
+    size_t rxCount      = 0;
+    bool state_complete = false;
+
+    /* Set default isDone return value. */
+    *isDone = false;
+
+    /* Check for errors. */
+    status = (uint32_t)I3C_MasterGetPendingInterrupts(base);
+    I3C_MasterClearStatusFlags(base, status);
+
+    i3c_master_state_t masterState = I3C_MasterGetState(base);
+    errStatus                      = I3C_MasterGetErrorStatusFlags(base);
+    result                         = I3C_MasterCheckAndClearError(base, errStatus);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    if (0UL != (status & (uint32_t)kI3C_MasterSlave2MasterFlag))
+    {
+        if (handle->callback.slave2Master != NULL)
+        {
+            handle->callback.slave2Master(base, handle->userData);
+        }
+    }
+
+    if ((0UL != (status & (uint32_t)kI3C_MasterSlaveStartFlag)) && (handle->transfer.busType != kI3C_TypeI2C))
+    {
+        handle->state = (uint8_t)kSlaveStartState;
+    }
+
+    if ((masterState == kI3C_MasterStateIbiRcv) || (masterState == kI3C_MasterStateIbiAck))
+    {
+        handle->state = (uint8_t)kIBIWonState;
+    }
+
+    if (handle->state == (uint8_t)kIdleState)
+    {
+        return result;
+    }
+
+    if (handle->state == (uint8_t)kIBIWonState)
+    {
+        /* Get fifo counts and compute room in tx fifo. */
+        rxCount = (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK) >> I3C_MDATACTRL_RXCOUNT_SHIFT;
+    }
+
+    /* Get pointer to private data. */
+    xfer = &handle->transfer;
+
+    while (!state_complete)
+    {
+        /* Execute the state. */
+        switch (handle->state)
+        {
+            case (uint8_t)kSlaveStartState:
+                /* Emit start + 0x7E */
+                I3C_MasterEmitRequest(base, kI3C_RequestAutoIbi);
+                handle->state  = (uint8_t)kIBIWonState;
+                state_complete = true;
+                break;
+
+            case (uint8_t)kIBIWonState:
+                if (masterState == kI3C_MasterStateIbiAck)
+                {
+                    handle->ibiType = I3C_GetIBIType(base);
+                    if (handle->callback.ibiCallback != NULL)
+                    {
+                        handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiAckNackPending);
+                    }
+                    else
+                    {
+                        I3C_MasterEmitIBIResponse(base, kI3C_IbiRespNack);
+                    }
+                }
+
+                /* Make sure there is data in the rx fifo. */
+                if (0UL != rxCount)
+                {
+                    if ((handle->ibiBuff == NULL) && (handle->callback.ibiCallback != NULL))
+                    {
+                        handle->callback.ibiCallback(base, handle, kI3C_IbiNormal, kI3C_IbiDataBuffNeed);
+                    }
+                    uint8_t tempData = (uint8_t)base->MRDATAB;
+                    if (handle->ibiBuff != NULL)
+                    {
+                        handle->ibiBuff[handle->ibiPayloadSize++] = tempData;
+                    }
+                    rxCount--;
+                    break;
+                }
+                else if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag))
+                {
+                    handle->ibiType    = I3C_GetIBIType(base);
+                    handle->ibiAddress = I3C_GetIBIAddress(base);
+                    state_complete     = true;
+                    result             = kStatus_I3C_IBIWon;
+                }
+                else
+                {
+                    state_complete = true;
+                }
+                break;
+
+            case (uint8_t)kSendCommandState:
+                I3C_MasterRunEDMATransfer(base, handle, handle->subaddressBuffer, handle->subaddressCount, kI3C_Write);
+
+                if ((xfer->direction == kI3C_Read) || (0UL == xfer->dataSize))
+                {
+                    if (0UL == xfer->dataSize)
+                    {
+                        handle->state = (uint8_t)kWaitForCompletionState;
+                    }
+                    else
+                    {
+                        /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */
+                        handle->state = (uint8_t)kWaitRepeatedStartCompleteState;
+                    }
+                }
+                else
+                {
+                    /* Next state, transfer data. */
+                    handle->state = (uint8_t)kTransmitDataState;
+                }
+
+                state_complete = true;
+                break;
+
+            case (uint8_t)kWaitRepeatedStartCompleteState:
+                /* We stay in this state until the maste complete. */
+                if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag))
+                {
+                    handle->state = (uint8_t)kReceiveDataState;
+                    /* Send repeated start and slave address. */
+                    result = I3C_MasterRepeatedStart(base, xfer->busType, xfer->slaveAddress, kI3C_Read);
+                }
+
+                state_complete = true;
+                break;
+
+            case (uint8_t)kTransmitDataState:
+                I3C_MasterRunEDMATransfer(base, handle, xfer->data, xfer->dataSize, kI3C_Write);
+                handle->state = (uint8_t)kWaitForCompletionState;
+
+                state_complete = true;
+                break;
+
+            case (uint8_t)kReceiveDataState:
+                /* Do DMA read. */
+                handle->state = (uint8_t)kWaitForCompletionState;
+
+                state_complete = true;
+                break;
+
+            case (uint8_t)kWaitForCompletionState:
+                /* We stay in this state until the maste complete. */
+                if (0UL != (status & (uint32_t)kI3C_MasterCompleteFlag))
+                {
+                    handle->state = (uint8_t)kStopState;
+                }
+                else
+                {
+                    state_complete = true;
+                }
+                break;
+
+            case (uint8_t)kStopState:
+                /* Only issue a stop transition if the caller requested it. */
+                if (0UL == (xfer->flags & (uint32_t)kI3C_TransferNoStopFlag))
+                {
+                    if (xfer->busType == kI3C_TypeI3CDdr)
+                    {
+                        I3C_MasterEmitRequest(base, kI3C_RequestForceExit);
+                    }
+                    else
+                    {
+                        I3C_MasterEmitRequest(base, kI3C_RequestEmitStop);
+                        result = I3C_MasterWaitForCtrlDone(base, false);
+                    }
+                }
+                *isDone        = true;
+                state_complete = true;
+                break;
+
+            default:
+                assert(false);
+                break;
+        }
+    }
+    return result;
+}
+
+void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base,
+                                        i3c_master_edma_handle_t *handle,
+                                        const i3c_master_edma_callback_t *callback,
+                                        void *userData,
+                                        edma_handle_t *rxDmaHandle,
+                                        edma_handle_t *txDmaHandle)
+{
+    uint32_t instance;
+
+    assert(NULL != handle);
+
+    /* Clear out the handle. */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Look up instance number */
+    instance = I3C_GetInstance(base);
+
+    handle->base        = base;
+    handle->txDmaHandle = txDmaHandle;
+    handle->rxDmaHandle = rxDmaHandle;
+    handle->callback    = *callback;
+    handle->userData    = userData;
+
+    /* Save this handle for IRQ use. */
+    s_i3cMasterHandle[instance] = handle;
+
+    /* Set irq handler. */
+    s_i3cMasterIsr = I3C_MasterTransferEDMAHandleIRQ;
+
+    EDMA_SetCallback(handle->rxDmaHandle, I3C_MasterTransferEDMACallbackRx, handle);
+    EDMA_SetCallback(handle->txDmaHandle, I3C_MasterTransferEDMACallbackTx, handle);
+
+    /* Clear all flags. */
+    I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags);
+    I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags);
+    /* Reset fifos. These flags clear automatically. */
+    base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK;
+
+    /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC.
+     In some cases the I3C IRQ is configured through INTMUX, user needs to enable
+     INTMUX IRQ in application code. */
+    (void)EnableIRQ(kI3cIrqs[instance]);
+
+    /* Clear internal IRQ enables and enable NVIC IRQ. */
+    I3C_MasterEnableInterrupts(base, (uint32_t)kMasterDMAIrqFlags);
+}
+
+/*!
+ * brief Performs a non-blocking DMA transaction on the I2C/I3C bus.
+ *
+ * param base The I3C peripheral base address.
+ * param handle Pointer to the I3C master driver handle.
+ * param transfer The pointer to the transfer descriptor.
+ * retval #kStatus_Success The transaction was started successfully.
+ * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking
+ *      transaction is already in progress.
+ */
+status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer)
+{
+    assert(NULL != handle);
+    assert(NULL != transfer);
+    assert(transfer->subaddressSize <= sizeof(transfer->subaddress));
+    i3c_master_state_t masterState = I3C_MasterGetState(base);
+    bool checkDdrState             = false;
+
+    /* Return busy if another transaction is in progress. */
+    if (handle->state != (uint8_t)kIdleState)
+    {
+        return kStatus_I3C_Busy;
+    }
+
+    /* Return an error if the bus is already in use not by us. */
+    checkDdrState = (transfer->busType == kI3C_TypeI3CDdr) ? (masterState != kI3C_MasterStateDdr) : true;
+    if ((masterState != kI3C_MasterStateIdle) && (masterState != kI3C_MasterStateNormAct) && checkDdrState)
+    {
+        return kStatus_I3C_Busy;
+    }
+
+    /* Disable I3C IRQ sources while we configure stuff. */
+    I3C_MasterDisableInterrupts(
+        base, ((uint32_t)kMasterDMAIrqFlags | (uint32_t)kI3C_MasterRxReadyFlag | (uint32_t)kI3C_MasterTxReadyFlag));
+
+    /* Save transfer into handle. */
+    handle->transfer = *transfer;
+
+    /* Configure IBI response type. */
+    base->MCTRL &= ~I3C_MCTRL_IBIRESP_MASK;
+    base->MCTRL |= I3C_MCTRL_IBIRESP(transfer->ibiResponse);
+
+    /* Clear all flags. */
+    I3C_MasterClearErrorStatusFlags(base, (uint32_t)kMasterErrorFlags);
+    I3C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags);
+    /* Reset fifos. These flags clear automatically. */
+    base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK;
+
+    /* Generate commands to send. */
+    (void)I3C_MasterInitTransferStateMachineEDMA(base, handle);
+
+    /* Enable I3C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */
+    I3C_MasterEnableInterrupts(base, (uint32_t)(kMasterDMAIrqFlags));
+
+    if (transfer->busType == kI3C_TypeI2C)
+    {
+        I3C_MasterDisableInterrupts(base, (uint32_t)kI3C_MasterSlaveStartFlag);
+    }
+
+    return kStatus_Success;
+}
+
+void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle)
+{
+    i3c_master_edma_handle_t *handle = (i3c_master_edma_handle_t *)i3cHandle;
+
+    bool isDone;
+    status_t result;
+
+    /* Don't do anything if we don't have a valid handle. */
+    if (NULL == handle)
+    {
+        return;
+    }
+
+    result = I3C_MasterRunTransferStateMachineEDMA(base, handle, &isDone);
+
+    if (handle->state == (uint8_t)kIdleState)
+    {
+        return;
+    }
+
+    if (isDone || (result != kStatus_Success))
+    {
+        /* XXX need to handle data that may be in rx fifo below watermark level? */
+
+        /* XXX handle error, terminate xfer */
+        if ((result == kStatus_I3C_Nak) || (result == kStatus_I3C_IBIWon))
+        {
+            I3C_MasterEmitRequest(base, kI3C_RequestEmitStop);
+            (void)I3C_MasterWaitForCtrlDone(base, false);
+        }
+
+        /* Set handle to idle state. */
+        handle->state = (uint8_t)kIdleState;
+
+        /* Invoke IBI user callback. */
+        if ((result == kStatus_I3C_IBIWon) && (handle->callback.ibiCallback != NULL))
+        {
+            handle->callback.ibiCallback(base, handle, handle->ibiType, kI3C_IbiReady);
+            handle->ibiPayloadSize = 0;
+        }
+
+        /* Invoke callback. */
+        if (NULL != handle->callback.transferComplete)
+        {
+            handle->callback.transferComplete(base, handle, result, handle->userData);
+        }
+    }
+}
+
+/*!
+ * brief Get master transfer status during a dma non-blocking transfer
+ *
+ * param base I3C peripheral base address
+ * param handle pointer to i2c_master_edma_handle_t structure
+ * param count Number of bytes transferred so far by the non-blocking transaction.
+ */
+status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count)
+{
+    assert(handle != NULL);
+
+    if (NULL == count)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Catch when there is not an active transfer. */
+    if (handle->state == (uint8_t)kIdleState)
+    {
+        *count = 0;
+        return kStatus_NoTransferInProgress;
+    }
+
+    /* There is no necessity to disable interrupts as we read a single integer value */
+    i3c_direction_t dir = handle->transfer.direction;
+
+    if (dir == kI3C_Read)
+    {
+        *count = handle->transferCount -
+                 1U * EDMA_GetRemainingMajorLoopCount(handle->rxDmaHandle->base, handle->rxDmaHandle->channel);
+    }
+    else
+    {
+        *count = handle->transferCount -
+                 1U * EDMA_GetRemainingMajorLoopCount(handle->txDmaHandle->base, handle->txDmaHandle->channel);
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Abort a master edma non-blocking transfer in a early time
+ *
+ * param base I3C peripheral base address
+ * param handle pointer to i2c_master_edma_handle_t structure
+ */
+void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle)
+{
+    if (handle->state != (uint8_t)kIdleState)
+    {
+        EDMA_AbortTransfer(handle->txDmaHandle);
+        EDMA_AbortTransfer(handle->rxDmaHandle);
+
+        I3C_MasterEnableDMA(base, false, false, 0);
+
+        /* Reset fifos. These flags clear automatically. */
+        base->MDATACTRL |= I3C_MDATACTRL_FLUSHTB_MASK | I3C_MDATACTRL_FLUSHFB_MASK;
+
+        /* Send a stop command to finalize the transfer. */
+        (void)I3C_MasterStop(base);
+
+        /* Reset handle. */
+        handle->state = (uint8_t)kIdleState;
+    }
+}
+
+static void I3C_SlaveTransferEDMACallback(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds)
+{
+    i3c_slave_edma_handle_t *i3cHandle = (i3c_slave_edma_handle_t *)param;
+
+    if (transferDone)
+    {
+        /* Simply disable dma enablement */
+        if (i3cHandle->txDmaHandle == dmaHandle)
+        {
+            i3cHandle->base->SDMACTRL &= ~I3C_SDMACTRL_DMATB_MASK;
+
+            if (i3cHandle->transfer.txDataSize > 1U)
+            {
+                /* Ensure there's space in the Tx FIFO. */
+                while ((i3cHandle->base->SDATACTRL & I3C_SDATACTRL_TXFULL_MASK) != 0U)
+                {
+                }
+                /* Send the last byte. */
+                i3cHandle->base->SWDATABE = *(uint8_t *)((uintptr_t)i3cHandle->transfer.txData + i3cHandle->transfer.txDataSize - 1U);
+            }
+        }
+        else
+        {
+#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086)
+            if (i3cHandle->transfer.rxDataSize > 1U)
+            {
+                size_t rxCount;
+                /* Read out the last byte data. */
+                do
+                {
+                    I3C_SlaveGetFifoCounts(i3cHandle->base, &rxCount, NULL);
+                } while (rxCount == 0U);
+                *(uint8_t *)((uintptr_t)i3cHandle->transfer.rxData + i3cHandle->transfer.rxDataSize - 1U) =
+                    (uint8_t)i3cHandle->base->SRDATAB;
+            }
+#endif
+            i3cHandle->base->SDMACTRL &= ~I3C_SDMACTRL_DMAFB_MASK;
+        }
+    }
+}
+
+/*!
+ * brief Create a new handle for the I3C slave DMA APIs.
+ *
+ * The creation of a handle is for use with the DMA APIs. Once a handle
+ * is created, there is not a corresponding destroy handle. If the user wants to
+ * terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called.
+ *
+ * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle
+ * parameter is ignored and may be set to NULL.
+ *
+ * param base The I3C peripheral base address.
+ * param handle Pointer to the I3C slave driver handle.
+ * param callback User provided pointer to the asynchronous callback function.
+ * param userData User provided pointer to the application callback data.
+ * param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function.
+ * param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function.
+ */
+void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base,
+                                       i3c_slave_edma_handle_t *handle,
+                                       i3c_slave_edma_callback_t callback,
+                                       void *userData,
+                                       edma_handle_t *rxDmaHandle,
+                                       edma_handle_t *txDmaHandle)
+{
+    uint32_t instance;
+
+    assert(NULL != handle);
+
+    /* Clear out the handle. */
+    (void)memset(handle, 0, sizeof(*handle));
+
+    /* Look up instance number */
+    instance = I3C_GetInstance(base);
+
+    handle->base        = base;
+    handle->txDmaHandle = txDmaHandle;
+    handle->rxDmaHandle = rxDmaHandle;
+    handle->callback    = callback;
+    handle->userData    = userData;
+
+    /* Save this handle for IRQ use. */
+    s_i3cSlaveHandle[instance] = handle;
+
+    /* Set irq handler. */
+    s_i3cSlaveIsr = I3C_SlaveTransferEDMAHandleIRQ;
+
+    EDMA_SetCallback(handle->rxDmaHandle, I3C_SlaveTransferEDMACallback, handle);
+    EDMA_SetCallback(handle->txDmaHandle, I3C_SlaveTransferEDMACallback, handle);
+
+    /* Clear internal IRQ enables and enable NVIC IRQ. */
+    I3C_SlaveDisableInterrupts(base, (uint32_t)kSlaveDMAIrqFlags);
+
+    /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC.
+     In some cases the I3C IRQ is configured through INTMUX, user needs to enable
+     INTMUX IRQ in application code. */
+    (void)EnableIRQ(kI3cIrqs[instance]);
+
+    /* Enable IRQ. */
+    I3C_SlaveEnableInterrupts(base, (uint32_t)kSlaveDMAIrqFlags);
+}
+
+static void I3C_SlavePrepareTxEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle)
+{
+    edma_transfer_config_t txConfig;
+    uint32_t *txFifoBase;
+    i3c_slave_edma_transfer_t *xfer = &handle->transfer;
+
+    if (xfer->txDataSize == 1U)
+    {
+        txFifoBase = (uint32_t *)(uintptr_t)&base->SWDATABE;
+        EDMA_PrepareTransfer(&txConfig, xfer->txData, 1, (void *)txFifoBase, 1, 1, xfer->txDataSize,
+                             kEDMA_MemoryToPeripheral);
+    }
+    else
+    {
+        txFifoBase = (uint32_t *)(uintptr_t)&base->SWDATAB1;
+        EDMA_PrepareTransfer(&txConfig, xfer->txData, 1, (void *)txFifoBase, 1, 1, xfer->txDataSize - 1U,
+                             kEDMA_MemoryToPeripheral);
+    }
+
+    (void)EDMA_SubmitTransfer(handle->txDmaHandle, &txConfig);
+    EDMA_StartTransfer(handle->txDmaHandle);
+}
+
+static void I3C_SlavePrepareRxEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle)
+{
+    uint32_t *rxFifoBase            = (uint32_t *)(uintptr_t)&base->SRDATAB;
+    i3c_slave_edma_transfer_t *xfer = &handle->transfer;
+    size_t dataSize                 = xfer->rxDataSize;
+    edma_transfer_config_t rxConfig;
+
+#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086)
+    /* ERRATA052086: Soc integration issue results in target misses the last DMA request to copy the
+    last one byte from controler when transmission data size is > 1 byte. Resolution: Triggering DMA
+    interrupt one byte in advance, then receive the last one byte data after DMA transmission finishes. */
+    if (dataSize > 1U)
+    {
+        dataSize--;
+    }
+#endif
+
+    EDMA_PrepareTransfer(&rxConfig, (void *)rxFifoBase, 1, xfer->rxData, 1, 1, dataSize,
+                         kEDMA_PeripheralToMemory);
+    (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &rxConfig);
+    EDMA_StartTransfer(handle->rxDmaHandle);
+}
+
+/*!
+ * brief Prepares for a non-blocking DMA-based transaction on the I3C bus.
+ *
+ * The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when
+ * there's bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned
+ * with master application to ensure the transfer is executed as expected.
+ * Callback specified when the @a handle was created is invoked when the transaction has completed.
+ *
+ * param base The I3C peripheral base address.
+ * param handle Pointer to the I3C slave driver handle.
+ * param transfer The pointer to the transfer descriptor.
+ * param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. The transmit and receive events is not allowed to be enabled.
+ * retval kStatus_Success The transaction was started successfully.
+ * retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA
+ *      transaction is already in progress.
+ * retval #kStatus_Fail The transaction can't be set.
+ */
+status_t I3C_SlaveTransferEDMA(I3C_Type *base,
+                               i3c_slave_edma_handle_t *handle,
+                               i3c_slave_edma_transfer_t *transfer,
+                               uint32_t eventMask)
+{
+    assert(NULL != handle);
+    assert(NULL != transfer);
+
+    bool txDmaEn = false, rxDmaEn = false;
+    uint32_t width;
+
+    if (handle->isBusy)
+    {
+        return kStatus_I3C_Busy;
+    }
+    /* Clear all flags. */
+    I3C_SlaveClearErrorStatusFlags(base, (uint32_t)kSlaveErrorFlags);
+    I3C_SlaveClearStatusFlags(base, (uint32_t)kSlaveClearFlags);
+    /* Reset fifos. These flags clear automatically. */
+    base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK;
+
+    handle->transfer = *transfer;
+
+    /* Set up event mask. */
+    handle->eventMask = eventMask;
+
+    if ((transfer->txData != NULL) && (transfer->txDataSize != 0U))
+    {
+        I3C_SlavePrepareTxEDMA(base, handle);
+        txDmaEn = true;
+        width   = 1U;
+    }
+
+    if ((transfer->rxData != NULL) && (transfer->rxDataSize != 0U))
+    {
+        I3C_SlavePrepareRxEDMA(base, handle);
+        rxDmaEn = true;
+        width   = 1U;
+    }
+
+    if (txDmaEn || rxDmaEn)
+    {
+        I3C_SlaveEnableDMA(base, txDmaEn, rxDmaEn, width);
+        return kStatus_Success;
+    }
+    else
+    {
+        return kStatus_Fail;
+    }
+}
+
+void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle)
+{
+    uint32_t flags;
+    uint32_t errFlags;
+    i3c_slave_edma_transfer_t *xfer;
+
+    i3c_slave_edma_handle_t *handle = (i3c_slave_edma_handle_t *)i3cHandle;
+    /* Check for a valid handle in case of a spurious interrupt. */
+    if (NULL == handle)
+    {
+        return;
+    }
+
+    xfer = &handle->transfer;
+
+    /* Get status flags. */
+    flags    = I3C_SlaveGetStatusFlags(base);
+    errFlags = I3C_SlaveGetErrorStatusFlags(base);
+
+    /* Clear status flags. */
+    I3C_SlaveClearStatusFlags(base, flags);
+
+    if (0UL != (errFlags & (uint32_t)kSlaveErrorFlags))
+    {
+        xfer->event            = (uint32_t)kI3C_SlaveCompletionEvent;
+        xfer->completionStatus = I3C_SlaveCheckAndClearError(base, errFlags);
+
+        if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveCompletionEvent)) && (NULL != handle->callback))
+        {
+            handle->callback(base, xfer, handle->userData);
+        }
+        return;
+    }
+
+    if (0UL != (flags & (uint32_t)kI3C_SlaveEventSentFlag))
+    {
+        xfer->event = (uint32_t)kI3C_SlaveRequestSentEvent;
+        if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback))
+        {
+            handle->callback(base, xfer, handle->userData);
+        }
+    }
+
+    if (0UL != (flags & (uint32_t)kI3C_SlaveReceivedCCCFlag))
+    {
+        handle->isBusy = true;
+        xfer->event    = (uint32_t)kI3C_SlaveReceivedCCCEvent;
+        if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback))
+        {
+            handle->callback(base, xfer, handle->userData);
+        }
+    }
+
+    if (0UL != (flags & (uint32_t)kI3C_SlaveBusStopFlag))
+    {
+        if (handle->isBusy == true)
+        {
+            xfer->event            = (uint32_t)kI3C_SlaveCompletionEvent;
+            xfer->completionStatus = kStatus_Success;
+            handle->isBusy         = false;
+
+            if ((0UL != (handle->eventMask & xfer->event)) && (NULL != handle->callback))
+            {
+                handle->callback(base, xfer, handle->userData);
+            }
+            I3C_SlaveTransferAbortEDMA(base, handle);
+        }
+        else
+        {
+            return;
+        }
+    }
+
+    if (0UL != (flags & (uint32_t)kI3C_SlaveMatchedFlag))
+    {
+        xfer->event    = (uint32_t)kI3C_SlaveAddressMatchEvent;
+        handle->isBusy = true;
+        if ((0UL != (handle->eventMask & (uint32_t)kI3C_SlaveAddressMatchEvent)) && (NULL != handle->callback))
+        {
+            handle->callback(base, xfer, handle->userData);
+        }
+    }
+}
+
+/*!
+ * brief Abort a slave dma non-blocking transfer in a early time
+ *
+ * param base I3C peripheral base address
+ * param handle pointer to i3c_slave_edma_handle_t structure
+ */
+void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle)
+{
+    if (handle->isBusy != false)
+    {
+        EDMA_AbortTransfer(handle->txDmaHandle);
+        EDMA_AbortTransfer(handle->rxDmaHandle);
+
+        I3C_SlaveEnableDMA(base, false, false, 0);
+
+        /* Reset fifos. These flags clear automatically. */
+        base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK;
+    }
+}

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_i3c_edma.h

@@ -0,0 +1,279 @@
+/*
+ * Copyright 2022-2023 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_I3C_EDMA_H_
+#define FSL_I3C_EDMA_H_
+
+#include "fsl_i3c.h"
+#include "fsl_edma.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief I3C EDMA driver version. */
+#define FSL_I3C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 9))
+/*! @} */
+
+/*!
+ * @addtogroup i3c_master_edma_driver
+ * @{
+ */
+
+/* Forward declaration of the transfer descriptor and handle typedefs. */
+typedef struct _i3c_master_edma_handle i3c_master_edma_handle_t;
+
+/*! @brief i3c master callback functions. */
+typedef struct _i3c_master_edma_callback
+{
+    void (*slave2Master)(I3C_Type *base, void *userData); /*!< Transfer complete callback */
+    void (*ibiCallback)(I3C_Type *base,
+                        i3c_master_edma_handle_t *handle,
+                        i3c_ibi_type_t ibiType,
+                        i3c_ibi_state_t ibiState); /*!< IBI event callback */
+    void (*transferComplete)(I3C_Type *base,
+                             i3c_master_edma_handle_t *handle,
+                             status_t status,
+                             void *userData); /*!< Transfer complete callback */
+} i3c_master_edma_callback_t;
+/*!
+ * @brief Driver handle for master EDMA APIs.
+ * @note The contents of this structure are private and subject to change.
+ */
+struct _i3c_master_edma_handle
+{
+    I3C_Type *base;                      /*!< I3C base pointer. */
+    uint8_t state;                       /*!< Transfer state machine current state. */
+    uint32_t transferCount;              /*!< Indicates progress of the transfer */
+    uint8_t subaddressBuffer[4];         /*!< Saving subaddress command. */
+    uint8_t subaddressCount;             /*!< Saving command count. */
+    i3c_master_transfer_t transfer;      /*!< Copy of the current transfer info. */
+    i3c_master_edma_callback_t callback; /*!< Callback function pointer. */
+    void *userData;                      /*!< Application data passed to callback. */
+    edma_handle_t *rxDmaHandle;          /*!< Handle for receive DMA channel. */
+    edma_handle_t *txDmaHandle;          /*!< Handle for transmit DMA channel. */
+    uint8_t ibiAddress;                  /*!< Slave address which request IBI. */
+    uint8_t *ibiBuff;                    /*!< Pointer to IBI buffer to keep ibi bytes. */
+    size_t ibiPayloadSize;               /*!< IBI payload size. */
+    i3c_ibi_type_t ibiType;              /*!< IBI type. */
+};
+
+/*! @} */
+
+/*!
+ * @addtogroup i3c_slave_edma_driver
+ * @{
+ */
+/* Forward declaration of the transfer descriptor and handle typedefs. */
+typedef struct _i3c_slave_edma_handle i3c_slave_edma_handle_t;
+
+/*! @brief I3C slave transfer structure */
+typedef struct _i3c_slave_edma_transfer
+{
+    uint32_t event;            /*!< Reason the callback is being invoked. */
+    uint8_t *txData;           /*!< Transfer buffer */
+    size_t txDataSize;         /*!< Transfer size */
+    uint8_t *rxData;           /*!< Transfer buffer */
+    size_t rxDataSize;         /*!< Transfer size */
+    status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for
+                                  #kI3C_SlaveCompletionEvent. */
+} i3c_slave_edma_transfer_t;
+
+/*!
+ * @brief Slave event callback function pointer type.
+ *
+ * This callback is used only for the slave DMA transfer API.
+ *
+ * @param base Base address for the I3C instance on which the event occurred.
+ * @param handle   Pointer to slave DMA transfer handle.
+ * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback.
+ * @param userData Arbitrary pointer-sized value passed from the application.
+ */
+typedef void (*i3c_slave_edma_callback_t)(I3C_Type *base, i3c_slave_edma_transfer_t *transfer, void *userData);
+/*!
+ * @brief I3C slave edma handle structure.
+ * @note The contents of this structure are private and subject to change.
+ */
+struct _i3c_slave_edma_handle
+{
+    I3C_Type *base;                     /*!< I3C base pointer. */
+    i3c_slave_edma_transfer_t transfer; /*!< I3C slave transfer copy. */
+    bool isBusy;                        /*!< Whether transfer is busy. */
+    bool wasTransmit;                   /*!< Whether the last transfer was a transmit. */
+    uint32_t eventMask;                 /*!< Mask of enabled events. */
+    i3c_slave_edma_callback_t callback; /*!< Callback function called at transfer event. */
+    edma_handle_t *rxDmaHandle;         /*!< Handle for receive DMA channel. */
+    edma_handle_t *txDmaHandle;         /*!< Handle for transmit DMA channel. */
+    void *userData;                     /*!< Callback parameter passed to callback. */
+};
+/*! @} */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @addtogroup i3c_master_edma_driver
+ * @{
+ */
+
+/*! @name Master DMA */
+/*! @{ */
+
+/*!
+ * @brief Create a new handle for the I3C master DMA APIs.
+ *
+ * The creation of a handle is for use with the DMA APIs. Once a handle
+ * is created, there is not a corresponding destroy handle. If the user wants to
+ * terminate a transfer, the I3C_MasterTransferAbortDMA() API shall be called.
+ *
+ * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle
+ * parameter is ignored and may be set to NULL.
+ *
+ * @param base The I3C peripheral base address.
+ * @param handle Pointer to the I3C master driver handle.
+ * @param callback User provided pointer to the asynchronous callback function.
+ * @param userData User provided pointer to the application callback data.
+ * @param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function.
+ * @param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function.
+ */
+void I3C_MasterTransferCreateHandleEDMA(I3C_Type *base,
+                                        i3c_master_edma_handle_t *handle,
+                                        const i3c_master_edma_callback_t *callback,
+                                        void *userData,
+                                        edma_handle_t *rxDmaHandle,
+                                        edma_handle_t *txDmaHandle);
+
+/*!
+ * @brief Performs a non-blocking DMA-based transaction on the I3C bus.
+ *
+ * The callback specified when the @a handle was created is invoked when the transaction has
+ * completed.
+ *
+ * @param base The I3C peripheral base address.
+ * @param handle Pointer to the I3C master driver handle.
+ * @param transfer The pointer to the transfer descriptor.
+ * @retval kStatus_Success The transaction was started successfully.
+ * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA
+ *      transaction is already in progress.
+ */
+status_t I3C_MasterTransferEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, i3c_master_transfer_t *transfer);
+
+/*!
+ * @brief Returns number of bytes transferred so far.
+ *
+ * @param base The I3C peripheral base address.
+ * @param handle Pointer to the I3C master driver handle.
+ * @param[out] count Number of bytes transferred so far by the non-blocking transaction.
+ * @retval kStatus_Success
+ * @retval kStatus_NoTransferInProgress There is not a DMA transaction currently in progress.
+ */
+status_t I3C_MasterTransferGetCountEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle, size_t *count);
+
+/*!
+ * @brief Terminates a non-blocking I3C master transmission early.
+ *
+ * @note It is not safe to call this function from an IRQ handler that has a higher priority than the
+ *      DMA peripheral's IRQ priority.
+ *
+ * @param base The I3C peripheral base address.
+ * @param handle Pointer to the I3C master driver handle.
+ */
+void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handle);
+
+/*!
+ * @brief Reusable routine to handle master interrupts.
+ * @note This function does not need to be called unless you are reimplementing the
+ *  nonblocking API's interrupt handler routines to add special functionality.
+ * @param base The I3C peripheral base address.
+ * @param i3cHandle Pointer to the I3C master DMA driver handle.
+ */
+void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle);
+/*! @} */
+
+/*! @} */
+
+/*!
+ * @addtogroup i3c_slave_edma_driver
+ * @{
+ */
+
+/*! @name Slave DMA */
+/*! @{ */
+/*!
+ * @brief Create a new handle for the I3C slave DMA APIs.
+ *
+ * The creation of a handle is for use with the DMA APIs. Once a handle
+ * is created, there is not a corresponding destroy handle. If the user wants to
+ * terminate a transfer, the I3C_SlaveTransferAbortDMA() API shall be called.
+ *
+ * For devices where the I3C send and receive DMA requests are OR'd together, the @a txDmaHandle
+ * parameter is ignored and may be set to NULL.
+ *
+ * @param base The I3C peripheral base address.
+ * @param handle Pointer to the I3C slave driver handle.
+ * @param callback User provided pointer to the asynchronous callback function.
+ * @param userData User provided pointer to the application callback data.
+ * @param rxDmaHandle Handle for the DMA receive channel. Created by the user prior to calling this function.
+ * @param txDmaHandle Handle for the DMA transmit channel. Created by the user prior to calling this function.
+ */
+void I3C_SlaveTransferCreateHandleEDMA(I3C_Type *base,
+                                       i3c_slave_edma_handle_t *handle,
+                                       i3c_slave_edma_callback_t callback,
+                                       void *userData,
+                                       edma_handle_t *rxDmaHandle,
+                                       edma_handle_t *txDmaHandle);
+
+/*!
+ * @brief Prepares for a non-blocking DMA-based transaction on the I3C bus.
+ *
+ * The API will do DMA configuration according to the input transfer descriptor, and the data will be transferred when
+ * there's bus master requesting transfer from/to this slave. So the timing of call to this API need be aligned
+ * with master application to ensure the transfer is executed as expected.
+ * Callback specified when the @a handle was created is invoked when the transaction has completed.
+ *
+ * @param base The I3C peripheral base address.
+ * @param handle Pointer to the I3C slave driver handle.
+ * @param transfer The pointer to the transfer descriptor.
+ * @param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify
+ *      which events to send to the callback. The transmit and receive events is not allowed to be enabled.
+ * @retval kStatus_Success The transaction was started successfully.
+ * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or another DMA
+ *      transaction is already in progress.
+ * @retval #kStatus_Fail The transaction can't be set.
+ */
+status_t I3C_SlaveTransferEDMA(I3C_Type *base,
+                               i3c_slave_edma_handle_t *handle,
+                               i3c_slave_edma_transfer_t *transfer,
+                               uint32_t eventMask);
+/*!
+ * @brief Abort a slave edma non-blocking transfer in a early time
+ *
+ * @param base I3C peripheral base address
+ * @param handle pointer to i3c_slave_edma_handle_t structure
+ */
+void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle);
+
+/*!
+ * @brief Reusable routine to handle slave interrupts.
+ * @note This function does not need to be called unless you are reimplementing the
+ *  nonblocking API's interrupt handler routines to add special functionality.
+ * @param base The I3C peripheral base address.
+ * @param i3cHandle Pointer to the I3C slave DMA driver handle.
+ */
+void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle);
+/*! @} */
+
+/*! @} */
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* FSL_I3C_EDMA_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2021, 2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -17,12 +17,57 @@
 #define FSL_COMPONENT_ID "platform.drivers.inputmux"
 #endif
 
+#if defined(INPUTMUX_RSTS)
+#define INPUTMUX_RESETS_ARRAY INPUTMUX_RSTS
+#endif
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(INPUTMUX_RESETS_ARRAY)
+/*!
+ * @brief Get instance number for INPUTMUX module.
+ *
+ * @param base INPUTMUX peripheral base address
+ */
+static uint32_t INPUTMUX_GetInstance(INPUTMUX_Type *base);
+#endif
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if defined(INPUTMUX_RESETS_ARRAY)
+/*! @brief Pointers to INPUTMUX bases for each instance. */
+static INPUTMUX_Type *const s_inputmuxBases[] = INPUTMUX_BASE_PTRS;
+
+/* Reset array */
+static const reset_ip_name_t s_inputmuxResets[] = INPUTMUX_RESETS_ARRAY;
+#endif
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
+#if defined(INPUTMUX_RESETS_ARRAY)
+static uint32_t INPUTMUX_GetInstance(INPUTMUX_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_inputmuxBases); instance++)
+    {
+        if (s_inputmuxBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_inputmuxBases));
+
+    return instance;
+}
+#endif
 
 /*!
- * brief    Initialize INPUTMUX peripheral.
+ * brief	Initialize INPUTMUX peripheral.
 
  * This function enables the INPUTMUX clock.
  *
@@ -42,16 +87,26 @@ void INPUTMUX_Init(INPUTMUX_Type *base)
     CLOCK_EnableClock(kCLOCK_InputMux);
 #endif /* FSL_FEATURE_INPUTMUX_HAS_NO_INPUTMUX_CLOCK_SOURCE */
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(INPUTMUX_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_inputmuxResets[INPUTMUX_GetInstance(base)]);
+#endif
 }
 
 /*!
  * brief Attaches a signal
  *
- * This function gates the INPUTPMUX clock.
+ * This function attaches multiplexed signals from INPUTMUX to target signals.
+ * For example, to attach GPIO PORT0 Pin 5 to PINT peripheral, do the following:
+ * code
+ *      INPUTMUX_AttachSignal(INPUTMUX, 2, kINPUTMUX_GpioPort0Pin5ToPintsel);
+ * endcode
+ * In this example, INTMUX has 8 registers for PINT, PINT_SEL0~PINT_SEL7.
+ * With parameter p index specified as 2, this function configures register PINT_SEL2.
  *
  * param base Base address of the INPUTMUX peripheral.
- * param index Destination peripheral to attach the signal to.
- * param connection Selects connection.
+ * param index The serial number of destination register in the group of INPUTMUX registers with same name.
+ * param connection Applies signal from source signals collection to target signal.
  *
  * retval None.
  */
@@ -116,7 +171,7 @@ void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool e
 #endif
 
 /*!
- * brief    Deinitialize INPUTMUX peripheral.
+ * brief	Deinitialize INPUTMUX peripheral.
 
  * This function disables the INPUTMUX clock.
  *

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_inputmux.h

@@ -1,13 +1,13 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2021, 2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_INPUTMUX_H_
-#define _FSL_INPUTMUX_H_
+#ifndef FSL_INPUTMUX_H_
+#define FSL_INPUTMUX_H_
 
 #include "fsl_inputmux_connections.h"
 #include "fsl_common.h"
@@ -25,10 +25,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief Group interrupt driver version for SDK */
-#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
-/*@}*/
+#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 7))
+/*! @} */
 
 /*******************************************************************************
  * API
@@ -39,7 +39,7 @@ extern "C" {
 #endif
 
 /*!
- * @brief   Initialize INPUTMUX peripheral.
+ * @brief	Initialize INPUTMUX peripheral.
 
  * This function enables the INPUTMUX clock.
  *
@@ -52,11 +52,17 @@ void INPUTMUX_Init(INPUTMUX_Type *base);
 /*!
  * @brief Attaches a signal
  *
- * This function gates the INPUTPMUX clock.
+ * This function attaches multiplexed signals from INPUTMUX to target signals.
+ * For example, to attach GPIO PORT0 Pin 5 to PINT peripheral, do the following:
+ * @code
+ *      INPUTMUX_AttachSignal(INPUTMUX, 2, kINPUTMUX_GpioPort0Pin5ToPintsel);
+ * @endcode
+ * In this example, INTMUX has 8 registers for PINT, PINT_SEL0~PINT_SEL7.
+ * With parameter @p index specified as 2, this function configures register PINT_SEL2.
  *
  * @param base Base address of the INPUTMUX peripheral.
- * @param index Destination peripheral to attach the signal to.
- * @param connection Selects connection.
+ * @param index The serial number of destination register in the group of INPUTMUX registers with same name.
+ * @param connection Applies signal from source signals collection to target signal.
  *
  * @retval None.
  */
@@ -78,7 +84,7 @@ void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool e
 #endif
 
 /*!
- * @brief   Deinitialize INPUTMUX peripheral.
+ * @brief	Deinitialize INPUTMUX peripheral.
 
  * This function disables the INPUTMUX clock.
  *
@@ -92,6 +98,6 @@ void INPUTMUX_Deinit(INPUTMUX_Type *base);
 }
 #endif
 
-/*@}*/
+/*! @} */
 
-#endif /* _FSL_INPUTMUX_H_ */
+#endif /* FSL_INPUTMUX_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_intm.h

@@ -5,8 +5,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_INTM_H_
-#define _FSL_INTM_H_
+#ifndef FSL_INTM_H_
+#define FSL_INTM_H_
 
 #include "fsl_common.h"
 
@@ -20,10 +20,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief INTM driver version. */
 #define FSL_INTM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
-/*@}*/
+/*! @} */
 
 /*! @brief Interrupt monitors. */
 typedef enum _intm_monitor
@@ -204,4 +204,4 @@ static inline bool INTM_GetStatusFlags(INTM_Type *base, intm_monitor_t intms)
 }
 
 /*! @} */
-#endif /* _FSL_INTM_H_*/
+#endif /* FSL_INTM_H_*/

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_irtc.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2019, 2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -21,6 +21,22 @@
 #define YEAR_RANGE_START (1984U) /* Valid values for year range from -128 to 127; 2112 - 128 */
 #define YEAR_RANGE_END   (2239U) /* Valid values for year range from -128 to 127; 2112 + 127 */
 
+#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) || \
+    (defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET)
+/*! @brief Array to map IRTC instance number to base pointer. */
+static RTC_Type *const kIrtcBases[] = RTC_BASE_PTRS;
+#endif
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map IRTC instance number to clock gate enum. */
+static clock_ip_name_t const kIrtcClocks[] = RTC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET
+/*! @brief Pointers to IRTC resets for each instance. */
+static const reset_ip_name_t kIrtcResets[] = RTC_RSTS;
+#endif
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -33,6 +49,18 @@
  */
 static bool IRTC_CheckDatetimeFormat(const irtc_datetime_t *datetime);
 
+#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) || \
+    (defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET)
+/*!
+ * @brief Returns an instance number given a base address.
+ *
+ * @param base The IRTC peripheral base address.
+ * @return IRTC instance number starting from 0. If cannot the base address is
+ * not a valid address, this function returns -1.
+ */
+static int32_t IRTC_GetInstance(RTC_Type *base);
+#endif
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -70,6 +98,29 @@ static bool IRTC_CheckDatetimeFormat(const irtc_datetime_t *datetime)
     return fgRet;
 }
 
+#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) || \
+    (defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET)
+static int32_t IRTC_GetInstance(RTC_Type *base)
+{
+    int32_t instance;
+
+    for (instance = 0; instance < (int32_t)ARRAY_SIZE(kIrtcBases); ++instance)
+    {
+        if (kIrtcBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    if (instance >= (int32_t)ARRAY_SIZE(kIrtcBases))
+    {
+        instance = -1;
+    }
+
+    return instance;
+}
+#endif
+
 /*!
  * brief Ungates the IRTC clock and configures the peripheral for basic operation.
  *
@@ -90,12 +141,21 @@ status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config)
     uint16_t reg;
     status_t status = kStatus_Success;
 
+#if (!(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)) || \
+    (defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET)
+    int32_t instance = IRTC_GetInstance(base);
+    if (instance < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+#endif
+
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    CLOCK_EnableClock(kCLOCK_Rtc0);
+    CLOCK_EnableClock(kIrtcClocks[instance]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 #if defined(FSL_FEATURE_RTC_HAS_RESET) && FSL_FEATURE_RTC_HAS_RESET
-    RESET_PeripheralReset(kRTC_RST_SHIFT_RSTn);
+    RESET_ReleasePeripheralReset(kIrtcResets[instance]);
 #endif
 
     /* Unlock to allow register write operation */
@@ -123,7 +183,7 @@ status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config)
 #endif
 #if defined(FSL_FEATURE_RTC_HAS_CLOCK_SELECT) && FSL_FEATURE_RTC_HAS_CLOCK_SELECT
                (uint16_t)RTC_CTRL_CLK_SEL_MASK |
-#endif
+#endif 
 #if defined(FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE) && FSL_FEATURE_RTC_HAS_CLOCK_OUTPUT_DISABLE
                (uint16_t)RTC_CTRL_CLKO_DIS_MASK |
 #endif
@@ -149,6 +209,26 @@ status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config)
     return status;
 }
 
+/*
+ * brief Gate the IRTC clock
+ *
+ * param base IRTC peripheral base address
+ */
+status_t IRTC_Deinit(RTC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    int32_t instance = IRTC_GetInstance(base);
+    if (instance < 0)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    CLOCK_DisableClock(kIrtcClocks[instance]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+    return kStatus_Success;
+}
+
 /*!
  * brief Fill in the IRTC config struct with the default settings
  *
@@ -172,7 +252,7 @@ void IRTC_GetDefaultConfig(irtc_config_t *config)
     config->wakeupSelect = true;
 #endif
 
-#if !defined(FSL_FEATURE_RTC_HAS_NO_SAMPLING_CLOCKS) || (!FSL_FEATURE_RTC_HAS_NO_SAMPLING_CLOCKS)
+#if !defined(FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) || (!FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK)
     /* Sampling clock are not gated when in standby mode */
     config->timerStdMask = false;
 #endif
@@ -191,6 +271,7 @@ void IRTC_GetDefaultConfig(irtc_config_t *config)
 #endif
 }
 
+#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U))
 /*!
  * brief Sets the IRTC date and time according to the given time structure.
  *
@@ -239,6 +320,7 @@ status_t IRTC_SetDatetime(RTC_Type *base, const irtc_datetime_t *datetime)
 
     return status;
 }
+#endif /* FSL_FEATURE_RTC_IS_SLAVE  */
 
 /*!
  * brief Gets the IRTC time and stores it in the given time structure.
@@ -395,6 +477,7 @@ status_t IRTC_SetWriteProtection(RTC_Type *base, bool lock)
     return status;
 }
 
+#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U))
 /*!
  * brief Sets the IRTC daylight savings start and stop date and time.
  *
@@ -423,6 +506,7 @@ void IRTC_SetDaylightTime(RTC_Type *base, const irtc_daylight_time_t *datetime)
     /* Enable daylight saving time */
     base->CTRL |= RTC_CTRL_DST_EN_MASK;
 }
+#endif /* FSL_FEATURE_RTC_IS_SLAVE  */
 
 /*!
  * brief Gets the IRTC daylight savings time and stores it in the given time structure.
@@ -452,6 +536,7 @@ void IRTC_GetDaylightTime(RTC_Type *base, irtc_daylight_time_t *datetime)
     datetime->endHour   = (uint8_t)((temp & RTC_DST_HOUR_DST_END_HOUR_MASK) >> RTC_DST_HOUR_DST_END_HOUR_SHIFT);
 }
 
+#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U))
 /*!
  * brief Enables the coarse compensation and sets the value in the IRTC compensation register.
  *
@@ -497,6 +582,7 @@ void IRTC_SetFineCompensation(RTC_Type *base, uint8_t integralValue, uint8_t fra
     /* Enable fine compensation */
     base->CTRL |= (RTC_CTRL_COMP_EN_MASK | RTC_CTRL_FINEEN_MASK);
 }
+#endif /* FSL_FEATURE_RTC_IS_SLAVE  */
 
 #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE)
 
@@ -676,6 +762,8 @@ void IRTC_ConfigClockOut(RTC_Type *base, irtc_clockout_sel_t clkOut)
     ctrlVal &= (uint16_t)(~RTC_CTRL_CLKOUT_MASK);
 
     ctrlVal |= RTC_CTRL_CLKOUT((uint16_t)clkOut);
+
+#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U))
     if (clkOut == kIRTC_ClkoutCoarse1Hz)
     {
         ctrlVal |= RTC_CTRL_COMP_EN_MASK;
@@ -688,6 +776,7 @@ void IRTC_ConfigClockOut(RTC_Type *base, irtc_clockout_sel_t clkOut)
     {
         /* empty else */
     }
+#endif /* FSL_FEATURE_RTC_IS_SLAVE */
 
     base->CTRL = ctrlVal;
 }

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_irtc.h

@@ -1,12 +1,12 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2019, 2022 NXP
+ * Copyright 2016-2019, 2022-2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_IRTC_H_
-#define _FSL_IRTC_H_
+#ifndef FSL_IRTC_H_
+#define FSL_IRTC_H_
 
 #include "fsl_common.h"
 
@@ -20,9 +20,15 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
-#define FSL_IRTC_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*!< Version. */
-/*@}*/
+/*! @{ */
+#define FSL_IRTC_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
+/*! @} */
+
+#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U))
+#define IRTC_STATUS_W1C_BITS ((uint16_t)(RTC_STATUS_BUS_ERR_MASK) | (uint16_t)(RTC_STATUS_CMP_DONE_MASK))
+#else
+#define IRTC_STATUS_W1C_BITS ((uint16_t)(RTC_STATUS_BUS_ERR_MASK))
+#endif
 
 #if defined(FSL_FEATURE_RTC_HAS_CLOCK_SELECT) && FSL_FEATURE_RTC_HAS_CLOCK_SELECT
 /*! @brief IRTC clock select. */
@@ -114,9 +120,11 @@ typedef enum _irtc_status_flags
 #if !defined(FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG) || (!FSL_FEATURE_RTC_HAS_NO_RST_SRC_FLAG)
     kIRTC_ResetSrcFlag = (RTC_STATUS_RST_SRC_MASK << 16U), /*!< Reset source flag */
 #endif
+#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U))
     kIRTC_CmpIntFlag  = (RTC_STATUS_CMP_INT_MASK << 16U),  /*!< Compensation interval status flag */
-    kIRTC_BusErrFlag  = (RTC_STATUS_BUS_ERR_MASK << 16U),  /*!< Bus error flag */
     kIRTC_CmpDoneFlag = (RTC_STATUS_CMP_DONE_MASK << 16U), /*!< Compensation done flag */
+#endif
+    kIRTC_BusErrFlag  = (RTC_STATUS_BUS_ERR_MASK << 16U),  /*!< Bus error flag */
 #if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM
     kIRTC_WakeTimerFlag = (RTC_WAKE_TIMER_CTRL_WAKE_FLAG_MASK << 28U) /*!< Wake timer status flag */
 #endif
@@ -131,7 +139,7 @@ typedef enum _irtc_alarm_match
     kRTC_MatchSecMinHrDayMnthYr = 3U  /*!< Only match second, minute, hour, day, month and year */
 } irtc_alarm_match_t;
 
-#if !defined(FSL_FEATURE_RTC_HAS_NO_OSC_CAP_LOAD) || (!FSL_FEATURE_RTC_HAS_NO_OSC_CAP_LOAD)
+#if !defined(FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG) || (!FSL_FEATURE_RTC_HAS_NO_GP_DATA_REG)
 /*! @brief List of RTC Oscillator capacitor load settings */
 typedef enum _irtc_osc_cap_load
 {
@@ -205,7 +213,7 @@ typedef struct _irtc_config
     bool wakeupSelect; /*!< true: Tamper pin 0 is used to wakeup the chip;
                             false: Tamper pin 0 is used as the tamper pin */
 #endif
-#if !defined(FSL_FEATURE_RTC_HAS_NO_SAMPLING_CLOCKS) || (!FSL_FEATURE_RTC_HAS_NO_SAMPLING_CLOCKS)
+#if !defined(FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK) || (!FSL_FEATURE_RTC_HAS_NO_TIMER_STB_MASK)
     bool timerStdMask; /*!< true: Sampling clocks gated in standby mode;
                             false: Sampling clocks not gated */
 #endif
@@ -243,7 +251,9 @@ extern "C" {
  * @param base   IRTC peripheral base address
  * @param config Pointer to user's IRTC config structure.
  *
+ * @return kStatus_Success If the driver is initialized successfully.
  * @return kStatus_Fail if we cannot disable register write protection
+ * @return kStatus_InvalidArgument If the input parameters are wrong.
  */
 status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config);
 
@@ -251,13 +261,10 @@ status_t IRTC_Init(RTC_Type *base, const irtc_config_t *config);
  * @brief Gate the IRTC clock
  *
  * @param base IRTC peripheral base address
+ * @return kStatus_Success If the driver is initialized successfully.
+ * @return kStatus_InvalidArgument If the input parameters are wrong.
  */
-static inline void IRTC_Deinit(RTC_Type *base)
-{
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    CLOCK_DisableClock(kCLOCK_Rtc0);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-}
+status_t IRTC_Deinit(RTC_Type *base);
 
 /*!
  * @brief Fill in the IRTC config struct with the default settings
@@ -279,6 +286,7 @@ void IRTC_GetDefaultConfig(irtc_config_t *config);
  * @{
  */
 
+#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U))
 /*!
  * @brief Sets the IRTC date and time according to the given time structure.
  *
@@ -291,6 +299,7 @@ void IRTC_GetDefaultConfig(irtc_config_t *config);
  *         kStatus_InvalidArgument: failure. An error occurs because the datetime format is incorrect.
  */
 status_t IRTC_SetDatetime(RTC_Type *base, const irtc_datetime_t *datetime);
+#endif /* FSL_FEATURE_RTC_IS_SLAVE  */
 
 /*!
  * @brief Gets the IRTC time and stores it in the given time structure.
@@ -346,7 +355,7 @@ static inline void IRTC_EnableInterrupts(RTC_Type *base, uint32_t mask)
 #endif
 #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE)
 #if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE)
-    if (0U != (mask & kIRTC_TamperQueueFullInterruptEnable))
+    if (0U != (mask & (uint32_t)kIRTC_TamperQueueFullInterruptEnable))
     {
         base->TAMPER_QSCR |= RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK;
     }
@@ -367,14 +376,14 @@ static inline void IRTC_DisableInterrupts(RTC_Type *base, uint32_t mask)
 #if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM
     if (0U != (mask & (uint32_t)kIRTC_WakeTimerInterruptEnable))
     {
-        base->WAKE_TIMER_CTRL &= ~RTC_WAKE_TIMER_CTRL_INTR_EN_MASK;
+        base->WAKE_TIMER_CTRL &= ~(uint16_t)RTC_WAKE_TIMER_CTRL_INTR_EN_MASK;
     }
 #endif
 #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE)
 #if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE)
-    if (0U != (mask & kIRTC_TamperQueueFullInterruptEnable))
+    if (0U != (mask & (uint32_t)kIRTC_TamperQueueFullInterruptEnable))
     {
-        base->TAMPER_QSCR &= ~RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK;
+        base->TAMPER_QSCR &= ~(uint16_t)RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK;
     }
 #endif
 #endif
@@ -392,11 +401,11 @@ static inline uint32_t IRTC_GetEnabledInterrupts(RTC_Type *base)
 {
     uint32_t intsEnabled = base->IER;
 #if defined(FSL_FEATURE_RTC_HAS_SUBSYSTEM) && FSL_FEATURE_RTC_HAS_SUBSYSTEM
-    intsEnabled |= (base->WAKE_TIMER_CTRL & RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) << 16U;
+    intsEnabled |= (base->WAKE_TIMER_CTRL & (uint32_t)RTC_WAKE_TIMER_CTRL_INTR_EN_MASK) << 16U;
 #endif
 #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE)
 #if defined(FSL_FEATURE_RTC_HAS_TAMPER_QUEUE) && (FSL_FEATURE_RTC_HAS_TAMPER_QUEUE)
-    intsEnabled |= (base->TAMPER_QSCR & RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK) << 24U;
+    intsEnabled |= (base->TAMPER_QSCR & (uint32_t)RTC_TAMPER_QSCR_Q_FULL_INT_EN_MASK) << 24U;
 #endif
 #endif
 
@@ -437,7 +446,7 @@ static inline uint32_t IRTC_GetStatusFlags(RTC_Type *base)
 static inline void IRTC_ClearStatusFlags(RTC_Type *base, uint32_t mask)
 {
     base->ISR    = (uint16_t)mask;
-    base->STATUS = (base->STATUS & ~((uint16_t)RTC_STATUS_BUS_ERR_MASK | (uint16_t)RTC_STATUS_CMP_DONE_MASK)) |
+    base->STATUS = (base->STATUS & ~IRTC_STATUS_W1C_BITS) |
                    ((uint16_t)(mask >> 16U));
 #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE)
     /* TAMPER flag need clear TAMPER_SCR[TMPR_STS] filed */
@@ -541,7 +550,7 @@ static inline void IRTC_Enable32kClkDuringRegisterWrite(RTC_Type *base, bool ena
  * RTC subsystem needs RTC to output 1HZ clock for sub-second counter.
  *
  * @param base IRTC peripheral base address
- * @param cloOut select clock to use for output,
+ * @param clkOut select clock to use for output,
  */
 void IRTC_ConfigClockOut(RTC_Type *base, irtc_clockout_sel_t clkOut);
 
@@ -632,6 +641,7 @@ static inline void IRTC_SetTamperConfigurationOver(RTC_Type *base)
  * @{
  */
 
+#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U))
 /*!
  * @brief Sets the IRTC daylight savings start and stop date and time.
  *
@@ -641,6 +651,7 @@ static inline void IRTC_SetTamperConfigurationOver(RTC_Type *base)
  * @param datetime Pointer to a structure where the date and time details are stored.
  */
 void IRTC_SetDaylightTime(RTC_Type *base, const irtc_daylight_time_t *datetime);
+#endif /* FSL_FEATURE_RTC_IS_SLAVE  */
 
 /*!
  * @brief Gets the IRTC daylight savings time and stores it in the given time structure.
@@ -652,6 +663,7 @@ void IRTC_GetDaylightTime(RTC_Type *base, irtc_daylight_time_t *datetime);
 
 /*! @}*/
 
+#if !(defined(FSL_FEATURE_RTC_IS_SLAVE) && (FSL_FEATURE_RTC_IS_SLAVE != 0U))
 /*!
  * @name Time Compensation Interface
  * @{
@@ -680,6 +692,7 @@ void IRTC_SetCoarseCompensation(RTC_Type *base, uint8_t compensationValue, uint8
 void IRTC_SetFineCompensation(RTC_Type *base, uint8_t integralValue, uint8_t fractionValue, bool accumulateFractional);
 
 /*! @}*/
+#endif /* FSL_FEATURE_RTC_IS_SLAVE  */
 
 #if !defined(FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE) || (!FSL_FEATURE_RTC_HAS_NO_TAMPER_FEATURE)
 
@@ -756,6 +769,7 @@ static inline void IRTC_ClearTamperQueueFullStatus(RTC_Type *base)
  * @{
  */
 
+#if !(defined(FSL_FEATURE_RTC_HAS_SUBSECOND) && (FSL_FEATURE_RTC_HAS_SUBSECOND == 0))
 /*!
  * @brief Enable the RTC wake-up timer.
  *
@@ -799,6 +813,8 @@ static inline uint32_t IRTC_GetSubsecondCount(RTC_Type *base)
 
     return b;
 }
+#endif /* FSL_FEATURE_RTC_HAS_SUBSECOND */
+
 /*!
  * @brief Set countdown value to the RTC wake timer counter register.
  *
@@ -849,4 +865,4 @@ static inline uint32_t IRTC_GetWakeupCount(RTC_Type *base)
 
 /*! @}*/
 
-#endif /* _FSL_IRTC_H_ */
+#endif /* FSL_IRTC_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_itrc.h

@@ -4,8 +4,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_ITRC_H_
-#define _FSL_ITRC_H_
+#ifndef FSL_ITRC_H_
+#define FSL_ITRC_H_
 
 #include "fsl_common.h"
 
@@ -21,10 +21,12 @@
  *******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
-/*! @brief Defines ITRC driver version 2.2.0.
+/*! @{ */
+/*! @brief Defines ITRC driver version 2.3.0.
  *
  * Change log:
+ * - Version 2.3.0
+ *   - Update names of kITRC_SwEvent1/2 to kITRC_SwEvent0/1 to align with RM
  * - Version 2.2.0
  *   - Update driver to new version and input events
  * - Version 2.1.0
@@ -32,8 +34,8 @@
  * - Version 2.0.0
  *   - initial version
  */
-#define FSL_ITRC_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
-/*@}*/
+#define FSL_ITRC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
+/*! @} */
 
 typedef enum _itrc_input_signals
 {
@@ -59,8 +61,8 @@ typedef enum _itrc_input_signals
 #if defined(ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK)
     kITRC_Freqme = 13u,
 #endif /* ITRC_OUTX_SEL_OUTX_SELY_OUT_SEL_IN13_SELn_MASK */
-    kITRC_SwEvent1 = 14u,
-    kITRC_SwEvent2 = 15u,
+    kITRC_SwEvent0 = 14u,
+    kITRC_SwEvent1 = 15u,
 #if defined(ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK)
     kITRC_VddSysLow = 16u,
 #endif /* ITRC_OUTX_SEL_1_OUTX_SELY_OUT_SEL_1_IN16_SELn_MASK */
@@ -317,4 +319,4 @@ void ITRC_Deinit(ITRC_Type *base);
 
 /*! @}*/ /* end of group itrc */
 
-#endif /* _FSL_ITRC_H_ */
+#endif /* FSL_ITRC_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpadc.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2022 NXP
+ * Copyright 2016-2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -8,11 +8,47 @@
 
 #include "fsl_lpadc.h"
 
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
 /* Component ID definition, used by tools. */
 #ifndef FSL_COMPONENT_ID
 #define FSL_COMPONENT_ID "platform.drivers.lpadc"
 #endif
 
+#ifndef ADC_VERID_DIFFEN_MASK
+#define ADC_VERID_DIFFEN_MASK (0x2U)
+#endif /* ADC_VERID_DIFFEN_MASK */
+
+#ifndef ADC_VERID_NUM_SEC_MASK
+#define ADC_VERID_NUM_SEC_MASK (0x800U)
+#endif /* ADC_VERID_NUM_SEC_MASK */
+
+#define ADC_CMDL_CHANNEL_MODE_MASK  (0x60U)
+#define ADC_CMDL_CHANNEL_MODE_SHIFT (5U)
+#define ADC_CMDL_CHANNEL_MODE(x) \
+    (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CHANNEL_MODE_SHIFT)) & ADC_CMDL_CHANNEL_MODE_MASK)
+
+#define GET_ADC_CFG_TPRICTRL_VALUE(val) (((uint32_t)val) & 0x3U)
+
+#if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES
+#define GET_ADC_CFG_TRES_VALUE(val) ((((uint32_t)val) & 0x4U) >> 2U)
+#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */
+
+#if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES
+#define GET_ADC_CFG_TCMDRES_VALUE(val) ((((uint32_t)val) & 0x8U) >> 3U)
+#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */
+
+#if defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI
+#define GET_ADC_CFG_HPT_EXDI_VALUE(val) ((((uint32_t)val) & 0x10U) >> 4U)
+#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */
+
+#if defined(LPADC_RSTS)
+#define LPADC_RESETS_ARRAY LPADC_RSTS
+#elif defined(ADC_RSTS)
+#define LPADC_RESETS_ARRAY ADC_RSTS
+#endif
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -23,14 +59,14 @@
  */
 static uint32_t LPADC_GetInstance(ADC_Type *base);
 
-#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE
+#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ
 /*!
  * @brief Get gain conversion result .
  *
  * @param gainAdjustment gain adjustment value.
  */
 static uint32_t LPADC_GetGainConvResult(float gainAdjustment);
-#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */
+#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */
 
 /*******************************************************************************
  * Variables
@@ -41,6 +77,10 @@ static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS;
 /*! @brief Pointers to LPADC clocks for each instance. */
 static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#if defined(LPADC_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_lpadcResets[] = LPADC_RESETS_ARRAY;
+#endif
 
 /*******************************************************************************
  * Code
@@ -50,8 +90,18 @@ static uint32_t LPADC_GetInstance(ADC_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
+    /*
+     * $Branch Coverage Justification$
+     * (instance >= ARRAY_SIZE(s_lpadcBases)) not covered. The peripheral base
+     * address is always valid and checked by assert.
+     */
     for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++)
     {
+        /*
+         * $Branch Coverage Justification$
+         * (s_lpadcBases[instance] != base) not covered. The peripheral base
+         * address is always valid and checked by assert.
+         */
         if (s_lpadcBases[instance] == base)
         {
             break;
@@ -63,7 +113,7 @@ static uint32_t LPADC_GetInstance(ADC_Type *base)
     return instance;
 }
 
-#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE
+#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ)
 /*!
  * brief  Get gain conversion Result .
  *
@@ -71,27 +121,27 @@ static uint32_t LPADC_GetInstance(ADC_Type *base)
  */
 static uint32_t LPADC_GetGainConvResult(float gainAdjustment)
 {
-    int8_t i          = 0;
+    uint16_t i        = 0U;
     uint32_t tmp32    = 0U;
     uint32_t GCRa[17] = {0};
     uint32_t GCALR    = 0U;
 
-    for (i = 0x10; i >= 0; i--)
+    for (i = 0x11U; i > 0U; i--)
     {
-        tmp32          = (uint32_t)((gainAdjustment) / ((float)(1.0 / (0x01 << (0x10 - i)))));
-        GCRa[i]        = tmp32;
-        gainAdjustment = gainAdjustment - ((float)tmp32) * ((float)(1.0 / (0x01 << (0x10 - i))));
+        tmp32          = (uint32_t)((gainAdjustment) / ((float)(1.0 / (double)(1U << (0x10U - (i - 1U))))));
+        GCRa[i - 1U]   = tmp32;
+        gainAdjustment = gainAdjustment - ((float)tmp32) * ((float)(1.0 / (double)(1U << (0x10U - (i - 1U)))));
     }
     /* Get GCALR value calculated */
-    for (i = 0x10; i >= 0; i--)
+    for (i = 0x11U; i > 0U; i--)
     {
-        GCALR += GCRa[i] * (0x01 << i);
+        GCALR += GCRa[i - 1U] * ((uint32_t)(1UL << (uint32_t)(i - 1UL)));
     }
 
     /* to return GCALR value calculated */
     return GCALR;
 }
-#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */
+#endif /* defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */
 
 /*!
  * brief Initializes the LPADC module.
@@ -111,6 +161,10 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
     (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
+#if defined(LPADC_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_lpadcResets[LPADC_GetInstance(base)]);
+#endif
+
     /* Reset the module. */
     LPADC_DoResetConfig(base);
 #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
@@ -155,13 +209,27 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
     {
         tmp32 |= ADC_CFG_PWREN_MASK;
     }
-    tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay)              /* Power up delay. */
-             | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */
+    tmp32 |= (ADC_CFG_PUDLY(config->powerUpDelay)              /* Power up delay. */
+              | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */
+#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U)
+              | ADC_CFG_PWRSEL(config->powerLevelMode)         /* Power configuration. */
+#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */
+    );
+
+    tmp32 |= ADC_CFG_TPRICTRL(GET_ADC_CFG_TPRICTRL_VALUE(config->triggerPriorityPolicy));
+
+#if (defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES)
+    tmp32 |= ADC_CFG_TRES(GET_ADC_CFG_TRES_VALUE(config->triggerPriorityPolicy));
+#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */
+
+#if (defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES)
+    tmp32 |= ADC_CFG_TCMDRES(GET_ADC_CFG_TCMDRES_VALUE(config->triggerPriorityPolicy));
+#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */
+
+#if (defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI)
+    tmp32 |= ADC_CFG_HPT_EXDI(GET_ADC_CFG_HPT_EXDI_VALUE(config->triggerPriorityPolicy));
+#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */
 
-#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL)
-             | ADC_CFG_PWRSEL(config->powerLevelMode)           /* Power configuration. */
-#endif                                                          /* FSL_FEATURE_LPADC_HAS_CFG_PWRSEL */
-             | ADC_CFG_TPRICTRL(config->triggerPriorityPolicy); /* Trigger priority policy. */
     base->CFG = tmp32;
 
     /* ADCx_PAUSE. */
@@ -227,9 +295,9 @@ void LPADC_GetDefaultConfig(lpadc_config_t *config)
     config->enableAnalogPreliminary = false;
     config->powerUpDelay            = 0x80;
     config->referenceVoltageSource  = kLPADC_ReferenceVoltageAlt1;
-#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && FSL_FEATURE_LPADC_HAS_CFG_PWRSEL
+#if defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U)
     config->powerLevelMode = kLPADC_PowerLevelAlt1;
-#endif /* FSL_FEATURE_LPADC_HAS_CFG_PWRSEL */
+#endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_PWRSEL) && (FSL_FEATURE_LPADC_HAS_CFG_PWRSEL == 1U) */
     config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately;
     config->enableConvPause       = false;
     config->convPauseDelay        = 0U;
@@ -271,11 +339,11 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t in
 {
     assert(result != NULL); /* Check if the input pointer is available. */
 
-    uint32_t tmp32;
+    uint32_t tmp32 = 0U;
 
     tmp32 = base->RESFIFO[index];
 
-    if (0U == (ADC_RESFIFO_VALID_MASK & tmp32))
+    if (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK))
     {
         return false; /* FIFO is empty. Discard any read from RESFIFO. */
     }
@@ -287,6 +355,31 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t in
 
     return true;
 }
+/*!
+ * brief Get the result in conversion FIFOn using blocking method.
+ *
+ * param base LPADC peripheral base address.
+ * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
+ * param index Result FIFO index.
+ */
+void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index)
+{
+    assert(result != NULL); /* Check if the input pointer is available. */
+
+    uint32_t tmp32 = 0U;
+
+    tmp32 = base->RESFIFO[index];
+
+    while (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK))
+    {
+        tmp32 = base->RESFIFO[index];
+    }
+
+    result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
+    result->loopCountIndex  = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT;
+    result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT;
+    result->convValue       = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK);
+}
 #else
 /*!
  * brief Get the result in conversion FIFO.
@@ -300,22 +393,46 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result)
 {
     assert(result != NULL); /* Check if the input pointer is available. */
 
-    uint32_t tmp32;
+    uint32_t tmp32 = 0U;
 
     tmp32 = base->RESFIFO;
 
-    if (0U == (ADC_RESFIFO_VALID_MASK & tmp32))
+    if (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK))
     {
         return false; /* FIFO is empty. Discard any read from RESFIFO. */
     }
 
     result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
-    result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT;
+    result->loopCountIndex  = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT;
     result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT;
-    result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK);
+    result->convValue       = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK);
 
     return true;
 }
+/*!
+ * @brief Get the result in conversion FIFO using blocking method.
+ *
+ * @param base LPADC peripheral base address.
+ * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO.
+ */
+void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result)
+{
+    assert(result != NULL); /* Check if the input pointer is available. */
+
+    uint32_t tmp32 = 0U;
+
+    tmp32 = base->RESFIFO;
+
+    while (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK))
+    {
+        tmp32 = base->RESFIFO;
+    }
+
+    result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
+    result->loopCountIndex  = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT;
+    result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT;
+    result->convValue       = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK);
+}
 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
 
 /*!
@@ -324,7 +441,7 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result)
  * Each programmable trigger can launch the conversion command in command buffer.
  *
  * param base LPADC peripheral base address.
- * param triggerId ID for each trigger. Typically, the available value range is from 0.
+ * param triggerId ID for each trigger. Typically, the available value range is from 0 to 3.
  * param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t.
  */
 void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config)
@@ -357,12 +474,12 @@ void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_
  *
  * This function initializes the trigger's configuration structure with an available settings. The default values are:
  * code
- *   config->commandIdSource       = 0U;
- *   config->loopCountIndex        = 0U;
- *   config->triggerIdSource       = 0U;
- *   config->enableHardwareTrigger = false;
- *   config->channelAFIFOSelect    = 0U;
- *   config->channelBFIFOSelect    = 0U;
+ *   config->targetCommandId        = 0U;
+ *   config->delayPower             = 0U;
+ *   config->priority               = 0U;
+ *   config->channelAFIFOSelect     = 0U;
+ *   config->channelBFIFOSelect     = 0U;
+ *   config->enableHardwareTrigger  = false;
  * endcode
  * param config Pointer to configuration structure.
  */
@@ -386,6 +503,9 @@ void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config)
 /*!
  * brief Configure conversion command.
  *
+ * note The number of compare value register on different chips is different, that is mean in some chips, some
+ * command buffers do not have the compare functionality.
+ *
  * param base LPADC peripheral base address.
  * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15.
  * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t.
@@ -400,36 +520,35 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_
     commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */
 
     /* ADCx_CMDL. */
-    tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */
+    tmp32 = ADC_CMDL_ADCH(config->channelNumber);        /* Channel number. */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH
     tmp32 |= ADC_CMDL_ALTB_ADCH(config->channelBNumber); /* Alternate channel B number. */
 #endif
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE
-    tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */
-#endif                                                 /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */
+    tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode);        /* Full/Part scale input voltage. */
+#endif                                                        /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE
     tmp32 |= ADC_CMDL_ALTB_CSCALE(config->channelBScaleMode); /* Alternate channel B full/Part scale input voltage. */
 #endif                                                        /* FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE */
-#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE
-    tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode);
-#else
-    switch (config->sampleChannelMode) /* Sample input. */
-    {
-        case kLPADC_SampleChannelSingleEndSideB:
-            tmp32 |= ADC_CMDL_ABSEL_MASK;
-            break;
+
+#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U))
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF
-        case kLPADC_SampleChannelDiffBothSideAB:
-            tmp32 |= ADC_CMDL_DIFF_MASK;
-            break;
-        case kLPADC_SampleChannelDiffBothSideBA:
-            tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK;
-            break;
-#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */
-        default: /* kLPADC_SampleChannelSingleEndSideA. */
-            break;
-    }
-#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */
+    assert(((config->sampleChannelMode >= kLPADC_SampleChannelDiffBothSideAB) &&
+            (((base->VERID) & ADC_VERID_DIFFEN_MASK) != 0U)) ||
+           (config->sampleChannelMode < kLPADC_SampleChannelDiffBothSideAB));
+#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF */
+
+#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE
+    assert(((config->sampleChannelMode == kLPADC_SampleChannelDiffBothSide) &&
+            (((base->VERID) & ADC_VERID_DIFFEN_MASK) != 0U)) ||
+           ((config->sampleChannelMode == kLPADC_SampleChannelDualSingleEndBothSide) &&
+            (((base->VERID) & ADC_VERID_NUM_SEC_MASK) != 0U)) ||
+           (config->sampleChannelMode < kLPADC_SampleChannelDualSingleEndBothSide));
+#endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */
+#endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */
+
+    tmp32 |= ADC_CMDL_CHANNEL_MODE(config->sampleChannelMode);
+
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
     tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode);
 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
@@ -455,7 +574,7 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_
     {
         tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */
     }
-#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */
+#endif                                    /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */
 
     if (config->enableAutoChannelIncrement)
     {
@@ -465,16 +584,15 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_
 
     /* Hardware compare settings.
      * Not all Command Buffers have an associated Compare Value register. The compare function is only available on
-     * Command Buffers that have a corresponding Compare Value register.
+     * Command Buffers that have a corresponding Compare Value register. Therefore, assertion judgment needs to be
+     * made before setting the CV register.
      */
-    if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode)
-    {
-        /* Check if the hardware compare feature is available for indicated command buffer. */
-        assert(commandId < ADC_CV_COUNT);
 
+    if ((kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) && (commandId < ADC_CV_COUNT))
+    {
         /* Set CV register. */
-        base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh)   /* Compare value high. */
-                              | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */
+        base->CV[commandId] = (ADC_CV_CVH(config->hardwareCompareValueHigh)    /* Compare value high. */
+                               | ADC_CV_CVL(config->hardwareCompareValueLow)); /* Compare value low. */
     }
 }
 
@@ -486,10 +604,10 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_
  * code
  *   config->sampleScaleMode            = kLPADC_SampleFullScale;
  *   config->channelBScaleMode          = kLPADC_SampleFullScale;
- *   config->channelSampleMode          = kLPADC_SampleChannelSingleEndSideA;
+ *   config->sampleChannelMode          = kLPADC_SampleChannelSingleEndSideA;
  *   config->channelNumber              = 0U;
- *   config ->alternateChannelNumber    = 0U;
- *   config->chainedNextCmdNumber       = 0U;
+ *   config->channelBNumber             = 0U;
+ *   config->chainedNextCommandNumber   = 0U;
  *   config->enableAutoChannelIncrement = false;
  *   config->loopCount                  = 0U;
  *   config->hardwareAverageMode        = kLPADC_HardwareAverageCount1;
@@ -534,7 +652,7 @@ void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config)
 #endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG
     config->enableWaitTrigger = false;
-#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */
+#endif                              /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN) && FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN
     config->enableChannelB = false; /* Enable alternate channel B.*/
 #endif                              /* FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN */
@@ -622,8 +740,8 @@ void LPADC_DoAutoCalibration(ADC_Type *base)
     base->CMD[0].CMDH = mLpadcCMDH;    /* CMD1H. */
     base->TCTRL[0]    = mLpadcTrigger; /* Trigger0. */
 }
-#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
-#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
+#endif                                 /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
+#endif                                 /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
 
 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS
 /*!
@@ -647,8 +765,35 @@ void LPADC_DoOffsetCalibration(ADC_Type *base)
  */
 void LPADC_DoAutoCalibration(ADC_Type *base)
 {
-    assert((0u == LPADC_GetConvResultCount(base, 0)) && (0u == LPADC_GetConvResultCount(base, 1)));
+    LPADC_PrepareAutoCalibration(base);
+    LPADC_FinishAutoCalibration(base);
+}
+
+/*!
+ * brief Prepare auto calibration, LPADC_FinishAutoCalibration has to be called before using the LPADC.
+ * LPADC_DoAutoCalibration has been split in two API to avoid to be stuck too long in the function.
+ *
+ * param base  LPADC peripheral base address.
+ */
+void LPADC_PrepareAutoCalibration(ADC_Type *base)
+{
+#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
+    assert((0U == LPADC_GetConvResultCount(base, 0)) && (0U == LPADC_GetConvResultCount(base, 1)));
+#else  /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 1)) */
+    assert(LPADC_GetConvResultCount(base) == 0U);
+#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */
 
+    /* Request gain calibration. */
+    base->CTRL |= ADC_CTRL_CAL_REQ_MASK;
+}
+
+/*!
+ * brief Finish auto calibration start with LPADC_PrepareAutoCalibration.
+ *
+ * param base  LPADC peripheral base address.
+ */
+void LPADC_FinishAutoCalibration(ADC_Type *base)
+{
 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE
     int32_t GCCa;
     int32_t GCCb;
@@ -656,53 +801,177 @@ void LPADC_DoAutoCalibration(ADC_Type *base)
     float GCRb;
 #else
     uint32_t GCCa;
+    float GCRa;
+#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
     uint32_t GCCb;
-    uint32_t GCRa;
-    uint32_t GCRb;
+    float GCRb;
+#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */
 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */
 
-    /* Request gain calibration. */
-    base->CTRL |= ADC_CTRL_CAL_REQ_MASK;
-    while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) ||
-           (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK)))
+    while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK))
+#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
+           || (ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK))
+#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */
+    )
     {
     }
 
-    /* Calculate gain offset. */
-    GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK);
-    GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK);
-
 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE
-    if (((base->GCC[0]) & 0x8000U))
+    GCCa = (int32_t)(base->GCC[0] & ADC_GCC_GAIN_CAL_MASK);
+    GCCb = (int32_t)(base->GCC[1] & ADC_GCC_GAIN_CAL_MASK);
+    if (0U != ((base->GCC[0]) & 0x8000U))
     {
-        GCCa = GCCa - 0x10000;
-        GCRa =
-            (float)((131072.0) / (0x20000 - GCCa)); /* Gain_CalA = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[0]))*/
+        GCCa         = GCCa - 0x10000;
+        GCRa         = (float)((131072.0) /
+                       (131072.0 - (double)GCCa)); /* Gain_CalA = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[0]))*/
         base->GCR[0] = LPADC_GetGainConvResult(GCRa); /* write A side GCALR. */
     }
 
-    if (((base->GCC[1]) & 0x8000U))
+    if (0U != ((base->GCC[1]) & 0x8000U))
     {
-        GCCb = GCCb - 0x10000;
-        GCRb =
-            (float)((131072.0) / (0x20000 - GCCb)); /* Gain_CalB = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[1]))*/
+        GCCb         = GCCb - 0x10000;
+        GCRb         = (float)((131072.0) /
+                       (131072.0 - (double)GCCb)); /* Gain_CalB = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[1]))*/
         base->GCR[1] = LPADC_GetGainConvResult(GCRb); /* write B side GCALR. */
     }
 #else
-    GCRa         = (uint16_t)((GCCa << 16U) /
-                      (0x1FFFFU - GCCa)); /* Gain_CalA = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[0])) - 1. */
-    GCRb         = (uint16_t)((GCCb << 16U) /
-                      (0x1FFFFU - GCCb)); /* Gain_CalB = (131072 / (131072-(ADC_GCC_GAIN_CAL(ADC0->GCC[1])) - 1. */
-    base->GCR[0] = ADC_GCR_GCALR(GCRa);
-    base->GCR[1] = ADC_GCR_GCALR(GCRb);
+    /* Calculate gain offset. */
+    GCCa         = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK);
+    GCRa         = (float)((131072.0) /
+                   (131072.0 - (double)GCCa)); /* Gain_CalA = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[0]))*/
+    base->GCR[0] = LPADC_GetGainConvResult(GCRa);      /* write A side GCALR. */
+
+#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
+    GCCb         = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK);
+    GCRb         = (float)((131072.0) /
+                   (131072.0 - (double)GCCb)); /* Gain_CalB = (131072.0 / (131072-(ADC_GCC_GAIN_CAL(ADC->GCC[1]))*/
+    base->GCR[1] = LPADC_GetGainConvResult(GCRb);      /* write B side GCALR. */
+#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */
 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE */
     /* Indicate the values are valid. */
     base->GCR[0] |= ADC_GCR_RDY_MASK;
+#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
     base->GCR[1] |= ADC_GCR_RDY_MASK;
+#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */
 
     while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK))
     {
     }
 }
 #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */
-#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
+
+/*!
+ * brief Get calibration value into the memory which is defined by invoker.
+ *
+ * note Please note the ADC will be disabled temporary.
+ * note This function should be used after finish calibration.
+ *
+ * param base LPADC peripheral base address.
+ * param ptrCalibrationValue Pointer to lpadc_calibration_value_t structure, this memory block should be always powered
+ * on even in low power modes.
+ */
+void LPADC_GetCalibrationValue(ADC_Type *base, lpadc_calibration_value_t *ptrCalibrationValue)
+{
+    assert(ptrCalibrationValue != NULL);
+
+    bool adcEnabled = false;
+
+    /* Check if ADC is enabled. */
+    if ((base->CTRL & ADC_CTRL_ADCEN_MASK) != 0UL)
+    {
+        LPADC_Enable(base, false);
+        adcEnabled = true;
+    }
+
+#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ)
+    uint32_t i;
+    for (i = 0UL; i < 33UL; i++)
+    {
+#if defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK)
+        ptrCalibrationValue->generalCalibrationValueA[i] =
+            (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GAR0))) + i)) & 0xFFFFU);
+#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U))
+        ptrCalibrationValue->generalCalibrationValueB[i] =
+            (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GBR0))) + i)) & 0xFFFFU);
+#endif /* (defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */
+#else
+        ptrCalibrationValue->generalCalibrationValueA[i] =
+            (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GAR[0]))) + i)) & 0xFFFFU);
+#if !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U))
+        ptrCalibrationValue->generalCalibrationValueB[i] =
+            (uint16_t)((*(((volatile uint32_t *)(&(base->CAL_GBR[0]))) + i)) & 0xFFFFU);
+#endif /* (defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */
+
+#endif /* defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) */
+    }
+#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */
+
+    ptrCalibrationValue->gainCalibrationResultA = (uint16_t)(base->GCR[0] & ADC_GCR_GCALR_MASK);
+#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
+    ptrCalibrationValue->gainCalibrationResultB = (uint16_t)(base->GCR[1] & ADC_GCR_GCALR_MASK);
+#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */
+
+    if (adcEnabled)
+    {
+        LPADC_Enable(base, true);
+    }
+}
+
+/*!
+ * brief Set calibration value into ADC calibration registers.
+ *
+ * note Please note the ADC will be disabled temporary.
+ *
+ * param base LPADC peripheral base address.
+ * param ptrCalibrationValue Pointer to lpadc_calibration_value_t structure which contains ADC's calibration value.
+ */
+void LPADC_SetCalibrationValue(ADC_Type *base, const lpadc_calibration_value_t *ptrCalibrationValue)
+{
+    assert(ptrCalibrationValue != NULL);
+
+    bool adcEnabled = false;
+
+    /* Check if ADC is enabled. */
+    if ((base->CTRL & ADC_CTRL_ADCEN_MASK) != 0UL)
+    {
+        LPADC_Enable(base, false);
+        adcEnabled = true;
+    }
+
+#if (defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ)
+    for (uint32_t i = 0UL; i < 33UL; i++)
+    {
+#if defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK)
+        *(((volatile uint32_t *)(&(base->CAL_GAR0))) + i) = ptrCalibrationValue->generalCalibrationValueA[i];
+#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
+        *(((volatile uint32_t *)(&(base->CAL_GBR0))) + i) = ptrCalibrationValue->generalCalibrationValueB[i];
+#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */
+#else
+        *(((volatile uint32_t *)(&(base->CAL_GAR[0]))) + i) = ptrCalibrationValue->generalCalibrationValueA[i];
+#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
+        *(((volatile uint32_t *)(&(base->CAL_GBR[0]))) + i) = ptrCalibrationValue->generalCalibrationValueB[i];
+#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */
+#endif /* defined(ADC_CAL_GAR0_CAL_GAR_VAL_MASK) */
+    }
+#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */
+
+    base->GCR[0] = ADC_GCR_GCALR(ptrCalibrationValue->gainCalibrationResultA) | ADC_GCR_RDY_MASK;
+#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U))
+    base->GCR[1] = ADC_GCR_GCALR(ptrCalibrationValue->gainCalibrationResultB) | ADC_GCR_RDY_MASK;
+#endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2U)) */
+    /*
+     * $Branch Coverage Justification$
+     * while ((base->STAT & ADC_STAT_CAL_RDY_MASK) == ADC_STAT_CAL_RDY_MASK) not covered. Test unfeasible,
+     * the calibration ready state is too short not to catch.
+     */
+    while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK))
+    {
+    }
+
+    if (adcEnabled)
+    {
+        LPADC_Enable(base, true);
+    }
+}
+
+#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpcmp.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2019 NXP
+ * Copyright 2016-2019, 2023 NXP
  * All rights reserved.
  *
  *
@@ -9,11 +9,18 @@
 
 #include "fsl_lpcmp.h"
 
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
 /* Component ID definition, used by tools. */
 #ifndef FSL_COMPONENT_ID
 #define FSL_COMPONENT_ID "platform.drivers.lpcmp"
 #endif
 
+#if defined(LPCMP_RSTS)
+#define LPCMP_RESETS_ARRAY LPCMP_RSTS
+#endif
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -39,6 +46,11 @@ static const clock_ip_name_t s_lpcmpClocks[] = LPCMP_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 #endif /* LPCMP_CLOCKS */
 
+#if defined(LPCMP_RESETS_ARRAY)
+/* Reset array */
+static const reset_ip_name_t s_lpcmpResets[] = LPCMP_RESETS_ARRAY;
+#endif
+
 /*******************************************************************************
  * Codes
  ******************************************************************************/
@@ -48,8 +60,18 @@ static uint32_t LPCMP_GetInstance(LPCMP_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
+    /*
+     * $Branch Coverage Justification$
+     * (instance >= ARRAY_SIZE(s_lpcmpBases)) not covered. The peripheral base
+     * address is always valid and checked by assert.
+     */
     for (instance = 0; instance < ARRAY_SIZE(s_lpcmpBases); instance++)
     {
+        /*
+         * $Branch Coverage Justification$
+         * (s_lpcmpBases[instance] != base) not covered. The peripheral base
+         * address is always valid and checked by assert.
+         */
         if (s_lpcmpBases[instance] == base)
         {
             break;
@@ -88,19 +110,37 @@ void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config)
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 #endif /* LPCMP_CLOCKS */
 
+#if defined(LPCMP_RESETS_ARRAY)
+    RESET_ReleasePeripheralReset(s_lpcmpResets[LPCMP_GetInstance(base)]);
+#endif
+
     /* Configure. */
     LPCMP_Enable(base, false);
+
+#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN)
     /* CCR0 register. */
-    if (config->enableStopMode)
-    {
-        base->CCR0 |= LPCMP_CCR0_CMP_STOP_EN_MASK;
-    }
-    else
+#if defined(FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn)
+    if (1U == FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(base))
+#endif /* FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn */
     {
-        base->CCR0 &= ~LPCMP_CCR0_CMP_STOP_EN_MASK;
+        if (config->enableStopMode)
+        {
+            base->CCR0 |= LPCMP_CCR0_CMP_STOP_EN_MASK;
+        }
+        else
+        {
+            base->CCR0 &= ~LPCMP_CCR0_CMP_STOP_EN_MASK;
+        }
     }
+#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */
+
     /* CCR1 register. */
-    tmp32 = base->CCR1 & ~(LPCMP_CCR1_COUT_PEN_MASK | LPCMP_CCR1_COUT_SEL_MASK | LPCMP_CCR1_COUT_INV_MASK);
+    tmp32 = (base->CCR1 & (~(LPCMP_CCR1_COUT_PEN_MASK | LPCMP_CCR1_COUT_SEL_MASK | LPCMP_CCR1_COUT_INV_MASK
+#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL
+                             | LPCMP_CCR1_FUNC_CLK_SEL_MASK
+#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */
+                             )));
+
     if (config->enableOutputPin)
     {
         tmp32 |= LPCMP_CCR1_COUT_PEN_MASK;
@@ -113,6 +153,9 @@ void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config)
     {
         tmp32 |= LPCMP_CCR1_COUT_INV_MASK;
     }
+#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL
+    tmp32 |= LPCMP_CCR1_FUNC_CLK_SEL(config->functionalSourceClock);
+#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */
     base->CCR1 = tmp32;
     /* CCR2 register. */
     tmp32 = base->CCR2 & ~(LPCMP_CCR2_HYSTCTR_MASK | LPCMP_CCR2_CMP_NPMD_MASK | LPCMP_CCR2_CMP_HPMD_MASK);
@@ -159,6 +202,7 @@ void LPCMP_Deinit(LPCMP_Type *base)
  *   config->enableInvertOutput  = false;
  *   config->hysteresisMode      = kLPCMP_HysteresisLevel0;
  *   config->powerMode           = kLPCMP_LowSpeedPowerMode;
+ *   config->functionalSourceClock = kLPCMP_FunctionalClockSource0;
  * endcode
  * param config Pointer to "lpcmp_config_t" structure.
  */
@@ -166,13 +210,17 @@ void LPCMP_GetDefaultConfig(lpcmp_config_t *config)
 {
     /* Initializes the configure structure to zero. */
     (void)memset(config, 0, sizeof(*config));
-
-    config->enableStopMode      = false;
+#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN)
+    config->enableStopMode = false;
+#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */
     config->enableOutputPin     = false;
     config->useUnfilteredOutput = false;
     config->enableInvertOutput  = false;
     config->hysteresisMode      = kLPCMP_HysteresisLevel0;
     config->powerMode           = kLPCMP_LowSpeedPowerMode;
+#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL
+    config->functionalSourceClock = kLPCMP_FunctionalClockSource0;
+#endif /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */
 }
 
 /*!
@@ -180,8 +228,8 @@ void LPCMP_GetDefaultConfig(lpcmp_config_t *config)
  *        is selected for the negative and positive mux.
  *
  * param base LPCMP peripheral base address.
- * param positiveChannel Positive side input channel number. Available range is 0-7.
- * param negativeChannel Negative side input channel number. Available range is 0-7.
+ * param positiveChannel Positive side input channel number.
+ * param negativeChannel Negative side input channel number.
  */
 void LPCMP_SetInputChannels(LPCMP_Type *base, uint32_t positiveChannel, uint32_t negativeChannel)
 {
@@ -237,3 +285,88 @@ void LPCMP_SetDACConfig(LPCMP_Type *base, const lpcmp_dac_config_t *config)
     }
     base->DCR = tmp32;
 }
+
+#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL
+/*!
+ * @brief Configure the window control, users can use this API to implement operations on the window,
+ * such as inverting the window signal, setting the window closing event(only valid in windowing mode),
+ * and setting the COUTA signal after the window is closed(only valid in windowing mode).
+ *
+ * @param base LPCMP peripheral base address.
+ * @param config Pointer "lpcmp_window_control_config_t" structure.
+ */
+void LPCMP_SetWindowControl(LPCMP_Type *base, const lpcmp_window_control_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t tmp32 = 0UL;
+
+    tmp32 = (base->CCR1 & (~(LPCMP_CCR1_COUTA_CFG_MASK | LPCMP_CCR1_EVT_SEL_CFG_MASK | LPCMP_CCR1_WINDOW_INV_MASK)));
+
+    if (config->enableInvertWindowSignal)
+    {
+        tmp32 |= LPCMP_CCR1_WINDOW_INV_MASK;
+    }
+
+    /* Set COUT event, which can close the active window in window mode. */
+    tmp32 |= LPCMP_CCR1_EVT_SEL_CFG(config->closeWindowEvent);
+
+    /* Set the COUTA signal value when the window is closed. */
+    tmp32 |= LPCMP_CCR1_COUTA_CFG(config->COUTASignal);
+
+    base->CCR1 = tmp32;
+}
+#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */
+
+#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE
+/*!
+ * @brief Configure the roundrobin mode.
+ *
+ * @param base LPCMP peripheral base address.
+ * @param config Pointer "lpcmp_roundrobin_config_t" structure.
+ */
+void LPCMP_SetRoundRobinConfig(LPCMP_Type *base, const lpcmp_roundrobin_config_t *config)
+{
+    assert(config != NULL);
+
+    uint32_t tmp32 = 0UL;
+
+    /* LPCMPx_RRCR0 register, Configuration options for the round-robin operation. */
+    tmp32 = (base->RRCR0 &
+             (~(LPCMP_RRCR0_RR_TRG_SEL_MASK | LPCMP_RRCR0_RR_NSAM_MASK | LPCMP_RRCR0_RR_CLK_SEL_MASK |
+                LPCMP_RRCR0_RR_INITMOD_MASK | LPCMP_RRCR0_RR_SAMPLE_CNT_MASK | LPCMP_RRCR0_RR_SAMPLE_THRESHOLD_MASK)));
+
+    tmp32 |=
+        (LPCMP_RRCR0_RR_TRG_SEL(config->roundrobinTriggerSource) | LPCMP_RRCR0_RR_NSAM(config->sampleClockNumbers) |
+         LPCMP_RRCR0_RR_CLK_SEL(config->roundrobinClockSource) | LPCMP_RRCR0_RR_INITMOD(config->initDelayModules) |
+         LPCMP_RRCR0_RR_SAMPLE_CNT(config->channelSampleNumbers) |
+         LPCMP_RRCR0_RR_SAMPLE_THRESHOLD(config->sampleTimeThreshhold));
+
+    base->RRCR0 = tmp32;
+
+    /* LPCMPx_RRCR1 register, Configure the fix port, fix channel and checker channel. */
+    tmp32 =
+        (base->RRCR1 & (~(LPCMP_RRCR1_FIXP_MASK | LPCMP_RRCR1_FIXCH_MASK | (0xFFUL << LPCMP_RRCR1_RR_CH0EN_SHIFT))));
+    tmp32 |= (LPCMP_RRCR1_FIXP(config->fixedMuxPort) | LPCMP_RRCR1_FIXCH(config->fixedChannel) |
+              ((uint32_t)(config->checkerChannelMask) << LPCMP_RRCR1_RR_CH0EN_SHIFT));
+
+    base->RRCR1 = tmp32;
+}
+
+/*!
+ * brief Configure the roundrobin internal timer reload value.
+ *
+ * param base LPCMP peripheral base address.
+ * param value RoundRobin internal timer reload value, allowed range:0x0UL-0xFFFFFFFUL.
+ */
+void LPCMP_SetRoundRobinInternalTimer(LPCMP_Type *base, uint32_t value)
+{
+    uint32_t tmp32 = 0UL;
+
+    tmp32 = (base->RRCR2 & (~LPCMP_RRCR2_RR_TIMER_RELOAD_MASK));
+    tmp32 |= LPCMP_RRCR2_RR_TIMER_RELOAD(value);
+
+    base->RRCR2 = tmp32;
+}
+
+#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpcmp.h

@@ -1,14 +1,14 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2020 NXP
+ * Copyright 2016-2020, 2023-2024 NXP
  * All rights reserved.
  *
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_LPCMP_H_
-#define _FSL_LPCMP_H_
+#ifndef FSL_LPCMP_H_
+#define FSL_LPCMP_H_
 
 #include "fsl_common.h"
 
@@ -20,22 +20,35 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
-
 /*! @name Driver version */
-/*@{*/
-/*! @brief LPCMP driver version 2.0.3. */
-#define FSL_LPCMP_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
-/*@}*/
+/*! @{ */
+/*! @brief LPCMP driver version 2.1.3. */
+#define FSL_LPCMP_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
+/*! @} */
+
+#define LPCMP_CCR1_COUTA_CFG_MASK  (LPCMP_CCR1_COUTA_OWEN_MASK | LPCMP_CCR1_COUTA_OW_MASK)
+#define LPCMP_CCR1_COUTA_CFG_SHIFT LPCMP_CCR1_COUTA_OWEN_SHIFT
+#define LPCMP_CCR1_COUTA_CFG(x) \
+    (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_CFG_SHIFT)) & LPCMP_CCR1_COUTA_CFG_MASK)
+
+#define LPCMP_CCR1_EVT_SEL_CFG_MASK  (LPCMP_CCR1_EVT_SEL_MASK | LPCMP_CCR1_WINDOW_CLS_MASK)
+#define LPCMP_CCR1_EVT_SEL_CFG_SHIFT LPCMP_CCR1_WINDOW_CLS_SHIFT
+#define LPCMP_CCR1_EVT_SEL_CFG(x) \
+    (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_CFG_SHIFT)) & LPCMP_CCR1_EVT_SEL_CFG_MASK)
 
 /*!
  * @brief LPCMP status falgs mask.
  */
 enum _lpcmp_status_flags
 {
-    kLPCMP_OutputRisingEventFlag  = LPCMP_CSR_CFR_MASK,  /*!< Rising-edge on the comparison output has occurred. */
-    kLPCMP_OutputFallingEventFlag = LPCMP_CSR_CFF_MASK,  /*!< Falling-edge on the comparison output has occurred. */
-    kLPCMP_OutputAssertEventFlag  = LPCMP_CSR_COUT_MASK, /*!< Return the current value of the analog comparator output.
-                                                              The flag does not support W1C. */
+    kLPCMP_OutputRisingEventFlag  = LPCMP_CSR_CFR_MASK,    /*!< Rising-edge on the comparison output has occurred. */
+    kLPCMP_OutputFallingEventFlag = LPCMP_CSR_CFF_MASK,    /*!< Falling-edge on the comparison output has occurred. */
+#if defined(FSL_FEATURE_LPCMP_HAS_CSR_RRF) && FSL_FEATURE_LPCMP_HAS_CSR_RRF
+    kLPCMP_OutputRoundRobinEventFlag = LPCMP_CSR_RRF_MASK, /*!< Detects when any channel's last comparison result is
+                                                                different from the pre-set value in trigger mode. */
+#endif                                                     /* FSL_FEATURE_LPCMP_HAS_CSR_RRF */
+    kLPCMP_OutputAssertEventFlag = LPCMP_CSR_COUT_MASK, /*!< Return the current value of the analog comparator output.
+                                                             The flag does not support W1C. */
 };
 
 /*!
@@ -45,7 +58,12 @@ enum _lpcmp_interrupt_enable
 {
     kLPCMP_OutputRisingInterruptEnable  = LPCMP_IER_CFR_IE_MASK, /*!< Comparator interrupt enable rising. */
     kLPCMP_OutputFallingInterruptEnable = LPCMP_IER_CFF_IE_MASK, /*!< Comparator interrupt enable falling. */
+#if defined(FSL_FEATURE_LPCMP_HAS_IER_RRF_IE) && FSL_FEATURE_LPCMP_HAS_IER_RRF_IE
+    kLPCMP_RoundRobinInterruptEnable = LPCMP_IER_RRF_IE_MASK,    /*!< Comparator round robin mode interrupt
+                                       occurred when the comparison result changes for a given channel. */
+#endif                                                           /* FSL_FEATURE_LPCMP_HAS_IER_RRF_IE */
 };
+
 /*!
  * @brief LPCMP hysteresis mode. See chip data sheet to get the actual hystersis
  *        value with each level
@@ -77,6 +95,79 @@ typedef enum _lpcmp_dac_reference_voltage_source
     kLPCMP_VrefSourceVin2 = 1U, /*!< vrefh_ext is selected as resistor ladder network supply reference Vin. */
 } lpcmp_dac_reference_voltage_source_t;
 
+#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL
+/*!
+ * @brief LPCMP functional mode clock source selection.
+ *
+ * Note: In different devices, the functional mode clock source selection is different,
+ * please refer to specific device Reference Manual for details.
+ */
+typedef enum _lpcmp_functional_source_clock
+{
+    kLPCMP_FunctionalClockSource0 = 0U, /*!< Select functional mode clock source0. */
+    kLPCMP_FunctionalClockSource1 = 1U, /*!< Select functional mode clock source1. */
+    kLPCMP_FunctionalClockSource2 = 2U, /*!< Select functional mode clock source2. */
+    kLPCMP_FunctionalClockSource3 = 3U, /*!< Select functional mode clock source3. */
+} lpcmp_functional_source_clock_t;
+#endif                                  /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */
+
+#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL
+/*!
+ * @brief Set the COUTA signal value when the window is closed.
+ */
+typedef enum _lpcmp_couta_signal
+{
+    kLPCMP_COUTASignalNoSet = 0U, /*!< NO set the COUTA signal value when the window is closed. */
+    kLPCMP_COUTASignalLow   = 1U, /*!< Set COUTA signal low(0) when the window is closed. */
+    kLPCMP_COUTASignalHigh  = 3U, /*!< Set COUTA signal high(1) when the window is closed. */
+} lpcmp_couta_signal_t;
+
+/*!
+ * @brief Set COUT event, which can close the active window in window mode.
+ */
+typedef enum _lpcmp_close_window_event
+{
+    kLPCMP_CLoseWindowEventNoSet      = 0U, /*!< No Set COUT event, which can close the active window in window mode. */
+    kLPCMP_CloseWindowEventRisingEdge = 1U, /*!< Set rising edge COUT signal as COUT event. */
+    kLPCMP_CloseWindowEventFallingEdge = 3U, /*!< Set falling edge COUT signal as COUT event. */
+    kLPCMP_CLoseWindowEventBothEdge    = 5U, /*!< Set both rising and falling edge COUT signal as COUT event. */
+} lpcmp_close_window_event_t;
+#endif                                       /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */
+
+#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE
+/*!
+ * @brief LPCMP round robin mode fixed mux port.
+ */
+typedef enum _lpcmp_roundrobin_fixedmuxport
+{
+    kLPCMP_FixedPlusMuxPort  = 0U, /*!< Fixed plus mux port. */
+    kLPCMP_FixedMinusMuxPort = 1U, /*!< Fixed minus mux port. */
+} lpcmp_roundrobin_fixedmuxport_t;
+
+/*!
+ * @brief LPCMP round robin mode clock source selection.
+ *
+ * Note: In different devices,the round robin mode clock source selection is different,
+ * please refer to the specific device Reference Manual for details.
+ */
+typedef enum _lpcmp_roundrobin_clock_source
+{
+    kLPCMP_RoundRobinClockSource0 = 0U, /*!< Select roundrobin mode clock source0. */
+    kLPCMP_RoundRobinClockSource1 = 1U, /*!< Select roundrobin mode clock source1. */
+    kLPCMP_RoundRobinClockSource2 = 2U, /*!< Select roundrobin mode clock source2. */
+    kLPCMP_RoundRobinClockSource3 = 3U, /*!< Select roundrobin mode clock source3. */
+} lpcmp_roundrobin_clock_source_t;
+
+/*!
+ * @brief LPCMP round robin mode trigger source.
+ */
+typedef enum _lpcmp_roundrobin_trigger_source
+{
+    kLPCMP_TriggerSourceExternally = 0U, /*!< Select external trigger source. */
+    kLPCMP_TriggerSourceInternally = 1U, /*!< Select internal trigger source. */
+} lpcmp_roundrobin_trigger_source_t;
+#endif                                   /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */
+
 /*!
  * @brief Configure the filter.
  */
@@ -85,8 +176,8 @@ typedef struct _lpcmp_filter_config
     bool enableSample;          /*!< Decide whether to use the external SAMPLE as a sampling clock input. */
     uint8_t filterSampleCount;  /*!< Filter Sample Count. Available range is 1-7; 0 disables the filter. */
     uint8_t filterSamplePeriod; /*!< Filter Sample Period. The divider to the bus clock. Available range is 0-255. The
-                                sampling clock must be at least 4 times slower than the system clock to the comparator.
-                                So if enableSample is "false", filterSamplePeriod should be set greater than 4.*/
+                            sampling clock must be at least 4 times slower than the system clock to the comparator.
+                            So if enableSample is "false", filterSamplePeriod should be set greater than 4.*/
 } lpcmp_filter_config_t;
 
 /*!
@@ -96,7 +187,8 @@ typedef struct _lpcmp_dac_config
 {
     bool enableLowPowerMode;                                     /*!< Decide whether to enable DAC low power mode. */
     lpcmp_dac_reference_voltage_source_t referenceVoltageSource; /*!< Internal DAC supply voltage reference source. */
-    uint8_t DACValue; /*!< Value for the DAC Output Voltage. Available range is 0-63.*/
+    uint8_t DACValue; /*!< Value for the DAC Output Voltage. Different devices has different available range,
+                           for specific values, please refer to the reference manual.*/
 } lpcmp_dac_config_t;
 
 /*!
@@ -104,19 +196,71 @@ typedef struct _lpcmp_dac_config
  */
 typedef struct _lpcmp_config
 {
-    bool enableStopMode;      /*!< Decide whether to enable the comparator when in STOP modes. */
+#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN)
+    bool enableStopMode; /*!< Decide whether to enable the comparator when in STOP modes. */
+#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */
+
     bool enableOutputPin;     /*!< Decide whether to enable the comparator is available in selected pin. */
     bool useUnfilteredOutput; /*!< Decide whether to use unfiltered output. */
     bool enableInvertOutput;  /*!< Decide whether to inverts the comparator output. */
-    lpcmp_hysteresis_mode_t hysteresisMode; /*!< LPCMP hysteresis mode. */
-    lpcmp_power_mode_t powerMode;           /*!< LPCMP power mode. */
+    lpcmp_hysteresis_mode_t hysteresisMode;                /*!< LPCMP hysteresis mode. */
+    lpcmp_power_mode_t powerMode;                          /*!< LPCMP power mode. */
+#if defined(FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL) && FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL
+    lpcmp_functional_source_clock_t functionalSourceClock; /*!< Select LPCMP functional mode clock source. */
+#endif                                                     /* FSL_FEATURE_LPCMP_HAS_CCR1_FUNC_CLK_SEL */
 } lpcmp_config_t;
+
+#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL
+/*!
+ * @brief Configure the window mode control.
+ */
+typedef struct _lpcmp_window_control_config
+{
+    bool enableInvertWindowSignal;    /*!< True: enable invert window signal, False: disable invert window signal. */
+    lpcmp_couta_signal_t COUTASignal; /*!< Decide whether to define the COUTA signal value when the window is closed. */
+    lpcmp_close_window_event_t closeWindowEvent; /*!< Decide whether to select COUT event signal edge defines
+                                                      a COUT event to close window. */
+} lpcmp_window_control_config_t;
+#endif                                           /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */
+
+#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE
+/*!
+ * @brief Configure the round robin mode.
+ */
+typedef struct _lpcmp_roundrobin_config
+{
+    uint8_t initDelayModules;   /*!< Comparator and DAC initialization delay modulus, See Reference Manual and DataSheet
+                                     for specific value. */
+    uint8_t sampleClockNumbers; /*!< Specify the number of the round robin clock cycles(0~3) to wait after scanning the
+                                     active channel before sampling the channel's comparison result. */
+    uint8_t channelSampleNumbers; /*!< Specify the number of samples for one channel, note that channelSampleNumbers
+                                       must not smaller than sampleTimeThreshhold. */
+    uint8_t sampleTimeThreshhold; /*!< Specify that for one channel, when (sampleTimeThreshhold + 1) sample results are
+                                       "1",the final result is "1", otherwise the final result is "0", note that the
+                                       sampleTimeThreshhold must not be larger than channelSampleNumbers. */
+    lpcmp_roundrobin_clock_source_t roundrobinClockSource;     /*!< Decide which clock source to
+                                                        choose in round robin mode. */
+    lpcmp_roundrobin_trigger_source_t roundrobinTriggerSource; /*!< Decide which trigger source to
+                                                        choose in round robin mode. */
+    lpcmp_roundrobin_fixedmuxport_t fixedMuxPort;              /*!< Decide which mux port to choose as
+                                                        fixed channel in round robin mode. */
+    uint8_t fixedChannel;       /*!< Indicate which channel of the fixed mux port is used in round robin mode. */
+    uint8_t checkerChannelMask; /*!< Indicate which channel of the non-fixed mux port to check its voltage value in
+                                     round robin mode, for example, if checkerChannelMask set to 0x11U means select
+                                     channel 0 and channel 4 as checker channel.*/
+} lpcmp_roundrobin_config_t;
+#endif                          /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */
+
 /*******************************************************************************
  * API
  ******************************************************************************/
 
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
 /*!
- * @name Initialization
+ * @name Initialization and configuration
  * @{
  */
 
@@ -161,6 +305,7 @@ void LPCMP_Deinit(LPCMP_Type *base);
  *   config->enableInvertOutput  = false;
  *   config->hysteresisMode      = kLPCMP_HysteresisLevel0;
  *   config->powerMode           = kLPCMP_LowSpeedPowerMode;
+ *   config->functionalSourceClock = kLPCMP_FunctionalClockSource0;
  * @endcode
  * @param config Pointer to "lpcmp_config_t" structure.
  */
@@ -215,27 +360,6 @@ static inline void LPCMP_EnableDMA(LPCMP_Type *base, bool enable)
     }
 }
 
-/*!
- * @brief Enable/Disable window mode.When any windowed mode is active, COUTA is clocked by
- *        the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0.
- *        The optionally inverted comparator output COUT_RAW is sampled on every bus clock
- *        when WINDOW=1 to generate COUTA.
- *
- * @param base LPCMP peripheral base address.
- * @param enable "true" means enable window mode, and "false" means disable window mode.
- */
-static inline void LPCMP_EnableWindowMode(LPCMP_Type *base, bool enable)
-{
-    if (enable)
-    {
-        base->CCR1 |= LPCMP_CCR1_WINDOW_EN_MASK;
-    }
-    else
-    {
-        base->CCR1 &= ~LPCMP_CCR1_WINDOW_EN_MASK;
-    }
-}
-
 /*!
  * @brief Configures the filter.
  *
@@ -297,8 +421,165 @@ static inline void LPCMP_ClearStatusFlags(LPCMP_Type *base, uint32_t mask)
     base->CSR = mask;
 }
 
-/*@}*/
+/*! @} */
+
+/*!
+ * @name Window mode
+ * @{
+ */
+
+/*!
+ * @brief Enable/Disable window mode.When any windowed mode is active, COUTA is clocked by
+ *        the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0.
+ *        The optionally inverted comparator output COUT_RAW is sampled on every bus clock
+ *        when WINDOW=1 to generate COUTA.
+ *
+ * @param base LPCMP peripheral base address.
+ * @param enable "true" means enable window mode, and "false" means disable window mode.
+ */
+static inline void LPCMP_EnableWindowMode(LPCMP_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CCR1 |= LPCMP_CCR1_WINDOW_EN_MASK;
+    }
+    else
+    {
+        base->CCR1 &= ~LPCMP_CCR1_WINDOW_EN_MASK;
+    }
+}
+
+#if defined(FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL) && FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL
+/*!
+ * @brief Configure the window control, users can use this API to implement operations on the window,
+ * such as inverting the window signal, setting the window closing event(only valid in windowing mode),
+ * and setting the COUTA signal after the window is closed(only valid in windowing mode).
+ *
+ * @param base LPCMP peripheral base address.
+ * @param config Pointer "lpcmp_window_control_config_t" structure.
+ */
+void LPCMP_SetWindowControl(LPCMP_Type *base, const lpcmp_window_control_config_t *config);
+#endif /* FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL */
+
+/*! @} */
+
+#if defined(FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE) && FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE
+/*!
+ * @name RoundRobin mode
+ * @{
+ */
+
+/*!
+ * @brief Configure the roundrobin mode.
+ *
+ * @param base LPCMP peripheral base address.
+ * @param config Pointer "lpcmp_roundrobin_config_t" structure.
+ */
+void LPCMP_SetRoundRobinConfig(LPCMP_Type *base, const lpcmp_roundrobin_config_t *config);
+
+/*!
+ * brief Configure the roundrobin internal timer reload value.
+ *
+ * param base LPCMP peripheral base address.
+ * param value RoundRobin internal timer reload value, allowed range:0x0UL-0xFFFFFFFUL.
+ */
+void LPCMP_SetRoundRobinInternalTimer(LPCMP_Type *base, uint32_t value);
+
+/*!
+ * @brief Enable/Disable roundrobin mode.
+ *
+ * @param base LPCMP peripheral base address.
+ * @param enable "true" means enable roundrobin mode, and "false" means disable roundrobin mode.
+ */
+static inline void LPCMP_EnableRoundRobinMode(LPCMP_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->RRCR0 |= LPCMP_RRCR0_RR_EN_MASK;
+    }
+    else
+    {
+        base->RRCR0 &= ~LPCMP_RRCR0_RR_EN_MASK;
+    }
+}
+
+/*!
+ * @brief Enable/Disable roundrobin internal timer, note that this function is only valid
+ * when using the internal trigger source.
+ *
+ * @param base LPCMP peripheral base address.
+ * @param enable "true" means enable roundrobin internal timer, and "false" means disable roundrobin internal timer.
+ */
+static inline void LPCMP_EnableRoundRobinInternalTimer(LPCMP_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->RRCR2 |= LPCMP_RRCR2_RR_TIMER_EN_MASK;
+    }
+    else
+    {
+        base->RRCR2 &= ~LPCMP_RRCR2_RR_TIMER_EN_MASK;
+    }
+}
+
+/*!
+ * @brief Set preset value for all channels, users can set all channels' preset vaule through this API,
+ * for example, if the mask set to 0x03U means channel0 and channel2's preset value set to 1U and other
+ * channels' preset value set to 0U.
+ *
+ * @param base LPCMP peripheral base address.
+ * @param mask Mask of channel index.
+ */
+static inline void LPCMP_SetPreSetValue(LPCMP_Type *base, uint8_t mask)
+{
+    base->RRCSR = (uint32_t)mask;
+}
+
+/*!
+ * @brief Get comparison results for all channels, users can get all channels' comparison
+ * results through this API.
+ *
+ * @param base LPCMP peripheral base address.
+ * @return return All channels' comparison result.
+ */
+static inline uint8_t LPCMP_GetComparisonResult(LPCMP_Type *base)
+{
+    return (uint8_t)base->RRCSR;
+}
+
+/*!
+ * @brief Clear input changed flags for single channel or multiple channels, users can clear
+ * input changed flag of a single channel or multiple channels through this API, for example,
+ * if the mask set to 0x03U means clear channel0 and channel2's input changed flags.
+ *
+ * @param base LPCMP peripheral base address.
+ * @param mask Mask of channel index.
+ */
+static inline void LPCMP_ClearInputChangedFlags(LPCMP_Type *base, uint8_t mask)
+{
+    base->RRSR = (uint32_t)mask;
+}
+
+/*!
+ * @brief Get input changed flags for all channels, Users can get all channels' input changed
+ * flags through this API.
+ *
+ * @param base LPCMP peripheral base address.
+ * @return return All channels' changed flag.
+ */
+static inline uint8_t LPCMP_GetInputChangedFlags(LPCMP_Type *base)
+{
+    return (uint8_t)base->RRSR;
+}
+
+/*! @} */
+
+#endif /* FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE */
+
+#if defined(__cplusplus)
+}
+#endif
 
-/*@}*/
+/*! @} */
 
-#endif /* _FSL_LPCMP_H_ */
+#endif /* FSL_LPCMP_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpflexcomm.c

@@ -32,6 +32,11 @@ typedef union pvoid_to_u32
 /*! @brief check whether lpflexcomm supports peripheral type */
 static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_PERIPH_T periph);
 
+/*! @brief Changes LP_FLEXCOMM mode. */
+static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock);
+
+/*! @brief Common LPFLEXCOMM IRQhandle. */
+static void LP_FLEXCOMM_CommonIRQHandler(uint32_t instance);
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -39,6 +44,9 @@ static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_
 /*! @brief Array to map LP_FLEXCOMM instance number to base address. */
 static const uint32_t s_lpflexcommBaseAddrs[] = LP_FLEXCOMM_BASE_ADDRS;
 
+/*! @brief Array to map LP_FLEXCOMM instance PTRS. */
+static LP_FLEXCOMM_Type *const s_lpflexcommBase[] = LP_FLEXCOMM_BASE_PTRS;
+
 /*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
 static lpflexcomm_irq_handler_t s_lpflexcommIrqHandler[LP_FLEXCOMM_PERIPH_LPI2C + 1][ARRAY_SIZE(s_lpflexcommBaseAddrs)];
 
@@ -57,7 +65,6 @@ static const clock_ip_name_t s_lpflexcommClocks[] = LP_FLEXCOMM_CLOCKS;
 /*! @brief Pointers to LP_FLEXCOMM resets for each instance. */
 static const reset_ip_name_t s_lpflexcommResets[] = LP_FLEXCOMM_RSTS;
 #endif
-
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -83,10 +90,20 @@ static bool LP_FLEXCOMM_PeripheralIsPresent(LP_FLEXCOMM_Type *base, LP_FLEXCOMM_
     }
 }
 
+/*! @brief Returns for LP_FLEXCOMM base address. */
+uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance)
+{
+    if(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs))
+    {
+        return s_lpflexcommBaseAddrs[instance];
+    }
+    return 0U;
+}
+
 /*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */
 uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance)
 {
-    LP_FLEXCOMM_Type *base = (LP_FLEXCOMM_Type *)s_lpflexcommBaseAddrs[instance];
+    LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance];
     return base->ISTAT;
 }
 
@@ -114,8 +131,7 @@ uint32_t LP_FLEXCOMM_GetInstance(void *base)
 static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph, int lock)
 {
     assert(periph <= LP_FLEXCOMM_PERIPH_LPI2CAndLPUART);
-    assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs));
-    LP_FLEXCOMM_Type *base = (LP_FLEXCOMM_Type *)s_lpflexcommBaseAddrs[instance];
+    LP_FLEXCOMM_Type *base = s_lpflexcommBase[instance];
 
     /* Check whether peripheral type is present */
     if (!LP_FLEXCOMM_PeripheralIsPresent(base, periph))
@@ -146,15 +162,15 @@ static status_t LP_FLEXCOMM_SetPeriph(uint32_t instance, LP_FLEXCOMM_PERIPH_T pe
 /*! brief Initializes LP_FLEXCOMM and selects peripheral mode according to the second parameter. */
 status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph)
 {
-    assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs));
+    assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable the peripheral clock */
     CLOCK_EnableClock(s_lpflexcommClocks[instance]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 #if !(defined(FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_LP_FLEXCOMM_HAS_NO_RESET)
-    /* Reset the LP_FLEXCOMM module */
-    RESET_PeripheralReset(s_lpflexcommResets[instance]);
+    /* Reset the LP_FLEXCOMM module before configuring it.*/
+    RESET_ClearPeripheralReset(s_lpflexcommResets[instance]);
 #endif
     /* Set the LP_FLEXCOMM to given peripheral */
     return LP_FLEXCOMM_SetPeriph(instance, periph, 0);
@@ -163,11 +179,12 @@ status_t LP_FLEXCOMM_Init(uint32_t instance, LP_FLEXCOMM_PERIPH_T periph)
 /*! brief Deinitializes LP_FLEXCOMM. */
 void LP_FLEXCOMM_Deinit(uint32_t instance)
 {
-    assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs));
+    assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable the peripheral clock */
     CLOCK_DisableClock(s_lpflexcommClocks[instance]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    RESET_SetPeripheralReset(s_lpflexcommResets[instance]);
 }
 
 /*! brief Sets IRQ handler for given LP_FLEXCOMM module. It is used by drivers register IRQ handler according to
@@ -177,7 +194,7 @@ void LP_FLEXCOMM_SetIRQHandler(uint32_t instance,
                                void *lpflexcommHandle,
                                LP_FLEXCOMM_PERIPH_T periph)
 {
-    assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBaseAddrs));
+    assert(instance < (uint32_t)ARRAY_SIZE(s_lpflexcommBase));
     /* Clear handler first to avoid execution of the handler with wrong handle */
     s_lpflexcommIrqHandler[periph][instance] = NULL;
     s_lpflexcommHandle[periph][instance]     = lpflexcommHandle;

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpflexcomm.h

@@ -4,8 +4,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_LP_FLEXCOMM_H_
-#define _FSL_LP_FLEXCOMM_H_
+#ifndef FSL_LP_FLEXCOMM_H_
+#define FSL_LP_FLEXCOMM_H_
 
 #include "fsl_common.h"
 
@@ -15,10 +15,10 @@
  */
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief FlexCOMM driver version. */
-#define FSL_LP_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
-/*@}*/
+#define FSL_LP_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
+/*! @} */
 
 /*! @brief LP_FLEXCOMM peripheral modes. */
 typedef enum
@@ -60,6 +60,9 @@ extern "C" {
 /*! @brief Returns instance number for LP_FLEXCOMM module with given base address. */
 uint32_t LP_FLEXCOMM_GetInstance(void *base);
 
+/*! @brief Returns for LP_FLEXCOMM base address. */
+uint32_t LP_FLEXCOMM_GetBaseAddress(uint32_t instance);
+
 /*! brief Returns for LP_FLEXCOMM interrupt source,see #_lpflexcomm_interrupt_flag. */
 uint32_t LP_FLEXCOMM_GetInterruptStatus(uint32_t instance);
 
@@ -80,6 +83,6 @@ void LP_FLEXCOMM_SetIRQHandler(uint32_t instance,
 }
 #endif
 
-/*@}*/
+/*! @} */
 
-#endif /* _FSL_LP_FLEXCOMM_H_*/
+#endif /* FSL_LP_FLEXCOMM_H_*/

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c.c

@@ -87,6 +87,31 @@ static LPI2C_Type *const kLpi2cBases[] = LPI2C_BASE_PTRS;
 transactional APIs. */
 IRQn_Type const kLpi2cIrqs[] = LPI2C_IRQS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map LPI2C instance number to clock gate enum. */
+static clock_ip_name_t const kLpi2cClocks[] = LPI2C_CLOCKS;
+
+#if defined(LPI2C_PERIPH_CLOCKS)
+/*! @brief Array to map LPI2C instance number to pheripheral clock gate enum. */
+static const clock_ip_name_t kLpi2cPeriphClocks[] = LPI2C_PERIPH_CLOCKS;
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA
+transactional APIs. */
+lpi2c_master_isr_t s_lpi2cMasterIsr;
+
+/*! @brief Pointer to slave IRQ handler for each instance. */
+static lpi2c_slave_isr_t s_lpi2cSlaveIsr;
+
+/*! @brief Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA
+transactional APIs. */
+void *s_lpi2cMasterHandle[ARRAY_SIZE(kLpi2cBases)];
+
+/*! @brief Pointers to slave handles for each instance. */
+static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[ARRAY_SIZE(kLpi2cBases)];
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -343,16 +368,36 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi
     uint32_t cycles;
     uint32_t cfgr2;
     uint32_t value;
-
-#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER)
-    /* initialize flexcomm to LPI2C mode */
-    status_t status = LP_FLEXCOMM_Init(LPI2C_GetInstance(base), LP_FLEXCOMM_PERIPH_LPI2C);
-    if (kStatus_Success != status)
+    uint32_t instance = LPI2C_GetInstance(base);
+    
+    if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U)
     {
-        assert(false);
-    }
+      
+#if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER)
+        /* initialize flexcomm to LPI2C mode */
+        status_t status = LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPI2C);
+        if (kStatus_Success != status)
+        {
+            assert(false);
+        }
 #endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */
+        
+    }
+    else
+    {
+     
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+        /* Ungate the clock. */
+        (void)CLOCK_EnableClock(kLpi2cClocks[instance]);
+#if defined(LPI2C_PERIPH_CLOCKS)
+        /* Ungate the functional clock in initialize function. */
+        CLOCK_EnableClock(kLpi2cPeriphClocks[instance]);
+#endif
 
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+        
+    }
+    
     /* Reset peripheral before configuring it. */
     LPI2C_MasterReset(base);
 
@@ -438,12 +483,28 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi
  */
 void LPI2C_MasterDeinit(LPI2C_Type *base)
 {
+    uint32_t instance = LPI2C_GetInstance(base); 
+    
     /* Restore to reset state. */
     LPI2C_MasterReset(base);
-
+    if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U)
+    {
 #if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER)
-    LP_FLEXCOMM_Deinit(LPI2C_GetInstance(base));
+        LP_FLEXCOMM_Deinit(instance);
 #endif
+    }
+    else
+    {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+        /* Gate clock. */
+        (void)CLOCK_DisableClock(kLpi2cClocks[instance]);
+#if defined(LPI2C_PERIPH_CLOCKS)
+        /* Gate the functional clock. */
+        CLOCK_DisableClock(kLpi2cPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    }
 }
 
 /*!
@@ -957,6 +1018,15 @@ status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t
                 }
             }
         }
+
+        /* Transmit fail */
+        if (kStatus_Success != result)
+        {
+            if ((transfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U)
+            {
+                (void)LPI2C_MasterStop(base);
+            }
+        }
     }
 
     return result;
@@ -987,10 +1057,7 @@ void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base,
     uint32_t instance;
 
     assert(NULL != handle);
-
-    lpi2c_to_lpflexcomm_t handler;
-    (void)memset(&handler, 0, sizeof(handler));
-
+    
     /* Clear out the handle. */
     (void)memset(handle, 0, sizeof(*handle));
 
@@ -1001,9 +1068,23 @@ void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base,
     handle->completionCallback = callback;
     handle->userData           = userData;
 
-    /* Save the handle in global variables to support the double weak mechanism. */
-    handler.lpi2c_master_handler = LPI2C_MasterTransferHandleIRQ;
-    LP_FLEXCOMM_SetIRQHandler(LPI2C_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C);
+    if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U)
+    {
+        lpi2c_to_lpflexcomm_t handler;
+        (void)memset(&handler, 0, sizeof(handler));
+
+        /* Save the handle in global variables to support the double weak mechanism. */
+        handler.lpi2c_master_handler = LPI2C_MasterTransferHandleIRQ;
+        LP_FLEXCOMM_SetIRQHandler(LPI2C_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C);
+    }
+    else
+    {
+         /* Save this handle for IRQ use. */
+        s_lpi2cMasterHandle[instance] = handle;
+
+        /* Set irq handler. */
+        s_lpi2cMasterIsr = LPI2C_MasterTransferHandleIRQ;
+    }
 
     /* Clear internal IRQ enables and enable NVIC IRQ. */
     LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags);
@@ -1598,15 +1679,35 @@ void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig,
 {
     uint32_t tmpReg;
     uint32_t tmpCycle;
+    uint32_t instance = LPI2C_GetInstance(base);
 
+    if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U)
+    {
+      
 #if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER)
-    /* initialize flexcomm to LPI2C mode */
-    status_t status = LP_FLEXCOMM_Init(LPI2C_GetInstance(base), LP_FLEXCOMM_PERIPH_LPI2C);
-    if (kStatus_Success != status)
+        /* initialize flexcomm to LPI2C mode */
+        status_t status = LP_FLEXCOMM_Init(instance, LP_FLEXCOMM_PERIPH_LPI2C);
+        if (kStatus_Success != status)
+        {
+            assert(false);
+        }
+#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */
+        
+    }
+    else
     {
-        assert(false);
+      
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+        /* Ungate the clock. */
+        (void)CLOCK_EnableClock(kLpi2cClocks[instance]);
+#if defined(LPI2C_PERIPH_CLOCKS)
+        /* Ungate the functional clock in initialize function. */
+        CLOCK_EnableClock(kLpi2cPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+      
     }
-#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */
 
     /* Restore to reset conditions. */
     LPI2C_SlaveReset(base);
@@ -1664,11 +1765,28 @@ void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig,
  */
 void LPI2C_SlaveDeinit(LPI2C_Type *base)
 {
-    LPI2C_SlaveReset(base);
+    uint32_t instance = LPI2C_GetInstance(base); 
 
+    /* Restore to reset state. */
+    LPI2C_SlaveReset(base);
+    if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U)
+    {
 #if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER)
-    LP_FLEXCOMM_Deinit(LPI2C_GetInstance(base));
+        LP_FLEXCOMM_Deinit(instance);
 #endif
+    }
+    else
+    {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+        /* Gate clock. */
+        (void)CLOCK_DisableClock(kLpi2cClocks[instance]);
+#if defined(LPI2C_PERIPH_CLOCKS)
+        /* Gate the functional clock. */
+        CLOCK_DisableClock(kLpi2cPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    }
 }
 
 /*!
@@ -1908,10 +2026,7 @@ void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base,
     uint32_t instance;
 
     assert(NULL != handle);
-
-    lpi2c_to_lpflexcomm_t handler;
-    (void)memset(&handler, 0, sizeof(handler));
-
+    
     /* Clear out the handle. */
     (void)memset(handle, 0, sizeof(*handle));
 
@@ -1922,9 +2037,23 @@ void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base,
     handle->callback = callback;
     handle->userData = userData;
 
-    /* Save the handle in global variables to support the double weak mechanism. */
-    handler.lpi2c_slave_handler = LPI2C_SlaveTransferHandleIRQ;
-    LP_FLEXCOMM_SetIRQHandler(LPI2C_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C);
+    if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U)
+    {
+        lpi2c_to_lpflexcomm_t handler;
+        (void)memset(&handler, 0, sizeof(handler));
+
+        /* Save the handle in global variables to support the double weak mechanism. */
+        handler.lpi2c_slave_handler = LPI2C_SlaveTransferHandleIRQ;
+        LP_FLEXCOMM_SetIRQHandler(LPI2C_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C);
+    }
+    else
+    {        
+        /* Save this handle for IRQ use. */
+        s_lpi2cSlaveHandle[instance] = handle;
+
+        /* Set irq handler. */
+        s_lpi2cSlaveIsr = LPI2C_SlaveTransferHandleIRQ;
+    }
 
     /* Clear internal IRQ enables and enable NVIC IRQ. */
     LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags);
@@ -2076,7 +2205,7 @@ void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle)
  * note This function does not need to be called unless you are reimplementing the
  *  non blocking API's interrupt handler routines to add special functionality.
  * param instance The LPI2C instance.
- * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state.
+ * param lpi2cSlaveHandle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state.
  */
 void LPI2C_SlaveTransferHandleIRQ(uint32_t instance, void *lpi2cSlaveHandle)
 {
@@ -2221,7 +2350,7 @@ void LPI2C_SlaveTransferHandleIRQ(uint32_t instance, void *lpi2cSlaveHandle)
                     *xfer->data++ = (uint8_t)base->SRDR;
                     --xfer->dataSize;
                     ++handle->transferredCount;
-                    if (0U != (base->SCFGR1 & LPI2C_SCFGR1_ACKSTALL_MASK))
+					if (0U != (base->SCFGR1 & LPI2C_SCFGR1_ACKSTALL_MASK))
                     {
                         if (((0U == (handle->eventMask & (uint32_t)kLPI2C_SlaveTransmitAckEvent)) ||
                              (NULL == handle->callback)))
@@ -2246,3 +2375,43 @@ void LPI2C_SlaveTransferHandleIRQ(uint32_t instance, void *lpi2cSlaveHandle)
         }
     }
 }
+
+#if !(defined(FSL_FEATURE_I2C_HAS_NO_IRQ) && FSL_FEATURE_I2C_HAS_NO_IRQ)
+/*!
+ * @brief Shared IRQ handler that can call both master and slave ISRs.
+ *
+ * The master and slave ISRs are called through function pointers in order to decouple
+ * this code from the ISR functions. Without this, the linker would always pull in both
+ * ISRs and every function they call, even if only the functional API was used.
+ *
+ * @param base The LPI2C peripheral base address.
+ * @param instance The LPI2C peripheral instance number.
+ */
+void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance);
+void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance)
+{
+    /* Check for master IRQ. */
+    if ((0U != (base->MCR & LPI2C_MCR_MEN_MASK)) && (NULL != s_lpi2cMasterIsr))
+    {
+        /* Master mode. */
+        s_lpi2cMasterIsr(instance, s_lpi2cMasterHandle[instance]);
+    }
+
+    /* Check for slave IRQ. */
+    if ((0U != (base->SCR & LPI2C_SCR_SEN_MASK)) && (NULL != s_lpi2cSlaveIsr))
+    {
+        /* Slave mode. */
+        s_lpi2cSlaveIsr(instance, s_lpi2cSlaveHandle[instance]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(LPI2C15)
+/* Implementation of LPI2C15 handler named in startup code. */
+void LPI2C15_DriverIRQHandler(void);
+void LPI2C15_DriverIRQHandler(void)
+{
+    LPI2C_CommonIRQHandler(LPI2C15, 15U);
+}
+#endif

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c.h

@@ -4,8 +4,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_LPI2C_H_
-#define _FSL_LPI2C_H_
+#ifndef FSL_LPI2C_H_
+#define FSL_LPI2C_H_
 
 #include <stddef.h>
 #include "fsl_device_registers.h"
@@ -22,10 +22,10 @@
  */
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief LPI2C driver version. */
-#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
-/*@}*/
+#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 2, 4))
+/*! @} */
 
 /*! @brief Retry times for waiting flag. */
 #ifndef I2C_RETRY_TIMES
@@ -375,7 +375,7 @@ typedef enum _lpi2c_slave_transfer_event
                                                  (slave-transmitter role). */
     kLPI2C_SlaveReceiveEvent = 0x04U,       /*!< Callback is requested to provide a buffer in which to place received
                                                   data (slave-receiver role). */
-    kLPI2C_SlaveTransmitAckEvent = 0x08U,   /*!< Callback needs to either transmit an ACK or NACK.
+    kLPI2C_SlaveTransmitAckEvent   = 0x08U, /*!< Callback needs to either transmit an ACK or NACK.
               When this event is set, the driver will no longer decide to reply to ack/nack. */
     kLPI2C_SlaveRepeatedStartEvent = 0x10U, /*!< A repeated start was detected. */
     kLPI2C_SlaveCompletionEvent    = 0x20U, /*!< A stop was detected, completing the transfer. */
@@ -436,6 +436,14 @@ struct _lpi2c_slave_handle
 APIs. */
 extern IRQn_Type const kLpi2cIrqs[];
 
+/*! Pointer to master IRQ handler for each instance, used internally for LPI2C master interrupt and EDMA transactional
+APIs. */
+extern lpi2c_master_isr_t s_lpi2cMasterIsr;
+
+/*! Pointers to master handles for each instance, used internally for LPI2C master interrupt and EDMA transactional
+APIs. */
+extern void *s_lpi2cMasterHandle[];
+
 /*******************************************************************************
  * API
  ******************************************************************************/
@@ -461,7 +469,7 @@ uint32_t LPI2C_GetInstance(LPI2C_Type *base);
  */
 
 /*! @name Initialization and deinitialization */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Provides a default configuration for the LPI2C master peripheral.
@@ -552,10 +560,10 @@ static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable)
     base->MCR = (base->MCR & ~LPI2C_MCR_MEN_MASK) | LPI2C_MCR_MEN(enable);
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Status */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Gets the LPI2C master status flags.
@@ -599,10 +607,10 @@ static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statu
     base->MSR = statusMask;
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Interrupts */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Enables the LPI2C master interrupt requests.
@@ -646,10 +654,10 @@ static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base)
     return base->MIER;
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name DMA control */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Enables or disables LPI2C master DMA requests.
@@ -685,10 +693,10 @@ static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base)
     return (uint32_t)&base->MRDR;
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name FIFO control */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Sets the watermarks for LPI2C master FIFOs.
@@ -727,10 +735,10 @@ static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount,
     }
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Bus operations */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Sets the I2C bus frequency for master transactions.
@@ -866,10 +874,10 @@ status_t LPI2C_MasterStop(LPI2C_Type *base);
  */
 status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer);
 
-/*@}*/
+/*! @} */
 
 /*! @name Non-blocking */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Creates a new handle for the LPI2C master non-blocking APIs.
@@ -930,10 +938,10 @@ status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *h
  */
 void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle);
 
-/*@}*/
+/*! @} */
 
 /*! @name IRQ handler */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Reusable routine to handle master interrupts.
@@ -944,7 +952,7 @@ void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle);
  */
 void LPI2C_MasterTransferHandleIRQ(uint32_t instance, void *lpi2cMasterHandle);
 
-/*@}*/
+/*! @} */
 
 /*! @} */
 
@@ -954,7 +962,7 @@ void LPI2C_MasterTransferHandleIRQ(uint32_t instance, void *lpi2cMasterHandle);
  */
 
 /*! @name Slave initialization and deinitialization */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Provides a default configuration for the LPI2C slave peripheral.
@@ -1035,10 +1043,10 @@ static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable)
     base->SCR = (base->SCR & ~LPI2C_SCR_SEN_MASK) | LPI2C_SCR_SEN(enable);
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Slave status */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Gets the LPI2C slave status flags.
@@ -1079,10 +1087,10 @@ static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t status
     base->SSR = statusMask;
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Slave interrupts */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Enables the LPI2C slave interrupt requests.
@@ -1125,10 +1133,10 @@ static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base)
     return base->SIER;
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Slave DMA control */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Enables or disables the LPI2C slave peripheral DMA requests.
@@ -1145,10 +1153,10 @@ static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressVali
                  LPI2C_SDER_AVDE(enableAddressValid) | LPI2C_SDER_RDDE(enableRx) | LPI2C_SDER_TDDE(enableTx);
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Slave bus operations */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Returns whether the bus is idle.
@@ -1236,10 +1244,10 @@ status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *
  */
 status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize);
 
-/*@}*/
+/*! @} */
 
 /*! @name Slave non-blocking */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Creates a new handle for the LPI2C slave non-blocking APIs.
@@ -1309,21 +1317,21 @@ status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *han
  */
 void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle);
 
-/*@}*/
+/*! @} */
 
 /*! @name Slave IRQ handler */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Reusable routine to handle slave interrupts.
  * @note This function does not need to be called unless you are reimplementing the
  *  non blocking API's interrupt handler routines to add special functionality.
  * @param instance The LPI2C instance.
- * @param handle Pointer to lpi2c_slave_handle_t structure which stores the transfer state.
+ * @param lpi2cSlaveHandle Pointer to lpi2c_slave_handle_t structure which stores the transfer state.
  */
 void LPI2C_SlaveTransferHandleIRQ(uint32_t instance, void *lpi2cSlaveHandle);
 
-/*@}*/
+/*! @} */
 
 /*! @} */
 
@@ -1331,4 +1339,4 @@ void LPI2C_SlaveTransferHandleIRQ(uint32_t instance, void *lpi2cSlaveHandle);
 }
 #endif
 
-#endif /* _FSL_LPI2C_H_ */
+#endif /* FSL_LPI2C_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_edma.c

@@ -41,9 +41,6 @@ enum _lpi2c_transfer_states
     kWaitForCompletionState,
 };
 
-/*! @brief Typedef for interrupt handler. */
-typedef void (*lpi2c_isr_t)(LPI2C_Type *base, void *handle);
-
 /*!
  * @brief Used for conversion from `lpflexcomm_irq_handler_t` to `lpi2c_master_isr_t`
  */
@@ -126,7 +123,6 @@ void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base,
 
     /* Look up instance number */
     uint32_t instance = LPI2C_GetInstance(base);
-    lpi2c_to_lpflexcomm_edma_t handler;
 
     /* Clear out the handle. */
     (void)memset(handle, 0, sizeof(*handle));
@@ -139,9 +135,21 @@ void LPI2C_MasterCreateEDMAHandle(LPI2C_Type *base,
     handle->rx                 = rxDmaHandle;
     handle->tx                 = (FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base) > 0) ? txDmaHandle : rxDmaHandle;
 
-    handler.lpi2c_master_handler = LPI2C_MasterTransferEdmaHandleIRQ;
+    if (LP_FLEXCOMM_GetBaseAddress(instance) != 0U)
+    {
+        lpi2c_to_lpflexcomm_edma_t handler;
+        handler.lpi2c_master_handler = LPI2C_MasterTransferEdmaHandleIRQ;
 
-    LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C);
+        LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPI2C);
+    }
+    else
+    {
+        /* Save the handle in global variables to support the double weak mechanism. */
+        s_lpi2cMasterHandle[instance] = handle;
+
+        /* Set LPI2C_MasterTransferEdmaHandleIRQ as LPI2C DMA IRQ handler */
+        s_lpi2cMasterIsr = LPI2C_MasterTransferEdmaHandleIRQ;
+    }
 
     /* Enable interrupt in NVIC. */
     (void)EnableIRQ(kLpi2cIrqs[instance]);
@@ -330,10 +338,17 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
 
         if (commandCount != 0U)
         {
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+            /* Create a software TCD, which will be chained after the commands. */
+            EDMA_TcdResetExt(handle->tx->base, tcd);
+            EDMA_TcdSetTransferConfigExt(handle->tx->base, tcd, &transferConfig, NULL);
+            EDMA_TcdEnableInterruptsExt(handle->tx->base, tcd, (uint32_t)kEDMA_MajorInterruptEnable);
+#else
             /* Create a software TCD, which will be chained after the commands. */
             EDMA_TcdReset(tcd);
             EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL);
             EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable);
+#endif
             linkTcd = tcd;
         }
         else
@@ -371,9 +386,15 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
                enabling rx dma and disabling tx dma, which will be chained onto the commands transfer,
                and create another software TCD of transfering data and chain it onto the last TCD.
                Notice that in this situation assume tx/rx uses same channel */
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+            EDMA_TcdResetExt(handle->rx->base, tcd);
+            EDMA_TcdSetTransferConfigExt(handle->rx->base, tcd, &transferConfig, NULL);
+            EDMA_TcdEnableInterruptsExt(handle->rx->base, tcd, (uint32_t)kEDMA_MajorInterruptEnable);
+#else
             EDMA_TcdReset(tcd);
             EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL);
             EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable);
+#endif
 
             transferConfig.srcAddr          = (uint32_t)&lpi2c_edma_RecSetting;
             transferConfig.destAddr         = (uint32_t) & (base->MDER);
@@ -386,8 +407,13 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
 
             edma_tcd_t *tcdSetRxClearTxDMA = (edma_tcd_t *)((uint32_t)(&handle->tcds[2]) & (~ALIGN_32_MASK));
 
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+            EDMA_TcdResetExt(handle->rx->base, tcdSetRxClearTxDMA);
+            EDMA_TcdSetTransferConfigExt(handle->rx->base, tcdSetRxClearTxDMA, &transferConfig, tcd);
+#else
             EDMA_TcdReset(tcdSetRxClearTxDMA);
             EDMA_TcdSetTransferConfig(tcdSetRxClearTxDMA, &transferConfig, tcd);
+#endif
             linkTcd = tcdSetRxClearTxDMA;
         }
     }

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_edma.h

@@ -5,8 +5,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_LPI2C_EDMA_H_
-#define _FSL_LPI2C_EDMA_H_
+#ifndef FSL_LPI2C_EDMA_H_
+#define FSL_LPI2C_EDMA_H_
 
 #include "fsl_lpi2c.h"
 #include "fsl_edma.h"
@@ -16,10 +16,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief LPI2C EDMA driver version. */
-#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
+#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! @} */
 
 /*!
  * @addtogroup lpi2c_master_edma_driver
@@ -80,7 +80,7 @@ extern "C" {
  */
 
 /*! @name Master DMA */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Create a new handle for the LPI2C master DMA APIs.
@@ -147,7 +147,7 @@ status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_ha
  */
 status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle);
 
-/*@}*/
+/*! @} */
 
 /*! @} */
 
@@ -155,4 +155,4 @@ status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handl
 }
 #endif
 
-#endif /* _FSL_LPI2C_EDMA_H_ */
+#endif /* FSL_LPI2C_EDMA_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_freertos.c

@@ -15,7 +15,7 @@
 static void LPI2C_RTOS_Callback(LPI2C_Type *base, lpi2c_master_handle_t *drv_handle, status_t status, void *userData)
 {
     lpi2c_rtos_handle_t *handle = (lpi2c_rtos_handle_t *)userData;
-    BaseType_t reschedule;
+    BaseType_t reschedule = pdFALSE;
     handle->async_status = status;
     (void)xSemaphoreGiveFromISR(handle->semaphore, &reschedule);
     portYIELD_FROM_ISR(reschedule);

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpi2c_freertos.h

@@ -25,8 +25,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief LPI2C FreeRTOS driver version 2.0.8. */
-#define FSL_LPI2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
+/*! @brief LPI2C FreeRTOS driver version 2.0.0. */
+#define FSL_LPI2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
 /*! @brief LPI2C FreeRTOS handle */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 NXP
+ * Copyright 2022-2024 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -67,7 +67,7 @@ static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base,
  * @brief Combine the write data for 1 byte to 4 bytes.
  * This is not a public API.
  */
-static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap);
+static uint32_t LPSPI_CombineWriteData(const uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap);
 
 /*!
  * @brief Separate the read data for 1 byte to 4 bytes.
@@ -122,9 +122,27 @@ static LPSPI_Type *const s_lpspiBases[] = LPSPI_BASE_PTRS;
 /*! @brief Pointers to lpspi IRQ number for each instance. */
 static const IRQn_Type s_lpspiIRQ[] = LPSPI_IRQS;
 
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to lpspi clocks for each instance. */
+static const clock_ip_name_t s_lpspiClocks[] = LPSPI_CLOCKS;
+
+#if defined(LPSPI_PERIPH_CLOCKS)
+static const clock_ip_name_t s_LpspiPeriphClocks[] = LPSPI_PERIPH_CLOCKS;
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*! @brief Pointers to lpspi handles for each instance. */
+static void *s_lpspiHandle[ARRAY_SIZE(s_lpspiBases)];
+
 /* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/
 volatile uint8_t g_lpspiDummyData[ARRAY_SIZE(s_lpspiBases)] = {0};
 
+/*! @brief Pointer to master IRQ handler for each instance. */
+static lpspi_master_isr_t s_lpspiMasterIsr;
+/*! @brief Pointer to slave IRQ handler for each instance. */
+static lpspi_slave_isr_t s_lpspiSlaveIsr;
+
 /**********************************************************************************************************************
  * Code
  *********************************************************************************************************************/
@@ -179,17 +197,37 @@ void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData)
 void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz)
 {
     assert(masterConfig != NULL);
-
+    
     uint32_t tcrPrescaleValue = 0;
+    uint32_t instance = LPSPI_GetInstance(base);    
 
+    if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U)
+    {
 #if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER)
     /* initialize flexcomm to LPSPI mode */
-    status_t status = LP_FLEXCOMM_Init(LPSPI_GetInstance(base), LP_FLEXCOMM_PERIPH_LPSPI);
-    if (kStatus_Success != status)
+        status_t status = LP_FLEXCOMM_Init(LPSPI_GetInstance(base), LP_FLEXCOMM_PERIPH_LPSPI);
+        if (kStatus_Success != status)
+        {
+            assert(false);
+        }
+#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */
+    }
+    else
     {
-        assert(false);
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+
+        /* Enable LPSPI clock */
+        (void)CLOCK_EnableClock(s_lpspiClocks[instance]);
+
+#if defined(LPSPI_PERIPH_CLOCKS)
+        (void)CLOCK_EnableClock(s_LpspiPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
     }
-#endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */
+
+    /* Disable LPSPI first */
+    LPSPI_Enable(base, false);
 
     /* Set LPSPI to master */
     LPSPI_SetMasterSlaveMode(base, kLPSPI_Master);
@@ -199,9 +237,9 @@ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfi
 
     /* Set Configuration Register 1 related setting.*/
     base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK |
-                                   LPSPI_CFGR1_SAMPLE_MASK | LPSPI_CFGR1_PCSCFG_MASK)) |
+                                   LPSPI_CFGR1_SAMPLE_MASK | LPSPI_CFGR1_PCSCFG_MASK )) |
                   LPSPI_CFGR1_OUTCFG(masterConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(masterConfig->pinCfg) |
-                  LPSPI_CFGR1_NOSTALL(0) | LPSPI_CFGR1_SAMPLE((uint32_t)masterConfig->enableInputDelay) |
+                  LPSPI_CFGR1_NOSTALL(0) | LPSPI_CFGR1_SAMPLE((uint32_t)masterConfig->enableInputDelay )|
                   LPSPI_CFGR1_PCSCFG(masterConfig->pcsFunc);
 
     /* Set baudrate and delay times*/
@@ -251,12 +289,13 @@ void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)
     masterConfig->cpha         = kLPSPI_ClockPhaseFirstEdge;
     masterConfig->direction    = kLPSPI_MsbFirst;
 
-    masterConfig->pcsToSckDelayInNanoSec        = 1000000000U / masterConfig->baudRate * 2U;
-    masterConfig->lastSckToPcsDelayInNanoSec    = 1000000000U / masterConfig->baudRate * 2U;
-    masterConfig->betweenTransferDelayInNanoSec = 1000000000U / masterConfig->baudRate * 2U;
+    masterConfig->pcsToSckDelayInNanoSec        = (1000000000U / masterConfig->baudRate) / 2U;
+    masterConfig->lastSckToPcsDelayInNanoSec    = (1000000000U / masterConfig->baudRate) / 2U;
+    masterConfig->betweenTransferDelayInNanoSec = (1000000000U / masterConfig->baudRate) / 2U;
 
     masterConfig->whichPcs           = kLPSPI_Pcs0;
     masterConfig->pcsActiveHighOrLow = kLPSPI_PcsActiveLow;
+    masterConfig->pcsFunc            = kLPSPI_PcsAsCs; 
 
     masterConfig->pinCfg        = kLPSPI_SdiInSdoOut;
     masterConfig->dataOutConfig = kLpspiDataOutRetained;
@@ -273,23 +312,40 @@ void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)
 void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig)
 {
     assert(slaveConfig != NULL);
+    
+    uint32_t instance = LPSPI_GetInstance(base);
 
+    if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U)
+    {
 #if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER)
     /* initialize flexcomm to LPSPI mode */
-    status_t status = LP_FLEXCOMM_Init(LPSPI_GetInstance(base), LP_FLEXCOMM_PERIPH_LPSPI);
-    if (kStatus_Success != status)
-    {
-        assert(false);
-    }
+        status_t status = LP_FLEXCOMM_Init(LPSPI_GetInstance(base), LP_FLEXCOMM_PERIPH_LPSPI);
+        if (kStatus_Success != status)
+        {
+            assert(false);
+        }
 #endif /* LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER */
+    }
+    else
+    {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+
+        /* Enable LPSPI clock */
+        (void)CLOCK_EnableClock(s_lpspiClocks[instance]);
+
+#if defined(LPSPI_PERIPH_CLOCKS)
+        (void)CLOCK_EnableClock(s_LpspiPeriphClocks[instance]);
+#endif
 
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    }
+    
     LPSPI_SetMasterSlaveMode(base, kLPSPI_Slave);
 
     LPSPI_SetOnePcsPolarity(base, slaveConfig->whichPcs, slaveConfig->pcsActiveHighOrLow);
 
     base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK)) |
-                  LPSPI_CFGR1_OUTCFG(slaveConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(slaveConfig->pinCfg)|
-                  LPSPI_CFGR1_PCSCFG(slaveConfig->pcsFunc);
+                  LPSPI_CFGR1_OUTCFG(slaveConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(slaveConfig->pinCfg);
 
     LPSPI_SetFifoWatermarks(base, (uint32_t)kLpspiDefaultTxWatermark, (uint32_t)kLpspiDefaultRxWatermark);
 
@@ -358,12 +414,28 @@ void LPSPI_Reset(LPSPI_Type *base)
  */
 void LPSPI_Deinit(LPSPI_Type *base)
 {
+    uint32_t instance = LPSPI_GetInstance(base);
+
     /* Reset to default value */
     LPSPI_Reset(base);
-
+    if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U)
+    {
 #if !(defined(LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER) && LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER)
-    LP_FLEXCOMM_Deinit(LPSPI_GetInstance(base));
+        LP_FLEXCOMM_Deinit(instance);
 #endif
+    }
+    else
+    {        
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+        /* Disable LPSPI clock */
+        (void)CLOCK_DisableClock(s_lpspiClocks[instance]);
+
+#if defined(LPSPI_PERIPH_CLOCKS)
+        (void)CLOCK_DisableClock(s_LpspiPeriphClocks[instance]);
+#endif
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+    }
 }
 
 static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base,
@@ -715,9 +787,8 @@ void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base,
                                       void *userData)
 {
     assert(handle != NULL);
-
-    lpspi_to_lpflexcomm_t handler;
-    handler.lpspi_master_handler = LPSPI_MasterTransferHandleIRQ;
+    
+    uint32_t instance = LPSPI_GetInstance(base);
 
     /* Zero the handle. */
     (void)memset(handle, 0, sizeof(*handle));
@@ -725,8 +796,21 @@ void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base,
     handle->callback = callback;
     handle->userData = userData;
 
-    /* Save the handle in global variables to support the double weak mechanism. */
-    LP_FLEXCOMM_SetIRQHandler(LPSPI_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPSPI);
+    if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U)
+    {
+        lpspi_to_lpflexcomm_t handler;
+        handler.lpspi_master_handler = LPSPI_MasterTransferHandleIRQ;
+
+        /* Save the handle in global variables to support the double weak mechanism. */
+        LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPSPI);
+    }
+    else
+    {        
+        s_lpspiHandle[instance] = handle;
+
+        /* Set irq handler. */
+        s_lpspiMasterIsr = LPSPI_MasterTransferHandleIRQ;
+    }
 }
 
 /*!
@@ -847,7 +931,7 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf
     bool isByteSwap = ((transfer->configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U);
     uint8_t bytesEachWrite;
     uint8_t bytesEachRead;
-    uint8_t *txData               = transfer->txData;
+    const uint8_t *txData         = transfer->txData;
     uint8_t *rxData               = transfer->rxData;
     uint8_t dummyData             = g_lpspiDummyData[LPSPI_GetInstance(base)];
     uint32_t readData             = 0U;
@@ -882,9 +966,8 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf
 
     /* Configure transfer control register. */
     base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK |
-                               LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK | LPSPI_TCR_WIDTH_MASK)) |
-                LPSPI_TCR_PCS(whichPcs) |
-                LPSPI_TCR_WIDTH(width);
+                               LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) |
+                LPSPI_TCR_PCS(whichPcs) | LPSPI_TCR_WIDTH(width);
 
     /*TCR is also shared the FIFO, so wait for TCR written.*/
     if (!LPSPI_TxFifoReady(base))
@@ -1118,6 +1201,7 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t
 
     /* Variables */
     bool isRxMask = false;
+    handle->isTxMask = false;
     uint8_t txWatermark;
     uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)];
     uint32_t tmpTimes;
@@ -1566,10 +1650,7 @@ void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base,
     assert(handle != NULL);
 
     /* Get instance from peripheral base address. */
-    // uint32_t instance = LPSPI_GetInstance(base);
-
-    lpspi_to_lpflexcomm_t handler;
-    handler.lpspi_slave_handler = LPSPI_SlaveTransferHandleIRQ;
+    uint32_t instance = LPSPI_GetInstance(base);
 
     /* Zero the handle. */
     (void)memset(handle, 0, sizeof(*handle));
@@ -1577,8 +1658,21 @@ void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base,
     handle->callback = callback;
     handle->userData = userData;
 
-    /* Save the handle in global variables to support the double weak mechanism. */
-    LP_FLEXCOMM_SetIRQHandler(LPSPI_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPSPI);
+    if(LP_FLEXCOMM_GetBaseAddress(instance) != 0U)
+    {      
+        lpspi_to_lpflexcomm_t handler;
+        handler.lpspi_slave_handler = LPSPI_SlaveTransferHandleIRQ;
+        
+        /* Save the handle in global variables to support the double weak mechanism. */
+        LP_FLEXCOMM_SetIRQHandler(instance, handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPSPI);
+    }
+    else
+    {
+        s_lpspiHandle[instance] = handle;
+
+        /* Set irq handler. */
+        s_lpspiSlaveIsr = LPSPI_SlaveTransferHandleIRQ;
+    }
 }
 
 /*!
@@ -1627,7 +1721,6 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *
     uint32_t readRegRemainingTimes;
     uint32_t whichPcs      = (transfer->configFlags & LPSPI_SLAVE_PCS_MASK) >> LPSPI_SLAVE_PCS_SHIFT;
     uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U;
-    uint32_t width          = (transfer->configFlags & LPSPI_SLAVE_WIDTH_MASK) >> LPSPI_SLAVE_WIDTH_SHIFT;
 
     /* Assign the original value for members of transfer handle. */
     handle->state                  = (uint8_t)kLPSPI_Busy;
@@ -1684,8 +1777,7 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *
 
     base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK |
                                LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) |
-                LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_TXMSK(isTxMask) | LPSPI_TCR_PCS(whichPcs) |
-                LPSPI_TCR_WIDTH(width);
+                LPSPI_TCR_RXMSK(isRxMask) | LPSPI_TCR_TXMSK(isTxMask) | LPSPI_TCR_PCS(whichPcs);
 
     /* Enable the NVIC for LPSPI peripheral. Note that below code is useless if the LPSPI interrupt is in INTMUX ,
      * and you should also enable the INTMUX interupt in your application.
@@ -1862,7 +1954,7 @@ void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle)
  *
  * This function processes the LPSPI transmit and receives an IRQ.
  *
- * param base LPSPI instance.
+ * param instance LPSPI instance index.
  * param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
  */
 void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handle)
@@ -1962,7 +2054,9 @@ void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handl
         {
             handle->state = (uint8_t)kLPSPI_Error;
         }
-        handle->errorCount++;
+        handle->errorCount++;     
+        /* ERR051588: Clear FIFO after underrun occurs */   
+        LPSPI_FlushFifo(base, true, false);
     }
     /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */
     if (((LPSPI_GetStatusFlags(base) & (uint32_t)kLPSPI_ReceiveErrorFlag) != 0U) &&
@@ -1978,7 +2072,7 @@ void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handl
     }
 }
 
-static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap)
+static uint32_t LPSPI_CombineWriteData(const uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap)
 {
     assert(txData != NULL);
 
@@ -2160,3 +2254,34 @@ static bool LPSPI_TxFifoReady(LPSPI_Type *base)
 #endif
     return true;
 }
+
+void LPSPI_CommonIRQHandler(LPSPI_Type *base, uint32_t instance);
+void LPSPI_CommonIRQHandler(LPSPI_Type *base, uint32_t instance)
+{
+    assert(s_lpspiHandle[instance] != NULL);
+    if (LPSPI_IsMaster(base))
+    {
+        s_lpspiMasterIsr(instance, (lpspi_master_handle_t *)s_lpspiHandle[instance]);
+    }
+    else
+    {
+        s_lpspiSlaveIsr(instance, (lpspi_slave_handle_t *)s_lpspiHandle[instance]);
+    }
+    SDK_ISR_EXIT_BARRIER;
+}
+
+#if defined(LPSPI14)
+void LPSPI14_DriverIRQHandler(void);
+void LPSPI14_DriverIRQHandler(void)
+{
+    LPSPI_CommonIRQHandler(LPSPI14, 14);
+}
+#endif
+
+#if defined(LPSPI16)
+void LPSPI16_DriverIRQHandler(void);
+void LPSPI16_DriverIRQHandler(void)
+{
+    LPSPI_CommonIRQHandler(LPSPI16, 16);
+}
+#endif

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_LPSPI_H_
-#define _FSL_LPSPI_H_
+#ifndef FSL_LPSPI_H_
+#define FSL_LPSPI_H_
 
 #include "fsl_common.h"
 #include "fsl_lpflexcomm.h"
@@ -21,10 +21,10 @@
  *********************************************************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief LPSPI driver version. */
-#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
-/*@}*/
+#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 6))
+/*! @} */
 
 #ifndef LPSPI_DUMMY_DATA
 /*! @brief LPSPI dummy data if no Tx data.*/
@@ -180,10 +180,11 @@ typedef enum _lpspi_data_out_config
     kLpspiDataOutTristate = 1U  /*!< Data out is tristated when chip select is de-asserted */
 } lpspi_data_out_config_t;
 
+/*! @brief LPSPI cs function configuration. */
 typedef enum _lpspi_pcs_function_config
 {
-    kLPSPI_PcsAsCs = 0U,
-    kLPSPI_PcsAsData = 1U,
+    kLPSPI_PcsAsCs = 0U,        /*!< PCS pin select as cs function */
+    kLPSPI_PcsAsData = 1U,      /*!< PCS pin select as date function */
 } lpspi_pcs_function_config_t;
 
 /*! @brief LPSPI transfer width configuration. */
@@ -206,7 +207,7 @@ typedef enum _lpspi_delay_type
 #define LPSPI_MASTER_PCS_MASK  (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */
 
 #define LPSPI_MASTER_WIDTH_SHIFT (16U)      /*!< LPSPI master width shift macro, internal used */
-#define LPSPI_MASTER_WIDTH_MASK  (0x30000U) /*!< LPSPI master width shift macro, internal used */
+#define LPSPI_MASTER_WIDTH_MASK  (0x30000U) /*!< LPSPI master width shift mask, internal used */
 
 /*! @brief Use this enumeration for LPSPI master transfer configFlags. */
 enum _lpspi_transfer_config_flag_for_master
@@ -219,7 +220,7 @@ enum _lpspi_transfer_config_flag_for_master
     kLPSPI_MasterWidth1 = 0U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 1bit */
     kLPSPI_MasterWidth2 = 1U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 2bit */
     kLPSPI_MasterWidth4 = 2U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 4bit */
-
+    
     kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */
 
     kLPSPI_MasterByteSwap =
@@ -240,9 +241,6 @@ enum _lpspi_transfer_config_flag_for_master
 #define LPSPI_SLAVE_PCS_SHIFT (4U)    /*!< LPSPI slave PCS shift macro , internal used. */
 #define LPSPI_SLAVE_PCS_MASK  (0xF0U) /*!< LPSPI slave PCS shift macro , internal used. */
 
-#define LPSPI_SLAVE_WIDTH_SHIFT (16U)      /*!< LPSPI slave width shift macro, internal used */
-#define LPSPI_SLAVE_WIDTH_MASK  (0x30000U) /*!< LPSPI slave width shift macro, internal used */
-
 /*! @brief Use this enumeration for LPSPI slave transfer configFlags. */
 enum _lpspi_transfer_config_flag_for_slave
 {
@@ -251,10 +249,6 @@ enum _lpspi_transfer_config_flag_for_slave
     kLPSPI_SlavePcs2 = 2U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS2 signal */
     kLPSPI_SlavePcs3 = 3U << LPSPI_SLAVE_PCS_SHIFT, /*!< LPSPI slave transfer use PCS3 signal */
 
-    kLPSPI_SlaveWidth1 = 0U << LPSPI_SLAVE_WIDTH_SHIFT, /*!< LPSPI slave transfer 1bit */
-    kLPSPI_SlaveWidth2 = 1U << LPSPI_SLAVE_WIDTH_SHIFT, /*!< LPSPI slave transfer 2bit */
-    kLPSPI_SlaveWidth4 = 2U << LPSPI_SLAVE_WIDTH_SHIFT, /*!< LPSPI slave transfer 4bit */
-
     kLPSPI_SlaveByteSwap =
         1U << 22 /*!< Is slave swap the byte.
                   * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
@@ -299,8 +293,8 @@ typedef struct _lpspi_master_config
 
     lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data
                                 *during single bit transfers.*/
-
-    lpspi_pcs_function_config_t pcsFunc;
+    
+    lpspi_pcs_function_config_t pcsFunc; /*!< Configures cs pins function.*/
 
     lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated
                                             * between accesses (LPSPI_PCS is negated). */
@@ -322,8 +316,6 @@ typedef struct _lpspi_slave_config
     lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data
                                 *during single bit transfers.*/
 
-    lpspi_pcs_function_config_t pcsFunc;
-
     lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated
                                             * between accesses (LPSPI_PCS is negated). */
 } lpspi_slave_config_t;
@@ -367,7 +359,7 @@ typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base,
 /*! @brief LPSPI master/slave transfer structure.*/
 typedef struct _lpspi_transfer
 {
-    uint8_t *txData;          /*!< Send buffer. */
+    const uint8_t *txData;    /*!< Send buffer. */
     uint8_t *rxData;          /*!< Receive buffer. */
     volatile size_t dataSize; /*!< Transfer bytes. */
 
@@ -393,7 +385,7 @@ struct _lpspi_master_handle
     volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
     volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR. */
 
-    uint8_t *volatile txData;             /*!< Send buffer. */
+    const uint8_t *volatile txData;            /*!< Send buffer. */
     uint8_t *volatile rxData;             /*!< Receive buffer. */
     volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
     volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
@@ -423,7 +415,7 @@ struct _lpspi_slave_handle
     volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
     volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR. */
 
-    uint8_t *volatile txData; /*!< Send buffer. */
+    const uint8_t *volatile txData;           /*!< Send buffer. */
     uint8_t *volatile rxData; /*!< Receive buffer. */
 
     volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
@@ -1165,7 +1157,7 @@ void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle);
  *
  * This function processes the LPSPI transmit and receives an IRQ.
  *
- * @param base LPSPI instance.
+ * @param instance LPSPI instance index.
  * @param handle pointer to lpspi_slave_handle_t structure which stores the transfer state.
  */
 void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handle);
@@ -1180,4 +1172,4 @@ void LPSPI_SlaveTransferHandleIRQ(uint32_t instance, lpspi_slave_handle_t *handl
 
 /*! @}*/
 
-#endif /*_FSL_LPSPI_H_*/
+#endif /*FSL_LPSPI_H_*/

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_edma.c

@@ -181,26 +181,20 @@ static void LPSPI_PrepareTransferEDMA(LPSPI_Type *base)
 }
 
 /*!
- * brief LPSPI master transfer data using eDMA.
+ * brief LPSPI master config transfer parameter using eDMA.
  *
- * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data
- * is transferred, the callback function is called.
- *
- * Note:
- * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4.
- * For bytesPerFrame greater than 4:
- * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4.
- * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
+ * This function is preparing to transfers data using eDMA.
  *
  * param base LPSPI peripheral base address.
  * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
- * param transfer pointer to lpspi_transfer_t structure.
- * return status of status_t.
+ * param configFlags transfer configuration flags. ref _lpspi_transfer_config_flag_for_master.
+ * return Indicates whether LPSPI master transfer was successful or not.
+ * retval kStatus_Success          Execution successfully.
+ * retval kStatus_LPSPI_Busy       The LPSPI device is busy.
  */
-status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)
+status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, uint32_t configFlags)
 {
     assert(handle != NULL);
-    assert(transfer != NULL);
 
     /* Check that we're not busy.*/
     if (handle->state == (uint8_t)kLPSPI_Busy)
@@ -210,41 +204,17 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
 
     /* Disable module before configuration */
     LPSPI_Enable(base, false);
-    /* Check arguements */
-    if (!LPSPI_CheckTransferArgument(base, transfer, true))
-    {
-        return kStatus_InvalidArgument;
-    }
 
     LPSPI_PrepareTransferEDMA(base);
 
-    /* Variables */
-    bool isThereExtraTxBytes = false;
-    bool isByteSwap          = ((transfer->configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U);
-    bool isPcsContinuous     = ((transfer->configFlags & (uint32_t)kLPSPI_MasterPcsContinuous) != 0U);
-    uint32_t instance        = LPSPI_GetInstance(base);
-    uint8_t dummyData        = g_lpspiDummyData[instance];
-    uint8_t bytesLastWrite   = 0;
+    bool isByteSwap      = ((configFlags & (uint32_t)kLPSPI_MasterByteSwap) != 0U);
+    bool isPcsContinuous = ((configFlags & (uint32_t)kLPSPI_MasterPcsContinuous) != 0U);
+    uint32_t instance    = LPSPI_GetInstance(base);
+    uint8_t dummyData    = g_lpspiDummyData[instance];
     /*Used for byte swap*/
-    uint32_t addrOffset    = 0;
-    uint32_t rxAddr        = LPSPI_GetRxRegisterAddress(base);
-    uint32_t txAddr        = LPSPI_GetTxRegisterAddress(base);
-    uint32_t whichPcs      = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT;
-    uint32_t width          = (transfer->configFlags & LPSPI_MASTER_WIDTH_MASK) >> LPSPI_MASTER_WIDTH_SHIFT;
+    uint32_t whichPcs      = (configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT;
     uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U;
-    edma_transfer_config_t transferConfigRx = {0};
-    edma_transfer_config_t transferConfigTx = {0};
-    edma_tcd_t *softwareTCD_pcsContinuous   = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU));
-    edma_tcd_t *softwareTCD_extraBytes      = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU));
 
-    handle->state                  = (uint8_t)kLPSPI_Busy;
-    handle->txData                 = transfer->txData;
-    handle->rxData                 = transfer->rxData;
-    handle->txRemainingByteCount   = transfer->dataSize;
-    handle->rxRemainingByteCount   = transfer->dataSize;
-    handle->totalByteCount         = transfer->dataSize;
-    handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U);
-    handle->readRegRemainingTimes  = handle->writeRegRemainingTimes;
     handle->txBuffIfNull =
         ((uint32_t)dummyData) | ((uint32_t)dummyData << 8) | ((uint32_t)dummyData << 16) | ((uint32_t)dummyData << 24);
     /*The TX and RX FIFO sizes are always the same*/
@@ -265,16 +235,13 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
     /* For DMA transfer , we'd better not masked the transmit data and receive data in TCR since the transfer flow is
      * hard to controlled by software. */
     base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_PCS_MASK)) |
-                LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs) |
-                LPSPI_TCR_WIDTH(width);
-
+                LPSPI_TCR_CONT(isPcsContinuous) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs);
     /*Calculate the bytes for write/read the TX/RX register each time*/
     if (bytesPerFrame <= 4U)
     {
         handle->bytesEachWrite = (uint8_t)bytesPerFrame;
         handle->bytesEachRead  = (uint8_t)bytesPerFrame;
-
-        handle->bytesLastRead = (uint8_t)bytesPerFrame;
+        handle->bytesLastRead  = (uint8_t)bytesPerFrame;
     }
     else
     {
@@ -282,7 +249,77 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
         handle->bytesEachRead  = 4U;
 
         handle->bytesLastRead = 4U;
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief LPSPI master transfer data using eDMA without configs.
+ *
+ * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data
+ * is transferred, the callback function is called.
+ *
+ * Note:
+ * This API is only for transfer through DMA without configuration.
+ * Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once.
+ * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4.
+ * For bytesPerFrame greater than 4:
+ * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4.
+ * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
+ *
+ * param base LPSPI peripheral base address.
+ * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
+ * param transfer pointer to lpspi_transfer_t structure, config field is not working.
+ * return Indicates whether LPSPI master transfer was successful or not.
+ * retval kStatus_Success          Execution successfully.
+ * retval kStatus_LPSPI_Busy       The LPSPI device is busy.
+ * retval kStatus_InvalidArgument  The transfer structure is invalid.
+ */
+status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)
+{
+    assert(handle != NULL);
+    assert(transfer != NULL);
 
+    /* Check that we're not busy.*/
+    if (handle->state == (uint8_t)kLPSPI_Busy)
+    {
+        return kStatus_LPSPI_Busy;
+    }
+
+    /* Check arguements */
+    if (!LPSPI_CheckTransferArgument(base, transfer, true))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Variables */
+    bool isThereExtraTxBytes = false;
+    uint8_t bytesLastWrite   = 0;
+    uint32_t instance        = LPSPI_GetInstance(base);
+    /*Used for byte swap*/
+    uint32_t addrOffset    = 0;
+    uint32_t rxAddr        = LPSPI_GetRxRegisterAddress(base);
+    uint32_t txAddr        = LPSPI_GetTxRegisterAddress(base);
+    uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U;
+    edma_transfer_config_t transferConfigRx = {0};
+    edma_transfer_config_t transferConfigTx = {0};
+    edma_tcd_t *softwareTCD_pcsContinuous   = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU));
+    edma_tcd_t *softwareTCD_extraBytes      = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU));
+
+    handle->state                  = (uint8_t)kLPSPI_Busy;
+    handle->txData                 = transfer->txData;
+    handle->rxData                 = transfer->rxData;
+    handle->txRemainingByteCount   = transfer->dataSize;
+    handle->rxRemainingByteCount   = transfer->dataSize;
+    handle->totalByteCount         = transfer->dataSize;
+    handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U);
+    handle->readRegRemainingTimes  = handle->writeRegRemainingTimes;
+
+    handle->isThereExtraRxBytes = false;
+
+    /*Calculate the bytes for write/read the TX/RX register each time*/
+    if (bytesPerFrame > 4U)
+    {
         if ((transfer->dataSize % 4U) != 0U)
         {
             bytesLastWrite        = (uint8_t)(transfer->dataSize % 4U);
@@ -412,8 +449,20 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
         transferConfigTx.destAddr        = (uint32_t)txAddr + addrOffset;
         transferConfigTx.majorLoopCounts = 1;
 
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+        EDMA_TcdResetExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes);
+        if (handle->isPcsContinuous)
+        {
+            EDMA_TcdSetTransferConfigExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes,
+                                         &transferConfigTx, softwareTCD_pcsContinuous);
+        }
+        else
+        {
+            EDMA_TcdSetTransferConfigExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes,
+                                         &transferConfigTx, NULL);
+        }
+#else
         EDMA_TcdReset(softwareTCD_extraBytes);
-
         if (handle->isPcsContinuous)
         {
             EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, softwareTCD_pcsContinuous);
@@ -422,6 +471,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
         {
             EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL);
         }
+#endif
     }
 
     if (handle->isPcsContinuous)
@@ -439,8 +489,14 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
         transferConfigTx.minorLoopBytes   = 4;
         transferConfigTx.majorLoopCounts  = 1;
 
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+        EDMA_TcdResetExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_pcsContinuous);
+        EDMA_TcdSetTransferConfigExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_pcsContinuous,
+                                     &transferConfigTx, NULL);
+#else
         EDMA_TcdReset(softwareTCD_pcsContinuous);
         EDMA_TcdSetTransferConfig(softwareTCD_pcsContinuous, &transferConfigTx, NULL);
+#endif
     }
 
     if (handle->txData != NULL)
@@ -519,6 +575,34 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
     return kStatus_Success;
 }
 
+/*!
+ * brief LPSPI master transfer data using eDMA.
+ *
+ * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data
+ * is transferred, the callback function is called.
+ *
+ * Note:
+ * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4.
+ * For bytesPerFrame greater than 4:
+ * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4.
+ * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
+ *
+ * param base LPSPI peripheral base address.
+ * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
+ * param transfer pointer to lpspi_transfer_t structure.
+ * return status of status_t.
+ */
+status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)
+{
+    status_t status = kStatus_Fail;
+    status          = LPSPI_MasterTransferPrepareEDMALite(base, handle, transfer->configFlags);
+    if (kStatus_Success != status)
+    {
+        return status;
+    }
+    return LPSPI_MasterTransferEDMALite(base, handle, transfer);
+}
+
 static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle,
                                      void *g_lpspiEdmaPrivateHandle,
                                      bool transferDone,
@@ -715,7 +799,6 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
     uint32_t rxAddr        = LPSPI_GetRxRegisterAddress(base);
     uint32_t txAddr        = LPSPI_GetTxRegisterAddress(base);
     uint32_t whichPcs      = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT;
-    uint32_t width          = (transfer->configFlags & LPSPI_SLAVE_WIDTH_MASK) >> LPSPI_SLAVE_WIDTH_SHIFT;
     uint32_t bytesPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) / 8U + 1U;
     edma_transfer_config_t transferConfigRx = {0};
     edma_transfer_config_t transferConfigTx = {0};
@@ -750,8 +833,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
        any time since we use rx dma transfer finish cllback to indicate transfer finish. */
     base->TCR =
         (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_TXMSK_MASK)) |
-        LPSPI_TCR_TXMSK(transfer->txData == NULL) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs) |
-        LPSPI_TCR_WIDTH(width);
+        LPSPI_TCR_TXMSK(transfer->txData == NULL) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs);
 
     /*Calculate the bytes for write/read the TX/RX register each time*/
     if (bytesPerFrame <= 4U)
@@ -890,8 +972,14 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
             transferConfigTx.destAddr        = (uint32_t)txAddr + addrOffset;
             transferConfigTx.majorLoopCounts = 1;
 
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+            EDMA_TcdResetExt(handle->edmaTxDataToTxRegHandle->base, softwareTCD_extraBytes);
+            EDMA_TcdSetTransferConfigExt(handle->edmaTxDataToTxRegHandle->base, softwareTCD_extraBytes,
+                                         &transferConfigTx, NULL);
+#else
             EDMA_TcdReset(softwareTCD_extraBytes);
             EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL);
+#endif
         }
 
         transferConfigTx.srcAddr         = (uint32_t)(handle->txData);

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_edma.h

@@ -5,8 +5,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_LPSPI_EDMA_H_
-#define _FSL_LPSPI_EDMA_H_
+#ifndef FSL_LPSPI_EDMA_H_
+#define FSL_LPSPI_EDMA_H_
 
 #include "fsl_lpspi.h"
 #include "fsl_edma.h"
@@ -20,10 +20,10 @@
  * Definitions
  **********************************************************************************************************************/
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief LPSPI EDMA driver version. */
-#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
+#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*! @} */
 
 /*!
  * @brief Forward declaration of the _lpspi_master_edma_handle typedefs.
@@ -77,7 +77,7 @@ struct _lpspi_master_edma_handle
     volatile uint8_t bytesLastRead;    /*!< Bytes for last read RDR. */
     volatile bool isThereExtraRxBytes; /*!< Is there extra RX byte. */
 
-    uint8_t *volatile txData;             /*!< Send buffer. */
+    const uint8_t *volatile txData;                 /*!< Send buffer. */
     uint8_t *volatile rxData;             /*!< Receive buffer. */
     volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
     volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
@@ -122,7 +122,7 @@ struct _lpspi_slave_edma_handle
 
     uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
 
-    uint8_t *volatile txData;             /*!< Send buffer. */
+    const uint8_t *volatile txData;                /*!< Send buffer. */
     uint8_t *volatile rxData;             /*!< Receive buffer. */
     volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
     volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
@@ -202,6 +202,46 @@ void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base,
  */
 status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer);
 
+/*!
+ * @brief LPSPI master config transfer parameter while using eDMA.
+ *
+ * This function is preparing to transfer data using eDMA, work with LPSPI_MasterTransferEDMALite. 
+ *
+ * @param base LPSPI peripheral base address.
+ * @param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
+ * @param configFlags transfer configuration flags. @ref _lpspi_transfer_config_flag_for_master.
+ * @return Indicates whether LPSPI master transfer was successful or not.
+ * @retval kStatus_Success          Execution successfully.
+ * @retval kStatus_LPSPI_Busy       The LPSPI device is busy.
+ */
+status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base,
+                                             lpspi_master_edma_handle_t *handle,
+                                             uint32_t configFlags);
+
+/*!
+ * @brief LPSPI master transfer data using eDMA without configs.
+ *
+ * This function transfers data using eDMA. This is a non-blocking function, which returns right away. When all data
+ * is transferred, the callback function is called.
+ *
+ * Note:
+ * This API is only for transfer through DMA without configuration. 
+ * Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once.
+ * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4.
+ * For bytesPerFrame greater than 4:
+ * The transfer data size should be equal to bytesPerFrame if the bytesPerFrame is not an integer multiple of 4.
+ * Otherwise, the transfer data size can be an integer multiple of bytesPerFrame.
+ *
+ * @param base LPSPI peripheral base address.
+ * @param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
+ * @param transfer pointer to lpspi_transfer_t structure, config field is not uesed.
+ * @return Indicates whether LPSPI master transfer was successful or not.
+ * @retval kStatus_Success          Execution successfully.
+ * @retval kStatus_LPSPI_Busy       The LPSPI device is busy.
+ * @retval kStatus_InvalidArgument  The transfer structure is invalid.
+ */
+status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer);
+
 /*!
  * @brief LPSPI master aborts a transfer which is using eDMA.
  *
@@ -298,4 +338,4 @@ status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_hand
 
 /*! @}*/
 
-#endif /*_FSL_LPSPI_EDMA_H_*/
+#endif /*FSL_LPSPI_EDMA_H_*/

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_freertos.c

@@ -15,7 +15,7 @@
 static void LPSPI_RTOS_Callback(LPSPI_Type *base, lpspi_master_handle_t *drv_handle, status_t status, void *userData)
 {
     lpspi_rtos_handle_t *handle = (lpspi_rtos_handle_t *)userData;
-    BaseType_t reschedule;
+    BaseType_t reschedule = pdFALSE;
     handle->async_status = status;
     (void)xSemaphoreGiveFromISR(handle->event, &reschedule);
     portYIELD_FROM_ISR(reschedule);

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpspi_freertos.h

@@ -25,8 +25,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief LPSPI FreeRTOS driver version 2.1.0. */
-#define FSL_LPSPI_FREERTOS_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
+/*! @brief LPSPI FreeRTOS driver version 2.0.0. */
+#define FSL_LPSPI_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
 /*! @brief LPSPI FreeRTOS handle */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lptmr.c

@@ -165,9 +165,19 @@ void LPTMR_GetDefaultConfig(lptmr_config_t *config)
 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \
       FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT)
     config->prescalerClockSource = kLPTMR_PrescalerClock_1;
-#else
+#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT)
     config->prescalerClockSource = kLPTMR_PrescalerClock_0;
-#endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */
+#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT)
+    config->prescalerClockSource = kLPTMR_PrescalerClock_2;
+#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT)
+    config->prescalerClockSource = kLPTMR_PrescalerClock_3;
+#else
+#error No valid source
+#endif
+
     /* Divide the prescaler clock by 2 */
     config->value = kLPTMR_Prescale_Glitch_0;
 }

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lptmr.h

@@ -1,12 +1,12 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_LPTMR_H_
-#define _FSL_LPTMR_H_
+#ifndef FSL_LPTMR_H_
+#define FSL_LPTMR_H_
 
 #include "fsl_common.h"
 
@@ -20,9 +20,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
-#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */
-/*@}*/
+/*! @{ */
+/*! Driver Version */
+#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*! @} */
 
 /*! @brief LPTMR pin selection used in pulse counter mode.*/
 typedef enum _lptmr_pin_select
@@ -74,12 +75,21 @@ typedef enum _lptmr_prescaler_glitch_value
  */
 typedef enum _lptmr_prescaler_clock_select
 {
+#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT)
     kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */
+#endif
+
 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \
       FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT)
     kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */
 #endif                              /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */
+
+#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT)
     kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */
+#endif
+
 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \
       FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT)
     kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */
@@ -371,4 +381,4 @@ static inline void LPTMR_StopTimer(LPTMR_Type *base)
 
 /*! @}*/
 
-#endif /* _FSL_LPTMR_H_ */
+#endif /* FSL_LPTMR_H_ */

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 NXP
+ * Copyright 2022-2024 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -62,6 +62,17 @@ static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t
  */
 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
 
+/*!
+ * @brief Write to TX register using non-blocking method in 9bit or 10bit mode.
+ *
+ * @note This function only support 9bit or 10bit transfer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the buffer to be sent.
+ */
+static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length);
+
 /*!
  * @brief Read RX register using non-blocking method.
  *
@@ -74,6 +85,17 @@ static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size
  */
 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length);
 
+/*!
+ * @brief Read RX register using non-blocking method in 9bit or 10bit mode.
+ *
+ * @note This function only support 9bit or 10bit transfer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ */
+static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length);
+
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -168,6 +190,20 @@ static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size
     }
 }
 
+static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    size_t i;
+
+    /* The Non Blocking write data API assume user have ensured there is enough space in
+    peripheral to write. */
+    for (i = 0; i < length; i++)
+    {
+        base->DATA = data[i];
+    }
+}
+
 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length)
 {
     assert(NULL != data);
@@ -198,6 +234,18 @@ static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t leng
     }
 }
 
+static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    size_t i;
+    /* The Non Blocking read data API assume user have ensured there is enough space in
+    peripheral to write. */
+    for (i = 0; i < length; i++)
+    {
+        data[i] = (uint16_t)(base->DATA & 0x03FFU);
+    }
+}
 /*!
  * brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
  *
@@ -249,16 +297,24 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
     for (osrTemp = 4U; osrTemp <= 32U; osrTemp++)
     {
         /* calculate the temporary sbr value   */
-        sbrTemp = (uint16_t)((srcClock_Hz * 10U / (config->baudRate_Bps * (uint32_t)osrTemp) + 5U) / 10U);
+        sbrTemp = (uint16_t)((srcClock_Hz * 2U / (config->baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U);
         /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
         if (sbrTemp == 0U)
         {
             sbrTemp = 1U;
         }
+        else if (sbrTemp > LPUART_BAUD_SBR_MASK)
+        {
+            sbrTemp = LPUART_BAUD_SBR_MASK;
+        }
+        else
+        {
+            /* For MISRA 15.7 */
+        }
         /* Calculate the baud rate based on the temporary OSR and SBR values */
         calculatedBaud = (srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp));
         tempDiff       = calculatedBaud > config->baudRate_Bps ? (calculatedBaud - config->baudRate_Bps) :
-                                                           (config->baudRate_Bps - calculatedBaud);
+                                                                 (config->baudRate_Bps - calculatedBaud);
 
         if (tempDiff <= baudDiff)
         {
@@ -579,12 +635,21 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s
     for (osrTemp = 4U; osrTemp <= 32U; osrTemp++)
     {
         /* calculate the temporary sbr value   */
-        sbrTemp = (uint16_t)((srcClock_Hz * 10U / (baudRate_Bps * (uint32_t)osrTemp) + 5U) / 10U);
+        sbrTemp = (uint16_t)((srcClock_Hz * 2U / (baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U);
         /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
         if (sbrTemp == 0U)
         {
             sbrTemp = 1U;
         }
+        else if (sbrTemp > LPUART_BAUD_SBR_MASK)
+        {
+            sbrTemp = LPUART_BAUD_SBR_MASK;
+        }
+        else
+        {
+            /* For MISRA 15.7 */
+        }
+
         /* Calculate the baud rate based on the temporary OSR and SBR values */
         calculatedBaud = srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp);
 
@@ -703,6 +768,7 @@ void LPUART_SendAddress(LPUART_Type *base, uint8_t address)
  */
 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
 {
+    uint32_t s_atomicOldInt;
     /* Only consider the real interrupt enable bits. */
     mask &= (uint32_t)kLPUART_AllInterruptEnable;
 
@@ -715,27 +781,36 @@ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
     base->TOSR |= ((mask >> 2U) & 0xF00UL);
 #endif
     /* Check int enable bits in base->BAUD */
-    uint32_t tempReg = base->BAUD;
+    uint32_t baudRegMask = 0UL;
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    tempReg |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK);
+    baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK);
     /* Clear bit 7 from mask */
     mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable;
 #endif
-    tempReg |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK);
+    baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK);
     /* Clear bit 6 from mask */
     mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable;
-    base->BAUD = tempReg;
+
+    s_atomicOldInt = DisableGlobalIRQ();
+    base->BAUD |= baudRegMask;
+    EnableGlobalIRQ(s_atomicOldInt);
 
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     /* Check int enable bits in base->FIFO */
-    base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
+
+    s_atomicOldInt = DisableGlobalIRQ();
+    base->FIFO     = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
                  (mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+    EnableGlobalIRQ(s_atomicOldInt);
+
     /* Clear bit 9 and bit 8 from mask */
     mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable);
 #endif
 
     /* Check int enable bits in base->CTRL */
+    s_atomicOldInt = DisableGlobalIRQ();
     base->CTRL |= mask;
+    EnableGlobalIRQ(s_atomicOldInt);
 }
 
 /*!
@@ -753,6 +828,7 @@ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
  */
 void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
 {
+    uint32_t s_atomicOldInt;
     /* Only consider the real interrupt enable bits. */
     mask &= (uint32_t)kLPUART_AllInterruptEnable;
 
@@ -764,28 +840,37 @@ void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
     /* Timeout interrupt enables. */
     base->TOSR &= ~((mask >> 2U) & 0xF00UL);
 #endif
-    /* Check int enable bits in base->BAUD */
-    uint32_t tempReg = base->BAUD;
+
+    /* Clear int enable bits in base->BAUD */
+    uint32_t baudRegMask = 0UL;
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    tempReg &= ~((mask << 8U) & LPUART_BAUD_LBKDIE_MASK);
+    baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK);
     /* Clear bit 7 from mask */
     mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable;
 #endif
-    tempReg &= ~((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK);
+    baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK);
     /* Clear bit 6 from mask */
     mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable;
-    base->BAUD = tempReg;
+
+    s_atomicOldInt = DisableGlobalIRQ();
+    base->BAUD &= ~baudRegMask;
+    EnableGlobalIRQ(s_atomicOldInt);
 
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     /* Check int enable bits in base->FIFO */
-    base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
+
+    s_atomicOldInt = DisableGlobalIRQ();
+    base->FIFO     = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
                  ~(mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+    EnableGlobalIRQ(s_atomicOldInt);
     /* Clear bit 9 and bit 8 from mask */
     mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable);
 #endif
 
-    /* Check int enable bits in base->CTRL */
+    /* Clear int enable bits in base->CTRL */
+    s_atomicOldInt = DisableGlobalIRQ();
     base->CTRL &= ~mask;
+    EnableGlobalIRQ(s_atomicOldInt);
 }
 
 /*!
@@ -918,8 +1003,8 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
         /* Get the FIFO register value and mask the rx/tx FIFO flush bits and the status bits that can be W1C in case
            they are written 1 accidentally. */
         temp = (uint32_t)base->FIFO;
-        temp &= (uint32_t)(
-            ~(LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK));
+        temp &= (uint32_t)(~(LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK | LPUART_FIFO_TXOF_MASK |
+                             LPUART_FIFO_RXUF_MASK));
         temp |= (mask << 16U) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK);
         base->FIFO = temp;
     }
@@ -1003,6 +1088,67 @@ status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t len
     return kStatus_Success;
 }
 
+/*!
+ * brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode.
+ *
+ * note This function only support 9bit or 10bit transfer.
+ *       Please make sure only 10bit of data is valid and other bits are 0.
+ *
+ * param base LPUART peripheral base address.
+ * param data Start address of the data to write.
+ * param length Size of the data to write.
+ * retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully wrote all data.
+ */
+status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    const uint16_t *dataAddress = data;
+    size_t transferSize         = length;
+
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    while (0U != transferSize)
+    {
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+        while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes))
+#else
+        while (0U == (base->STAT & LPUART_STAT_TDRE_MASK))
+#endif
+        {
+        }
+#if UART_RETRY_TIMES
+        if (0U == waitTimes)
+        {
+            return kStatus_LPUART_Timeout;
+        }
+#endif
+        base->DATA = *(dataAddress);
+        dataAddress++;
+        transferSize--;
+    }
+    /* Ensure all the data in the transmit buffer are sent out to bus. */
+#if UART_RETRY_TIMES
+    waitTimes = UART_RETRY_TIMES;
+    while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes))
+#else
+    while (0U == (base->STAT & LPUART_STAT_TC_MASK))
+#endif
+    {
+    }
+#if UART_RETRY_TIMES
+    if (0U == waitTimes)
+    {
+        return kStatus_LPUART_Timeout;
+    }
+#endif
+    return kStatus_Success;
+}
+
 /*!
  * brief Reads the receiver data register using a blocking method.
  *
@@ -1120,6 +1266,118 @@ status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
     return status;
 }
 
+/*!
+ * brief Reads the receiver data register in 9bit or 10bit mode.
+ *
+ * note This function only support 9bit or 10bit transfer.
+ *
+ * param base LPUART peripheral base address.
+ * param data Start address of the buffer to store the received data by 16bit, only 10bit is valid.
+ * param length Size of the buffer.
+ * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
+ * retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
+ * retval kStatus_LPUART_FramingError Framing error happened while receiving data.
+ * retval kStatus_LPUART_ParityError Parity error happened while receiving data.
+ * retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully received all data.
+ */
+status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    status_t status = kStatus_Success;
+    uint32_t statusFlag;
+    uint16_t *dataAddress = data;
+
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    while (0U != (length--))
+    {
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT))
+#else
+        while (0U == (base->STAT & LPUART_STAT_RDRF_MASK))
+#endif
+        {
+#if UART_RETRY_TIMES
+            if (0U == --waitTimes)
+            {
+                status = kStatus_LPUART_Timeout;
+                break;
+            }
+#endif
+            statusFlag = LPUART_GetStatusFlags(base);
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ?
+                              (kStatus_LPUART_RxHardwareOverrun) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+                /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other
+                 * error flags*/
+                break;
+            }
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ?
+                              (kStatus_LPUART_ParityError) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+            }
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ?
+                              (kStatus_LPUART_FramingError) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+            }
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ?
+                              (kStatus_LPUART_NoiseError) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+            }
+            if (kStatus_Success != status)
+            {
+                break;
+            }
+        }
+        if (kStatus_Success == status)
+        {
+            *(dataAddress) = (uint16_t)(base->DATA & 0x03FFU);
+            dataAddress++;
+        }
+        else
+        {
+            break;
+        }
+    }
+
+    return status;
+}
+
 /*!
  * brief Initializes the LPUART handle.
  *
@@ -1172,6 +1430,7 @@ void LPUART_TransferCreateHandle(LPUART_Type *base,
     /* Initial seven data bits flag */
     handle->isSevenDataBits = isSevenDataBits;
 #endif
+    handle->is16bitData = false;
 
     /* Save the handle in global variables to support the double weak mechanism. */
     LP_FLEXCOMM_SetIRQHandler(LPUART_GetInstance(base), handler.lpflexcomm_handler, handle, LP_FLEXCOMM_PERIPH_LPUART);
@@ -1206,8 +1465,15 @@ void LPUART_TransferStartRingBuffer(LPUART_Type *base,
     assert(NULL != ringBuffer);
 
     /* Setup the ring buffer address */
-    handle->rxRingBuffer     = ringBuffer;
-    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBuffer = ringBuffer;
+    if (!handle->is16bitData)
+    {
+        handle->rxRingBufferSize = ringBufferSize;
+    }
+    else
+    {
+        handle->rxRingBufferSize = ringBufferSize / 2U;
+    }
     handle->rxRingBufferHead = 0U;
     handle->rxRingBufferTail = 0U;
 
@@ -1280,7 +1546,14 @@ status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *hand
     }
     else
     {
-        handle->txData        = xfer->txData;
+        if (!handle->is16bitData)
+        {
+            handle->txData = xfer->txData;
+        }
+        else
+        {
+            handle->txData16 = xfer->txData16;
+        }
         handle->txDataSize    = xfer->dataSize;
         handle->txDataSizeAll = xfer->dataSize;
         handle->txState       = (uint8_t)kLPUART_TxBusy;
@@ -1451,7 +1724,14 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
                 /* Copy data from ring buffer to user memory. */
                 for (i = 0U; i < bytesToCopy; i++)
                 {
-                    xfer->rxData[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail];
+                    if (!handle->is16bitData)
+                    {
+                        xfer->rxData[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail];
+                    }
+                    else
+                    {
+                        xfer->rxData16[bytesCurrentReceived] = handle->rxRingBuffer16[handle->rxRingBufferTail];
+                    }
                     bytesCurrentReceived++;
 
                     /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
@@ -1470,7 +1750,14 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
             if (0U != bytesToReceive)
             {
                 /* No data in ring buffer, save the request to LPUART handle. */
-                handle->rxData        = &xfer->rxData[bytesCurrentReceived];
+                if (!handle->is16bitData)
+                {
+                    handle->rxData = &xfer->rxData[bytesCurrentReceived];
+                }
+                else
+                {
+                    handle->rxData16 = &xfer->rxData16[bytesCurrentReceived];
+                }
                 handle->rxDataSize    = bytesToReceive;
                 handle->rxDataSizeAll = xfer->dataSize;
                 handle->rxState       = (uint8_t)kLPUART_RxBusy;
@@ -1495,7 +1782,14 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
         /* Ring buffer not used. */
         else
         {
-            handle->rxData        = &xfer->rxData[bytesCurrentReceived];
+            if (!handle->is16bitData)
+            {
+                handle->rxData = &xfer->rxData[bytesCurrentReceived];
+            }
+            else
+            {
+                handle->rxData16 = &xfer->rxData16[bytesCurrentReceived];
+            }
             handle->rxDataSize    = bytesToReceive;
             handle->rxDataSizeAll = bytesToReceive;
             handle->rxState       = (uint8_t)kLPUART_RxBusy;
@@ -1627,8 +1921,16 @@ void LPUART_TransferHandleIRQ(uint32_t instance, void *irqHandle)
             tempCount = (uint8_t)MIN(handle->rxDataSize, count);
 
             /* Using non block API to read the data from the registers. */
-            LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
-            handle->rxData = &handle->rxData[tempCount];
+            if (!handle->is16bitData)
+            {
+                LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
+                handle->rxData = &handle->rxData[tempCount];
+            }
+            else
+            {
+                LPUART_ReadNonBlocking16bit(base, handle->rxData16, tempCount);
+                handle->rxData16 = &handle->rxData16[tempCount];
+            }
             handle->rxDataSize -= tempCount;
             count -= tempCount;
 
@@ -1687,8 +1989,16 @@ void LPUART_TransferHandleIRQ(uint32_t instance, void *irqHandle)
 #endif
 
             /* Using non block API to read the data from the registers. */
-            LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
-            handle->rxData = &handle->rxData[tempCount];
+            if (!handle->is16bitData)
+            {
+                LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
+                handle->rxData = &handle->rxData[tempCount];
+            }
+            else
+            {
+                LPUART_ReadNonBlocking16bit(base, handle->rxData16, tempCount);
+                handle->rxData16 = &handle->rxData16[tempCount];
+            }
             handle->rxDataSize -= tempCount;
             count -= tempCount;
 
@@ -1742,10 +2052,24 @@ void LPUART_TransferHandleIRQ(uint32_t instance, void *irqHandle)
                 }
                 else
                 {
-                    handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData;
+                    if (!handle->is16bitData)
+                    {
+                        handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData;
+                    }
+                    else
+                    {
+                        handle->rxRingBuffer16[tpmRxRingBufferHead] = (uint16_t)(tpmData & 0x3FFU);
+                    }
                 }
 #else
-                handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData;
+                if (!handle->is16bitData)
+                {
+                    handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData;
+                }
+                else
+                {
+                    handle->rxRingBuffer16[tpmRxRingBufferHead] = (uint16_t)(tpmData & 0x3FFU);
+                }
 #endif
 
                 /* Increase handle->rxRingBufferHead. */
@@ -1794,8 +2118,16 @@ void LPUART_TransferHandleIRQ(uint32_t instance, void *irqHandle)
 #endif
 
             /* Using non block API to write the data to the registers. */
-            LPUART_WriteNonBlocking(base, handle->txData, tempCount);
-            handle->txData = &handle->txData[tempCount];
+            if (!handle->is16bitData)
+            {
+                LPUART_WriteNonBlocking(base, handle->txData, tempCount);
+                handle->txData = &handle->txData[tempCount];
+            }
+            else
+            {
+                LPUART_WriteNonBlocking16bit(base, handle->txData16, tempCount);
+                handle->txData16 = &handle->txData16[tempCount];
+            }
             handle->txDataSize -= tempCount;
             count -= tempCount;
 

bsp/nxp/mcx/mcxn/Libraries/MCXN947/MCXN947/drivers/fsl_lpuart.h

@@ -1,11 +1,11 @@
 /*
- * Copyright 2022 NXP
+ * Copyright 2022, 2024 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_LPUART_H_
-#define _FSL_LPUART_H_
+#ifndef FSL_LPUART_H_
+#define FSL_LPUART_H_
 
 #include "fsl_common.h"
 #include "fsl_lpflexcomm.h"
@@ -20,10 +20,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief LPUART driver version. */
-#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
-/*@}*/
+#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 3, 2))
+/*! @} */
 
 /*! @brief Retry times for waiting flag. */
 #ifndef UART_RETRY_TIMES
@@ -124,23 +124,23 @@ typedef enum _lpuart_idle_config
 enum _lpuart_interrupt_enable
 {
 #if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR
-    kLPUART_CtsStateChangeInterruptEnable = LPUART_MCR_CTS_MASK, /*!< Change of state on CTS_B pin. bit 0 */
-    kLPUART_DsrStateChangeInterruptEnable = LPUART_MCR_DSR_MASK, /*!< Change of state on DSR_B pin. bit 1 */
-    kLPUART_RinStateChangeInterruptEnable = LPUART_MCR_RIN_MASK, /*!< Change of state on RIN_B pin. bit 2 */
-    kLPUART_DcdStateChangeInterruptEnable = LPUART_MCR_DCD_MASK, /*!< Change of state on DCD_B pin. bit 3 */
+    kLPUART_CtsStateChangeInterruptEnable = LPUART_MCR_CTS_MASK,            /*!< Change of state on CTS_B pin. bit 0 */
+    kLPUART_DsrStateChangeInterruptEnable = LPUART_MCR_DSR_MASK,            /*!< Change of state on DSR_B pin. bit 1 */
+    kLPUART_RinStateChangeInterruptEnable = LPUART_MCR_RIN_MASK,            /*!< Change of state on RIN_B pin. bit 2 */
+    kLPUART_DcdStateChangeInterruptEnable = LPUART_MCR_DCD_MASK,            /*!< Change of state on DCD_B pin. bit 3 */
 #endif
     kLPUART_RxActiveEdgeInterruptEnable = (LPUART_BAUD_RXEDGIE_MASK >> 8U), /*!< Receive Active Edge. bit 6 */
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8U), /*!< LIN break detect. bit 7 */
+    kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8U),      /*!< LIN break detect. bit 7 */
 #endif
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     kLPUART_RxFifoUnderflowInterruptEnable = (LPUART_FIFO_RXUFE_MASK), /*!< Receive FIFO Underflow. bit 8 */
     kLPUART_TxFifoOverflowInterruptEnable  = (LPUART_FIFO_TXOFE_MASK), /*!< Transmit FIFO Overflow. bit 9 */
 #endif
-    kLPUART_RxCounter0TimeoutInterruptEnable = 1UL << 10, /*!< Receiver counter0 timeout. bit 10 */
-    kLPUART_RxCounter1TimeoutInterruptEnable = 1UL << 11, /*!< Receiver counter1 timeout. bit 11 */
-    kLPUART_TxCounter0TimeoutInterruptEnable = 1UL << 12, /*!< Transmitter counter0 timeout. bit 12 */
-    kLPUART_TxCounter1TimeoutInterruptEnable = 1UL << 13, /*!< Transmitter counter1 timeout. bit 13 */
+    kLPUART_RxCounter0TimeoutInterruptEnable = 1UL << 10,              /*!< Receiver counter0 timeout. bit 10 */
+    kLPUART_RxCounter1TimeoutInterruptEnable = 1UL << 11,              /*!< Receiver counter1 timeout. bit 11 */
+    kLPUART_TxCounter0TimeoutInterruptEnable = 1UL << 12,              /*!< Transmitter counter0 timeout. bit 12 */
+    kLPUART_TxCounter1TimeoutInterruptEnable = 1UL << 13,              /*!< Transmitter counter1 timeout. bit 13 */
 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
     kLPUART_DataMatch2InterruptEnable =
         (LPUART_CTRL_MA2IE_MASK), /*!< The next character to be read from LPUART_DATA matches MA2. bit 14 */
@@ -185,9 +185,9 @@ enum _lpuart_flags
 {
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     kLPUART_RxFifoUnderflowFlag =
-        (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred. bit 0 */
+        (LPUART_FIFO_RXUF_MASK >> 16),   /*!< RXUF bit, sets if receive buffer underflow occurred. bit 0 */
     kLPUART_TxFifoOverflowFlag =
-        (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred. bit 1 */
+        (LPUART_FIFO_TXOF_MASK >> 16),   /*!< TXOF bit, sets if transmit buffer overflow occurred. bit 1 */
     kLPUART_RxFifoEmptyFlag =
         (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty. bit 6 */
     kLPUART_TxFifoEmptyFlag =
@@ -200,10 +200,10 @@ enum _lpuart_flags
     kLPUART_RinStateChangeFlag = LPUART_MCR_RIN_MASK << 2U, /*!< Change of state on RIN_B pin. bit 4 */
     kLPUART_DcdStateChangeFlag = LPUART_MCR_DCD_MASK << 2U, /*!< Change of state on DCD_B pin. bit 5 */
 #endif
-    kLPUART_RxCounter0TimeoutFlag = 1UL << 10, /*!< Receiver counter0 timeout. bit 10 */
-    kLPUART_RxCounter1TimeoutFlag = 1UL << 11, /*!< Receiver counter1 timeout. bit 11 */
-    kLPUART_TxCounter0TimeoutFlag = 1UL << 12, /*!< Transmitter counter0 timeout. bit 12 */
-    kLPUART_TxCounter1TimeoutFlag = 1UL << 13, /*!< Transmitter counter1 timeout. bit 13 */
+    kLPUART_RxCounter0TimeoutFlag = 1UL << 10,              /*!< Receiver counter0 timeout. bit 10 */
+    kLPUART_RxCounter1TimeoutFlag = 1UL << 11,              /*!< Receiver counter1 timeout. bit 11 */
+    kLPUART_TxCounter0TimeoutFlag = 1UL << 12,              /*!< Transmitter counter0 timeout. bit 12 */
+    kLPUART_TxCounter1TimeoutFlag = 1UL << 13,              /*!< Transmitter counter1 timeout. bit 13 */
 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
     kLPUART_DataMatch2Flag =
         LPUART_STAT_MA2F_MASK, /*!< The next character to be read from LPUART_DATA matches MA2. bit 14 */
@@ -221,16 +221,16 @@ enum _lpuart_flags
     kLPUART_RxDataRegFullFlag = (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the
                                                             receive data buffer is full. bit 21 */
     kLPUART_TransmissionCompleteFlag =
-        (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete. bit 22 */
+        (LPUART_STAT_TC_MASK),   /*!< Transmission complete flag, sets when transmission activity complete. bit 22 */
     kLPUART_TxDataRegEmptyFlag =
         (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty. bit 23 */
     kLPUART_RxActiveFlag =
-        (LPUART_STAT_RAF_MASK), /*!< Receiver Active Flag (RAF), sets at beginning of valid start. bit 24 */
+        (LPUART_STAT_RAF_MASK),  /*!< Receiver Active Flag (RAF), sets at beginning of valid start. bit 24 */
     kLPUART_RxActiveEdgeFlag = (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets
                                                               when active edge detected. bit 30 */
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break
-                                                         char detected and LIN circuit enabled. bit 31 */
+    kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK),      /*!< LIN break detect interrupt flag, sets when LIN break
+                                                              char detected and LIN circuit enabled. bit 31 */
 #endif
 
     kLPUART_AllClearFlags =
@@ -299,7 +299,8 @@ typedef struct _lpuart_timeout_config
 {
     uint16_t rxExtendedTimeoutValue;            /*!< The number of bits since the last stop bit that is required for an
                   idle condition to be detected. Enable this will disable rxIdleType and rxIdleConfig. Set to 0 to disable. */
-    uint16_t txExtendedTimeoutValue;            /*!< . */
+    uint16_t txExtendedTimeoutValue;            /*!< The transmitter idle time in number of bits (baud rate) whenever an
+                  idle character is queued through the transmit FIFO. */
     lpuart_timeout_counter_config_t rxCounter0; /*!< Rx counter 0 configuration. */
     lpuart_timeout_counter_config_t rxCounter1; /*!< Rx counter 1 configuration. */
     lpuart_timeout_counter_config_t txCounter0; /*!< Tx counter 0 configuration. */
@@ -309,10 +310,10 @@ typedef struct _lpuart_timeout_config
 /*! @brief LPUART configuration structure. */
 typedef struct _lpuart_config
 {
-    uint32_t baudRate_Bps;            /*!< LPUART baud rate  */
-    lpuart_parity_mode_t parityMode;  /*!< Parity mode, disabled (default), even, odd */
-    lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */
-    bool isMsb;                       /*!< Data bits order, LSB (default), MSB */
+    uint32_t baudRate_Bps;                /*!< LPUART baud rate  */
+    lpuart_parity_mode_t parityMode;      /*!< Parity mode, disabled (default), even, odd */
+    lpuart_data_bits_t dataBitsCount;     /*!< Data bits count, eight (default), seven */
+    bool isMsb;                           /*!< Data bits order, LSB (default), MSB */
 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
     lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
 #endif
@@ -326,9 +327,9 @@ typedef struct _lpuart_config
     lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */
     lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */
 #endif
-    lpuart_idle_type_select_t rxIdleType;  /*!< RX IDLE type. */
-    lpuart_idle_config_t rxIdleConfig;     /*!< RX IDLE configuration. */
-    lpuart_timeout_config_t timeoutConfig; /*!< Timeout configuration. */
+    lpuart_idle_type_select_t rxIdleType;     /*!< RX IDLE type. */
+    lpuart_idle_config_t rxIdleConfig;        /*!< RX IDLE configuration. */
+    lpuart_timeout_config_t timeoutConfig;    /*!< Timeout configuration. */
     bool enableSingleWire; /*!< Use TXD pin as the source for the receiver. When enabled the TXD pin should be
                               configured as open drain. */
     uint8_t rtsDelay;      /*!< Delay the negation of RTS by the configured number of bit clocks. */
@@ -345,11 +346,13 @@ typedef struct _lpuart_transfer
      */
     union
     {
-        uint8_t *data;         /*!< The buffer of data to be transfer.*/
-        uint8_t *rxData;       /*!< The buffer to receive data. */
-        const uint8_t *txData; /*!< The buffer of data to be sent. */
+        uint8_t *data;            /*!< The buffer of data to be transfer.*/
+        uint8_t *rxData;          /*!< The buffer to receive data. */
+        uint16_t *rxData16;       /*!< The buffer to receive data. */
+        const uint8_t *txData;    /*!< The buffer of data to be sent. */
+        const uint16_t *txData16; /*!< The buffer of data to be sent. */
     };
-    size_t dataSize; /*!< The byte count to be transfer. */
+    size_t dataSize;              /*!< The byte count to be transfer. */
 } lpuart_transfer_t;
 
 /* Forward declaration of the handle typedef. */
@@ -361,27 +364,40 @@ typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *h
 /*! @brief LPUART handle structure. */
 struct _lpuart_handle
 {
-    const uint8_t *volatile txData; /*!< Address of remaining data to send. */
-    volatile size_t txDataSize;     /*!< Size of the remaining data to send. */
-    size_t txDataSizeAll;           /*!< Size of the data to send out. */
-    uint8_t *volatile rxData;       /*!< Address of remaining data to receive. */
-    volatile size_t rxDataSize;     /*!< Size of the remaining data to receive. */
-    size_t rxDataSizeAll;           /*!< Size of the data to receive. */
-
-    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
-    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
-    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
-    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+    union
+    {
+        const uint8_t *volatile txData;    /*!< Address of remaining data to send. */
+        const uint16_t *volatile txData16; /*!< Address of remaining data to send. */
+    };
+    volatile size_t txDataSize;            /*!< Size of the remaining data to send. */
+    size_t txDataSizeAll;                  /*!< Size of the data to send out. */
+    union
+    {
+        uint8_t *volatile rxData;    /*!< Address of remaining data to receive. */
+        uint16_t *volatile rxData16; /*!< Address of remaining data to receive. */
+    };
+    volatile size_t rxDataSize;      /*!< Size of the remaining data to receive. */
+    size_t rxDataSizeAll;            /*!< Size of the data to receive. */
+
+    union
+    {
+        uint8_t *rxRingBuffer;           /*!< Start address of the receiver ring buffer. */
+        uint16_t *rxRingBuffer16;        /*!< Start address of the receiver ring buffer. */
+    };
+    size_t rxRingBufferSize;             /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead;  /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail;  /*!< Index for the user to get data from the ring buffer. */
 
     lpuart_transfer_callback_t callback; /*!< Callback function. */
     void *userData;                      /*!< LPUART callback function parameter.*/
 
-    volatile uint8_t txState; /*!< TX transfer state. */
-    volatile uint8_t rxState; /*!< RX transfer state. */
+    volatile uint8_t txState;            /*!< TX transfer state. */
+    volatile uint8_t rxState;            /*!< RX transfer state. */
 
 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
     bool isSevenDataBits; /*!< Seven data bits flag. */
 #endif
+    bool is16bitData;     /*!< 16bit data bits flag, only used for 9bit or 10bit data */
 };
 
 /* Typedef for interrupt handler. */
@@ -421,7 +437,7 @@ static inline void LPUART_SoftwareReset(LPUART_Type *base)
     base->GLOBAL |= LPUART_GLOBAL_RST_MASK;
     base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
 }
-/* @} */
+/*! @} */
 #endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/
 
 /*!
@@ -484,7 +500,7 @@ void LPUART_Deinit(LPUART_Type *base);
  * @param config Pointer to a configuration structure.
  */
 void LPUART_GetDefaultConfig(lpuart_config_t *config);
-/* @} */
+/*! @} */
 
 /*!
  * @name Module configuration
@@ -595,7 +611,20 @@ static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water)
     base->WATER = (base->WATER & ~LPUART_WATER_TXWATER_MASK) | LPUART_WATER_TXWATER(water);
 }
 #endif
-/* @} */
+
+/*!
+ * @brief Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode.
+ *
+ * This function Enable 16bit Data transmit in lpuart_handle_t.
+ *
+ * @param handle LPUART handle pointer.
+ * @param enable true to enable, false to disable.
+ */
+static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle, bool enable)
+{
+    handle->is16bitData = enable;
+}
+/*! @} */
 
 /*!
  * @name Status
@@ -641,7 +670,7 @@ uint32_t LPUART_GetStatusFlags(LPUART_Type *base);
  * @retval kStatus_Success Status in the mask are cleared.
  */
 status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask);
-/* @} */
+/*! @} */
 
 /*!
  * @name Interrupts
@@ -699,7 +728,7 @@ void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask);
  * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable.
  */
 uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base);
-/* @} */
+/*! @} */
 
 #if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE
 /*!
@@ -758,7 +787,7 @@ static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)
         base->BAUD &= ~LPUART_BAUD_RDMAE_MASK;
     }
 }
-/* @} */
+/*! @} */
 #endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */
 
 /*!
@@ -907,6 +936,20 @@ void LPUART_SendAddress(LPUART_Type *base, uint8_t address);
  */
 status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
 
+/*!
+ * @brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode.
+ *
+ * @note This function only support 9bit or 10bit transfer.
+ *       Please make sure only 10bit of data is valid and other bits are 0.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_Success Successfully wrote all data.
+ */
+status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length);
+
 /*!
  * @brief Reads the receiver data register using a blocking method.
  *
@@ -925,7 +968,24 @@ status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t len
  */
 status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length);
 
-/* @} */
+/*!
+ * @brief Reads the receiver data register in 9bit or 10bit mode.
+ *
+ * @note This function only support 9bit or 10bit transfer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the buffer to store the received data by 16bit, only 10bit is valid.
+ * @param length Size of the buffer.
+ * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
+ * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
+ * @retval kStatus_LPUART_FramingError Framing error happened while receiving data.
+ * @retval kStatus_LPUART_ParityError Parity error happened while receiving data.
+ * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length);
+
+/*! @} */
 
 /*!
  * @name Transactional
@@ -1117,7 +1177,7 @@ void LPUART_TransferHandleIRQ(uint32_t instance, void *irqHandle);
  */
 void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle);
 
-/* @} */
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -1125,4 +1185,4 @@ void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle);
 
 /*! @}*/
 
-#endif /* _FSL_LPUART_H_ */
+#endif /* FSL_LPUART_H_ */