【更新】STM32CubeMP1_V1.3.0

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xx.h

@@ -70,7 +70,7 @@
   * @brief CMSIS Device version number
   */
 #define __STM32MP1xx_CMSIS_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32MP1xx_CMSIS_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
+#define __STM32MP1xx_CMSIS_VERSION_SUB1   (0x03U) /*!< [23:16] sub1 version */
 #define __STM32MP1xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32MP1xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32MP1xx_CMSIS_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xxxxx-generate-diff.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+# Generate all CMSIS files
+
+currdir=${PWD}
+export scriptPATH=${PWD}/../../../../../../../__INTERNAL__tools/tools/_CmsisDeviceGenerator
+
+if [ ! -d "${scriptPATH}" ] ; then
+  echo Input directory does not exist
+  return
+fi
+
+cd ${scriptPATH}
+
+perl DeviceGeneration.pl  --target STM32MP1xx -diff
+
+cd ${currdir}

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Include/stm32mp1xxxxx-generate-replace.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+# Generate all CMSIS files
+
+currdir=${PWD}
+export scriptPATH=${PWD}/../../../../../../../__INTERNAL__tools/tools/_CmsisDeviceGenerator
+
+if [ ! -d "${scriptPATH}" ] ; then
+  echo Input directory does not exist
+  return
+fi
+
+cd ${scriptPATH}
+
+perl DeviceGeneration.pl  --target STM32MP1xx -replace
+
+cd ${currdir}

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Release_Notes.html

@@ -163,11 +163,11 @@ compliance with the License. You may obtain a copy of the License at:</p>
 </div>
 <div id="release_container" class="topic1">
 <div class="topic2" id="identification">
-<h3 style="width: 230px;">V1.2.0 / 03-Feb-2020</h3>
+<h3 style="width: 230px;">V1.3.0 / 20-oct-2020</h3>
 </div>
 <div style="margin-left: 20px; width: 974px;" class="topic3" id="changes">
 <h4>Main changes</h4>
-<ul><li>Header files:&nbsp;</li><ul><li>Add new Part Number for 800MHz</li><li>Update license with BSD 3-Clause template</li><li>Rework CMSIS for RTC/TAMP, GPIO and TIM</li><li>Rename TIM Break source bit definition</li></ul></ul><ul><li>Update Linker Template&nbsp;file for KEIL and IAR:</li><ul><li>Add OpenAMP region ( region present by default, to comment if needed )</li></ul></ul><br>
+<ul><li>Header files:&nbsp;</li><ul><li>Rename&nbsp;&nbsp;RCC bit definition&nbsp;to be more compliant with the name from RCC spec</li></ul></ul><ul><ul><li>Update STGEN register structure</li><li>Fix typo in MDMA register definition</li></ul></ul><br>
 </div>
 <div class="topic3" id="contents">
 <h4>Contents</h4>
@@ -181,7 +181,13 @@ History</button><br>
 </div>
 <div id="history" class="topic1" hidden="">
 <h2>Update History</h2>
-<br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 26px; width: 174px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 10-Sept-2019</span><br></h3><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
+<br><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 26px; width: 174px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0 / 03-Feb-2020</span><br></h3><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
+<h4>Main changes</h4>
+<ul><li>Header files:&nbsp;</li><ul><li>Add new Part Number for 800MHz</li><li>Update license with BSD 3-Clause template</li><li>Rework CMSIS for RTC/TAMP, GPIO and TIM</li><li>Rename TIM Break source bit definition</li></ul><li>Update Linker Template&nbsp;file for KEIL and IAR:</li><ul><li>Add OpenAMP region ( region present by default, to comment if needed )</li></ul></ul></div><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
+<h4>Contents</h4>
+<ul><li>CMSIS devices files for STM32MP<span style="font-weight: bold;">151C</span>xx ,STM32MP<span style="font-weight: bold;">151A</span>xx, STM32MP<span style="font-weight: bold;">153C</span>xx, STM32MP<span style="font-weight: bold;">153A</span>xx, STM32MP<span style="font-weight: bold;">157C</span>xx ,STM32MP<span style="font-weight: bold;">157A</span>xx</li></ul>
+<br>
+</div><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; margin-left: 26px; width: 174px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 10-Sept-2019</span><br></h3><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
 <h4>Main changes</h4>
 <ul><li>Header files:&nbsp;</li><ul><li>Update FMC bit definition</li><li>Update ETH&nbsp;bit definition</li><li>update EXTI_EXTICR&nbsp;bit definition</li><li>Update I2C&nbsp;bit definition</li><li>Update SPI&nbsp;bit definition (SPI_CR1_CRC33_17, SPI_RXCRC, SPI_IER, SPI_I2SCFGR)&nbsp;</li><li>TMPSENS IP renamed DTS</li><li>Update FDCAN TXBC&nbsp;bit definition</li><li>Update DAC_DHR8RD&nbsp;bit definition</li><li>Add CRYP in STM32MP151Cx and STM32MP153Cx</li><li>Update TIM / LPTIM&nbsp;bit definition + add missing macros</li></ul><li>Update system_stm32mp1xx.c</li><ul><li>Update SystemCoreClock</li></ul><li>Update startup file for KEIL and IAR</li></ul></div><div style="margin-left: 40px; width: 954px;" class="topic3" id="changes">
 <h4>Contents</h4>

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/arm/startup_stm32mp15xx.s

@@ -14,8 +14,8 @@
 ;****************************************************************************** 
 ;* @attention
 ;*
-;* © Copyright (c) 2019 STMicroelectronics. 
-;* All rights reserved.
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
+;* All rights reserved.</center></h2>
 ;*
 ;* This software component is licensed by ST under BSD 3-Clause license,
 ;* the "License"; You may not use this file except in compliance with the 
@@ -30,7 +30,7 @@
 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
 ; </h>
 
-Stack_Size      EQU     0x00000800
+Stack_Size      EQU     0x00000400
 
                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
 __stack_limit

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151a_cm4 .s

@@ -0,0 +1,759 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32mp151a_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32MP15xx Devices vector table for GCC based toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+  .section .startup_copro_fw.Reset_Handler,"ax"
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack      /* set stack pointer */
+
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      _sidata: End of code section, i.e., begin of data sections to copy from.
+ *      _sdata/_edata: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+  
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+  
+/* Call the clock system intitialization function.*/
+
+  bl  SystemInit
+ // ldr r0, =SystemInit
+ // blx r0
+/* Call static constructors */
+ bl __libc_init_array
+ // ldr r0, =__libc_init_array
+ // blx r0
+/* Call the application's entry point.*/
+  bl entry
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack                           // Top of Stack
+  .word  Reset_Handler                     // Reset Handler
+  .word  NMI_Handler                       // NMI Handler
+  .word  HardFault_Handler                 // Hard Fault Handler
+  .word  MemManage_Handler                 // MPU Fault Handler
+  .word  BusFault_Handler                  // Bus Fault Handler
+  .word  UsageFault_Handler                // Usage Fault Handler
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  SVC_Handler                       // SVCall Handler
+  .word  DebugMon_Handler                  // Debug Monitor Handler
+  .word  0                                 // Reserved
+  .word  PendSV_Handler                    // PendSV Handler
+  .word  SysTick_Handler                   // SysTick Handler
+
+                // External Interrupts
+  .word  WWDG1_IRQHandler                  // Window WatchDog 1
+  .word  PVD_AVD_IRQHandler                // PVD and AVD through EXTI Line detection                        
+  .word  TAMP_IRQHandler                   // Tamper and TimeStamps through the EXTI line
+  .word  RTC_WKUP_ALARM_IRQHandler         // RTC Wakeup and Alarm through the EXTI line
+  .word  RESERVED4_IRQHandler              // Reserved
+  .word  RCC_IRQHandler                    // RCC                                             
+  .word  EXTI0_IRQHandler                  // EXTI Line0                                             
+  .word  EXTI1_IRQHandler                  // EXTI Line1                                             
+  .word  EXTI2_IRQHandler                  // EXTI Line2                                             
+  .word  EXTI3_IRQHandler                  // EXTI Line3                                             
+  .word  EXTI4_IRQHandler                  // EXTI Line4 
+  .word  DMA1_Stream0_IRQHandler           // DMA1 Stream 0
+  .word  DMA1_Stream1_IRQHandler           // DMA1 Stream 1                                   
+  .word  DMA1_Stream2_IRQHandler           // DMA1 Stream 2                                   
+  .word  DMA1_Stream3_IRQHandler           // DMA1 Stream 3                                   
+  .word  DMA1_Stream4_IRQHandler           // DMA1 Stream 4                                   
+  .word  DMA1_Stream5_IRQHandler           // DMA1 Stream 5
+  .word  DMA1_Stream6_IRQHandler           // DMA1 Stream 6 
+  .word  ADC1_IRQHandler                   // ADC1                             
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  EXTI5_IRQHandler                  // External Line5 interrupts through AIEC
+  .word  TIM1_BRK_IRQHandler               // TIM1 Break interrupt
+  .word  TIM1_UP_IRQHandler                 // TIM1 Update Interrupt
+  .word  TIM1_TRG_COM_IRQHandler           // TIM1 Trigger and Commutation Interrupt
+  .word  TIM1_CC_IRQHandler                // TIM1 Capture Compare                                   
+  .word  TIM2_IRQHandler                   // TIM2                                            
+  .word  TIM3_IRQHandler                   // TIM3                                            
+  .word  TIM4_IRQHandler                   // TIM4                                            
+  .word  I2C1_EV_IRQHandler                // I2C1 Event                                             
+  .word  I2C1_ER_IRQHandler                // I2C1 Error                                             
+  .word  I2C2_EV_IRQHandler                // I2C2 Event                                             
+  .word  I2C2_ER_IRQHandler                // I2C2 Error                                               
+  .word  SPI1_IRQHandler                   // SPI1                                            
+  .word  SPI2_IRQHandler                   // SPI2                                            
+  .word  USART1_IRQHandler                 // USART1                                          
+  .word  USART2_IRQHandler                 // USART2                                          
+  .word  USART3_IRQHandler                 // USART3                                          
+  .word  EXTI10_IRQHandler                 // External Line10 interrupts through AIEC
+  .word  RTC_TIMESTAMP_IRQHandler          // RTC TimeStamp through EXTI Line
+  .word  EXTI11_IRQHandler                 // External Line11 interrupts through AIEC
+  .word  TIM8_BRK_IRQHandler               // TIM8 Break Interrupt
+  .word  TIM8_UP_IRQHandler                // TIM8 Update Interrupt
+  .word  TIM8_TRG_COM_IRQHandler           // TIM8 Trigger and Commutation Interrupt
+  .word  TIM8_CC_IRQHandler                // TIM8 Capture Compare Interrupt
+  .word  DMA1_Stream7_IRQHandler           // DMA1 Stream7                                           
+  .word  FMC_IRQHandler                    // FMC                             
+  .word  SDMMC1_IRQHandler                 // SDMMC1
+  .word  TIM5_IRQHandler                   // TIM5                            
+  .word  SPI3_IRQHandler                   // SPI3                            
+  .word  UART4_IRQHandler                  // UART4                           
+  .word  UART5_IRQHandler                  // UART5                           
+  .word  TIM6_IRQHandler                   // TIM6
+  .word  TIM7_IRQHandler                   // TIM7           
+  .word  DMA2_Stream0_IRQHandler           // DMA2 Stream 0                   
+  .word  DMA2_Stream1_IRQHandler           // DMA2 Stream 1                   
+  .word  DMA2_Stream2_IRQHandler           // DMA2 Stream 2                   
+  .word  DMA2_Stream3_IRQHandler           // DMA2 Stream 3                   
+  .word  DMA2_Stream4_IRQHandler           // DMA2 Stream 4                   
+  .word  ETH1_IRQHandler                    // Ethernet                        
+  .word  ETH1_WKUP_IRQHandler               // Ethernet Wakeup through EXTI line              
+  .word  0                                 // Reserved
+  .word  EXTI6_IRQHandler                  // EXTI Line6 interrupts through AIEC
+  .word  EXTI7_IRQHandler                  // EXTI Line7 interrupts through AIEC
+  .word  EXTI8_IRQHandler                  // EXTI Line8 interrupts through AIEC
+  .word  EXTI9_IRQHandler                  // EXTI Line9 interrupts through AIEC
+  .word  DMA2_Stream5_IRQHandler           // DMA2 Stream 5                   
+  .word  DMA2_Stream6_IRQHandler           // DMA2 Stream 6                   
+  .word  DMA2_Stream7_IRQHandler           // DMA2 Stream 7                   
+  .word  USART6_IRQHandler                 // USART6                           
+  .word  I2C3_EV_IRQHandler                // I2C3 event                             
+  .word  I2C3_ER_IRQHandler                // I2C3 error                             
+  .word  USBH_OHCI_IRQHandler              // USB Host OHCI
+  .word  USBH_EHCI_IRQHandler              // USB Host EHCI
+  .word  EXTI12_IRQHandler                 // EXTI Line12 interrupts through AIEC
+  .word  EXTI13_IRQHandler                 // EXTI Line13 interrupts through AIEC
+  .word  DCMI_IRQHandler                   // DCMI                            
+  .word  0                                 // Reserved
+  .word  HASH1_IRQHandler                  // Crypto Hash1 interrupt
+  .word  FPU_IRQHandler                    // FPU
+  .word  UART7_IRQHandler                  // UART7
+  .word  UART8_IRQHandler                  // UART8
+  .word  SPI4_IRQHandler                   // SPI4
+  .word  SPI5_IRQHandler                   // SPI5
+  .word  SPI6_IRQHandler                   // SPI6
+  .word  SAI1_IRQHandler                   // SAI1
+  .word  LTDC_IRQHandler                   // LTDC
+  .word  LTDC_ER_IRQHandler                // LTDC error
+  .word  ADC2_IRQHandler                   // ADC2 
+  .word  SAI2_IRQHandler                   // SAI2
+  .word  QUADSPI_IRQHandler                // QUADSPI
+  .word  LPTIM1_IRQHandler                 // LPTIM1 global interrupt
+  .word  CEC_IRQHandler                    // HDMI_CEC
+  .word  I2C4_EV_IRQHandler                // I2C4 Event                             
+  .word  I2C4_ER_IRQHandler                // I2C4 Error 
+  .word  SPDIF_RX_IRQHandler               // SPDIF_RX
+  .word  OTG_IRQHandler                    // USB On The Go HS global interrupt
+  .word  RESERVED99_IRQHandler             // Reserved
+  .word  IPCC_RX0_IRQHandler               // Mailbox RX0 Free interrupt
+  .word  IPCC_TX0_IRQHandler               // Mailbox TX0 Free interrupt
+  .word  DMAMUX1_OVR_IRQHandler            // DMAMUX1 Overrun interrupt
+  .word  IPCC_RX1_IRQHandler               // Mailbox RX1 Free interrupt
+  .word  IPCC_TX1_IRQHandler               // Mailbox TX1 Free interrupt
+  .word  0                                 // Reserved
+  .word  HASH2_IRQHandler                  // Crypto Hash2 interrupt
+  .word  I2C5_EV_IRQHandler                // I2C5 Event Interrupt
+  .word  I2C5_ER_IRQHandler                // I2C5 Error Interrupt
+  .word  0                                 // Reserved
+  .word  DFSDM1_FLT0_IRQHandler            // DFSDM Filter0 Interrupt
+  .word  DFSDM1_FLT1_IRQHandler            // DFSDM Filter1 Interrupt
+  .word  DFSDM1_FLT2_IRQHandler            // DFSDM Filter2 Interrupt
+  .word  DFSDM1_FLT3_IRQHandler            // DFSDM Filter3 Interrupt
+  .word  SAI3_IRQHandler                   // SAI3 global Interrupt
+  .word  DFSDM1_FLT4_IRQHandler            // DFSDM Filter4 Interrupt
+  .word  TIM15_IRQHandler                  // TIM15 global Interrupt
+  .word  TIM16_IRQHandler                  // TIM16 global Interrupt
+  .word  TIM17_IRQHandler                  // TIM17 global Interrupt
+  .word  TIM12_IRQHandler                  // TIM12 global Interrupt
+  .word  MDIOS_IRQHandler                  // MDIOS global Interrupt
+  .word  EXTI14_IRQHandler                 // EXTI Line14 interrupts through AIEC
+  .word  MDMA_IRQHandler                   // MDMA global Interrupt
+  .word  0                                 // Reserved
+  .word  SDMMC2_IRQHandler                 // SDMMC2 global Interrupt
+  .word  HSEM_IT2_IRQHandler               // HSEM global Interrupt
+  .word  DFSDM1_FLT5_IRQHandler            // DFSDM Filter5 Interrupt
+  .word  EXTI15_IRQHandler                 // EXTI Line15 interrupts through AIEC
+  .word  nCTIIRQ1_IRQHandler               // Cortex-M4 CTI interrupt 1
+  .word  nCTIIRQ2_IRQHandler               // Cortex-M4 CTI interrupt 2
+  .word  TIM13_IRQHandler                  // TIM13 global interrupt
+  .word  TIM14_IRQHandler                  // TIM14 global interrupt
+  .word  DAC_IRQHandler                    // DAC1 and DAC2 underrun error interrupts
+  .word  RNG1_IRQHandler                   // RNG1 interrupt
+  .word  RNG2_IRQHandler                   // RNG2 interrupt
+  .word  I2C6_EV_IRQHandler                // I2C6 Event Interrupt
+  .word  I2C6_ER_IRQHandler                // I2C6 Error Interrupt
+  .word  SDMMC3_IRQHandler                 // SDMMC3 global Interrupt
+  .word  LPTIM2_IRQHandler                 // LPTIM2 global interrupt
+  .word  LPTIM3_IRQHandler                 // LPTIM3 global interrupt
+  .word  LPTIM4_IRQHandler                 // LPTIM4 global interrupt
+  .word  LPTIM5_IRQHandler                 // LPTIM5 global interrupt
+  .word  ETH1_LPI_IRQHandler               // ETH1_LPI interrupt 
+  .word  RESERVED143_IRQHandler            // Reserved
+  .word  MPU_SEV_IRQHandler                // MPU Send Event through AIEC
+  .word  RCC_WAKEUP_IRQHandler             // RCC Wake up interrupt
+  .word  SAI4_IRQHandler                   // SAI4 global interrupt
+  .word  DTS_IRQHandler                    // Temperature sensor interrupt
+  .word  RESERVED148_IRQHandler            // Reserved
+  .word  WAKEUP_PIN_IRQHandler             // Interrupt for all 6 wake-up pins
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak      BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak      UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak      DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak      RESERVED4_IRQHandler
+  .thumb_set RESERVED4_IRQHandler,Default_Handler
+
+  .weak      RESERVED99_IRQHandler
+  .thumb_set RESERVED99_IRQHandler,Default_Handler
+
+  .weak      ETH1_LPI_IRQHandler
+  .thumb_set ETH1_LPI_IRQHandler,Default_Handler
+
+  .weak      RESERVED143_IRQHandler
+  .thumb_set RESERVED143_IRQHandler,Default_Handler
+
+  .weak      WWDG1_IRQHandler
+  .thumb_set WWDG1_IRQHandler,Default_Handler
+
+  .weak      PVD_AVD_IRQHandler                      
+  .thumb_set PVD_AVD_IRQHandler,Default_Handler
+                           
+  .weak      TAMP_IRQHandler
+  .thumb_set TAMP_IRQHandler,Default_Handler
+     
+  .weak      RTC_WKUP_ALARM_IRQHandler
+  .thumb_set RTC_WKUP_ALARM_IRQHandler,Default_Handler
+                                                        
+  .weak      RCC_IRQHandler                      
+  .thumb_set RCC_IRQHandler,Default_Handler
+                                            
+  .weak      EXTI0_IRQHandler                    
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI1_IRQHandler                    
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+                                             
+  .weak      EXTI2_IRQHandler                    
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI3_IRQHandler                    
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI4_IRQHandler                    
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+                                                                               
+  .weak      DMA1_Stream0_IRQHandler
+  .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+  .weak      DMA1_Stream1_IRQHandler             
+  .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                          
+  .weak      DMA1_Stream2_IRQHandler             
+  .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                       
+  .weak      DMA1_Stream3_IRQHandler             
+  .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+                      
+  .weak      DMA1_Stream4_IRQHandler             
+  .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                          
+  .weak      DMA1_Stream5_IRQHandler             
+  .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                            
+  .weak      DMA1_Stream6_IRQHandler             
+  .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+  
+  .weak      ADC1_IRQHandler                      
+  .thumb_set ADC1_IRQHandler,Default_Handler
+  
+  .weak      ADC2_IRQHandler                      
+  .thumb_set ADC2_IRQHandler,Default_Handler
+                                                                                      
+  .weak      EXTI5_IRQHandler
+  .thumb_set EXTI5_IRQHandler,Default_Handler
+                                      
+  .weak      TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+                    
+  .weak      TIM1_UP_IRQHandler
+  .thumb_set TIM1_UP_IRQHandler,Default_Handler
+                  
+  .weak      TIM1_TRG_COM_IRQHandler
+  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+   
+  .weak      TIM1_CC_IRQHandler                  
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                                     
+  .weak      TIM2_IRQHandler                     
+  .thumb_set TIM2_IRQHandler,Default_Handler
+                                              
+  .weak      TIM3_IRQHandler                     
+  .thumb_set TIM3_IRQHandler,Default_Handler
+                                              
+  .weak      TIM4_IRQHandler                     
+  .thumb_set TIM4_IRQHandler,Default_Handler
+                                              
+  .weak      I2C1_EV_IRQHandler                  
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                                               
+  .weak      I2C1_ER_IRQHandler                  
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                                               
+  .weak      I2C2_EV_IRQHandler                  
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                                              
+  .weak      I2C2_ER_IRQHandler                  
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak      SPI1_IRQHandler                     
+  .thumb_set SPI1_IRQHandler,Default_Handler
+                                             
+  .weak      SPI2_IRQHandler                     
+  .thumb_set SPI2_IRQHandler,Default_Handler
+                                              
+  .weak      USART1_IRQHandler                   
+  .thumb_set USART1_IRQHandler,Default_Handler
+                                            
+  .weak      USART2_IRQHandler                   
+  .thumb_set USART2_IRQHandler,Default_Handler
+                                            
+  .weak      USART3_IRQHandler                   
+  .thumb_set USART3_IRQHandler,Default_Handler
+                                           
+  .weak      EXTI10_IRQHandler
+  .thumb_set EXTI10_IRQHandler,Default_Handler
+                                    
+  .weak      RTC_TIMESTAMP_IRQHandler
+  .thumb_set RTC_TIMESTAMP_IRQHandler,Default_Handler
+                    
+  .weak      EXTI11_IRQHandler
+  .thumb_set EXTI11_IRQHandler,Default_Handler
+
+  .weak      TIM8_BRK_IRQHandler
+  .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+                   
+  .weak      TIM8_UP_IRQHandler
+  .thumb_set TIM8_UP_IRQHandler,Default_Handler
+                   
+  .weak      TIM8_TRG_COM_IRQHandler
+  .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+   
+  .weak      TIM8_CC_IRQHandler                  
+  .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                                     
+  .weak      DMA1_Stream7_IRQHandler             
+  .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                                            
+  .weak      FMC_IRQHandler                      
+  .thumb_set FMC_IRQHandler,Default_Handler
+                                               
+  .weak      SDMMC1_IRQHandler
+  .thumb_set SDMMC1_IRQHandler,Default_Handler
+                                               
+  .weak      TIM5_IRQHandler                     
+  .thumb_set TIM5_IRQHandler,Default_Handler
+                                               
+  .weak      SPI3_IRQHandler                     
+  .thumb_set SPI3_IRQHandler,Default_Handler
+                                               
+  .weak      UART4_IRQHandler                    
+  .thumb_set UART4_IRQHandler,Default_Handler
+                                              
+  .weak      UART5_IRQHandler                    
+  .thumb_set UART5_IRQHandler,Default_Handler
+                                              
+  .weak      TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+                     
+  .weak      TIM7_IRQHandler                     
+  .thumb_set TIM7_IRQHandler,Default_Handler
+                      
+  .weak      DMA2_Stream0_IRQHandler             
+  .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+                                    
+  .weak      DMA2_Stream1_IRQHandler             
+  .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream2_IRQHandler             
+  .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+                                      
+  .weak      DMA2_Stream3_IRQHandler             
+  .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+                                      
+  .weak      DMA2_Stream4_IRQHandler             
+  .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+                                   
+  .weak      ETH1_IRQHandler                      
+  .thumb_set ETH1_IRQHandler,Default_Handler
+                                           
+  .weak      ETH1_WKUP_IRQHandler                 
+  .thumb_set ETH1_WKUP_IRQHandler,Default_Handler
+  
+  .weak      ETH1_LPI_IRQHandler                 
+  .thumb_set ETH1_LPI_IRQHandler,Default_Handler 
+                       
+  .weak      EXTI6_IRQHandler
+  .thumb_set EXTI6_IRQHandler,Default_Handler
+                                         
+  .weak      EXTI7_IRQHandler
+  .thumb_set EXTI7_IRQHandler,Default_Handler
+
+  .weak      EXTI8_IRQHandler
+  .thumb_set EXTI8_IRQHandler,Default_Handler
+
+  .weak      EXTI9_IRQHandler
+  .thumb_set EXTI9_IRQHandler,Default_Handler
+
+  .weak      DMA2_Stream5_IRQHandler             
+  .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream6_IRQHandler             
+  .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream7_IRQHandler             
+  .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                                     
+  .weak      USART6_IRQHandler                   
+  .thumb_set USART6_IRQHandler,Default_Handler
+                                             
+  .weak      I2C3_EV_IRQHandler                  
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                                                
+  .weak      I2C3_ER_IRQHandler                  
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                                                
+  .weak      USBH_OHCI_IRQHandler
+  .thumb_set USBH_OHCI_IRQHandler,Default_Handler
+                        
+  .weak      USBH_EHCI_IRQHandler
+  .thumb_set USBH_EHCI_IRQHandler,Default_Handler
+                        
+  .weak      EXTI12_IRQHandler
+  .thumb_set EXTI12_IRQHandler,Default_Handler
+
+  .weak      EXTI13_IRQHandler
+  .thumb_set EXTI13_IRQHandler,Default_Handler
+                                        
+  .weak      DCMI_IRQHandler                     
+  .thumb_set DCMI_IRQHandler,Default_Handler
+
+  .weak      HASH1_IRQHandler
+  .thumb_set HASH1_IRQHandler,Default_Handler
+
+  .weak      FPU_IRQHandler                      
+  .thumb_set FPU_IRQHandler,Default_Handler
+  
+  .weak      UART7_IRQHandler                    
+  .thumb_set UART7_IRQHandler,Default_Handler
+  
+  .weak      UART8_IRQHandler                    
+  .thumb_set UART8_IRQHandler,Default_Handler
+  
+  .weak      SPI4_IRQHandler                     
+  .thumb_set SPI4_IRQHandler,Default_Handler
+  
+  .weak      SPI5_IRQHandler                     
+  .thumb_set SPI5_IRQHandler,Default_Handler
+  
+  .weak      SPI6_IRQHandler                     
+  .thumb_set SPI6_IRQHandler,Default_Handler
+  
+  .weak      SAI1_IRQHandler                     
+  .thumb_set SAI1_IRQHandler,Default_Handler
+  
+  .weak      LTDC_IRQHandler                     
+  .thumb_set LTDC_IRQHandler,Default_Handler
+  
+  .weak      LTDC_ER_IRQHandler                  
+  .thumb_set LTDC_ER_IRQHandler,Default_Handler
+  
+  .weak      SAI2_IRQHandler                     
+  .thumb_set SAI2_IRQHandler,Default_Handler
+     
+  .weak      QUADSPI_IRQHandler                  
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+  
+  .weak      LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+  
+  .weak      CEC_IRQHandler                      
+  .thumb_set CEC_IRQHandler,Default_Handler
+     
+  .weak      I2C4_EV_IRQHandler                  
+  .thumb_set I2C4_EV_IRQHandler,Default_Handler
+  
+  .weak      I2C4_ER_IRQHandler                  
+  .thumb_set I2C4_ER_IRQHandler,Default_Handler
+   
+  .weak      SPDIF_RX_IRQHandler                 
+  .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+  .weak      OTG_IRQHandler
+  .thumb_set OTG_IRQHandler,Default_Handler
+  
+  .weak      IPCC_RX0_IRQHandler
+  .thumb_set IPCC_RX0_IRQHandler,Default_Handler
+
+  .weak      IPCC_TX0_IRQHandler
+  .thumb_set IPCC_TX0_IRQHandler,Default_Handler
+
+  .weak      DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+  .weak      IPCC_RX1_IRQHandler
+  .thumb_set IPCC_RX1_IRQHandler,Default_Handler
+  
+  .weak      IPCC_TX1_IRQHandler
+  .thumb_set IPCC_TX1_IRQHandler,Default_Handler
+
+  .weak      HASH2_IRQHandler
+  .thumb_set HASH2_IRQHandler,Default_Handler
+
+  .weak      I2C5_EV_IRQHandler
+  .thumb_set I2C5_EV_IRQHandler,Default_Handler
+
+  .weak      I2C5_ER_IRQHandler
+  .thumb_set I2C5_ER_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT0_IRQHandler
+  .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT1_IRQHandler
+  .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT2_IRQHandler
+  .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT3_IRQHandler
+  .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+                                               
+  .weak      SAI3_IRQHandler                        
+  .thumb_set SAI3_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT4_IRQHandler
+  .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+                                               
+  .weak      TIM15_IRQHandler                       
+  .thumb_set TIM15_IRQHandler,Default_Handler
+                                               
+  .weak      TIM16_IRQHandler                       
+  .thumb_set TIM16_IRQHandler,Default_Handler
+                                                
+  .weak      TIM17_IRQHandler                       
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak      TIM12_IRQHandler                       
+  .thumb_set TIM12_IRQHandler,Default_Handler
+  
+  .weak      MDIOS_IRQHandler                       
+  .thumb_set MDIOS_IRQHandler,Default_Handler
+                                                
+  .weak      EXTI14_IRQHandler
+  .thumb_set EXTI14_IRQHandler,Default_Handler
+                                                 
+  .weak      MDMA_IRQHandler                        
+  .thumb_set MDMA_IRQHandler,Default_Handler
+                                                
+  .weak      SDMMC2_IRQHandler                      
+  .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+  .weak      HSEM_IT2_IRQHandler
+  .thumb_set HSEM_IT2_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT5_IRQHandler
+  .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+                                                 
+  .weak      EXTI15_IRQHandler
+  .thumb_set EXTI15_IRQHandler,Default_Handler
+
+  .weak      nCTIIRQ1_IRQHandler
+  .thumb_set nCTIIRQ1_IRQHandler,Default_Handler
+
+  .weak      nCTIIRQ2_IRQHandler
+  .thumb_set nCTIIRQ2_IRQHandler,Default_Handler
+
+  .weak      TIM13_IRQHandler
+  .thumb_set TIM13_IRQHandler,Default_Handler
+
+  .weak      TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak      DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak      RNG1_IRQHandler
+  .thumb_set RNG1_IRQHandler,Default_Handler
+
+  .weak      RNG2_IRQHandler
+  .thumb_set RNG2_IRQHandler,Default_Handler
+
+  .weak      I2C6_EV_IRQHandler
+  .thumb_set I2C6_EV_IRQHandler,Default_Handler
+
+  .weak      I2C6_ER_IRQHandler
+  .thumb_set I2C6_ER_IRQHandler,Default_Handler
+
+  .weak      SDMMC3_IRQHandler
+  .thumb_set SDMMC3_IRQHandler,Default_Handler
+                                                
+  .weak      LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+                                             
+  .weak      LPTIM3_IRQHandler
+  .thumb_set LPTIM3_IRQHandler,Default_Handler
+                                        
+  .weak      LPTIM4_IRQHandler
+  .thumb_set LPTIM4_IRQHandler,Default_Handler
+                                              
+  .weak      LPTIM5_IRQHandler
+  .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+  .weak      MPU_SEV_IRQHandler
+  .thumb_set MPU_SEV_IRQHandler,Default_Handler
+
+  .weak      RCC_WAKEUP_IRQHandler
+  .thumb_set RCC_WAKEUP_IRQHandler,Default_Handler
+
+  .weak      SAI4_IRQHandler
+  .thumb_set SAI4_IRQHandler,Default_Handler
+
+  .weak      DTS_IRQHandler
+  .thumb_set DTS_IRQHandler,Default_Handler
+
+  .weak      RESERVED148_IRQHandler
+  .thumb_set RESERVED148_IRQHandler,Default_Handler
+ 
+  .weak      WAKEUP_PIN_IRQHandler
+  .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp151c_cm4.s

@@ -0,0 +1,765 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32mp151c_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32MP15xx Devices vector table for GCC based toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+  .section .startup_copro_fw.Reset_Handler,"ax"
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack      /* set stack pointer */
+
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      _sidata: End of code section, i.e., begin of data sections to copy from.
+ *      _sdata/_edata: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+  
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+  
+/* Call the clock system intitialization function.*/
+
+  bl  SystemInit
+ // ldr r0, =SystemInit
+ // blx r0
+/* Call static constructors */
+ bl __libc_init_array
+ // ldr r0, =__libc_init_array
+ // blx r0
+/* Call the application's entry point.*/
+  bl entry
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack                           // Top of Stack
+  .word  Reset_Handler                     // Reset Handler
+  .word  NMI_Handler                       // NMI Handler
+  .word  HardFault_Handler                 // Hard Fault Handler
+  .word  MemManage_Handler                 // MPU Fault Handler
+  .word  BusFault_Handler                  // Bus Fault Handler
+  .word  UsageFault_Handler                // Usage Fault Handler
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  SVC_Handler                       // SVCall Handler
+  .word  DebugMon_Handler                  // Debug Monitor Handler
+  .word  0                                 // Reserved
+  .word  PendSV_Handler                    // PendSV Handler
+  .word  SysTick_Handler                   // SysTick Handler
+
+                // External Interrupts
+  .word  WWDG1_IRQHandler                  // Window WatchDog 1
+  .word  PVD_AVD_IRQHandler                // PVD and AVD through EXTI Line detection                        
+  .word  TAMP_IRQHandler                   // Tamper and TimeStamps through the EXTI line
+  .word  RTC_WKUP_ALARM_IRQHandler         // RTC Wakeup and Alarm through the EXTI line
+  .word  RESERVED4_IRQHandler              // Reserved
+  .word  RCC_IRQHandler                    // RCC                                             
+  .word  EXTI0_IRQHandler                  // EXTI Line0                                             
+  .word  EXTI1_IRQHandler                  // EXTI Line1                                             
+  .word  EXTI2_IRQHandler                  // EXTI Line2                                             
+  .word  EXTI3_IRQHandler                  // EXTI Line3                                             
+  .word  EXTI4_IRQHandler                  // EXTI Line4 
+  .word  DMA1_Stream0_IRQHandler           // DMA1 Stream 0
+  .word  DMA1_Stream1_IRQHandler           // DMA1 Stream 1                                   
+  .word  DMA1_Stream2_IRQHandler           // DMA1 Stream 2                                   
+  .word  DMA1_Stream3_IRQHandler           // DMA1 Stream 3                                   
+  .word  DMA1_Stream4_IRQHandler           // DMA1 Stream 4                                   
+  .word  DMA1_Stream5_IRQHandler           // DMA1 Stream 5
+  .word  DMA1_Stream6_IRQHandler           // DMA1 Stream 6 
+  .word  ADC1_IRQHandler                   // ADC1                             
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  EXTI5_IRQHandler                  // External Line5 interrupts through AIEC
+  .word  TIM1_BRK_IRQHandler               // TIM1 Break interrupt
+  .word  TIM1_UP_IRQHandler                 // TIM1 Update Interrupt
+  .word  TIM1_TRG_COM_IRQHandler           // TIM1 Trigger and Commutation Interrupt
+  .word  TIM1_CC_IRQHandler                // TIM1 Capture Compare                                   
+  .word  TIM2_IRQHandler                   // TIM2                                            
+  .word  TIM3_IRQHandler                   // TIM3                                            
+  .word  TIM4_IRQHandler                   // TIM4                                            
+  .word  I2C1_EV_IRQHandler                // I2C1 Event                                             
+  .word  I2C1_ER_IRQHandler                // I2C1 Error                                             
+  .word  I2C2_EV_IRQHandler                // I2C2 Event                                             
+  .word  I2C2_ER_IRQHandler                // I2C2 Error                                               
+  .word  SPI1_IRQHandler                   // SPI1                                            
+  .word  SPI2_IRQHandler                   // SPI2                                            
+  .word  USART1_IRQHandler                 // USART1                                          
+  .word  USART2_IRQHandler                 // USART2                                          
+  .word  USART3_IRQHandler                 // USART3                                          
+  .word  EXTI10_IRQHandler                 // External Line10 interrupts through AIEC
+  .word  RTC_TIMESTAMP_IRQHandler          // RTC TimeStamp through EXTI Line
+  .word  EXTI11_IRQHandler                 // External Line11 interrupts through AIEC
+  .word  TIM8_BRK_IRQHandler               // TIM8 Break Interrupt
+  .word  TIM8_UP_IRQHandler                // TIM8 Update Interrupt
+  .word  TIM8_TRG_COM_IRQHandler           // TIM8 Trigger and Commutation Interrupt
+  .word  TIM8_CC_IRQHandler                // TIM8 Capture Compare Interrupt
+  .word  DMA1_Stream7_IRQHandler           // DMA1 Stream7                                           
+  .word  FMC_IRQHandler                    // FMC                             
+  .word  SDMMC1_IRQHandler                 // SDMMC1
+  .word  TIM5_IRQHandler                   // TIM5                            
+  .word  SPI3_IRQHandler                   // SPI3                            
+  .word  UART4_IRQHandler                  // UART4                           
+  .word  UART5_IRQHandler                  // UART5                           
+  .word  TIM6_IRQHandler                   // TIM6
+  .word  TIM7_IRQHandler                   // TIM7           
+  .word  DMA2_Stream0_IRQHandler           // DMA2 Stream 0                   
+  .word  DMA2_Stream1_IRQHandler           // DMA2 Stream 1                   
+  .word  DMA2_Stream2_IRQHandler           // DMA2 Stream 2                   
+  .word  DMA2_Stream3_IRQHandler           // DMA2 Stream 3                   
+  .word  DMA2_Stream4_IRQHandler           // DMA2 Stream 4                   
+  .word  ETH1_IRQHandler                    // Ethernet                        
+  .word  ETH1_WKUP_IRQHandler               // Ethernet Wakeup through EXTI line              
+  .word  0                                 // Reserved
+  .word  EXTI6_IRQHandler                  // EXTI Line6 interrupts through AIEC
+  .word  EXTI7_IRQHandler                  // EXTI Line7 interrupts through AIEC
+  .word  EXTI8_IRQHandler                  // EXTI Line8 interrupts through AIEC
+  .word  EXTI9_IRQHandler                  // EXTI Line9 interrupts through AIEC
+  .word  DMA2_Stream5_IRQHandler           // DMA2 Stream 5                   
+  .word  DMA2_Stream6_IRQHandler           // DMA2 Stream 6                   
+  .word  DMA2_Stream7_IRQHandler           // DMA2 Stream 7                   
+  .word  USART6_IRQHandler                 // USART6                           
+  .word  I2C3_EV_IRQHandler                // I2C3 event                             
+  .word  I2C3_ER_IRQHandler                // I2C3 error                             
+  .word  USBH_OHCI_IRQHandler              // USB Host OHCI
+  .word  USBH_EHCI_IRQHandler              // USB Host EHCI
+  .word  EXTI12_IRQHandler                 // EXTI Line12 interrupts through AIEC
+  .word  EXTI13_IRQHandler                 // EXTI Line13 interrupts through AIEC
+  .word  DCMI_IRQHandler                   // DCMI                            
+  .word  CRYP1_IRQHandler                  // Crypto1 global interrupt
+  .word  HASH1_IRQHandler                  // Crypto Hash1 interrupt
+  .word  FPU_IRQHandler                    // FPU
+  .word  UART7_IRQHandler                  // UART7
+  .word  UART8_IRQHandler                  // UART8
+  .word  SPI4_IRQHandler                   // SPI4
+  .word  SPI5_IRQHandler                   // SPI5
+  .word  SPI6_IRQHandler                   // SPI6
+  .word  SAI1_IRQHandler                   // SAI1
+  .word  LTDC_IRQHandler                   // LTDC
+  .word  LTDC_ER_IRQHandler                // LTDC error
+  .word  ADC2_IRQHandler                   // ADC2 
+  .word  SAI2_IRQHandler                   // SAI2
+  .word  QUADSPI_IRQHandler                // QUADSPI
+  .word  LPTIM1_IRQHandler                 // LPTIM1 global interrupt
+  .word  CEC_IRQHandler                    // HDMI_CEC
+  .word  I2C4_EV_IRQHandler                // I2C4 Event                             
+  .word  I2C4_ER_IRQHandler                // I2C4 Error 
+  .word  SPDIF_RX_IRQHandler               // SPDIF_RX
+  .word  OTG_IRQHandler                    // USB On The Go HS global interrupt
+  .word  RESERVED99_IRQHandler             // Reserved
+  .word  IPCC_RX0_IRQHandler               // Mailbox RX0 Free interrupt
+  .word  IPCC_TX0_IRQHandler               // Mailbox TX0 Free interrupt
+  .word  DMAMUX1_OVR_IRQHandler            // DMAMUX1 Overrun interrupt
+  .word  IPCC_RX1_IRQHandler               // Mailbox RX1 Free interrupt
+  .word  IPCC_TX1_IRQHandler               // Mailbox TX1 Free interrupt
+  .word  CRYP2_IRQHandler                  // Crypto2 global interrupt
+  .word  HASH2_IRQHandler                  // Crypto Hash2 interrupt
+  .word  I2C5_EV_IRQHandler                // I2C5 Event Interrupt
+  .word  I2C5_ER_IRQHandler                // I2C5 Error Interrupt
+  .word  0                                 // Reserved
+  .word  DFSDM1_FLT0_IRQHandler            // DFSDM Filter0 Interrupt
+  .word  DFSDM1_FLT1_IRQHandler            // DFSDM Filter1 Interrupt
+  .word  DFSDM1_FLT2_IRQHandler            // DFSDM Filter2 Interrupt
+  .word  DFSDM1_FLT3_IRQHandler            // DFSDM Filter3 Interrupt
+  .word  SAI3_IRQHandler                   // SAI3 global Interrupt
+  .word  DFSDM1_FLT4_IRQHandler            // DFSDM Filter4 Interrupt
+  .word  TIM15_IRQHandler                  // TIM15 global Interrupt
+  .word  TIM16_IRQHandler                  // TIM16 global Interrupt
+  .word  TIM17_IRQHandler                  // TIM17 global Interrupt
+  .word  TIM12_IRQHandler                  // TIM12 global Interrupt
+  .word  MDIOS_IRQHandler                  // MDIOS global Interrupt
+  .word  EXTI14_IRQHandler                 // EXTI Line14 interrupts through AIEC
+  .word  MDMA_IRQHandler                   // MDMA global Interrupt
+  .word  0                                 // Reserved
+  .word  SDMMC2_IRQHandler                 // SDMMC2 global Interrupt
+  .word  HSEM_IT2_IRQHandler               // HSEM global Interrupt
+  .word  DFSDM1_FLT5_IRQHandler            // DFSDM Filter5 Interrupt
+  .word  EXTI15_IRQHandler                 // EXTI Line15 interrupts through AIEC
+  .word  nCTIIRQ1_IRQHandler               // Cortex-M4 CTI interrupt 1
+  .word  nCTIIRQ2_IRQHandler               // Cortex-M4 CTI interrupt 2
+  .word  TIM13_IRQHandler                  // TIM13 global interrupt
+  .word  TIM14_IRQHandler                  // TIM14 global interrupt
+  .word  DAC_IRQHandler                    // DAC1 and DAC2 underrun error interrupts
+  .word  RNG1_IRQHandler                   // RNG1 interrupt
+  .word  RNG2_IRQHandler                   // RNG2 interrupt
+  .word  I2C6_EV_IRQHandler                // I2C6 Event Interrupt
+  .word  I2C6_ER_IRQHandler                // I2C6 Error Interrupt
+  .word  SDMMC3_IRQHandler                 // SDMMC3 global Interrupt
+  .word  LPTIM2_IRQHandler                 // LPTIM2 global interrupt
+  .word  LPTIM3_IRQHandler                 // LPTIM3 global interrupt
+  .word  LPTIM4_IRQHandler                 // LPTIM4 global interrupt
+  .word  LPTIM5_IRQHandler                 // LPTIM5 global interrupt
+  .word  ETH1_LPI_IRQHandler               // ETH1_LPI interrupt 
+  .word  RESERVED143_IRQHandler            // Reserved
+  .word  MPU_SEV_IRQHandler                // MPU Send Event through AIEC
+  .word  RCC_WAKEUP_IRQHandler             // RCC Wake up interrupt
+  .word  SAI4_IRQHandler                   // SAI4 global interrupt
+  .word  DTS_IRQHandler                    // Temperature sensor interrupt
+  .word  RESERVED148_IRQHandler            // Reserved
+  .word  WAKEUP_PIN_IRQHandler             // Interrupt for all 6 wake-up pins
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak      BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak      UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak      DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak      RESERVED4_IRQHandler
+  .thumb_set RESERVED4_IRQHandler,Default_Handler
+
+  .weak      RESERVED99_IRQHandler
+  .thumb_set RESERVED99_IRQHandler,Default_Handler
+
+  .weak      ETH1_LPI_IRQHandler
+  .thumb_set ETH1_LPI_IRQHandler,Default_Handler
+
+  .weak      RESERVED143_IRQHandler
+  .thumb_set RESERVED143_IRQHandler,Default_Handler
+
+  .weak      WWDG1_IRQHandler
+  .thumb_set WWDG1_IRQHandler,Default_Handler
+
+  .weak      PVD_AVD_IRQHandler                      
+  .thumb_set PVD_AVD_IRQHandler,Default_Handler
+                           
+  .weak      TAMP_IRQHandler
+  .thumb_set TAMP_IRQHandler,Default_Handler
+     
+  .weak      RTC_WKUP_ALARM_IRQHandler
+  .thumb_set RTC_WKUP_ALARM_IRQHandler,Default_Handler
+                                                        
+  .weak      RCC_IRQHandler                      
+  .thumb_set RCC_IRQHandler,Default_Handler
+                                            
+  .weak      EXTI0_IRQHandler                    
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI1_IRQHandler                    
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+                                             
+  .weak      EXTI2_IRQHandler                    
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI3_IRQHandler                    
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI4_IRQHandler                    
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+                                                                               
+  .weak      DMA1_Stream0_IRQHandler
+  .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+  .weak      DMA1_Stream1_IRQHandler             
+  .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                          
+  .weak      DMA1_Stream2_IRQHandler             
+  .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                       
+  .weak      DMA1_Stream3_IRQHandler             
+  .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+                      
+  .weak      DMA1_Stream4_IRQHandler             
+  .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                          
+  .weak      DMA1_Stream5_IRQHandler             
+  .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                            
+  .weak      DMA1_Stream6_IRQHandler             
+  .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+  
+  .weak      ADC1_IRQHandler                      
+  .thumb_set ADC1_IRQHandler,Default_Handler
+  
+  .weak      ADC2_IRQHandler                      
+  .thumb_set ADC2_IRQHandler,Default_Handler
+                            
+  .weak      EXTI5_IRQHandler
+  .thumb_set EXTI5_IRQHandler,Default_Handler
+                                      
+  .weak      TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+                    
+  .weak      TIM1_UP_IRQHandler
+  .thumb_set TIM1_UP_IRQHandler,Default_Handler
+                  
+  .weak      TIM1_TRG_COM_IRQHandler
+  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+   
+  .weak      TIM1_CC_IRQHandler                  
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                                     
+  .weak      TIM2_IRQHandler                     
+  .thumb_set TIM2_IRQHandler,Default_Handler
+                                              
+  .weak      TIM3_IRQHandler                     
+  .thumb_set TIM3_IRQHandler,Default_Handler
+                                              
+  .weak      TIM4_IRQHandler                     
+  .thumb_set TIM4_IRQHandler,Default_Handler
+                                              
+  .weak      I2C1_EV_IRQHandler                  
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                                               
+  .weak      I2C1_ER_IRQHandler                  
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                                               
+  .weak      I2C2_EV_IRQHandler                  
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                                              
+  .weak      I2C2_ER_IRQHandler                  
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak      SPI1_IRQHandler                     
+  .thumb_set SPI1_IRQHandler,Default_Handler
+                                             
+  .weak      SPI2_IRQHandler                     
+  .thumb_set SPI2_IRQHandler,Default_Handler
+                                              
+  .weak      USART1_IRQHandler                   
+  .thumb_set USART1_IRQHandler,Default_Handler
+                                            
+  .weak      USART2_IRQHandler                   
+  .thumb_set USART2_IRQHandler,Default_Handler
+                                            
+  .weak      USART3_IRQHandler                   
+  .thumb_set USART3_IRQHandler,Default_Handler
+                                           
+  .weak      EXTI10_IRQHandler
+  .thumb_set EXTI10_IRQHandler,Default_Handler
+                                    
+  .weak      RTC_TIMESTAMP_IRQHandler
+  .thumb_set RTC_TIMESTAMP_IRQHandler,Default_Handler
+                    
+  .weak      EXTI11_IRQHandler
+  .thumb_set EXTI11_IRQHandler,Default_Handler
+
+  .weak      TIM8_BRK_IRQHandler
+  .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+                   
+  .weak      TIM8_UP_IRQHandler
+  .thumb_set TIM8_UP_IRQHandler,Default_Handler
+                   
+  .weak      TIM8_TRG_COM_IRQHandler
+  .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+   
+  .weak      TIM8_CC_IRQHandler                  
+  .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                                     
+  .weak      DMA1_Stream7_IRQHandler             
+  .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                                            
+  .weak      FMC_IRQHandler                      
+  .thumb_set FMC_IRQHandler,Default_Handler
+                                               
+  .weak      SDMMC1_IRQHandler
+  .thumb_set SDMMC1_IRQHandler,Default_Handler
+                                               
+  .weak      TIM5_IRQHandler                     
+  .thumb_set TIM5_IRQHandler,Default_Handler
+                                               
+  .weak      SPI3_IRQHandler                     
+  .thumb_set SPI3_IRQHandler,Default_Handler
+                                               
+  .weak      UART4_IRQHandler                    
+  .thumb_set UART4_IRQHandler,Default_Handler
+                                              
+  .weak      UART5_IRQHandler                    
+  .thumb_set UART5_IRQHandler,Default_Handler
+                                              
+  .weak      TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+                     
+  .weak      TIM7_IRQHandler                     
+  .thumb_set TIM7_IRQHandler,Default_Handler
+                      
+  .weak      DMA2_Stream0_IRQHandler             
+  .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+                                    
+  .weak      DMA2_Stream1_IRQHandler             
+  .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream2_IRQHandler             
+  .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+                                      
+  .weak      DMA2_Stream3_IRQHandler             
+  .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+                                      
+  .weak      DMA2_Stream4_IRQHandler             
+  .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+                                   
+  .weak      ETH1_IRQHandler                      
+  .thumb_set ETH1_IRQHandler,Default_Handler
+                                           
+  .weak      ETH1_WKUP_IRQHandler                 
+  .thumb_set ETH1_WKUP_IRQHandler,Default_Handler
+  
+  .weak      ETH1_LPI_IRQHandler                 
+  .thumb_set ETH1_LPI_IRQHandler,Default_Handler 
+                       
+  .weak      EXTI6_IRQHandler
+  .thumb_set EXTI6_IRQHandler,Default_Handler
+                                         
+  .weak      EXTI7_IRQHandler
+  .thumb_set EXTI7_IRQHandler,Default_Handler
+
+  .weak      EXTI8_IRQHandler
+  .thumb_set EXTI8_IRQHandler,Default_Handler
+
+  .weak      EXTI9_IRQHandler
+  .thumb_set EXTI9_IRQHandler,Default_Handler
+
+  .weak      DMA2_Stream5_IRQHandler             
+  .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream6_IRQHandler             
+  .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream7_IRQHandler             
+  .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                                     
+  .weak      USART6_IRQHandler                   
+  .thumb_set USART6_IRQHandler,Default_Handler
+                                             
+  .weak      I2C3_EV_IRQHandler                  
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                                                
+  .weak      I2C3_ER_IRQHandler                  
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                                                
+  .weak      USBH_OHCI_IRQHandler
+  .thumb_set USBH_OHCI_IRQHandler,Default_Handler
+                        
+  .weak      USBH_EHCI_IRQHandler
+  .thumb_set USBH_EHCI_IRQHandler,Default_Handler
+                        
+  .weak      EXTI12_IRQHandler
+  .thumb_set EXTI12_IRQHandler,Default_Handler
+
+  .weak      EXTI13_IRQHandler
+  .thumb_set EXTI13_IRQHandler,Default_Handler
+                                        
+  .weak      DCMI_IRQHandler                     
+  .thumb_set DCMI_IRQHandler,Default_Handler
+                                               
+  .weak      CRYP1_IRQHandler
+  .thumb_set CRYP1_IRQHandler,Default_Handler
+
+  .weak      HASH1_IRQHandler
+  .thumb_set HASH1_IRQHandler,Default_Handler
+
+  .weak      FPU_IRQHandler                      
+  .thumb_set FPU_IRQHandler,Default_Handler
+  
+  .weak      UART7_IRQHandler                    
+  .thumb_set UART7_IRQHandler,Default_Handler
+  
+  .weak      UART8_IRQHandler                    
+  .thumb_set UART8_IRQHandler,Default_Handler
+  
+  .weak      SPI4_IRQHandler                     
+  .thumb_set SPI4_IRQHandler,Default_Handler
+  
+  .weak      SPI5_IRQHandler                     
+  .thumb_set SPI5_IRQHandler,Default_Handler
+  
+  .weak      SPI6_IRQHandler                     
+  .thumb_set SPI6_IRQHandler,Default_Handler
+  
+  .weak      SAI1_IRQHandler                     
+  .thumb_set SAI1_IRQHandler,Default_Handler
+  
+  .weak      LTDC_IRQHandler                     
+  .thumb_set LTDC_IRQHandler,Default_Handler
+  
+  .weak      LTDC_ER_IRQHandler                  
+  .thumb_set LTDC_ER_IRQHandler,Default_Handler
+  
+  .weak      SAI2_IRQHandler                     
+  .thumb_set SAI2_IRQHandler,Default_Handler
+     
+  .weak      QUADSPI_IRQHandler                  
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+  
+  .weak      LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+  
+  .weak      CEC_IRQHandler                      
+  .thumb_set CEC_IRQHandler,Default_Handler
+     
+  .weak      I2C4_EV_IRQHandler                  
+  .thumb_set I2C4_EV_IRQHandler,Default_Handler
+  
+  .weak      I2C4_ER_IRQHandler                  
+  .thumb_set I2C4_ER_IRQHandler,Default_Handler
+   
+  .weak      SPDIF_RX_IRQHandler                 
+  .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+  .weak      OTG_IRQHandler
+  .thumb_set OTG_IRQHandler,Default_Handler
+  
+  .weak      IPCC_RX0_IRQHandler
+  .thumb_set IPCC_RX0_IRQHandler,Default_Handler
+
+  .weak      IPCC_TX0_IRQHandler
+  .thumb_set IPCC_TX0_IRQHandler,Default_Handler
+
+  .weak      DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+  .weak      IPCC_RX1_IRQHandler
+  .thumb_set IPCC_RX1_IRQHandler,Default_Handler
+  
+  .weak      IPCC_TX1_IRQHandler
+  .thumb_set IPCC_TX1_IRQHandler,Default_Handler
+
+  .weak      CRYP2_IRQHandler
+  .thumb_set CRYP2_IRQHandler,Default_Handler
+
+  .weak      HASH2_IRQHandler
+  .thumb_set HASH2_IRQHandler,Default_Handler
+
+  .weak      I2C5_EV_IRQHandler
+  .thumb_set I2C5_EV_IRQHandler,Default_Handler
+
+  .weak      I2C5_ER_IRQHandler
+  .thumb_set I2C5_ER_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT0_IRQHandler
+  .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT1_IRQHandler
+  .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT2_IRQHandler
+  .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT3_IRQHandler
+  .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+                                               
+  .weak      SAI3_IRQHandler                        
+  .thumb_set SAI3_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT4_IRQHandler
+  .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+                                               
+  .weak      TIM15_IRQHandler                       
+  .thumb_set TIM15_IRQHandler,Default_Handler
+                                               
+  .weak      TIM16_IRQHandler                       
+  .thumb_set TIM16_IRQHandler,Default_Handler
+                                                
+  .weak      TIM17_IRQHandler                       
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak      TIM12_IRQHandler                       
+  .thumb_set TIM12_IRQHandler,Default_Handler
+  
+  .weak      MDIOS_IRQHandler                       
+  .thumb_set MDIOS_IRQHandler,Default_Handler
+                                                
+  .weak      EXTI14_IRQHandler
+  .thumb_set EXTI14_IRQHandler,Default_Handler
+                                                 
+  .weak      MDMA_IRQHandler                        
+  .thumb_set MDMA_IRQHandler,Default_Handler
+                                                
+  .weak      SDMMC2_IRQHandler                      
+  .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+  .weak      HSEM_IT2_IRQHandler
+  .thumb_set HSEM_IT2_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT5_IRQHandler
+  .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+                                                 
+  .weak      EXTI15_IRQHandler
+  .thumb_set EXTI15_IRQHandler,Default_Handler
+
+  .weak      nCTIIRQ1_IRQHandler
+  .thumb_set nCTIIRQ1_IRQHandler,Default_Handler
+
+  .weak      nCTIIRQ2_IRQHandler
+  .thumb_set nCTIIRQ2_IRQHandler,Default_Handler
+
+  .weak      TIM13_IRQHandler
+  .thumb_set TIM13_IRQHandler,Default_Handler
+
+  .weak      TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak      DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak      RNG1_IRQHandler
+  .thumb_set RNG1_IRQHandler,Default_Handler
+
+  .weak      RNG2_IRQHandler
+  .thumb_set RNG2_IRQHandler,Default_Handler
+
+  .weak      I2C6_EV_IRQHandler
+  .thumb_set I2C6_EV_IRQHandler,Default_Handler
+
+  .weak      I2C6_ER_IRQHandler
+  .thumb_set I2C6_ER_IRQHandler,Default_Handler
+
+  .weak      SDMMC3_IRQHandler
+  .thumb_set SDMMC3_IRQHandler,Default_Handler
+                                                
+  .weak      LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+                                             
+  .weak      LPTIM3_IRQHandler
+  .thumb_set LPTIM3_IRQHandler,Default_Handler
+                                        
+  .weak      LPTIM4_IRQHandler
+  .thumb_set LPTIM4_IRQHandler,Default_Handler
+                                              
+  .weak      LPTIM5_IRQHandler
+  .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+  .weak      MPU_SEV_IRQHandler
+  .thumb_set MPU_SEV_IRQHandler,Default_Handler
+
+  .weak      RCC_WAKEUP_IRQHandler
+  .thumb_set RCC_WAKEUP_IRQHandler,Default_Handler
+
+  .weak      SAI4_IRQHandler
+  .thumb_set SAI4_IRQHandler,Default_Handler
+
+  .weak      DTS_IRQHandler
+  .thumb_set DTS_IRQHandler,Default_Handler
+
+  .weak      RESERVED148_IRQHandler
+  .thumb_set RESERVED148_IRQHandler,Default_Handler
+ 
+  .weak      WAKEUP_PIN_IRQHandler
+  .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153a_cm4.s

@@ -0,0 +1,774 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32mp153a_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32MP15xx Devices vector table for GCC based toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+  .section .startup_copro_fw.Reset_Handler,"ax"
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack      /* set stack pointer */
+
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      _sidata: End of code section, i.e., begin of data sections to copy from.
+ *      _sdata/_edata: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+  
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+  
+/* Call the clock system intitialization function.*/
+
+  bl  SystemInit
+ // ldr r0, =SystemInit
+ // blx r0
+/* Call static constructors */
+ bl __libc_init_array
+ // ldr r0, =__libc_init_array
+ // blx r0
+/* Call the application's entry point.*/
+  bl entry
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack                           // Top of Stack
+  .word  Reset_Handler                     // Reset Handler
+  .word  NMI_Handler                       // NMI Handler
+  .word  HardFault_Handler                 // Hard Fault Handler
+  .word  MemManage_Handler                 // MPU Fault Handler
+  .word  BusFault_Handler                  // Bus Fault Handler
+  .word  UsageFault_Handler                // Usage Fault Handler
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  SVC_Handler                       // SVCall Handler
+  .word  DebugMon_Handler                  // Debug Monitor Handler
+  .word  0                                 // Reserved
+  .word  PendSV_Handler                    // PendSV Handler
+  .word  SysTick_Handler                   // SysTick Handler
+
+                // External Interrupts
+  .word  WWDG1_IRQHandler                  // Window WatchDog 1
+  .word  PVD_AVD_IRQHandler                // PVD and AVD through EXTI Line detection                        
+  .word  TAMP_IRQHandler                   // Tamper and TimeStamps through the EXTI line
+  .word  RTC_WKUP_ALARM_IRQHandler         // RTC Wakeup and Alarm through the EXTI line
+  .word  RESERVED4_IRQHandler              // Reserved
+  .word  RCC_IRQHandler                    // RCC                                             
+  .word  EXTI0_IRQHandler                  // EXTI Line0                                             
+  .word  EXTI1_IRQHandler                  // EXTI Line1                                             
+  .word  EXTI2_IRQHandler                  // EXTI Line2                                             
+  .word  EXTI3_IRQHandler                  // EXTI Line3                                             
+  .word  EXTI4_IRQHandler                  // EXTI Line4 
+  .word  DMA1_Stream0_IRQHandler           // DMA1 Stream 0
+  .word  DMA1_Stream1_IRQHandler           // DMA1 Stream 1                                   
+  .word  DMA1_Stream2_IRQHandler           // DMA1 Stream 2                                   
+  .word  DMA1_Stream3_IRQHandler           // DMA1 Stream 3                                   
+  .word  DMA1_Stream4_IRQHandler           // DMA1 Stream 4                                   
+  .word  DMA1_Stream5_IRQHandler           // DMA1 Stream 5
+  .word  DMA1_Stream6_IRQHandler           // DMA1 Stream 6 
+  .word  ADC1_IRQHandler                   // ADC1                             
+  .word  FDCAN1_IT0_IRQHandler        // FDCAN1 Interrupt line 0
+  .word  FDCAN2_IT0_IRQHandler        // FDCAN2 Interrupt line 0
+  .word  FDCAN1_IT1_IRQHandler        // FDCAN1 Interrupt line 1
+  .word  FDCAN2_IT1_IRQHandler        // FDCAN2 Interrupt line 1
+  .word  EXTI5_IRQHandler                  // External Line5 interrupts through AIEC
+  .word  TIM1_BRK_IRQHandler               // TIM1 Break interrupt
+  .word  TIM1_UP_IRQHandler                 // TIM1 Update Interrupt
+  .word  TIM1_TRG_COM_IRQHandler           // TIM1 Trigger and Commutation Interrupt
+  .word  TIM1_CC_IRQHandler                // TIM1 Capture Compare                                   
+  .word  TIM2_IRQHandler                   // TIM2                                            
+  .word  TIM3_IRQHandler                   // TIM3                                            
+  .word  TIM4_IRQHandler                   // TIM4                                            
+  .word  I2C1_EV_IRQHandler                // I2C1 Event                                             
+  .word  I2C1_ER_IRQHandler                // I2C1 Error                                             
+  .word  I2C2_EV_IRQHandler                // I2C2 Event                                             
+  .word  I2C2_ER_IRQHandler                // I2C2 Error                                               
+  .word  SPI1_IRQHandler                   // SPI1                                            
+  .word  SPI2_IRQHandler                   // SPI2                                            
+  .word  USART1_IRQHandler                 // USART1                                          
+  .word  USART2_IRQHandler                 // USART2                                          
+  .word  USART3_IRQHandler                 // USART3                                          
+  .word  EXTI10_IRQHandler                 // External Line10 interrupts through AIEC
+  .word  RTC_TIMESTAMP_IRQHandler          // RTC TimeStamp through EXTI Line
+  .word  EXTI11_IRQHandler                 // External Line11 interrupts through AIEC
+  .word  TIM8_BRK_IRQHandler               // TIM8 Break Interrupt
+  .word  TIM8_UP_IRQHandler                // TIM8 Update Interrupt
+  .word  TIM8_TRG_COM_IRQHandler           // TIM8 Trigger and Commutation Interrupt
+  .word  TIM8_CC_IRQHandler                // TIM8 Capture Compare Interrupt
+  .word  DMA1_Stream7_IRQHandler           // DMA1 Stream7                                           
+  .word  FMC_IRQHandler                    // FMC                             
+  .word  SDMMC1_IRQHandler                 // SDMMC1
+  .word  TIM5_IRQHandler                   // TIM5                            
+  .word  SPI3_IRQHandler                   // SPI3                            
+  .word  UART4_IRQHandler                  // UART4                           
+  .word  UART5_IRQHandler                  // UART5                           
+  .word  TIM6_IRQHandler                   // TIM6
+  .word  TIM7_IRQHandler                   // TIM7           
+  .word  DMA2_Stream0_IRQHandler           // DMA2 Stream 0                   
+  .word  DMA2_Stream1_IRQHandler           // DMA2 Stream 1                   
+  .word  DMA2_Stream2_IRQHandler           // DMA2 Stream 2                   
+  .word  DMA2_Stream3_IRQHandler           // DMA2 Stream 3                   
+  .word  DMA2_Stream4_IRQHandler           // DMA2 Stream 4                   
+  .word  ETH1_IRQHandler                    // Ethernet                        
+  .word  ETH1_WKUP_IRQHandler               // Ethernet Wakeup through EXTI line              
+  .word  FDCAN_CAL_IRQHandler               // FDCAN Calibration
+  .word  EXTI6_IRQHandler                  // EXTI Line6 interrupts through AIEC
+  .word  EXTI7_IRQHandler                  // EXTI Line7 interrupts through AIEC
+  .word  EXTI8_IRQHandler                  // EXTI Line8 interrupts through AIEC
+  .word  EXTI9_IRQHandler                  // EXTI Line9 interrupts through AIEC
+  .word  DMA2_Stream5_IRQHandler           // DMA2 Stream 5                   
+  .word  DMA2_Stream6_IRQHandler           // DMA2 Stream 6                   
+  .word  DMA2_Stream7_IRQHandler           // DMA2 Stream 7                   
+  .word  USART6_IRQHandler                 // USART6                           
+  .word  I2C3_EV_IRQHandler                // I2C3 event                             
+  .word  I2C3_ER_IRQHandler                // I2C3 error                             
+  .word  USBH_OHCI_IRQHandler              // USB Host OHCI
+  .word  USBH_EHCI_IRQHandler              // USB Host EHCI
+  .word  EXTI12_IRQHandler                 // EXTI Line12 interrupts through AIEC
+  .word  EXTI13_IRQHandler                 // EXTI Line13 interrupts through AIEC
+  .word  DCMI_IRQHandler                   // DCMI                            
+  .word  0                                 // Reserved
+  .word  HASH1_IRQHandler                  // Crypto Hash1 interrupt
+  .word  FPU_IRQHandler                    // FPU
+  .word  UART7_IRQHandler                  // UART7
+  .word  UART8_IRQHandler                  // UART8
+  .word  SPI4_IRQHandler                   // SPI4
+  .word  SPI5_IRQHandler                   // SPI5
+  .word  SPI6_IRQHandler                   // SPI6
+  .word  SAI1_IRQHandler                   // SAI1
+  .word  LTDC_IRQHandler                   // LTDC
+  .word  LTDC_ER_IRQHandler                // LTDC error
+  .word  ADC2_IRQHandler                   // ADC2 
+  .word  SAI2_IRQHandler                   // SAI2
+  .word  QUADSPI_IRQHandler                // QUADSPI
+  .word  LPTIM1_IRQHandler                 // LPTIM1 global interrupt
+  .word  CEC_IRQHandler                    // HDMI_CEC
+  .word  I2C4_EV_IRQHandler                // I2C4 Event                             
+  .word  I2C4_ER_IRQHandler                // I2C4 Error 
+  .word  SPDIF_RX_IRQHandler               // SPDIF_RX
+  .word  OTG_IRQHandler                    // USB On The Go HS global interrupt
+  .word  RESERVED99_IRQHandler             // Reserved
+  .word  IPCC_RX0_IRQHandler               // Mailbox RX0 Free interrupt
+  .word  IPCC_TX0_IRQHandler               // Mailbox TX0 Free interrupt
+  .word  DMAMUX1_OVR_IRQHandler            // DMAMUX1 Overrun interrupt
+  .word  IPCC_RX1_IRQHandler               // Mailbox RX1 Free interrupt
+  .word  IPCC_TX1_IRQHandler               // Mailbox TX1 Free interrupt
+  .word  0                                 // Reserved
+  .word  HASH2_IRQHandler                  // Crypto Hash2 interrupt
+  .word  I2C5_EV_IRQHandler                // I2C5 Event Interrupt
+  .word  I2C5_ER_IRQHandler                // I2C5 Error Interrupt
+  .word  0                                 // Reserved
+  .word  DFSDM1_FLT0_IRQHandler            // DFSDM Filter0 Interrupt
+  .word  DFSDM1_FLT1_IRQHandler            // DFSDM Filter1 Interrupt
+  .word  DFSDM1_FLT2_IRQHandler            // DFSDM Filter2 Interrupt
+  .word  DFSDM1_FLT3_IRQHandler            // DFSDM Filter3 Interrupt
+  .word  SAI3_IRQHandler                   // SAI3 global Interrupt
+  .word  DFSDM1_FLT4_IRQHandler            // DFSDM Filter4 Interrupt
+  .word  TIM15_IRQHandler                  // TIM15 global Interrupt
+  .word  TIM16_IRQHandler                  // TIM16 global Interrupt
+  .word  TIM17_IRQHandler                  // TIM17 global Interrupt
+  .word  TIM12_IRQHandler                  // TIM12 global Interrupt
+  .word  MDIOS_IRQHandler                  // MDIOS global Interrupt
+  .word  EXTI14_IRQHandler                 // EXTI Line14 interrupts through AIEC
+  .word  MDMA_IRQHandler                   // MDMA global Interrupt
+  .word  0                                 // Reserved
+  .word  SDMMC2_IRQHandler                 // SDMMC2 global Interrupt
+  .word  HSEM_IT2_IRQHandler               // HSEM global Interrupt
+  .word  DFSDM1_FLT5_IRQHandler            // DFSDM Filter5 Interrupt
+  .word  EXTI15_IRQHandler                 // EXTI Line15 interrupts through AIEC
+  .word  nCTIIRQ1_IRQHandler               // Cortex-M4 CTI interrupt 1
+  .word  nCTIIRQ2_IRQHandler               // Cortex-M4 CTI interrupt 2
+  .word  TIM13_IRQHandler                  // TIM13 global interrupt
+  .word  TIM14_IRQHandler                  // TIM14 global interrupt
+  .word  DAC_IRQHandler                    // DAC1 and DAC2 underrun error interrupts
+  .word  RNG1_IRQHandler                   // RNG1 interrupt
+  .word  RNG2_IRQHandler                   // RNG2 interrupt
+  .word  I2C6_EV_IRQHandler                // I2C6 Event Interrupt
+  .word  I2C6_ER_IRQHandler                // I2C6 Error Interrupt
+  .word  SDMMC3_IRQHandler                 // SDMMC3 global Interrupt
+  .word  LPTIM2_IRQHandler                 // LPTIM2 global interrupt
+  .word  LPTIM3_IRQHandler                 // LPTIM3 global interrupt
+  .word  LPTIM4_IRQHandler                 // LPTIM4 global interrupt
+  .word  LPTIM5_IRQHandler                 // LPTIM5 global interrupt
+  .word  ETH1_LPI_IRQHandler               // ETH1_LPI interrupt 
+  .word  RESERVED143_IRQHandler            // Reserved
+  .word  MPU_SEV_IRQHandler                // MPU Send Event through AIEC
+  .word  RCC_WAKEUP_IRQHandler             // RCC Wake up interrupt
+  .word  SAI4_IRQHandler                   // SAI4 global interrupt
+  .word  DTS_IRQHandler                    // Temperature sensor interrupt
+  .word  RESERVED148_IRQHandler            // Reserved
+  .word  WAKEUP_PIN_IRQHandler             // Interrupt for all 6 wake-up pins
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak      BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak      UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak      DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak      RESERVED4_IRQHandler
+  .thumb_set RESERVED4_IRQHandler,Default_Handler
+
+  .weak      RESERVED99_IRQHandler
+  .thumb_set RESERVED99_IRQHandler,Default_Handler
+
+  .weak      ETH1_LPI_IRQHandler
+  .thumb_set ETH1_LPI_IRQHandler,Default_Handler
+
+  .weak      RESERVED143_IRQHandler
+  .thumb_set RESERVED143_IRQHandler,Default_Handler
+
+  .weak      WWDG1_IRQHandler
+  .thumb_set WWDG1_IRQHandler,Default_Handler
+
+  .weak      PVD_AVD_IRQHandler                      
+  .thumb_set PVD_AVD_IRQHandler,Default_Handler
+                           
+  .weak      TAMP_IRQHandler
+  .thumb_set TAMP_IRQHandler,Default_Handler
+     
+  .weak      RTC_WKUP_ALARM_IRQHandler
+  .thumb_set RTC_WKUP_ALARM_IRQHandler,Default_Handler
+                                                        
+  .weak      RCC_IRQHandler                      
+  .thumb_set RCC_IRQHandler,Default_Handler
+                                            
+  .weak      EXTI0_IRQHandler                    
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI1_IRQHandler                    
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+                                             
+  .weak      EXTI2_IRQHandler                    
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI3_IRQHandler                    
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI4_IRQHandler                    
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+                                                                               
+  .weak      DMA1_Stream0_IRQHandler
+  .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+  .weak      DMA1_Stream1_IRQHandler             
+  .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                          
+  .weak      DMA1_Stream2_IRQHandler             
+  .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                       
+  .weak      DMA1_Stream3_IRQHandler             
+  .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+                      
+  .weak      DMA1_Stream4_IRQHandler             
+  .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                          
+  .weak      DMA1_Stream5_IRQHandler             
+  .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                            
+  .weak      DMA1_Stream6_IRQHandler             
+  .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+  
+  .weak      ADC1_IRQHandler                      
+  .thumb_set ADC1_IRQHandler,Default_Handler
+  
+  .weak      ADC2_IRQHandler                      
+  .thumb_set ADC2_IRQHandler,Default_Handler
+                            
+  .weak      FDCAN1_IT0_IRQHandler
+  .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+  .weak      FDCAN2_IT0_IRQHandler
+  .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+  .weak      FDCAN1_IT1_IRQHandler
+  .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+                                              
+  .weak      FDCAN2_IT1_IRQHandler
+  .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+  .weak      FDCAN_CAL_IRQHandler
+  .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+                                                                                      
+  .weak      EXTI5_IRQHandler
+  .thumb_set EXTI5_IRQHandler,Default_Handler
+                                      
+  .weak      TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+                    
+  .weak      TIM1_UP_IRQHandler
+  .thumb_set TIM1_UP_IRQHandler,Default_Handler
+                  
+  .weak      TIM1_TRG_COM_IRQHandler
+  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+   
+  .weak      TIM1_CC_IRQHandler                  
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                                     
+  .weak      TIM2_IRQHandler                     
+  .thumb_set TIM2_IRQHandler,Default_Handler
+                                              
+  .weak      TIM3_IRQHandler                     
+  .thumb_set TIM3_IRQHandler,Default_Handler
+                                              
+  .weak      TIM4_IRQHandler                     
+  .thumb_set TIM4_IRQHandler,Default_Handler
+                                              
+  .weak      I2C1_EV_IRQHandler                  
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                                               
+  .weak      I2C1_ER_IRQHandler                  
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                                               
+  .weak      I2C2_EV_IRQHandler                  
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                                              
+  .weak      I2C2_ER_IRQHandler                  
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak      SPI1_IRQHandler                     
+  .thumb_set SPI1_IRQHandler,Default_Handler
+                                             
+  .weak      SPI2_IRQHandler                     
+  .thumb_set SPI2_IRQHandler,Default_Handler
+                                              
+  .weak      USART1_IRQHandler                   
+  .thumb_set USART1_IRQHandler,Default_Handler
+                                            
+  .weak      USART2_IRQHandler                   
+  .thumb_set USART2_IRQHandler,Default_Handler
+                                            
+  .weak      USART3_IRQHandler                   
+  .thumb_set USART3_IRQHandler,Default_Handler
+                                           
+  .weak      EXTI10_IRQHandler
+  .thumb_set EXTI10_IRQHandler,Default_Handler
+                                    
+  .weak      RTC_TIMESTAMP_IRQHandler
+  .thumb_set RTC_TIMESTAMP_IRQHandler,Default_Handler
+                    
+  .weak      EXTI11_IRQHandler
+  .thumb_set EXTI11_IRQHandler,Default_Handler
+
+  .weak      TIM8_BRK_IRQHandler
+  .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+                   
+  .weak      TIM8_UP_IRQHandler
+  .thumb_set TIM8_UP_IRQHandler,Default_Handler
+                   
+  .weak      TIM8_TRG_COM_IRQHandler
+  .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+   
+  .weak      TIM8_CC_IRQHandler                  
+  .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                                     
+  .weak      DMA1_Stream7_IRQHandler             
+  .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                                            
+  .weak      FMC_IRQHandler                      
+  .thumb_set FMC_IRQHandler,Default_Handler
+                                               
+  .weak      SDMMC1_IRQHandler
+  .thumb_set SDMMC1_IRQHandler,Default_Handler
+                                               
+  .weak      TIM5_IRQHandler                     
+  .thumb_set TIM5_IRQHandler,Default_Handler
+                                               
+  .weak      SPI3_IRQHandler                     
+  .thumb_set SPI3_IRQHandler,Default_Handler
+                                               
+  .weak      UART4_IRQHandler                    
+  .thumb_set UART4_IRQHandler,Default_Handler
+                                              
+  .weak      UART5_IRQHandler                    
+  .thumb_set UART5_IRQHandler,Default_Handler
+                                              
+  .weak      TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+                     
+  .weak      TIM7_IRQHandler                     
+  .thumb_set TIM7_IRQHandler,Default_Handler
+                      
+  .weak      DMA2_Stream0_IRQHandler             
+  .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+                                    
+  .weak      DMA2_Stream1_IRQHandler             
+  .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream2_IRQHandler             
+  .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+                                      
+  .weak      DMA2_Stream3_IRQHandler             
+  .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+                                      
+  .weak      DMA2_Stream4_IRQHandler             
+  .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+                                   
+  .weak      ETH1_IRQHandler                      
+  .thumb_set ETH1_IRQHandler,Default_Handler
+                                           
+  .weak      ETH1_WKUP_IRQHandler                 
+  .thumb_set ETH1_WKUP_IRQHandler,Default_Handler
+  
+  .weak      ETH1_LPI_IRQHandler                 
+  .thumb_set ETH1_LPI_IRQHandler,Default_Handler 
+                       
+  .weak      EXTI6_IRQHandler
+  .thumb_set EXTI6_IRQHandler,Default_Handler
+                                         
+  .weak      EXTI7_IRQHandler
+  .thumb_set EXTI7_IRQHandler,Default_Handler
+
+  .weak      EXTI8_IRQHandler
+  .thumb_set EXTI8_IRQHandler,Default_Handler
+
+  .weak      EXTI9_IRQHandler
+  .thumb_set EXTI9_IRQHandler,Default_Handler
+
+  .weak      DMA2_Stream5_IRQHandler             
+  .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream6_IRQHandler             
+  .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream7_IRQHandler             
+  .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                                     
+  .weak      USART6_IRQHandler                   
+  .thumb_set USART6_IRQHandler,Default_Handler
+                                             
+  .weak      I2C3_EV_IRQHandler                  
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                                                
+  .weak      I2C3_ER_IRQHandler                  
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                                                
+  .weak      USBH_OHCI_IRQHandler
+  .thumb_set USBH_OHCI_IRQHandler,Default_Handler
+                        
+  .weak      USBH_EHCI_IRQHandler
+  .thumb_set USBH_EHCI_IRQHandler,Default_Handler
+                        
+  .weak      EXTI12_IRQHandler
+  .thumb_set EXTI12_IRQHandler,Default_Handler
+
+  .weak      EXTI13_IRQHandler
+  .thumb_set EXTI13_IRQHandler,Default_Handler
+                                        
+  .weak      DCMI_IRQHandler                     
+  .thumb_set DCMI_IRQHandler,Default_Handler
+
+  .weak      HASH1_IRQHandler
+  .thumb_set HASH1_IRQHandler,Default_Handler
+
+  .weak      FPU_IRQHandler                      
+  .thumb_set FPU_IRQHandler,Default_Handler
+  
+  .weak      UART7_IRQHandler                    
+  .thumb_set UART7_IRQHandler,Default_Handler
+  
+  .weak      UART8_IRQHandler                    
+  .thumb_set UART8_IRQHandler,Default_Handler
+  
+  .weak      SPI4_IRQHandler                     
+  .thumb_set SPI4_IRQHandler,Default_Handler
+  
+  .weak      SPI5_IRQHandler                     
+  .thumb_set SPI5_IRQHandler,Default_Handler
+  
+  .weak      SPI6_IRQHandler                     
+  .thumb_set SPI6_IRQHandler,Default_Handler
+  
+  .weak      SAI1_IRQHandler                     
+  .thumb_set SAI1_IRQHandler,Default_Handler
+  
+  .weak      LTDC_IRQHandler                     
+  .thumb_set LTDC_IRQHandler,Default_Handler
+  
+  .weak      LTDC_ER_IRQHandler                  
+  .thumb_set LTDC_ER_IRQHandler,Default_Handler
+  
+  .weak      SAI2_IRQHandler                     
+  .thumb_set SAI2_IRQHandler,Default_Handler
+     
+  .weak      QUADSPI_IRQHandler                  
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+  
+  .weak      LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+  
+  .weak      CEC_IRQHandler                      
+  .thumb_set CEC_IRQHandler,Default_Handler
+     
+  .weak      I2C4_EV_IRQHandler                  
+  .thumb_set I2C4_EV_IRQHandler,Default_Handler
+  
+  .weak      I2C4_ER_IRQHandler                  
+  .thumb_set I2C4_ER_IRQHandler,Default_Handler
+   
+  .weak      SPDIF_RX_IRQHandler                 
+  .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+  .weak      OTG_IRQHandler
+  .thumb_set OTG_IRQHandler,Default_Handler
+  
+  .weak      IPCC_RX0_IRQHandler
+  .thumb_set IPCC_RX0_IRQHandler,Default_Handler
+
+  .weak      IPCC_TX0_IRQHandler
+  .thumb_set IPCC_TX0_IRQHandler,Default_Handler
+
+  .weak      DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+  .weak      IPCC_RX1_IRQHandler
+  .thumb_set IPCC_RX1_IRQHandler,Default_Handler
+  
+  .weak      IPCC_TX1_IRQHandler
+  .thumb_set IPCC_TX1_IRQHandler,Default_Handler
+
+  .weak      HASH2_IRQHandler
+  .thumb_set HASH2_IRQHandler,Default_Handler
+
+  .weak      I2C5_EV_IRQHandler
+  .thumb_set I2C5_EV_IRQHandler,Default_Handler
+
+  .weak      I2C5_ER_IRQHandler
+  .thumb_set I2C5_ER_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT0_IRQHandler
+  .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT1_IRQHandler
+  .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT2_IRQHandler
+  .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT3_IRQHandler
+  .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+                                               
+  .weak      SAI3_IRQHandler                        
+  .thumb_set SAI3_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT4_IRQHandler
+  .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+                                               
+  .weak      TIM15_IRQHandler                       
+  .thumb_set TIM15_IRQHandler,Default_Handler
+                                               
+  .weak      TIM16_IRQHandler                       
+  .thumb_set TIM16_IRQHandler,Default_Handler
+                                                
+  .weak      TIM17_IRQHandler                       
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak      TIM12_IRQHandler                       
+  .thumb_set TIM12_IRQHandler,Default_Handler
+  
+  .weak      MDIOS_IRQHandler                       
+  .thumb_set MDIOS_IRQHandler,Default_Handler
+                                                
+  .weak      EXTI14_IRQHandler
+  .thumb_set EXTI14_IRQHandler,Default_Handler
+                                                 
+  .weak      MDMA_IRQHandler                        
+  .thumb_set MDMA_IRQHandler,Default_Handler
+                                                
+  .weak      SDMMC2_IRQHandler                      
+  .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+  .weak      HSEM_IT2_IRQHandler
+  .thumb_set HSEM_IT2_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT5_IRQHandler
+  .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+                                                 
+  .weak      EXTI15_IRQHandler
+  .thumb_set EXTI15_IRQHandler,Default_Handler
+
+  .weak      nCTIIRQ1_IRQHandler
+  .thumb_set nCTIIRQ1_IRQHandler,Default_Handler
+
+  .weak      nCTIIRQ2_IRQHandler
+  .thumb_set nCTIIRQ2_IRQHandler,Default_Handler
+
+  .weak      TIM13_IRQHandler
+  .thumb_set TIM13_IRQHandler,Default_Handler
+
+  .weak      TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak      DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak      RNG1_IRQHandler
+  .thumb_set RNG1_IRQHandler,Default_Handler
+
+  .weak      RNG2_IRQHandler
+  .thumb_set RNG2_IRQHandler,Default_Handler
+
+  .weak      I2C6_EV_IRQHandler
+  .thumb_set I2C6_EV_IRQHandler,Default_Handler
+
+  .weak      I2C6_ER_IRQHandler
+  .thumb_set I2C6_ER_IRQHandler,Default_Handler
+
+  .weak      SDMMC3_IRQHandler
+  .thumb_set SDMMC3_IRQHandler,Default_Handler
+                                                
+  .weak      LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+                                             
+  .weak      LPTIM3_IRQHandler
+  .thumb_set LPTIM3_IRQHandler,Default_Handler
+                                        
+  .weak      LPTIM4_IRQHandler
+  .thumb_set LPTIM4_IRQHandler,Default_Handler
+                                              
+  .weak      LPTIM5_IRQHandler
+  .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+  .weak      MPU_SEV_IRQHandler
+  .thumb_set MPU_SEV_IRQHandler,Default_Handler
+
+  .weak      RCC_WAKEUP_IRQHandler
+  .thumb_set RCC_WAKEUP_IRQHandler,Default_Handler
+
+  .weak      SAI4_IRQHandler
+  .thumb_set SAI4_IRQHandler,Default_Handler
+
+  .weak      DTS_IRQHandler
+  .thumb_set DTS_IRQHandler,Default_Handler
+
+  .weak      RESERVED148_IRQHandler
+  .thumb_set RESERVED148_IRQHandler,Default_Handler
+ 
+  .weak      WAKEUP_PIN_IRQHandler
+  .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp153c_cm4.s

@@ -0,0 +1,780 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32mp153c_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32MP15xx Devices vector table for GCC based toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+  .section .startup_copro_fw.Reset_Handler,"ax"
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack      /* set stack pointer */
+
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      _sidata: End of code section, i.e., begin of data sections to copy from.
+ *      _sdata/_edata: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+  
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+  
+/* Call the clock system intitialization function.*/
+
+  bl  SystemInit
+ // ldr r0, =SystemInit
+ // blx r0
+/* Call static constructors */
+ bl __libc_init_array
+ // ldr r0, =__libc_init_array
+ // blx r0
+/* Call the application's entry point.*/
+  bl entry
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack                           // Top of Stack
+  .word  Reset_Handler                     // Reset Handler
+  .word  NMI_Handler                       // NMI Handler
+  .word  HardFault_Handler                 // Hard Fault Handler
+  .word  MemManage_Handler                 // MPU Fault Handler
+  .word  BusFault_Handler                  // Bus Fault Handler
+  .word  UsageFault_Handler                // Usage Fault Handler
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  SVC_Handler                       // SVCall Handler
+  .word  DebugMon_Handler                  // Debug Monitor Handler
+  .word  0                                 // Reserved
+  .word  PendSV_Handler                    // PendSV Handler
+  .word  SysTick_Handler                   // SysTick Handler
+
+                // External Interrupts
+  .word  WWDG1_IRQHandler                  // Window WatchDog 1
+  .word  PVD_AVD_IRQHandler                // PVD and AVD through EXTI Line detection                        
+  .word  TAMP_IRQHandler                   // Tamper and TimeStamps through the EXTI line
+  .word  RTC_WKUP_ALARM_IRQHandler         // RTC Wakeup and Alarm through the EXTI line
+  .word  RESERVED4_IRQHandler              // Reserved
+  .word  RCC_IRQHandler                    // RCC                                             
+  .word  EXTI0_IRQHandler                  // EXTI Line0                                             
+  .word  EXTI1_IRQHandler                  // EXTI Line1                                             
+  .word  EXTI2_IRQHandler                  // EXTI Line2                                             
+  .word  EXTI3_IRQHandler                  // EXTI Line3                                             
+  .word  EXTI4_IRQHandler                  // EXTI Line4 
+  .word  DMA1_Stream0_IRQHandler           // DMA1 Stream 0
+  .word  DMA1_Stream1_IRQHandler           // DMA1 Stream 1                                   
+  .word  DMA1_Stream2_IRQHandler           // DMA1 Stream 2                                   
+  .word  DMA1_Stream3_IRQHandler           // DMA1 Stream 3                                   
+  .word  DMA1_Stream4_IRQHandler           // DMA1 Stream 4                                   
+  .word  DMA1_Stream5_IRQHandler           // DMA1 Stream 5
+  .word  DMA1_Stream6_IRQHandler           // DMA1 Stream 6 
+  .word  ADC1_IRQHandler                   // ADC1                             
+  .word  FDCAN1_IT0_IRQHandler        // FDCAN1 Interrupt line 0
+  .word  FDCAN2_IT0_IRQHandler        // FDCAN2 Interrupt line 0
+  .word  FDCAN1_IT1_IRQHandler        // FDCAN1 Interrupt line 1
+  .word  FDCAN2_IT1_IRQHandler        // FDCAN2 Interrupt line 1
+  .word  EXTI5_IRQHandler                  // External Line5 interrupts through AIEC
+  .word  TIM1_BRK_IRQHandler               // TIM1 Break interrupt
+  .word  TIM1_UP_IRQHandler                 // TIM1 Update Interrupt
+  .word  TIM1_TRG_COM_IRQHandler           // TIM1 Trigger and Commutation Interrupt
+  .word  TIM1_CC_IRQHandler                // TIM1 Capture Compare                                   
+  .word  TIM2_IRQHandler                   // TIM2                                            
+  .word  TIM3_IRQHandler                   // TIM3                                            
+  .word  TIM4_IRQHandler                   // TIM4                                            
+  .word  I2C1_EV_IRQHandler                // I2C1 Event                                             
+  .word  I2C1_ER_IRQHandler                // I2C1 Error                                             
+  .word  I2C2_EV_IRQHandler                // I2C2 Event                                             
+  .word  I2C2_ER_IRQHandler                // I2C2 Error                                               
+  .word  SPI1_IRQHandler                   // SPI1                                            
+  .word  SPI2_IRQHandler                   // SPI2                                            
+  .word  USART1_IRQHandler                 // USART1                                          
+  .word  USART2_IRQHandler                 // USART2                                          
+  .word  USART3_IRQHandler                 // USART3                                          
+  .word  EXTI10_IRQHandler                 // External Line10 interrupts through AIEC
+  .word  RTC_TIMESTAMP_IRQHandler          // RTC TimeStamp through EXTI Line
+  .word  EXTI11_IRQHandler                 // External Line11 interrupts through AIEC
+  .word  TIM8_BRK_IRQHandler               // TIM8 Break Interrupt
+  .word  TIM8_UP_IRQHandler                // TIM8 Update Interrupt
+  .word  TIM8_TRG_COM_IRQHandler           // TIM8 Trigger and Commutation Interrupt
+  .word  TIM8_CC_IRQHandler                // TIM8 Capture Compare Interrupt
+  .word  DMA1_Stream7_IRQHandler           // DMA1 Stream7                                           
+  .word  FMC_IRQHandler                    // FMC                             
+  .word  SDMMC1_IRQHandler                 // SDMMC1
+  .word  TIM5_IRQHandler                   // TIM5                            
+  .word  SPI3_IRQHandler                   // SPI3                            
+  .word  UART4_IRQHandler                  // UART4                           
+  .word  UART5_IRQHandler                  // UART5                           
+  .word  TIM6_IRQHandler                   // TIM6
+  .word  TIM7_IRQHandler                   // TIM7           
+  .word  DMA2_Stream0_IRQHandler           // DMA2 Stream 0                   
+  .word  DMA2_Stream1_IRQHandler           // DMA2 Stream 1                   
+  .word  DMA2_Stream2_IRQHandler           // DMA2 Stream 2                   
+  .word  DMA2_Stream3_IRQHandler           // DMA2 Stream 3                   
+  .word  DMA2_Stream4_IRQHandler           // DMA2 Stream 4                   
+  .word  ETH1_IRQHandler                    // Ethernet                        
+  .word  ETH1_WKUP_IRQHandler               // Ethernet Wakeup through EXTI line              
+  .word  FDCAN_CAL_IRQHandler               // FDCAN Calibration
+  .word  EXTI6_IRQHandler                  // EXTI Line6 interrupts through AIEC
+  .word  EXTI7_IRQHandler                  // EXTI Line7 interrupts through AIEC
+  .word  EXTI8_IRQHandler                  // EXTI Line8 interrupts through AIEC
+  .word  EXTI9_IRQHandler                  // EXTI Line9 interrupts through AIEC
+  .word  DMA2_Stream5_IRQHandler           // DMA2 Stream 5                   
+  .word  DMA2_Stream6_IRQHandler           // DMA2 Stream 6                   
+  .word  DMA2_Stream7_IRQHandler           // DMA2 Stream 7                   
+  .word  USART6_IRQHandler                 // USART6                           
+  .word  I2C3_EV_IRQHandler                // I2C3 event                             
+  .word  I2C3_ER_IRQHandler                // I2C3 error                             
+  .word  USBH_OHCI_IRQHandler              // USB Host OHCI
+  .word  USBH_EHCI_IRQHandler              // USB Host EHCI
+  .word  EXTI12_IRQHandler                 // EXTI Line12 interrupts through AIEC
+  .word  EXTI13_IRQHandler                 // EXTI Line13 interrupts through AIEC
+  .word  DCMI_IRQHandler                   // DCMI                            
+  .word  CRYP1_IRQHandler                  // Crypto1 global interrupt
+  .word  HASH1_IRQHandler                  // Crypto Hash1 interrupt
+  .word  FPU_IRQHandler                    // FPU
+  .word  UART7_IRQHandler                  // UART7
+  .word  UART8_IRQHandler                  // UART8
+  .word  SPI4_IRQHandler                   // SPI4
+  .word  SPI5_IRQHandler                   // SPI5
+  .word  SPI6_IRQHandler                   // SPI6
+  .word  SAI1_IRQHandler                   // SAI1
+  .word  LTDC_IRQHandler                   // LTDC
+  .word  LTDC_ER_IRQHandler                // LTDC error
+  .word  ADC2_IRQHandler                   // ADC2 
+  .word  SAI2_IRQHandler                   // SAI2
+  .word  QUADSPI_IRQHandler                // QUADSPI
+  .word  LPTIM1_IRQHandler                 // LPTIM1 global interrupt
+  .word  CEC_IRQHandler                    // HDMI_CEC
+  .word  I2C4_EV_IRQHandler                // I2C4 Event                             
+  .word  I2C4_ER_IRQHandler                // I2C4 Error 
+  .word  SPDIF_RX_IRQHandler               // SPDIF_RX
+  .word  OTG_IRQHandler                    // USB On The Go HS global interrupt
+  .word  RESERVED99_IRQHandler             // Reserved
+  .word  IPCC_RX0_IRQHandler               // Mailbox RX0 Free interrupt
+  .word  IPCC_TX0_IRQHandler               // Mailbox TX0 Free interrupt
+  .word  DMAMUX1_OVR_IRQHandler            // DMAMUX1 Overrun interrupt
+  .word  IPCC_RX1_IRQHandler               // Mailbox RX1 Free interrupt
+  .word  IPCC_TX1_IRQHandler               // Mailbox TX1 Free interrupt
+  .word  CRYP2_IRQHandler                  // Crypto2 global interrupt
+  .word  HASH2_IRQHandler                  // Crypto Hash2 interrupt
+  .word  I2C5_EV_IRQHandler                // I2C5 Event Interrupt
+  .word  I2C5_ER_IRQHandler                // I2C5 Error Interrupt
+  .word  0                                 // Reserved
+  .word  DFSDM1_FLT0_IRQHandler            // DFSDM Filter0 Interrupt
+  .word  DFSDM1_FLT1_IRQHandler            // DFSDM Filter1 Interrupt
+  .word  DFSDM1_FLT2_IRQHandler            // DFSDM Filter2 Interrupt
+  .word  DFSDM1_FLT3_IRQHandler            // DFSDM Filter3 Interrupt
+  .word  SAI3_IRQHandler                   // SAI3 global Interrupt
+  .word  DFSDM1_FLT4_IRQHandler            // DFSDM Filter4 Interrupt
+  .word  TIM15_IRQHandler                  // TIM15 global Interrupt
+  .word  TIM16_IRQHandler                  // TIM16 global Interrupt
+  .word  TIM17_IRQHandler                  // TIM17 global Interrupt
+  .word  TIM12_IRQHandler                  // TIM12 global Interrupt
+  .word  MDIOS_IRQHandler                  // MDIOS global Interrupt
+  .word  EXTI14_IRQHandler                 // EXTI Line14 interrupts through AIEC
+  .word  MDMA_IRQHandler                   // MDMA global Interrupt
+  .word  0                                 // Reserved
+  .word  SDMMC2_IRQHandler                 // SDMMC2 global Interrupt
+  .word  HSEM_IT2_IRQHandler               // HSEM global Interrupt
+  .word  DFSDM1_FLT5_IRQHandler            // DFSDM Filter5 Interrupt
+  .word  EXTI15_IRQHandler                 // EXTI Line15 interrupts through AIEC
+  .word  nCTIIRQ1_IRQHandler               // Cortex-M4 CTI interrupt 1
+  .word  nCTIIRQ2_IRQHandler               // Cortex-M4 CTI interrupt 2
+  .word  TIM13_IRQHandler                  // TIM13 global interrupt
+  .word  TIM14_IRQHandler                  // TIM14 global interrupt
+  .word  DAC_IRQHandler                    // DAC1 and DAC2 underrun error interrupts
+  .word  RNG1_IRQHandler                   // RNG1 interrupt
+  .word  RNG2_IRQHandler                   // RNG2 interrupt
+  .word  I2C6_EV_IRQHandler                // I2C6 Event Interrupt
+  .word  I2C6_ER_IRQHandler                // I2C6 Error Interrupt
+  .word  SDMMC3_IRQHandler                 // SDMMC3 global Interrupt
+  .word  LPTIM2_IRQHandler                 // LPTIM2 global interrupt
+  .word  LPTIM3_IRQHandler                 // LPTIM3 global interrupt
+  .word  LPTIM4_IRQHandler                 // LPTIM4 global interrupt
+  .word  LPTIM5_IRQHandler                 // LPTIM5 global interrupt
+  .word  ETH1_LPI_IRQHandler               // ETH1_LPI interrupt 
+  .word  RESERVED143_IRQHandler            // Reserved
+  .word  MPU_SEV_IRQHandler                // MPU Send Event through AIEC
+  .word  RCC_WAKEUP_IRQHandler             // RCC Wake up interrupt
+  .word  SAI4_IRQHandler                   // SAI4 global interrupt
+  .word  DTS_IRQHandler                    // Temperature sensor interrupt
+  .word  RESERVED148_IRQHandler            // Reserved
+  .word  WAKEUP_PIN_IRQHandler             // Interrupt for all 6 wake-up pins
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak      BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak      UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak      DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak      RESERVED4_IRQHandler
+  .thumb_set RESERVED4_IRQHandler,Default_Handler
+
+  .weak      RESERVED99_IRQHandler
+  .thumb_set RESERVED99_IRQHandler,Default_Handler
+
+  .weak      ETH1_LPI_IRQHandler
+  .thumb_set ETH1_LPI_IRQHandler,Default_Handler
+
+  .weak      RESERVED143_IRQHandler
+  .thumb_set RESERVED143_IRQHandler,Default_Handler
+
+  .weak      WWDG1_IRQHandler
+  .thumb_set WWDG1_IRQHandler,Default_Handler
+
+  .weak      PVD_AVD_IRQHandler                      
+  .thumb_set PVD_AVD_IRQHandler,Default_Handler
+                           
+  .weak      TAMP_IRQHandler
+  .thumb_set TAMP_IRQHandler,Default_Handler
+     
+  .weak      RTC_WKUP_ALARM_IRQHandler
+  .thumb_set RTC_WKUP_ALARM_IRQHandler,Default_Handler
+                                                        
+  .weak      RCC_IRQHandler                      
+  .thumb_set RCC_IRQHandler,Default_Handler
+                                            
+  .weak      EXTI0_IRQHandler                    
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI1_IRQHandler                    
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+                                             
+  .weak      EXTI2_IRQHandler                    
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI3_IRQHandler                    
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI4_IRQHandler                    
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+                                                                               
+  .weak      DMA1_Stream0_IRQHandler
+  .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+  .weak      DMA1_Stream1_IRQHandler             
+  .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                          
+  .weak      DMA1_Stream2_IRQHandler             
+  .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                       
+  .weak      DMA1_Stream3_IRQHandler             
+  .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+                      
+  .weak      DMA1_Stream4_IRQHandler             
+  .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                          
+  .weak      DMA1_Stream5_IRQHandler             
+  .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                            
+  .weak      DMA1_Stream6_IRQHandler             
+  .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+  
+  .weak      ADC1_IRQHandler                      
+  .thumb_set ADC1_IRQHandler,Default_Handler
+  
+  .weak      ADC2_IRQHandler                      
+  .thumb_set ADC2_IRQHandler,Default_Handler
+                            
+  .weak      FDCAN1_IT0_IRQHandler
+  .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+  .weak      FDCAN2_IT0_IRQHandler
+  .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+  .weak      FDCAN1_IT1_IRQHandler
+  .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+                                              
+  .weak      FDCAN2_IT1_IRQHandler
+  .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+  .weak      FDCAN_CAL_IRQHandler
+  .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+                                                                                      
+  .weak      EXTI5_IRQHandler
+  .thumb_set EXTI5_IRQHandler,Default_Handler
+                                      
+  .weak      TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+                    
+  .weak      TIM1_UP_IRQHandler
+  .thumb_set TIM1_UP_IRQHandler,Default_Handler
+                  
+  .weak      TIM1_TRG_COM_IRQHandler
+  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+   
+  .weak      TIM1_CC_IRQHandler                  
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                                     
+  .weak      TIM2_IRQHandler                     
+  .thumb_set TIM2_IRQHandler,Default_Handler
+                                              
+  .weak      TIM3_IRQHandler                     
+  .thumb_set TIM3_IRQHandler,Default_Handler
+                                              
+  .weak      TIM4_IRQHandler                     
+  .thumb_set TIM4_IRQHandler,Default_Handler
+                                              
+  .weak      I2C1_EV_IRQHandler                  
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                                               
+  .weak      I2C1_ER_IRQHandler                  
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                                               
+  .weak      I2C2_EV_IRQHandler                  
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                                              
+  .weak      I2C2_ER_IRQHandler                  
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak      SPI1_IRQHandler                     
+  .thumb_set SPI1_IRQHandler,Default_Handler
+                                             
+  .weak      SPI2_IRQHandler                     
+  .thumb_set SPI2_IRQHandler,Default_Handler
+                                              
+  .weak      USART1_IRQHandler                   
+  .thumb_set USART1_IRQHandler,Default_Handler
+                                            
+  .weak      USART2_IRQHandler                   
+  .thumb_set USART2_IRQHandler,Default_Handler
+                                            
+  .weak      USART3_IRQHandler                   
+  .thumb_set USART3_IRQHandler,Default_Handler
+                                           
+  .weak      EXTI10_IRQHandler
+  .thumb_set EXTI10_IRQHandler,Default_Handler
+                                    
+  .weak      RTC_TIMESTAMP_IRQHandler
+  .thumb_set RTC_TIMESTAMP_IRQHandler,Default_Handler
+                    
+  .weak      EXTI11_IRQHandler
+  .thumb_set EXTI11_IRQHandler,Default_Handler
+
+  .weak      TIM8_BRK_IRQHandler
+  .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+                   
+  .weak      TIM8_UP_IRQHandler
+  .thumb_set TIM8_UP_IRQHandler,Default_Handler
+                   
+  .weak      TIM8_TRG_COM_IRQHandler
+  .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+   
+  .weak      TIM8_CC_IRQHandler                  
+  .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                                     
+  .weak      DMA1_Stream7_IRQHandler             
+  .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                                            
+  .weak      FMC_IRQHandler                      
+  .thumb_set FMC_IRQHandler,Default_Handler
+                                               
+  .weak      SDMMC1_IRQHandler
+  .thumb_set SDMMC1_IRQHandler,Default_Handler
+                                               
+  .weak      TIM5_IRQHandler                     
+  .thumb_set TIM5_IRQHandler,Default_Handler
+                                               
+  .weak      SPI3_IRQHandler                     
+  .thumb_set SPI3_IRQHandler,Default_Handler
+                                               
+  .weak      UART4_IRQHandler                    
+  .thumb_set UART4_IRQHandler,Default_Handler
+                                              
+  .weak      UART5_IRQHandler                    
+  .thumb_set UART5_IRQHandler,Default_Handler
+                                              
+  .weak      TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+                     
+  .weak      TIM7_IRQHandler                     
+  .thumb_set TIM7_IRQHandler,Default_Handler
+                      
+  .weak      DMA2_Stream0_IRQHandler             
+  .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+                                    
+  .weak      DMA2_Stream1_IRQHandler             
+  .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream2_IRQHandler             
+  .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+                                      
+  .weak      DMA2_Stream3_IRQHandler             
+  .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+                                      
+  .weak      DMA2_Stream4_IRQHandler             
+  .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+                                   
+  .weak      ETH1_IRQHandler                      
+  .thumb_set ETH1_IRQHandler,Default_Handler
+                                           
+  .weak      ETH1_WKUP_IRQHandler                 
+  .thumb_set ETH1_WKUP_IRQHandler,Default_Handler
+  
+  .weak      ETH1_LPI_IRQHandler                 
+  .thumb_set ETH1_LPI_IRQHandler,Default_Handler 
+                       
+  .weak      EXTI6_IRQHandler
+  .thumb_set EXTI6_IRQHandler,Default_Handler
+                                         
+  .weak      EXTI7_IRQHandler
+  .thumb_set EXTI7_IRQHandler,Default_Handler
+
+  .weak      EXTI8_IRQHandler
+  .thumb_set EXTI8_IRQHandler,Default_Handler
+
+  .weak      EXTI9_IRQHandler
+  .thumb_set EXTI9_IRQHandler,Default_Handler
+
+  .weak      DMA2_Stream5_IRQHandler             
+  .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream6_IRQHandler             
+  .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream7_IRQHandler             
+  .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                                     
+  .weak      USART6_IRQHandler                   
+  .thumb_set USART6_IRQHandler,Default_Handler
+                                             
+  .weak      I2C3_EV_IRQHandler                  
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                                                
+  .weak      I2C3_ER_IRQHandler                  
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                                                
+  .weak      USBH_OHCI_IRQHandler
+  .thumb_set USBH_OHCI_IRQHandler,Default_Handler
+                        
+  .weak      USBH_EHCI_IRQHandler
+  .thumb_set USBH_EHCI_IRQHandler,Default_Handler
+                        
+  .weak      EXTI12_IRQHandler
+  .thumb_set EXTI12_IRQHandler,Default_Handler
+
+  .weak      EXTI13_IRQHandler
+  .thumb_set EXTI13_IRQHandler,Default_Handler
+                                        
+  .weak      DCMI_IRQHandler                     
+  .thumb_set DCMI_IRQHandler,Default_Handler
+                                               
+  .weak      CRYP1_IRQHandler
+  .thumb_set CRYP1_IRQHandler,Default_Handler
+
+  .weak      HASH1_IRQHandler
+  .thumb_set HASH1_IRQHandler,Default_Handler
+
+  .weak      FPU_IRQHandler                      
+  .thumb_set FPU_IRQHandler,Default_Handler
+  
+  .weak      UART7_IRQHandler                    
+  .thumb_set UART7_IRQHandler,Default_Handler
+  
+  .weak      UART8_IRQHandler                    
+  .thumb_set UART8_IRQHandler,Default_Handler
+  
+  .weak      SPI4_IRQHandler                     
+  .thumb_set SPI4_IRQHandler,Default_Handler
+  
+  .weak      SPI5_IRQHandler                     
+  .thumb_set SPI5_IRQHandler,Default_Handler
+  
+  .weak      SPI6_IRQHandler                     
+  .thumb_set SPI6_IRQHandler,Default_Handler
+  
+  .weak      SAI1_IRQHandler                     
+  .thumb_set SAI1_IRQHandler,Default_Handler
+  
+  .weak      LTDC_IRQHandler                     
+  .thumb_set LTDC_IRQHandler,Default_Handler
+  
+  .weak      LTDC_ER_IRQHandler                  
+  .thumb_set LTDC_ER_IRQHandler,Default_Handler
+  
+  .weak      SAI2_IRQHandler                     
+  .thumb_set SAI2_IRQHandler,Default_Handler
+     
+  .weak      QUADSPI_IRQHandler                  
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+  
+  .weak      LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+  
+  .weak      CEC_IRQHandler                      
+  .thumb_set CEC_IRQHandler,Default_Handler
+     
+  .weak      I2C4_EV_IRQHandler                  
+  .thumb_set I2C4_EV_IRQHandler,Default_Handler
+  
+  .weak      I2C4_ER_IRQHandler                  
+  .thumb_set I2C4_ER_IRQHandler,Default_Handler
+   
+  .weak      SPDIF_RX_IRQHandler                 
+  .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+  .weak      OTG_IRQHandler
+  .thumb_set OTG_IRQHandler,Default_Handler
+  
+  .weak      IPCC_RX0_IRQHandler
+  .thumb_set IPCC_RX0_IRQHandler,Default_Handler
+
+  .weak      IPCC_TX0_IRQHandler
+  .thumb_set IPCC_TX0_IRQHandler,Default_Handler
+
+  .weak      DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+  .weak      IPCC_RX1_IRQHandler
+  .thumb_set IPCC_RX1_IRQHandler,Default_Handler
+  
+  .weak      IPCC_TX1_IRQHandler
+  .thumb_set IPCC_TX1_IRQHandler,Default_Handler
+
+  .weak      CRYP2_IRQHandler
+  .thumb_set CRYP2_IRQHandler,Default_Handler
+
+  .weak      HASH2_IRQHandler
+  .thumb_set HASH2_IRQHandler,Default_Handler
+
+  .weak      I2C5_EV_IRQHandler
+  .thumb_set I2C5_EV_IRQHandler,Default_Handler
+
+  .weak      I2C5_ER_IRQHandler
+  .thumb_set I2C5_ER_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT0_IRQHandler
+  .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT1_IRQHandler
+  .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT2_IRQHandler
+  .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT3_IRQHandler
+  .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+                                               
+  .weak      SAI3_IRQHandler                        
+  .thumb_set SAI3_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT4_IRQHandler
+  .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+                                               
+  .weak      TIM15_IRQHandler                       
+  .thumb_set TIM15_IRQHandler,Default_Handler
+                                               
+  .weak      TIM16_IRQHandler                       
+  .thumb_set TIM16_IRQHandler,Default_Handler
+                                                
+  .weak      TIM17_IRQHandler                       
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak      TIM12_IRQHandler                       
+  .thumb_set TIM12_IRQHandler,Default_Handler
+  
+  .weak      MDIOS_IRQHandler                       
+  .thumb_set MDIOS_IRQHandler,Default_Handler
+                                                
+  .weak      EXTI14_IRQHandler
+  .thumb_set EXTI14_IRQHandler,Default_Handler
+                                                 
+  .weak      MDMA_IRQHandler                        
+  .thumb_set MDMA_IRQHandler,Default_Handler
+                                                
+  .weak      SDMMC2_IRQHandler                      
+  .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+  .weak      HSEM_IT2_IRQHandler
+  .thumb_set HSEM_IT2_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT5_IRQHandler
+  .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+                                                 
+  .weak      EXTI15_IRQHandler
+  .thumb_set EXTI15_IRQHandler,Default_Handler
+
+  .weak      nCTIIRQ1_IRQHandler
+  .thumb_set nCTIIRQ1_IRQHandler,Default_Handler
+
+  .weak      nCTIIRQ2_IRQHandler
+  .thumb_set nCTIIRQ2_IRQHandler,Default_Handler
+
+  .weak      TIM13_IRQHandler
+  .thumb_set TIM13_IRQHandler,Default_Handler
+
+  .weak      TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak      DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak      RNG1_IRQHandler
+  .thumb_set RNG1_IRQHandler,Default_Handler
+
+  .weak      RNG2_IRQHandler
+  .thumb_set RNG2_IRQHandler,Default_Handler
+
+  .weak      I2C6_EV_IRQHandler
+  .thumb_set I2C6_EV_IRQHandler,Default_Handler
+
+  .weak      I2C6_ER_IRQHandler
+  .thumb_set I2C6_ER_IRQHandler,Default_Handler
+
+  .weak      SDMMC3_IRQHandler
+  .thumb_set SDMMC3_IRQHandler,Default_Handler
+                                                
+  .weak      LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+                                             
+  .weak      LPTIM3_IRQHandler
+  .thumb_set LPTIM3_IRQHandler,Default_Handler
+                                        
+  .weak      LPTIM4_IRQHandler
+  .thumb_set LPTIM4_IRQHandler,Default_Handler
+                                              
+  .weak      LPTIM5_IRQHandler
+  .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+  .weak      MPU_SEV_IRQHandler
+  .thumb_set MPU_SEV_IRQHandler,Default_Handler
+
+  .weak      RCC_WAKEUP_IRQHandler
+  .thumb_set RCC_WAKEUP_IRQHandler,Default_Handler
+
+  .weak      SAI4_IRQHandler
+  .thumb_set SAI4_IRQHandler,Default_Handler
+
+  .weak      DTS_IRQHandler
+  .thumb_set DTS_IRQHandler,Default_Handler
+
+  .weak      RESERVED148_IRQHandler
+  .thumb_set RESERVED148_IRQHandler,Default_Handler
+ 
+  .weak      WAKEUP_PIN_IRQHandler
+  .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157a_cm4.s

@@ -0,0 +1,780 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32mp157a_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32MP15xx Devices vector table for GCC based toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+  .section .startup_copro_fw.Reset_Handler,"ax"
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack      /* set stack pointer */
+
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      _sidata: End of code section, i.e., begin of data sections to copy from.
+ *      _sdata/_edata: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+  
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+  
+/* Call the clock system intitialization function.*/
+
+  bl  SystemInit
+ // ldr r0, =SystemInit
+ // blx r0
+/* Call static constructors */
+ bl __libc_init_array
+ // ldr r0, =__libc_init_array
+ // blx r0
+/* Call the application's entry point.*/
+  bl entry
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack                           // Top of Stack
+  .word  Reset_Handler                     // Reset Handler
+  .word  NMI_Handler                       // NMI Handler
+  .word  HardFault_Handler                 // Hard Fault Handler
+  .word  MemManage_Handler                 // MPU Fault Handler
+  .word  BusFault_Handler                  // Bus Fault Handler
+  .word  UsageFault_Handler                // Usage Fault Handler
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  SVC_Handler                       // SVCall Handler
+  .word  DebugMon_Handler                  // Debug Monitor Handler
+  .word  0                                 // Reserved
+  .word  PendSV_Handler                    // PendSV Handler
+  .word  SysTick_Handler                   // SysTick Handler
+
+                // External Interrupts
+  .word  WWDG1_IRQHandler                  // Window WatchDog 1
+  .word  PVD_AVD_IRQHandler                // PVD and AVD through EXTI Line detection                        
+  .word  TAMP_IRQHandler                   // Tamper and TimeStamps through the EXTI line
+  .word  RTC_WKUP_ALARM_IRQHandler         // RTC Wakeup and Alarm through the EXTI line
+  .word  RESERVED4_IRQHandler              // Reserved
+  .word  RCC_IRQHandler                    // RCC                                             
+  .word  EXTI0_IRQHandler                  // EXTI Line0                                             
+  .word  EXTI1_IRQHandler                  // EXTI Line1                                             
+  .word  EXTI2_IRQHandler                  // EXTI Line2                                             
+  .word  EXTI3_IRQHandler                  // EXTI Line3                                             
+  .word  EXTI4_IRQHandler                  // EXTI Line4 
+  .word  DMA1_Stream0_IRQHandler           // DMA1 Stream 0
+  .word  DMA1_Stream1_IRQHandler           // DMA1 Stream 1                                   
+  .word  DMA1_Stream2_IRQHandler           // DMA1 Stream 2                                   
+  .word  DMA1_Stream3_IRQHandler           // DMA1 Stream 3                                   
+  .word  DMA1_Stream4_IRQHandler           // DMA1 Stream 4                                   
+  .word  DMA1_Stream5_IRQHandler           // DMA1 Stream 5
+  .word  DMA1_Stream6_IRQHandler           // DMA1 Stream 6 
+  .word  ADC1_IRQHandler                   // ADC1                             
+  .word  FDCAN1_IT0_IRQHandler        // FDCAN1 Interrupt line 0
+  .word  FDCAN2_IT0_IRQHandler        // FDCAN2 Interrupt line 0
+  .word  FDCAN1_IT1_IRQHandler        // FDCAN1 Interrupt line 1
+  .word  FDCAN2_IT1_IRQHandler        // FDCAN2 Interrupt line 1
+  .word  EXTI5_IRQHandler                  // External Line5 interrupts through AIEC
+  .word  TIM1_BRK_IRQHandler               // TIM1 Break interrupt
+  .word  TIM1_UP_IRQHandler                 // TIM1 Update Interrupt
+  .word  TIM1_TRG_COM_IRQHandler           // TIM1 Trigger and Commutation Interrupt
+  .word  TIM1_CC_IRQHandler                // TIM1 Capture Compare                                   
+  .word  TIM2_IRQHandler                   // TIM2                                            
+  .word  TIM3_IRQHandler                   // TIM3                                            
+  .word  TIM4_IRQHandler                   // TIM4                                            
+  .word  I2C1_EV_IRQHandler                // I2C1 Event                                             
+  .word  I2C1_ER_IRQHandler                // I2C1 Error                                             
+  .word  I2C2_EV_IRQHandler                // I2C2 Event                                             
+  .word  I2C2_ER_IRQHandler                // I2C2 Error                                               
+  .word  SPI1_IRQHandler                   // SPI1                                            
+  .word  SPI2_IRQHandler                   // SPI2                                            
+  .word  USART1_IRQHandler                 // USART1                                          
+  .word  USART2_IRQHandler                 // USART2                                          
+  .word  USART3_IRQHandler                 // USART3                                          
+  .word  EXTI10_IRQHandler                 // External Line10 interrupts through AIEC
+  .word  RTC_TIMESTAMP_IRQHandler          // RTC TimeStamp through EXTI Line
+  .word  EXTI11_IRQHandler                 // External Line11 interrupts through AIEC
+  .word  TIM8_BRK_IRQHandler               // TIM8 Break Interrupt
+  .word  TIM8_UP_IRQHandler                // TIM8 Update Interrupt
+  .word  TIM8_TRG_COM_IRQHandler           // TIM8 Trigger and Commutation Interrupt
+  .word  TIM8_CC_IRQHandler                // TIM8 Capture Compare Interrupt
+  .word  DMA1_Stream7_IRQHandler           // DMA1 Stream7                                           
+  .word  FMC_IRQHandler                    // FMC                             
+  .word  SDMMC1_IRQHandler                 // SDMMC1
+  .word  TIM5_IRQHandler                   // TIM5                            
+  .word  SPI3_IRQHandler                   // SPI3                            
+  .word  UART4_IRQHandler                  // UART4                           
+  .word  UART5_IRQHandler                  // UART5                           
+  .word  TIM6_IRQHandler                   // TIM6
+  .word  TIM7_IRQHandler                   // TIM7           
+  .word  DMA2_Stream0_IRQHandler           // DMA2 Stream 0                   
+  .word  DMA2_Stream1_IRQHandler           // DMA2 Stream 1                   
+  .word  DMA2_Stream2_IRQHandler           // DMA2 Stream 2                   
+  .word  DMA2_Stream3_IRQHandler           // DMA2 Stream 3                   
+  .word  DMA2_Stream4_IRQHandler           // DMA2 Stream 4                   
+  .word  ETH1_IRQHandler                    // Ethernet                        
+  .word  ETH1_WKUP_IRQHandler               // Ethernet Wakeup through EXTI line              
+  .word  FDCAN_CAL_IRQHandler               // FDCAN Calibration
+  .word  EXTI6_IRQHandler                  // EXTI Line6 interrupts through AIEC
+  .word  EXTI7_IRQHandler                  // EXTI Line7 interrupts through AIEC
+  .word  EXTI8_IRQHandler                  // EXTI Line8 interrupts through AIEC
+  .word  EXTI9_IRQHandler                  // EXTI Line9 interrupts through AIEC
+  .word  DMA2_Stream5_IRQHandler           // DMA2 Stream 5                   
+  .word  DMA2_Stream6_IRQHandler           // DMA2 Stream 6                   
+  .word  DMA2_Stream7_IRQHandler           // DMA2 Stream 7                   
+  .word  USART6_IRQHandler                 // USART6                           
+  .word  I2C3_EV_IRQHandler                // I2C3 event                             
+  .word  I2C3_ER_IRQHandler                // I2C3 error                             
+  .word  USBH_OHCI_IRQHandler              // USB Host OHCI
+  .word  USBH_EHCI_IRQHandler              // USB Host EHCI
+  .word  EXTI12_IRQHandler                 // EXTI Line12 interrupts through AIEC
+  .word  EXTI13_IRQHandler                 // EXTI Line13 interrupts through AIEC
+  .word  DCMI_IRQHandler                   // DCMI                            
+  .word  0                                 // Reserved
+  .word  HASH1_IRQHandler                  // Crypto Hash1 interrupt
+  .word  FPU_IRQHandler                    // FPU
+  .word  UART7_IRQHandler                  // UART7
+  .word  UART8_IRQHandler                  // UART8
+  .word  SPI4_IRQHandler                   // SPI4
+  .word  SPI5_IRQHandler                   // SPI5
+  .word  SPI6_IRQHandler                   // SPI6
+  .word  SAI1_IRQHandler                   // SAI1
+  .word  LTDC_IRQHandler                   // LTDC
+  .word  LTDC_ER_IRQHandler                // LTDC error
+  .word  ADC2_IRQHandler                   // ADC2 
+  .word  SAI2_IRQHandler                   // SAI2
+  .word  QUADSPI_IRQHandler                // QUADSPI
+  .word  LPTIM1_IRQHandler                 // LPTIM1 global interrupt
+  .word  CEC_IRQHandler                    // HDMI_CEC
+  .word  I2C4_EV_IRQHandler                // I2C4 Event                             
+  .word  I2C4_ER_IRQHandler                // I2C4 Error 
+  .word  SPDIF_RX_IRQHandler               // SPDIF_RX
+  .word  OTG_IRQHandler                    // USB On The Go HS global interrupt
+  .word  RESERVED99_IRQHandler             // Reserved
+  .word  IPCC_RX0_IRQHandler               // Mailbox RX0 Free interrupt
+  .word  IPCC_TX0_IRQHandler               // Mailbox TX0 Free interrupt
+  .word  DMAMUX1_OVR_IRQHandler            // DMAMUX1 Overrun interrupt
+  .word  IPCC_RX1_IRQHandler               // Mailbox RX1 Free interrupt
+  .word  IPCC_TX1_IRQHandler               // Mailbox TX1 Free interrupt
+  .word  0                                 // Reserved
+  .word  HASH2_IRQHandler                  // Crypto Hash2 interrupt
+  .word  I2C5_EV_IRQHandler                // I2C5 Event Interrupt
+  .word  I2C5_ER_IRQHandler                // I2C5 Error Interrupt
+  .word  GPU_IRQHandler                    // GPU Global Interrupt
+  .word  DFSDM1_FLT0_IRQHandler            // DFSDM Filter0 Interrupt
+  .word  DFSDM1_FLT1_IRQHandler            // DFSDM Filter1 Interrupt
+  .word  DFSDM1_FLT2_IRQHandler            // DFSDM Filter2 Interrupt
+  .word  DFSDM1_FLT3_IRQHandler            // DFSDM Filter3 Interrupt
+  .word  SAI3_IRQHandler                   // SAI3 global Interrupt
+  .word  DFSDM1_FLT4_IRQHandler            // DFSDM Filter4 Interrupt
+  .word  TIM15_IRQHandler                  // TIM15 global Interrupt
+  .word  TIM16_IRQHandler                  // TIM16 global Interrupt
+  .word  TIM17_IRQHandler                  // TIM17 global Interrupt
+  .word  TIM12_IRQHandler                  // TIM12 global Interrupt
+  .word  MDIOS_IRQHandler                  // MDIOS global Interrupt
+  .word  EXTI14_IRQHandler                 // EXTI Line14 interrupts through AIEC
+  .word  MDMA_IRQHandler                   // MDMA global Interrupt
+  .word  DSI_IRQHandler                    // DSI global Interrupt
+  .word  SDMMC2_IRQHandler                 // SDMMC2 global Interrupt
+  .word  HSEM_IT2_IRQHandler               // HSEM global Interrupt
+  .word  DFSDM1_FLT5_IRQHandler            // DFSDM Filter5 Interrupt
+  .word  EXTI15_IRQHandler                 // EXTI Line15 interrupts through AIEC
+  .word  nCTIIRQ1_IRQHandler               // Cortex-M4 CTI interrupt 1
+  .word  nCTIIRQ2_IRQHandler               // Cortex-M4 CTI interrupt 2
+  .word  TIM13_IRQHandler                  // TIM13 global interrupt
+  .word  TIM14_IRQHandler                  // TIM14 global interrupt
+  .word  DAC_IRQHandler                    // DAC1 and DAC2 underrun error interrupts
+  .word  RNG1_IRQHandler                   // RNG1 interrupt
+  .word  RNG2_IRQHandler                   // RNG2 interrupt
+  .word  I2C6_EV_IRQHandler                // I2C6 Event Interrupt
+  .word  I2C6_ER_IRQHandler                // I2C6 Error Interrupt
+  .word  SDMMC3_IRQHandler                 // SDMMC3 global Interrupt
+  .word  LPTIM2_IRQHandler                 // LPTIM2 global interrupt
+  .word  LPTIM3_IRQHandler                 // LPTIM3 global interrupt
+  .word  LPTIM4_IRQHandler                 // LPTIM4 global interrupt
+  .word  LPTIM5_IRQHandler                 // LPTIM5 global interrupt
+  .word  ETH1_LPI_IRQHandler               // ETH1_LPI interrupt 
+  .word  RESERVED143_IRQHandler            // Reserved
+  .word  MPU_SEV_IRQHandler                // MPU Send Event through AIEC
+  .word  RCC_WAKEUP_IRQHandler             // RCC Wake up interrupt
+  .word  SAI4_IRQHandler                   // SAI4 global interrupt
+  .word  DTS_IRQHandler                    // Temperature sensor interrupt
+  .word  RESERVED148_IRQHandler            // Reserved
+  .word  WAKEUP_PIN_IRQHandler             // Interrupt for all 6 wake-up pins
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak      BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak      UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak      DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak      RESERVED4_IRQHandler
+  .thumb_set RESERVED4_IRQHandler,Default_Handler
+
+  .weak      RESERVED99_IRQHandler
+  .thumb_set RESERVED99_IRQHandler,Default_Handler
+
+  .weak      ETH1_LPI_IRQHandler
+  .thumb_set ETH1_LPI_IRQHandler,Default_Handler
+
+  .weak      RESERVED143_IRQHandler
+  .thumb_set RESERVED143_IRQHandler,Default_Handler
+
+  .weak      WWDG1_IRQHandler
+  .thumb_set WWDG1_IRQHandler,Default_Handler
+
+  .weak      PVD_AVD_IRQHandler                      
+  .thumb_set PVD_AVD_IRQHandler,Default_Handler
+                           
+  .weak      TAMP_IRQHandler
+  .thumb_set TAMP_IRQHandler,Default_Handler
+     
+  .weak      RTC_WKUP_ALARM_IRQHandler
+  .thumb_set RTC_WKUP_ALARM_IRQHandler,Default_Handler
+                                                        
+  .weak      RCC_IRQHandler                      
+  .thumb_set RCC_IRQHandler,Default_Handler
+                                            
+  .weak      EXTI0_IRQHandler                    
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI1_IRQHandler                    
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+                                             
+  .weak      EXTI2_IRQHandler                    
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI3_IRQHandler                    
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI4_IRQHandler                    
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+                                                                               
+  .weak      DMA1_Stream0_IRQHandler
+  .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+  .weak      DMA1_Stream1_IRQHandler             
+  .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                          
+  .weak      DMA1_Stream2_IRQHandler             
+  .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                       
+  .weak      DMA1_Stream3_IRQHandler             
+  .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+                      
+  .weak      DMA1_Stream4_IRQHandler             
+  .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                          
+  .weak      DMA1_Stream5_IRQHandler             
+  .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                            
+  .weak      DMA1_Stream6_IRQHandler             
+  .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+  
+  .weak      ADC1_IRQHandler                      
+  .thumb_set ADC1_IRQHandler,Default_Handler
+  
+  .weak      ADC2_IRQHandler                      
+  .thumb_set ADC2_IRQHandler,Default_Handler
+                            
+  .weak      FDCAN1_IT0_IRQHandler
+  .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+  .weak      FDCAN2_IT0_IRQHandler
+  .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+  .weak      FDCAN1_IT1_IRQHandler
+  .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+                                              
+  .weak      FDCAN2_IT1_IRQHandler
+  .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+  .weak      FDCAN_CAL_IRQHandler
+  .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+                                                                                      
+  .weak      EXTI5_IRQHandler
+  .thumb_set EXTI5_IRQHandler,Default_Handler
+                                      
+  .weak      TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+                    
+  .weak      TIM1_UP_IRQHandler
+  .thumb_set TIM1_UP_IRQHandler,Default_Handler
+                  
+  .weak      TIM1_TRG_COM_IRQHandler
+  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+   
+  .weak      TIM1_CC_IRQHandler                  
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                                     
+  .weak      TIM2_IRQHandler                     
+  .thumb_set TIM2_IRQHandler,Default_Handler
+                                              
+  .weak      TIM3_IRQHandler                     
+  .thumb_set TIM3_IRQHandler,Default_Handler
+                                              
+  .weak      TIM4_IRQHandler                     
+  .thumb_set TIM4_IRQHandler,Default_Handler
+                                              
+  .weak      I2C1_EV_IRQHandler                  
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                                               
+  .weak      I2C1_ER_IRQHandler                  
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                                               
+  .weak      I2C2_EV_IRQHandler                  
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                                              
+  .weak      I2C2_ER_IRQHandler                  
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak      SPI1_IRQHandler                     
+  .thumb_set SPI1_IRQHandler,Default_Handler
+                                             
+  .weak      SPI2_IRQHandler                     
+  .thumb_set SPI2_IRQHandler,Default_Handler
+                                              
+  .weak      USART1_IRQHandler                   
+  .thumb_set USART1_IRQHandler,Default_Handler
+                                            
+  .weak      USART2_IRQHandler                   
+  .thumb_set USART2_IRQHandler,Default_Handler
+                                            
+  .weak      USART3_IRQHandler                   
+  .thumb_set USART3_IRQHandler,Default_Handler
+                                           
+  .weak      EXTI10_IRQHandler
+  .thumb_set EXTI10_IRQHandler,Default_Handler
+                                    
+  .weak      RTC_TIMESTAMP_IRQHandler
+  .thumb_set RTC_TIMESTAMP_IRQHandler,Default_Handler
+                    
+  .weak      EXTI11_IRQHandler
+  .thumb_set EXTI11_IRQHandler,Default_Handler
+
+  .weak      TIM8_BRK_IRQHandler
+  .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+                   
+  .weak      TIM8_UP_IRQHandler
+  .thumb_set TIM8_UP_IRQHandler,Default_Handler
+                   
+  .weak      TIM8_TRG_COM_IRQHandler
+  .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+   
+  .weak      TIM8_CC_IRQHandler                  
+  .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                                     
+  .weak      DMA1_Stream7_IRQHandler             
+  .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                                            
+  .weak      FMC_IRQHandler                      
+  .thumb_set FMC_IRQHandler,Default_Handler
+                                               
+  .weak      SDMMC1_IRQHandler
+  .thumb_set SDMMC1_IRQHandler,Default_Handler
+                                               
+  .weak      TIM5_IRQHandler                     
+  .thumb_set TIM5_IRQHandler,Default_Handler
+                                               
+  .weak      SPI3_IRQHandler                     
+  .thumb_set SPI3_IRQHandler,Default_Handler
+                                               
+  .weak      UART4_IRQHandler                    
+  .thumb_set UART4_IRQHandler,Default_Handler
+                                              
+  .weak      UART5_IRQHandler                    
+  .thumb_set UART5_IRQHandler,Default_Handler
+                                              
+  .weak      TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+                     
+  .weak      TIM7_IRQHandler                     
+  .thumb_set TIM7_IRQHandler,Default_Handler
+                      
+  .weak      DMA2_Stream0_IRQHandler             
+  .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+                                    
+  .weak      DMA2_Stream1_IRQHandler             
+  .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream2_IRQHandler             
+  .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+                                      
+  .weak      DMA2_Stream3_IRQHandler             
+  .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+                                      
+  .weak      DMA2_Stream4_IRQHandler             
+  .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+                                   
+  .weak      ETH1_IRQHandler                      
+  .thumb_set ETH1_IRQHandler,Default_Handler
+                                           
+  .weak      ETH1_WKUP_IRQHandler                 
+  .thumb_set ETH1_WKUP_IRQHandler,Default_Handler
+  
+  .weak      ETH1_LPI_IRQHandler                 
+  .thumb_set ETH1_LPI_IRQHandler,Default_Handler 
+                       
+  .weak      EXTI6_IRQHandler
+  .thumb_set EXTI6_IRQHandler,Default_Handler
+                                         
+  .weak      EXTI7_IRQHandler
+  .thumb_set EXTI7_IRQHandler,Default_Handler
+
+  .weak      EXTI8_IRQHandler
+  .thumb_set EXTI8_IRQHandler,Default_Handler
+
+  .weak      EXTI9_IRQHandler
+  .thumb_set EXTI9_IRQHandler,Default_Handler
+
+  .weak      DMA2_Stream5_IRQHandler             
+  .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream6_IRQHandler             
+  .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream7_IRQHandler             
+  .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                                     
+  .weak      USART6_IRQHandler                   
+  .thumb_set USART6_IRQHandler,Default_Handler
+                                             
+  .weak      I2C3_EV_IRQHandler                  
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                                                
+  .weak      I2C3_ER_IRQHandler                  
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                                                
+  .weak      USBH_OHCI_IRQHandler
+  .thumb_set USBH_OHCI_IRQHandler,Default_Handler
+                        
+  .weak      USBH_EHCI_IRQHandler
+  .thumb_set USBH_EHCI_IRQHandler,Default_Handler
+                        
+  .weak      EXTI12_IRQHandler
+  .thumb_set EXTI12_IRQHandler,Default_Handler
+
+  .weak      EXTI13_IRQHandler
+  .thumb_set EXTI13_IRQHandler,Default_Handler
+                                        
+  .weak      DCMI_IRQHandler                     
+  .thumb_set DCMI_IRQHandler,Default_Handler
+
+  .weak      HASH1_IRQHandler
+  .thumb_set HASH1_IRQHandler,Default_Handler
+
+  .weak      FPU_IRQHandler                      
+  .thumb_set FPU_IRQHandler,Default_Handler
+  
+  .weak      UART7_IRQHandler                    
+  .thumb_set UART7_IRQHandler,Default_Handler
+  
+  .weak      UART8_IRQHandler                    
+  .thumb_set UART8_IRQHandler,Default_Handler
+  
+  .weak      SPI4_IRQHandler                     
+  .thumb_set SPI4_IRQHandler,Default_Handler
+  
+  .weak      SPI5_IRQHandler                     
+  .thumb_set SPI5_IRQHandler,Default_Handler
+  
+  .weak      SPI6_IRQHandler                     
+  .thumb_set SPI6_IRQHandler,Default_Handler
+  
+  .weak      SAI1_IRQHandler                     
+  .thumb_set SAI1_IRQHandler,Default_Handler
+  
+  .weak      LTDC_IRQHandler                     
+  .thumb_set LTDC_IRQHandler,Default_Handler
+  
+  .weak      LTDC_ER_IRQHandler                  
+  .thumb_set LTDC_ER_IRQHandler,Default_Handler
+  
+  .weak      SAI2_IRQHandler                     
+  .thumb_set SAI2_IRQHandler,Default_Handler
+     
+  .weak      QUADSPI_IRQHandler                  
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+  
+  .weak      LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+  
+  .weak      CEC_IRQHandler                      
+  .thumb_set CEC_IRQHandler,Default_Handler
+     
+  .weak      I2C4_EV_IRQHandler                  
+  .thumb_set I2C4_EV_IRQHandler,Default_Handler
+  
+  .weak      I2C4_ER_IRQHandler                  
+  .thumb_set I2C4_ER_IRQHandler,Default_Handler
+   
+  .weak      SPDIF_RX_IRQHandler                 
+  .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+  .weak      OTG_IRQHandler
+  .thumb_set OTG_IRQHandler,Default_Handler
+  
+  .weak      IPCC_RX0_IRQHandler
+  .thumb_set IPCC_RX0_IRQHandler,Default_Handler
+
+  .weak      IPCC_TX0_IRQHandler
+  .thumb_set IPCC_TX0_IRQHandler,Default_Handler
+
+  .weak      DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+  .weak      IPCC_RX1_IRQHandler
+  .thumb_set IPCC_RX1_IRQHandler,Default_Handler
+  
+  .weak      IPCC_TX1_IRQHandler
+  .thumb_set IPCC_TX1_IRQHandler,Default_Handler
+
+  .weak      HASH2_IRQHandler
+  .thumb_set HASH2_IRQHandler,Default_Handler
+
+  .weak      I2C5_EV_IRQHandler
+  .thumb_set I2C5_EV_IRQHandler,Default_Handler
+
+  .weak      I2C5_ER_IRQHandler
+  .thumb_set I2C5_ER_IRQHandler,Default_Handler
+
+  .weak      GPU_IRQHandler
+  .thumb_set GPU_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT0_IRQHandler
+  .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT1_IRQHandler
+  .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT2_IRQHandler
+  .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT3_IRQHandler
+  .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+                                               
+  .weak      SAI3_IRQHandler                        
+  .thumb_set SAI3_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT4_IRQHandler
+  .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+                                               
+  .weak      TIM15_IRQHandler                       
+  .thumb_set TIM15_IRQHandler,Default_Handler
+                                               
+  .weak      TIM16_IRQHandler                       
+  .thumb_set TIM16_IRQHandler,Default_Handler
+                                                
+  .weak      TIM17_IRQHandler                       
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak      TIM12_IRQHandler                       
+  .thumb_set TIM12_IRQHandler,Default_Handler
+  
+  .weak      MDIOS_IRQHandler                       
+  .thumb_set MDIOS_IRQHandler,Default_Handler
+                                                
+  .weak      EXTI14_IRQHandler
+  .thumb_set EXTI14_IRQHandler,Default_Handler
+                                                 
+  .weak      MDMA_IRQHandler                        
+  .thumb_set MDMA_IRQHandler,Default_Handler
+                                                 
+  .weak      DSI_IRQHandler                         
+  .thumb_set DSI_IRQHandler,Default_Handler 
+                                                
+  .weak      SDMMC2_IRQHandler                      
+  .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+  .weak      HSEM_IT2_IRQHandler
+  .thumb_set HSEM_IT2_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT5_IRQHandler
+  .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+                                                 
+  .weak      EXTI15_IRQHandler
+  .thumb_set EXTI15_IRQHandler,Default_Handler
+
+  .weak      nCTIIRQ1_IRQHandler
+  .thumb_set nCTIIRQ1_IRQHandler,Default_Handler
+
+  .weak      nCTIIRQ2_IRQHandler
+  .thumb_set nCTIIRQ2_IRQHandler,Default_Handler
+
+  .weak      TIM13_IRQHandler
+  .thumb_set TIM13_IRQHandler,Default_Handler
+
+  .weak      TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak      DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak      RNG1_IRQHandler
+  .thumb_set RNG1_IRQHandler,Default_Handler
+
+  .weak      RNG2_IRQHandler
+  .thumb_set RNG2_IRQHandler,Default_Handler
+
+  .weak      I2C6_EV_IRQHandler
+  .thumb_set I2C6_EV_IRQHandler,Default_Handler
+
+  .weak      I2C6_ER_IRQHandler
+  .thumb_set I2C6_ER_IRQHandler,Default_Handler
+
+  .weak      SDMMC3_IRQHandler
+  .thumb_set SDMMC3_IRQHandler,Default_Handler
+                                                
+  .weak      LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+                                             
+  .weak      LPTIM3_IRQHandler
+  .thumb_set LPTIM3_IRQHandler,Default_Handler
+                                        
+  .weak      LPTIM4_IRQHandler
+  .thumb_set LPTIM4_IRQHandler,Default_Handler
+                                              
+  .weak      LPTIM5_IRQHandler
+  .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+  .weak      MPU_SEV_IRQHandler
+  .thumb_set MPU_SEV_IRQHandler,Default_Handler
+
+  .weak      RCC_WAKEUP_IRQHandler
+  .thumb_set RCC_WAKEUP_IRQHandler,Default_Handler
+
+  .weak      SAI4_IRQHandler
+  .thumb_set SAI4_IRQHandler,Default_Handler
+
+  .weak      DTS_IRQHandler
+  .thumb_set DTS_IRQHandler,Default_Handler
+
+  .weak      RESERVED148_IRQHandler
+  .thumb_set RESERVED148_IRQHandler,Default_Handler
+ 
+  .weak      WAKEUP_PIN_IRQHandler
+  .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp157c_cm4.s

@@ -0,0 +1,786 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32mp157c_cm4.s
+  * @author    MCD Application Team
+  * @brief     STM32MP15xx Devices vector table for GCC based toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m4
+  .fpu softvfp
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+  .section .startup_copro_fw.Reset_Handler,"ax"
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack      /* set stack pointer */
+
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      _sidata: End of code section, i.e., begin of data sections to copy from.
+ *      _sdata/_edata: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+  
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+  
+/* Call the clock system intitialization function.*/
+
+  bl  SystemInit
+ // ldr r0, =SystemInit
+ // blx r0
+/* Call static constructors */
+ bl __libc_init_array
+ // ldr r0, =__libc_init_array
+ // blx r0
+/* Call the application's entry point.*/
+  bl entry
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M4.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+   .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack                           // Top of Stack
+  .word  Reset_Handler                     // Reset Handler
+  .word  NMI_Handler                       // NMI Handler
+  .word  HardFault_Handler                 // Hard Fault Handler
+  .word  MemManage_Handler                 // MPU Fault Handler
+  .word  BusFault_Handler                  // Bus Fault Handler
+  .word  UsageFault_Handler                // Usage Fault Handler
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  0                                 // Reserved
+  .word  SVC_Handler                       // SVCall Handler
+  .word  DebugMon_Handler                  // Debug Monitor Handler
+  .word  0                                 // Reserved
+  .word  PendSV_Handler                    // PendSV Handler
+  .word  SysTick_Handler                   // SysTick Handler
+
+                // External Interrupts
+  .word  WWDG1_IRQHandler                  // Window WatchDog 1
+  .word  PVD_AVD_IRQHandler                // PVD and AVD through EXTI Line detection                        
+  .word  TAMP_IRQHandler                   // Tamper and TimeStamps through the EXTI line
+  .word  RTC_WKUP_ALARM_IRQHandler         // RTC Wakeup and Alarm through the EXTI line
+  .word  RESERVED4_IRQHandler              // Reserved
+  .word  RCC_IRQHandler                    // RCC                                             
+  .word  EXTI0_IRQHandler                  // EXTI Line0                                             
+  .word  EXTI1_IRQHandler                  // EXTI Line1                                             
+  .word  EXTI2_IRQHandler                  // EXTI Line2                                             
+  .word  EXTI3_IRQHandler                  // EXTI Line3                                             
+  .word  EXTI4_IRQHandler                  // EXTI Line4 
+  .word  DMA1_Stream0_IRQHandler           // DMA1 Stream 0
+  .word  DMA1_Stream1_IRQHandler           // DMA1 Stream 1                                   
+  .word  DMA1_Stream2_IRQHandler           // DMA1 Stream 2                                   
+  .word  DMA1_Stream3_IRQHandler           // DMA1 Stream 3                                   
+  .word  DMA1_Stream4_IRQHandler           // DMA1 Stream 4                                   
+  .word  DMA1_Stream5_IRQHandler           // DMA1 Stream 5
+  .word  DMA1_Stream6_IRQHandler           // DMA1 Stream 6 
+  .word  ADC1_IRQHandler                   // ADC1                             
+  .word  FDCAN1_IT0_IRQHandler        // FDCAN1 Interrupt line 0
+  .word  FDCAN2_IT0_IRQHandler        // FDCAN2 Interrupt line 0
+  .word  FDCAN1_IT1_IRQHandler        // FDCAN1 Interrupt line 1
+  .word  FDCAN2_IT1_IRQHandler        // FDCAN2 Interrupt line 1
+  .word  EXTI5_IRQHandler                  // External Line5 interrupts through AIEC
+  .word  TIM1_BRK_IRQHandler               // TIM1 Break interrupt
+  .word  TIM1_UP_IRQHandler                 // TIM1 Update Interrupt
+  .word  TIM1_TRG_COM_IRQHandler           // TIM1 Trigger and Commutation Interrupt
+  .word  TIM1_CC_IRQHandler                // TIM1 Capture Compare                                   
+  .word  TIM2_IRQHandler                   // TIM2                                            
+  .word  TIM3_IRQHandler                   // TIM3                                            
+  .word  TIM4_IRQHandler                   // TIM4                                            
+  .word  I2C1_EV_IRQHandler                // I2C1 Event                                             
+  .word  I2C1_ER_IRQHandler                // I2C1 Error                                             
+  .word  I2C2_EV_IRQHandler                // I2C2 Event                                             
+  .word  I2C2_ER_IRQHandler                // I2C2 Error                                               
+  .word  SPI1_IRQHandler                   // SPI1                                            
+  .word  SPI2_IRQHandler                   // SPI2                                            
+  .word  USART1_IRQHandler                 // USART1                                          
+  .word  USART2_IRQHandler                 // USART2                                          
+  .word  USART3_IRQHandler                 // USART3                                          
+  .word  EXTI10_IRQHandler                 // External Line10 interrupts through AIEC
+  .word  RTC_TIMESTAMP_IRQHandler          // RTC TimeStamp through EXTI Line
+  .word  EXTI11_IRQHandler                 // External Line11 interrupts through AIEC
+  .word  TIM8_BRK_IRQHandler               // TIM8 Break Interrupt
+  .word  TIM8_UP_IRQHandler                // TIM8 Update Interrupt
+  .word  TIM8_TRG_COM_IRQHandler           // TIM8 Trigger and Commutation Interrupt
+  .word  TIM8_CC_IRQHandler                // TIM8 Capture Compare Interrupt
+  .word  DMA1_Stream7_IRQHandler           // DMA1 Stream7                                           
+  .word  FMC_IRQHandler                    // FMC                             
+  .word  SDMMC1_IRQHandler                 // SDMMC1
+  .word  TIM5_IRQHandler                   // TIM5                            
+  .word  SPI3_IRQHandler                   // SPI3                            
+  .word  UART4_IRQHandler                  // UART4                           
+  .word  UART5_IRQHandler                  // UART5                           
+  .word  TIM6_IRQHandler                   // TIM6
+  .word  TIM7_IRQHandler                   // TIM7           
+  .word  DMA2_Stream0_IRQHandler           // DMA2 Stream 0                   
+  .word  DMA2_Stream1_IRQHandler           // DMA2 Stream 1                   
+  .word  DMA2_Stream2_IRQHandler           // DMA2 Stream 2                   
+  .word  DMA2_Stream3_IRQHandler           // DMA2 Stream 3                   
+  .word  DMA2_Stream4_IRQHandler           // DMA2 Stream 4                   
+  .word  ETH1_IRQHandler                    // Ethernet                        
+  .word  ETH1_WKUP_IRQHandler               // Ethernet Wakeup through EXTI line              
+  .word  FDCAN_CAL_IRQHandler               // FDCAN Calibration
+  .word  EXTI6_IRQHandler                  // EXTI Line6 interrupts through AIEC
+  .word  EXTI7_IRQHandler                  // EXTI Line7 interrupts through AIEC
+  .word  EXTI8_IRQHandler                  // EXTI Line8 interrupts through AIEC
+  .word  EXTI9_IRQHandler                  // EXTI Line9 interrupts through AIEC
+  .word  DMA2_Stream5_IRQHandler           // DMA2 Stream 5                   
+  .word  DMA2_Stream6_IRQHandler           // DMA2 Stream 6                   
+  .word  DMA2_Stream7_IRQHandler           // DMA2 Stream 7                   
+  .word  USART6_IRQHandler                 // USART6                           
+  .word  I2C3_EV_IRQHandler                // I2C3 event                             
+  .word  I2C3_ER_IRQHandler                // I2C3 error                             
+  .word  USBH_OHCI_IRQHandler              // USB Host OHCI
+  .word  USBH_EHCI_IRQHandler              // USB Host EHCI
+  .word  EXTI12_IRQHandler                 // EXTI Line12 interrupts through AIEC
+  .word  EXTI13_IRQHandler                 // EXTI Line13 interrupts through AIEC
+  .word  DCMI_IRQHandler                   // DCMI                            
+  .word  CRYP1_IRQHandler                  // Crypto1 global interrupt
+  .word  HASH1_IRQHandler                  // Crypto Hash1 interrupt
+  .word  FPU_IRQHandler                    // FPU
+  .word  UART7_IRQHandler                  // UART7
+  .word  UART8_IRQHandler                  // UART8
+  .word  SPI4_IRQHandler                   // SPI4
+  .word  SPI5_IRQHandler                   // SPI5
+  .word  SPI6_IRQHandler                   // SPI6
+  .word  SAI1_IRQHandler                   // SAI1
+  .word  LTDC_IRQHandler                   // LTDC
+  .word  LTDC_ER_IRQHandler                // LTDC error
+  .word  ADC2_IRQHandler                   // ADC2 
+  .word  SAI2_IRQHandler                   // SAI2
+  .word  QUADSPI_IRQHandler                // QUADSPI
+  .word  LPTIM1_IRQHandler                 // LPTIM1 global interrupt
+  .word  CEC_IRQHandler                    // HDMI_CEC
+  .word  I2C4_EV_IRQHandler                // I2C4 Event                             
+  .word  I2C4_ER_IRQHandler                // I2C4 Error 
+  .word  SPDIF_RX_IRQHandler               // SPDIF_RX
+  .word  OTG_IRQHandler                    // USB On The Go HS global interrupt
+  .word  RESERVED99_IRQHandler             // Reserved
+  .word  IPCC_RX0_IRQHandler               // Mailbox RX0 Free interrupt
+  .word  IPCC_TX0_IRQHandler               // Mailbox TX0 Free interrupt
+  .word  DMAMUX1_OVR_IRQHandler            // DMAMUX1 Overrun interrupt
+  .word  IPCC_RX1_IRQHandler               // Mailbox RX1 Free interrupt
+  .word  IPCC_TX1_IRQHandler               // Mailbox TX1 Free interrupt
+  .word  CRYP2_IRQHandler                  // Crypto2 global interrupt
+  .word  HASH2_IRQHandler                  // Crypto Hash2 interrupt
+  .word  I2C5_EV_IRQHandler                // I2C5 Event Interrupt
+  .word  I2C5_ER_IRQHandler                // I2C5 Error Interrupt
+  .word  GPU_IRQHandler                    // GPU Global Interrupt
+  .word  DFSDM1_FLT0_IRQHandler            // DFSDM Filter0 Interrupt
+  .word  DFSDM1_FLT1_IRQHandler            // DFSDM Filter1 Interrupt
+  .word  DFSDM1_FLT2_IRQHandler            // DFSDM Filter2 Interrupt
+  .word  DFSDM1_FLT3_IRQHandler            // DFSDM Filter3 Interrupt
+  .word  SAI3_IRQHandler                   // SAI3 global Interrupt
+  .word  DFSDM1_FLT4_IRQHandler            // DFSDM Filter4 Interrupt
+  .word  TIM15_IRQHandler                  // TIM15 global Interrupt
+  .word  TIM16_IRQHandler                  // TIM16 global Interrupt
+  .word  TIM17_IRQHandler                  // TIM17 global Interrupt
+  .word  TIM12_IRQHandler                  // TIM12 global Interrupt
+  .word  MDIOS_IRQHandler                  // MDIOS global Interrupt
+  .word  EXTI14_IRQHandler                 // EXTI Line14 interrupts through AIEC
+  .word  MDMA_IRQHandler                   // MDMA global Interrupt
+  .word  DSI_IRQHandler                    // DSI global Interrupt
+  .word  SDMMC2_IRQHandler                 // SDMMC2 global Interrupt
+  .word  HSEM_IT2_IRQHandler               // HSEM global Interrupt
+  .word  DFSDM1_FLT5_IRQHandler            // DFSDM Filter5 Interrupt
+  .word  EXTI15_IRQHandler                 // EXTI Line15 interrupts through AIEC
+  .word  nCTIIRQ1_IRQHandler               // Cortex-M4 CTI interrupt 1
+  .word  nCTIIRQ2_IRQHandler               // Cortex-M4 CTI interrupt 2
+  .word  TIM13_IRQHandler                  // TIM13 global interrupt
+  .word  TIM14_IRQHandler                  // TIM14 global interrupt
+  .word  DAC_IRQHandler                    // DAC1 and DAC2 underrun error interrupts
+  .word  RNG1_IRQHandler                   // RNG1 interrupt
+  .word  RNG2_IRQHandler                   // RNG2 interrupt
+  .word  I2C6_EV_IRQHandler                // I2C6 Event Interrupt
+  .word  I2C6_ER_IRQHandler                // I2C6 Error Interrupt
+  .word  SDMMC3_IRQHandler                 // SDMMC3 global Interrupt
+  .word  LPTIM2_IRQHandler                 // LPTIM2 global interrupt
+  .word  LPTIM3_IRQHandler                 // LPTIM3 global interrupt
+  .word  LPTIM4_IRQHandler                 // LPTIM4 global interrupt
+  .word  LPTIM5_IRQHandler                 // LPTIM5 global interrupt
+  .word  ETH1_LPI_IRQHandler               // ETH1_LPI interrupt 
+  .word  RESERVED143_IRQHandler            // Reserved
+  .word  MPU_SEV_IRQHandler                // MPU Send Event through AIEC
+  .word  RCC_WAKEUP_IRQHandler             // RCC Wake up interrupt
+  .word  SAI4_IRQHandler                   // SAI4 global interrupt
+  .word  DTS_IRQHandler                    // Temperature sensor interrupt
+  .word  RESERVED148_IRQHandler            // Reserved
+  .word  WAKEUP_PIN_IRQHandler             // Interrupt for all 6 wake-up pins
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak      NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak      HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak      MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak      BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak      UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak      SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak      DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak      PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak      SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak      RESERVED4_IRQHandler
+  .thumb_set RESERVED4_IRQHandler,Default_Handler
+
+  .weak      RESERVED99_IRQHandler
+  .thumb_set RESERVED99_IRQHandler,Default_Handler
+
+  .weak      ETH1_LPI_IRQHandler
+  .thumb_set ETH1_LPI_IRQHandler,Default_Handler
+
+  .weak      RESERVED143_IRQHandler
+  .thumb_set RESERVED143_IRQHandler,Default_Handler
+
+  .weak      WWDG1_IRQHandler
+  .thumb_set WWDG1_IRQHandler,Default_Handler
+
+  .weak      PVD_AVD_IRQHandler                      
+  .thumb_set PVD_AVD_IRQHandler,Default_Handler
+                           
+  .weak      TAMP_IRQHandler
+  .thumb_set TAMP_IRQHandler,Default_Handler
+     
+  .weak      RTC_WKUP_ALARM_IRQHandler
+  .thumb_set RTC_WKUP_ALARM_IRQHandler,Default_Handler
+                                                        
+  .weak      RCC_IRQHandler                      
+  .thumb_set RCC_IRQHandler,Default_Handler
+                                            
+  .weak      EXTI0_IRQHandler                    
+  .thumb_set EXTI0_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI1_IRQHandler                    
+  .thumb_set EXTI1_IRQHandler,Default_Handler
+                                             
+  .weak      EXTI2_IRQHandler                    
+  .thumb_set EXTI2_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI3_IRQHandler                    
+  .thumb_set EXTI3_IRQHandler,Default_Handler
+                                              
+  .weak      EXTI4_IRQHandler                    
+  .thumb_set EXTI4_IRQHandler,Default_Handler
+                                                                               
+  .weak      DMA1_Stream0_IRQHandler
+  .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+  .weak      DMA1_Stream1_IRQHandler             
+  .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                          
+  .weak      DMA1_Stream2_IRQHandler             
+  .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                       
+  .weak      DMA1_Stream3_IRQHandler             
+  .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+                      
+  .weak      DMA1_Stream4_IRQHandler             
+  .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                          
+  .weak      DMA1_Stream5_IRQHandler             
+  .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                            
+  .weak      DMA1_Stream6_IRQHandler             
+  .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+  
+  .weak      ADC1_IRQHandler                      
+  .thumb_set ADC1_IRQHandler,Default_Handler
+  
+  .weak      ADC2_IRQHandler                      
+  .thumb_set ADC2_IRQHandler,Default_Handler
+                            
+  .weak      FDCAN1_IT0_IRQHandler
+  .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+  .weak      FDCAN2_IT0_IRQHandler
+  .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+  .weak      FDCAN1_IT1_IRQHandler
+  .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+                                              
+  .weak      FDCAN2_IT1_IRQHandler
+  .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+  .weak      FDCAN_CAL_IRQHandler
+  .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+                                                                                      
+  .weak      EXTI5_IRQHandler
+  .thumb_set EXTI5_IRQHandler,Default_Handler
+                                      
+  .weak      TIM1_BRK_IRQHandler
+  .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+                    
+  .weak      TIM1_UP_IRQHandler
+  .thumb_set TIM1_UP_IRQHandler,Default_Handler
+                  
+  .weak      TIM1_TRG_COM_IRQHandler
+  .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+   
+  .weak      TIM1_CC_IRQHandler                  
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                                     
+  .weak      TIM2_IRQHandler                     
+  .thumb_set TIM2_IRQHandler,Default_Handler
+                                              
+  .weak      TIM3_IRQHandler                     
+  .thumb_set TIM3_IRQHandler,Default_Handler
+                                              
+  .weak      TIM4_IRQHandler                     
+  .thumb_set TIM4_IRQHandler,Default_Handler
+                                              
+  .weak      I2C1_EV_IRQHandler                  
+  .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                                               
+  .weak      I2C1_ER_IRQHandler                  
+  .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                                               
+  .weak      I2C2_EV_IRQHandler                  
+  .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                                              
+  .weak      I2C2_ER_IRQHandler                  
+  .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+  .weak      SPI1_IRQHandler                     
+  .thumb_set SPI1_IRQHandler,Default_Handler
+                                             
+  .weak      SPI2_IRQHandler                     
+  .thumb_set SPI2_IRQHandler,Default_Handler
+                                              
+  .weak      USART1_IRQHandler                   
+  .thumb_set USART1_IRQHandler,Default_Handler
+                                            
+  .weak      USART2_IRQHandler                   
+  .thumb_set USART2_IRQHandler,Default_Handler
+                                            
+  .weak      USART3_IRQHandler                   
+  .thumb_set USART3_IRQHandler,Default_Handler
+                                           
+  .weak      EXTI10_IRQHandler
+  .thumb_set EXTI10_IRQHandler,Default_Handler
+                                    
+  .weak      RTC_TIMESTAMP_IRQHandler
+  .thumb_set RTC_TIMESTAMP_IRQHandler,Default_Handler
+                    
+  .weak      EXTI11_IRQHandler
+  .thumb_set EXTI11_IRQHandler,Default_Handler
+
+  .weak      TIM8_BRK_IRQHandler
+  .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+                   
+  .weak      TIM8_UP_IRQHandler
+  .thumb_set TIM8_UP_IRQHandler,Default_Handler
+                   
+  .weak      TIM8_TRG_COM_IRQHandler
+  .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+   
+  .weak      TIM8_CC_IRQHandler                  
+  .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                                     
+  .weak      DMA1_Stream7_IRQHandler             
+  .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                                            
+  .weak      FMC_IRQHandler                      
+  .thumb_set FMC_IRQHandler,Default_Handler
+                                               
+  .weak      SDMMC1_IRQHandler
+  .thumb_set SDMMC1_IRQHandler,Default_Handler
+                                               
+  .weak      TIM5_IRQHandler                     
+  .thumb_set TIM5_IRQHandler,Default_Handler
+                                               
+  .weak      SPI3_IRQHandler                     
+  .thumb_set SPI3_IRQHandler,Default_Handler
+                                               
+  .weak      UART4_IRQHandler                    
+  .thumb_set UART4_IRQHandler,Default_Handler
+                                              
+  .weak      UART5_IRQHandler                    
+  .thumb_set UART5_IRQHandler,Default_Handler
+                                              
+  .weak      TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+                     
+  .weak      TIM7_IRQHandler                     
+  .thumb_set TIM7_IRQHandler,Default_Handler
+                      
+  .weak      DMA2_Stream0_IRQHandler             
+  .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+                                    
+  .weak      DMA2_Stream1_IRQHandler             
+  .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream2_IRQHandler             
+  .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+                                      
+  .weak      DMA2_Stream3_IRQHandler             
+  .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+                                      
+  .weak      DMA2_Stream4_IRQHandler             
+  .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+                                   
+  .weak      ETH1_IRQHandler                      
+  .thumb_set ETH1_IRQHandler,Default_Handler
+                                           
+  .weak      ETH1_WKUP_IRQHandler                 
+  .thumb_set ETH1_WKUP_IRQHandler,Default_Handler
+  
+  .weak      ETH1_LPI_IRQHandler                 
+  .thumb_set ETH1_LPI_IRQHandler,Default_Handler 
+                       
+  .weak      EXTI6_IRQHandler
+  .thumb_set EXTI6_IRQHandler,Default_Handler
+                                         
+  .weak      EXTI7_IRQHandler
+  .thumb_set EXTI7_IRQHandler,Default_Handler
+
+  .weak      EXTI8_IRQHandler
+  .thumb_set EXTI8_IRQHandler,Default_Handler
+
+  .weak      EXTI9_IRQHandler
+  .thumb_set EXTI9_IRQHandler,Default_Handler
+
+  .weak      DMA2_Stream5_IRQHandler             
+  .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream6_IRQHandler             
+  .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                                     
+  .weak      DMA2_Stream7_IRQHandler             
+  .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                                     
+  .weak      USART6_IRQHandler                   
+  .thumb_set USART6_IRQHandler,Default_Handler
+                                             
+  .weak      I2C3_EV_IRQHandler                  
+  .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                                                
+  .weak      I2C3_ER_IRQHandler                  
+  .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                                                
+  .weak      USBH_OHCI_IRQHandler
+  .thumb_set USBH_OHCI_IRQHandler,Default_Handler
+                        
+  .weak      USBH_EHCI_IRQHandler
+  .thumb_set USBH_EHCI_IRQHandler,Default_Handler
+                        
+  .weak      EXTI12_IRQHandler
+  .thumb_set EXTI12_IRQHandler,Default_Handler
+
+  .weak      EXTI13_IRQHandler
+  .thumb_set EXTI13_IRQHandler,Default_Handler
+                                        
+  .weak      DCMI_IRQHandler                     
+  .thumb_set DCMI_IRQHandler,Default_Handler
+                                               
+  .weak      CRYP1_IRQHandler
+  .thumb_set CRYP1_IRQHandler,Default_Handler
+
+  .weak      HASH1_IRQHandler
+  .thumb_set HASH1_IRQHandler,Default_Handler
+
+  .weak      FPU_IRQHandler                      
+  .thumb_set FPU_IRQHandler,Default_Handler
+  
+  .weak      UART7_IRQHandler                    
+  .thumb_set UART7_IRQHandler,Default_Handler
+  
+  .weak      UART8_IRQHandler                    
+  .thumb_set UART8_IRQHandler,Default_Handler
+  
+  .weak      SPI4_IRQHandler                     
+  .thumb_set SPI4_IRQHandler,Default_Handler
+  
+  .weak      SPI5_IRQHandler                     
+  .thumb_set SPI5_IRQHandler,Default_Handler
+  
+  .weak      SPI6_IRQHandler                     
+  .thumb_set SPI6_IRQHandler,Default_Handler
+  
+  .weak      SAI1_IRQHandler                     
+  .thumb_set SAI1_IRQHandler,Default_Handler
+  
+  .weak      LTDC_IRQHandler                     
+  .thumb_set LTDC_IRQHandler,Default_Handler
+  
+  .weak      LTDC_ER_IRQHandler                  
+  .thumb_set LTDC_ER_IRQHandler,Default_Handler
+  
+  .weak      SAI2_IRQHandler                     
+  .thumb_set SAI2_IRQHandler,Default_Handler
+     
+  .weak      QUADSPI_IRQHandler                  
+  .thumb_set QUADSPI_IRQHandler,Default_Handler
+  
+  .weak      LPTIM1_IRQHandler
+  .thumb_set LPTIM1_IRQHandler,Default_Handler
+  
+  .weak      CEC_IRQHandler                      
+  .thumb_set CEC_IRQHandler,Default_Handler
+     
+  .weak      I2C4_EV_IRQHandler                  
+  .thumb_set I2C4_EV_IRQHandler,Default_Handler
+  
+  .weak      I2C4_ER_IRQHandler                  
+  .thumb_set I2C4_ER_IRQHandler,Default_Handler
+   
+  .weak      SPDIF_RX_IRQHandler                 
+  .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+  .weak      OTG_IRQHandler
+  .thumb_set OTG_IRQHandler,Default_Handler
+  
+  .weak      IPCC_RX0_IRQHandler
+  .thumb_set IPCC_RX0_IRQHandler,Default_Handler
+
+  .weak      IPCC_TX0_IRQHandler
+  .thumb_set IPCC_TX0_IRQHandler,Default_Handler
+
+  .weak      DMAMUX1_OVR_IRQHandler
+  .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+  .weak      IPCC_RX1_IRQHandler
+  .thumb_set IPCC_RX1_IRQHandler,Default_Handler
+  
+  .weak      IPCC_TX1_IRQHandler
+  .thumb_set IPCC_TX1_IRQHandler,Default_Handler
+
+  .weak      CRYP2_IRQHandler
+  .thumb_set CRYP2_IRQHandler,Default_Handler
+
+  .weak      HASH2_IRQHandler
+  .thumb_set HASH2_IRQHandler,Default_Handler
+
+  .weak      I2C5_EV_IRQHandler
+  .thumb_set I2C5_EV_IRQHandler,Default_Handler
+
+  .weak      I2C5_ER_IRQHandler
+  .thumb_set I2C5_ER_IRQHandler,Default_Handler
+
+  .weak      GPU_IRQHandler
+  .thumb_set GPU_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT0_IRQHandler
+  .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT1_IRQHandler
+  .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT2_IRQHandler
+  .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+                                               
+  .weak      DFSDM1_FLT3_IRQHandler
+  .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+                                               
+  .weak      SAI3_IRQHandler                        
+  .thumb_set SAI3_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT4_IRQHandler
+  .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+                                               
+  .weak      TIM15_IRQHandler                       
+  .thumb_set TIM15_IRQHandler,Default_Handler
+                                               
+  .weak      TIM16_IRQHandler                       
+  .thumb_set TIM16_IRQHandler,Default_Handler
+                                                
+  .weak      TIM17_IRQHandler                       
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak      TIM12_IRQHandler                       
+  .thumb_set TIM12_IRQHandler,Default_Handler
+  
+  .weak      MDIOS_IRQHandler                       
+  .thumb_set MDIOS_IRQHandler,Default_Handler
+                                                
+  .weak      EXTI14_IRQHandler
+  .thumb_set EXTI14_IRQHandler,Default_Handler
+                                                 
+  .weak      MDMA_IRQHandler                        
+  .thumb_set MDMA_IRQHandler,Default_Handler
+                                                 
+  .weak      DSI_IRQHandler                         
+  .thumb_set DSI_IRQHandler,Default_Handler 
+                                                
+  .weak      SDMMC2_IRQHandler                      
+  .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+  .weak      HSEM_IT2_IRQHandler
+  .thumb_set HSEM_IT2_IRQHandler,Default_Handler
+
+  .weak      DFSDM1_FLT5_IRQHandler
+  .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+                                                 
+  .weak      EXTI15_IRQHandler
+  .thumb_set EXTI15_IRQHandler,Default_Handler
+
+  .weak      nCTIIRQ1_IRQHandler
+  .thumb_set nCTIIRQ1_IRQHandler,Default_Handler
+
+  .weak      nCTIIRQ2_IRQHandler
+  .thumb_set nCTIIRQ2_IRQHandler,Default_Handler
+
+  .weak      TIM13_IRQHandler
+  .thumb_set TIM13_IRQHandler,Default_Handler
+
+  .weak      TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak      DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak      RNG1_IRQHandler
+  .thumb_set RNG1_IRQHandler,Default_Handler
+
+  .weak      RNG2_IRQHandler
+  .thumb_set RNG2_IRQHandler,Default_Handler
+
+  .weak      I2C6_EV_IRQHandler
+  .thumb_set I2C6_EV_IRQHandler,Default_Handler
+
+  .weak      I2C6_ER_IRQHandler
+  .thumb_set I2C6_ER_IRQHandler,Default_Handler
+
+  .weak      SDMMC3_IRQHandler
+  .thumb_set SDMMC3_IRQHandler,Default_Handler
+                                                
+  .weak      LPTIM2_IRQHandler
+  .thumb_set LPTIM2_IRQHandler,Default_Handler
+                                             
+  .weak      LPTIM3_IRQHandler
+  .thumb_set LPTIM3_IRQHandler,Default_Handler
+                                        
+  .weak      LPTIM4_IRQHandler
+  .thumb_set LPTIM4_IRQHandler,Default_Handler
+                                              
+  .weak      LPTIM5_IRQHandler
+  .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+  .weak      MPU_SEV_IRQHandler
+  .thumb_set MPU_SEV_IRQHandler,Default_Handler
+
+  .weak      RCC_WAKEUP_IRQHandler
+  .thumb_set RCC_WAKEUP_IRQHandler,Default_Handler
+
+  .weak      SAI4_IRQHandler
+  .thumb_set SAI4_IRQHandler,Default_Handler
+
+  .weak      DTS_IRQHandler
+  .thumb_set DTS_IRQHandler,Default_Handler
+
+  .weak      RESERVED148_IRQHandler
+  .thumb_set RESERVED148_IRQHandler,Default_Handler
+ 
+  .weak      WAKEUP_PIN_IRQHandler
+  .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

bsp/stm32/libraries/STM32MPxx_HAL/CMSIS/Device/ST/STM32MP1xx/Source/Templates/gcc/startup_stm32mp15xx.s

@@ -95,14 +95,8 @@ LoopFillZerobss:
  // ldr r0, =__libc_init_array
  // blx r0
 /* Call the application's entry point.*/
-  bl main
-  //ldr r0, =main
-  //blx r0
-
-LoopForever:
-    b LoopForever
-
-
+  bl entry
+  bx lr
 .size Reset_Handler, .-Reset_Handler
 
 /**

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

@@ -38,7 +38,6 @@
 #define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
 #define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
 #define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
-
 /**
   * @}
   */
@@ -315,6 +314,11 @@
 #if defined(STM32G0)
 #define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
 #define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM
 #endif
 
 #if defined(STM32H7)
@@ -643,6 +647,10 @@
 #define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
 #define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
 #define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
 #endif /* STM32G4 */
 
 #if defined(STM32H7)
@@ -887,7 +895,6 @@
 #define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
 #define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
 #define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
 /**
   * @}
   */
@@ -1014,7 +1021,7 @@
 /**
   * @}
   */
-
+  
 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
   * @{
   */
@@ -1450,7 +1457,7 @@
 #define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
 #define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
 
-#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
 
 #define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
 #define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
@@ -1472,7 +1479,7 @@
 #define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
 #define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
 
-#endif  /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */
+#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
 /**
   * @}
   */
@@ -1531,18 +1538,18 @@
 
 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
 
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
 #define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
 #define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
 #define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
 #define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
 #define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
 #define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
 #define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
 
 #if defined(STM32F4)
 #define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
@@ -3243,9 +3250,8 @@
 #define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
 #define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
 
-#if defined(STM32L4)
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5)
 #define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
-#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
 #else
 #define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
 #endif
@@ -3373,7 +3379,7 @@
 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
   * @{
   */
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)
 #else
 #define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
 #endif
@@ -3751,7 +3757,7 @@
 /** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
   * @{
   */
-#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7)
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
 #endif /* STM32L4 || STM32F4 || STM32F7 */
 /**

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal.h

@@ -28,7 +28,6 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32mp1xx_hal_conf.h"
-#include <stddef.h>
 
 /** @addtogroup STM32MP1xx_HAL_Driver
  * @{

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc.h

@@ -117,8 +117,8 @@ typedef struct
                                        This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
                                        for low frequency applications.
                                        This parameter can be set to ENABLE or DISABLE.
-                                       Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
-                                             to free the IRQ vector sequencer.
+                                       Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
+                                             Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
                                              Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
                                              use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
                                              (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
@@ -152,7 +152,7 @@ typedef struct
                                        If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
                                        This parameter can be a value of @ref ADC_regular_external_trigger_edge */
 
-  uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register.
+  uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transferred to DFSDM register.
                                        Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
                                        This parameter can be a value of @ref ADC_ConversionDataManagement.
                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups
@@ -334,7 +334,7 @@ typedef struct
                                                               external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
 #define HAL_ADC_STATE_REG_EOC           (0x00000200UL)   /*!< Conversion data available on group regular */
 #define HAL_ADC_STATE_REG_OVR           (0x00000400UL)   /*!< Overrun occurrence */
-#define HAL_ADC_STATE_REG_EOSMP         (0x00000800UL)   /*!< Not available on this STM32 serie: End Of Sampling flag raised  */
+#define HAL_ADC_STATE_REG_EOSMP         (0x00000800UL)   /*!< Not available on this STM32 series: End Of Sampling flag raised  */
 
 /* States of ADC group injected */
 #define HAL_ADC_STATE_INJ_BUSY          (0x00001000UL)   /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
@@ -361,7 +361,7 @@ typedef struct
 typedef struct __ADC_HandleTypeDef
 #else
 typedef struct
-#endif
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
 {
   ADC_TypeDef                   *Instance;              /*!< Register base address */
   ADC_InitTypeDef               Init;                   /*!< ADC initialization parameters and regular conversions setting */
@@ -715,7 +715,6 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   * @}
   */
 
-
 /** @defgroup ADC_Event_type ADC Event type
   * @{
   */
@@ -813,10 +812,10 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   * @param __HANDLE__ ADC handle
   * @retval SET (ADC enabled) or RESET (ADC disabled)
   */
-#define ADC_IS_ENABLE(__HANDLE__)                                                    \
-       (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
-          ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
-        ) ? SET : RESET)
+#define ADC_IS_ENABLE(__HANDLE__)                                                     \
+  ((((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
+    ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \
+   ) ? SET : RESET)
 
 /**
   * @brief Check if conversion is on going on regular group.
@@ -1063,7 +1062,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 #else
 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
   ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-#endif
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
 
 /**
   * @brief Enable ADC interrupt.
@@ -1214,7 +1213,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   *         @arg @ref ADC_CHANNEL_VBAT         (1)
   *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
   *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
-  *         
+  *
   *         (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
   *         (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
   *             Other channels are slow channels (conversion rate: refer to reference manual).
@@ -1257,7 +1256,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   *         @arg @ref ADC_CHANNEL_VBAT         (1)
   *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
   *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
-  *         
+  *
   *         (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
   *         (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
   *             Other channels are slow channels (conversion rate: refer to reference manual).\n
@@ -1312,7 +1311,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   *         @arg @ref ADC_CHANNEL_VBAT         (1)
   *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
   *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
-  *         
+  *
   *         (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
   *         (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
   *             Other channels are slow channels (conversion rate: refer to reference manual).
@@ -1362,7 +1361,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   *         @arg @ref ADC_CHANNEL_VBAT         (1)
   *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
   *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
-  *         
+  *
   *         (1) On STM32MP1, parameter available only on ADC instance: ADC2.\n
   *         (3) On STM32MP1, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).
   *             Other channels are slow channels (conversion rate: refer to reference manual).
@@ -1411,7 +1410,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   *         @arg @ref ADC_CHANNEL_VBAT         (1)
   *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (1)
   *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (1)
-  *         
+  *
   *         (1) On STM32MP1, parameter available only on ADC instance: ADC2.
   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
   *         Value "1" if the internal channel selected is available on the ADC instance selected.
@@ -1435,7 +1434,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   */
 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \
   __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
-#endif
+#endif /* ADC_MULTIMODE_SUPPORT */
 
 /**
   * @brief  Helper macro to select the ADC common instance
@@ -1509,10 +1508,10 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   */
 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
                                           __ADC_RESOLUTION_CURRENT__,\
-                                          __ADC_RESOLUTION_TARGET__)            \
-  __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),                                  \
-                                   (__ADC_RESOLUTION_CURRENT__),                \
-                                   (__ADC_RESOLUTION_TARGET__))
+                                          __ADC_RESOLUTION_TARGET__) \
+__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
+                                 (__ADC_RESOLUTION_CURRENT__),\
+                                 (__ADC_RESOLUTION_TARGET__))
 
 /**
   * @brief  Helper macro to calculate the voltage (unit: mVolt)
@@ -1533,10 +1532,10 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   */
 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
                                        __ADC_DATA__,\
-                                       __ADC_RESOLUTION__)                     \
-  __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),                      \
-                                (__ADC_DATA__),                                \
-                                (__ADC_RESOLUTION__))
+                                       __ADC_RESOLUTION__) \
+__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
+                              (__ADC_DATA__),\
+                              (__ADC_RESOLUTION__))
 
 /**
   * @brief  Helper macro to calculate analog reference voltage (Vref+)
@@ -1548,7 +1547,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   *         connected to pin Vref+.
   *         On devices with small package, the pin Vref+ is not present
   *         and internally bonded to pin Vdda.
-  * @note   On this STM32 serie, calibration data of internal voltage reference
+  * @note   On this STM32 series, calibration data of internal voltage reference
   *         VrefInt corresponds to a resolution of 12 bits,
   *         this is the recommended ADC resolution to convert voltage of
   *         internal voltage reference VrefInt.
@@ -1565,9 +1564,9 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   * @retval Analog reference voltage (unit: mV)
   */
 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
-                                          __ADC_RESOLUTION__)                  \
-  __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),                     \
-                                  (__ADC_RESOLUTION__))
+                                          __ADC_RESOLUTION__) \
+__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
+                                 (__ADC_RESOLUTION__))
 
 /**
   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
@@ -1596,7 +1595,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   * @note   Analog reference voltage (Vref+) must be either known from
   *         user board environment or can be calculated using ADC measurement
   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
-  * @note   On this STM32 serie, calibration data of temperature sensor
+  * @note   On this STM32 series, calibration data of temperature sensor
   *         corresponds to a resolution of 12 bits,
   *         this is the recommended ADC resolution to convert voltage of
   *         temperature sensor.
@@ -1617,10 +1616,10 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   */
 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
                                    __TEMPSENSOR_ADC_DATA__,\
-                                   __ADC_RESOLUTION__)                         \
-  __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),                          \
-                            (__TEMPSENSOR_ADC_DATA__),                         \
-                            (__ADC_RESOLUTION__))
+                                   __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
+                          (__TEMPSENSOR_ADC_DATA__),\
+                          (__ADC_RESOLUTION__))
 
 /**
   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
@@ -1672,13 +1671,13 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
                                               __TEMPSENSOR_CALX_TEMP__,\
                                               __VREFANALOG_VOLTAGE__,\
                                               __TEMPSENSOR_ADC_DATA__,\
-                                              __ADC_RESOLUTION__)              \
-  __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),          \
-                                      (__TEMPSENSOR_TYP_CALX_V__),             \
-                                      (__TEMPSENSOR_CALX_TEMP__),              \
-                                      (__VREFANALOG_VOLTAGE__),                \
-                                      (__TEMPSENSOR_ADC_DATA__),               \
-                                      (__ADC_RESOLUTION__))
+                                              __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
+                                     (__TEMPSENSOR_TYP_CALX_V__),\
+                                     (__TEMPSENSOR_CALX_TEMP__),\
+                                     (__VREFANALOG_VOLTAGE__),\
+                                     (__TEMPSENSOR_ADC_DATA__),\
+                                     (__ADC_RESOLUTION__))
 
 /**
   * @}

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_adc_ex.h

@@ -396,7 +396,7 @@ typedef struct
   *         Usage of this macro is not the Standard way of multimode
   *         configuration and can lead to have HAL ADC handles status
   *         misaligned. Usage of this macro must be limited to cases
-  *         mentionned above.
+  *         mentioned above.
   * @param __HANDLE__ ADC handle.
   * @retval None
   */
@@ -439,7 +439,8 @@ typedef struct
   * @param __RANKNB__ Rank number.
   * @retval None
   */
-#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
+#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\
+                                                  & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
 
 /**
   * @brief Configure ADC injected context queue
@@ -509,7 +510,8 @@ typedef struct
   * @param __CALIBRATION_FACTOR__ Calibration factor value.
   * @retval None
   */
-#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
+#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__)\
+                                                       & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
 
 /**
   * @brief Calibration factor in differential mode to be retrieved from calibration register.
@@ -1078,7 +1080,8 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
   * @{
   */
 /* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
+                                                        ADC_InjectionConfTypeDef *sConfigInjected);
 #if defined(ADC_MULTIMODE_SUPPORT)
 HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
 #endif /* ADC_MULTIMODE_SUPPORT */

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_conf_template.h

@@ -58,9 +58,11 @@
 #define HAL_RTC_MODULE_ENABLED
 #define HAL_SAI_MODULE_ENABLED
 #define HAL_SD_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
 #define HAL_SMBUS_MODULE_ENABLED
 #define HAL_SPDIFRX_MODULE_ENABLED
 #define HAL_SPI_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
 #define HAL_TIM_MODULE_ENABLED
 #define HAL_UART_MODULE_ENABLED
 #define HAL_USART_MODULE_ENABLED
@@ -76,6 +78,7 @@
 #define USE_HAL_I2C_REGISTER_CALLBACKS    0u
 #define USE_HAL_RNG_REGISTER_CALLBACKS    0u
 #define USE_HAL_SPI_REGISTER_CALLBACKS    0u
+#define USE_HAL_SRAM_REGISTER_CALLBACKS   0U
 #define USE_HAL_UART_REGISTER_CALLBACKS   0u
 #define USE_HAL_USART_REGISTER_CALLBACKS  0u
 #define USE_HAL_WWDG_REGISTER_CALLBACKS   0u
@@ -291,6 +294,10 @@
  #include "stm32mp1xx_hal_sd.h"
 #endif /* HAL_SD_MODULE_ENABLED */
 
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32mp1xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
 #ifdef HAL_SMBUS_MODULE_ENABLED
  #include "stm32mp1xx_hal_smbus.h"
 #endif /* HAL_SMBUS_MODULE_ENABLED */
@@ -303,6 +310,10 @@
  #include "stm32mp1xx_hal_spi.h"
 #endif /* HAL_SPI_MODULE_ENABLED */
 
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32mp1xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
 #ifdef HAL_TIM_MODULE_ENABLED
  #include "stm32mp1xx_hal_tim.h"
 #endif /* HAL_TIM_MODULE_ENABLED */

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_cryp.h

@@ -64,6 +64,9 @@ typedef struct
   uint32_t HeaderSize;                /*!< The size of header buffer in word  */
   uint32_t *B0;                       /*!< B0 is first authentication block used only  in AES CCM mode */
   uint32_t DataWidthUnit;             /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+  uint32_t KeyIVConfigSkip;            /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
+                                           Vector only once and to skip configuration for consecutive processings.
+                                           This parameter can be a value of @ref CRYP_Configuration_Skip */
 
 } CRYP_ConfigTypeDef;
 
@@ -128,6 +131,13 @@ typedef struct
 
   uint32_t                          Version;          /*!< CRYP1 IP version*/
 
+  uint32_t                          KeyIVConfig;      /*!< CRYP peripheral Key and IV configuration flag, used when
+                                                           configuration can be skipped */
+
+  uint32_t                          SizesSum;         /*!< Sum of successive payloads lengths (in bytes), stored
+                                                           for a single signature computation after several
+                                                           messages processing */
+
 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
   void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);      /*!< CRYP Input FIFO transfer completed callback  */
   void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);     /*!< CRYP Output FIFO transfer completed callback */
@@ -286,6 +296,16 @@ typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< point
   * @}
   */
 
+/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
+  * @{
+  */
+
+#define CRYP_KEYIVCONFIG_ALWAYS        0x00000000U            /*!< Peripheral Key and IV configuration to do systematically */
+#define CRYP_KEYIVCONFIG_ONCE          0x00000001U            /*!< Peripheral Key and IV configuration to do only once      */
+
+/**
+  * @}
+  */
 
 /**
   * @}
@@ -468,6 +488,9 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
                                    ((DATATYPE) == CRYP_DATATYPE_8B) || \
                                    ((DATATYPE) == CRYP_DATATYPE_1B))
 
+#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
+                             ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
+
 /**
   * @}
   */

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_dfsdm.h

@@ -116,12 +116,16 @@ typedef struct
 /** 
   * @brief  DFSDM channel handle structure definition  
   */  
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
 typedef struct __DFSDM_Channel_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
 {
   DFSDM_Channel_TypeDef          *Instance; /*!< DFSDM channel instance */
   DFSDM_Channel_InitTypeDef      Init;      /*!< DFSDM channel init parameters */
   HAL_DFSDM_Channel_StateTypeDef State;     /*!< DFSDM channel state */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
   void (*CkabCallback)      (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */
   void (*ScdCallback)       (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */
   void (*MspInitCallback)   (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */
@@ -129,7 +133,7 @@ typedef struct __DFSDM_Channel_HandleTypeDef
 #endif
 }DFSDM_Channel_HandleTypeDef;
 
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
 /**
   * @brief  DFSDM channel callback ID enumeration definition
   */
@@ -212,7 +216,11 @@ typedef struct
 /** 
   * @brief  DFSDM filter handle structure definition  
   */  
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
 typedef struct __DFSDM_Filter_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */
 {
   DFSDM_Filter_TypeDef          *Instance;           /*!< DFSDM filter instance */
   DFSDM_Filter_InitTypeDef      Init;                /*!< DFSDM filter init parameters */
@@ -227,7 +235,7 @@ typedef struct __DFSDM_Filter_HandleTypeDef
   uint32_t                      InjConvRemaining;    /*!< Injected conversions remaining */
   HAL_DFSDM_Filter_StateTypeDef State;               /*!< DFSDM filter state */
   uint32_t                      ErrorCode;           /*!< DFSDM filter error code */  
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
   void (*AwdCallback)             (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
                                    uint32_t Channel, uint32_t Threshold);               /*!< DFSDM filter analog watchdog callback */
   void (*RegConvCpltCallback)     (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */
@@ -259,7 +267,7 @@ typedef struct
                                  This parameter can be a values combination of @ref DFSDM_BreakSignals */
 }DFSDM_Filter_AwdParamTypeDef;
 
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
 /**
   * @brief  DFSDM filter callback ID enumeration definition
   */
@@ -437,7 +445,7 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  0x00000001U /*!< Overrun occurs during regular conversion */
 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */
 #define DFSDM_FILTER_ERROR_DMA              0x00000003U /*!< DMA error occurs */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
 #define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */
 #endif
 /**
@@ -511,7 +519,7 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
   * @param  __HANDLE__ DFSDM channel handle.
   * @retval None
   */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{                                                      \
                                                                (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \
                                                                (__HANDLE__)->MspInitCallback = NULL;                \
@@ -525,7 +533,7 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
   * @param  __HANDLE__ DFSDM filter handle.
   * @retval None
   */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{                                                     \
                                                               (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \
                                                               (__HANDLE__)->MspInitCallback = NULL;               \
@@ -557,7 +565,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch
 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
 
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
 /* Channel callbacks register/unregister functions ****************************/
 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,
                                                      HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,
@@ -613,7 +621,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filt
 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
 
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
 /* Filter callbacks register/unregister functions ****************************/
 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,
                                                     HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_exti.h

@@ -254,7 +254,8 @@ typedef struct
 #define EXTI_REG_SHIFT                      16u
 #define EXTI_REG1                           (0x00uL << EXTI_REG_SHIFT)
 #define EXTI_REG2                           (0x01uL << EXTI_REG_SHIFT)
-#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2)
+#define EXTI_REG3                           (0x02uL << EXTI_REG_SHIFT)
+#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2 | EXTI_REG3)
 #define EXTI_PIN_MASK                       0x0000001Fu
 
 /**

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_mdma.h

@@ -2,13 +2,11 @@
   ******************************************************************************
   * @file    stm32mp1xx_hal_mdma.h
   * @author  MCD Application Team
-  * @version V0.3.0
-  * @date    9-December-2016
   * @brief   Header file of DMA HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
   * This software component is licensed by ST under BSD 3-Clause license,
@@ -17,11 +15,11 @@
   *                        opensource.org/licenses/BSD-3-Clause
   *
   ******************************************************************************
-  */ 
+  */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32MP1xx_HAL_MDMA_H
-#define __STM32MP1xx_HAL_MDMA_H
+#ifndef STM32MP1xx_HAL_MDMA_H
+#define STM32MP1xx_HAL_MDMA_H
 
 #ifdef __cplusplus
  extern "C" {
@@ -36,131 +34,132 @@
 
 /** @addtogroup MDMA
   * @{
-  */ 
+  */
 
 /* Exported types ------------------------------------------------------------*/
 
 /** @defgroup MDMA_Exported_Types MDMA Exported Types
-  * @brief    MDMA Exported Types 
+  * @brief    MDMA Exported Types
   * @{
   */
 
-/** 
+/**
   * @brief  MDMA Configuration Structure definition
   */
 typedef struct
 {
-  
+
   uint32_t Request;                 /*!< Specifies the MDMA request.
                                         This parameter can be a value of @ref MDMA_Request_selection*/
-                                     
+
   uint32_t TransferTriggerMode;     /*!< Specifies the Trigger Transfer mode : each request triggers a :
-                                         a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer 
-                                         This parameter can be a value of @ref MDMA_Transfer_TriggerMode  */  
-                                     
+                                         a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer
+                                         This parameter can be a value of @ref MDMA_Transfer_TriggerMode  */
+
   uint32_t Priority;                 /*!< Specifies the software priority for the MDMAy channelx.
                                          This parameter can be a value of @ref MDMA_Priority_level */
 
- uint32_t SecureMode;            /*!< Specifies if the MDMA master transactions are done in secure mode.
-                                      This parameter can be a value of @ref MDMA_Secure_Mode */
-                                          
-  uint32_t Endianess;                /*!< Specifies if the MDMA transactions preserve the Little endianess.
-                                         This parameter can be a value of @ref MDMA_Endianess */ 
-                                     
+  uint32_t SecureMode;               /*!< Specifies if the MDMA master transactions are done in secure mode.
+                                         This parameter can be a value of @ref MDMA_Secure_Mode */
+
+  uint32_t Endianness;                /*!< Specifies if the MDMA transactions preserve the Little endianness.
+                                         This parameter can be a value of @ref MDMA_Endianness */
+
   uint32_t SourceInc;                /*!< Specifies if the Source increment mode .
                                          This parameter can be a value of @ref MDMA_Source_increment_mode */
-                                     
+
   uint32_t DestinationInc;           /*!< Specifies if the Destination increment mode .
                                          This parameter can be a value of @ref MDMA_Destination_increment_mode */
-                                     
+
   uint32_t SourceDataSize;           /*!< Specifies the source data size.
                                          This parameter can be a value of @ref MDMA_Source_data_size */
-                                     
+
   uint32_t DestDataSize;             /*!< Specifies the destination data size.
                                           This parameter can be a value of @ref MDMA_Destination_data_size */
-                                       
- 
+
+
   uint32_t DataAlignment;            /*!< Specifies the source to destination Memory data packing/padding mode.
-                                            This parameter can be a value of @ref MDMA_data_Alignment */                                     
+                                            This parameter can be a value of @ref MDMA_data_Alignment */
 
   uint32_t BufferTransferLength;      /*!< Specifies the buffer Transfer Length (number of bytes),
                                           this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/
-  
-  uint32_t SourceBurst;              /*!< Specifies the Burst transfer configuration for the source memory transfers. 
-                                         It specifies the amount of data to be transferred in a single non interruptable 
+
+  uint32_t SourceBurst;              /*!< Specifies the Burst transfer configuration for the source memory transfers.
+                                         It specifies the amount of data to be transferred in a single non interruptable
                                          transaction.
-                                         This parameter can be a value of @ref MDMA_Source_burst 
+                                         This parameter can be a value of @ref MDMA_Source_burst
                                          @note : the burst may be FIXED/INCR based on SourceInc value ,
                                          the BURST must be programmed as to ensure that the burst size will be lower than than
                                          BufferTransferLength */
-                                    
-  uint32_t DestBurst;                 /*!< Specifies the Burst transfer configuration for the destination memory transfers. 
-                                           It specifies the amount of data to be transferred in a single non interruptable 
+
+  uint32_t DestBurst;                 /*!< Specifies the Burst transfer configuration for the destination memory transfers.
+                                           It specifies the amount of data to be transferred in a single non interruptable
                                            transaction.
-                                           This parameter can be a value of @ref MDMA_Destination_burst 
+                                           This parameter can be a value of @ref MDMA_Destination_burst
                                            @note : the burst may be FIXED/INCR based on DestinationInc value ,
                                            the BURST must be programmed as to ensure that the burst size will be lower than than
                                            BufferTransferLength */
-                                     
+
   int32_t SourceBlockAddressOffset;   /*!< this field specifies the Next block source address offset
                                            signed value : if > 0 then  increment the next block source Address by offset from where the last block ends
                                                           if < 0 then  decrement the next block source Address by offset from where the last block ends
                                                           if == 0, the next block source address starts from where the last block ends
-                                       */                                                                            
+                                       */
 
 
   int32_t DestBlockAddressOffset;      /*!< this field specifies the Next block destination address offset
                                            signed value : if > 0 then  increment the next block destination Address by offset from where the last block ends
                                                           if < 0 then  decrement the next block destination Address by offset from where the last block ends
                                                           if == 0, the next block destination address starts from where the last block ends
-                                       */  
-  
+                                       */
+
 }MDMA_InitTypeDef;
 
-/** 
-  * @brief  HAL MDMA linked list node structure definition  
-  * @note   The Linked list node allows to define a new MDMA configuration 
+/**
+  * @brief  HAL MDMA linked list node structure definition
+  * @note   The Linked list node allows to define a new MDMA configuration
   *         (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).
   *         When CLAR register is configured to a non NULL value , each time a transfer ends,
-  *         a new configuration (linked list node) is automatically loaded from the address given in CLAR register.            
+  *         a new configuration (linked list node) is automatically loaded from the address given in CLAR register.
   */
 typedef struct
 {
-  uint32_t CTCR;    /*!< New CTCR register configuration for the given MDMA linked list node   */
-  uint32_t CBNDTR;  /*!< New CBNDTR register configuration for the given MDMA linked list node */
-  uint32_t CSAR;    /*!< New CSAR register configuration for the given MDMA linked list node   */
-  uint32_t CDAR;    /*!< New CDAR register configuration for the given MDMA linked list node   */
-  uint32_t CBRUR;   /*!< New CBRUR register configuration for the given MDMA linked list node  */
-  uint32_t CLAR;    /*!< New CLAR register configuration for the given MDMA linked list node   */
-  uint32_t CTBR;    /*!< New CTBR register configuration for the given MDMA linked list node   */
-  uint32_t CMAR;    /*!< New CMAR register configuration for the given MDMA linked list node   */
-  uint32_t CMDR;    /*!< New CMDR register configuration for the given MDMA linked list node   */  
-  
+  __IO uint32_t CTCR;     /*!< New CTCR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CBNDTR;   /*!< New CBNDTR register configuration for the given MDMA linked list node */
+  __IO uint32_t CSAR;     /*!< New CSAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CDAR;     /*!< New CDAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CBRUR;    /*!< New CBRUR register configuration for the given MDMA linked list node  */
+  __IO uint32_t CLAR;     /*!< New CLAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CTBR;     /*!< New CTBR register configuration for the given MDMA linked list node   */
+  __IO uint32_t Reserved; /*!< Reserved register                                                     */
+  __IO uint32_t CMAR;     /*!< New CMAR register configuration for the given MDMA linked list node   */
+  __IO uint32_t CMDR;     /*!< New CMDR register configuration for the given MDMA linked list node   */
+
 }MDMA_LinkNodeTypeDef;
 
-/** 
-  * @brief  HAL MDMA linked list node configuration structure definition  
-  * @note   used with HAL_MDMA_LinkedList_CreateNode function 
+/**
+  * @brief  HAL MDMA linked list node configuration structure definition
+  * @note   used with HAL_MDMA_LinkedList_CreateNode function
   */
 typedef struct
-{ 
-  MDMA_InitTypeDef Init;            /* !< configuration of the specified MDMA Linked List Node    */
-  uint32_t         SrcAddress;      /* !< The source memory address for the Linked list Node      */
-  uint32_t         DstAddress;      /* !< The destination memory address for the Linked list Node */
-  uint32_t         BlockDataLength; /* !< The length of a block transfer in bytes                 */
-  uint32_t         BlockCount;      /* !< The number of a blocks to be transfer                   */
+{
+  MDMA_InitTypeDef Init;            /*!< configuration of the specified MDMA Linked List Node    */
+  uint32_t         SrcAddress;      /*!< The source memory address for the Linked list Node      */
+  uint32_t         DstAddress;      /*!< The destination memory address for the Linked list Node */
+  uint32_t         BlockDataLength; /*!< The data length of a block in bytes                     */
+  uint32_t         BlockCount;      /*!< The number of blocks to be transferred                  */
 
   uint32_t PostRequestMaskAddress;  /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served.
                                          PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */
 
   uint32_t PostRequestMaskData;     /*!< specifies the value to be written to PostRequestMaskAddress after a request is served.
                                          PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */
-  
-  
+
+
 }MDMA_LinkNodeConfTypeDef;
 
 
-/** 
+/**
   * @brief  HAL MDMA State structure definition
   */
 typedef enum
@@ -168,13 +167,13 @@ typedef enum
   HAL_MDMA_STATE_RESET               = 0x00U,  /*!< MDMA not yet initialized or disabled */
   HAL_MDMA_STATE_READY               = 0x01U,  /*!< MDMA initialized and ready for use   */
   HAL_MDMA_STATE_BUSY                = 0x02U,  /*!< MDMA process is ongoing              */
-  HAL_MDMA_STATE_TIMEOUT             = 0x03U,  /*!< MDMA timeout state                   */
-  HAL_MDMA_STATE_ERROR               = 0x04U,  /*!< MDMA error state                     */
-  HAL_MDMA_STATE_ABORT               = 0x05U,  /*!< DMA Abort state                      */
+  HAL_MDMA_STATE_ERROR               = 0x03U,  /*!< MDMA error state                     */
+  HAL_MDMA_STATE_ABORT               = 0x04U,  /*!< MDMA Abort state                     */
+  HAL_MDMA_STATE_TIMEOUT             = 0x05U,  /*!< MDMA timeout state                   */
 
 }HAL_MDMA_StateTypeDef;
 
-/** 
+/**
   * @brief  HAL MDMA Level Complete structure definition
   */
 typedef enum
@@ -183,10 +182,10 @@ typedef enum
   HAL_MDMA_BUFFER_TRANSFER       = 0x01U,   /*!< Buffer Transfer       */
   HAL_MDMA_BLOCK_TRANSFER        = 0x02U,   /*!< Block Transfer        */
   HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U    /*!< repeat block Transfer */
-  
+
 }HAL_MDMA_LevelCompleteTypeDef;
 
-/** 
+/**
   * @brief  HAL MDMA Callbacks IDs structure definition
   */
 typedef enum
@@ -202,47 +201,46 @@ typedef enum
 }HAL_MDMA_CallbackIDTypeDef;
 
 
-/** 
+/**
   * @brief  MDMA handle Structure definition
   */
 typedef struct __MDMA_HandleTypeDef
 {
   MDMA_Channel_TypeDef *Instance;                                                              /*!< Register base address                  */
-                                                                                                                                      
-  MDMA_InitTypeDef      Init;                                                                  /*!< MDMA communication parameters          */
 
+  MDMA_InitTypeDef      Init;                                                                  /*!< MDMA communication parameters          */
 
   HAL_LockTypeDef       Lock;                                                                  /*!< MDMA locking object                    */
-  
+
   __IO HAL_MDMA_StateTypeDef  State;                                                           /*!< MDMA transfer state                    */
 
   void                  *Parent;                                                               /*!< Parent object state                    */
 
   void                  (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);            /*!< MDMA transfer complete callback        */
-                           
+
   void                  (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);      /*!< MDMA buffer transfer complete callback */
 
   void                  (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);       /*!< MDMA block transfer complete callback  */
-  
+
   void                  (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback    */
 
   void                  (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer error callback           */
 
-  void                  (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer Abort callback           */ 
-  
+  void                  (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer Abort callback           */
 
-  MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress;                                             /*!< specifies the first node address of the transfer list 
+
+  MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress;                                             /*!< specifies the first node address of the transfer list
                                                                                                      (after the initial node defined by the Init struct)
-                                                                                                    this parameter is used internally by the MDMA driver
-                                                                                                     to construct the liked list node
+                                                                                                     this parameter is used internally by the MDMA driver
+                                                                                                     to construct the linked list node
                                                                                                 */
 
   MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress;                                             /*!< specifies the last node address of the transfer list
                                                                                                     this parameter is used internally by the MDMA driver
-                                                                                                     to construct the liked list node
+                                                                                                    to construct the linked list node
                                                                                                 */
-  uint32_t LinkedListNodeCounter;                                                               /*!< Number of nodes in the MDMA linked list */ 
-                                                                                                                                      
+  uint32_t LinkedListNodeCounter;                                                               /*!< Number of nodes in the MDMA linked list */
+
   __IO uint32_t          ErrorCode;                                                            /*!< MDMA Error code                        */
 
 } MDMA_HandleTypeDef;
@@ -254,14 +252,14 @@ typedef struct __MDMA_HandleTypeDef
 /* Exported constants --------------------------------------------------------*/
 
 /** @defgroup MDMA_Exported_Constants MDMA Exported Constants
-  * @brief    MDMA Exported constants 
+  * @brief    MDMA Exported constants
   * @{
   */
 
 /** @defgroup MDMA_Error_Codes MDMA Error Codes
-  * @brief    MDMA Error Codes 
+  * @brief    MDMA Error Codes
   * @{
-  */ 
+  */
 #define HAL_MDMA_ERROR_NONE        ((uint32_t)0x00000000U)   /*!< No error                               */
 #define HAL_MDMA_ERROR_READ_XFER   ((uint32_t)0x00000001U)   /*!< Read Transfer error                    */
 #define HAL_MDMA_ERROR_WRITE_XFER  ((uint32_t)0x00000002U)   /*!< Write Transfer error                   */
@@ -270,9 +268,9 @@ typedef struct __MDMA_HandleTypeDef
 #define HAL_MDMA_ERROR_ALIGNMENT   ((uint32_t)0x00000010U)   /*!< Address/Size alignment  error          */
 #define HAL_MDMA_ERROR_BLOCK_SIZE  ((uint32_t)0x00000020U)   /*!< Block Size error                       */
 #define HAL_MDMA_ERROR_TIMEOUT     ((uint32_t)0x00000040U)   /*!< Timeout error                          */
-#define HAL_MDMA_ERROR_NO_XFER     ((uint32_t)0x00000080U)   /*!< Abort or SW trigger requested with no Xfer ongoing   */ 
-#define HAL_MDMA_ERROR_BUSY        ((uint32_t)0x00000100U)   /*!< DeInit or SW trigger requested with Xfer ongoing   */ 
-    
+#define HAL_MDMA_ERROR_NO_XFER     ((uint32_t)0x00000080U)   /*!< Abort or SW trigger requested with no Xfer ongoing   */
+#define HAL_MDMA_ERROR_BUSY        ((uint32_t)0x00000100U)   /*!< DeInit or SW trigger requested with Xfer ongoing   */
+
 /**
   * @}
   */
@@ -316,7 +314,6 @@ typedef struct __MDMA_HandleTypeDef
 #define MDMA_REQUEST_I2C6_RX              ((uint32_t)0x00000026U)  /*!< MDMA HW request is I2C6 Rx Transfer Complete Flag         */
 #define MDMA_REQUEST_I2C6_TX              ((uint32_t)0x00000027U)  /*!< MDMA HW request is I2C6 Tx Transfer Complete Flag         */
 #define MDMA_REQUEST_SW                   ((uint32_t)0x40000000U) /*!< MDMA SW request   */
-
 /**
   * @}
   */
@@ -325,12 +322,12 @@ typedef struct __MDMA_HandleTypeDef
   * @brief    MDMA Transfer Trigger Mode
   * @{
   */
-#define MDMA_BUFFER_TRANSFER          ((uint32_t)0x00000000U)        /*!< Each MDMA request (SW or HW) triggers a buffer transfer */  
-#define MDMA_BLOCK_TRANSFER           ((uint32_t)MDMA_CTCR_TRGM_0)   /*!< Each MDMA request (SW or HW) triggers a block transfer */ 
-#define MDMA_REPEAT_BLOCK_TRANSFER    ((uint32_t)MDMA_CTCR_TRGM_1)   /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */ 
+#define MDMA_BUFFER_TRANSFER          ((uint32_t)0x00000000U)        /*!< Each MDMA request (SW or HW) triggers a buffer transfer                                */
+#define MDMA_BLOCK_TRANSFER           ((uint32_t)MDMA_CTCR_TRGM_0)   /*!< Each MDMA request (SW or HW) triggers a block transfer                                 */
+#define MDMA_REPEAT_BLOCK_TRANSFER    ((uint32_t)MDMA_CTCR_TRGM_1)   /*!< Each MDMA request (SW or HW) triggers a repeated block transfer                        */
 #define MDMA_FULL_TRANSFER            ((uint32_t)MDMA_CTCR_TRGM)     /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
 
-/**                                 
+/**
   * @}
   */
 
@@ -345,8 +342,8 @@ typedef struct __MDMA_HandleTypeDef
 
 /**
   * @}
-  */ 
-  
+  */
+
 /** @defgroup MDMA_Secure_Mode MDMA Secure Mode
   * @brief    MDMA Secure Mode
   * @{
@@ -358,64 +355,64 @@ typedef struct __MDMA_HandleTypeDef
   * @}
   */
 
-/** @defgroup MDMA_Endianess MDMA Endianess
-  * @brief    MDMA Endianess
+/** @defgroup MDMA_Endianness MDMA Endianness
+  * @brief    MDMA Endianness
   * @{
   */
-#define MDMA_LITTLE_ENDIANESS_PRESERVE          ((uint32_t)0x00000000U)   /*!< little endianess preserve    */
-#define MDMA_LITTLE_BYTE_ENDIANESS_EXCHANGE     ((uint32_t)MDMA_CCR_BEX)  /*!< BYTEs endianess exchange when destination data size is > Byte  */
-#define MDMA_LITTLE_HALFWORD_ENDIANESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)  /*!< HALF WORDs endianess exchange when destination data size is > HALF WORD*/
-#define MDMA_LITTLE_WORD_ENDIANESS_EXCHANGE     ((uint32_t)MDMA_CCR_WEX)  /*!< WORDs endianess exchange  when destination data size is > DOUBLE WORD */
+#define MDMA_LITTLE_ENDIANNESS_PRESERVE          ((uint32_t)0x00000000U)   /*!< little endianness preserve                                               */
+#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_BEX)  /*!< BYTEs endianness exchange when destination data size is > Byte           */
+#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)  /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */
+#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_WEX)  /*!< WORDs endianness exchange  when destination data size is > DOUBLE WORD   */
 
 /**
   * @}
   */
-  
+
 /** @defgroup MDMA_Source_increment_mode MDMA Source increment mode
   * @brief    MDMA Source increment mode
   * @{
   */
-#define MDMA_SRC_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed */
-#define MDMA_SRC_INC_BYTE         ((uint32_t)MDMA_CTCR_SINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)*/
-#define MDMA_SRC_INC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
-#define MDMA_SRC_INC_WORD         ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
+#define MDMA_SRC_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */
+#define MDMA_SRC_INC_BYTE         ((uint32_t)MDMA_CTCR_SINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */
+#define MDMA_SRC_INC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */
+#define MDMA_SRC_INC_WORD         ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */
 #define MDMA_SRC_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
-#define MDMA_SRC_DEC_BYTE         ((uint32_t)MDMA_CTCR_SINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)*/
-#define MDMA_SRC_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits) */
-#define MDMA_SRC_DEC_WORD         ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)*/
+#define MDMA_SRC_DEC_BYTE         ((uint32_t)MDMA_CTCR_SINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */
+#define MDMA_SRC_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */
+#define MDMA_SRC_DEC_WORD         ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */
 #define MDMA_SRC_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
 
 /**
   * @}
-  */ 
-  
+  */
+
 /** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode
   * @brief    MDMA Destination increment mode
   * @{
   */
-#define MDMA_DEST_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed */
-#define MDMA_DEST_INC_BYTE         ((uint32_t)MDMA_CTCR_DINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)*/
-#define MDMA_DEST_INC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
-#define MDMA_DEST_INC_WORD         ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
+#define MDMA_DEST_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */
+#define MDMA_DEST_INC_BYTE         ((uint32_t)MDMA_CTCR_DINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */
+#define MDMA_DEST_INC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */
+#define MDMA_DEST_INC_WORD         ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */
 #define MDMA_DEST_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
-#define MDMA_DEST_DEC_BYTE         ((uint32_t)MDMA_CTCR_DINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)*/
-#define MDMA_DEST_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits) */
-#define MDMA_DEST_DEC_WORD         ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)*/
+#define MDMA_DEST_DEC_BYTE         ((uint32_t)MDMA_CTCR_DINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */
+#define MDMA_DEST_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */
+#define MDMA_DEST_DEC_WORD         ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */
 #define MDMA_DEST_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
 
 /**
   * @}
-  */ 
-  
+  */
+
 /** @defgroup MDMA_Source_data_size MDMA Source data size
   * @brief    MDMA Source data size
   * @{
   */
-#define MDMA_SRC_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Source data size is Byte */
-#define MDMA_SRC_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_SSIZE_0)   /*!< Source data size is half word */  
-#define MDMA_SRC_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_SSIZE_1)   /*!< Source data size is word */ 
+#define MDMA_SRC_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Source data size is Byte        */
+#define MDMA_SRC_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_SSIZE_0)   /*!< Source data size is half word   */
+#define MDMA_SRC_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_SSIZE_1)   /*!< Source data size is word        */
 #define MDMA_SRC_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_SSIZE)     /*!< Source data size is double word */
- 
+
 /**
   * @}
   */
@@ -424,88 +421,88 @@ typedef struct __MDMA_HandleTypeDef
   * @brief    MDMA Destination data size
   * @{
   */
-#define MDMA_DEST_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Destination data size is Byte */
-#define MDMA_DEST_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_DSIZE_0)   /*!< Destination data size is half word */  
-#define MDMA_DEST_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_DSIZE_1)   /*!< Destination data size is word */ 
+#define MDMA_DEST_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Destination data size is Byte        */
+#define MDMA_DEST_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_DSIZE_0)   /*!< Destination data size is half word   */
+#define MDMA_DEST_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_DSIZE_1)   /*!< Destination data size is word        */
 #define MDMA_DEST_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_DSIZE)     /*!< Destination data size is double word */
- 
+
 /**
   * @}
   */
 
 /** @defgroup MDMA_data_Alignment MDMA data alignment
-  * @brief    MDMA MDMA data alignment
+  * @brief    MDMA data alignment
   * @{
   */
 #define MDMA_DATAALIGN_PACKENABLE        ((uint32_t)MDMA_CTCR_PKE)     /*!< The source data is packed/un-packed into the destination data size
-                                                                            All data are right aligned, in Little Endien mode. */   
-#define MDMA_DATAALIGN_RIGHT            ((uint32_t)0x00000000U)        /*!< Right Aligned, padded w/ 0s (default) */                       
-#define MDMA_DATAALIGN_RIGHT_SIGNED     ((uint32_t)MDMA_CTCR_PAM_0)    /*!< Right Aligned, Sign extended , 
-                                                                            Note : this mode is allowed only if the Source data size smaller than Destination data size  */ 
-#define MDMA_DATAALIGN_LEFT             ((uint32_t)MDMA_CTCR_PAM_1)    /*!< Left Aligned (padded with 0s) */  
- 
+                                                                            All data are right aligned, in Little Endien mode.                                              */
+#define MDMA_DATAALIGN_RIGHT            ((uint32_t)0x00000000U)        /*!< Right Aligned, padded w/ 0s (default)                                                           */
+#define MDMA_DATAALIGN_RIGHT_SIGNED     ((uint32_t)MDMA_CTCR_PAM_0)    /*!< Right Aligned, Sign extended ,
+                                                                            Note : this mode is allowed only if the Source data size is smaller than Destination data size  */
+#define MDMA_DATAALIGN_LEFT             ((uint32_t)MDMA_CTCR_PAM_1)    /*!< Left Aligned (padded with 0s)                                                                   */
+
 /**
   * @}
   */
- 
+
 /** @defgroup MDMA_Source_burst MDMA Source burst
   * @brief    MDMA Source burst
   * @{
   */
-#define MDMA_SOURCE_BURST_SINGLE        ((uint32_t)0x00000000U)                                       /*!< single transfer */ 
-#define MDMA_SOURCE_BURST_2BEATS        ((uint32_t)MDMA_CTCR_SBURST_0)                                /*!< Burst 2 beats */ 
-#define MDMA_SOURCE_BURST_4BEATS        ((uint32_t)MDMA_CTCR_SBURST_1)                                /*!< Burst 4 beats */
-#define MDMA_SOURCE_BURST_8BEATS        ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */
-#define MDMA_SOURCE_BURST_16BEATS       ((uint32_t)MDMA_CTCR_SBURST_2)                                /*!< Burst 16 beats */
-#define MDMA_SOURCE_BURST_32BEATS       ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */
-#define MDMA_SOURCE_BURST_64BEATS       ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */
-#define MDMA_SOURCE_BURST_128BEATS      ((uint32_t)MDMA_CTCR_SBURST)                                  /*!< Burst 128 beats */                                                                                                      
- 
+#define MDMA_SOURCE_BURST_SINGLE        ((uint32_t)0x00000000U)                                       /*!< single transfer */
+#define MDMA_SOURCE_BURST_2BEATS        ((uint32_t)MDMA_CTCR_SBURST_0)                                /*!< Burst 2 beats   */
+#define MDMA_SOURCE_BURST_4BEATS        ((uint32_t)MDMA_CTCR_SBURST_1)                                /*!< Burst 4 beats   */
+#define MDMA_SOURCE_BURST_8BEATS        ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats   */
+#define MDMA_SOURCE_BURST_16BEATS       ((uint32_t)MDMA_CTCR_SBURST_2)                                /*!< Burst 16 beats  */
+#define MDMA_SOURCE_BURST_32BEATS       ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats  */
+#define MDMA_SOURCE_BURST_64BEATS       ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats  */
+#define MDMA_SOURCE_BURST_128BEATS      ((uint32_t)MDMA_CTCR_SBURST)                                  /*!< Burst 128 beats */
+
 /**
   * @}
   */
- 
+
 /** @defgroup MDMA_Destination_burst MDMA Destination burst
   * @brief    MDMA Destination burst
   * @{
   */
-#define MDMA_DEST_BURST_SINGLE        ((uint32_t)0x00000000U)                                        /*!< single transfer */ 
-#define MDMA_DEST_BURST_2BEATS        ((uint32_t)MDMA_CTCR_DBURST_0)                                 /*!< Burst 2 beats */ 
-#define MDMA_DEST_BURST_4BEATS        ((uint32_t)MDMA_CTCR_DBURST_1)                                 /*!< Burst 4 beats */
-#define MDMA_DEST_BURST_8BEATS        ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)  /*!< Burst 8 beats */
-#define MDMA_DEST_BURST_16BEATS       ((uint32_t)MDMA_CTCR_DBURST_2)                                 /*!< Burst 16 beats */
-#define MDMA_DEST_BURST_32BEATS       ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 32 beats */
-#define MDMA_DEST_BURST_64BEATS       ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 64 beats */
-#define MDMA_DEST_BURST_128BEATS      ((uint32_t)MDMA_CTCR_DBURST)                                   /*!< Burst 128 beats */                                                                                                    
+#define MDMA_DEST_BURST_SINGLE        ((uint32_t)0x00000000U)                                        /*!< single transfer */
+#define MDMA_DEST_BURST_2BEATS        ((uint32_t)MDMA_CTCR_DBURST_0)                                 /*!< Burst 2 beats   */
+#define MDMA_DEST_BURST_4BEATS        ((uint32_t)MDMA_CTCR_DBURST_1)                                 /*!< Burst 4 beats   */
+#define MDMA_DEST_BURST_8BEATS        ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)  /*!< Burst 8 beats   */
+#define MDMA_DEST_BURST_16BEATS       ((uint32_t)MDMA_CTCR_DBURST_2)                                 /*!< Burst 16 beats  */
+#define MDMA_DEST_BURST_32BEATS       ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 32 beats  */
+#define MDMA_DEST_BURST_64BEATS       ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 64 beats  */
+#define MDMA_DEST_BURST_128BEATS      ((uint32_t)MDMA_CTCR_DBURST)                                   /*!< Burst 128 beats */
 
 /**
   * @}
   */
-  
+
 /** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions
   * @brief    MDMA interrupt enable definitions
   * @{
   */
-#define MDMA_IT_TE   ((uint32_t)MDMA_CCR_TEIE)   /*!< Transfer Error interrupt */
+#define MDMA_IT_TE   ((uint32_t)MDMA_CCR_TEIE)   /*!< Transfer Error interrupt            */
 #define MDMA_IT_CTC  ((uint32_t)MDMA_CCR_CTCIE)  /*!< Channel Transfer Complete interrupt */
-#define MDMA_IT_BRT  ((uint32_t)MDMA_CCR_BRTIE)  /*!< Block Repeat Transfer interrupt */
-#define MDMA_IT_BT   ((uint32_t)MDMA_CCR_BTIE)   /*!< Block Transfer interrupt */
-#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)   /*!< Buffer Transfer Complete interrupt */
+#define MDMA_IT_BRT  ((uint32_t)MDMA_CCR_BRTIE)  /*!< Block Repeat Transfer interrupt     */
+#define MDMA_IT_BT   ((uint32_t)MDMA_CCR_BTIE)   /*!< Block Transfer interrupt            */
+#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)   /*!< Buffer Transfer Complete interrupt  */
 
 /**
   * @}
-  */ 
- 
+  */
+
 /** @defgroup MDMA_flag_definitions MDMA flag definitions
   * @brief    MDMA flag definitions
   * @{
   */
-#define MDMA_FLAG_TE    ((uint32_t)MDMA_CISR_TEIF)  /*!< Transfer Error flag    */
-#define MDMA_FLAG_CTC   ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */
+#define MDMA_FLAG_TE    ((uint32_t)MDMA_CISR_TEIF)  /*!< Transfer Error flag                 */
+#define MDMA_FLAG_CTC   ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag      */
 #define MDMA_FLAG_BRT   ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
-#define MDMA_FLAG_BT    ((uint32_t)MDMA_CISR_BTIF)  /*!< Block Transfer complete flag */
-#define MDMA_FLAG_BFTC  ((uint32_t)MDMA_CISR_TCIF)  /*!< BuFfer Transfer complete flag */
-#define MDMA_FLAG_CRQA  ((uint32_t)MDMA_CISR_CRQA)  /*!< Channel ReQest Active flag */
+#define MDMA_FLAG_BT    ((uint32_t)MDMA_CISR_BTIF)  /*!< Block Transfer complete flag        */
+#define MDMA_FLAG_BFTC  ((uint32_t)MDMA_CISR_TCIF)  /*!< BuFfer Transfer complete flag       */
+#define MDMA_FLAG_CRQA  ((uint32_t)MDMA_CISR_CRQA)  /*!< Channel ReQest Active flag          */
 
 /**
   * @}
@@ -527,9 +524,9 @@ typedef struct __MDMA_HandleTypeDef
   * @retval None
   */
 #define __HAL_MDMA_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR |=  MDMA_CCR_EN)
- 
+
 /**
-  * @brief  Disable the specified DMA Channel.
+  * @brief  Disable the specified MDMA Channel.
   * @param  __HANDLE__: MDMA handle
   * @retval None
   */
@@ -545,10 +542,10 @@ typedef struct __MDMA_HandleTypeDef
   *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.
   *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.
   *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
-  *            @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.  
+  *            @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.
   * @retval The state of FLAG (SET or RESET).
   */
-#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->CISR & (__FLAG__)) 
+#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->CISR & (__FLAG__))
 
 /**
   * @brief  Clear the MDMA Stream pending flags.
@@ -559,21 +556,21 @@ typedef struct __MDMA_HandleTypeDef
   *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.
   *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.
   *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.
-  *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.  
+  *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
   * @retval None
   */
 #define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
 
 /**
-  * @brief  Enables the specified DMA Channel interrupts.
+  * @brief  Enables the specified MDMA Channel interrupts.
   * @param  __HANDLE__: MDMA handle
-  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
+  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
   *          This parameter can be any combination of the following values:
   *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
   *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
   *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
   *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
-  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask 
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
   * @retval None
   */
 #define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
@@ -581,34 +578,49 @@ typedef struct __MDMA_HandleTypeDef
 /**
   * @brief  Disables the specified MDMA Channel interrupts.
   * @param  __HANDLE__: MDMA handle
-  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
+  * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled.
   *          This parameter can be any combination of the following values:
   *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
   *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
   *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
   *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
-  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask                            
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
   * @retval None
   */
 #define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
 
 /**
   * @brief  Checks whether the specified MDMA Channel interrupt is enabled or not.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  * @param  __HANDLE__: MDMA handle
+  * @param  __INTERRUPT__: specifies the MDMA interrupt source to check.
   *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask
   *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask
   *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask
   *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask
-  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask 
+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask
   * @retval The state of MDMA_IT (SET or RESET).
   */
 #define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
 
+/**
+  * @brief  Writes the number of data in bytes to be transferred on the MDMA Channelx.
+  * @param  __HANDLE__ : MDMA handle
+  * @param  __COUNTER__: Number of data in bytes to be transferred.
+  * @retval None
+  */
+#define __HAL_MDMA_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CBNDTR |= ((__COUNTER__) & MDMA_CBNDTR_BNDT))
+
+/**
+  * @brief  Returns the number of remaining data in bytes in the current MDMA Channelx transfer.
+  * @param  __HANDLE__ : MDMA handle
+  * @retval The number of remaining data in bytes in the current MDMA Channelx transfer.
+  */
+#define __HAL_MDMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CBNDTR & MDMA_CBNDTR_BNDT)
+
 /**
   * @}
   */
-  
+
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup MDMA_Exported_Functions  MDMA Exported Functions
   * @{
@@ -616,7 +628,7 @@ typedef struct __MDMA_HandleTypeDef
 
 /* Initialization and de-initialization functions *****************************/
 /** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @brief   Initialization and de-initialization functions 
+  * @brief   Initialization and de-initialization functions
   * @{
   */
 HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma);
@@ -628,43 +640,45 @@ HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDM
 
 /**
   * @}
-  */ 
+  */
 
 /* Linked list operation functions ********************************************/
 /** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions
-  * @brief   Linked list operation functions  
+  * @brief   Linked list operation functions
   * @{
   */
 
 HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);
 HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode);
 HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma);
+HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma);
 
 
 /**
   * @}
-  */ 
+  */
 
 /* IO operation functions *****************************************************/
 /** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions
-  * @brief   I/O operation functions  
+  * @brief   I/O operation functions
   * @{
   */
 HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
 HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
 HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma);
 HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma);
-HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, uint32_t CompleteLevel, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
 HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma);
 void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma);
 
 /**
   * @}
-  */ 
+  */
 
 /* Peripheral State and Error functions ***************************************/
 /** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions
-  * @brief    Peripheral State functions 
+  * @brief    Peripheral State functions
   * @{
   */
 HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma);
@@ -672,13 +686,14 @@ uint32_t              HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
 
 void HAL_MDMA_MspInit(MDMA_HandleTypeDef *hmdma);
 void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma);
+
 /**
   * @}
   */
 
 /**
   * @}
-  */ 
+  */
 
 /* Private types -------------------------------------------------------------*/
 /** @defgroup MDMA_Private_Types MDMA Private Types
@@ -687,7 +702,7 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma);
 
 /**
   * @}
-  */ 
+  */
 
 /* Private defines -----------------------------------------------------------*/
 /** @defgroup MDMA_Private_Defines MDMA Private Defines
@@ -696,8 +711,8 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma);
 
 /**
   * @}
-  */ 
-          
+  */
+
 /* Private variables ---------------------------------------------------------*/
 /** @defgroup MDMA_Private_Variables MDMA Private Variables
   * @{
@@ -705,7 +720,7 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma);
 
 /**
   * @}
-  */ 
+  */
 
 /* Private constants ---------------------------------------------------------*/
 /** @defgroup MDMA_Private_Constants MDMA Private Constants
@@ -714,36 +729,30 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma);
 
 /**
   * @}
-  */ 
+  */
 
 /* Private macros ------------------------------------------------------------*/
 /** @defgroup MDMA_Private_Macros MDMA Private Macros
   * @{
   */
 
-/** @defgroup MDMA_IS_Definitions MDMA Private macros to check input parameters
-  * @{
-  */
-
 #define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER )  || \
                                            ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \
                                            ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \
                                            ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))
 
 
-#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW )  || \
-                                       ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
-                                       ((__PRIORITY__) == MDMA_PRIORITY_HIGH)   || \
-                                       ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
+#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW )   || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_HIGH)   || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
 
 #define IS_MDMA_SECURE_MODE(__SECURE_MODE__) (((__SECURE_MODE__) == MDMA_SECURE_MODE_DISABLE ) || \
                                               ((__SECURE_MODE__) == MDMA_SECURE_MODE_ENABLE))
-
-#define IS_MDMA_ENDIANESS_MODE(__ENDIANESS__) (((__ENDIANESS__) == MDMA_LITTLE_ENDIANESS_PRESERVE )        || \
-                                              ((__ENDIANESS__) == MDMA_LITTLE_BYTE_ENDIANESS_EXCHANGE)     || \
-                                              ((__ENDIANESS__) == MDMA_LITTLE_HALFWORD_ENDIANESS_EXCHANGE) || \
-                                              ((__ENDIANESS__) == MDMA_LITTLE_WORD_ENDIANESS_EXCHANGE))
-
+#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE )         || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE)     || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
 
 #define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_I2C6_TX))
 
@@ -778,9 +787,9 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma);
                                                 ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))
 
 #define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE )    || \
-                                                 ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT )         || \
-                                                 ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED )  || \
-                                                 ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT )         || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED )  || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
 
 
 #define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
@@ -792,7 +801,7 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma);
                                          ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \
                                          ((__BURST__) == MDMA_SOURCE_BURST_128BEATS))
 
- 
+
 #define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \
                                               ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \
                                               ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \
@@ -803,25 +812,21 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma);
                                               ((__BURST__) == MDMA_DEST_BURST_128BEATS))
 
  #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER )      || \
-                                         ((__MODE__) == MDMA_BLOCK_TRANSFER )        || \
-                                         ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
-                                         ((__MODE__) == MDMA_FULL_TRANSFER))
+                                                  ((__MODE__) == MDMA_BLOCK_TRANSFER )        || \
+                                                  ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
+                                                  ((__MODE__) == MDMA_FULL_TRANSFER))
 
-#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001) && ((__LENGTH__) < 0x000000FF))
+#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU))
 
-#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0 ) && ((__COUNT__) <= 4096))
+#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U))
 
-#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0) && ((SIZE) <= 65536))
+#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U))
 
 #define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))
 
 /**
   * @}
-  */ 
-
-/**
-  * @}
-  */ 
+  */
 
 /* Private functions prototypes ----------------------------------------------*/
 /** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes
@@ -853,6 +858,6 @@ void HAL_MDMA_MspDeInit(MDMA_HandleTypeDef *hmdma);
 }
 #endif
 
-#endif /* __STM32MP1xx_HAL_MDMA_H */
+#endif /* STM32MP1xx_HAL_MDMA_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rcc_ex.h

@@ -355,10 +355,10 @@ typedef struct
 /** @defgroup RCCEx_I2C12_Clock_Source  I2C12 Clock Source
   * @{
   */
-#define RCC_I2C12CLKSOURCE_PCLK1        RCC_I2C12CKSELR_I2C12SRC_0
-#define RCC_I2C12CLKSOURCE_PLL4         RCC_I2C12CKSELR_I2C12SRC_1
-#define RCC_I2C12CLKSOURCE_HSI          RCC_I2C12CKSELR_I2C12SRC_2
-#define RCC_I2C12CLKSOURCE_CSI          RCC_I2C12CKSELR_I2C12SRC_3
+#define RCC_I2C12CLKSOURCE_PCLK1        0U
+#define RCC_I2C12CLKSOURCE_PLL4         RCC_I2C12CKSELR_I2C12SRC_0
+#define RCC_I2C12CLKSOURCE_HSI          RCC_I2C12CKSELR_I2C12SRC_1
+#define RCC_I2C12CLKSOURCE_CSI          (RCC_I2C12CKSELR_I2C12SRC_1 | RCC_I2C12CKSELR_I2C12SRC_0)
 
 #define IS_RCC_I2C12CLKSOURCE(SOURCE) \
                               (((SOURCE) == RCC_I2C12CLKSOURCE_PCLK1)  || \
@@ -372,10 +372,10 @@ typedef struct
 /** @defgroup RCCEx_I2C35_Clock_Source I2C35 Clock Source
   * @{
   */
-#define RCC_I2C35CLKSOURCE_PCLK1        RCC_I2C35CKSELR_I2C35SRC_0
-#define RCC_I2C35CLKSOURCE_PLL4         RCC_I2C35CKSELR_I2C35SRC_1
-#define RCC_I2C35CLKSOURCE_HSI          RCC_I2C35CKSELR_I2C35SRC_2
-#define RCC_I2C35CLKSOURCE_CSI          RCC_I2C35CKSELR_I2C35SRC_3
+#define RCC_I2C35CLKSOURCE_PCLK1        0U
+#define RCC_I2C35CLKSOURCE_PLL4         RCC_I2C35CKSELR_I2C35SRC_0
+#define RCC_I2C35CLKSOURCE_HSI          RCC_I2C35CKSELR_I2C35SRC_1
+#define RCC_I2C35CLKSOURCE_CSI          (RCC_I2C35CKSELR_I2C35SRC_1 | RCC_I2C35CKSELR_I2C35SRC_0)
 
 #define IS_RCC_I2C35CLKSOURCE(SOURCE) \
                               (((SOURCE) == RCC_I2C35CLKSOURCE_PCLK1) || \
@@ -390,10 +390,10 @@ typedef struct
 /** @defgroup RCCEx_I2C46_Clock_Source I2C46 Clock Source
   * @{
   */
-#define RCC_I2C46CLKSOURCE_PCLK5        RCC_I2C46CKSELR_I2C46SRC_0
-#define RCC_I2C46CLKSOURCE_PLL3         RCC_I2C46CKSELR_I2C46SRC_1
-#define RCC_I2C46CLKSOURCE_HSI          RCC_I2C46CKSELR_I2C46SRC_2
-#define RCC_I2C46CLKSOURCE_CSI          RCC_I2C46CKSELR_I2C46SRC_3
+#define RCC_I2C46CLKSOURCE_PCLK5        0U
+#define RCC_I2C46CLKSOURCE_PLL3         RCC_I2C46CKSELR_I2C46SRC_0
+#define RCC_I2C46CLKSOURCE_HSI          RCC_I2C46CKSELR_I2C46SRC_1
+#define RCC_I2C46CLKSOURCE_CSI          (RCC_I2C46CKSELR_I2C46SRC_1 | RCC_I2C46CKSELR_I2C46SRC_0)
 
 #define IS_RCC_I2C46CLKSOURCE(SOURCE) \
                               (((SOURCE) == RCC_I2C46CLKSOURCE_PCLK5)  || \
@@ -407,11 +407,11 @@ typedef struct
 /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
   * @{
   */
-#define RCC_SAI1CLKSOURCE_PLL4         RCC_SAI1CKSELR_SAI1SRC_0
-#define RCC_SAI1CLKSOURCE_PLL3_Q       RCC_SAI1CKSELR_SAI1SRC_1
-#define RCC_SAI1CLKSOURCE_I2SCKIN      RCC_SAI1CKSELR_SAI1SRC_2
-#define RCC_SAI1CLKSOURCE_PER          RCC_SAI1CKSELR_SAI1SRC_3
-#define RCC_SAI1CLKSOURCE_PLL3_R       RCC_SAI1CKSELR_SAI1SRC_4
+#define RCC_SAI1CLKSOURCE_PLL4         0U
+#define RCC_SAI1CLKSOURCE_PLL3_Q       RCC_SAI1CKSELR_SAI1SRC_0
+#define RCC_SAI1CLKSOURCE_I2SCKIN      RCC_SAI1CKSELR_SAI1SRC_1
+#define RCC_SAI1CLKSOURCE_PER          (RCC_SAI1CKSELR_SAI1SRC_1 | RCC_SAI1CKSELR_SAI1SRC_0)
+#define RCC_SAI1CLKSOURCE_PLL3_R       RCC_SAI1CKSELR_SAI1SRC_2
 
 #define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \
                              (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL4)    || \
@@ -427,12 +427,12 @@ typedef struct
 /** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source
   * @{
   */
-#define RCC_SAI2CLKSOURCE_PLL4          RCC_SAI2CKSELR_SAI2SRC_0
-#define RCC_SAI2CLKSOURCE_PLL3_Q        RCC_SAI2CKSELR_SAI2SRC_1
-#define RCC_SAI2CLKSOURCE_I2SCKIN       RCC_SAI2CKSELR_SAI2SRC_2
-#define RCC_SAI2CLKSOURCE_PER           RCC_SAI2CKSELR_SAI2SRC_3
-#define RCC_SAI2CLKSOURCE_SPDIF         RCC_SAI2CKSELR_SAI2SRC_4
-#define RCC_SAI2CLKSOURCE_PLL3_R        RCC_SAI2CKSELR_SAI2SRC_5
+#define RCC_SAI2CLKSOURCE_PLL4          0U
+#define RCC_SAI2CLKSOURCE_PLL3_Q        RCC_SAI2CKSELR_SAI2SRC_0
+#define RCC_SAI2CLKSOURCE_I2SCKIN       RCC_SAI2CKSELR_SAI2SRC_1
+#define RCC_SAI2CLKSOURCE_PER           (RCC_SAI2CKSELR_SAI2SRC_1 | RCC_SAI2CKSELR_SAI2SRC_0)
+#define RCC_SAI2CLKSOURCE_SPDIF         RCC_SAI2CKSELR_SAI2SRC_2
+#define RCC_SAI2CLKSOURCE_PLL3_R        (RCC_SAI2CKSELR_SAI2SRC_2 | RCC_SAI2CKSELR_SAI2SRC_0)
 
 
 #define IS_RCC_SAI2CLKSOURCE(__SOURCE__) \
@@ -449,11 +449,11 @@ typedef struct
 /** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source
   * @{
   */
-#define RCC_SAI3CLKSOURCE_PLL4          RCC_SAI3CKSELR_SAI3SRC_0
-#define RCC_SAI3CLKSOURCE_PLL3_Q        RCC_SAI3CKSELR_SAI3SRC_1
-#define RCC_SAI3CLKSOURCE_I2SCKIN       RCC_SAI3CKSELR_SAI3SRC_2
-#define RCC_SAI3CLKSOURCE_PER           RCC_SAI3CKSELR_SAI3SRC_3
-#define RCC_SAI3CLKSOURCE_PLL3_R        RCC_SAI3CKSELR_SAI3SRC_4
+#define RCC_SAI3CLKSOURCE_PLL4          0U
+#define RCC_SAI3CLKSOURCE_PLL3_Q        RCC_SAI3CKSELR_SAI3SRC_0
+#define RCC_SAI3CLKSOURCE_I2SCKIN       RCC_SAI3CKSELR_SAI3SRC_1
+#define RCC_SAI3CLKSOURCE_PER           (RCC_SAI3CKSELR_SAI3SRC_1 | RCC_SAI3CKSELR_SAI3SRC_0)
+#define RCC_SAI3CLKSOURCE_PLL3_R        RCC_SAI3CKSELR_SAI3SRC_2
 
 #define IS_RCC_SAI3CLKSOURCE(__SOURCE__) \
                              (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL4)    || \
@@ -469,11 +469,11 @@ typedef struct
 /** @defgroup RCCEx_SAI4_Clock_Source SAI4 Clock Source
   * @{
   */
-#define RCC_SAI4CLKSOURCE_PLL4          RCC_SAI4CKSELR_SAI4SRC_0
-#define RCC_SAI4CLKSOURCE_PLL3_Q        RCC_SAI4CKSELR_SAI4SRC_1
-#define RCC_SAI4CLKSOURCE_I2SCKIN       RCC_SAI4CKSELR_SAI4SRC_2
-#define RCC_SAI4CLKSOURCE_PER           RCC_SAI4CKSELR_SAI4SRC_3
-#define RCC_SAI4CLKSOURCE_PLL3_R        RCC_SAI4CKSELR_SAI4SRC_4
+#define RCC_SAI4CLKSOURCE_PLL4          0U
+#define RCC_SAI4CLKSOURCE_PLL3_Q        RCC_SAI4CKSELR_SAI4SRC_0
+#define RCC_SAI4CLKSOURCE_I2SCKIN       RCC_SAI4CKSELR_SAI4SRC_1
+#define RCC_SAI4CLKSOURCE_PER           (RCC_SAI4CKSELR_SAI4SRC_1 | RCC_SAI4CKSELR_SAI4SRC_0)
+#define RCC_SAI4CLKSOURCE_PLL3_R        RCC_SAI4CKSELR_SAI4SRC_2
 
 #define IS_RCC_SAI4CLKSOURCE(__SOURCE__) \
                              (((__SOURCE__) == RCC_SAI4CLKSOURCE_PLL4)    || \
@@ -489,11 +489,11 @@ typedef struct
 /** @defgroup RCCEx_SPI1_Clock_Source SPI/I2S1 Clock Source
   * @{
   */
-#define RCC_SPI1CLKSOURCE_PLL4        RCC_SPI2S1CKSELR_SPI1SRC_0
-#define RCC_SPI1CLKSOURCE_PLL3_Q      RCC_SPI2S1CKSELR_SPI1SRC_1
-#define RCC_SPI1CLKSOURCE_I2SCKIN     RCC_SPI2S1CKSELR_SPI1SRC_2
-#define RCC_SPI1CLKSOURCE_PER         RCC_SPI2S1CKSELR_SPI1SRC_3
-#define RCC_SPI1CLKSOURCE_PLL3_R      RCC_SPI2S1CKSELR_SPI1SRC_4
+#define RCC_SPI1CLKSOURCE_PLL4        0U
+#define RCC_SPI1CLKSOURCE_PLL3_Q      RCC_SPI2S1CKSELR_SPI1SRC_0
+#define RCC_SPI1CLKSOURCE_I2SCKIN     RCC_SPI2S1CKSELR_SPI1SRC_1
+#define RCC_SPI1CLKSOURCE_PER         (RCC_SPI2S1CKSELR_SPI1SRC_1 | RCC_SPI2S1CKSELR_SPI1SRC_0)
+#define RCC_SPI1CLKSOURCE_PLL3_R      RCC_SPI2S1CKSELR_SPI1SRC_2
 
 #define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \
                              (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL4)    || \
@@ -508,11 +508,11 @@ typedef struct
 /** @defgroup RCCEx_SPI23_Clock_Source SPI/I2S2,3 Clock Source
   * @{
   */
-#define RCC_SPI23CLKSOURCE_PLL4       RCC_SPI2S23CKSELR_SPI23SRC_0
-#define RCC_SPI23CLKSOURCE_PLL3_Q     RCC_SPI2S23CKSELR_SPI23SRC_1
-#define RCC_SPI23CLKSOURCE_I2SCKIN    RCC_SPI2S23CKSELR_SPI23SRC_2
-#define RCC_SPI23CLKSOURCE_PER        RCC_SPI2S23CKSELR_SPI23SRC_3
-#define RCC_SPI23CLKSOURCE_PLL3_R     RCC_SPI2S23CKSELR_SPI23SRC_4
+#define RCC_SPI23CLKSOURCE_PLL4       0U
+#define RCC_SPI23CLKSOURCE_PLL3_Q     RCC_SPI2S23CKSELR_SPI23SRC_0
+#define RCC_SPI23CLKSOURCE_I2SCKIN    RCC_SPI2S23CKSELR_SPI23SRC_1
+#define RCC_SPI23CLKSOURCE_PER        (RCC_SPI2S23CKSELR_SPI23SRC_1 | RCC_SPI2S23CKSELR_SPI23SRC_0)
+#define RCC_SPI23CLKSOURCE_PLL3_R     RCC_SPI2S23CKSELR_SPI23SRC_2
 
 #define IS_RCC_SPI23CLKSOURCE(__SOURCE__) \
                               (((__SOURCE__) == RCC_SPI23CLKSOURCE_PLL4)    || \
@@ -527,11 +527,11 @@ typedef struct
 /** @defgroup RCCEx_SPI45_Clock_Source SPI45 Clock Source
   * @{
   */
-#define RCC_SPI45CLKSOURCE_PCLK2        RCC_SPI45CKSELR_SPI45SRC_0
-#define RCC_SPI45CLKSOURCE_PLL4         RCC_SPI45CKSELR_SPI45SRC_1
-#define RCC_SPI45CLKSOURCE_HSI          RCC_SPI45CKSELR_SPI45SRC_2
-#define RCC_SPI45CLKSOURCE_CSI          RCC_SPI45CKSELR_SPI45SRC_3
-#define RCC_SPI45CLKSOURCE_HSE          RCC_SPI45CKSELR_SPI45SRC_4
+#define RCC_SPI45CLKSOURCE_PCLK2        0U
+#define RCC_SPI45CLKSOURCE_PLL4         RCC_SPI45CKSELR_SPI45SRC_0
+#define RCC_SPI45CLKSOURCE_HSI          RCC_SPI45CKSELR_SPI45SRC_1
+#define RCC_SPI45CLKSOURCE_CSI          (RCC_SPI45CKSELR_SPI45SRC_1 | RCC_SPI45CKSELR_SPI45SRC_0)
+#define RCC_SPI45CLKSOURCE_HSE          RCC_SPI45CKSELR_SPI45SRC_2
 
 #define IS_RCC_SPI45CLKSOURCE(__SOURCE__) \
                               (((__SOURCE__) == RCC_SPI45CLKSOURCE_PCLK2) || \
@@ -546,12 +546,12 @@ typedef struct
 /** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source
   * @{
   */
-#define RCC_SPI6CLKSOURCE_PCLK5         RCC_SPI6CKSELR_SPI6SRC_0
-#define RCC_SPI6CLKSOURCE_PLL4          RCC_SPI6CKSELR_SPI6SRC_1
-#define RCC_SPI6CLKSOURCE_HSI           RCC_SPI6CKSELR_SPI6SRC_2
-#define RCC_SPI6CLKSOURCE_CSI           RCC_SPI6CKSELR_SPI6SRC_3
-#define RCC_SPI6CLKSOURCE_HSE           RCC_SPI6CKSELR_SPI6SRC_4
-#define RCC_SPI6CLKSOURCE_PLL3          RCC_SPI6CKSELR_SPI6SRC_5
+#define RCC_SPI6CLKSOURCE_PCLK5         0U
+#define RCC_SPI6CLKSOURCE_PLL4          RCC_SPI6CKSELR_SPI6SRC_0
+#define RCC_SPI6CLKSOURCE_HSI           RCC_SPI6CKSELR_SPI6SRC_1
+#define RCC_SPI6CLKSOURCE_CSI           (RCC_SPI6CKSELR_SPI6SRC_1 | RCC_SPI6CKSELR_SPI6SRC_0)
+#define RCC_SPI6CLKSOURCE_HSE           RCC_SPI6CKSELR_SPI6SRC_2
+#define RCC_SPI6CLKSOURCE_PLL3          (RCC_SPI6CKSELR_SPI6SRC_2 | RCC_SPI6CKSELR_SPI6SRC_0)
 
 #define IS_RCC_SPI6CLKSOURCE(__SOURCE__) \
                              (((__SOURCE__) == RCC_SPI6CLKSOURCE_PCLK5) || \
@@ -568,12 +568,12 @@ typedef struct
 /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
   * @{
   */
-#define RCC_USART1CLKSOURCE_PCLK5       RCC_UART1CKSELR_UART1SRC_0
-#define RCC_USART1CLKSOURCE_PLL3        RCC_UART1CKSELR_UART1SRC_1
-#define RCC_USART1CLKSOURCE_HSI         RCC_UART1CKSELR_UART1SRC_2
-#define RCC_USART1CLKSOURCE_CSI         RCC_UART1CKSELR_UART1SRC_3
-#define RCC_USART1CLKSOURCE_PLL4        RCC_UART1CKSELR_UART1SRC_4
-#define RCC_USART1CLKSOURCE_HSE         RCC_UART1CKSELR_UART1SRC_5
+#define RCC_USART1CLKSOURCE_PCLK5       0U
+#define RCC_USART1CLKSOURCE_PLL3        RCC_UART1CKSELR_UART1SRC_0
+#define RCC_USART1CLKSOURCE_HSI         RCC_UART1CKSELR_UART1SRC_1
+#define RCC_USART1CLKSOURCE_CSI         (RCC_UART1CKSELR_UART1SRC_1 | RCC_UART1CKSELR_UART1SRC_0)
+#define RCC_USART1CLKSOURCE_PLL4        RCC_UART1CKSELR_UART1SRC_2
+#define RCC_USART1CLKSOURCE_HSE         (RCC_UART1CKSELR_UART1SRC_2 | RCC_UART1CKSELR_UART1SRC_0)
 
 #define IS_RCC_USART1CLKSOURCE(SOURCE) \
                                (((SOURCE) == RCC_USART1CLKSOURCE_PCLK5) || \
@@ -589,11 +589,11 @@ typedef struct
 /** @defgroup RCCEx_UART24_Clock_Source UART24 Clock Source
   * @{
   */
-#define RCC_UART24CLKSOURCE_PCLK1        RCC_UART24CKSELR_UART24SRC_0
-#define RCC_UART24CLKSOURCE_PLL4         RCC_UART24CKSELR_UART24SRC_1
-#define RCC_UART24CLKSOURCE_HSI          RCC_UART24CKSELR_UART24SRC_2
-#define RCC_UART24CLKSOURCE_CSI          RCC_UART24CKSELR_UART24SRC_3
-#define RCC_UART24CLKSOURCE_HSE          RCC_UART24CKSELR_UART24SRC_4
+#define RCC_UART24CLKSOURCE_PCLK1        0U
+#define RCC_UART24CLKSOURCE_PLL4         RCC_UART24CKSELR_UART24SRC_0
+#define RCC_UART24CLKSOURCE_HSI          RCC_UART24CKSELR_UART24SRC_1
+#define RCC_UART24CLKSOURCE_CSI          (RCC_UART24CKSELR_UART24SRC_1 | RCC_UART24CKSELR_UART24SRC_0)
+#define RCC_UART24CLKSOURCE_HSE          RCC_UART24CKSELR_UART24SRC_2
 
 #define IS_RCC_UART24CLKSOURCE(SOURCE) \
                                (((SOURCE) == RCC_UART24CLKSOURCE_PCLK1) || \
@@ -608,11 +608,11 @@ typedef struct
 /** @defgroup RCCEx_UART35_Clock_Source UART35 Clock Source
   * @{
   */
-#define RCC_UART35CLKSOURCE_PCLK1        RCC_UART35CKSELR_UART35SRC_0
-#define RCC_UART35CLKSOURCE_PLL4         RCC_UART35CKSELR_UART35SRC_1
-#define RCC_UART35CLKSOURCE_HSI          RCC_UART35CKSELR_UART35SRC_2
-#define RCC_UART35CLKSOURCE_CSI          RCC_UART35CKSELR_UART35SRC_3
-#define RCC_UART35CLKSOURCE_HSE          RCC_UART35CKSELR_UART35SRC_4
+#define RCC_UART35CLKSOURCE_PCLK1        0U
+#define RCC_UART35CLKSOURCE_PLL4         RCC_UART35CKSELR_UART35SRC_0
+#define RCC_UART35CLKSOURCE_HSI          RCC_UART35CKSELR_UART35SRC_1
+#define RCC_UART35CLKSOURCE_CSI          (RCC_UART35CKSELR_UART35SRC_1 | RCC_UART35CKSELR_UART35SRC_0)
+#define RCC_UART35CLKSOURCE_HSE          RCC_UART35CKSELR_UART35SRC_2
 
 #define IS_RCC_UART35CLKSOURCE(SOURCE) \
                                (((SOURCE) == RCC_UART35CLKSOURCE_PCLK1) || \
@@ -627,11 +627,11 @@ typedef struct
 /** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source
   * @{
   */
-#define RCC_USART6CLKSOURCE_PCLK2       RCC_UART6CKSELR_UART6SRC_0
-#define RCC_USART6CLKSOURCE_PLL4        RCC_UART6CKSELR_UART6SRC_1
-#define RCC_USART6CLKSOURCE_HSI         RCC_UART6CKSELR_UART6SRC_2
-#define RCC_USART6CLKSOURCE_CSI         RCC_UART6CKSELR_UART6SRC_3
-#define RCC_USART6CLKSOURCE_HSE         RCC_UART6CKSELR_UART6SRC_4
+#define RCC_USART6CLKSOURCE_PCLK2       0U
+#define RCC_USART6CLKSOURCE_PLL4        RCC_UART6CKSELR_UART6SRC_0
+#define RCC_USART6CLKSOURCE_HSI         RCC_UART6CKSELR_UART6SRC_1
+#define RCC_USART6CLKSOURCE_CSI         (RCC_UART6CKSELR_UART6SRC_1 | RCC_UART6CKSELR_UART6SRC_0)
+#define RCC_USART6CLKSOURCE_HSE         RCC_UART6CKSELR_UART6SRC_2
 
 #define IS_RCC_USART6CLKSOURCE(SOURCE) \
                                (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \
@@ -646,11 +646,11 @@ typedef struct
 /** @defgroup RCCEx_UART78_Clock_Source UART78 Clock Source
   * @{
   */
-#define RCC_UART78CLKSOURCE_PCLK1        RCC_UART78CKSELR_UART78SRC_0
-#define RCC_UART78CLKSOURCE_PLL4         RCC_UART78CKSELR_UART78SRC_1
-#define RCC_UART78CLKSOURCE_HSI          RCC_UART78CKSELR_UART78SRC_2
-#define RCC_UART78CLKSOURCE_CSI          RCC_UART78CKSELR_UART78SRC_3
-#define RCC_UART78CLKSOURCE_HSE          RCC_UART78CKSELR_UART78SRC_4
+#define RCC_UART78CLKSOURCE_PCLK1        0U
+#define RCC_UART78CLKSOURCE_PLL4         RCC_UART78CKSELR_UART78SRC_0
+#define RCC_UART78CLKSOURCE_HSI          RCC_UART78CKSELR_UART78SRC_1
+#define RCC_UART78CLKSOURCE_CSI          (RCC_UART78CKSELR_UART78SRC_1 | RCC_UART78CKSELR_UART78SRC_0)
+#define RCC_UART78CLKSOURCE_HSE          RCC_UART78CKSELR_UART78SRC_2
 
 #define IS_RCC_UART78CLKSOURCE(SOURCE) \
                                (((SOURCE) == RCC_UART78CLKSOURCE_PCLK1) || \
@@ -665,10 +665,10 @@ typedef struct
 /** @defgroup RCCEx_SDMMC12_Clock_Source SDMMC12 Clock Source
   * @{
   */
-#define RCC_SDMMC12CLKSOURCE_HCLK6       RCC_SDMMC12CKSELR_SDMMC12SRC_0
-#define RCC_SDMMC12CLKSOURCE_PLL3        RCC_SDMMC12CKSELR_SDMMC12SRC_1
-#define RCC_SDMMC12CLKSOURCE_PLL4        RCC_SDMMC12CKSELR_SDMMC12SRC_2
-#define RCC_SDMMC12CLKSOURCE_HSI         RCC_SDMMC12CKSELR_SDMMC12SRC_3
+#define RCC_SDMMC12CLKSOURCE_HCLK6       0U
+#define RCC_SDMMC12CLKSOURCE_PLL3        RCC_SDMMC12CKSELR_SDMMC12SRC_0
+#define RCC_SDMMC12CLKSOURCE_PLL4        RCC_SDMMC12CKSELR_SDMMC12SRC_1
+#define RCC_SDMMC12CLKSOURCE_HSI         (RCC_SDMMC12CKSELR_SDMMC12SRC_1 | RCC_SDMMC12CKSELR_SDMMC12SRC_0)
 
 #define IS_RCC_SDMMC12CLKSOURCE(SOURCE) \
                                 (((SOURCE) == RCC_SDMMC12CLKSOURCE_HCLK6) || \
@@ -682,10 +682,10 @@ typedef struct
 /** @defgroup RCCEx_SDMMC3_Clock_Source SDMMC3 Clock Source
   * @{
   */
-#define RCC_SDMMC3CLKSOURCE_HCLK2      RCC_SDMMC3CKSELR_SDMMC3SRC_0
-#define RCC_SDMMC3CLKSOURCE_PLL3       RCC_SDMMC3CKSELR_SDMMC3SRC_1
-#define RCC_SDMMC3CLKSOURCE_PLL4       RCC_SDMMC3CKSELR_SDMMC3SRC_2
-#define RCC_SDMMC3CLKSOURCE_HSI        RCC_SDMMC3CKSELR_SDMMC3SRC_3
+#define RCC_SDMMC3CLKSOURCE_HCLK2      0U
+#define RCC_SDMMC3CLKSOURCE_PLL3       RCC_SDMMC3CKSELR_SDMMC3SRC_0
+#define RCC_SDMMC3CLKSOURCE_PLL4       RCC_SDMMC3CKSELR_SDMMC3SRC_1
+#define RCC_SDMMC3CLKSOURCE_HSI        (RCC_SDMMC3CKSELR_SDMMC3SRC_1 | RCC_SDMMC3CKSELR_SDMMC3SRC_0)
 
 #define IS_RCC_SDMMC3CLKSOURCE(SOURCE)  \
                                (((SOURCE) == RCC_SDMMC3CLKSOURCE_HCLK2) || \
@@ -699,9 +699,9 @@ typedef struct
 /** @defgroup RCCEx_ETH_Clock_Source ETH Clock Source
   * @{
   */
-#define RCC_ETHCLKSOURCE_PLL4       RCC_ETHCKSELR_ETHSRC_0
-#define RCC_ETHCLKSOURCE_PLL3       RCC_ETHCKSELR_ETHSRC_1
-#define RCC_ETHCLKSOURCE_OFF        RCC_ETHCKSELR_ETHSRC_2
+#define RCC_ETHCLKSOURCE_PLL4       0U
+#define RCC_ETHCLKSOURCE_PLL3       RCC_ETHCKSELR_ETHSRC_0
+#define RCC_ETHCLKSOURCE_OFF        RCC_ETHCKSELR_ETHSRC_1
 
 
 #define IS_RCC_ETHCLKSOURCE(SOURCE) (((SOURCE) == RCC_ETHCLKSOURCE_PLL4)  || \
@@ -715,22 +715,22 @@ typedef struct
 /** @defgroup RCCEx_ETH_PrecisionTimeProtocol_Divider ETH PrecisionTimeProtocol Divider
   * @{
   */
-#define RCC_ETHPTPDIV_1   RCC_ETHCKSELR_ETHPTPDIV_0   /*Bypass (default after reset*/
-#define RCC_ETHPTPDIV_2   RCC_ETHCKSELR_ETHPTPDIV_1   /*Division by 2*/
-#define RCC_ETHPTPDIV_3   RCC_ETHCKSELR_ETHPTPDIV_2   /*Division by 3*/
-#define RCC_ETHPTPDIV_4   RCC_ETHCKSELR_ETHPTPDIV_3   /*Division by 4*/
-#define RCC_ETHPTPDIV_5   RCC_ETHCKSELR_ETHPTPDIV_4   /*Division by 5*/
-#define RCC_ETHPTPDIV_6   RCC_ETHCKSELR_ETHPTPDIV_5   /*Division by 6*/
-#define RCC_ETHPTPDIV_7   RCC_ETHCKSELR_ETHPTPDIV_6   /*Division by 7*/
-#define RCC_ETHPTPDIV_8   RCC_ETHCKSELR_ETHPTPDIV_7   /*Division by 8*/
-#define RCC_ETHPTPDIV_9   RCC_ETHCKSELR_ETHPTPDIV_8   /*Division by 9*/
-#define RCC_ETHPTPDIV_10  RCC_ETHCKSELR_ETHPTPDIV_9   /*Division by 10*/
-#define RCC_ETHPTPDIV_11  RCC_ETHCKSELR_ETHPTPDIV_10  /*Division by 11*/
-#define RCC_ETHPTPDIV_12  RCC_ETHCKSELR_ETHPTPDIV_11  /*Division by 12*/
-#define RCC_ETHPTPDIV_13  RCC_ETHCKSELR_ETHPTPDIV_12  /*Division by 13*/
-#define RCC_ETHPTPDIV_14  RCC_ETHCKSELR_ETHPTPDIV_13  /*Division by 14*/
-#define RCC_ETHPTPDIV_15  RCC_ETHCKSELR_ETHPTPDIV_14  /*Division by 15*/
-#define RCC_ETHPTPDIV_16  RCC_ETHCKSELR_ETHPTPDIV_15  /*Division by 16*/
+#define RCC_ETHPTPDIV_1   0U                                                        /*Bypass (default after reset*/
+#define RCC_ETHPTPDIV_2   RCC_ETHCKSELR_ETHPTPDIV_0                                 /*Division by 2*/
+#define RCC_ETHPTPDIV_3   RCC_ETHCKSELR_ETHPTPDIV_1                                 /*Division by 3*/
+#define RCC_ETHPTPDIV_4   (RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0)   /*Division by 4*/
+#define RCC_ETHPTPDIV_5   RCC_ETHCKSELR_ETHPTPDIV_2                                 /*Division by 5*/
+#define RCC_ETHPTPDIV_6   (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_0)   /*Division by 6*/
+#define RCC_ETHPTPDIV_7   (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1)   /*Division by 7*/
+#define RCC_ETHPTPDIV_8   (RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0)  /*Division by 8*/
+#define RCC_ETHPTPDIV_9   RCC_ETHCKSELR_ETHPTPDIV_3                                 /*Division by 9*/
+#define RCC_ETHPTPDIV_10  (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_0)   /*Division by 10*/
+#define RCC_ETHPTPDIV_11  (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_1)   /*Division by 11*/
+#define RCC_ETHPTPDIV_12  (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0)  /*Division by 12*/
+#define RCC_ETHPTPDIV_13  (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2)   /*Division by 13*/
+#define RCC_ETHPTPDIV_14  (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_0)  /*Division by 14*/
+#define RCC_ETHPTPDIV_15  (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1)  /*Division by 15*/
+#define RCC_ETHPTPDIV_16  (RCC_ETHCKSELR_ETHPTPDIV_3 | RCC_ETHCKSELR_ETHPTPDIV_2 | RCC_ETHCKSELR_ETHPTPDIV_1 | RCC_ETHCKSELR_ETHPTPDIV_0)  /*Division by 16*/
 
 
 #define IS_RCC_ETHPTPDIV(SOURCE)        (((SOURCE) == RCC_ETHPTPDIV_1)  || \
@@ -757,10 +757,10 @@ typedef struct
 /** @defgroup RCCEx_QSPI_Clock_Source QSPI Clock Source
   * @{
   */
-#define RCC_QSPICLKSOURCE_ACLK  RCC_QSPICKSELR_QSPISRC_0
-#define RCC_QSPICLKSOURCE_PLL3  RCC_QSPICKSELR_QSPISRC_1
-#define RCC_QSPICLKSOURCE_PLL4  RCC_QSPICKSELR_QSPISRC_2
-#define RCC_QSPICLKSOURCE_PER   RCC_QSPICKSELR_QSPISRC_3
+#define RCC_QSPICLKSOURCE_ACLK  0U
+#define RCC_QSPICLKSOURCE_PLL3  RCC_QSPICKSELR_QSPISRC_0
+#define RCC_QSPICLKSOURCE_PLL4  RCC_QSPICKSELR_QSPISRC_1
+#define RCC_QSPICLKSOURCE_PER   (RCC_QSPICKSELR_QSPISRC_1 | RCC_QSPICKSELR_QSPISRC_0)
 
 #define IS_RCC_QSPICLKSOURCE(SOURCE) \
                              (((SOURCE) == RCC_QSPICLKSOURCE_ACLK) || \
@@ -774,10 +774,10 @@ typedef struct
 /** @defgroup RCCEx_FMC_Clock_Source FMC Clock Source
   * @{
   */
-#define RCC_FMCCLKSOURCE_ACLK       RCC_FMCCKSELR_FMCSRC_0
-#define RCC_FMCCLKSOURCE_PLL3       RCC_FMCCKSELR_FMCSRC_1
-#define RCC_FMCCLKSOURCE_PLL4       RCC_FMCCKSELR_FMCSRC_2
-#define RCC_FMCCLKSOURCE_PER        RCC_FMCCKSELR_FMCSRC_3
+#define RCC_FMCCLKSOURCE_ACLK       0U
+#define RCC_FMCCLKSOURCE_PLL3       RCC_FMCCKSELR_FMCSRC_0
+#define RCC_FMCCLKSOURCE_PLL4       RCC_FMCCKSELR_FMCSRC_1
+#define RCC_FMCCLKSOURCE_PER        (RCC_FMCCKSELR_FMCSRC_1 | RCC_FMCCKSELR_FMCSRC_0)
 
 #define IS_RCC_FMCCLKSOURCE(SOURCE) (((SOURCE) == RCC_FMCCLKSOURCE_ACLK)  || \
                                      ((SOURCE) == RCC_FMCCLKSOURCE_PLL3)  || \
@@ -791,10 +791,10 @@ typedef struct
 /** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source
   * @{
   */
-#define RCC_FDCANCLKSOURCE_HSE          RCC_FDCANCKSELR_FDCANSRC_0
-#define RCC_FDCANCLKSOURCE_PLL3         RCC_FDCANCKSELR_FDCANSRC_1
-#define RCC_FDCANCLKSOURCE_PLL4_Q       RCC_FDCANCKSELR_FDCANSRC_2
-#define RCC_FDCANCLKSOURCE_PLL4_R       RCC_FDCANCKSELR_FDCANSRC_3
+#define RCC_FDCANCLKSOURCE_HSE          0U
+#define RCC_FDCANCLKSOURCE_PLL3         RCC_FDCANCKSELR_FDCANSRC_0
+#define RCC_FDCANCLKSOURCE_PLL4_Q       RCC_FDCANCKSELR_FDCANSRC_1
+#define RCC_FDCANCLKSOURCE_PLL4_R       (RCC_FDCANCKSELR_FDCANSRC_1 | RCC_FDCANCKSELR_FDCANSRC_0)
 
 
 
@@ -811,9 +811,9 @@ typedef struct
 /** @defgroup RCCEx_SPDIFRX_Clock_Source SPDIFRX Clock Source
   * @{
   */
-#define RCC_SPDIFRXCLKSOURCE_PLL4         RCC_SPDIFCKSELR_SPDIFSRC_0
-#define RCC_SPDIFRXCLKSOURCE_PLL3         RCC_SPDIFCKSELR_SPDIFSRC_1
-#define RCC_SPDIFRXCLKSOURCE_HSI          RCC_SPDIFCKSELR_SPDIFSRC_2
+#define RCC_SPDIFRXCLKSOURCE_PLL4         0U
+#define RCC_SPDIFRXCLKSOURCE_PLL3         RCC_SPDIFCKSELR_SPDIFSRC_0
+#define RCC_SPDIFRXCLKSOURCE_HSI          RCC_SPDIFCKSELR_SPDIFSRC_1
 
 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) \
                                 (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL4)  || \
@@ -826,9 +826,9 @@ typedef struct
 /** @defgroup RCCEx_CEC_Clock_Source CEC Clock Source
   * @{
   */
-#define RCC_CECCLKSOURCE_LSE            RCC_CECCKSELR_CECSRC_0
-#define RCC_CECCLKSOURCE_LSI            RCC_CECCKSELR_CECSRC_1
-#define RCC_CECCLKSOURCE_CSI122         RCC_CECCKSELR_CECSRC_2
+#define RCC_CECCLKSOURCE_LSE            0U
+#define RCC_CECCLKSOURCE_LSI            RCC_CECCKSELR_CECSRC_0
+#define RCC_CECCLKSOURCE_CSI122         RCC_CECCKSELR_CECSRC_1
 
 #define IS_RCC_CECCLKSOURCE(SOURCE)     (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \
                                          ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \
@@ -840,9 +840,9 @@ typedef struct
 /** @defgroup RCCEx_USBPHY_Clock_Source USBPHY Clock Source
   * @{
   */
-#define RCC_USBPHYCLKSOURCE_HSE         RCC_USBCKSELR_USBPHYSRC_0
-#define RCC_USBPHYCLKSOURCE_PLL4        RCC_USBCKSELR_USBPHYSRC_1
-#define RCC_USBPHYCLKSOURCE_HSE2        RCC_USBCKSELR_USBPHYSRC_2
+#define RCC_USBPHYCLKSOURCE_HSE         0U
+#define RCC_USBPHYCLKSOURCE_PLL4        RCC_USBCKSELR_USBPHYSRC_0
+#define RCC_USBPHYCLKSOURCE_HSE2        RCC_USBCKSELR_USBPHYSRC_1
 
 #define IS_RCC_USBPHYCLKSOURCE(SOURCE) \
                                (((SOURCE) == RCC_USBPHYCLKSOURCE_HSE) || \
@@ -855,8 +855,8 @@ typedef struct
 /** @defgroup RCCEx_USBO_Clock_Source USBO Clock Source
   * @{
   */
-#define RCC_USBOCLKSOURCE_PLL4            RCC_USBCKSELR_USBOSRC_0
-#define RCC_USBOCLKSOURCE_PHY             RCC_USBCKSELR_USBOSRC_1
+#define RCC_USBOCLKSOURCE_PLL4            0U
+#define RCC_USBOCLKSOURCE_PHY             RCC_USBCKSELR_USBOSRC
 
 #define IS_RCC_USBOCLKSOURCE(SOURCE)  (((SOURCE) == RCC_USBOCLKSOURCE_PLL4) || \
                                        ((SOURCE) == RCC_USBOCLKSOURCE_PHY))
@@ -868,10 +868,10 @@ typedef struct
 /** @defgroup RCCEx_RNG1_Clock_Source RNG1 Clock Source
   * @{
   */
-#define RCC_RNG1CLKSOURCE_CSI         RCC_RNG1CKSELR_RNG1SRC_0
-#define RCC_RNG1CLKSOURCE_PLL4        RCC_RNG1CKSELR_RNG1SRC_1
-#define RCC_RNG1CLKSOURCE_LSE         RCC_RNG1CKSELR_RNG1SRC_2
-#define RCC_RNG1CLKSOURCE_LSI         RCC_RNG1CKSELR_RNG1SRC_3
+#define RCC_RNG1CLKSOURCE_CSI         0U
+#define RCC_RNG1CLKSOURCE_PLL4        RCC_RNG1CKSELR_RNG1SRC_0
+#define RCC_RNG1CLKSOURCE_LSE         RCC_RNG1CKSELR_RNG1SRC_1
+#define RCC_RNG1CLKSOURCE_LSI         (RCC_RNG1CKSELR_RNG1SRC_1 | RCC_RNG1CKSELR_RNG1SRC_0)
 
 #define IS_RCC_RNG1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_RNG1CLKSOURCE_CSI)  || \
                                        ((SOURCE) == RCC_RNG1CLKSOURCE_PLL4) || \
@@ -886,10 +886,10 @@ typedef struct
 /** @defgroup RCCEx_RNG2_Clock_Source RNG2 Clock Source
   * @{
   */
-#define RCC_RNG2CLKSOURCE_CSI         RCC_RNG2CKSELR_RNG2SRC_0
-#define RCC_RNG2CLKSOURCE_PLL4        RCC_RNG2CKSELR_RNG2SRC_1
-#define RCC_RNG2CLKSOURCE_LSE         RCC_RNG2CKSELR_RNG2SRC_2
-#define RCC_RNG2CLKSOURCE_LSI         RCC_RNG2CKSELR_RNG2SRC_3
+#define RCC_RNG2CLKSOURCE_CSI         0U
+#define RCC_RNG2CLKSOURCE_PLL4        RCC_RNG2CKSELR_RNG2SRC_0
+#define RCC_RNG2CLKSOURCE_LSE         RCC_RNG2CKSELR_RNG2SRC_1
+#define RCC_RNG2CLKSOURCE_LSI         (RCC_RNG2CKSELR_RNG2SRC_1 | RCC_RNG2CKSELR_RNG2SRC_0)
 
 #define IS_RCC_RNG2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_RNG2CLKSOURCE_CSI)  || \
                                        ((SOURCE) == RCC_RNG2CLKSOURCE_PLL4) || \
@@ -904,10 +904,10 @@ typedef struct
 /** @defgroup RCCEx_CKPER_Clock_Source CKPER Clock Source
   * @{
   */
-#define RCC_CKPERCLKSOURCE_HSI          RCC_CPERCKSELR_CKPERSRC_0
-#define RCC_CKPERCLKSOURCE_CSI          RCC_CPERCKSELR_CKPERSRC_1
-#define RCC_CKPERCLKSOURCE_HSE          RCC_CPERCKSELR_CKPERSRC_2
-#define RCC_CKPERCLKSOURCE_OFF          RCC_CPERCKSELR_CKPERSRC_3 /*Clock disabled*/
+#define RCC_CKPERCLKSOURCE_HSI          0U
+#define RCC_CKPERCLKSOURCE_CSI          RCC_CPERCKSELR_CKPERSRC_0
+#define RCC_CKPERCLKSOURCE_HSE          RCC_CPERCKSELR_CKPERSRC_1
+#define RCC_CKPERCLKSOURCE_OFF          (RCC_CPERCKSELR_CKPERSRC_1 | RCC_CPERCKSELR_CKPERSRC_0) /*Clock disabled*/
 
 #define IS_RCC_CKPERCLKSOURCE(SOURCE) (((SOURCE) == RCC_CKPERCLKSOURCE_HSI) || \
                                        ((SOURCE) == RCC_CKPERCLKSOURCE_CSI) || \
@@ -921,9 +921,9 @@ typedef struct
 /** @defgroup RCCEx_STGEN_Clock_Source STGEN Clock Source
   * @{
   */
-#define RCC_STGENCLKSOURCE_HSI          RCC_STGENCKSELR_STGENSRC_0
-#define RCC_STGENCLKSOURCE_HSE          RCC_STGENCKSELR_STGENSRC_1
-#define RCC_STGENCLKSOURCE_OFF          RCC_STGENCKSELR_STGENSRC_2
+#define RCC_STGENCLKSOURCE_HSI          0U
+#define RCC_STGENCLKSOURCE_HSE          RCC_STGENCKSELR_STGENSRC_0
+#define RCC_STGENCLKSOURCE_OFF          RCC_STGENCKSELR_STGENSRC_1
 
 #define IS_RCC_STGENCLKSOURCE(SOURCE) \
                               (((SOURCE) == RCC_STGENCLKSOURCE_HSI) || \
@@ -937,8 +937,8 @@ typedef struct
 /** @defgroup RCCEx_DSI_Clock_Source  DSI Clock Source
   * @{
   */
-#define RCC_DSICLKSOURCE_PHY            RCC_DSICKSELR_DSISRC_0
-#define RCC_DSICLKSOURCE_PLL4           RCC_DSICKSELR_DSISRC_1
+#define RCC_DSICLKSOURCE_PHY            0U
+#define RCC_DSICLKSOURCE_PLL4           RCC_DSICKSELR_DSISRC
 
 #define IS_RCC_DSICLKSOURCE(__SOURCE__) \
                             (((__SOURCE__) == RCC_DSICLKSOURCE_PHY)  || \
@@ -951,9 +951,9 @@ typedef struct
 /** @defgroup RCCEx_ADC_Clock_Source ADC Clock Source
   * @{
   */
-#define RCC_ADCCLKSOURCE_PLL4           RCC_ADCCKSELR_ADCSRC_0
-#define RCC_ADCCLKSOURCE_PER            RCC_ADCCKSELR_ADCSRC_1
-#define RCC_ADCCLKSOURCE_PLL3           RCC_ADCCKSELR_ADCSRC_2
+#define RCC_ADCCLKSOURCE_PLL4           0U
+#define RCC_ADCCLKSOURCE_PER            RCC_ADCCKSELR_ADCSRC_0
+#define RCC_ADCCLKSOURCE_PLL3           RCC_ADCCKSELR_ADCSRC_1
 
 #define IS_RCC_ADCCLKSOURCE(SOURCE) (((SOURCE) == RCC_ADCCLKSOURCE_PLL4)  || \
                                      ((SOURCE) == RCC_ADCCLKSOURCE_PER)   || \
@@ -966,13 +966,13 @@ typedef struct
 /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
   * @{
   */
-#define RCC_LPTIM1CLKSOURCE_PCLK1       RCC_LPTIM1CKSELR_LPTIM1SRC_0
-#define RCC_LPTIM1CLKSOURCE_PLL4        RCC_LPTIM1CKSELR_LPTIM1SRC_1
-#define RCC_LPTIM1CLKSOURCE_PLL3        RCC_LPTIM1CKSELR_LPTIM1SRC_2
-#define RCC_LPTIM1CLKSOURCE_LSE         RCC_LPTIM1CKSELR_LPTIM1SRC_3
-#define RCC_LPTIM1CLKSOURCE_LSI         RCC_LPTIM1CKSELR_LPTIM1SRC_4
-#define RCC_LPTIM1CLKSOURCE_PER         RCC_LPTIM1CKSELR_LPTIM1SRC_5
-#define RCC_LPTIM1CLKSOURCE_OFF         RCC_LPTIM1CKSELR_LPTIM1SRC_6
+#define RCC_LPTIM1CLKSOURCE_PCLK1       0U
+#define RCC_LPTIM1CLKSOURCE_PLL4        RCC_LPTIM1CKSELR_LPTIM1SRC_0
+#define RCC_LPTIM1CLKSOURCE_PLL3        RCC_LPTIM1CKSELR_LPTIM1SRC_1
+#define RCC_LPTIM1CLKSOURCE_LSE         (RCC_LPTIM1CKSELR_LPTIM1SRC_1 | RCC_LPTIM1CKSELR_LPTIM1SRC_0)
+#define RCC_LPTIM1CLKSOURCE_LSI         RCC_LPTIM1CKSELR_LPTIM1SRC_2
+#define RCC_LPTIM1CLKSOURCE_PER         (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_0)
+#define RCC_LPTIM1CLKSOURCE_OFF         (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_1)
 
 #define IS_RCC_LPTIM1CLKSOURCE(SOURCE) \
                                (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
@@ -989,12 +989,12 @@ typedef struct
 /** @defgroup RCCEx_LPTIM23_Clock_Source LPTIM23 Clock Source
   * @{
   */
-#define RCC_LPTIM23CLKSOURCE_PCLK3       RCC_LPTIM23CKSELR_LPTIM23SRC_0
-#define RCC_LPTIM23CLKSOURCE_PLL4        RCC_LPTIM23CKSELR_LPTIM23SRC_1
-#define RCC_LPTIM23CLKSOURCE_PER         RCC_LPTIM23CKSELR_LPTIM23SRC_2
-#define RCC_LPTIM23CLKSOURCE_LSE         RCC_LPTIM23CKSELR_LPTIM23SRC_3
-#define RCC_LPTIM23CLKSOURCE_LSI         RCC_LPTIM23CKSELR_LPTIM23SRC_4
-#define RCC_LPTIM23CLKSOURCE_OFF         RCC_LPTIM23CKSELR_LPTIM23SRC_5
+#define RCC_LPTIM23CLKSOURCE_PCLK3       0U
+#define RCC_LPTIM23CLKSOURCE_PLL4        RCC_LPTIM23CKSELR_LPTIM23SRC_0
+#define RCC_LPTIM23CLKSOURCE_PER         RCC_LPTIM23CKSELR_LPTIM23SRC_1
+#define RCC_LPTIM23CLKSOURCE_LSE         (RCC_LPTIM23CKSELR_LPTIM23SRC_1 | RCC_LPTIM23CKSELR_LPTIM23SRC_0)
+#define RCC_LPTIM23CLKSOURCE_LSI         RCC_LPTIM23CKSELR_LPTIM23SRC_2
+#define RCC_LPTIM23CLKSOURCE_OFF         (RCC_LPTIM23CKSELR_LPTIM23SRC_2 | RCC_LPTIM23CKSELR_LPTIM23SRC_0)
 
 
 #define IS_RCC_LPTIM23CLKSOURCE(SOURCE) \
@@ -1011,13 +1011,13 @@ typedef struct
 /** @defgroup RCCEx_LPTIM45_Clock_Source LPTIM45 Clock Source
   * @{
   */
-#define RCC_LPTIM45CLKSOURCE_PCLK3      RCC_LPTIM45CKSELR_LPTIM45SRC_0
-#define RCC_LPTIM45CLKSOURCE_PLL4       RCC_LPTIM45CKSELR_LPTIM45SRC_1
-#define RCC_LPTIM45CLKSOURCE_PLL3       RCC_LPTIM45CKSELR_LPTIM45SRC_2
-#define RCC_LPTIM45CLKSOURCE_LSE        RCC_LPTIM45CKSELR_LPTIM45SRC_3
-#define RCC_LPTIM45CLKSOURCE_LSI        RCC_LPTIM45CKSELR_LPTIM45SRC_4
-#define RCC_LPTIM45CLKSOURCE_PER        RCC_LPTIM45CKSELR_LPTIM45SRC_5
-#define RCC_LPTIM45CLKSOURCE_OFF        RCC_LPTIM45CKSELR_LPTIM45SRC_6
+#define RCC_LPTIM45CLKSOURCE_PCLK3      0U
+#define RCC_LPTIM45CLKSOURCE_PLL4       RCC_LPTIM45CKSELR_LPTIM45SRC_0
+#define RCC_LPTIM45CLKSOURCE_PLL3       RCC_LPTIM45CKSELR_LPTIM45SRC_1
+#define RCC_LPTIM45CLKSOURCE_LSE        (RCC_LPTIM45CKSELR_LPTIM45SRC_1 | RCC_LPTIM45CKSELR_LPTIM45SRC_0)
+#define RCC_LPTIM45CLKSOURCE_LSI        RCC_LPTIM45CKSELR_LPTIM45SRC_2
+#define RCC_LPTIM45CLKSOURCE_PER        (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_0)
+#define RCC_LPTIM45CLKSOURCE_OFF        (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_1)
 
 
 
@@ -1037,8 +1037,8 @@ typedef struct
 /** @defgroup RCCEx_TIMG1_Prescaler_Selection TIMG1 Prescaler Selection
   * @{
   */
-#define RCC_TIMG1PRES_DEACTIVATED                RCC_TIMG1PRER_TIMG1PRE_0
-#define RCC_TIMG1PRES_ACTIVATED                  RCC_TIMG1PRER_TIMG1PRE_1
+#define RCC_TIMG1PRES_DEACTIVATED                0U
+#define RCC_TIMG1PRES_ACTIVATED                  RCC_TIMG1PRER_TIMG1PRE
 
 #define IS_RCC_TIMG1PRES(PRES)  (((PRES) == RCC_TIMG1PRES_DEACTIVATED)    || \
                                 ((PRES) == RCC_TIMG1PRES_ACTIVATED))
@@ -1050,8 +1050,8 @@ typedef struct
 /** @defgroup RCCEx_TIMG2_Prescaler_Selection TIMG2 Prescaler Selection
   * @{
   */
-#define RCC_TIMG2PRES_DEACTIVATED                RCC_TIMG2PRER_TIMG2PRE_0
-#define RCC_TIMG2PRES_ACTIVATED                  RCC_TIMG2PRER_TIMG2PRE_1
+#define RCC_TIMG2PRES_DEACTIVATED                0U
+#define RCC_TIMG2PRES_ACTIVATED                  RCC_TIMG2PRER_TIMG2PRE
 
 #define IS_RCC_TIMG2PRES(PRES)  (((PRES) == RCC_TIMG2PRES_DEACTIVATED)    || \
                                 ((PRES) == RCC_TIMG2PRES_ACTIVATED))

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_rtc.h

@@ -702,8 +702,6 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
 
 #elif defined(CORE_CA7)
 
-#else /* !CORE_CA7 */
-
 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI_C1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
 
 /**
@@ -724,6 +722,8 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to
   */
 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI_C1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
 
+#else /* !CORE_CA7 */
+
 #error Please #define CORE_CM4 or CORE_CA7
 
 #endif

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_sai.h

@@ -66,7 +66,7 @@ typedef struct
 {
   FunctionalState  Activation;  /*!< Enable/disable PDM interface */
   uint32_t         MicPairsNbr; /*!< Specifies the number of microphone pairs used.
-                                     This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
   uint32_t         ClockEnable; /*!< Specifies which clock must be enabled.
                                      This parameter can be a values combination of @ref SAI_PDM_ClockEnable */
 } SAI_PdmInitTypeDef;
@@ -113,9 +113,10 @@ typedef struct
   uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.
                                      This parameter can be a value of @ref SAI_Audio_Frequency */
 
-  uint32_t Mckdiv;              /*!< Specifies the master clock divider, the parameter will be used if for
-                                     AudioFrequency the user choice
-                                     This parameter must be a number between Min_Data = 0 and Max_Data = 63. */
+  uint32_t Mckdiv;              /*!< Specifies the master clock divider.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 63.
+                                     @note This parameter is used only if AudioFrequency is set to
+                                           SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
 
   uint32_t MckOverSampling;     /*!< Specifies the master clock oversampling.
                                      This parameter can be a value of @ref SAI_Block_Mck_OverSampling */
@@ -152,6 +153,7 @@ typedef struct
 
 /** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
   * @brief  SAI Frame Init structure definition
+  * @note   For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
   * @{
   */
 typedef struct
@@ -184,6 +186,8 @@ typedef struct
 
 /** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
   * @brief   SAI Block Slot Init Structure definition
+  * @note    For SPDIF protocol, these parameters are not used (set by hardware).
+  * @note    For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
   * @{
   */
 typedef struct
@@ -285,17 +289,17 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Error_Code SAI Error Code
   * @{
   */
-#define HAL_SAI_ERROR_NONE    ((uint32_t)0x00000000U)  /*!< No error */
-#define HAL_SAI_ERROR_OVR     ((uint32_t)0x00000001U)  /*!< Overrun Error */
-#define HAL_SAI_ERROR_UDR     ((uint32_t)0x00000002U)  /*!< Underrun error */
-#define HAL_SAI_ERROR_AFSDET  ((uint32_t)0x00000004U)  /*!< Anticipated Frame synchronisation detection */
-#define HAL_SAI_ERROR_LFSDET  ((uint32_t)0x00000008U)  /*!< Late Frame synchronisation detection */
-#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U)  /*!< codec not ready */
-#define HAL_SAI_ERROR_WCKCFG  ((uint32_t)0x00000020U)  /*!< Wrong clock configuration */
-#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U)  /*!< Timeout error */
-#define HAL_SAI_ERROR_DMA     ((uint32_t)0x00000080U)  /*!< DMA error */
+#define HAL_SAI_ERROR_NONE             0x00000000U  /*!< No error */
+#define HAL_SAI_ERROR_OVR              0x00000001U  /*!< Overrun Error */
+#define HAL_SAI_ERROR_UDR              0x00000002U  /*!< Underrun error */
+#define HAL_SAI_ERROR_AFSDET           0x00000004U  /*!< Anticipated Frame synchronisation detection */
+#define HAL_SAI_ERROR_LFSDET           0x00000008U  /*!< Late Frame synchronisation detection */
+#define HAL_SAI_ERROR_CNREADY          0x00000010U  /*!< codec not ready */
+#define HAL_SAI_ERROR_WCKCFG           0x00000020U  /*!< Wrong clock configuration */
+#define HAL_SAI_ERROR_TIMEOUT          0x00000040U  /*!< Timeout error */
+#define HAL_SAI_ERROR_DMA              0x00000080U  /*!< DMA error */
 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
-#define HAL_SAI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U)  /*!< Invalid callback error */
+#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U  /*!< Invalid callback error */
 #endif
 /**
   * @}
@@ -304,9 +308,9 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_SyncExt SAI External synchronisation
   * @{
   */
-#define SAI_SYNCEXT_DISABLE          0
-#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1
-#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2
+#define SAI_SYNCEXT_DISABLE          0U
+#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
+#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U
 /**
   * @}
   */
@@ -314,8 +318,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output
   * @{
   */
-#define SAI_MCK_OUTPUT_DISABLE      ((uint32_t)0x00000000U)
-#define SAI_MCK_OUTPUT_ENABLE       ((uint32_t)SAI_xCR1_MCKEN)
+#define SAI_MCK_OUTPUT_DISABLE      0x00000000U
+#define SAI_MCK_OUTPUT_ENABLE       SAI_xCR1_MCKEN
 /**
   * @}
   */
@@ -323,11 +327,11 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Protocol SAI Supported protocol
   * @{
   */
-#define SAI_I2S_STANDARD      0
-#define SAI_I2S_MSBJUSTIFIED  1
-#define SAI_I2S_LSBJUSTIFIED  2
-#define SAI_PCM_LONG          3
-#define SAI_PCM_SHORT         4
+#define SAI_I2S_STANDARD      0U
+#define SAI_I2S_MSBJUSTIFIED  1U
+#define SAI_I2S_LSBJUSTIFIED  2U
+#define SAI_PCM_LONG          3U
+#define SAI_PCM_SHORT         4U
 /**
   * @}
   */
@@ -335,10 +339,10 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Protocol_DataSize SAI protocol data size
   * @{
   */
-#define SAI_PROTOCOL_DATASIZE_16BIT         0
-#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1
-#define SAI_PROTOCOL_DATASIZE_24BIT         2
-#define SAI_PROTOCOL_DATASIZE_32BIT         3
+#define SAI_PROTOCOL_DATASIZE_16BIT         0U
+#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
+#define SAI_PROTOCOL_DATASIZE_24BIT         2U
+#define SAI_PROTOCOL_DATASIZE_32BIT         3U
 /**
   * @}
   */
@@ -346,16 +350,16 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Audio_Frequency SAI Audio Frequency
   * @{
   */
-#define SAI_AUDIO_FREQUENCY_192K          ((uint32_t)192000U)
-#define SAI_AUDIO_FREQUENCY_96K           ((uint32_t)96000U)
-#define SAI_AUDIO_FREQUENCY_48K           ((uint32_t)48000U)
-#define SAI_AUDIO_FREQUENCY_44K           ((uint32_t)44100U)
-#define SAI_AUDIO_FREQUENCY_32K           ((uint32_t)32000U)
-#define SAI_AUDIO_FREQUENCY_22K           ((uint32_t)22050U)
-#define SAI_AUDIO_FREQUENCY_16K           ((uint32_t)16000U)
-#define SAI_AUDIO_FREQUENCY_11K           ((uint32_t)11025U)
-#define SAI_AUDIO_FREQUENCY_8K            ((uint32_t)8000U)
-#define SAI_AUDIO_FREQUENCY_MCKDIV        ((uint32_t)0U)
+#define SAI_AUDIO_FREQUENCY_192K          192000U
+#define SAI_AUDIO_FREQUENCY_96K           96000U
+#define SAI_AUDIO_FREQUENCY_48K           48000U
+#define SAI_AUDIO_FREQUENCY_44K           44100U
+#define SAI_AUDIO_FREQUENCY_32K           32000U
+#define SAI_AUDIO_FREQUENCY_22K           22050U
+#define SAI_AUDIO_FREQUENCY_16K           16000U
+#define SAI_AUDIO_FREQUENCY_11K           11025U
+#define SAI_AUDIO_FREQUENCY_8K            8000U
+#define SAI_AUDIO_FREQUENCY_MCKDIV        0U
 /**
   * @}
   */
@@ -363,8 +367,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling
   * @{
   */
-#define SAI_MCK_OVERSAMPLING_DISABLE  ((uint32_t)0x00000000U)
-#define SAI_MCK_OVERSAMPLING_ENABLE   ((uint32_t)SAI_xCR1_OSR)
+#define SAI_MCK_OVERSAMPLING_DISABLE      0x00000000U
+#define SAI_MCK_OVERSAMPLING_ENABLE       SAI_xCR1_OSR
 /**
   * @}
   */
@@ -372,9 +376,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable
   * @{
   */
-#define SAI_PDM_CLOCK1_ENABLE  ((uint32_t)SAI_PDMCR_CKEN1)
-#define SAI_PDM_CLOCK2_ENABLE  ((uint32_t)SAI_PDMCR_CKEN2)
-
+#define SAI_PDM_CLOCK1_ENABLE     SAI_PDMCR_CKEN1
+#define SAI_PDM_CLOCK2_ENABLE     SAI_PDMCR_CKEN2
 /**
   * @}
   */
@@ -382,10 +385,10 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Mode SAI Block Mode
   * @{
   */
-#define SAI_MODEMASTER_TX         ((uint32_t)0x00000000U)
-#define SAI_MODEMASTER_RX         ((uint32_t)SAI_xCR1_MODE_0)
-#define SAI_MODESLAVE_TX          ((uint32_t)SAI_xCR1_MODE_1)
-#define SAI_MODESLAVE_RX          ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
+#define SAI_MODEMASTER_TX         0x00000000U
+#define SAI_MODEMASTER_RX         SAI_xCR1_MODE_0
+#define SAI_MODESLAVE_TX          SAI_xCR1_MODE_1
+#define SAI_MODESLAVE_RX          (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)
 
 /**
   * @}
@@ -394,9 +397,9 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Protocol SAI Block Protocol
   * @{
   */
-#define SAI_FREE_PROTOCOL                 ((uint32_t)0x00000000U)
-#define SAI_SPDIF_PROTOCOL                ((uint32_t)SAI_xCR1_PRTCFG_0)
-#define SAI_AC97_PROTOCOL                 ((uint32_t)SAI_xCR1_PRTCFG_1)
+#define SAI_FREE_PROTOCOL                 0x00000000U
+#define SAI_SPDIF_PROTOCOL                SAI_xCR1_PRTCFG_0
+#define SAI_AC97_PROTOCOL                 SAI_xCR1_PRTCFG_1
 /**
   * @}
   */
@@ -404,12 +407,12 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Data_Size SAI Block Data Size
   * @{
   */
-#define SAI_DATASIZE_8     ((uint32_t)SAI_xCR1_DS_1)
-#define SAI_DATASIZE_10    ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
-#define SAI_DATASIZE_16    ((uint32_t)SAI_xCR1_DS_2)
-#define SAI_DATASIZE_20    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
-#define SAI_DATASIZE_24    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
-#define SAI_DATASIZE_32    ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
+#define SAI_DATASIZE_8     SAI_xCR1_DS_1
+#define SAI_DATASIZE_10    (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
+#define SAI_DATASIZE_16    SAI_xCR1_DS_2
+#define SAI_DATASIZE_20    (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
+#define SAI_DATASIZE_24    (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
+#define SAI_DATASIZE_32    (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
 /**
   * @}
   */
@@ -417,8 +420,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
   * @{
   */
-#define SAI_FIRSTBIT_MSB                  ((uint32_t)0x00000000U)
-#define SAI_FIRSTBIT_LSB                  ((uint32_t)SAI_xCR1_LSBFIRST)
+#define SAI_FIRSTBIT_MSB                  0x00000000U
+#define SAI_FIRSTBIT_LSB                  SAI_xCR1_LSBFIRST
 /**
   * @}
   */
@@ -426,8 +429,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
   * @{
   */
-#define SAI_CLOCKSTROBING_FALLINGEDGE     0
-#define SAI_CLOCKSTROBING_RISINGEDGE      1
+#define SAI_CLOCKSTROBING_FALLINGEDGE     0U
+#define SAI_CLOCKSTROBING_RISINGEDGE      1U
 /**
   * @}
   */
@@ -435,10 +438,16 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Synchronization SAI Block Synchronization
   * @{
   */
-#define SAI_ASYNCHRONOUS                  0 /*!< Asynchronous */
-#define SAI_SYNCHRONOUS                   1 /*!< Synchronous with other block of same SAI */
-#define SAI_SYNCHRONOUS_EXT_SAI1          2 /*!< Synchronous with other SAI, SAI1 */
-#define SAI_SYNCHRONOUS_EXT_SAI2          3 /*!< Synchronous with other SAI, SAI2 */
+#define SAI_ASYNCHRONOUS                  0U /*!< Asynchronous */
+#define SAI_SYNCHRONOUS                   1U /*!< Synchronous with other block of same SAI */
+#define SAI_SYNCHRONOUS_EXT_SAI1          2U /*!< Synchronous with other SAI, SAI1 */
+#define SAI_SYNCHRONOUS_EXT_SAI2          3U /*!< Synchronous with other SAI, SAI2 */
+#if defined(SAI3)
+#define SAI_SYNCHRONOUS_EXT_SAI3          4U /*!< Synchronous with other SAI, SAI3 */
+#endif
+#if defined(SAI4)
+#define SAI_SYNCHRONOUS_EXT_SAI4          5U /*!< Synchronous with other SAI, SAI4 */
+#endif
 /**
   * @}
   */
@@ -446,8 +455,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
   * @{
   */
-#define SAI_OUTPUTDRIVE_DISABLE          ((uint32_t)0x00000000U)
-#define SAI_OUTPUTDRIVE_ENABLE           ((uint32_t)SAI_xCR1_OUTDRIV)
+#define SAI_OUTPUTDRIVE_DISABLE          0x00000000U
+#define SAI_OUTPUTDRIVE_ENABLE           SAI_xCR1_OUTDRIV
 /**
   * @}
   */
@@ -455,8 +464,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_NoDivider SAI Block NoDivider
   * @{
   */
-#define SAI_MASTERDIVIDER_ENABLE         ((uint32_t)0x00000000U)
-#define SAI_MASTERDIVIDER_DISABLE        ((uint32_t)SAI_xCR1_NODIV)
+#define SAI_MASTERDIVIDER_ENABLE         0x00000000U
+#define SAI_MASTERDIVIDER_DISABLE        SAI_xCR1_NODIV
 /**
   * @}
   */
@@ -464,8 +473,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
   * @{
   */
-#define SAI_FS_STARTFRAME                 ((uint32_t)0x00000000U)
-#define SAI_FS_CHANNEL_IDENTIFICATION     ((uint32_t)SAI_xFRCR_FSDEF)
+#define SAI_FS_STARTFRAME                 0x00000000U
+#define SAI_FS_CHANNEL_IDENTIFICATION     SAI_xFRCR_FSDEF
 /**
   * @}
   */
@@ -473,8 +482,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
   * @{
   */
-#define SAI_FS_ACTIVE_LOW                  ((uint32_t)0x00000000U)
-#define SAI_FS_ACTIVE_HIGH                 ((uint32_t)SAI_xFRCR_FSPOL)
+#define SAI_FS_ACTIVE_LOW                  0x00000000U
+#define SAI_FS_ACTIVE_HIGH                 SAI_xFRCR_FSPOL
 /**
   * @}
   */
@@ -482,8 +491,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
   * @{
   */
-#define SAI_FS_FIRSTBIT                   ((uint32_t)0x00000000U)
-#define SAI_FS_BEFOREFIRSTBIT             ((uint32_t)SAI_xFRCR_FSOFF)
+#define SAI_FS_FIRSTBIT                   0x00000000U
+#define SAI_FS_BEFOREFIRSTBIT             SAI_xFRCR_FSOFF
 /**
   * @}
   */
@@ -491,9 +500,9 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
   * @{
   */
-#define SAI_SLOTSIZE_DATASIZE             ((uint32_t)0x00000000U)
-#define SAI_SLOTSIZE_16B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
-#define SAI_SLOTSIZE_32B                  ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
+#define SAI_SLOTSIZE_DATASIZE             0x00000000U
+#define SAI_SLOTSIZE_16B                  SAI_xSLOTR_SLOTSZ_0
+#define SAI_SLOTSIZE_32B                  SAI_xSLOTR_SLOTSZ_1
 /**
   * @}
   */
@@ -501,24 +510,24 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
   * @{
   */
-#define SAI_SLOT_NOTACTIVE           ((uint32_t)0x00000000U)
-#define SAI_SLOTACTIVE_0             ((uint32_t)0x00000001U)
-#define SAI_SLOTACTIVE_1             ((uint32_t)0x00000002U)
-#define SAI_SLOTACTIVE_2             ((uint32_t)0x00000004U)
-#define SAI_SLOTACTIVE_3             ((uint32_t)0x00000008U)
-#define SAI_SLOTACTIVE_4             ((uint32_t)0x00000010U)
-#define SAI_SLOTACTIVE_5             ((uint32_t)0x00000020U)
-#define SAI_SLOTACTIVE_6             ((uint32_t)0x00000040U)
-#define SAI_SLOTACTIVE_7             ((uint32_t)0x00000080U)
-#define SAI_SLOTACTIVE_8             ((uint32_t)0x00000100U)
-#define SAI_SLOTACTIVE_9             ((uint32_t)0x00000200U)
-#define SAI_SLOTACTIVE_10            ((uint32_t)0x00000400U)
-#define SAI_SLOTACTIVE_11            ((uint32_t)0x00000800U)
-#define SAI_SLOTACTIVE_12            ((uint32_t)0x00001000U)
-#define SAI_SLOTACTIVE_13            ((uint32_t)0x00002000U)
-#define SAI_SLOTACTIVE_14            ((uint32_t)0x00004000U)
-#define SAI_SLOTACTIVE_15            ((uint32_t)0x00008000U)
-#define SAI_SLOTACTIVE_ALL           ((uint32_t)0x0000FFFFU)
+#define SAI_SLOT_NOTACTIVE           0x00000000U
+#define SAI_SLOTACTIVE_0             0x00000001U
+#define SAI_SLOTACTIVE_1             0x00000002U
+#define SAI_SLOTACTIVE_2             0x00000004U
+#define SAI_SLOTACTIVE_3             0x00000008U
+#define SAI_SLOTACTIVE_4             0x00000010U
+#define SAI_SLOTACTIVE_5             0x00000020U
+#define SAI_SLOTACTIVE_6             0x00000040U
+#define SAI_SLOTACTIVE_7             0x00000080U
+#define SAI_SLOTACTIVE_8             0x00000100U
+#define SAI_SLOTACTIVE_9             0x00000200U
+#define SAI_SLOTACTIVE_10            0x00000400U
+#define SAI_SLOTACTIVE_11            0x00000800U
+#define SAI_SLOTACTIVE_12            0x00001000U
+#define SAI_SLOTACTIVE_13            0x00002000U
+#define SAI_SLOTACTIVE_14            0x00004000U
+#define SAI_SLOTACTIVE_15            0x00008000U
+#define SAI_SLOTACTIVE_ALL           0x0000FFFFU
 /**
   * @}
   */
@@ -526,8 +535,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
   * @{
   */
-#define SAI_STEREOMODE               ((uint32_t)0x00000000U)
-#define SAI_MONOMODE                 ((uint32_t)SAI_xCR1_MONO)
+#define SAI_STEREOMODE               0x00000000U
+#define SAI_MONOMODE                 SAI_xCR1_MONO
 /**
   * @}
   */
@@ -535,8 +544,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_TRIState_Management SAI TRIState Management
   * @{
   */
-#define SAI_OUTPUT_NOTRELEASED    ((uint32_t)0x00000000U)
-#define SAI_OUTPUT_RELEASED       ((uint32_t)SAI_xCR2_TRIS)
+#define SAI_OUTPUT_NOTRELEASED    0x00000000U
+#define SAI_OUTPUT_RELEASED       SAI_xCR2_TRIS
 /**
   * @}
   */
@@ -544,11 +553,11 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
   * @{
   */
-#define SAI_FIFOTHRESHOLD_EMPTY  ((uint32_t)0x00000000U)
-#define SAI_FIFOTHRESHOLD_1QF    ((uint32_t)(SAI_xCR2_FTH_0))
-#define SAI_FIFOTHRESHOLD_HF     ((uint32_t)(SAI_xCR2_FTH_1))
-#define SAI_FIFOTHRESHOLD_3QF    ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
-#define SAI_FIFOTHRESHOLD_FULL   ((uint32_t)(SAI_xCR2_FTH_2))
+#define SAI_FIFOTHRESHOLD_EMPTY  0x00000000U
+#define SAI_FIFOTHRESHOLD_1QF    SAI_xCR2_FTH_0
+#define SAI_FIFOTHRESHOLD_HF     SAI_xCR2_FTH_1
+#define SAI_FIFOTHRESHOLD_3QF    (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
+#define SAI_FIFOTHRESHOLD_FULL   SAI_xCR2_FTH_2
 /**
   * @}
   */
@@ -556,11 +565,11 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
   * @{
   */
-#define SAI_NOCOMPANDING                 ((uint32_t)0x00000000U)
-#define SAI_ULAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1))
-#define SAI_ALAW_1CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
-#define SAI_ULAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
-#define SAI_ALAW_2CPL_COMPANDING         ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
+#define SAI_NOCOMPANDING                 0x00000000U
+#define SAI_ULAW_1CPL_COMPANDING         SAI_xCR2_COMP_1
+#define SAI_ALAW_1CPL_COMPANDING         (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
+#define SAI_ULAW_2CPL_COMPANDING         (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
+#define SAI_ALAW_2CPL_COMPANDING         (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)
 /**
   * @}
   */
@@ -568,8 +577,8 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
   * @{
   */
-#define SAI_ZERO_VALUE                     ((uint32_t)0x00000000U)
-#define SAI_LAST_SENT_VALUE                ((uint32_t)SAI_xCR2_MUTEVAL)
+#define SAI_ZERO_VALUE                     0x00000000U
+#define SAI_LAST_SENT_VALUE                SAI_xCR2_MUTEVAL
 /**
   * @}
   */
@@ -577,13 +586,13 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
   * @{
   */
-#define SAI_IT_OVRUDR                     ((uint32_t)SAI_xIMR_OVRUDRIE)
-#define SAI_IT_MUTEDET                    ((uint32_t)SAI_xIMR_MUTEDETIE)
-#define SAI_IT_WCKCFG                     ((uint32_t)SAI_xIMR_WCKCFGIE)
-#define SAI_IT_FREQ                       ((uint32_t)SAI_xIMR_FREQIE)
-#define SAI_IT_CNRDY                      ((uint32_t)SAI_xIMR_CNRDYIE)
-#define SAI_IT_AFSDET                     ((uint32_t)SAI_xIMR_AFSDETIE)
-#define SAI_IT_LFSDET                     ((uint32_t)SAI_xIMR_LFSDETIE)
+#define SAI_IT_OVRUDR                     SAI_xIMR_OVRUDRIE
+#define SAI_IT_MUTEDET                    SAI_xIMR_MUTEDETIE
+#define SAI_IT_WCKCFG                     SAI_xIMR_WCKCFGIE
+#define SAI_IT_FREQ                       SAI_xIMR_FREQIE
+#define SAI_IT_CNRDY                      SAI_xIMR_CNRDYIE
+#define SAI_IT_AFSDET                     SAI_xIMR_AFSDETIE
+#define SAI_IT_LFSDET                     SAI_xIMR_LFSDETIE
 /**
   * @}
   */
@@ -591,13 +600,13 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition
   * @{
   */
-#define SAI_FLAG_OVRUDR                   ((uint32_t)SAI_xSR_OVRUDR)
-#define SAI_FLAG_MUTEDET                  ((uint32_t)SAI_xSR_MUTEDET)
-#define SAI_FLAG_WCKCFG                   ((uint32_t)SAI_xSR_WCKCFG)
-#define SAI_FLAG_FREQ                     ((uint32_t)SAI_xSR_FREQ)
-#define SAI_FLAG_CNRDY                    ((uint32_t)SAI_xSR_CNRDY)
-#define SAI_FLAG_AFSDET                   ((uint32_t)SAI_xSR_AFSDET)
-#define SAI_FLAG_LFSDET                   ((uint32_t)SAI_xSR_LFSDET)
+#define SAI_FLAG_OVRUDR                   SAI_xSR_OVRUDR
+#define SAI_FLAG_MUTEDET                  SAI_xSR_MUTEDET
+#define SAI_FLAG_WCKCFG                   SAI_xSR_WCKCFG
+#define SAI_FLAG_FREQ                     SAI_xSR_FREQ
+#define SAI_FLAG_CNRDY                    SAI_xSR_CNRDY
+#define SAI_FLAG_AFSDET                   SAI_xSR_AFSDET
+#define SAI_FLAG_LFSDET                   SAI_xSR_LFSDET
 /**
   * @}
   */
@@ -605,12 +614,12 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level
   * @{
   */
-#define SAI_FIFOSTATUS_EMPTY              ((uint32_t)0x00000000U)
-#define SAI_FIFOSTATUS_LESS1QUARTERFULL   ((uint32_t)0x00010000U)
-#define SAI_FIFOSTATUS_1QUARTERFULL       ((uint32_t)0x00020000U)
-#define SAI_FIFOSTATUS_HALFFULL           ((uint32_t)0x00030000U)
-#define SAI_FIFOSTATUS_3QUARTERFULL       ((uint32_t)0x00040000U)
-#define SAI_FIFOSTATUS_FULL               ((uint32_t)0x00050000U)
+#define SAI_FIFOSTATUS_EMPTY              0x00000000U
+#define SAI_FIFOSTATUS_LESS1QUARTERFULL   0x00010000U
+#define SAI_FIFOSTATUS_1QUARTERFULL       0x00020000U
+#define SAI_FIFOSTATUS_HALFFULL           0x00030000U
+#define SAI_FIFOSTATUS_3QUARTERFULL       0x00040000U
+#define SAI_FIFOSTATUS_FULL               0x00050000U
 /**
   * @}
   */
@@ -815,7 +824,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
   */
 
 /* Private macros ------------------------------------------------------------*/
-/** @addtogroup SAI_Private_Macros
+/** @defgroup SAI_Private_Macros SAI Private Macros
   * @{
   */
 #define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
@@ -842,7 +851,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
 #define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
                                               ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))
 
-#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE)   ((1U <= (VALUE)) && ((VALUE) <= 3U))
+#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE)   ((1U <= (VALUE)) && ((VALUE) <= 4U))
 
 #define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \
                                        (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U))
@@ -869,10 +878,19 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
 #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
                                             ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
 
-#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
-                                       ((SYNCHRO) == SAI_SYNCHRONOUS)          || \
-                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
+#if defined(SAI3) && defined(SAI4)
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)          || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS)           || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1)  || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)  || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI3)  || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI4))
+#else
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)          || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS)           || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1)  || \
                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
+#endif
 
 #define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
                                         ((VALUE) == SAI_MCK_OUTPUT_DISABLE))
@@ -883,7 +901,7 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
 #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
                                            ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
 
-#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
 
 #define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \
                                            ((VALUE) == SAI_LAST_SENT_VALUE))
@@ -908,13 +926,13 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
 
 #define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
 
-#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
 
 #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
                                       ((SIZE) == SAI_SLOTSIZE_16B)      || \
                                       ((SIZE) == SAI_SLOTSIZE_32B))
 
-#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
 
 #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
                                         ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
@@ -925,11 +943,11 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
 #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
                                                 ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
 
-#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63)
+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
 
-#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
 
-#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
 
 /**
   * @}

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smartcard.h

@@ -0,0 +1,1074 @@
+/**
+  ******************************************************************************
+  * @file    stm32mp1xx_hal_smartcard.h
+  * @author  MCD Application Team
+  * @version $VERSION$
+  * @date    $DATE$
+  * @brief   Header file of SMARTCARD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32MP1xx_HAL_SMARTCARD_H
+#define __STM32MP1xx_HAL_SMARTCARD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMARTCARD
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
+  * @{
+  */
+
+/**
+  * @brief SMARTCARD Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.
+                                           The baud rate register is computed using the following formula:
+                                              Baud Rate Register = ((PCLKx) / ((hsmartcard->Init.BaudRate))) */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits.
+                                           This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
+
+  uint16_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref SMARTCARD_Parity
+                                           @note The parity is enabled by default (PCE is forced to 1).
+                                                 Since the WordLength is forced to 8 bits + parity, M is
+                                                 forced to 1 and the parity bit is the 9th bit. */
+
+  uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref SMARTCARD_Mode */
+
+  uint16_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
+
+  uint16_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref SMARTCARD_Clock_Phase */
+
+  uint16_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref SMARTCARD_Last_Bit */
+
+  uint16_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.
+                                           Selecting the single sample method increases the receiver tolerance to clock
+                                           deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */
+
+  uint8_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler. */
+
+  uint8_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time applied after stop bits. */
+
+  uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled
+                                           in case of parity error.
+                                           This parameter can be a value of @ref SMARTCARD_NACK_Enable */
+
+  uint32_t TimeOutEnable;             /*!< Specifies whether the receiver timeout is enabled.
+                                            This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
+
+  uint32_t TimeOutValue;              /*!< Specifies the receiver time out value in number of baud blocks:
+                                           it is used to implement the Character Wait Time (CWT) and
+                                           Block Wait Time (BWT). It is coded over 24 bits. */
+
+  uint8_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
+                                           This parameter can be any value from 0x0 to 0xFF */
+
+  uint8_t AutoRetryCount;             /*!< Specifies the SmartCard auto-retry count (number of retries in
+                                            receive and transmit mode). When set to 0, retransmission is
+                                            disabled. Otherwise, its maximum value is 7 (before signalling
+                                            an error) */
+
+  uint32_t FIFOMode;                  /*!< Specifies if the FIFO mode will be used. This parameter can be a value
+                                           of @ref SMARTCARD_FIFO_mode */
+
+  uint32_t TXFIFOThreshold;           /*!< Specifies the TXFIFO threshold level.
+                                           This parameter can be a value of @ref SMARTCARD_TXFIFO_threshold_level */
+
+  uint32_t RXFIFOThreshold;           /*!< Specifies the RXFIFO threshold level.
+                                           This parameter can be a value of @ref SMARTCARD_RXFIFO_threshold_level */
+
+}SMARTCARD_InitTypeDef;
+
+/**
+  * @brief  SMARTCARD advanced features initalization structure definition
+  */
+typedef struct
+{
+  uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several
+                                           advanced features may be initialized at the same time. This parameter
+                                           can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
+
+  uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.
+                                           This parameter can be a value of @ref SMARTCARD_Tx_Inv  */
+
+  uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.
+                                           This parameter can be a value of @ref SMARTCARD_Rx_Inv  */
+
+  uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic
+                                           vs negative/inverted logic).
+                                           This parameter can be a value of @ref SMARTCARD_Data_Inv */
+
+  uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.
+                                           This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
+
+  uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.
+                                           This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
+
+  uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.
+                                           This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
+
+  uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.
+                                           This parameter can be a value of @ref SMARTCARD_MSB_First */
+                                           
+  uint16_t TxCompletionIndication;     /*!< Specifies which transmission completion indication is used: before (when 
+                                            relevant flag is available) or once guard time period has elapsed.
+                                           This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */                                            
+}SMARTCARD_AdvFeatureInitTypeDef;
+
+/**
+  * @brief HAL SMARTCARD State structures definition
+  * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains SMARTCARD state information related to global Handle management 
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information 
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized. HAL SMARTCARD Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (IP busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     IP initilisation status
+  *             0  : Reset (IP not initialized)
+  *             1  : Init done (IP not initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef enum
+{
+  HAL_SMARTCARD_STATE_RESET             = 0x00U,   /*!< Peripheral is not initialized
+                                                        Value is allowed for gState and RxState */
+  HAL_SMARTCARD_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use
+                                                        Value is allowed for gState and RxState */
+  HAL_SMARTCARD_STATE_BUSY              = 0x24U,   /*!< an internal process is ongoing
+                                                        Value is allowed for gState only */
+  HAL_SMARTCARD_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing
+                                                        Value is allowed for gState only */
+  HAL_SMARTCARD_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing
+                                                        Value is allowed for RxState only */
+  HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x23U,   /*!< Data Transmission and Reception process is ongoing
+                                                        Not to be used for neither gState nor RxState.
+                                                        Value is result of combination (Or) between gState and RxState values */
+  HAL_SMARTCARD_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state
+                                                        Value is allowed for gState only */
+  HAL_SMARTCARD_STATE_ERROR             = 0xE0U    /*!< Error
+                                                        Value is allowed for gState only */
+}HAL_SMARTCARD_StateTypeDef;
+
+/**
+  * @brief  HAL SMARTCARD Error Code structure definition
+  */
+typedef enum
+{
+  HAL_SMARTCARD_ERROR_NONE      = 0x00,    /*!< No error                */
+  HAL_SMARTCARD_ERROR_PE        = 0x01,    /*!< Parity error            */
+  HAL_SMARTCARD_ERROR_NE        = 0x02,    /*!< Noise error             */
+  HAL_SMARTCARD_ERROR_FE        = 0x04,    /*!< frame error             */
+  HAL_SMARTCARD_ERROR_ORE       = 0x08,    /*!< Overrun error           */
+  HAL_SMARTCARD_ERROR_DMA       = 0x10,    /*!< DMA transfer error      */
+  HAL_SMARTCARD_ERROR_UDR       = 0x11,    /*!< SPI UnderRun error      */
+  HAL_SMARTCARD_ERROR_RTO       = 0x20     /*!< Receiver TimeOut error  */
+}HAL_SMARTCARD_ErrorTypeDef;
+
+/**
+  * @brief  SMARTCARD handle Structure definition
+  */
+typedef struct
+{
+  USART_TypeDef                   *Instance;        /*!< USART registers base address                          */
+
+  SMARTCARD_InitTypeDef           Init;             /*!< SmartCard communication parameters                    */
+
+  SMARTCARD_AdvFeatureInitTypeDef AdvancedInit;     /*!< SmartCard advanced features initialization parameters */
+
+  uint8_t                         *pTxBuffPtr;      /*!< Pointer to SmartCard Tx transfer Buffer               */
+
+  uint16_t                        TxXferSize;       /*!< SmartCard Tx Transfer size                            */
+
+  __IO uint16_t                   TxXferCount;      /*!< SmartCard Tx Transfer Counter                         */
+
+  uint8_t                         *pRxBuffPtr;      /*!< Pointer to SmartCard Rx transfer Buffer               */
+
+  uint16_t                        RxXferSize;       /*!< SmartCard Rx Transfer size                            */
+
+  __IO uint16_t                   RxXferCount;      /*!< SmartCard Rx Transfer Counter                         */
+
+  DMA_HandleTypeDef               *hdmatx;          /*!< SmartCard Tx DMA Handle parameters                    */
+
+  DMA_HandleTypeDef               *hdmarx;          /*!< SmartCard Rx DMA Handle parameters                    */
+
+  HAL_LockTypeDef                 Lock;             /*!< Locking object                                        */
+
+  __IO HAL_SMARTCARD_StateTypeDef    gState;        /*!< SmartCard state information related to global Handle management 
+                                                         and also related to Tx operations.
+                                                         This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+
+  __IO HAL_SMARTCARD_StateTypeDef    RxState;       /*!< SmartCard state information related to Rx operations.
+                                                         This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */
+
+  uint32_t                        ErrorCode;        /*!< SmartCard Error code                                  */
+
+}SMARTCARD_HandleTypeDef;
+
+/**
+  * @brief  SMARTCARD clock sources
+  */
+typedef enum
+{
+  SMARTCARD_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */
+  SMARTCARD_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */
+  SMARTCARD_CLOCKSOURCE_PCLK5      = 0x02U,    /*!< PCLK5 clock source  (only used by USART1) */
+  SMARTCARD_CLOCKSOURCE_PLL3Q      = 0x04U,    /*!< PLL3Q clock source  (only used by USART1) */
+  SMARTCARD_CLOCKSOURCE_PLL4Q      = 0x08U,    /*!< PLL4Q clock source  */
+  SMARTCARD_CLOCKSOURCE_HSI        = 0x10U,    /*!< HSI clock source    */
+  SMARTCARD_CLOCKSOURCE_CSI        = 0x20U,    /*!< CSI clock source    */
+  SMARTCARD_CLOCKSOURCE_HSE        = 0x40U,    /*!< HSE clock source    */
+  SMARTCARD_CLOCKSOURCE_UNDEFINED  = 0x80U     /*!< Undefined clock source */
+}SMARTCARD_ClockSourceTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported Constants
+  * @{
+  */
+
+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
+  * @{
+  */
+#define SMARTCARD_WORDLENGTH_9B             ((uint32_t)USART_CR1_M0)              /*!< SMARTCARD frame length */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
+  * @{
+  */
+#define SMARTCARD_STOPBITS_0_5              ((uint32_t)USART_CR2_STOP_0)                      /*!< SMARTCARD frame with 0.5 stop bit  */
+#define SMARTCARD_STOPBITS_1_5              ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1)) /*!< SMARTCARD frame with 1.5 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Parity SMARTCARD Parity
+  * @{
+  */
+#define SMARTCARD_PARITY_EVEN               ((uint32_t)USART_CR1_PCE)                  /*!< SMARTCARD frame even parity */
+#define SMARTCARD_PARITY_ODD                ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< SMARTCARD frame odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
+  * @{
+  */
+#define SMARTCARD_MODE_RX                   ((uint32_t)USART_CR1_RE)                  /*!< SMARTCARD RX mode        */
+#define SMARTCARD_MODE_TX                   ((uint32_t)USART_CR1_TE)                  /*!< SMARTCARD TX mode        */
+#define SMARTCARD_MODE_TX_RX                ((uint32_t)(USART_CR1_TE |USART_CR1_RE))  /*!< SMARTCARD RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
+  * @{
+  */
+#define SMARTCARD_POLARITY_LOW              ((uint32_t)0x00000000)                   /*!< SMARTCARD frame low polarity  */
+#define SMARTCARD_POLARITY_HIGH             ((uint32_t)USART_CR2_CPOL)               /*!< SMARTCARD frame high polarity */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
+  * @{
+  */
+#define SMARTCARD_PHASE_1EDGE               ((uint32_t)0x00000000)                  /*!< SMARTCARD frame phase on first clock transition  */
+#define SMARTCARD_PHASE_2EDGE               ((uint32_t)USART_CR2_CPHA)              /*!< SMARTCARD frame phase on second clock transition */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
+  * @{
+  */
+#define SMARTCARD_LASTBIT_DISABLE           ((uint32_t)0x00000000)                 /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
+#define SMARTCARD_LASTBIT_ENABLE            ((uint32_t)USART_CR2_LBCL)             /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin     */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_FIFO_mode SMARTCARD FIFO  mode
+  * @brief    SMARTCARD FIFO  mode
+  * @{
+  */
+#define SMARTCARD_FIFOMODE_DISABLE        ((uint32_t)0x00000000)        /*!< FIFO mode disable */
+#define SMARTCARD_FIFOMODE_ENABLE         ((uint32_t)USART_CR1_FIFOEN)  /*!< FIFO mode enable  */
+/**
+  * @}
+  */ 
+
+/** @defgroup SMARTCARD_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
+  * @brief    SMARTCARD TXFIFO level 
+  * @{
+  */
+#define SMARTCARD_TXFIFO_THRESHOLD_1EIGHTHFULL    ((uint32_t)0x00000000)                              /*!< TXFIFO threshold 1 eighth full configuration  */
+#define SMARTCARD_TXFIFO_THRESHOLD_1QUARTERFULL   ((uint32_t)USART_CR3_TXFTCFG_0)                     /*!< TXFIFO threshold 1 quart full configuration  */
+#define SMARTCARD_TXFIFO_THRESHOLD_HALFFULL       ((uint32_t)USART_CR3_TXFTCFG_1)                     /*!< TXFIFO threshold half full configuration     */
+#define SMARTCARD_TXFIFO_THRESHOLD_3QUARTERSFULL  ((uint32_t)(USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)) /*!< TXFIFO threshold 3 quarts full configuration */
+#define SMARTCARD_TXFIFO_THRESHOLD_7EIGHTHFULL    ((uint32_t)USART_CR3_TXFTCFG_2)                     /*!< TXFIFO threshold 7 eighth full configuration */
+#define SMARTCARD_TXFIFO_THRESHOLD_EMPTY          ((uint32_t)(USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)) /*!< TXFIFO becomes empty */
+/**
+  * @}
+  */
+   
+/** @defgroup SMARTCARD_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
+  * @brief    SMARTCARD RXFIFO level 
+  * @{
+  */
+#define SMARTCARD_RXFIFO_THRESHOLD_1EIGHTHFULL    ((uint32_t)0x00000000)                              /*!< RXFIFO threshold 1 eighth full configuration  */
+#define SMARTCARD_RXFIFO_THRESHOLD_1QUARTERFULL   ((uint32_t)USART_CR3_RXFTCFG_0)                     /*!< RXFIFO threshold 1 quart full configuration  */
+#define SMARTCARD_RXFIFO_THRESHOLD_HALFFULL       ((uint32_t)USART_CR3_RXFTCFG_1)                     /*!< RXFIFO threshold half full configuration     */
+#define SMARTCARD_RXFIFO_THRESHOLD_3QUARTERSFULL  ((uint32_t)(USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)) /*!< RXFIFO threshold 3 quarts full configuration */
+#define SMARTCARD_RXFIFO_THRESHOLD_7EIGHTHFULL    ((uint32_t)USART_CR3_RXFTCFG_2)                     /*!< RXFIFO threshold 7 eighth full configuration */
+#define SMARTCARD_RXFIFO_THRESHOLD_FULL           ((uint32_t)(USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)) /*!< RXFIFO becomes Full */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
+  * @{
+  */
+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    ((uint32_t)0x00000000)                 /*!< SMARTCARD frame one-bit sample disabled */
+#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     ((uint32_t)USART_CR3_ONEBIT)           /*!< SMARTCARD frame one-bit sample enabled  */
+/**
+  * @}
+  */
+
+
+/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
+  * @{
+  */
+#define SMARTCARD_NACK_ENABLE               ((uint32_t)USART_CR3_NACK)            /*!< SMARTCARD NACK transmission disabled */
+#define SMARTCARD_NACK_DISABLE              ((uint32_t)0x00000000)                /*!< SMARTCARD NACK transmission enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
+  * @{
+  */
+#define SMARTCARD_TIMEOUT_DISABLE           ((uint32_t)0x00000000)                /*!< SMARTCARD receiver timeout disabled */
+#define SMARTCARD_TIMEOUT_ENABLE            ((uint32_t)USART_CR2_RTOEN)           /*!< SMARTCARD receiver timeout enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE  ((uint32_t)0x00000000)                /*!< TX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE   ((uint32_t)USART_CR2_TXINV)           /*!< TX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE  ((uint32_t)0x00000000)                /*!< RX pin active level inversion disable */
+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE   ((uint32_t)USART_CR2_RXINV)           /*!< RX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE  ((uint32_t)0x00000000)              /*!< Binary data inversion disable */
+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE   ((uint32_t)USART_CR2_DATAINV)       /*!< Binary data inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE   ((uint32_t)0x00000000)                /*!< TX/RX pins swap disable */
+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE    ((uint32_t)USART_CR2_SWAP)            /*!< TX/RX pins swap enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   ((uint32_t)0x00000000)              /*!< RX overrun enable  */
+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  ((uint32_t)USART_CR3_OVRDIS)        /*!< RX overrun disable */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR   ((uint32_t)0x00000000)         /*!< DMA enable on Reception Error  */
+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR  ((uint32_t)USART_CR3_DDRE)     /*!< DMA disable on Reception Error */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_MSB_First   SMARTCARD advanced feature MSB first
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      ((uint32_t)0x00000000)           /*!< Most significant bit sent/received first disable */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       ((uint32_t)USART_CR2_MSBFIRST)   /*!< Most significant bit sent/received first enable  */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
+  * @{
+  */
+#define SMARTCARD_RXDATA_FLUSH_REQUEST      ((uint16_t)USART_RQR_RXFRQ)        /*!< Receive data flush request */
+#define SMARTCARD_TXDATA_FLUSH_REQUEST      ((uint16_t)USART_RQR_TXFRQ)        /*!< Transmit data flush request */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_CR3_SCARCNT_LSB_POS SMARTCARD auto retry counter LSB position in CR3 register
+  * @{
+  */
+#define SMARTCARD_CR3_SCARCNT_LSB_POS       ((uint32_t) 17)   /*!< SMARTCARD auto retry counter LSB position in CR3 register */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_GTPR_GT_LSB_POS SMARTCARD guard time value LSB position in GTPR register
+  * @{
+  */
+#define SMARTCARD_GTPR_GT_LSB_POS           ((uint32_t) 8)   /*!<  SMARTCARD guard time value LSB position in GTPR register */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_RTOR_BLEN_LSB_POS SMARTCARD block length LSB position in RTOR register
+  * @{
+  */
+#define SMARTCARD_RTOR_BLEN_LSB_POS         ((uint32_t) 24)  /*!< SMARTCARD block length LSB position in RTOR register */
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
+  * @{
+  */
+#define SMARTCARD_IT_MASK                   ((uint16_t)0x001F)   /*!< SMARTCARD interruptions flags mask */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros
+  * @{
+  */
+
+/** @brief  Reset SMARTCARD handle state.
+  * @param  __HANDLE__: SMARTCARD handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
+                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
+                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
+                                                          } while(0)
+
+/** @brief  Flush the Smartcard Data registers.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                                 \
+    do{                                                                              \
+      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
+      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
+      } while(0)
+
+/** @brief  Clear the specified SMARTCARD pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
+  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag
+  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
+  *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
+  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
+  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the SMARTCARD PE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
+
+
+/** @brief  Clear the SMARTCARD FE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
+
+/** @brief  Clear the SMARTCARD NE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
+
+/** @brief  Clear the SMARTCARD ORE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
+
+/** @brief  Clear the SMARTCARD IDLE pending flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
+
+/** @brief  Check whether the specified Smartcard flag is set or not.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag
+  *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref SMARTCARD_FLAG_BUSY  Busy flag
+  *            @arg @ref SMARTCARD_FLAG_EOBF  End of block flag
+  *            @arg @ref SMARTCARD_FLAG_RTOF  Receiver timeout flag
+  *            @arg @ref SMARTCARD_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref SMARTCARD_FLAG_TC    Transmission complete flag
+  *            @arg @ref SMARTCARD_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref SMARTCARD_FLAG_IDLE  Idle line detection flag  
+  *            @arg @ref SMARTCARD_FLAG_ORE   Overrun error flag
+  *            @arg @ref SMARTCARD_FLAG_NE    Noise error flag
+  *            @arg @ref SMARTCARD_FLAG_FE    Framing error flag
+  *            @arg @ref SMARTCARD_FLAG_PE    Parity error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+
+/** @brief  Enable the specified SmartCard interrupt.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
+  *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)             
+  *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt  
+  *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
+  *            @arg @ref SMARTCARD_IT_ERR   Error interrupt(frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+/** @brief  Disable the specified SmartCard interrupt.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
+  *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)   
+  *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt   
+  *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
+  *            @arg @ref SMARTCARD_IT_ERR   Error interrupt(frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
+                                                                ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
+
+
+/** @brief  Check whether the specified SmartCard interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __IT__: specifies the SMARTCARD interrupt to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
+  *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)    
+  *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt  
+  *            @arg @ref SMARTCARD_IT_ORE   Overrun error interrupt
+  *            @arg @ref SMARTCARD_IT_NE    Noise error interrupt
+  *            @arg @ref SMARTCARD_IT_FE    Framing error interrupt
+  *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
+
+/** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __IT__: specifies the SMARTCARD interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_IT_EOB   End of block interrupt
+  *            @arg @ref SMARTCARD_IT_RTO   Receive timeout interrupt
+  *            @arg @ref SMARTCARD_IT_TXE   Transmit data register empty interrupt
+  *            @arg @ref SMARTCARD_IT_TC    Transmission complete interrupt
+  *            @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available)     
+  *            @arg @ref SMARTCARD_IT_RXNE  Receive data register not empty interrupt
+  *            @arg @ref SMARTCARD_IT_IDLE  Idle line detection interrupt  
+  *            @arg @ref SMARTCARD_IT_ERR   Framing, overrun or noise error interrupt
+  *            @arg @ref SMARTCARD_IT_PE    Parity error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1 : \
+                                                           (((((uint8_t)(__IT__)) >> 5U) == 2)? (__HANDLE__)->Instance->CR2 : \
+                                                           (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & SMARTCARD_IT_MASK)))
+
+
+/** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt.
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag
+  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag
+  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detection clear flag    
+  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag
+  *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)     
+  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag
+  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Clear the SMARTCARD TX FIFO empty clear flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_CLEAR_TXFECF(__HANDLE__)   __HAL_SMARTCARD_CLEAR_IT((__HANDLE__), SMARTCARD_CLEAR_TXFECF)
+
+/** @brief  Set a specific SMARTCARD request flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __REQ__: specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
+  *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  *
+  * @retval None
+  */
+#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the SMARTCARD one bit sample method.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.  
+  * @retval None
+  */     
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the SMARTCARD one bit sample method.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.  
+  * @retval None
+  */      
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+
+/** @brief  Enable the USART associated to the SMARTCARD Handle.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+
+/** @brief  Disable the USART associated to the SMARTCARD Handle
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+
+/**
+  * @}
+  */
+
+/* Private macros -------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
+  * @{
+  */
+
+/** @brief  Check the Baud rate range.
+  * @param  __BAUDRATE__: Baudrate specified by the user.
+  *         The maximum Baud Rate is derived from the maximum clock on MP1 (i.e. 100 MHz)
+  *         divided by the smallest oversampling used on the SMARTCARD (i.e. 8).
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)
+
+/** @brief  Check the block length range.
+  * @note   The maximum SMARTCARD block length is 0xFF.
+  * @param  __LENGTH__: block length.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFF)
+
+/** @brief  Check the receiver timeout value. 
+  * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
+  * @param  __TIMEOUTVALUE__: receiver timeout value.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFF)
+
+/** @brief  Check the SMARTCARD autoretry counter value. 
+  * @note   The maximum number of retransmissions is 0x7.
+  * @param  __COUNT__: number of retransmissions.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7)
+
+/**
+  * @brief Ensure that SMARTCARD frame length is valid.
+  * @param __LENGTH__: SMARTCARD frame length. 
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */ 
+#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
+
+/**
+  * @brief Ensure that SMARTCARD frame number of stop bits is valid.
+  * @param __STOPBITS__: SMARTCARD frame number of stop bits. 
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */ 
+#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
+                                             ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
+
+/**
+  * @brief Ensure that SMARTCARD frame parity is valid.
+  * @param __PARITY__: SMARTCARD frame parity. 
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */ 
+#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
+                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))
+
+/**
+  * @brief Ensure that SMARTCARD communication mode is valid.
+  * @param __MODE__: SMARTCARD communication mode. 
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */ 
+#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & (uint16_t)0xFFF3) == 0x00) && ((__MODE__) != (uint16_t)0x00))
+
+/**
+  * @brief Ensure that SMARTCARD frame polarity is valid.
+  * @param __CPOL__: SMARTCARD frame polarity. 
+  * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
+  */ 
+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
+
+/**
+  * @brief Ensure that SMARTCARD frame phase is valid.
+  * @param __CPHA__: SMARTCARD frame phase. 
+  * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
+  */
+#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
+
+/**
+  * @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
+  * @param __LASTBIT__: SMARTCARD frame last bit clock pulse setting. 
+  * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
+  */
+#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
+                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame sampling is valid.
+  * @param __ONEBIT__: SMARTCARD frame sampling. 
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */
+#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
+                                                 ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD NACK transmission setting is valid.
+  * @param __NACK__: SMARTCARD NACK transmission setting. 
+  * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
+  */
+#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
+                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))
+
+/**
+  * @brief Ensure that SMARTCARD receiver timeout setting is valid.
+  * @param __TIMEOUT__: SMARTCARD receiver timeout setting. 
+  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+  */
+#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
+                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD advanced features initialization is valid.
+  * @param __INIT__: SMARTCARD advanced features initialization. 
+  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \
+                                                               SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \
+                                                               SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \
+                                                               SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \
+                                                               SMARTCARD_ADVFEATURE_SWAP_INIT              | \
+                                                               SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
+                                                               SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
+                                                               SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+  * @brief Ensure that SMARTCARD frame TX inversion setting is valid.
+  * @param __TXINV__: SMARTCARD frame TX inversion setting. 
+  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
+                                                  ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame RX inversion setting is valid.
+  * @param __RXINV__: SMARTCARD frame RX inversion setting. 
+  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
+                                                  ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame data inversion setting is valid.
+  * @param __DATAINV__: SMARTCARD frame data inversion setting. 
+  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
+                                                      ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
+  * @param __SWAP__: SMARTCARD frame RX/TX pins swap setting. 
+  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
+                                                ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD frame overrun setting is valid.
+  * @param __OVERRUN__: SMARTCARD frame overrun setting. 
+  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+  */
+#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
+                                           ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+  * @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
+  * @param __DMA__: SMARTCARD DMA enabling or disabling on error setting. 
+  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+                                                       ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+  * @brief Ensure that SMARTCARD frame MSB first setting is valid.
+  * @param __MSBFIRST__: SMARTCARD frame MSB first setting. 
+  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+  */
+#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
+                                                        ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD request parameter is valid.
+  * @param __PARAM__: SMARTCARD request parameter. 
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
+                                                   ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @brief Ensure that SMARTCARD FIFO mode is valid.
+  * @param __STATE__: SMARTCARD FIFO mode. 
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */
+#define IS_SMARTCARD_FIFO_MODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
+                                                 ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
+
+/**
+  * @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
+  * @param __THRESHOLD__: SMARTCARD TXFIFO threshold level. 
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1EIGHTHFULL )  || \
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1QUARTERFULL ) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_HALFFULL)      || \
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3QUARTERSFULL) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7EIGHTHFULL)   || \
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_EMPTY))
+
+/**
+  * @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
+  * @param __THRESHOLD__: SMARTCARD RXFIFO threshold level. 
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1EIGHTHFULL )  || \
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1QUARTERFULL ) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_HALFFULL)      || \
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3QUARTERSFULL) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7EIGHTHFULL)   || \
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_FULL))
+
+/**
+  * @}
+  */
+
+/* Include SMARTCARD HAL Extended module */
+#include "stm32mp1xx_hal_smartcard_ex.h"
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARD_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group1
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group2
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/* Peripheral Control functions ***********************************************/
+/* Peripheral State and Error functions ***************************************/
+/** @addtogroup SMARTCARD_Exported_Functions_Group4
+  * @{
+  */
+
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
+uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32MP1xx_HAL_SMARTCARD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_hal_smartcard_ex.h

@@ -0,0 +1,337 @@
+/**
+  ******************************************************************************
+  * @file    stm32mp1xx_hal_smartcard_ex.h
+  * @author  MCD Application Team
+  * @version $VERSION$
+  * @date    $DATE$
+  * @brief   Header file of SMARTCARD HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32MP1xx_HAL_SMARTCARD_EX_H
+#define __STM32MP1xx_HAL_SMARTCARD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal_def.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SMARTCARDEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/  
+/* Exported constants --------------------------------------------------------*/
+
+/** @addtogroup SMARTCARDEx_Exported_Constants  SMARTCARD Extended Exported Constants
+  * @{
+  */
+  
+/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
+  * @{
+  */
+#define SMARTCARD_TCBGT      SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
+#define SMARTCARD_TC         SMARTCARD_IT_TC    /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
+/**
+  * @}
+  */    
+  
+/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
+  * @{
+  */
+#define SMARTCARD_ADVFEATURE_NO_INIT                 ((uint32_t)0x00000000)    /*!< No advanced feature initialization                  */ 
+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT           ((uint32_t)0x00000001)    /*!< TX pin active level inversion                       */
+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT           ((uint32_t)0x00000002)    /*!< RX pin active level inversion                       */
+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         ((uint32_t)0x00000004)    /*!< Binary data inversion                               */
+#define SMARTCARD_ADVFEATURE_SWAP_INIT               ((uint32_t)0x00000008)    /*!< TX/RX pins swap                                     */
+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   ((uint32_t)0x00000010)    /*!< RX overrun disable                                  */
+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  ((uint32_t)0x00000020)    /*!< DMA disable on Reception Error                      */
+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           ((uint32_t)0x00000080)    /*!< Most significant bit sent/received first            */
+#define SMARTCARD_ADVFEATURE_TXCOMPLETION            ((uint32_t)0x00000100)    /*!< TX completion indication before of after guard time */
+/**
+  * @}
+  */
+
+
+  
+  
+/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define SMARTCARD_FLAG_TCBGT          USART_ISR_TCBGT      /*!< SMARTCARD transmission complete before guard time completion */
+#define SMARTCARD_FLAG_REACK          USART_ISR_REACK      /*!< SMARTCARD receive enable acknowledge flag  */
+#define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK      /*!< SMARTCARD transmit enable acknowledge flag */
+#define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY       /*!< SMARTCARD busy flag                        */
+#define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF       /*!< SMARTCARD end of block flag                */
+#define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF       /*!< SMARTCARD receiver timeout flag            */
+#define SMARTCARD_FLAG_TXE            USART_ISR_TXE        /*!< SMARTCARD transmit data register empty     */
+#define SMARTCARD_FLAG_TC             USART_ISR_TC         /*!< SMARTCARD transmission complete            */
+#define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE       /*!< SMARTCARD read data register not empty     */
+#define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE       /*!< SMARTCARD idle line detection              */
+#define SMARTCARD_FLAG_ORE            USART_ISR_ORE        /*!< SMARTCARD overrun error                    */
+#define SMARTCARD_FLAG_NE             USART_ISR_NE         /*!< SMARTCARD noise error                      */
+#define SMARTCARD_FLAG_FE             USART_ISR_FE         /*!< SMARTCARD frame error                      */
+#define SMARTCARD_FLAG_PE             USART_ISR_PE         /*!< SMARTCARD parity error                     */
+#define SMARTCARD_FLAG_TXFT           USART_ISR_TXFT       /*!< SMARTCARD TXFIFO threshold flag            */
+#define SMARTCARD_FLAG_RXFT           USART_ISR_RXFT       /*!< SMARTCARD RXFIFO threshold flag            */
+#define SMARTCARD_FLAG_RXFF           USART_ISR_RXFF       /*!< SMARTCARD RXFIFO Fullflag                  */
+#define SMARTCARD_FLAG_TXFE           USART_ISR_TXFE       /*!< SMARTCARD TXFIFO Empty flag                */
+
+/**
+  * @}
+  */
+  
+/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
+  *        Elements values convention: 000ZZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5 bits)
+  *           - XX  : Interrupt source register (2 bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZZ  : Flag position in the ISR register(5 bits)
+  * @{
+  */
+#define SMARTCARD_IT_PE                     ((uint16_t)0x0028)        /*!< SMARTCARD parity error interruption                 */
+#define SMARTCARD_IT_TXE                    ((uint16_t)0x0727)        /*!< SMARTCARD transmit data register empty interruption */
+#define SMARTCARD_IT_TC                     ((uint16_t)0x0626)        /*!< SMARTCARD transmission complete interruption        */
+#define SMARTCARD_IT_RXNE                   ((uint16_t)0x0525)        /*!< SMARTCARD read data register not empty interruption */
+#define SMARTCARD_IT_IDLE                   ((uint16_t)0x0424)        /*!< SMARTCARD idle line detection interruption          */
+                                                                      
+#define SMARTCARD_IT_ERR                    ((uint16_t)0x0060)        /*!< SMARTCARD error interruption         */
+#define SMARTCARD_IT_ORE                    ((uint16_t)0x0300)        /*!< SMARTCARD overrun error interruption */
+#define SMARTCARD_IT_NE                     ((uint16_t)0x0200)        /*!< SMARTCARD noise error interruption   */
+#define SMARTCARD_IT_FE                     ((uint16_t)0x0100)        /*!< SMARTCARD frame error interruption   */
+
+#define SMARTCARD_IT_EOB                    ((uint16_t)0x0C3B)        /*!< SMARTCARD end of block interruption     */ 
+#define SMARTCARD_IT_RTO                    ((uint16_t)0x0B3A)        /*!< SMARTCARD receiver timeout interruption */
+
+#define SMARTCARD_IT_RXFF                   ((uint16_t)0x183F)
+#define SMARTCARD_IT_TXFE                   ((uint16_t)0x173E)
+#define SMARTCARD_IT_RXFT                   ((uint16_t)0x187C)
+#define SMARTCARD_IT_TXFT                   ((uint16_t)0x1B77)
+#define SMARTCARD_IT_TCBGT                  ((uint16_t)0x1978)        /*!< SMARTCARD transmission complete before guard time completion interruption */
+/**
+  * @}
+  */
+  
+/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
+  * @{
+  */
+#define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */
+#define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */
+#define SMARTCARD_CLEAR_NEF                 USART_ICR_NECF     /*!< SMARTCARD noise detected clear flag        */
+#define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */
+#define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */
+#define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */
+#define SMARTCARD_CLEAR_TCBGTF              USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
+#define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */
+#define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */
+#define SMARTCARD_CLEAR_TXFECF              USART_ICR_TXFECF  /*!< SMARTCARD TXFIFO empty clear flag          */
+#define SMARTCARD_CLEAR_UDRCF               USART_ICR_UDRCF   /*!< SMARTCARD UnderRun Error Clear Flag        */
+/**
+  * @}
+  */  
+    
+/**
+  * @}
+  */ 
+/* Exported macros -----------------------------------------------------------*/  
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
+  * @{
+  */
+  
+/** @brief  Report the SMARTCARD clock source.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @param  __CLOCKSOURCE__: output variable.
+  * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
+  */
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                         \
+      if((__HANDLE__)->Instance == USART1)                     \
+    {                                                          \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+       {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK5:                      \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK5;       \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;         \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;           \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_PLL4:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL4Q;           \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSE;           \
+          break;                                               \
+       }                                                       \
+     }                                                        \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_UART24_SOURCE())                  \
+       {                                                      \
+        case RCC_UART24CLKSOURCE_PCLK1:                     \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;      \
+          break;                                              \
+        case RCC_UART24CLKSOURCE_PLL4:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL4Q;        \
+          break;                                              \
+        case RCC_UART24CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;          \
+          break;                                              \
+        case RCC_UART24CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;          \
+          break;                                              \
+        case RCC_UART24CLKSOURCE_HSE:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSE;          \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_UART35_SOURCE())                  \
+       {                                                      \
+        case RCC_UART35CLKSOURCE_PCLK1:                     \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1;      \
+          break;                                              \
+        case RCC_UART35CLKSOURCE_PLL4:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL4Q;        \
+          break;                                              \
+        case RCC_UART35CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;          \
+          break;                                              \
+        case RCC_UART35CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;          \
+          break;                                              \
+        case RCC_UART35CLKSOURCE_HSE:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSE;          \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART6)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART6_SOURCE())                  \
+       {                                                      \
+        case RCC_USART6CLKSOURCE_PCLK2:                     \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2;      \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL4:                       \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL4Q;        \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_HSE:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSE;          \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+
+
+/** @brief  Set the Transmission Completion flag
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @retval None
+  */
+#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)                                                \
+  do {                                                                                                       \
+    if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
+    {                                                                                                        \
+     (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                       \
+    }                                                                                                        \
+    else                                                                                                     \
+    {                                                                                                        \
+      assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
+    }                                                                                                        \
+  } while(0)
+
+/** @brief  Return the transmission completion flag.
+  * @param  __HANDLE__: specifies the SMARTCARD Handle.
+  * @note  Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
+  * @retval Transmission completion flag
+  */
+#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
+  (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) :  (SMARTCARD_FLAG_TCBGT))
+  
+/**
+  * @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
+  * @param __TXCOMPLETE__: SMARTCARD frame transmission completion used flag. 
+  * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
+  */ 
+#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\
+                                                              ((__TXCOMPLETE__) == SMARTCARD_TC))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SMARTCARDEx_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/* IO operation methods *******************************************************/
+
+/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Peripheral Control functions ***********************************************/
+void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
+void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32MP1xx_HAL_SMARTCARD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Inc/stm32mp1xx_ll_rcc.h

@@ -288,10 +288,10 @@ typedef struct
 /** @defgroup RCC_LL_EC_HSIDIV  HSI oscillator divider
   * @{
   */
-#define LL_RCC_HSI_DIV_1                   RCC_HSICFGR_HSIDIV_0
-#define LL_RCC_HSI_DIV_2                   RCC_HSICFGR_HSIDIV_1
-#define LL_RCC_HSI_DIV_4                   RCC_HSICFGR_HSIDIV_2
-#define LL_RCC_HSI_DIV_8                   RCC_HSICFGR_HSIDIV_3
+#define LL_RCC_HSI_DIV_1                   0U
+#define LL_RCC_HSI_DIV_2                   RCC_HSICFGR_HSIDIV_0
+#define LL_RCC_HSI_DIV_4                   RCC_HSICFGR_HSIDIV_1
+#define LL_RCC_HSI_DIV_8                   (RCC_HSICFGR_HSIDIV_0 | RCC_HSICFGR_HSIDIV_1)
 /**
   * @}
   */
@@ -299,18 +299,18 @@ typedef struct
 /** @defgroup RCC_LL_EC_MCOxSOURCE  MCO SOURCE selection
   * @{
   */
-#define LL_RCC_MCO1SOURCE_HSI      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_0)
-#define LL_RCC_MCO1SOURCE_HSE      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_1)
-#define LL_RCC_MCO1SOURCE_CSI      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_2)
-#define LL_RCC_MCO1SOURCE_LSI      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_3)
-#define LL_RCC_MCO1SOURCE_LSE      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_4)
+#define LL_RCC_MCO1SOURCE_HSI      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, 0)
+#define LL_RCC_MCO1SOURCE_HSE      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_0)
+#define LL_RCC_MCO1SOURCE_CSI      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_1)
+#define LL_RCC_MCO1SOURCE_LSI      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, (RCC_MCO1CFGR_MCO1SEL_0 | RCC_MCO1CFGR_MCO1SEL_1))
+#define LL_RCC_MCO1SOURCE_LSE      LL_CLKSOURCE(RCC_OFFSET_MCO1CFGR, RCC_MCO1CFGR_MCO1SEL, RCC_MCO1CFGR_MCO1SEL_2)
 
-#define LL_RCC_MCO2SOURCE_MPU      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_0)
-#define LL_RCC_MCO2SOURCE_AXI      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_1)
-#define LL_RCC_MCO2SOURCE_MCU      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_2)
-#define LL_RCC_MCO2SOURCE_PLL4     LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_3)
-#define LL_RCC_MCO2SOURCE_HSE      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_4)
-#define LL_RCC_MCO2SOURCE_HSI      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_5)
+#define LL_RCC_MCO2SOURCE_MPU      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, 0)
+#define LL_RCC_MCO2SOURCE_AXI      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_0)
+#define LL_RCC_MCO2SOURCE_MCU      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_1)
+#define LL_RCC_MCO2SOURCE_PLL4     LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, (RCC_MCO2CFGR_MCO2SEL_1 | RCC_MCO2CFGR_MCO2SEL_0))
+#define LL_RCC_MCO2SOURCE_HSE      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, RCC_MCO2CFGR_MCO2SEL_2)
+#define LL_RCC_MCO2SOURCE_HSI      LL_CLKSOURCE(RCC_OFFSET_MCO2CFGR, RCC_MCO2CFGR_MCO2SEL, (RCC_MCO2CFGR_MCO2SEL_2 | RCC_MCO2CFGR_MCO2SEL_0))
 /**
   * @}
   */
@@ -318,22 +318,22 @@ typedef struct
 /** @defgroup RCC_LL_EC_MCO1_DIV  MCO1 prescaler
   * @{
   */
-#define LL_RCC_MCO1_DIV_1                  RCC_MCO1CFGR_MCO1DIV_0   /*!< MCO not divided */
-#define LL_RCC_MCO1_DIV_2                  RCC_MCO1CFGR_MCO1DIV_1   /*!< MCO divided by 2 */
-#define LL_RCC_MCO1_DIV_3                  RCC_MCO1CFGR_MCO1DIV_2   /*!< MCO divided by 3 */
-#define LL_RCC_MCO1_DIV_4                  RCC_MCO1CFGR_MCO1DIV_3   /*!< MCO divided by 4 */
-#define LL_RCC_MCO1_DIV_5                  RCC_MCO1CFGR_MCO1DIV_4   /*!< MCO divided by 5 */
-#define LL_RCC_MCO1_DIV_6                  RCC_MCO1CFGR_MCO1DIV_5   /*!< MCO divided by 6 */
-#define LL_RCC_MCO1_DIV_7                  RCC_MCO1CFGR_MCO1DIV_6   /*!< MCO divided by 7 */
-#define LL_RCC_MCO1_DIV_8                  RCC_MCO1CFGR_MCO1DIV_7   /*!< MCO divided by 8 */
-#define LL_RCC_MCO1_DIV_9                  RCC_MCO1CFGR_MCO1DIV_8   /*!< MCO divided by 9 */
-#define LL_RCC_MCO1_DIV_10                 RCC_MCO1CFGR_MCO1DIV_9   /*!< MCO divided by 10 */
-#define LL_RCC_MCO1_DIV_11                 RCC_MCO1CFGR_MCO1DIV_10  /*!< MCO divided by 11 */
-#define LL_RCC_MCO1_DIV_12                 RCC_MCO1CFGR_MCO1DIV_11  /*!< MCO divided by 12 */
-#define LL_RCC_MCO1_DIV_13                 RCC_MCO1CFGR_MCO1DIV_12  /*!< MCO divided by 13 */
-#define LL_RCC_MCO1_DIV_14                 RCC_MCO1CFGR_MCO1DIV_13  /*!< MCO divided by 14 */
-#define LL_RCC_MCO1_DIV_15                 RCC_MCO1CFGR_MCO1DIV_14  /*!< MCO divided by 15 */
-#define LL_RCC_MCO1_DIV_16                 RCC_MCO1CFGR_MCO1DIV_15  /*!< MCO divided by 16 */
+#define LL_RCC_MCO1_DIV_1                  0U                       /*!< MCO not divided */
+#define LL_RCC_MCO1_DIV_2                  RCC_MCO1CFGR_MCO1DIV_0   /*!< MCO divided by 2 */
+#define LL_RCC_MCO1_DIV_3                  RCC_MCO1CFGR_MCO1DIV_1   /*!< MCO divided by 3 */
+#define LL_RCC_MCO1_DIV_4                  (RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0)   /*!< MCO divided by 4 */
+#define LL_RCC_MCO1_DIV_5                  RCC_MCO1CFGR_MCO1DIV_2   /*!< MCO divided by 5 */
+#define LL_RCC_MCO1_DIV_6                  (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_0)   /*!< MCO divided by 6 */
+#define LL_RCC_MCO1_DIV_7                  (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1)   /*!< MCO divided by 7 */
+#define LL_RCC_MCO1_DIV_8                  (RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1| RCC_MCO1CFGR_MCO1DIV_0)   /*!< MCO divided by 8 */
+#define LL_RCC_MCO1_DIV_9                  RCC_MCO1CFGR_MCO1DIV_3   /*!< MCO divided by 9 */
+#define LL_RCC_MCO1_DIV_10                 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_0)   /*!< MCO divided by 10 */
+#define LL_RCC_MCO1_DIV_11                 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_1)  /*!< MCO divided by 11 */
+#define LL_RCC_MCO1_DIV_12                 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0)  /*!< MCO divided by 12 */
+#define LL_RCC_MCO1_DIV_13                 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2)  /*!< MCO divided by 13 */
+#define LL_RCC_MCO1_DIV_14                 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_0)  /*!< MCO divided by 14 */
+#define LL_RCC_MCO1_DIV_15                 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1)  /*!< MCO divided by 15 */
+#define LL_RCC_MCO1_DIV_16                 (RCC_MCO1CFGR_MCO1DIV_3 | RCC_MCO1CFGR_MCO1DIV_2 | RCC_MCO1CFGR_MCO1DIV_1 | RCC_MCO1CFGR_MCO1DIV_0)  /*!< MCO divided by 16 */
 /**
   * @}
   */
@@ -435,10 +435,10 @@ typedef struct
 /** @defgroup RCC_LL_EC_MPU_CLKSOURCE  MPU clock switch
   * @{
   */
-#define LL_RCC_MPU_CLKSOURCE_HSI                RCC_MPCKSELR_MPUSRC_0 /*!< HSI selection as MPU clock */
-#define LL_RCC_MPU_CLKSOURCE_HSE                RCC_MPCKSELR_MPUSRC_1 /*!< HSE selection as MPU clock */
-#define LL_RCC_MPU_CLKSOURCE_PLL1               RCC_MPCKSELR_MPUSRC_2 /*!< PLL1 selection as MPU clock */
-#define LL_RCC_MPU_CLKSOURCE_MPUDIV             RCC_MPCKSELR_MPUSRC_3 /*!< MPUDIV selection as MPU clock */
+#define LL_RCC_MPU_CLKSOURCE_HSI                0U                    /*!< HSI selection as MPU clock */
+#define LL_RCC_MPU_CLKSOURCE_HSE                RCC_MPCKSELR_MPUSRC_0 /*!< HSE selection as MPU clock */
+#define LL_RCC_MPU_CLKSOURCE_PLL1               RCC_MPCKSELR_MPUSRC_1 /*!< PLL1 selection as MPU clock */
+#define LL_RCC_MPU_CLKSOURCE_MPUDIV             (RCC_MPCKSELR_MPUSRC_1 | RCC_MPCKSELR_MPUSRC_0) /*!< MPUDIV selection as MPU clock */
 /**
   * @}
   */
@@ -469,10 +469,10 @@ typedef struct
 /** @defgroup RCC_LL_EC_AXISS_CLKSOURCE  AXISS clock switch
   * @{
   */
-#define LL_RCC_AXISS_CLKSOURCE_HSI              RCC_ASSCKSELR_AXISSRC_0 /*!< HSI selection as AXISS clock */
-#define LL_RCC_AXISS_CLKSOURCE_HSE              RCC_ASSCKSELR_AXISSRC_1 /*!< HSE selection as AXISS clock */
-#define LL_RCC_AXISS_CLKSOURCE_PLL2             RCC_ASSCKSELR_AXISSRC_2 /*!< PLL2 selection as AXISS clock */
-#define LL_RCC_AXISS_CLKSOURCE_OFF              RCC_ASSCKSELR_AXISSRC_3 /*!< AXISS is gated */
+#define LL_RCC_AXISS_CLKSOURCE_HSI              0U                      /*!< HSI selection as AXISS clock */
+#define LL_RCC_AXISS_CLKSOURCE_HSE              RCC_ASSCKSELR_AXISSRC_0 /*!< HSE selection as AXISS clock */
+#define LL_RCC_AXISS_CLKSOURCE_PLL2             RCC_ASSCKSELR_AXISSRC_1 /*!< PLL2 selection as AXISS clock */
+#define LL_RCC_AXISS_CLKSOURCE_OFF              (RCC_ASSCKSELR_AXISSRC_1 | RCC_ASSCKSELR_AXISSRC_0) /*!< AXISS is gated */
 /**
   * @}
   */
@@ -480,10 +480,10 @@ typedef struct
 /** @defgroup RCC_LL_EC_AXISS_CLKSOURCE_STATUS  AXISS clock switch status
   * @{
   */
-#define LL_RCC_AXISS_CLKSOURCE_STATUS_HSI       RCC_ASSCKSELR_AXISSRC_0 /*!< HSI used as AXISS clock */
-#define LL_RCC_AXISS_CLKSOURCE_STATUS_HSE       RCC_ASSCKSELR_AXISSRC_1 /*!< HSE used as AXISS clock */
-#define LL_RCC_AXISS_CLKSOURCE_STATUS_PLL2      RCC_ASSCKSELR_AXISSRC_2 /*!< PLL2 used as AXISS clock */
-#define LL_RCC_AXISS_CLKSOURCE_STATUS_OFF       RCC_ASSCKSELR_AXISSRC_3 /*!< AXISS is gated */
+#define LL_RCC_AXISS_CLKSOURCE_STATUS_HSI       0U                      /*!< HSI used as AXISS clock */
+#define LL_RCC_AXISS_CLKSOURCE_STATUS_HSE       RCC_ASSCKSELR_AXISSRC_0 /*!< HSE used as AXISS clock */
+#define LL_RCC_AXISS_CLKSOURCE_STATUS_PLL2      RCC_ASSCKSELR_AXISSRC_1 /*!< PLL2 used as AXISS clock */
+#define LL_RCC_AXISS_CLKSOURCE_STATUS_OFF       (RCC_ASSCKSELR_AXISSRC_1 | RCC_ASSCKSELR_AXISSRC_0) /*!< AXISS is gated */
 /**
   * @}
   */
@@ -502,10 +502,10 @@ typedef struct
 /** @defgroup RCC_LL_EC_MCUSS_CLKSOURCE  MCUSS clock switch
   * @{
   */
-#define LL_RCC_MCUSS_CLKSOURCE_HSI              RCC_MSSCKSELR_MCUSSRC_0 /*!< HSI selection as MCUSS clock */
-#define LL_RCC_MCUSS_CLKSOURCE_HSE              RCC_MSSCKSELR_MCUSSRC_1 /*!< HSE selection as MCUSS clock */
-#define LL_RCC_MCUSS_CLKSOURCE_CSI              RCC_MSSCKSELR_MCUSSRC_2 /*!< CSI selection as MCUSS clock */
-#define LL_RCC_MCUSS_CLKSOURCE_PLL3             RCC_MSSCKSELR_MCUSSRC_3 /*!< PLL3 selection as MCUSS clock */
+#define LL_RCC_MCUSS_CLKSOURCE_HSI              0U                      /*!< HSI selection as MCUSS clock */
+#define LL_RCC_MCUSS_CLKSOURCE_HSE              RCC_MSSCKSELR_MCUSSRC_0 /*!< HSE selection as MCUSS clock */
+#define LL_RCC_MCUSS_CLKSOURCE_CSI              RCC_MSSCKSELR_MCUSSRC_1 /*!< CSI selection as MCUSS clock */
+#define LL_RCC_MCUSS_CLKSOURCE_PLL3             (RCC_MSSCKSELR_MCUSSRC_1 | RCC_MSSCKSELR_MCUSSRC_0) /*!< PLL3 selection as MCUSS clock */
 /**
   * @}
   */
@@ -541,11 +541,11 @@ typedef struct
 /** @defgroup RCC_LL_EC_APB1_DIV  APB1 prescaler
   * @{
   */
-#define LL_RCC_APB1_DIV_1                       RCC_APB1DIVR_APB1DIV_0  /*!< mlhclk not divided (default after reset) */
-#define LL_RCC_APB1_DIV_2                       RCC_APB1DIVR_APB1DIV_1  /*!< mlhclk divided by 2 */
-#define LL_RCC_APB1_DIV_4                       RCC_APB1DIVR_APB1DIV_2  /*!< mlhclk divided by 4 */
-#define LL_RCC_APB1_DIV_8                       RCC_APB1DIVR_APB1DIV_3  /*!< mlhclk divided by 8 */
-#define LL_RCC_APB1_DIV_16                      RCC_APB1DIVR_APB1DIV_4  /*!< mlhclk divided by 16 */
+#define LL_RCC_APB1_DIV_1                       0U                                                 /*!< mlhclk not divided (default after reset) */
+#define LL_RCC_APB1_DIV_2                       RCC_APB1DIVR_APB1DIV_0                             /*!< mlhclk divided by 2 */
+#define LL_RCC_APB1_DIV_4                       RCC_APB1DIVR_APB1DIV_1                             /*!< mlhclk divided by 4 */
+#define LL_RCC_APB1_DIV_8                       (RCC_APB1DIVR_APB1DIV_1 | RCC_APB1DIVR_APB1DIV_0)  /*!< mlhclk divided by 8 */
+#define LL_RCC_APB1_DIV_16                      RCC_APB1DIVR_APB1DIV_2                             /*!< mlhclk divided by 16 */
 /**
   * @}
   */
@@ -553,11 +553,11 @@ typedef struct
 /** @defgroup RCC_LL_EC_APB2_DIV  APB2 prescaler
   * @{
   */
-#define LL_RCC_APB2_DIV_1                       RCC_APB2DIVR_APB2DIV_0  /*!< mlhclk not divided (default after reset) */
-#define LL_RCC_APB2_DIV_2                       RCC_APB2DIVR_APB2DIV_1  /*!< mlhclk divided by 2 */
-#define LL_RCC_APB2_DIV_4                       RCC_APB2DIVR_APB2DIV_2  /*!< mlhclk divided by 4 */
-#define LL_RCC_APB2_DIV_8                       RCC_APB2DIVR_APB2DIV_3  /*!< mlhclk divided by 8 */
-#define LL_RCC_APB2_DIV_16                      RCC_APB2DIVR_APB2DIV_4  /*!< mlhclk divided by 16 */
+#define LL_RCC_APB2_DIV_1                       0U                                                 /*!< mlhclk not divided (default after reset) */
+#define LL_RCC_APB2_DIV_2                       RCC_APB2DIVR_APB2DIV_0                             /*!< mlhclk divided by 2 */
+#define LL_RCC_APB2_DIV_4                       RCC_APB2DIVR_APB2DIV_1                             /*!< mlhclk divided by 4 */
+#define LL_RCC_APB2_DIV_8                       (RCC_APB2DIVR_APB2DIV_1 | RCC_APB2DIVR_APB2DIV_0)  /*!< mlhclk divided by 8 */
+#define LL_RCC_APB2_DIV_16                      RCC_APB2DIVR_APB2DIV_2                             /*!< mlhclk divided by 16 */
 /**
   * @}
   */
@@ -565,11 +565,11 @@ typedef struct
 /** @defgroup RCC_LL_EC_APB3_DIV  APB3 prescaler
   * @{
   */
-#define LL_RCC_APB3_DIV_1                       RCC_APB3DIVR_APB3DIV_0  /*!< mlhclk not divided (default after reset) */
-#define LL_RCC_APB3_DIV_2                       RCC_APB3DIVR_APB3DIV_1  /*!< mlhclk divided by 2 */
-#define LL_RCC_APB3_DIV_4                       RCC_APB3DIVR_APB3DIV_2  /*!< mlhclk divided by 4 */
-#define LL_RCC_APB3_DIV_8                       RCC_APB3DIVR_APB3DIV_3  /*!< mlhclk divided by 8 */
-#define LL_RCC_APB3_DIV_16                      RCC_APB3DIVR_APB3DIV_4  /*!< mlhclk divided by 16 */
+#define LL_RCC_APB3_DIV_1                       0U                                                /*!< mlhclk not divided (default after reset) */
+#define LL_RCC_APB3_DIV_2                       RCC_APB3DIVR_APB3DIV_0                            /*!< mlhclk divided by 2 */
+#define LL_RCC_APB3_DIV_4                       RCC_APB3DIVR_APB3DIV_1                            /*!< mlhclk divided by 4 */
+#define LL_RCC_APB3_DIV_8                       (RCC_APB3DIVR_APB3DIV_1| RCC_APB3DIVR_APB3DIV_0)  /*!< mlhclk divided by 8 */
+#define LL_RCC_APB3_DIV_16                      RCC_APB3DIVR_APB3DIV_2                            /*!< mlhclk divided by 16 */
 /**
   * @}
   */
@@ -577,11 +577,11 @@ typedef struct
 /** @defgroup RCC_LL_EC_APB4_DIV  APB4 prescaler
   * @{
   */
-#define LL_RCC_APB4_DIV_1                       RCC_APB4DIVR_APB4DIV_0  /*!< aclk not divided (default after reset) */
-#define LL_RCC_APB4_DIV_2                       RCC_APB4DIVR_APB4DIV_1  /*!< aclk divided by 2 */
-#define LL_RCC_APB4_DIV_4                       RCC_APB4DIVR_APB4DIV_2  /*!< aclk divided by 4 */
-#define LL_RCC_APB4_DIV_8                       RCC_APB4DIVR_APB4DIV_3  /*!< aclk divided by 8 */
-#define LL_RCC_APB4_DIV_16                      RCC_APB4DIVR_APB4DIV_4  /*!< aclk divided by 16 */
+#define LL_RCC_APB4_DIV_1                       0U                                                 /*!< aclk not divided (default after reset) */
+#define LL_RCC_APB4_DIV_2                       RCC_APB4DIVR_APB4DIV_0                             /*!< aclk divided by 2 */
+#define LL_RCC_APB4_DIV_4                       RCC_APB4DIVR_APB4DIV_1                             /*!< aclk divided by 4 */
+#define LL_RCC_APB4_DIV_8                       (RCC_APB4DIVR_APB4DIV_1 | RCC_APB4DIVR_APB4DIV_0)  /*!< aclk divided by 8 */
+#define LL_RCC_APB4_DIV_16                      RCC_APB4DIVR_APB4DIV_2                             /*!< aclk divided by 16 */
 /**
   * @}
   */
@@ -589,11 +589,11 @@ typedef struct
 /** @defgroup RCC_LL_EC_APB5_DIV  APB5 prescaler
   * @{
   */
-#define LL_RCC_APB5_DIV_1                       RCC_APB5DIVR_APB5DIV_0  /*!< aclk not divided (default after reset) */
-#define LL_RCC_APB5_DIV_2                       RCC_APB5DIVR_APB5DIV_1  /*!< aclk divided by 2 */
-#define LL_RCC_APB5_DIV_4                       RCC_APB5DIVR_APB5DIV_2  /*!< aclk divided by 4 */
-#define LL_RCC_APB5_DIV_8                       RCC_APB5DIVR_APB5DIV_3  /*!< aclk divided by 8 */
-#define LL_RCC_APB5_DIV_16                      RCC_APB5DIVR_APB5DIV_4  /*!< aclk divided by 16 */
+#define LL_RCC_APB5_DIV_1                       0U                                                 /*!< aclk not divided (default after reset) */
+#define LL_RCC_APB5_DIV_2                       RCC_APB5DIVR_APB5DIV_0                             /*!< aclk divided by 2 */
+#define LL_RCC_APB5_DIV_4                       RCC_APB5DIVR_APB5DIV_1                             /*!< aclk divided by 4 */
+#define LL_RCC_APB5_DIV_8                       (RCC_APB5DIVR_APB5DIV_1 | RCC_APB5DIVR_APB5DIV_0)  /*!< aclk divided by 8 */
+#define LL_RCC_APB5_DIV_16                      RCC_APB5DIVR_APB5DIV_2                             /*!< aclk divided by 16 */
 /**
   * @}
   */
@@ -624,20 +624,20 @@ typedef struct
 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C clock source selection
   * @{
   */
-#define LL_RCC_I2C12_CLKSOURCE_PCLK1        LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_0)
-#define LL_RCC_I2C12_CLKSOURCE_PLL4R        LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_1)
-#define LL_RCC_I2C12_CLKSOURCE_HSI          LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_2)
-#define LL_RCC_I2C12_CLKSOURCE_CSI          LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_3)
+#define LL_RCC_I2C12_CLKSOURCE_PCLK1        LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, 0)
+#define LL_RCC_I2C12_CLKSOURCE_PLL4R        LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_0)
+#define LL_RCC_I2C12_CLKSOURCE_HSI          LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, RCC_I2C12CKSELR_I2C12SRC_1)
+#define LL_RCC_I2C12_CLKSOURCE_CSI          LL_CLKSOURCE(RCC_OFFSET_I2C12CKSELR, RCC_I2C12CKSELR_I2C12SRC, (RCC_I2C12CKSELR_I2C12SRC_1 | RCC_I2C12CKSELR_I2C12SRC_0))
 
-#define LL_RCC_I2C35_CLKSOURCE_PCLK1        LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_0)
-#define LL_RCC_I2C35_CLKSOURCE_PLL4R        LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_1)
-#define LL_RCC_I2C35_CLKSOURCE_HSI          LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_2)
-#define LL_RCC_I2C35_CLKSOURCE_CSI          LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_3)
+#define LL_RCC_I2C35_CLKSOURCE_PCLK1        LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, 0)
+#define LL_RCC_I2C35_CLKSOURCE_PLL4R        LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_0)
+#define LL_RCC_I2C35_CLKSOURCE_HSI          LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, RCC_I2C35CKSELR_I2C35SRC_1)
+#define LL_RCC_I2C35_CLKSOURCE_CSI          LL_CLKSOURCE(RCC_OFFSET_I2C35CKSELR, RCC_I2C35CKSELR_I2C35SRC, (RCC_I2C35CKSELR_I2C35SRC_1 | RCC_I2C35CKSELR_I2C35SRC_0))
 
-#define LL_RCC_I2C46_CLKSOURCE_PCLK5        LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_0)
-#define LL_RCC_I2C46_CLKSOURCE_PLL3Q        LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_1)
-#define LL_RCC_I2C46_CLKSOURCE_HSI          LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_2)
-#define LL_RCC_I2C46_CLKSOURCE_CSI          LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_3)
+#define LL_RCC_I2C46_CLKSOURCE_PCLK5        LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, 0)
+#define LL_RCC_I2C46_CLKSOURCE_PLL3Q        LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_0)
+#define LL_RCC_I2C46_CLKSOURCE_HSI          LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, RCC_I2C46CKSELR_I2C46SRC_1)
+#define LL_RCC_I2C46_CLKSOURCE_CSI          LL_CLKSOURCE(RCC_OFFSET_I2C46CKSELR, RCC_I2C46CKSELR_I2C46SRC, (RCC_I2C46CKSELR_I2C46SRC_1 | RCC_I2C46CKSELR_I2C46SRC_0))
 /**
   * @}
   */
@@ -645,30 +645,30 @@ typedef struct
 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection
   * @{
   */
-#define LL_RCC_SAI1_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_0)
-#define LL_RCC_SAI1_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_1)
-#define LL_RCC_SAI1_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_2)
-#define LL_RCC_SAI1_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_3)
-#define LL_RCC_SAI1_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_4)
-
-#define LL_RCC_SAI2_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_0)
-#define LL_RCC_SAI2_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_1)
-#define LL_RCC_SAI2_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_2)
-#define LL_RCC_SAI2_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_3)
-#define LL_RCC_SAI2_CLKSOURCE_SPDIF         LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_4)
-#define LL_RCC_SAI2_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_5)
-
-#define LL_RCC_SAI3_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_0)
-#define LL_RCC_SAI3_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_1)
-#define LL_RCC_SAI3_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_2)
-#define LL_RCC_SAI3_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_3)
-#define LL_RCC_SAI3_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_4)
-
-#define LL_RCC_SAI4_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_0)
-#define LL_RCC_SAI4_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_1)
-#define LL_RCC_SAI4_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_2)
-#define LL_RCC_SAI4_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_3)
-#define LL_RCC_SAI4_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_4)
+#define LL_RCC_SAI1_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, 0)
+#define LL_RCC_SAI1_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_0)
+#define LL_RCC_SAI1_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_1)
+#define LL_RCC_SAI1_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, (RCC_SAI1CKSELR_SAI1SRC_1 | RCC_SAI1CKSELR_SAI1SRC_0))
+#define LL_RCC_SAI1_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SAI1CKSELR, RCC_SAI1CKSELR_SAI1SRC, RCC_SAI1CKSELR_SAI1SRC_2)
+
+#define LL_RCC_SAI2_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, 0)
+#define LL_RCC_SAI2_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_0)
+#define LL_RCC_SAI2_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_1)
+#define LL_RCC_SAI2_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, (RCC_SAI2CKSELR_SAI2SRC_1 | RCC_SAI2CKSELR_SAI2SRC_0))
+#define LL_RCC_SAI2_CLKSOURCE_SPDIF         LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, RCC_SAI2CKSELR_SAI2SRC_2)
+#define LL_RCC_SAI2_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SAI2CKSELR, RCC_SAI2CKSELR_SAI2SRC, (RCC_SAI2CKSELR_SAI2SRC_2 | RCC_SAI2CKSELR_SAI2SRC_0))
+
+#define LL_RCC_SAI3_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, 0)
+#define LL_RCC_SAI3_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_0)
+#define LL_RCC_SAI3_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_1)
+#define LL_RCC_SAI3_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, (RCC_SAI3CKSELR_SAI3SRC_1 | RCC_SAI3CKSELR_SAI3SRC_0))
+#define LL_RCC_SAI3_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SAI3CKSELR, RCC_SAI3CKSELR_SAI3SRC, RCC_SAI3CKSELR_SAI3SRC_2)
+
+#define LL_RCC_SAI4_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, 0)
+#define LL_RCC_SAI4_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_0)
+#define LL_RCC_SAI4_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_1)
+#define LL_RCC_SAI4_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, (RCC_SAI4CKSELR_SAI4SRC_1 | RCC_SAI4CKSELR_SAI4SRC_0))
+#define LL_RCC_SAI4_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SAI4CKSELR, RCC_SAI4CKSELR_SAI4SRC, RCC_SAI4CKSELR_SAI4SRC_2)
 /**
   * @}
   */
@@ -676,30 +676,30 @@ typedef struct
 /** @defgroup RCC_LL_EC_SPIx_CLKSOURCE  Peripheral SPI/I2S clock source selection
   * @{
   */
-#define LL_RCC_SPI1_CLKSOURCE_PLL4P         LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_0)
-#define LL_RCC_SPI1_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_1)
-#define LL_RCC_SPI1_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_2)
-#define LL_RCC_SPI1_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_3)
-#define LL_RCC_SPI1_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_4)
-
-#define LL_RCC_SPI23_CLKSOURCE_PLL4P        LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_0)
-#define LL_RCC_SPI23_CLKSOURCE_PLL3Q        LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_1)
-#define LL_RCC_SPI23_CLKSOURCE_I2SCKIN      LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_2)
-#define LL_RCC_SPI23_CLKSOURCE_PER          LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_3)
-#define LL_RCC_SPI23_CLKSOURCE_PLL3R        LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_4)
-
-#define LL_RCC_SPI45_CLKSOURCE_PCLK2        LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_0)
-#define LL_RCC_SPI45_CLKSOURCE_PLL4Q        LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_1)
-#define LL_RCC_SPI45_CLKSOURCE_HSI          LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_2)
-#define LL_RCC_SPI45_CLKSOURCE_CSI          LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_3)
-#define LL_RCC_SPI45_CLKSOURCE_HSE          LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_4)
-
-#define LL_RCC_SPI6_CLKSOURCE_PCLK5         LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_0)
-#define LL_RCC_SPI6_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_1)
-#define LL_RCC_SPI6_CLKSOURCE_HSI           LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_2)
-#define LL_RCC_SPI6_CLKSOURCE_CSI           LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_3)
-#define LL_RCC_SPI6_CLKSOURCE_HSE           LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_4)
-#define LL_RCC_SPI6_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_5)
+#define LL_RCC_SPI1_CLKSOURCE_PLL4P         LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, 0)
+#define LL_RCC_SPI1_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_0)
+#define LL_RCC_SPI1_CLKSOURCE_I2SCKIN       LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_1)
+#define LL_RCC_SPI1_CLKSOURCE_PER           LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, (RCC_SPI2S1CKSELR_SPI1SRC_1 | RCC_SPI2S1CKSELR_SPI1SRC_0))
+#define LL_RCC_SPI1_CLKSOURCE_PLL3R         LL_CLKSOURCE(RCC_OFFSET_SPI2S1CKSELR, RCC_SPI2S1CKSELR_SPI1SRC, RCC_SPI2S1CKSELR_SPI1SRC_2)
+
+#define LL_RCC_SPI23_CLKSOURCE_PLL4P        LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, 0)
+#define LL_RCC_SPI23_CLKSOURCE_PLL3Q        LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_0)
+#define LL_RCC_SPI23_CLKSOURCE_I2SCKIN      LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_1)
+#define LL_RCC_SPI23_CLKSOURCE_PER          LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, (RCC_SPI2S23CKSELR_SPI23SRC_1 | RCC_SPI2S23CKSELR_SPI23SRC_0))
+#define LL_RCC_SPI23_CLKSOURCE_PLL3R        LL_CLKSOURCE(RCC_OFFSET_SPI2S23CKSELR, RCC_SPI2S23CKSELR_SPI23SRC, RCC_SPI2S23CKSELR_SPI23SRC_2)
+
+#define LL_RCC_SPI45_CLKSOURCE_PCLK2        LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, 0)
+#define LL_RCC_SPI45_CLKSOURCE_PLL4Q        LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_0)
+#define LL_RCC_SPI45_CLKSOURCE_HSI          LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_1)
+#define LL_RCC_SPI45_CLKSOURCE_CSI          LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, (RCC_SPI45CKSELR_SPI45SRC_1 | RCC_SPI45CKSELR_SPI45SRC_0))
+#define LL_RCC_SPI45_CLKSOURCE_HSE          LL_CLKSOURCE(RCC_OFFSET_SPI45CKSELR, RCC_SPI45CKSELR_SPI45SRC, RCC_SPI45CKSELR_SPI45SRC_2)
+
+#define LL_RCC_SPI6_CLKSOURCE_PCLK5         LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, 0)
+#define LL_RCC_SPI6_CLKSOURCE_PLL4Q         LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_0)
+#define LL_RCC_SPI6_CLKSOURCE_HSI           LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_1)
+#define LL_RCC_SPI6_CLKSOURCE_CSI           LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, (RCC_SPI6CKSELR_SPI6SRC_1 | RCC_SPI6CKSELR_SPI6SRC_0))
+#define LL_RCC_SPI6_CLKSOURCE_HSE           LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, RCC_SPI6CKSELR_SPI6SRC_2)
+#define LL_RCC_SPI6_CLKSOURCE_PLL3Q         LL_CLKSOURCE(RCC_OFFSET_SPI6CKSELR, RCC_SPI6CKSELR_SPI6SRC, (RCC_SPI6CKSELR_SPI6SRC_2 | RCC_SPI6CKSELR_SPI6SRC_0))
 /**
   * @}
   */
@@ -707,36 +707,36 @@ typedef struct
 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection
   * @{
   */
-#define LL_RCC_USART1_CLKSOURCE_PCLK5       LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_0)
-#define LL_RCC_USART1_CLKSOURCE_PLL3Q       LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_1)
-#define LL_RCC_USART1_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_2)
-#define LL_RCC_USART1_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_3)
-#define LL_RCC_USART1_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_4)
-#define LL_RCC_USART1_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_5)
-
-#define LL_RCC_UART24_CLKSOURCE_PCLK1       LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_0)
-#define LL_RCC_UART24_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_1)
-#define LL_RCC_UART24_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_2)
-#define LL_RCC_UART24_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_3)
-#define LL_RCC_UART24_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_4)
-
-#define LL_RCC_UART35_CLKSOURCE_PCLK1       LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_0)
-#define LL_RCC_UART35_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_1)
-#define LL_RCC_UART35_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_2)
-#define LL_RCC_UART35_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_3)
-#define LL_RCC_UART35_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_4)
-
-#define LL_RCC_USART6_CLKSOURCE_PCLK2       LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_0)
-#define LL_RCC_USART6_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_1)
-#define LL_RCC_USART6_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_2)
-#define LL_RCC_USART6_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_3)
-#define LL_RCC_USART6_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_4)
-
-#define LL_RCC_UART78_CLKSOURCE_PCLK1       LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_0)
-#define LL_RCC_UART78_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_1)
-#define LL_RCC_UART78_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_2)
-#define LL_RCC_UART78_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_3)
-#define LL_RCC_UART78_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_4)
+#define LL_RCC_USART1_CLKSOURCE_PCLK5       LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, 0)
+#define LL_RCC_USART1_CLKSOURCE_PLL3Q       LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_0)
+#define LL_RCC_USART1_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_1)
+#define LL_RCC_USART1_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, (RCC_UART1CKSELR_UART1SRC_1 | RCC_UART1CKSELR_UART1SRC_0))
+#define LL_RCC_USART1_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, RCC_UART1CKSELR_UART1SRC_2)
+#define LL_RCC_USART1_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART1CKSELR, RCC_UART1CKSELR_UART1SRC, (RCC_UART1CKSELR_UART1SRC_2 | RCC_UART1CKSELR_UART1SRC_0))
+
+#define LL_RCC_UART24_CLKSOURCE_PCLK1       LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, 0)
+#define LL_RCC_UART24_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_0)
+#define LL_RCC_UART24_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_1)
+#define LL_RCC_UART24_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, (RCC_UART24CKSELR_UART24SRC_1 | RCC_UART24CKSELR_UART24SRC_0))
+#define LL_RCC_UART24_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART24CKSELR, RCC_UART24CKSELR_UART24SRC, RCC_UART24CKSELR_UART24SRC_2)
+
+#define LL_RCC_UART35_CLKSOURCE_PCLK1       LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, 0)
+#define LL_RCC_UART35_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_0)
+#define LL_RCC_UART35_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_1)
+#define LL_RCC_UART35_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, (RCC_UART35CKSELR_UART35SRC_1 | RCC_UART35CKSELR_UART35SRC_0))
+#define LL_RCC_UART35_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART35CKSELR, RCC_UART35CKSELR_UART35SRC, RCC_UART35CKSELR_UART35SRC_2)
+
+#define LL_RCC_USART6_CLKSOURCE_PCLK2       LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, 0)
+#define LL_RCC_USART6_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_0)
+#define LL_RCC_USART6_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_1)
+#define LL_RCC_USART6_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, (RCC_UART6CKSELR_UART6SRC_1 | RCC_UART6CKSELR_UART6SRC_0))
+#define LL_RCC_USART6_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART6CKSELR, RCC_UART6CKSELR_UART6SRC, RCC_UART6CKSELR_UART6SRC_2)
+
+#define LL_RCC_UART78_CLKSOURCE_PCLK1       LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, 0)
+#define LL_RCC_UART78_CLKSOURCE_PLL4Q       LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_0)
+#define LL_RCC_UART78_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_1)
+#define LL_RCC_UART78_CLKSOURCE_CSI         LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, (RCC_UART78CKSELR_UART78SRC_1 | RCC_UART78CKSELR_UART78SRC_0))
+#define LL_RCC_UART78_CLKSOURCE_HSE         LL_CLKSOURCE(RCC_OFFSET_UART78CKSELR, RCC_UART78CKSELR_UART78SRC, RCC_UART78CKSELR_UART78SRC_2)
 /**
   * @}
   */
@@ -744,15 +744,15 @@ typedef struct
 /** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE  Peripheral SDMMC clock source selection
   * @{
   */
-#define LL_RCC_SDMMC12_CLKSOURCE_HCLK6      LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_0)
-#define LL_RCC_SDMMC12_CLKSOURCE_PLL3R      LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_1)
-#define LL_RCC_SDMMC12_CLKSOURCE_PLL4P      LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_2)
-#define LL_RCC_SDMMC12_CLKSOURCE_HSI        LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_3)
+#define LL_RCC_SDMMC12_CLKSOURCE_HCLK6      LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, 0)
+#define LL_RCC_SDMMC12_CLKSOURCE_PLL3R      LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_0)
+#define LL_RCC_SDMMC12_CLKSOURCE_PLL4P      LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, RCC_SDMMC12CKSELR_SDMMC12SRC_1)
+#define LL_RCC_SDMMC12_CLKSOURCE_HSI        LL_CLKSOURCE(RCC_OFFSET_SDMMC12CKSELR, RCC_SDMMC12CKSELR_SDMMC12SRC, (RCC_SDMMC12CKSELR_SDMMC12SRC_1 | RCC_SDMMC12CKSELR_SDMMC12SRC_0))
 
-#define LL_RCC_SDMMC3_CLKSOURCE_HCLK2       LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_0)
-#define LL_RCC_SDMMC3_CLKSOURCE_PLL3R       LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_1)
-#define LL_RCC_SDMMC3_CLKSOURCE_PLL4P       LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_2)
-#define LL_RCC_SDMMC3_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_3)
+#define LL_RCC_SDMMC3_CLKSOURCE_HCLK2       LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, 0)
+#define LL_RCC_SDMMC3_CLKSOURCE_PLL3R       LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_0)
+#define LL_RCC_SDMMC3_CLKSOURCE_PLL4P       LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, RCC_SDMMC3CKSELR_SDMMC3SRC_1)
+#define LL_RCC_SDMMC3_CLKSOURCE_HSI         LL_CLKSOURCE(RCC_OFFSET_SDMMC3CKSELR, RCC_SDMMC3CKSELR_SDMMC3SRC, (RCC_SDMMC3CKSELR_SDMMC3SRC_1 | RCC_SDMMC3CKSELR_SDMMC3SRC_0))
 /**
   * @}
   */
@@ -760,9 +760,9 @@ typedef struct
 /** @defgroup RCC_LL_EC_ETH_CLKSOURCE  Peripheral ETH clock source selection
   * @{
   */
-#define LL_RCC_ETH_CLKSOURCE_PLL4P          RCC_ETHCKSELR_ETHSRC_0
-#define LL_RCC_ETH_CLKSOURCE_PLL3Q          RCC_ETHCKSELR_ETHSRC_1
-#define LL_RCC_ETH_CLKSOURCE_OFF            RCC_ETHCKSELR_ETHSRC_2
+#define LL_RCC_ETH_CLKSOURCE_PLL4P          0U
+#define LL_RCC_ETH_CLKSOURCE_PLL3Q          RCC_ETHCKSELR_ETHSRC_0
+#define LL_RCC_ETH_CLKSOURCE_OFF            RCC_ETHCKSELR_ETHSRC_1
 /**
   * @}
   */
@@ -770,10 +770,10 @@ typedef struct
 /** @defgroup RCC_LL_EC_QSPI_CLKSOURCE  Peripheral QSPI clock source selection
   * @{
   */
-#define LL_RCC_QSPI_CLKSOURCE_ACLK          RCC_QSPICKSELR_QSPISRC_0
-#define LL_RCC_QSPI_CLKSOURCE_PLL3R         RCC_QSPICKSELR_QSPISRC_1
-#define LL_RCC_QSPI_CLKSOURCE_PLL4P         RCC_QSPICKSELR_QSPISRC_2
-#define LL_RCC_QSPI_CLKSOURCE_PER           RCC_QSPICKSELR_QSPISRC_3
+#define LL_RCC_QSPI_CLKSOURCE_ACLK          0U
+#define LL_RCC_QSPI_CLKSOURCE_PLL3R         RCC_QSPICKSELR_QSPISRC_0
+#define LL_RCC_QSPI_CLKSOURCE_PLL4P         RCC_QSPICKSELR_QSPISRC_1
+#define LL_RCC_QSPI_CLKSOURCE_PER           (RCC_QSPICKSELR_QSPISRC_1 | RCC_QSPICKSELR_QSPISRC_0)
 /**
   * @}
   */
@@ -781,10 +781,10 @@ typedef struct
 /** @defgroup RCC_LL_EC_FMC_CLKSOURCE  Peripheral FMC clock source selection
   * @{
   */
-#define LL_RCC_FMC_CLKSOURCE_ACLK           RCC_FMCCKSELR_FMCSRC_0
-#define LL_RCC_FMC_CLKSOURCE_PLL3R          RCC_FMCCKSELR_FMCSRC_1
-#define LL_RCC_FMC_CLKSOURCE_PLL4P          RCC_FMCCKSELR_FMCSRC_2
-#define LL_RCC_FMC_CLKSOURCE_PER            RCC_FMCCKSELR_FMCSRC_3
+#define LL_RCC_FMC_CLKSOURCE_ACLK           0U
+#define LL_RCC_FMC_CLKSOURCE_PLL3R          RCC_FMCCKSELR_FMCSRC_0
+#define LL_RCC_FMC_CLKSOURCE_PLL4P          RCC_FMCCKSELR_FMCSRC_1
+#define LL_RCC_FMC_CLKSOURCE_PER            (RCC_FMCCKSELR_FMCSRC_1 | RCC_FMCCKSELR_FMCSRC_0)
 /**
   * @}
   */
@@ -793,10 +793,10 @@ typedef struct
 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN clock source selection
   * @{
   */
-#define LL_RCC_FDCAN_CLKSOURCE_HSE          RCC_FDCANCKSELR_FDCANSRC_0
-#define LL_RCC_FDCAN_CLKSOURCE_PLL3Q        RCC_FDCANCKSELR_FDCANSRC_1
-#define LL_RCC_FDCAN_CLKSOURCE_PLL4Q        RCC_FDCANCKSELR_FDCANSRC_2
-#define LL_RCC_FDCAN_CLKSOURCE_PLL4R        RCC_FDCANCKSELR_FDCANSRC_3
+#define LL_RCC_FDCAN_CLKSOURCE_HSE          0U
+#define LL_RCC_FDCAN_CLKSOURCE_PLL3Q        RCC_FDCANCKSELR_FDCANSRC_0
+#define LL_RCC_FDCAN_CLKSOURCE_PLL4Q        RCC_FDCANCKSELR_FDCANSRC_1
+#define LL_RCC_FDCAN_CLKSOURCE_PLL4R        (RCC_FDCANCKSELR_FDCANSRC_1 | RCC_FDCANCKSELR_FDCANSRC_0)
 /**
   * @}
   */
@@ -805,9 +805,9 @@ typedef struct
 /** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE  Peripheral SPDIFRX clock source selection
   * @{
   */
-#define LL_RCC_SPDIFRX_CLKSOURCE_PLL4P      RCC_SPDIFCKSELR_SPDIFSRC_0
-#define LL_RCC_SPDIFRX_CLKSOURCE_PLL3Q      RCC_SPDIFCKSELR_SPDIFSRC_1
-#define LL_RCC_SPDIFRX_CLKSOURCE_HSI        RCC_SPDIFCKSELR_SPDIFSRC_2
+#define LL_RCC_SPDIFRX_CLKSOURCE_PLL4P      0U
+#define LL_RCC_SPDIFRX_CLKSOURCE_PLL3Q      RCC_SPDIFCKSELR_SPDIFSRC_0
+#define LL_RCC_SPDIFRX_CLKSOURCE_HSI        RCC_SPDIFCKSELR_SPDIFSRC_1
 /**
   * @}
   */
@@ -815,9 +815,9 @@ typedef struct
 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection
   * @{
   */
-#define LL_RCC_CEC_CLKSOURCE_LSE            RCC_CECCKSELR_CECSRC_0
-#define LL_RCC_CEC_CLKSOURCE_LSI            RCC_CECCKSELR_CECSRC_1
-#define LL_RCC_CEC_CLKSOURCE_CSI122         RCC_CECCKSELR_CECSRC_2
+#define LL_RCC_CEC_CLKSOURCE_LSE            0U
+#define LL_RCC_CEC_CLKSOURCE_LSI            RCC_CECCKSELR_CECSRC_0
+#define LL_RCC_CEC_CLKSOURCE_CSI122         RCC_CECCKSELR_CECSRC_1
 /**
   * @}
   */
@@ -825,9 +825,9 @@ typedef struct
 /** @defgroup RCC_LL_EC_USBPHY_CLKSOURCE  Peripheral USBPHY clock source selection
   * @{
   */
-#define LL_RCC_USBPHY_CLKSOURCE_HSE         RCC_USBCKSELR_USBPHYSRC_0
-#define LL_RCC_USBPHY_CLKSOURCE_PLL4R       RCC_USBCKSELR_USBPHYSRC_1
-#define LL_RCC_USBPHY_CLKSOURCE_HSE2        RCC_USBCKSELR_USBPHYSRC_2
+#define LL_RCC_USBPHY_CLKSOURCE_HSE         0U
+#define LL_RCC_USBPHY_CLKSOURCE_PLL4R       RCC_USBCKSELR_USBPHYSRC_0
+#define LL_RCC_USBPHY_CLKSOURCE_HSE2        RCC_USBCKSELR_USBPHYSRC_1
 /**
   * @}
   */
@@ -835,8 +835,8 @@ typedef struct
 /** @defgroup RCC_LL_EC_USBO_CLKSOURCE  Peripheral USBO clock source selection
   * @{
   */
-#define LL_RCC_USBO_CLKSOURCE_PLL4R         RCC_USBCKSELR_USBOSRC_0
-#define LL_RCC_USBO_CLKSOURCE_PHY           RCC_USBCKSELR_USBOSRC_1
+#define LL_RCC_USBO_CLKSOURCE_PLL4R         0U
+#define LL_RCC_USBO_CLKSOURCE_PHY           RCC_USBCKSELR_USBOSRC
 /**
   * @}
   */
@@ -844,15 +844,15 @@ typedef struct
 /** @defgroup RCC_LL_EC_RNGx_CLKSOURCE  Peripheral RNG clock source selection
   * @{
   */
-#define LL_RCC_RNG1_CLKSOURCE_CSI           LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_0)
-#define LL_RCC_RNG1_CLKSOURCE_PLL4R         LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_1)
-#define LL_RCC_RNG1_CLKSOURCE_LSE           LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_2)
-#define LL_RCC_RNG1_CLKSOURCE_LSI           LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_3)
+#define LL_RCC_RNG1_CLKSOURCE_CSI           LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, 0)
+#define LL_RCC_RNG1_CLKSOURCE_PLL4R         LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_0)
+#define LL_RCC_RNG1_CLKSOURCE_LSE           LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, RCC_RNG1CKSELR_RNG1SRC_1)
+#define LL_RCC_RNG1_CLKSOURCE_LSI           LL_CLKSOURCE(RCC_OFFSET_RNG1CKSELR, RCC_RNG1CKSELR_RNG1SRC, (RCC_RNG1CKSELR_RNG1SRC_1 | RCC_RNG1CKSELR_RNG1SRC_0))
 
-#define LL_RCC_RNG2_CLKSOURCE_CSI           LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_0)
-#define LL_RCC_RNG2_CLKSOURCE_PLL4R         LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_1)
-#define LL_RCC_RNG2_CLKSOURCE_LSE           LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_2)
-#define LL_RCC_RNG2_CLKSOURCE_LSI           LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_3)
+#define LL_RCC_RNG2_CLKSOURCE_CSI           LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, 0)
+#define LL_RCC_RNG2_CLKSOURCE_PLL4R         LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_0)
+#define LL_RCC_RNG2_CLKSOURCE_LSE           LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, RCC_RNG2CKSELR_RNG2SRC_1)
+#define LL_RCC_RNG2_CLKSOURCE_LSI           LL_CLKSOURCE(RCC_OFFSET_RNG2CKSELR, RCC_RNG2CKSELR_RNG2SRC, (RCC_RNG2CKSELR_RNG2SRC_1 | RCC_RNG2CKSELR_RNG2SRC_0))
 /**
   * @}
   */
@@ -860,10 +860,10 @@ typedef struct
 /** @defgroup RCC_LL_EC_CKPER_CLKSOURCE  Peripheral CKPER clock source selection
   * @{
   */
-#define LL_RCC_CKPER_CLKSOURCE_HSI          RCC_CPERCKSELR_CKPERSRC_0
-#define LL_RCC_CKPER_CLKSOURCE_CSI          RCC_CPERCKSELR_CKPERSRC_1
-#define LL_RCC_CKPER_CLKSOURCE_HSE          RCC_CPERCKSELR_CKPERSRC_2
-#define LL_RCC_CKPER_CLKSOURCE_OFF          RCC_CPERCKSELR_CKPERSRC_3 /*Clock disabled*/
+#define LL_RCC_CKPER_CLKSOURCE_HSI          0U
+#define LL_RCC_CKPER_CLKSOURCE_CSI          RCC_CPERCKSELR_CKPERSRC_0
+#define LL_RCC_CKPER_CLKSOURCE_HSE          RCC_CPERCKSELR_CKPERSRC_1
+#define LL_RCC_CKPER_CLKSOURCE_OFF          (RCC_CPERCKSELR_CKPERSRC_1 | RCC_CPERCKSELR_CKPERSRC_0) /*Clock disabled*/
 /**
   * @}
   */
@@ -871,9 +871,9 @@ typedef struct
 /** @defgroup RCC_LL_EC_STGEN_CLKSOURCE  Peripheral STGEN clock source selection
   * @{
   */
-#define LL_RCC_STGEN_CLKSOURCE_HSI          RCC_STGENCKSELR_STGENSRC_0
-#define LL_RCC_STGEN_CLKSOURCE_HSE          RCC_STGENCKSELR_STGENSRC_1
-#define LL_RCC_STGEN_CLKSOURCE_OFF          RCC_STGENCKSELR_STGENSRC_2
+#define LL_RCC_STGEN_CLKSOURCE_HSI          0U
+#define LL_RCC_STGEN_CLKSOURCE_HSE          RCC_STGENCKSELR_STGENSRC_0
+#define LL_RCC_STGEN_CLKSOURCE_OFF          RCC_STGENCKSELR_STGENSRC_1
 /**
   * @}
   */
@@ -882,8 +882,8 @@ typedef struct
 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral  DSI clock source selection
   * @{
   */
-#define LL_RCC_DSI_CLKSOURCE_PHY            RCC_DSICKSELR_DSISRC_0
-#define LL_RCC_DSI_CLKSOURCE_PLL4P          RCC_DSICKSELR_DSISRC_1
+#define LL_RCC_DSI_CLKSOURCE_PHY            0U
+#define LL_RCC_DSI_CLKSOURCE_PLL4P          RCC_DSICKSELR_DSISRC
 /**
   * @}
   */
@@ -892,9 +892,9 @@ typedef struct
 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection
   * @{
   */
-#define LL_RCC_ADC_CLKSOURCE_PLL4R          RCC_ADCCKSELR_ADCSRC_0
-#define LL_RCC_ADC_CLKSOURCE_PER            RCC_ADCCKSELR_ADCSRC_1
-#define LL_RCC_ADC_CLKSOURCE_PLL3Q          RCC_ADCCKSELR_ADCSRC_2
+#define LL_RCC_ADC_CLKSOURCE_PLL4R          0U
+#define LL_RCC_ADC_CLKSOURCE_PER            RCC_ADCCKSELR_ADCSRC_0
+#define LL_RCC_ADC_CLKSOURCE_PLL3Q          RCC_ADCCKSELR_ADCSRC_1
 /**
   * @}
   */
@@ -902,28 +902,28 @@ typedef struct
 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE  Peripheral LPTIM clock source selection
   * @{
   */
-#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1       LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_0)
-#define LL_RCC_LPTIM1_CLKSOURCE_PLL4P       LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_1)
-#define LL_RCC_LPTIM1_CLKSOURCE_PLL3Q       LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_2)
-#define LL_RCC_LPTIM1_CLKSOURCE_LSE         LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_3)
-#define LL_RCC_LPTIM1_CLKSOURCE_LSI         LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_4)
-#define LL_RCC_LPTIM1_CLKSOURCE_PER         LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_5)
-#define LL_RCC_LPTIM1_CLKSOURCE_OFF         LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_6)
-
-#define LL_RCC_LPTIM23_CLKSOURCE_PCLK3      LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_0)
-#define LL_RCC_LPTIM23_CLKSOURCE_PLL4Q      LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_1)
-#define LL_RCC_LPTIM23_CLKSOURCE_PER        LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_2)
-#define LL_RCC_LPTIM23_CLKSOURCE_LSE        LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_3)
-#define LL_RCC_LPTIM23_CLKSOURCE_LSI        LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_4)
-#define LL_RCC_LPTIM23_CLKSOURCE_OFF        LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_5)
-
-#define LL_RCC_LPTIM45_CLKSOURCE_PCLK3      LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_0)
-#define LL_RCC_LPTIM45_CLKSOURCE_PLL4P      LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_1)
-#define LL_RCC_LPTIM45_CLKSOURCE_PLL3Q      LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_2)
-#define LL_RCC_LPTIM45_CLKSOURCE_LSE        LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_3)
-#define LL_RCC_LPTIM45_CLKSOURCE_LSI        LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_4)
-#define LL_RCC_LPTIM45_CLKSOURCE_PER        LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_5)
-#define LL_RCC_LPTIM45_CLKSOURCE_OFF        LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_6)
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1       LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, 0)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL4P       LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_0)
+#define LL_RCC_LPTIM1_CLKSOURCE_PLL3Q       LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_1)
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE         LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (RCC_LPTIM1CKSELR_LPTIM1SRC_1 | RCC_LPTIM1CKSELR_LPTIM1SRC_0))
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI         LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, RCC_LPTIM1CKSELR_LPTIM1SRC_2)
+#define LL_RCC_LPTIM1_CLKSOURCE_PER         LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_0))
+#define LL_RCC_LPTIM1_CLKSOURCE_OFF         LL_CLKSOURCE(RCC_OFFSET_LPTIM1CKSELR, RCC_LPTIM1CKSELR_LPTIM1SRC, (RCC_LPTIM1CKSELR_LPTIM1SRC_2 | RCC_LPTIM1CKSELR_LPTIM1SRC_1))
+
+#define LL_RCC_LPTIM23_CLKSOURCE_PCLK3      LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, 0)
+#define LL_RCC_LPTIM23_CLKSOURCE_PLL4Q      LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_0)
+#define LL_RCC_LPTIM23_CLKSOURCE_PER        LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_1)
+#define LL_RCC_LPTIM23_CLKSOURCE_LSE        LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, (RCC_LPTIM23CKSELR_LPTIM23SRC_1 | RCC_LPTIM23CKSELR_LPTIM23SRC_0))
+#define LL_RCC_LPTIM23_CLKSOURCE_LSI        LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, RCC_LPTIM23CKSELR_LPTIM23SRC_2)
+#define LL_RCC_LPTIM23_CLKSOURCE_OFF        LL_CLKSOURCE(RCC_OFFSET_LPTIM23CKSELR, RCC_LPTIM23CKSELR_LPTIM23SRC, (RCC_LPTIM23CKSELR_LPTIM23SRC_2 | RCC_LPTIM23CKSELR_LPTIM23SRC_0))
+
+#define LL_RCC_LPTIM45_CLKSOURCE_PCLK3      LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, 0)
+#define LL_RCC_LPTIM45_CLKSOURCE_PLL4P      LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_0)
+#define LL_RCC_LPTIM45_CLKSOURCE_PLL3Q      LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_1)
+#define LL_RCC_LPTIM45_CLKSOURCE_LSE        LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (RCC_LPTIM45CKSELR_LPTIM45SRC_1 | RCC_LPTIM45CKSELR_LPTIM45SRC_0))
+#define LL_RCC_LPTIM45_CLKSOURCE_LSI        LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, RCC_LPTIM45CKSELR_LPTIM45SRC_2)
+#define LL_RCC_LPTIM45_CLKSOURCE_PER        LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_0))
+#define LL_RCC_LPTIM45_CLKSOURCE_OFF        LL_CLKSOURCE(RCC_OFFSET_LPTIM45CKSELR, RCC_LPTIM45CKSELR_LPTIM45SRC, (RCC_LPTIM45CKSELR_LPTIM45SRC_2 | RCC_LPTIM45CKSELR_LPTIM45SRC_1))
 /**
   * @}
   */
@@ -931,11 +931,11 @@ typedef struct
 /** @defgroup RCC_LL_EC_TIMGx_Prescaler_Selection TIMG Prescaler selection
   * @{
   */
-#define LL_RCC_TIMG1PRES_DEACTIVATED        LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, RCC_TIMG1PRER_TIMG1PRE_0)
-#define LL_RCC_TIMG1PRES_ACTIVATED          LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, RCC_TIMG1PRER_TIMG1PRE_1)
+#define LL_RCC_TIMG1PRES_DEACTIVATED        LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, 0)
+#define LL_RCC_TIMG1PRES_ACTIVATED          LL_CLKSOURCE(RCC_OFFSET_TIMG1PRER, RCC_TIMG1PRER_TIMG1PRE, RCC_TIMG1PRER_TIMG1PRE)
 
-#define LL_RCC_TIMG2PRES_DEACTIVATED        LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, RCC_TIMG2PRER_TIMG2PRE_0)
-#define LL_RCC_TIMG2PRES_ACTIVATED          LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, RCC_TIMG2PRER_TIMG2PRE_1)
+#define LL_RCC_TIMG2PRES_DEACTIVATED        LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, 0)
+#define LL_RCC_TIMG2PRES_ACTIVATED          LL_CLKSOURCE(RCC_OFFSET_TIMG2PRER, RCC_TIMG2PRER_TIMG2PRE, RCC_TIMG2PRER_TIMG2PRE)
 /**
   * @}
   */
@@ -943,10 +943,10 @@ typedef struct
 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
   * @{
   */
-#define LL_RCC_RTC_CLKSOURCE_NONE           RCC_BDCR_RTCSRC_0  /*!< No clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSE            RCC_BDCR_RTCSRC_1  /*!< LSE oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSI            RCC_BDCR_RTCSRC_2  /*!< LSI oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_HSE_DIV        RCC_BDCR_RTCSRC_3  /*!< HSE oscillator clock divided by RTCDIV used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_NONE           0U                                       /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE            RCC_BDCR_RTCSRC_0                        /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI            RCC_BDCR_RTCSRC_1                        /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE_DIV        (RCC_BDCR_RTCSRC_1 | RCC_BDCR_RTCSRC_0)  /*!< HSE oscillator clock divided by RTCDIV used as RTC clock */
 /**
   * @}
   */
@@ -1144,9 +1144,9 @@ typedef struct
 /** @defgroup RCC_LL_EC_PLL12SOURCE  PLL1 and PLL2 entry clock source
   * @{
   */
-#define LL_RCC_PLL12SOURCE_HSI        RCC_RCK12SELR_PLL12SRC_0  /*!< HSI clock selected as PLL12 entry clock source */
-#define LL_RCC_PLL12SOURCE_HSE        RCC_RCK12SELR_PLL12SRC_1  /*!< HSE clock selected as PLL12 entry clock source */
-#define LL_RCC_PLL12SOURCE_NONE       RCC_RCK12SELR_PLL12SRC_2  /*!< No clock */
+#define LL_RCC_PLL12SOURCE_HSI        0U                        /*!< HSI clock selected as PLL12 entry clock source */
+#define LL_RCC_PLL12SOURCE_HSE        RCC_RCK12SELR_PLL12SRC_0  /*!< HSE clock selected as PLL12 entry clock source */
+#define LL_RCC_PLL12SOURCE_NONE       RCC_RCK12SELR_PLL12SRC_1  /*!< No clock */
 /**
   * @}
   */
@@ -1154,10 +1154,10 @@ typedef struct
 /** @defgroup RCC_LL_EC_PLL3SOURCE  PLL3 entry clock source
   * @{
   */
-#define LL_RCC_PLL3SOURCE_HSI         RCC_RCK3SELR_PLL3SRC_0  /*!< HSI clock selected as PLL3 entry clock source */
-#define LL_RCC_PLL3SOURCE_HSE         RCC_RCK3SELR_PLL3SRC_1  /*!< HSE clock selected as PLL3 entry clock source */
-#define LL_RCC_PLL3SOURCE_CSI         RCC_RCK3SELR_PLL3SRC_2  /*!< CSI clock selected as PLL3 entry clock source */
-#define LL_RCC_PLL3SOURCE_NONE        RCC_RCK3SELR_PLL3SRC_3  /*!< No clock */
+#define LL_RCC_PLL3SOURCE_HSI         0U                                                 /*!< HSI clock selected as PLL3 entry clock source */
+#define LL_RCC_PLL3SOURCE_HSE         RCC_RCK3SELR_PLL3SRC_0                             /*!< HSE clock selected as PLL3 entry clock source */
+#define LL_RCC_PLL3SOURCE_CSI         RCC_RCK3SELR_PLL3SRC_1                             /*!< CSI clock selected as PLL3 entry clock source */
+#define LL_RCC_PLL3SOURCE_NONE        (RCC_RCK3SELR_PLL3SRC_1 | RCC_RCK3SELR_PLL3SRC_0)  /*!< No clock */
 /**
   * @}
   */
@@ -1165,10 +1165,10 @@ typedef struct
 /** @defgroup RCC_LL_EC_PLL4SOURCE  PLL4 entry clock source
   * @{
   */
-#define LL_RCC_PLL4SOURCE_HSI         RCC_RCK4SELR_PLL4SRC_0  /*!< HSI clock selected as PLL4 entry clock source */
-#define LL_RCC_PLL4SOURCE_HSE         RCC_RCK4SELR_PLL4SRC_1  /*!< HSE clock selected as PLL4 entry clock source */
-#define LL_RCC_PLL4SOURCE_CSI         RCC_RCK4SELR_PLL4SRC_2  /*!< CSI clock selected as PLL4 entry clock source */
-#define LL_RCC_PLL4SOURCE_I2SCKIN     RCC_RCK4SELR_PLL4SRC_3  /*!< Signal I2S_CKIN selected as PLL4 entry clock source */
+#define LL_RCC_PLL4SOURCE_HSI         0U                                                 /*!< HSI clock selected as PLL4 entry clock source */
+#define LL_RCC_PLL4SOURCE_HSE         RCC_RCK4SELR_PLL4SRC_0                             /*!< HSE clock selected as PLL4 entry clock source */
+#define LL_RCC_PLL4SOURCE_CSI         RCC_RCK4SELR_PLL4SRC_1                             /*!< CSI clock selected as PLL4 entry clock source */
+#define LL_RCC_PLL4SOURCE_I2SCKIN     (RCC_RCK4SELR_PLL4SRC_1 | RCC_RCK4SELR_PLL4SRC_0)  /*!< Signal I2S_CKIN selected as PLL4 entry clock source */
 /**
   * @}
   */

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal.c

@@ -54,7 +54,7 @@
  * @brief STM32MP1xx HAL Driver version number
    */
 #define __STM32MP1xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32MP1xx_HAL_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
+#define __STM32MP1xx_HAL_VERSION_SUB1   (0x03U) /*!< [23:16] sub1 version */
 #define __STM32MP1xx_HAL_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32MP1xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32MP1xx_HAL_VERSION         ((__STM32MP1xx_HAL_VERSION_MAIN << 24)\
@@ -292,17 +292,15 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
     return HAL_ERROR;
   }
   /* Configure the SysTick IRQ priority */
-//  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
-//  {
-//    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
-//    uwTickPrio = TickPriority;
-//  }
-//  else
-//  {
-//    return HAL_ERROR;
-//  }
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+  {
     HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
     uwTickPrio = TickPriority;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
 #endif /* CORE_CM4 */
 
 

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc.c

@@ -3,7 +3,7 @@
   * @file    stm32mp1xx_hal_adc.c
   * @author  MCD Application Team
   * @brief   This file provides firmware functions to manage the following
-  *          functionalities of the Analog to Digital Convertor (ADC)
+  *          functionalities of the Analog to Digital Converter (ADC)
   *          peripheral:
   *           + Initialization and de-initialization functions
   *             ++ Initialization and Configuration of ADC
@@ -321,13 +321,11 @@
 #define ADC_CFGR_FIELDS_1  ((uint32_t)(ADC_CFGR_RES    |\
                                        ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
                                        ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
-                                       ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated
-                                                                                  when no regular conversion is on-going */
+                                       ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */
 
 #define ADC_CFGR2_FIELDS  ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OSR  |\
                                        ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
-                                       ADC_CFGR2_ROVSM))                     /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion
-                                                                                 (neither regular nor injected) is on-going  */
+                                       ADC_CFGR2_ROVSM))                     /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going  */
 
 /* Timeout values for ADC operations (enable settling time,                   */
 /*   disable settling time, ...).                                             */
@@ -889,10 +887,10 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
     hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
   }
 
-  /* DeInit the low level hardware: RCC clock, NVIC */
+  /* DeInit the low level hardware */
   hadc->MspDeInitCallback(hadc);
 #else
-  /* DeInit the low level hardware: RCC clock, NVIC */
+  /* DeInit the low level hardware */
   HAL_ADC_MspDeInit(hadc);
 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
 
@@ -969,7 +967,8 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
   * @param  pCallback pointer to the Callback function
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback)
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+                                           pADC_CallbackTypeDef pCallback)
 {
   HAL_StatusTypeDef status = HAL_OK;
 
@@ -2154,7 +2153,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
   /* Disable ADC peripheral if conversions are effectively stopped */
   if (tmp_hal_status == HAL_OK)
   {
-    /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */
+    /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
     MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0UL);
 
     /* Disable the DMA channel (in case of DMA in circular mode or stop       */
@@ -2357,7 +2356,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
     /* Note: Into callback function "HAL_ADC_ConvCpltCallback()",             */
     /*       to determine if conversion has been triggered from EOC or EOS,   */
     /*       possibility to use:                                              */
-    /*        " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "                */
+    /*        " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "               */
 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
     hadc->ConvCpltCallback(hadc);
 #else
@@ -2412,44 +2411,46 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
     /* group having no further conversion upcoming (same conditions as        */
     /* regular group interruption disabling above),                           */
     /* and if injected scan sequence is completed.                            */
-    if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL)            ||
-        ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL)      &&
-         ((tmp_adc_reg_is_trigger_source_sw_start != 0UL)  &&
-          (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
+    if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
     {
-      /* If End of Sequence is reached, disable interrupts */
-      if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+      if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
+          ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+           (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
       {
-        /* Particular case if injected contexts queue is enabled:             */
-        /* when the last context has been fully processed, JSQR is reset      */
-        /* by the hardware. Even if no injected conversion is planned to come */
-        /* (queue empty, triggers are ignored), it can start again            */
-        /* immediately after setting a new context (JADSTART is still set).   */
-        /* Therefore, state of HAL ADC injected group is kept to busy.        */
-        if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
+        /* If End of Sequence is reached, disable interrupts */
+        if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
         {
-          /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit       */
-          /* JADSTART==0 (no conversion on going)                             */
-          if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+          /* Particular case if injected contexts queue is enabled:             */
+          /* when the last context has been fully processed, JSQR is reset      */
+          /* by the hardware. Even if no injected conversion is planned to come */
+          /* (queue empty, triggers are ignored), it can start again            */
+          /* immediately after setting a new context (JADSTART is still set).   */
+          /* Therefore, state of HAL ADC injected group is kept to busy.        */
+          if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
           {
-            /* Disable ADC end of sequence conversion interrupt  */
-            __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+            /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit       */
+            /* JADSTART==0 (no conversion on going)                             */
+            if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+            {
+              /* Disable ADC end of sequence conversion interrupt  */
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
 
-            /* Set ADC state */
-            CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+              /* Set ADC state */
+              CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
 
-            if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
-            {
-              SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+              if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+              {
+                SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+              }
             }
-          }
-          else
-          {
-            /* Update ADC state machine to error */
-            SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+            else
+            {
+              /* Update ADC state machine to error */
+              SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 
-            /* Set ADC error code to ADC peripheral internal error */
-            SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+              /* Set ADC error code to ADC peripheral internal error */
+              SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+            }
           }
         }
       }
@@ -2457,8 +2458,8 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
 
     /* Injected Conversion complete callback */
     /* Note:  HAL_ADCEx_InjectedConvCpltCallback can resort to
-              if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
-              if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
+              if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
+              if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
               interruption has been triggered by end of conversion or end of
               sequence.    */
 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
@@ -2713,7 +2714,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
   uint32_t tmpOffsetShifted;
   uint32_t tmp_config_internal_channel;
-  __IO uint32_t wait_loop_index = 0;
+  __IO uint32_t wait_loop_index = 0UL;
   uint32_t tmp_adc_is_conversion_on_going_regular;
   uint32_t tmp_adc_is_conversion_on_going_injected;
 
@@ -2853,7 +2854,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
       /* Note: these internal measurement paths can be disabled using           */
       /* HAL_ADC_DeInit().                                                      */
 
-      if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+      if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
       {
         /* Configuration of common ADC parameters                                 */
 
@@ -2865,7 +2866,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
         {
           /* If the requested internal measurement path has already been enabled, */
           /* bypass the configuration processing.                                 */
-          if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+          if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+              && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
           {
             if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
             {
@@ -2951,7 +2953,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConf
   *         The setting of these parameters is conditioned to ADC state.
   *         For parameters constraints, see comments of structure
   *         "ADC_AnalogWDGConfTypeDef".
-  * @note   On this STM32 serie, analog watchdog thresholds cannot be modified
+  * @note   On this STM32 series, analog watchdog thresholds cannot be modified
   *         while ADC conversion is on going.
   * @param hadc ADC handle
   * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
@@ -3393,8 +3395,6 @@ HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t Conversio
   return HAL_OK;
 }
 
-
-
 /**
   * @brief  Enable the selected ADC.
   * @note   Prerequisite condition to use this function: ADC must be disabled
@@ -3413,7 +3413,8 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
   if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
   {
     /* Check if conditions to enable the ADC are fulfilled */
-    if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+    if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+                               | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
     {
       /* Update ADC state machine to error */
       SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@@ -3448,12 +3449,12 @@ HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
             4 ADC clock cycle duration */
         /* Note: Test of ADC enabled required due to hardware constraint to     */
         /*       not enable ADC if already enabled.                             */
-        if(LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+        if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
         {
           LL_ADC_Enable(hadc->Instance);
         }
 
-        if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+        if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
         {
           /* Update ADC state machine to error */
           SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
@@ -3662,7 +3663,7 @@ void ADC_DMAError(DMA_HandleTypeDef *hdma)
 void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc)
 {
   uint32_t freq;
-  if(ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
+  if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
   {
     freq = HAL_RCC_GetHCLK2Freq();
     switch(hadc->Init.ClockPrescaler)
@@ -3711,7 +3712,7 @@ void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc)
     }
   }
 
-  if(freq > 20000000UL)
+  if (freq > 20000000UL)
   {
     SET_BIT(hadc->Instance->CR, ADC_CR_BOOST);
   }

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_adc_ex.c

@@ -3,7 +3,7 @@
   * @file    stm32mp1xx_hal_adc_ex.c
   * @author  MCD Application Team
   * @brief   This file provides firmware functions to manage the following
-  *          functionalities of the Analog to Digital Convertor (ADC)
+  *          functionalities of the Analog to Digital Converter (ADC)
   *          peripheral:
   *           + Operation functions
   *             ++ Start, stop, get result of conversions of ADC group injected,
@@ -62,8 +62,7 @@
 
 #define ADC_JSQR_FIELDS  ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
                            ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
-                           ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))  /*!< ADC_JSQR fields of parameters that can be updated anytime
-                                                                  once the ADC is enabled */
+                           ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))  /*!< ADC_JSQR fields of parameters that can be updated anytime once the ADC is enabled */
 
 /* Fixed timeout value for ADC calibration.                                   */
 /* Values defined to be higher than worst cases: maximum ratio between ADC    */
@@ -230,14 +229,14 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc,
   assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
 
   /* Enable the ADC ADEN = 1 to be able to read the linear calibration factor */
-  if(LL_ADC_IsEnabled(hadc->Instance) == 0UL) 
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) 
     {
       tmp_hal_status = ADC_Enable(hadc);
     }
 
   if (tmp_hal_status == HAL_OK)
   {
-   if(LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+   if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
     {
       LL_ADC_REG_StopConversion(hadc->Instance);
       temp_REG_IsConversionOngoing = 1UL;
@@ -246,7 +245,7 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc,
     {
       LinearCalib_Buffer[cnt-1U]=LL_ADC_GetCalibrationLinearFactor(hadc->Instance, ADC_CR_LINCALRDYW6 >> (ADC_LINEAR_CALIB_REG_COUNT-cnt));
     }
-   if(temp_REG_IsConversionOngoing != 0UL)
+   if (temp_REG_IsConversionOngoing != 0UL)
     {
       LL_ADC_REG_StartConversion(hadc->Instance);
     }
@@ -265,7 +264,8 @@ HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc,
   * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
   * @retval HAL state
   */
-HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+                                                 uint32_t CalibrationFactor)
 {
   HAL_StatusTypeDef tmp_hal_status = HAL_OK;
   uint32_t tmp_adc_is_conversion_on_going_regular;
@@ -2057,19 +2057,23 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
     {
       /* Scan each offset register to check if the selected channel is targeted. */
       /* If this is the case, the corresponding offset number is disabled.       */
-      if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+          == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
       {
         LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_1, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
       }
-      if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+          == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
       {
         LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_2, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
       }
-      if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+          == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
       {
         LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
       }
-      if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+          == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfigInjected->InjectedChannel))
       {
         LL_ADC_SetOffset(hadc->Instance, LL_ADC_OFFSET_4, sConfigInjected->InjectedChannel, LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
       }
@@ -2091,7 +2095,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
     if (sConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
     {
       /* Set sampling time of the selected ADC channel */
-      LL_ADC_SetChannelSamplingTime(hadc->Instance, (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel) + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
+      LL_ADC_SetChannelSamplingTime(hadc->Instance,
+                                    (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfigInjected->InjectedChannel)
+                                                                               + 1UL) & 0x1FUL)), sConfigInjected->InjectedSamplingTime);
     }
 
     /* Management of internal measurement channels: Vbat/VrefInt/TempSensor/VddCore   */
@@ -2100,7 +2106,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_I
     /* Note: these internal measurement paths can be disabled using           */
     /* HAL_ADC_DeInit().                                                      */
 
-    if(__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
+    if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfigInjected->InjectedChannel))
     {
       /* Configuration of common ADC parameters (continuation)                */
       /* Software is allowed to change common parameters only when all ADCs   */

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cryp.c

@@ -65,7 +65,13 @@
          new parametres, finally user can  start encryption/decryption.
 
        (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
-
+       
+       (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
+          without having to configure again the Key or the Initialization Vector between each API call,
+          the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
+          Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
+          or HAL_CRYP_Decrypt_DMA().
+          
     [..]
       The cryptographic processor supports following standards:
       (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
@@ -139,13 +145,15 @@
          (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
 
   *** Callback registration ***
-  =============================================
+  =============================
 
+  [..]
   The compilation define  USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
   allows the user to configure dynamically the driver callbacks.
   Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
   to register an interrupt callback.
 
+  [..]
   Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
     (+) InCpltCallback     :  Input FIFO transfer completed callback.
     (+) OutCpltCallback    : Output FIFO transfer completed callback.
@@ -155,6 +163,7 @@
   This function takes as parameters the HAL peripheral handle, the Callback ID
   and a pointer to the user callback function.
 
+  [..]
   Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
   weak function.
   @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
@@ -166,6 +175,7 @@
     (+) MspInitCallback    : CRYP MspInit.
     (+) MspDeInitCallback  : CRYP MspDeInit.
 
+  [..]
   By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
   all callbacks are set to the corresponding weak functions :
   examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
@@ -175,6 +185,7 @@
   if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
   keep and use the user MspInit/MspDeInit functions (registered beforehand)
 
+  [..]
   Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
   Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
   in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
@@ -183,6 +194,7 @@
   using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
   or @ref HAL_CRYP_Init() function.
 
+  [..]
   When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
   not defined, the callback registration feature is not available and all callbacks
   are set to the corresponding weak functions.
@@ -412,6 +424,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
   assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
   assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
   assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
+  assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
 
 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
   if (hcryp->State == HAL_CRYP_STATE_RESET)
@@ -448,6 +461,9 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
   /* Reset Error Code field */
   hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
 
+  /* Reset peripheral Key and IV configuration flag */
+  hcryp->KeyIVConfig = 0U;
+  
   /* Change the CRYP state */
   hcryp->State = HAL_CRYP_STATE_READY;
 
@@ -1218,7 +1234,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
 
         /* Enable CRYP to start DES/TDES process*/
         __HAL_CRYP_ENABLE(hcryp);
-
+        
+        status = HAL_OK;
         break;
 
       case CRYP_AES_ECB:
@@ -1386,7 +1403,8 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
 {
   uint32_t algo;
-  HAL_StatusTypeDef status = HAL_OK;
+  HAL_StatusTypeDef status = HAL_OK;  
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
 
   if (hcryp->State == HAL_CRYP_STATE_READY)
   {
@@ -1467,17 +1485,37 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
       case CRYP_AES_CBC:
       case CRYP_AES_CTR:
 
-        /*  Set the Key*/
-        CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+        if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+        {
+          if (hcryp->KeyIVConfig == 1U)
+          {
+            /* If the Key and IV configuration has to be done only once
+               and if it has already been done, skip it */
+            DoKeyIVConfig = 0U;
+          }
+          else
+          {
+            /* If the Key and IV configuration has to be done only once
+               and if it has not been done already, do it and set KeyIVConfig
+               to keep track it won't have to be done again next time */
+            hcryp->KeyIVConfig = 1U;
+          }
+        }
 
-        /* Set the Initialization Vector IV */
-        if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+        if (DoKeyIVConfig == 1U)
         {
+          /*  Set the Key*/
+          CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+          /* Set the Initialization Vector*/
+          if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+          {
           hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
-          hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
-          hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
-          hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
-        }
+          hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+          hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+          hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+          }
+        } /* if (DoKeyIVConfig == 1U) */
 
         /* Set the phase */
         hcryp->Phase = CRYP_PHASE_PROCESS;
@@ -1974,19 +2012,40 @@ static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
 {
   uint16_t outcount;  /* Temporary CrypOutCount Value */
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
 
-  /*  Set the Key*/
-  CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
-  if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
   {
-    /* Set the Initialization Vector*/
-    hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
-    hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
-    hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
-    hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has not been done already, do it and set KeyIVConfig
+         to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+    }
   }
 
+  if (DoKeyIVConfig == 1U)
+  {
+    /*  Set the Key*/
+    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+    if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+    {
+      /* Set the Initialization Vector*/
+      hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+      hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+      hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+      hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+    }
+  } /* if (DoKeyIVConfig == 1U) */
+
   /* Set the phase */
   hcryp->Phase = CRYP_PHASE_PROCESS;
 
@@ -2021,18 +2080,40 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti
   */
 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
 {
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
 
-  /*  Set the Key*/
-  CRYP_SetKey(hcryp, hcryp->Init.KeySize);
-
-  if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
   {
-    /* Set the Initialization Vector*/
-    hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
-    hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
-    hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
-    hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has not been done already, do it and set KeyIVConfig
+         to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+    }
   }
+
+  if (DoKeyIVConfig == 1U)
+  {
+    /*  Set the Key*/
+    CRYP_SetKey(hcryp, hcryp->Init.KeySize);
+
+    if (hcryp->Init.Algorithm != CRYP_AES_ECB)
+    {
+      /* Set the Initialization Vector*/
+      hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
+      hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
+      hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
+      hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
+    }
+  } /* if (DoKeyIVConfig == 1U) */
+
   /* Set the phase */
   hcryp->Phase = CRYP_PHASE_PROCESS;
 
@@ -2066,7 +2147,27 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
 {
   uint16_t outcount;  /* Temporary CrypOutCount Value */
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
 
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has not been done already, do it and set KeyIVConfig
+         to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+    }
+  }
+
+  if (DoKeyIVConfig == 1U)
+  {
   /*  Key preparation for ECB/CBC */
   if (hcryp->Init.Algorithm != CRYP_AES_CTR)   /*ECB or CBC*/
   {
@@ -2111,6 +2212,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti
     hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
     hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
   }
+} /* if (DoKeyIVConfig == 1U) */
+    
   /* Set the phase */
   hcryp->Phase = CRYP_PHASE_PROCESS;
 
@@ -2146,7 +2249,27 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Ti
 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
 {
   __IO uint32_t count = 0U;
+   uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
 
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has not been done already, do it and set KeyIVConfig
+         to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+    }
+  }
+
+  if (DoKeyIVConfig == 1U)
+  {
   /*  Key preparation for ECB/CBC */
   if (hcryp->Init.Algorithm != CRYP_AES_CTR)
   {
@@ -2194,6 +2317,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
     hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
     hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
   }
+} /* if (DoKeyIVConfig == 1U) */
+    
   /* Set the phase */
   hcryp->Phase = CRYP_PHASE_PROCESS;
   if (hcryp->Size != 0U)
@@ -2224,7 +2349,27 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
 {
   __IO uint32_t count = 0U;
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has not been done already, do it and set KeyIVConfig
+         to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+    }
+  }
 
+  if (DoKeyIVConfig == 1U)
+  {
   /*  Key preparation for ECB/CBC */
   if (hcryp->Init.Algorithm != CRYP_AES_CTR)
   {
@@ -2274,6 +2419,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
     hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
     hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
   }
+} /* if (DoKeyIVConfig == 1U) */
+
   /* Set the phase */
   hcryp->Phase = CRYP_PHASE_PROCESS;
 
@@ -2779,9 +2926,10 @@ static void CRYP_SetMDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, ui
 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
 {
 
-  uint32_t temp;  /* Temporary CrypOutBuff */
+  uint32_t temp[4];  /* Temporary CrypOutBuff */
   uint16_t incount;  /* Temporary CrypInCount Value */
   uint16_t outcount;  /* Temporary CrypOutCount Value */
+  uint32_t i;
 
   /*Temporary CrypOutCount Value*/
   incount = hcryp->CrypInCount;
@@ -2825,18 +2973,17 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
   if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < ((hcryp->Size) / 4U)))
   {
     /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer  */
-    temp  = hcryp->Instance->DOUT;
-    *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
-    hcryp->CrypOutCount++;
-    temp  = hcryp->Instance->DOUT;
-    *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
-    hcryp->CrypOutCount++;
-    temp  = hcryp->Instance->DOUT;
-    *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
-    hcryp->CrypOutCount++;
-    temp  = hcryp->Instance->DOUT;
-    *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
-    hcryp->CrypOutCount++;
+    for (i = 0U; i < 4U; i++)
+    {
+      temp[i] = hcryp->Instance->DOUT;
+    }
+    i = 0U;
+    while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
+    {
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+      hcryp->CrypOutCount++;
+      i++;
+    }
   }
 }
 
@@ -2850,9 +2997,10 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
   */
 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
 {
-  uint32_t temp;  /* Temporary CrypOutBuff */
+  uint32_t temp[4];  /* Temporary CrypOutBuff */
   uint16_t incount; /* Temporary CrypInCount Value */
   uint16_t outcount;  /* Temporary CrypOutCount Value */
+  uint32_t i;
 
   if (hcryp->State == HAL_CRYP_STATE_BUSY)
   {
@@ -2892,18 +3040,17 @@ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
     if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
     {
       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer  */
-      temp  = hcryp->Instance->DOUT;
-      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
-      hcryp->CrypOutCount++;
-      temp  = hcryp->Instance->DOUT;
-      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
-      hcryp->CrypOutCount++;
-      temp  = hcryp->Instance->DOUT;
-      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
-      hcryp->CrypOutCount++;
-      temp  = hcryp->Instance->DOUT;
-      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
-      hcryp->CrypOutCount++;
+      for (i = 0U; i < 4U; i++)
+      {
+        temp[i] = hcryp->Instance->DOUT;
+      }
+      i = 0U;
+      while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
+      {
+        *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+        hcryp->CrypOutCount++;
+        i++;
+      }
       if (hcryp->CrypOutCount == (hcryp->Size / 4U))
       {
         /* Disable interrupts */
@@ -2998,11 +3145,37 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
   uint32_t tickstart;
   uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
   uint32_t npblb ;
-  uint32_t temp ;  /* Temporary CrypOutBuff */
+  uint32_t temp[4];  /* Temporary CrypOutBuff */
   uint32_t index ;
   uint32_t lastwordsize ;
   uint16_t outcount;  /* Temporary CrypOutCount Value */
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+      hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has not been done already, do it and set KeyIVConfig
+         to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+      hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+    }
+  }
+  else
+  {
+    hcryp->SizesSum = hcryp->Size;
+  }
 
+  if (DoKeyIVConfig == 1U)
+  {
   /*  Reset CrypHeaderCount */
   hcryp->CrypHeaderCount = 0U;
 
@@ -3069,7 +3242,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
 
   /* Enable the CRYP peripheral */
   __HAL_CRYP_ENABLE(hcryp);
-
+} /* if (DoKeyIVConfig == 1U) */
+  
   if ((hcryp->Size % 16U) != 0U)
   {
     /* recalculate  wordsize */
@@ -3177,15 +3351,16 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
         for (index = 0U; index < 4U; index++)
         {
           /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
-          temp = hcryp->Instance->DOUT;
-
-          *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+          temp[index] = hcryp->Instance->DOUT;
+        }
+        for (index=0; index<lastwordsize; index++)
+        {
+          *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp[index];
           hcryp->CrypOutCount++;
         }
       }
   }
 
-
   /* Return function status */
   return HAL_OK;
 }
@@ -3199,7 +3374,34 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
 {
   __IO uint32_t count = 0U;
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
 
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+      hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has not been done already, do it and set KeyIVConfig
+      to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+      hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+    }
+  }
+  else
+  {
+    hcryp->SizesSum = hcryp->Size;
+  }
+
+  /* Configure Key, IV and process message (header and payload) */
+  if (DoKeyIVConfig == 1U)
+  {
   /*  Reset CrypHeaderCount */
   hcryp->CrypHeaderCount = 0U;
 
@@ -3243,7 +3445,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
 
   /* Select header phase */
   CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+  } /* end of if (DoKeyIVConfig == 1U) */
   /* Enable interrupts */
   __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
 
@@ -3268,8 +3470,35 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
   uint32_t index;
   uint32_t npblb;
   uint32_t lastwordsize;
-  uint32_t temp;  /* Temporary CrypOutBuff */
-  /*  Reset CrypHeaderCount */
+  uint32_t temp[4];  /* Temporary CrypOutBuff */
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+      hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+         and if it has not been done already, do it and set KeyIVConfig
+         to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+      hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+    }
+  }
+  else
+  {
+    hcryp->SizesSum = hcryp->Size;
+  }
+
+  if (DoKeyIVConfig == 1U)
+  {
+ /*  Reset CrypHeaderCount */
   hcryp->CrypHeaderCount = 0U;
 
   /*************************** Init phase ************************************/
@@ -3329,6 +3558,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
   /* Select payload phase once the header phase is performed */
   CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
 
+} /* if (DoKeyIVConfig == 1U) */
+    
   if (hcryp->Size == 0U)
   {
     /* Process unLocked */
@@ -3421,11 +3652,14 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
     for (index = 0U; index < 4U; index++)
     {
       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
-      temp = hcryp->Instance->DOUT;
-
-      *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+      temp[index] = hcryp->Instance->DOUT;
+    }
+    for (index=0; index<lastwordsize; index++)
+    {
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
       hcryp->CrypOutCount++;
     }
+
     /* Change the CRYP state to ready */
     hcryp->State = HAL_CRYP_STATE_READY;
 
@@ -3451,10 +3685,36 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
   uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
   uint32_t npblb ;
   uint32_t lastwordsize ;
-  uint32_t temp ;  /* Temporary CrypOutBuff */
+  uint32_t temp[4] ;  /* Temporary CrypOutBuff */
   uint32_t index ;
   uint16_t outcount;  /* Temporary CrypOutCount Value */
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
 
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+      hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has not been done already, do it and set KeyIVConfig
+      to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+      hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+    }
+  }
+  else
+  {
+    hcryp->SizesSum = hcryp->Size;
+  }
+
+  if (DoKeyIVConfig == 1U)
+  {
   /*  Reset CrypHeaderCount */
   hcryp->CrypHeaderCount = 0U;
 
@@ -3528,6 +3788,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
   /* Enable the CRYP peripheral */
   __HAL_CRYP_ENABLE(hcryp);
 
+} /* if (DoKeyIVConfig == 1U) */
+   
   if ((hcryp->Size % 16U) != 0U)
   {
     /* recalculate  wordsize */
@@ -3635,11 +3897,13 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
         for (index = 0U; index < 4U; index++)
         {
           /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
-          temp = hcryp->Instance->DOUT;
-
-          *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
-          hcryp->CrypOutCount++;
+          temp[index] = hcryp->Instance->DOUT;
         }
+        for (index=0; index<lastwordsize; index++)
+        {
+          *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
+          hcryp->CrypOutCount++;
+        } 
       }
   }
 
@@ -3656,7 +3920,34 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t
 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
 {
   __IO uint32_t count = 0U;
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
+
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+      hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has not been done already, do it and set KeyIVConfig
+      to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+      hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+    }
+  }
+  else
+  {
+    hcryp->SizesSum = hcryp->Size;
+  }
 
+  /* Configure Key, IV and process message (header and payload) */
+  if (DoKeyIVConfig == 1U)
+  {
   /*  Reset CrypHeaderCount */
   hcryp->CrypHeaderCount = 0U;
 
@@ -3704,7 +3995,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
 
   /* Select header phase */
   CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
-
+} /* end of if (DoKeyIVConfig == 1U) */
   /* Enable interrupts */
   __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
 
@@ -3727,8 +4018,34 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
   uint32_t index;
   uint32_t npblb;
   uint32_t lastwordsize;
-  uint32_t temp;  /* Temporary CrypOutBuff */
+  uint32_t temp[4];  /* Temporary CrypOutBuff */
+  uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
 
+  if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
+  {
+    if (hcryp->KeyIVConfig == 1U)
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has already been done, skip it */
+      DoKeyIVConfig = 0U;
+      hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
+    }
+    else
+    {
+      /* If the Key and IV configuration has to be done only once
+      and if it has not been done already, do it and set KeyIVConfig
+      to keep track it won't have to be done again next time */
+      hcryp->KeyIVConfig = 1U;
+      hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
+    }
+  }
+  else
+  {
+    hcryp->SizesSum = hcryp->Size;
+  }
+
+  if (DoKeyIVConfig == 1U)
+  {
   /*  Reset CrypHeaderCount */
   hcryp->CrypHeaderCount = 0U;
 
@@ -3794,6 +4111,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
 
   /* Select payload phase once the header phase is performed */
   CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
+  } /* if (DoKeyIVConfig == 1U) */
 
   if (hcryp->Size == 0U)
   {
@@ -3885,11 +4203,14 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
     for (index = 0U; index < 4U; index++)
     {
       /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
-      temp = hcryp->Instance->DOUT;
-
-      *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+      temp[index] = hcryp->Instance->DOUT;
+    }
+    for (index=0; index<lastwordsize; index++)
+    {
+      *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[index];
       hcryp->CrypOutCount++;
     }
+
     /* Change the CRYP state to ready */
     hcryp->State = HAL_CRYP_STATE_READY;
 
@@ -3902,7 +4223,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
 }
 
 /**
-  * @brief  Sets the payload phase in iterrupt mode
+  * @brief  Sets the payload phase in interrupt mode
   * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
   *         the configuration information for CRYP module
   * @retval state
@@ -3910,11 +4231,12 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
 {
   uint32_t loopcounter;
-  uint32_t temp;  /* Temporary CrypOutBuff */
+  uint32_t temp[4];  /* Temporary CrypOutBuff */
   uint32_t lastwordsize;
   uint32_t npblb;
   uint32_t temp_cr_algodir;
   uint8_t negative = 0U;
+  uint32_t i;
 
   /***************************** Payload phase *******************************/
 
@@ -3953,7 +4275,6 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
       {
         /* Disable interrupts */
         __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
-        
         /* Call the input data transfer complete callback */
 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
         /*Call registered Input complete callback*/
@@ -3969,23 +4290,22 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
         if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
         {
           /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer  */
-          temp  = hcryp->Instance->DOUT;
-          *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
-          hcryp->CrypOutCount++;
-          temp  = hcryp->Instance->DOUT;
-          *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
-          hcryp->CrypOutCount++;
-          temp  = hcryp->Instance->DOUT;
-          *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
-          hcryp->CrypOutCount++;
-          temp  = hcryp->Instance->DOUT;
-          *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp;
-          hcryp->CrypOutCount++;
+          for (i = 0U; i < 4U; i++)
+          {
+            temp[i] = hcryp->Instance->DOUT;
+          }
+          i = 0U;
+          while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
+          {
+            *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+            hcryp->CrypOutCount++;
+            i++;
+          }
           if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
           {
             /* Disable interrupts */
             __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
-            
+
             /* Change the CRYP state */
             hcryp->State = HAL_CRYP_STATE_READY;
             
@@ -4018,16 +4338,16 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
     
       /* Set Npblb in case of AES GCM payload encryption and CCM decryption to get right tag */
       temp_cr_algodir = hcryp->Instance->CR & CRYP_CR_ALGODIR;
-      
+
       if (((temp_cr_algodir == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM)) ||
           ((temp_cr_algodir == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
       {
         /* Disable the CRYP */
         __HAL_CRYP_DISABLE(hcryp);
-        
+
         /* Specify the number of non-valid bytes using NPBLB register*/
         MODIFY_REG(hcryp->Instance->CR, CRYP_CR_NPBLB, npblb << 20);
-        
+
         /* Enable CRYP to start the final phase */
         __HAL_CRYP_ENABLE(hcryp);
       }
@@ -4062,18 +4382,29 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
     /*Read the output block from the output FIFO */
     if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
     {
-      for (loopcounter = 0U; loopcounter < 4U; loopcounter++)
+      for (i = 0U; i < 4U; i++)
       {
-        /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
-        temp = hcryp->Instance->DOUT;
-
-        *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = temp;
+        temp[i] = hcryp->Instance->DOUT;
+      }
+      if (( (hcryp->Size)/4U)==0U)
+      {
+        for (i = 0U; (uint16_t)i<((hcryp->Size)%4U); i++)
+        {
+          *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
+          hcryp->CrypOutCount++;
+        }     
+      }
+      i = 0U;
+      while(((hcryp->CrypOutCount < ((hcryp->Size)/4U))) && (i<4U))
+      {
+        *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
         hcryp->CrypOutCount++;
+        i++;
       }
     }
 
     /* Disable the output FIFO Interrupt */
-    if (hcryp->CrypOutCount > ((hcryp->Size) / 4U))
+    if (hcryp->CrypOutCount >= ((hcryp->Size) / 4U))
     {
       /* Disable interrupts */
       __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_cryp_ex.c

@@ -110,7 +110,7 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u
 {
   uint32_t tickstart;
   uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */
-  uint64_t inputlength = (uint64_t)(hcryp->Size) * 8U; /* input length in bits */
+  uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* input length in bits */
   uint32_t tagaddr = (uint32_t)AuthTag;
 
   if (hcryp->State == HAL_CRYP_STATE_READY)

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_dfsdm.c

@@ -157,23 +157,26 @@
 
     *** Callback registration ***
     =============================
-
+    [..]
     The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1
     allows the user to configure dynamically the driver callbacks.
-    Use functions @ref HAL_DFSDM_Channel_RegisterCallback(),
-    @ref HAL_DFSDM_Filter_RegisterCallback() or
-    @ref HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
+    Use functions HAL_DFSDM_Channel_RegisterCallback(),
+    HAL_DFSDM_Filter_RegisterCallback() or
+    HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback.
 
-    Function @ref HAL_DFSDM_Channel_RegisterCallback() allows to register
+    [..]
+    Function HAL_DFSDM_Channel_RegisterCallback() allows to register
     following callbacks:
       (+) CkabCallback      : DFSDM channel clock absence detection callback.
       (+) ScdCallback       : DFSDM channel short circuit detection callback.
       (+) MspInitCallback   : DFSDM channel MSP init callback.
       (+) MspDeInitCallback : DFSDM channel MSP de-init callback.
+    [..]
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
 
-    Function @ref HAL_DFSDM_Filter_RegisterCallback() allows to register
+    [..]
+    Function HAL_DFSDM_Filter_RegisterCallback() allows to register
     following callbacks:
       (+) RegConvCpltCallback     : DFSDM filter regular conversion complete callback.
       (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
@@ -182,26 +185,33 @@
       (+) ErrorCallback           : DFSDM filter error callback.
       (+) MspInitCallback         : DFSDM filter MSP init callback.
       (+) MspDeInitCallback       : DFSDM filter MSP de-init callback.
+    [..]
     This function takes as parameters the HAL peripheral handle, the Callback ID
     and a pointer to the user callback function.
 
+    [..]
     For specific DFSDM filter analog watchdog callback use dedicated register callback:   
-    @ref HAL_DFSDM_Filter_RegisterAwdCallback().
+    HAL_DFSDM_Filter_RegisterAwdCallback().
 
-    Use functions @ref HAL_DFSDM_Channel_UnRegisterCallback() or
-    @ref HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
+    [..]
+    Use functions HAL_DFSDM_Channel_UnRegisterCallback() or
+    HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default
     weak function.
 
-    @ref HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    [..]
+    HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle,
     and the Callback ID.
+    [..]
     This function allows to reset following callbacks:
       (+) CkabCallback      : DFSDM channel clock absence detection callback.
       (+) ScdCallback       : DFSDM channel short circuit detection callback.
       (+) MspInitCallback   : DFSDM channel MSP init callback.
       (+) MspDeInitCallback : DFSDM channel MSP de-init callback.
 
-    @ref HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    [..]
+    HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle,
     and the Callback ID.
+    [..]
     This function allows to reset following callbacks:
       (+) RegConvCpltCallback     : DFSDM filter regular conversion complete callback.
       (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback.
@@ -211,26 +221,30 @@
       (+) MspInitCallback         : DFSDM filter MSP init callback.
       (+) MspDeInitCallback       : DFSDM filter MSP de-init callback.
 
+    [..]
     For specific DFSDM filter analog watchdog callback use dedicated unregister callback:
-    @ref HAL_DFSDM_Filter_UnRegisterAwdCallback().
+    HAL_DFSDM_Filter_UnRegisterAwdCallback().
 
+    [..]
     By default, after the call of init function and if the state is RESET 
     all callbacks are reset to the corresponding legacy weak functions: 
-    examples @ref HAL_DFSDM_ChannelScdCallback(), @ref HAL_DFSDM_FilterErrorCallback().
+    examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback().
     Exception done for MspInit and MspDeInit callbacks that are respectively
     reset to the legacy weak functions in the init and de-init only when these 
     callbacks are null (not registered beforehand).
     If not, MspInit or MspDeInit are not null, the init and de-init keep and use
     the user MspInit/MspDeInit callbacks (registered beforehand)
 
+    [..]
     Callbacks can be registered/unregistered in READY state only.
     Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
     in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
     during the init/de-init.
     In that case first register the MspInit/MspDeInit user callbacks using 
-    @ref HAL_DFSDM_Channel_RegisterCallback() or
-    @ref HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
+    HAL_DFSDM_Channel_RegisterCallback() or
+    HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function.
 
+    [..]
     When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or
     not defined, the callback registering feature is not available 
     and weak callbacks are used.
@@ -359,7 +373,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan
     return HAL_ERROR;
   }
   
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
   /* Reset callback pointers to the weak predefined callbacks */
   hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback;
   hdfsdm_channel->ScdCallback  = HAL_DFSDM_ChannelScdCallback;
@@ -469,7 +483,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch
   }
 
   /* Call MSP deinit function */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
   if(hdfsdm_channel->MspDeInitCallback == NULL)
   {
     hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit;
@@ -518,7 +532,7 @@ __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chann
    */
 }
 
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a user DFSDM channel callback
   *         to be used instead of the weak predefined callback.
@@ -1272,7 +1286,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter
   hdfsdm_filter->InjConvRemaining    = 1;
   hdfsdm_filter->ErrorCode           = DFSDM_FILTER_ERROR_NONE;
   
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
   /* Reset callback pointers to the weak predefined callbacks */
   hdfsdm_filter->AwdCallback             = HAL_DFSDM_FilterAwdCallback;
   hdfsdm_filter->RegConvCpltCallback     = HAL_DFSDM_FilterRegConvCpltCallback;
@@ -1380,7 +1394,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filt
   hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
   
   /* Call MSP deinit function */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
   if(hdfsdm_filter->MspDeInitCallback == NULL)
   {
     hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit;
@@ -1426,7 +1440,7 @@ __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
    */
 }
 
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
 /**
   * @brief  Register a user DFSDM filter callback
   *         to be used instead of the weak predefined callback.
@@ -1872,7 +1886,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe
     {
       /* Update error code and call error callback */
       hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
       hdfsdm_filter->ErrorCallback(hdfsdm_filter);
 #else
       HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
@@ -2283,7 +2297,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe
     {
       /* Update error code and call error callback */
       hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
       hdfsdm_filter->ErrorCallback(hdfsdm_filter);
 #else
       HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
@@ -2891,7 +2905,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
     hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
 
     /* Call error callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
     hdfsdm_filter->ErrorCallback(hdfsdm_filter);
 #else
     HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
@@ -2908,7 +2922,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
     hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
 
     /* Call error callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
     hdfsdm_filter->ErrorCallback(hdfsdm_filter);
 #else
     HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
@@ -2919,7 +2933,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
           ((temp_fltcr2 & DFSDM_FLTCR2_REOCIE) != 0U))
   {
     /* Call regular conversion complete callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
     hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
 #else
     HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
@@ -2942,7 +2956,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
           ((temp_fltcr2 & DFSDM_FLTCR2_JEOCIE) != 0U))
   {
     /* Call injected conversion complete callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
     hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
 #else
     HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
@@ -2993,7 +3007,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
                                         (1UL << channel);
 
     /* Call analog watchdog callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
     hdfsdm_filter->AwdCallback(hdfsdm_filter, channel, threshold);
 #else
     HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
@@ -3021,7 +3035,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
           hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
 
           /* Call clock absence callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
           a_dfsdm1ChannelHandle[channel]->CkabCallback(a_dfsdm1ChannelHandle[channel]);
 #else
           HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
@@ -3052,7 +3066,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
     hdfsdm_filter->Instance->FLTICR = (1UL << (DFSDM_FLTICR_CLRSCDF_Pos + channel));
 
     /* Call short circuit detection callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
     a_dfsdm1ChannelHandle[channel]->ScdCallback(a_dfsdm1ChannelHandle[channel]);
 #else
     HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
@@ -3223,7 +3237,7 @@ static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
   DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
 
   /* Call regular half conversion complete callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
   hdfsdm_filter->RegConvHalfCpltCallback(hdfsdm_filter);
 #else
   HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
@@ -3241,7 +3255,7 @@ static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
   DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
 
   /* Call regular conversion complete callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
   hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter);
 #else
   HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
@@ -3259,7 +3273,7 @@ static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
   DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
 
   /* Call injected half conversion complete callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
   hdfsdm_filter->InjConvHalfCpltCallback(hdfsdm_filter);
 #else
   HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
@@ -3277,7 +3291,7 @@ static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
   DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
 
   /* Call injected conversion complete callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
   hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter);
 #else
   HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
@@ -3298,7 +3312,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
   hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
 
   /* Call error callback */
-#if defined (USE_HAL_DFSDM_REGISTER_CALLBACKS) && (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1U)
+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
   hdfsdm_filter->ErrorCallback(hdfsdm_filter);
 #else
   HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
@@ -3366,14 +3380,10 @@ static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef* Instan
   {
     channel = 6;
   }
-  else if(Instance == DFSDM1_Channel7)
+  else /* DFSDM1_Channel7 */
   {
     channel = 7;
   }
-  else
-  {
-    channel = 0;
-  }
 
   return channel;
 }

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_pwr.c

@@ -607,7 +607,13 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
   SET_BIT(PWR->MPUCR, PWR_MPUCR_CSTBYDIS);
 
   /* RCC Stop Request Set Register */
+#if defined(RCC_MP_SREQSETR_STPREQ_P0) & defined(RCC_MP_SREQSETR_STPREQ_P1)
+  /* CA7_CORE0 and CA7_CORE1 available */
   RCC->MP_SREQSETR = RCC_MP_SREQSETR_STPREQ_P0 | RCC_MP_SREQSETR_STPREQ_P1;
+#else
+  /* Only CA7_CORE0 available */
+  RCC->MP_SREQSETR = RCC_MP_SREQSETR_STPREQ_P0;
+#endif /* RCC_MP_SREQSETR_STPREQ_P0 & RCC_MP_SREQSETR_STPREQ_P1 */
 
 #else
   /* Prevent unused argument compilation warning */
@@ -635,7 +641,13 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
 
 #ifdef CORE_CA7
   /* RCC Clear Request Set Register */
-  RCC->MP_SREQCLRR = RCC_MP_SREQSETR_STPREQ_P0 | RCC_MP_SREQSETR_STPREQ_P1;
+#if defined(RCC_MP_SREQCLRR_STPREQ_P0) & defined(RCC_MP_SREQCLRR_STPREQ_P1)
+  /* CA7_CORE0 and CA7_CORE1 available */
+  RCC->MP_SREQCLRR = RCC_MP_SREQCLRR_STPREQ_P0 | RCC_MP_SREQCLRR_STPREQ_P1;
+#else
+  /* Only CA7_CORE0 available */
+  RCC->MP_SREQCLRR = RCC_MP_SREQCLRR_STPREQ_P0;
+#endif /* RCC_MP_SREQCLRR_STPREQ_P0 | RCC_MP_SREQCLRR_STPREQ_P1 */
 #endif
 }
 
@@ -672,7 +684,13 @@ void HAL_PWR_EnterSTANDBYMode(void)
   CLEAR_BIT(PWR->MPUCR, PWR_MPUCR_CSTBYDIS);
 
   /* RCC Stop Request Set Register */
+#if defined(RCC_MP_SREQSETR_STPREQ_P0) & defined(RCC_MP_SREQSETR_STPREQ_P1)
+  /* CA7_CORE0 and CA7_CORE1 available */
   RCC->MP_SREQSETR = RCC_MP_SREQSETR_STPREQ_P0 | RCC_MP_SREQSETR_STPREQ_P1;
+#else
+  /* Only CA7_CORE0 available */
+  RCC->MP_SREQSETR = RCC_MP_SREQSETR_STPREQ_P0;
+#endif /* RCC_MP_SREQSETR_STPREQ_P0 & RCC_MP_SREQSETR_STPREQ_P1 */
 #endif
 
   /* Clear Reset Status */

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rcc.c

@@ -203,37 +203,37 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
   CLEAR_REG(RCC->MCO2CFGR);
 
   /* Reset MPU Clock Selection Register */
-  MODIFY_REG(RCC->MPCKSELR, (RCC_MPCKSELR_MPUSRC), RCC_MPCKSELR_MPUSRC_0);
+  MODIFY_REG(RCC->MPCKSELR, (RCC_MPCKSELR_MPUSRC), 0U);
 
   /* Reset AXI Sub-System Clock Selection Register */
-  MODIFY_REG(RCC->ASSCKSELR, (RCC_ASSCKSELR_AXISSRC), RCC_ASSCKSELR_AXISSRC_0);
+  MODIFY_REG(RCC->ASSCKSELR, (RCC_ASSCKSELR_AXISSRC), 0U);
 
   /* Reset MCU Sub-System Clock Selection Register */
-  MODIFY_REG(RCC->MSSCKSELR, (RCC_MSSCKSELR_MCUSSRC), RCC_MSSCKSELR_MCUSSRC_0);
+  MODIFY_REG(RCC->MSSCKSELR, (RCC_MSSCKSELR_MCUSSRC), 0U);
 
   /* Reset RCC MPU Clock Divider Register */
-  MODIFY_REG(RCC->MPCKDIVR, (RCC_MPCKDIVR_MPUDIV), RCC_MPCKDIVR_MPUDIV_1);
+  MODIFY_REG(RCC->MPCKDIVR, (RCC_MPCKDIVR_MPUDIV), RCC_MPCKDIVR_MPUDIV_0);
 
   /* Reset RCC AXI Clock Divider Register */
-  MODIFY_REG(RCC->AXIDIVR, (RCC_AXIDIVR_AXIDIV), RCC_AXIDIVR_AXIDIV_0);
+  MODIFY_REG(RCC->AXIDIVR, (RCC_AXIDIVR_AXIDIV), 0U);
 
   /* Reset RCC APB4 Clock Divider Register */
-  MODIFY_REG(RCC->APB4DIVR, (RCC_APB4DIVR_APB4DIV), RCC_APB4DIVR_APB4DIV_0);
+  MODIFY_REG(RCC->APB4DIVR, (RCC_APB4DIVR_APB4DIV), 0U);
 
   /* Reset RCC APB5 Clock Divider Register */
-  MODIFY_REG(RCC->APB5DIVR, (RCC_APB5DIVR_APB5DIV), RCC_APB5DIVR_APB5DIV_0);
+  MODIFY_REG(RCC->APB5DIVR, (RCC_APB5DIVR_APB5DIV), 0U);
 
   /* Reset RCC MCU Clock Divider Register */
-  MODIFY_REG(RCC->MCUDIVR, (RCC_MCUDIVR_MCUDIV), RCC_MCUDIVR_MCUDIV_0);
+  MODIFY_REG(RCC->MCUDIVR, (RCC_MCUDIVR_MCUDIV), 0U);
 
   /* Reset RCC APB1 Clock Divider Register */
-  MODIFY_REG(RCC->APB1DIVR, (RCC_APB1DIVR_APB1DIV), RCC_APB1DIVR_APB1DIV_0);
+  MODIFY_REG(RCC->APB1DIVR, (RCC_APB1DIVR_APB1DIV), 0U);
 
   /* Reset RCC APB2 Clock Divider Register */
-  MODIFY_REG(RCC->APB2DIVR, (RCC_APB2DIVR_APB2DIV), RCC_APB2DIVR_APB2DIV_0);
+  MODIFY_REG(RCC->APB2DIVR, (RCC_APB2DIVR_APB2DIV), 0U);
 
   /* Reset RCC APB3 Clock Divider Register */
-  MODIFY_REG(RCC->APB3DIVR, (RCC_APB3DIVR_APB3DIV), RCC_APB3DIVR_APB3DIV_0);
+  MODIFY_REG(RCC->APB3DIVR, (RCC_APB3DIVR_APB3DIV), 0U);
 
   /* Disable PLL1 outputs */
   CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN | RCC_PLL1CR_DIVQEN |
@@ -324,13 +324,13 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
   CLEAR_BIT(RCC->PLL4CR, RCC_PLL4CR_SSCG_CTRL);
 
   /* Reset PLL 1 and 2 Ref. Clock Selection Register */
-  MODIFY_REG(RCC->RCK12SELR, (RCC_RCK12SELR_PLL12SRC), RCC_RCK12SELR_PLL12SRC_0);
+  MODIFY_REG(RCC->RCK12SELR, (RCC_RCK12SELR_PLL12SRC), 0U);
 
   /* Reset RCC PLL 3 Ref. Clock Selection Register */
-  MODIFY_REG(RCC->RCK3SELR, (RCC_RCK3SELR_PLL3SRC), RCC_RCK3SELR_PLL3SRC_0);
+  MODIFY_REG(RCC->RCK3SELR, (RCC_RCK3SELR_PLL3SRC), 0U);
 
   /* Reset PLL4 Ref. Clock Selection Register */
-  MODIFY_REG(RCC->RCK4SELR, (RCC_RCK4SELR_PLL4SRC), RCC_RCK4SELR_PLL4SRC_0);
+  MODIFY_REG(RCC->RCK4SELR, (RCC_RCK4SELR_PLL4SRC), 0U);
 
   /* Reset RCC PLL1 Configuration Register 1 */
   WRITE_REG(RCC->PLL1CFGR1, 0x00010031U);

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_rtc_ex.c

@@ -2458,6 +2458,9 @@ HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef *hrtc, RTC_SecureSta
   * @}
   */
 
+/**
+  * @}
+  */
 #endif /* HAL_RTC_MODULE_ENABLED */
 
 /**

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_sai_ex.c

@@ -37,9 +37,15 @@
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
+/** @defgroup SAIEx_Private_Defines SAIEx Extended Private Defines
+  * @{
+  */
 #define SAI_PDM_DELAY_MASK          0x77U
 #define SAI_PDM_DELAY_OFFSET        8U
 #define SAI_PDM_RIGHT_DELAY_OFFSET  4U
+/**
+  * @}
+  */
 
 /* Private macros ------------------------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
@@ -71,12 +77,18 @@
 HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay)
 {
   HAL_StatusTypeDef status = HAL_OK;
+  uint32_t offset;
   SAI_TypeDef *SaiBaseAddress;
 
+#if defined(SAI4)
   /* Get the SAI base address according to the SAI handle */
   SaiBaseAddress = (hsai->Instance == SAI1_Block_A) ? SAI1 : \
                    ((hsai->Instance == SAI4_Block_A) ? SAI4 : \
                      NULL);
+#else
+  /* Get the SAI base address according to the SAI handle */
+  SaiBaseAddress = (hsai->Instance == SAI1_Block_A) ? SAI1 : NULL;
+#endif
 
   /* Check that SAI sub-block is SAI sub-block A */
   if (SaiBaseAddress == NULL)
@@ -90,15 +102,17 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_Pdm
     assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->LeftDelay));
     assert_param(IS_SAI_PDM_MIC_DELAY(pdmMicDelay->RightDelay));
 
-    /* Check SAI state */
-    if (hsai->State != HAL_SAI_STATE_RESET)
+    /* Compute offset on PDMDLY register according mic pair number */
+    offset = SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1U);
+
+    /* Check SAI state and offset */
+    if ((hsai->State != HAL_SAI_STATE_RESET) && (offset <= 24U))
     {
       /* Reset current delays for specified microphone */
-      SaiBaseAddress->PDMDLY &= ~(SAI_PDM_DELAY_MASK << (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1)));
+      SaiBaseAddress->PDMDLY &= ~(SAI_PDM_DELAY_MASK << offset);
 
       /* Apply new microphone delays */
-      SaiBaseAddress->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << \
-                                 (SAI_PDM_DELAY_OFFSET * (pdmMicDelay->MicPair - 1)));
+      SaiBaseAddress->PDMDLY |= (((pdmMicDelay->RightDelay << SAI_PDM_RIGHT_DELAY_OFFSET) | pdmMicDelay->LeftDelay) << offset);
     }
     else
     {

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_smartcard.c

@@ -0,0 +1,2323 @@
+/**
+  ******************************************************************************
+  * @file    stm32mp1xx_hal_smartcard.c
+  * @author  MCD Application Team
+  * @version $VERSION$
+  * @date    $DATE$
+  * @brief   SMARTCARD HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the SMARTCARD peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Error functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The SMARTCARD HAL driver can be used as follows:
+
+    (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard).
+    (#) Associate a USART to the SMARTCARD handle hsmartcard.
+    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
+        (++) Enable the USARTx interface clock.
+        (++) USART pins configuration:
+            (+++) Enable the clock for the USART GPIOs.
+            (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input).
+        (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
+             and HAL_SMARTCARD_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
+             and HAL_SMARTCARD_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
+
+    (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly,
+        the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission
+        error enabling or disabling in the hsmartcard handle Init structure.
+
+    (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...)
+        in the hsmartcard handle AdvancedInit structure.
+
+    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
+        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
+             by calling the customized HAL_SMARTCARD_MspInit() API.
+        [..]
+        (@) The specific SMARTCARD interrupts (Transmission complete interrupt,
+             RXNE interrupt and Error Interrupts) will be managed using the macros
+             __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
+
+    [..]
+    [..] Three operation modes are available within this driver :
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]
+       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit()
+       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
+
+     *** Interrupt mode IO operation ***
+     ===================================
+     [..]
+       (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT()
+       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+       (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT()
+       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+     *** DMA mode IO operation ***
+     ==============================
+     [..]
+       (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA()
+       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback()
+       (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA()
+       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback()
+       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback()
+
+     *** SMARTCARD HAL driver macros list ***
+     ========================================
+     [..]
+       Below the list of most used macros in SMARTCARD HAL driver.
+
+       (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set
+       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
+       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
+       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
+       (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled
+
+     [..]
+       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMARTCARD SMARTCARD
+  * @brief HAL SMARTCARD module driver
+  * @{
+  */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants
+ * @{
+ */
+#define SMARTCARD_TEACK_REACK_TIMEOUT               1000      /*!< SMARTCARD TX or RX enable acknowledge time-out value  */
+
+#define USART_CR1_FIELDS      ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \
+                                          USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8 | \
+                                          USART_CR1_FIFOEN)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR2_CLK_FIELDS  ((uint32_t)(USART_CR2_CLKEN|USART_CR2_CPOL|USART_CR2_CPHA|USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */
+#define USART_CR2_FIELDS      ((uint32_t)(USART_CR2_RTOEN|USART_CR2_CLK_FIELDS|USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */
+#define USART_CR3_FIELDS      ((uint32_t)(USART_CR3_ONEBIT|USART_CR3_NACK|USART_CR3_SCARCNT|\
+                                          USART_CR3_TXFTCFG|USART_CR3_RXFTCFG))   /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup SMARTCARD_Private_Functions
+  * @{
+  */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard);
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
+  * @{
+  */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and Configuration functions #####
+  ==============================================================================
+  [..]
+  This subsection provides a set of functions allowing to initialize the USARTx
+  associated to the SmartCard.
+  (+) These parameters can be configured:
+      (++) Baud Rate
+      (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity
+      (++) Receiver/transmitter modes
+      (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters)
+      (++) Prescaler value
+      (++) Guard bit time
+      (++) NACK enabling or disabling on transmission error
+
+  (+) The following advanced features can be configured as well:
+      (++) TX and/or RX pin level inversion
+      (++) data logical level inversion
+      (++) RX and TX pins swap
+      (++) RX overrun detection disabling
+      (++) DMA disabling on RX error
+      (++) MSB first on communication line
+      (++) Time out enabling (and if activated, timeout value)
+      (++) Block length
+      (++) Auto-retry counter
+  [..]
+  The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures
+  (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  The USART frame format is given in the following table:
+
+    Table 1. USART frame format.
+    +---------------------------------------------------------------+        
+    | M1M0 bits |  PCE bit  |            USART frame                |        
+    |-----------------------|---------------------------------------|        
+    |     01    |    1      |    | SB | 8 bit data | PB | STB |     |        
+    +---------------------------------------------------------------+        
+
+
+  * @{
+  */
+
+/**
+  * @brief  Initialize the SMARTCARD mode according to the specified
+  *         parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check the SMARTCARD handle allocation */
+  if(hsmartcard == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the USART associated to the SMARTCARD handle */
+  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    hsmartcard->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_SMARTCARD_MspInit(hsmartcard);
+  }
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Disable the Peripheral to set smartcard mode */
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+  /* In SmartCard mode, the following bits must be kept cleared:
+  - LINEN in the USART_CR2 register,
+  - HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN);
+  CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN));
+
+  /* set the USART in SMARTCARD mode */
+  SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN);
+
+  /* Set the SMARTCARD Communication parameters */
+  if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Set the SMARTCARD transmission completion indication */  
+  SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard);
+
+  if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT)
+  {
+    SMARTCARD_AdvFeatureConfig(hsmartcard);
+  }
+
+  /* Enable the Peripheral */
+  SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+  /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */
+  return (SMARTCARD_CheckIdleState(hsmartcard));
+}
+
+/**
+  * @brief  DeInitialize the SMARTCARD peripheral.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check the SMARTCARD handle allocation */
+  if(hsmartcard == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the USART/UART associated to the SMARTCARD handle */
+  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+
+  hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+  WRITE_REG(hsmartcard->Instance->CR1, 0x0);
+  WRITE_REG(hsmartcard->Instance->CR2, 0x0);
+  WRITE_REG(hsmartcard->Instance->CR3, 0x0);
+  WRITE_REG(hsmartcard->Instance->RTOR, 0x0);
+  WRITE_REG(hsmartcard->Instance->GTPR, 0x0);
+
+  /* DeInit the low level hardware */
+  HAL_SMARTCARD_MspDeInit(hsmartcard);
+
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+  hsmartcard->gState    = HAL_SMARTCARD_STATE_RESET;
+  hsmartcard->RxState   = HAL_SMARTCARD_STATE_RESET;
+
+  /* Process Unlock */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the SMARTCARD MSP.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the SMARTCARD MSP.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_MspDeInit can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions
+  *  @brief   SMARTCARD Transmit and Receive functions
+  *
+@verbatim
+  ==============================================================================
+                         ##### IO operation functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
+
+  [..]
+    Smartcard is a single wire half duplex communication protocol.
+    The Smartcard interface is designed to support asynchronous protocol Smartcards as
+    defined in the ISO 7816-3 standard. The USART should be configured as:
+    (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
+    (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
+
+  [..]
+    (+) There are two modes of transfer:
+        (++) Blocking mode: The communication is performed in polling mode.
+             The HAL status of all data processing is returned by the same function
+             after finishing transfer.
+        (++) Non-Blocking mode: The communication is performed using Interrupts
+             or DMA, the relevant API's return the HAL status.
+             The end of the data processing will be indicated through the
+             dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when
+             using DMA mode.
+        (++) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks
+             will be executed respectively at the end of the Transmit or Receive process
+             The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication
+             error is detected.
+
+    (+) Blocking mode APIs are :
+        (++) HAL_SMARTCARD_Transmit()
+        (++) HAL_SMARTCARD_Receive()
+
+    (+) Non Blocking mode APIs with Interrupt are :
+        (++) HAL_SMARTCARD_Transmit_IT()
+        (++) HAL_SMARTCARD_Receive_IT()
+        (++) HAL_SMARTCARD_IRQHandler()
+
+    (+) Non Blocking mode functions with DMA are :
+        (++) HAL_SMARTCARD_Transmit_DMA()
+        (++) HAL_SMARTCARD_Receive_DMA()
+
+    (+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
+        (++) HAL_SMARTCARD_TxCpltCallback()
+        (++) HAL_SMARTCARD_RxCpltCallback()
+        (++) HAL_SMARTCARD_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_SMARTCARD_Abort()
+        (+) HAL_SMARTCARD_AbortTransmit()
+        (+) HAL_SMARTCARD_AbortReceive()
+        (+) HAL_SMARTCARD_Abort_IT()
+        (+) HAL_SMARTCARD_AbortTransmit_IT()
+        (+) HAL_SMARTCARD_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_SMARTCARD_AbortCpltCallback()
+        (+) HAL_SMARTCARD_AbortTransmitCpltCallback()
+        (+) HAL_SMARTCARD_AbortReceiveCpltCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is 
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+           and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Frame Error in Interrupt mode tranmission, Overrun Error in Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_SMARTCARD_ErrorCallback() user callback is executed.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Send an amount of data in blocking mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @param  Timeout  Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+
+  /* Check that a Tx process is not already ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+    /* Disable the Peripheral first to update mode for TX master */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Disable Rx, enable Tx */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+    
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    
+    /* Init tickstart for timeout managment */ 
+    tickstart = HAL_GetTick();
+    
+    hsmartcard->TxXferSize = Size;
+    hsmartcard->TxXferCount = Size;
+
+    while(hsmartcard->TxXferCount > 0)
+    {
+      hsmartcard->TxXferCount--;
+      if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      hsmartcard->Instance->TDR = (*pData++ & (uint8_t)0xFF);
+    }
+    if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+    /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
+    if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+    {
+      /* Disable the Peripheral first to update modes */
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+      /* Enable the Peripheral */
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+    }
+    
+    /* At end of Tx process, restore hsmartcard->gState to Ready */
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in blocking mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @param  Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint32_t tickstart = 0U;
+
+  /* Check that a Rx process is not already ongoing */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
+
+    /* Init tickstart for timeout managment*/
+    tickstart = HAL_GetTick();
+
+    hsmartcard->RxXferSize = Size;
+    hsmartcard->RxXferCount = Size;
+
+    /* Check the remain data to be received */
+    while(hsmartcard->RxXferCount > 0)
+    {
+      hsmartcard->RxXferCount--;
+
+      if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      *pData++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
+    }
+
+    /* At end of Rx process, restore hsmartcard->RxState to Ready */
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in interrupt mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+    hsmartcard->pTxBuffPtr = pData;
+    hsmartcard->TxXferSize = Size;
+    hsmartcard->TxXferCount = Size;
+
+    /* Disable the Peripheral first to update mode for TX master */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Disable Rx, enable Tx */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+    
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    /* Enable the TX FIFO threshold interrupt (if FIFO mode is enabled) or 
+       Transmit Data Register Empty interrupt (if FIFO mode is Disabled).
+    */
+    if (READ_BIT(hsmartcard->Instance->CR1, USART_CR1_FIFOEN) != RESET)
+    {
+      SET_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+    }
+    else
+    {
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in interrupt mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
+
+    hsmartcard->pRxBuffPtr = pData;
+    hsmartcard->RxXferSize = Size;
+    hsmartcard->RxXferCount = Size;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the SMARTCARD Parity Error interupt and RX FIFO Threshold interrupt 
+       (if FIFO mode is enabled) or Data Register Not Empty interrupt 
+       (if FIFO mode is disabled).
+    */
+    if (READ_BIT(hsmartcard->Instance->CR1, USART_CR1_FIFOEN) != RESET)
+    {
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+      SET_BIT(hsmartcard->Instance->CR3, USART_CR3_RXFTIE);
+    }
+    else
+    {
+      SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Send an amount of data in DMA mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX;
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->pTxBuffPtr = pData;
+    hsmartcard->TxXferSize = Size;
+    hsmartcard->TxXferCount = Size;
+
+    /* Disable the Peripheral first to update mode for TX master */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Disable Rx, enable Tx */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    SET_BIT(hsmartcard->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST);
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE);
+    
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+
+    /* Set the SMARTCARD DMA transfer complete callback */
+    hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
+
+    /* Set the SMARTCARD error callback */
+    hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
+
+    /* Set the DMA abort callback */
+    hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the SMARTCARD transmit DMA channel */
+    HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, Size);
+
+    /* Clear the TC flag in the ICR register */
+    CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    /* Enable the UART Error Interrupt: (Frame error) */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the SMARTCARD associated USART CR3 register */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receive an amount of data in DMA mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  pData pointer to data buffer.
+  * @param  Size amount of data to be received.
+  * @note   The SMARTCARD-associated USART parity is enabled (PCE = 1),
+  *         the received data contain the parity bit (MSB position).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    if((pData == NULL) || (Size == 0))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+    hsmartcard->RxState   = HAL_SMARTCARD_STATE_BUSY_RX;
+
+    hsmartcard->pRxBuffPtr = pData;
+    hsmartcard->RxXferSize = Size;
+
+    /* Set the SMARTCARD DMA transfer complete callback */
+    hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
+
+    /* Set the SMARTCARD DMA error callback */
+    hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
+
+    /* Set the DMA abort callback */
+    hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA channel */
+    HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, Size);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+
+    /* Enable the SMARTCARD Parity Error Interrupt */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+       in the SMARTCARD associated USART CR3 register */
+    SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(hsmartcard->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsmartcard->hdmatx);
+    }
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(hsmartcard->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsmartcard->hdmarx);
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  hsmartcard->TxXferCount = 0; 
+  hsmartcard->RxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Reset Handle ErrorCode to No Error */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable TXEIE, TXFTIE and TCIE interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+
+  /* Check if a receive process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if(hsmartcard->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsmartcard->hdmatx);
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  hsmartcard->TxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+  /* Restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if(hsmartcard->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback to Null. 
+         No call back execution at end of DMA abort procedure */
+      hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+      HAL_DMA_Abort(hsmartcard->hdmarx);
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  hsmartcard->RxXferCount = 0; 
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t abortcplt = 1;
+  
+  /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if(hsmartcard->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+    {
+      hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback;
+    }
+    else
+    {
+      hsmartcard->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if(hsmartcard->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+    {
+      hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback;
+    }
+    else
+    {
+      hsmartcard->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+  
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(hsmartcard->hdmatx != NULL)
+    {
+      /* SMARTCARD Tx DMA Abort callback has already been initialised : 
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+      {
+        hsmartcard->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(hsmartcard->hdmarx != NULL)
+    {
+      /* SMARTCARD Rx DMA Abort callback has already been initialised : 
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+      {
+        hsmartcard->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1;
+      }
+      else
+      {
+        abortcplt = 0;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1)
+  {
+    /* Reset Tx and Rx transfer counters */
+    hsmartcard->TxXferCount = 0; 
+    hsmartcard->RxXferCount = 0;
+
+    /* Reset errorCode */
+    hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+    /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+    hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable TXEIE, TXFTIE and TCIE interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_TXFTIE);
+
+  /* Check if a receive process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Disable the SMARTCARD DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if(hsmartcard->hdmatx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback : 
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+      hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+      {
+        /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+        hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      hsmartcard->TxXferCount = 0; 
+
+      /* Restore hsmartcard->gState to Ready */
+      hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+      HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    hsmartcard->TxXferCount = 0; 
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+    /* Restore hsmartcard->gState to Ready */
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. 
+  *         This procedure performs following operations :
+  *           - Disable SMARTCARD Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+*/
+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* Check if a Transmit process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Disable the SMARTCARD DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+  {
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if(hsmartcard->hdmarx != NULL)
+    {
+      /* Set the SMARTCARD DMA Abort callback : 
+         will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */
+      hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+      {
+        /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+        hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      hsmartcard->RxXferCount = 0; 
+
+      /* Clear the Error flags in the ICR register */
+      __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+      /* Restore hsmartcard->RxState to Ready */
+      hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+      HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+    }
+  }
+  else
+  {
+    /* Reset Rx transfer counter */
+    hsmartcard->RxXferCount = 0; 
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+    /* Restore hsmartcard->RxState to Ready */
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+    HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle SMARTCARD interrupt requests.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t isrflags   = READ_REG(hsmartcard->Instance->ISR);
+  uint32_t cr1its     = READ_REG(hsmartcard->Instance->CR1);
+  uint32_t cr3its;
+  uint32_t errorflags;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+  if (errorflags == RESET)
+  {
+    /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+    if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      SMARTCARD_Receive_IT(hsmartcard);
+      /* Clear RXNE interrupt flag done by reading RDR in SMARTCARD_Receive_IT() */
+      return;
+    }
+  }  
+
+  /* If some errors occur */
+  cr3its = READ_REG(hsmartcard->Instance->CR3);
+  if(   (errorflags != RESET) 
+     && (    ((cr3its & USART_CR3_EIE) != RESET)
+          || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != RESET)) )
+  {
+    /* SMARTCARD parity error interrupt occurred -------------------------------------*/
+    if(((isrflags & USART_ISR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
+    }
+
+    /* SMARTCARD frame error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
+    }
+
+    /* SMARTCARD noise error interrupt occurred --------------------------------------*/
+    if(((isrflags & USART_ISR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
+    }
+
+    /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/
+    if(((isrflags & USART_ISR_ORE) != RESET) &&
+       (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET)))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
+    }
+
+    /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/
+    if(((isrflags & USART_ISR_RTOF) != RESET) && ((cr1its & USART_CR1_RTOIE) != RESET))
+    {
+      __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF);
+
+      hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO;
+    }
+
+    /* Call SMARTCARD Error Call back function if need be --------------------------*/
+    if(hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
+    {
+      /* SMARTCARD in mode Receiver ---------------------------------------------------*/
+      if(((isrflags & USART_ISR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        SMARTCARD_Receive_IT(hsmartcard);
+      }
+
+      /* If Error is to be considered as blocking :
+          - Receiver Timeout error in Reception
+          - Overrun error in Reception
+          - any error occurs in DMA mode reception
+      */
+      if (   ((hsmartcard->ErrorCode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != RESET)
+          || (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)))
+      {  
+        /* Blocking error : transfer is aborted
+           Set the SMARTCARD state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        SMARTCARD_EndRxTransfer(hsmartcard);
+
+        /* Disable the SMARTCARD DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR))
+        {
+          CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the SMARTCARD DMA Rx channel */
+          if(hsmartcard->hdmarx != NULL)
+          {
+            /* Set the SMARTCARD DMA Abort callback : 
+               will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+            hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if(HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK)
+            {
+              /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */
+              hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_SMARTCARD_ErrorCallback(hsmartcard);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_SMARTCARD_ErrorCallback(hsmartcard);
+        }
+      }
+      /* other error type to be considered as blocking :
+          - Frame error in Transmission
+      */
+      else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) && ((hsmartcard->ErrorCode & HAL_SMARTCARD_ERROR_FE) != RESET))
+      {
+        /* Blocking error : transfer is aborted
+           Set the SMARTCARD state ready to be able to start again the process,
+           Disable Tx Interrupts, and disable Tx DMA request, if ongoing */
+        SMARTCARD_EndTxTransfer(hsmartcard);
+
+        /* Disable the SMARTCARD DMA Tx request if enabled */
+        if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT))
+        {
+          CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+          /* Abort the SMARTCARD DMA Tx channel */
+          if(hsmartcard->hdmatx != NULL)
+          {
+            /* Set the SMARTCARD DMA Abort callback : 
+               will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */
+            hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError;
+
+            /* Abort DMA TX */
+            if(HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK)
+            {
+              /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */
+              hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+            HAL_SMARTCARD_ErrorCallback(hsmartcard);
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+          HAL_SMARTCARD_ErrorCallback(hsmartcard);
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on. 
+           Error is notified to user through user error callback */
+        HAL_SMARTCARD_ErrorCallback(hsmartcard);
+        hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+  /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/
+  if(((isrflags & USART_ISR_EOBF) != RESET) && ((cr1its & USART_CR1_EOBIE) != RESET))
+  {
+    hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+    __HAL_UNLOCK(hsmartcard);
+    HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+    /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information
+     * to be available during HAL_SMARTCARD_RxCpltCallback() processing */
+    __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF);
+    return;
+  }
+
+  /* SMARTCARD in mode Transmitter ------------------------------------------------*/
+  if(((isrflags & USART_ISR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+  {
+    SMARTCARD_Transmit_IT(hsmartcard);
+    return;
+  }
+
+  /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
+  if((__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) &&(__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET))
+  {
+    SMARTCARD_EndTransmit_IT(hsmartcard);
+    return;
+  }
+}
+
+/**
+  * @brief  Tx Transfer completed callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD error callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Complete callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Complete callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortTransmitCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  SMARTCARD Abort Receive Complete callback.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+__weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hsmartcard);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions
+  *  @brief   SMARTCARD State and Errors functions
+  *
+@verbatim
+  ==============================================================================
+                  ##### Peripheral State and Errors functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to return the State of SmartCard
+    handle and also return Peripheral Errors occurred during communication process
+     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state
+         of the SMARTCARD peripheral.
+     (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during
+         communication.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the SMARTCARD handle state.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval SMARTCARD handle state
+  */
+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Return SMARTCARD handle state */
+  uint32_t temp1= 0x00, temp2 = 0x00;
+  temp1 = hsmartcard->gState;
+  temp2 = hsmartcard->RxState;
+
+  return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the SMARTCARD handle error code.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval SMARTCARD handle Error Code
+*/
+uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  return hsmartcard->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions
+  * @{
+  */
+
+/**
+  * @brief Configure the SMARTCARD associated USART peripheral.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t tmpreg                          = 0x0U;
+  SMARTCARD_ClockSourceTypeDef clocksource = SMARTCARD_CLOCKSOURCE_UNDEFINED;
+  HAL_StatusTypeDef ret                    = HAL_OK;
+  PLL3_ClocksTypeDef pll3_clocks;
+  PLL4_ClocksTypeDef pll4_clocks;
+
+  /* Check the parameters */
+  assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
+  assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate));
+  assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength));
+  assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits));
+  assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity));
+  assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode));
+  assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity));
+  assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase));
+  assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit));
+  assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling));
+  assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable));
+  assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable));
+  assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount));
+  assert_param(IS_SMARTCARD_FIFO_MODE_STATE(hsmartcard->Init.FIFOMode));
+  if (hsmartcard->Init.FIFOMode == SMARTCARD_FIFOMODE_ENABLE)
+  {
+    assert_param(IS_SMARTCARD_TXFIFO_THRESHOLD(hsmartcard->Init.TXFIFOThreshold));
+    assert_param(IS_SMARTCARD_RXFIFO_THRESHOLD(hsmartcard->Init.RXFIFOThreshold));
+  }
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity).
+   * Oversampling is forced to 16 (OVER8 = 0).
+   * Configure the Parity and Mode:
+   *  set PS bit according to hsmartcard->Init.Parity value
+   *  set TE and RE bits according to hsmartcard->Init.Mode value */
+  tmpreg = (uint32_t) hsmartcard->Init.Parity | hsmartcard->Init.Mode;
+  tmpreg |= (uint32_t) hsmartcard->Init.WordLength;
+  tmpreg |= (uint32_t) hsmartcard->Init.FIFOMode;
+  MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = hsmartcard->Init.StopBits;
+  /* Synchronous mode is activated by default */
+  tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity;
+  tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit;
+  tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable;
+  MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* Configure
+   * - one-bit sampling method versus three samples' majority rule
+   *   according to hsmartcard->Init.OneBitSampling
+   * - NACK transmission in case of parity error according
+   *   to hsmartcard->Init.NACKEnable
+   * - autoretry counter according to hsmartcard->Init.AutoRetryCount 
+   * - set TXFTCFG bit according to hsmartcard->Init.TXFIFOThreshold value
+   * - set RXFTCFG bit according to hsmartcard->Init.RXFIFOThreshold value   */
+  tmpreg =  (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable;
+  tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << SMARTCARD_CR3_SCARCNT_LSB_POS);
+  tmpreg |= ((uint32_t)hsmartcard->Init.TXFIFOThreshold | (uint32_t)hsmartcard->Init.RXFIFOThreshold );
+  MODIFY_REG(hsmartcard->Instance-> CR3,USART_CR3_FIELDS, tmpreg);
+
+  /*-------------------------- USART GTPR Configuration ----------------------*/
+  tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << SMARTCARD_GTPR_GT_LSB_POS));
+  MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT|USART_GTPR_PSC), tmpreg);
+
+  /*-------------------------- USART RTOR Configuration ----------------------*/
+  tmpreg =   ((uint32_t)hsmartcard->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS);
+  if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE)
+  {
+    assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+    tmpreg |=  (uint32_t) hsmartcard->Init.TimeOutValue;
+  }
+  MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource);
+  switch (clocksource)
+  {
+    case SMARTCARD_CLOCKSOURCE_PCLK1:
+      hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK1Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_PCLK2:
+      hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK2Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_PCLK5:
+      hsmartcard->Instance->BRR = (uint16_t)((HAL_RCC_GetPCLK5Freq() + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_PLL3Q:
+      HAL_RCC_GetPLL3ClockFreq(&pll3_clocks);
+      hsmartcard->Instance->BRR = (uint16_t)((pll3_clocks.PLL3_Q_Frequency + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_PLL4Q:
+      HAL_RCC_GetPLL4ClockFreq(&pll4_clocks);
+      hsmartcard->Instance->BRR = (uint16_t)((pll4_clocks.PLL4_Q_Frequency + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_HSI:
+        hsmartcard->Instance->BRR = (uint16_t)((HSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_CSI:
+      hsmartcard->Instance->BRR = (uint16_t)((CSI_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_HSE:
+      hsmartcard->Instance->BRR = (uint16_t)((HSE_VALUE + (hsmartcard->Init.BaudRate/2)) / hsmartcard->Init.BaudRate);
+      break;
+    case SMARTCARD_CLOCKSOURCE_UNDEFINED:
+    default:
+      ret = HAL_ERROR;
+      break;
+  }
+
+  return ret;
+}
+
+
+/**
+  * @brief Configure the SMARTCARD associated USART peripheral advanced features.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check whether the set of advanced features to configure is properly set */
+  assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit));
+
+  /* if required, configure TX pin active level inversion */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert);
+  }
+
+  /* if required, configure RX pin active level inversion */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert);
+  }
+
+  /* if required, configure data inversion */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert);
+  }
+
+  /* if required, configure RX/TX pins swap */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap);
+  }
+
+  /* if required, configure RX overrun detection disabling */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+  {
+    assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable));
+    MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable);
+  }
+
+  /* if required, configure DMA disabling on reception error */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError));
+    MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError);
+  }
+
+  /* if required, configure MSB first on communication line */
+  if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
+  {
+    assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst));
+    MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst);
+  }
+
+}
+
+/**
+  * @brief Check the SMARTCARD Idle State.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  uint32_t tickstart = 0;
+
+  /* Initialize the SMARTCARD ErrorCode */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Init tickstart for timeout managment*/
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Check if the Receiver is enabled */
+  if((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if(SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK)
+    {
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the SMARTCARD states */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle SMARTCARD Communication Timeout.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param  Flag Specifies the SMARTCARD flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Tickstart Tick start value
+  * @param  Timeout Timeout duration.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick()-Tickstart) > Timeout))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+        CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+        hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+        hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hsmartcard);
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *               the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Tx process, restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *               the configuration information for the specified SMARTCARD module.
+  * @retval None
+  */
+static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* At end of Rx process, restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+}
+
+
+/**
+  * @brief  DMA SMARTCARD transmit process complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+  hsmartcard->TxXferCount = 0;
+
+  /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+  in the SMARTCARD associated USART CR3 register */
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT);
+
+  /* Enable the SMARTCARD Transmit Complete Interrupt */
+  __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+}
+
+/**
+  * @brief  DMA SMARTCARD receive process complete callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+  hsmartcard->RxXferCount = 0;
+
+  /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+  CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+
+  /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+     in the SMARTCARD associated USART CR3 register */
+  CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR);
+
+  /* At end of Rx process, restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+}
+
+/**
+  * @brief  DMA SMARTCARD communication error callback.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+
+  /* Stop SMARTCARD DMA Tx request if ongoing */
+  if (  (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+      &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) )
+  {
+    hsmartcard->TxXferCount = 0;
+    SMARTCARD_EndTxTransfer(hsmartcard);
+  }
+
+  /* Stop SMARTCARD DMA Rx request if ongoing */
+  if (  (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+      &&(HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) )
+  {
+    hsmartcard->RxXferCount = 0;
+    SMARTCARD_EndRxTransfer(hsmartcard);
+  }
+
+  hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA;
+  HAL_SMARTCARD_ErrorCallback(hsmartcard);
+}
+
+/**
+  * @brief  DMA SMARTCARD communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+  hsmartcard->RxXferCount = 0;
+  hsmartcard->TxXferCount = 0;
+
+  HAL_SMARTCARD_ErrorCallback(hsmartcard);
+}
+
+/**
+  * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
+  
+  hsmartcard->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(hsmartcard->hdmarx != NULL)
+  {
+    if(hsmartcard->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hsmartcard->TxXferCount = 0;
+  hsmartcard->RxXferCount = 0;
+
+  /* Reset errorCode */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+}
+
+
+/**
+  * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef* )(hdma->Parent);
+  
+  hsmartcard->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if(hsmartcard->hdmatx != NULL)
+  {
+    if(hsmartcard->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+  
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  hsmartcard->TxXferCount = 0;
+  hsmartcard->RxXferCount = 0;
+
+  /* Reset errorCode */
+  hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */
+  hsmartcard->gState  = HAL_SMARTCARD_STATE_READY;
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_SMARTCARD_AbortCpltCallback(hsmartcard);
+}
+
+
+/**
+  * @brief  DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to
+  *         HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = (SMARTCARD_HandleTypeDef*)(hdma->Parent);
+
+  hsmartcard->TxXferCount = 0;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF);
+
+  /* Restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard);
+}
+
+/**
+  * @brief  DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to
+  *         HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )(hdma->Parent);
+
+  hsmartcard->RxXferCount = 0;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF);
+
+  /* Restore hsmartcard->RxState to Ready */
+  hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+  /* Call user Abort complete callback */
+  HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard);
+}
+
+/**
+  * @brief Send an amount of data in non-blocking mode.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMARTCARD module.
+  *         Function called under interruption only, once
+  *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check that a Tx process is ongoing */
+  if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX)
+  {
+    if(hsmartcard->TxXferCount == 0)
+    {
+      /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE);
+
+      /* Enable the SMARTCARD Transmit Complete Interrupt */
+      __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+
+      return HAL_OK;
+    }
+    else
+    {
+      hsmartcard->Instance->TDR = (*hsmartcard->pTxBuffPtr++ & (uint8_t)0xFF);
+      hsmartcard->TxXferCount--;
+
+      return HAL_OK;
+    }
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Wrap up transmission in non-blocking mode.
+  * @param  hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Disable the SMARTCARD Transmit Complete Interrupt */
+  __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication);
+
+  /* Check if a receive process is ongoing or not. If not disable ERR IT */
+  if(hsmartcard->RxState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Disable the SMARTCARD Error Interrupt: (Frame error) */
+    CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+  }
+
+  /* Re-enable Rx at end of transmission if initial mode is Rx/Tx */
+  if(hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX)
+  {
+    /* Disable the Peripheral first to update modes */
+    CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE);
+    /* Enable the Peripheral */
+    SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE);
+  }
+  
+  /* Tx process is ended, restore hsmartcard->gState to Ready */
+  hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+  HAL_SMARTCARD_TxCpltCallback(hsmartcard);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Receive an amount of data in non-blocking mode.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                the configuration information for the specified SMARTCARD module.
+  *         Function called under interruption only, once
+  *         interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+  /* Check that a Rx process is ongoing */
+  if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX)
+  {
+    *hsmartcard->pRxBuffPtr++ = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF);
+
+    if(--hsmartcard->RxXferCount == 0)
+    {
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE);
+
+      /* Check if a transmit process is ongoing or not. If not disable ERR IT */
+      if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+      {
+        /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
+        CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE);
+      }
+
+      /* Disable the SMARTCARD Parity Error Interrupt */
+      CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE);
+
+      hsmartcard->RxState = HAL_SMARTCARD_STATE_READY;
+
+      HAL_SMARTCARD_RxCpltCallback(hsmartcard);
+
+      return HAL_OK;
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST);
+
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_smartcard_ex.c

@@ -0,0 +1,192 @@
+/**
+  ******************************************************************************
+  * @file    stm32mp1xx_hal_smartcard_ex.c
+  * @author  MCD Application Team
+  * @version $VERSION$
+  * @date    $DATE$
+  * @brief   SMARTCARD HAL module driver.
+  *          This file provides extended firmware functions to manage the following
+  *          functionalities of the SmartCard.
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  *
+  @verbatim
+  =============================================================================
+               ##### SMARTCARD peripheral extended features  #####
+  =============================================================================
+  [..]
+  The Extended SMARTCARD HAL driver can be used as follows:
+
+    (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
+        then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut,
+        auto-retry counter,...) in the hsmartcard AdvancedInit structure.
+
+
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32mp1xx_hal.h"
+
+/** @addtogroup STM32MP1xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SMARTCARDEx SMARTCARDEx
+  * @brief SMARTCARD Extended HAL module driver
+  * @{
+  */
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SMARTCARDEx_Exported_Functions  SMARTCARD Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions
+  * @brief    Extended control functions
+  *
+@verbatim
+  ===============================================================================
+                      ##### Peripheral Control functions #####
+  ===============================================================================
+  [..]
+  This subsection provides a set of functions allowing to initialize the SMARTCARD.
+     (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
+     (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
+     (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
+     (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Update on the fly the SMARTCARD block length in RTOR register.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param BlockLength: SMARTCARD block length (8-bit long at most)
+  * @retval None
+  */
+void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength)
+{
+  MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
+}
+
+/**
+  * @brief Update on the fly the receiver timeout value in RTOR register.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout
+  *                     value must be less or equal to 0x0FFFFFFFF.
+  * @retval None
+  */
+void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue)
+{
+  assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue));
+  MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
+}
+
+/**
+  * @brief Enable the SMARTCARD receiver timeout feature.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+    /* Set the USART RTOEN bit */
+    SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Disable the SMARTCARD receiver timeout feature.
+  * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains
+  *                    the configuration information for the specified SMARTCARD module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard)
+{
+
+  if(hsmartcard->gState == HAL_SMARTCARD_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hsmartcard);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY;
+
+    /* Clear the USART RTOEN bit */
+    CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN);
+
+    hsmartcard->gState = HAL_SMARTCARD_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hsmartcard);
+    
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

bsp/stm32/libraries/STM32MPxx_HAL/STM32MP1xx_HAL_Driver/Src/stm32mp1xx_ll_adc.c

@@ -80,7 +80,7 @@
 /* Check of parameters for configuration of ADC hierarchical scope:           */
 /* common to several ADC instances.                                           */
 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \
-  (   ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                             \
+  (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                                \
    || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
    || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
    || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
@@ -100,7 +100,7 @@
 /* Check of parameters for configuration of ADC hierarchical scope:           */
 /* ADC instance.                                                              */
 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
-  (   ((__RESOLUTION__) == LL_ADC_RESOLUTION_16B)                              \
+  (((__RESOLUTION__) == LL_ADC_RESOLUTION_16B)                                 \
    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_14B)                              \
    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                              \
    || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
@@ -108,7 +108,7 @@
   )
 
 #define IS_LL_ADC_LEFT_BIT_SHIFT(__LEFT_BIT_SHIFT__)                           \
-  (   ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE)                     \
+  (((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_NONE)                        \
    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_1)                        \
    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_2)                        \
    || ((__LEFT_BIT_SHIFT__) == LL_ADC_LEFT_BIT_SHIFT_3)                        \
@@ -127,14 +127,14 @@
   )
 
 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__)                                     \
-  (   ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                 \
+  (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                    \
    || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
   )
 
 /* Check of parameters for configuration of ADC hierarchical scope:           */
 /* ADC group regular                                                          */
 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__)                         \
-  (   ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                      \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
    || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
@@ -157,24 +157,24 @@
   )
 
 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
-  (   ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                    \
+  (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                       \
    || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
   )
 
 #define IS_LL_ADC_REG_DATA_TRANSFER_MODE(__REG_DATA_TRANSFER_MODE__)           \
-  (   ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER)                 \
+  (((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DR_TRANSFER)                    \
    || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)        \
    || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)      \
    || ((__REG_DATA_TRANSFER_MODE__) == LL_ADC_REG_DFSDM_TRANSFER)              \
   )
 
 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)             \
-  (   ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)           \
+  (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)              \
    || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
   )
 
 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
-  (   ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)               \
+  (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)                  \
    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
    || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
@@ -193,7 +193,7 @@
   )
 
 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
-  (   ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)           \
+  (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)              \
    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
    || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
@@ -207,7 +207,7 @@
 /* Check of parameters for configuration of ADC hierarchical scope:           */
 /* ADC group injected                                                         */
 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__)                         \
-  (   ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                      \
+  (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
    || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
@@ -230,25 +230,25 @@
   )
 
 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)                     \
-  (   ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                  \
+  (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                     \
    || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
    || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
   )
 
 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)                             \
-  (   ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                     \
+  (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                        \
    || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
   )
 
 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)                 \
-  (   ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)               \
+  (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)                  \
    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
    || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
   )
 
 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)          \
-  (   ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)           \
+  (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)              \
    || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
   )
 
@@ -256,7 +256,7 @@
 /* Check of parameters for configuration of ADC hierarchical scope:           */
 /* multimode.                                                                 */
 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)                                   \
-  (   ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                           \
+  (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                              \
    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \
    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL)                       \
    || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \
@@ -267,12 +267,12 @@
   )
 
 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)                   \
-  (   ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC)              \
+  (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC)                 \
    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_32_10B)            \
    || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_RES_8B)                \
   )
 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)                    \
-  (   ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5)          \
+  (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5)             \
    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5)         \
    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5)         \
    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5)         \
@@ -283,10 +283,10 @@
    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS) \
    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5)         \
    || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5_14_BITS) \
-   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5)           \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES_5)         \
   )
 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)                   \
-  (   ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                        \
+  (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                           \
    || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \
    || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \
   )
@@ -313,7 +313,7 @@
   *         the same ADC common instance to their default reset values.
   * @note   This function is performing a hard reset, using high level
   *         clock source RCC ADC reset.
-  *         Caution: On this STM32 serie, if several ADC instances are available
+  *         Caution: On this STM32 series, if several ADC instances are available
   *         on the selected device, RCC ADC reset will reset
   *         all ADC instances belonging to the common ADC instance.
   *         To de-initialize only 1 ADC instance, use
@@ -372,7 +372,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni
 
   /* Note: Hardware constraint (refer to description of functions             */
   /*       "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"):               */
-  /*       On this STM32 serie, setting of these features is conditioned to   */
+  /*       On this STM32 series, setting of these features is conditioned to  */
   /*       ADC state:                                                         */
   /*       All ADC instances of the ADC common group must be disabled.        */
   if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
@@ -459,7 +459,7 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
   *         is in an unknown state.
   *         In this case, perform a hard reset using high level
   *         clock source RCC ADC reset.
-  *         Caution: On this STM32 serie, if several ADC instances are available
+  *         Caution: On this STM32 series, if several ADC instances are available
   *         on the selected device, RCC ADC reset will reset
   *         all ADC instances belonging to the common ADC instance.
   *         Refer to function @ref LL_ADC_CommonDeInit().
@@ -705,10 +705,10 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
     /* ADC instance is in an unknown state */
     /* Need to performing a hard reset of ADC instance, using high level      */
     /* clock source RCC ADC reset.                                            */
-    /* Caution: On this STM32 serie, if several ADC instances are available   */
+    /* Caution: On this STM32 series, if several ADC instances are available  */
     /*          on the selected device, RCC ADC reset will reset              */
     /*          all ADC instances belonging to the common ADC instance.       */
-    /* Caution: On this STM32 serie, if several ADC instances are available   */
+    /* Caution: On this STM32 series, if several ADC instances are available  */
     /*          on the selected device, RCC ADC reset will reset              */
     /*          all ADC instances belonging to the common ADC instance.       */
     status = ERROR;
@@ -785,6 +785,7 @@ ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
     /* Initialization error: ADC instance is not disabled. */
     status = ERROR;
   }
+
   return status;
 }
 
@@ -847,6 +848,11 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
   if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
   {
     assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
+
+    /* ADC group regular continuous mode and discontinuous mode                 */
+    /* can not be enabled simultenaeously                                       */
+    assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+                 || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
   }
   assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
   assert_param(IS_LL_ADC_REG_DATA_TRANSFER_MODE(ADC_REG_InitStruct->DataTransferMode));
@@ -865,7 +871,7 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I
     /*    - Set ADC group regular conversion data transfer: no transfer or    */
     /*      transfer by DMA, and DMA requests mode                            */
     /*    - Set ADC group regular overrun behavior                            */
-    /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by     */
+    /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by    */
     /*       setting of trigger source to SW start.                           */
     if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
     {
@@ -925,7 +931,7 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
 {
   /* Set ADC_REG_InitStruct fields to default values */
   /* Set fields of ADC group regular */
-  /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by       */
+  /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by      */
   /*       setting of trigger source to SW start.                             */
   ADC_REG_InitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
   ADC_REG_InitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
@@ -961,6 +967,12 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
   *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
   *          - Set ADC channel sampling time
   *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @note   Caution if feature ADC group injected contexts queue is enabled
+  *         (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
+  *         using successively several times this function will appear as
+  *         having no effect.
+  *         To set several features of ADC group injected, use
+  *         function @ref LL_ADC_INJ_ConfigQueueContext().
   * @param  ADCx ADC instance
   * @param  ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
   * @retval An ErrorStatus enumeration value:
@@ -992,7 +1004,7 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I
     /*    - Set ADC group injected sequencer discontinuous mode               */
     /*    - Set ADC group injected conversion trigger: independent or         */
     /*      from ADC group regular                                            */
-    /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by     */
+    /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by    */
     /*       setting of trigger source to SW start.                           */
     if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
     {