usb_dc_fsdev.c 18 KB

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  1. /*
  2. * Copyright (c) 2022, sakumisu
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "usbd_core.h"
  7. #if (CONFIG_USB_DBG_LEVEL >= USB_DBG_LOG)
  8. #error "fsdev cannot enable USB_DBG_LOG"
  9. #endif
  10. #ifndef CONFIG_USBDEV_FSDEV_PMA_ACCESS
  11. #error "please define CONFIG_USBDEV_FSDEV_PMA_ACCESS in usb_config.h"
  12. #endif
  13. #define PMA_ACCESS CONFIG_USBDEV_FSDEV_PMA_ACCESS
  14. #include "usb_fsdev_reg.h"
  15. #ifndef CONFIG_USB_FSDEV_RAM_SIZE
  16. #define CONFIG_USB_FSDEV_RAM_SIZE 512
  17. #endif
  18. #ifndef CONFIG_USBDEV_EP_NUM
  19. #define CONFIG_USBDEV_EP_NUM 8
  20. #endif
  21. #define USB ((USB_TypeDef *)g_usbdev_bus[0].reg_base)
  22. #define USB_BTABLE_SIZE (8 * CONFIG_USBDEV_EP_NUM)
  23. static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
  24. static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
  25. /* Endpoint state */
  26. struct fsdev_ep_state {
  27. uint16_t ep_mps; /* Endpoint max packet size */
  28. uint8_t ep_type; /* Endpoint type */
  29. uint8_t ep_stalled; /* Endpoint stall flag */
  30. uint8_t ep_enable; /* Endpoint enable */
  31. uint16_t ep_pma_buf_len; /* Previously allocated buffer size */
  32. uint16_t ep_pma_addr; /* ep pmd allocated addr */
  33. uint8_t *xfer_buf;
  34. uint32_t xfer_len;
  35. uint32_t actual_xfer_len;
  36. };
  37. /* Driver state */
  38. struct fsdev_udc {
  39. struct usb_setup_packet setup;
  40. volatile uint8_t dev_addr; /*!< USB Address */
  41. volatile uint32_t pma_offset; /*!< pma offset */
  42. struct fsdev_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/
  43. struct fsdev_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */
  44. } g_fsdev_udc;
  45. __WEAK void usb_dc_low_level_init(void)
  46. {
  47. }
  48. __WEAK void usb_dc_low_level_deinit(void)
  49. {
  50. }
  51. int usb_dc_init(uint8_t busid)
  52. {
  53. usb_dc_low_level_init();
  54. /* Init Device */
  55. /* CNTR_FRES = 1 */
  56. USB->CNTR = (uint16_t)USB_CNTR_FRES;
  57. /* CNTR_FRES = 0 */
  58. USB->CNTR = 0U;
  59. /* Clear pending interrupts */
  60. USB->ISTR = 0U;
  61. /*Set Btable Address*/
  62. USB->BTABLE = BTABLE_ADDRESS;
  63. uint32_t winterruptmask;
  64. /* Set winterruptmask variable */
  65. winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
  66. USB_CNTR_SUSPM | USB_CNTR_ERRM |
  67. USB_CNTR_ESOFM | USB_CNTR_RESETM;
  68. #ifdef CONFIG_USBDEV_SOF_ENABLE
  69. winterruptmask |= USB_CNTR_SOFM;
  70. #endif
  71. /* Set interrupt mask */
  72. USB->CNTR = (uint16_t)winterruptmask;
  73. /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
  74. USB->BCDR |= (uint16_t)USB_BCDR_DPPU;
  75. return 0;
  76. }
  77. int usb_dc_deinit(uint8_t busid)
  78. {
  79. /* disable all interrupts and force USB reset */
  80. USB->CNTR = (uint16_t)USB_CNTR_FRES;
  81. /* clear interrupt status register */
  82. USB->ISTR = 0U;
  83. /* switch-off device */
  84. USB->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
  85. usb_dc_low_level_deinit();
  86. return 0;
  87. }
  88. int usbd_set_address(uint8_t busid, const uint8_t addr)
  89. {
  90. if (addr == 0U) {
  91. /* set device address and enable function */
  92. USB->DADDR = (uint16_t)USB_DADDR_EF;
  93. }
  94. g_fsdev_udc.dev_addr = addr;
  95. return 0;
  96. }
  97. int usbd_set_remote_wakeup(uint8_t busid)
  98. {
  99. return -1;
  100. }
  101. uint8_t usbd_get_port_speed(uint8_t busid)
  102. {
  103. return USB_SPEED_FULL;
  104. }
  105. int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep)
  106. {
  107. uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress);
  108. USB_ASSERT_MSG(ep_idx < CONFIG_USBDEV_EP_NUM, "Ep addr %02x overflow", ep->bEndpointAddress);
  109. USB_ASSERT_MSG(USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS, "iso endpoint not support in fsdev");
  110. uint16_t wEpRegVal;
  111. /* initialize Endpoint */
  112. switch (USB_GET_ENDPOINT_TYPE(ep->bmAttributes)) {
  113. case USB_ENDPOINT_TYPE_CONTROL:
  114. wEpRegVal = USB_EP_CONTROL;
  115. break;
  116. case USB_ENDPOINT_TYPE_BULK:
  117. wEpRegVal = USB_EP_BULK;
  118. break;
  119. case USB_ENDPOINT_TYPE_INTERRUPT:
  120. wEpRegVal = USB_EP_INTERRUPT;
  121. break;
  122. case USB_ENDPOINT_TYPE_ISOCHRONOUS:
  123. wEpRegVal = USB_EP_ISOCHRONOUS;
  124. break;
  125. default:
  126. return -1;
  127. }
  128. PCD_SET_EPTYPE(USB, ep_idx, wEpRegVal);
  129. PCD_SET_EP_ADDRESS(USB, ep_idx, ep_idx);
  130. if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) {
  131. g_fsdev_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  132. g_fsdev_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
  133. g_fsdev_udc.out_ep[ep_idx].ep_enable = true;
  134. if (g_fsdev_udc.out_ep[ep_idx].ep_mps > g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len) {
  135. USB_ASSERT_MSG((g_fsdev_udc.pma_offset + g_fsdev_udc.out_ep[ep_idx].ep_mps) <= CONFIG_USB_FSDEV_RAM_SIZE,
  136. "Ep pma %02x overflow", ep->bEndpointAddress);
  137. g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  138. g_fsdev_udc.out_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset;
  139. /*Set the endpoint Receive buffer address */
  140. PCD_SET_EP_RX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset);
  141. g_fsdev_udc.pma_offset += USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  142. }
  143. /*Set the endpoint Receive buffer counter*/
  144. PCD_SET_EP_RX_CNT(USB, ep_idx, USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize));
  145. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  146. } else {
  147. g_fsdev_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  148. g_fsdev_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
  149. g_fsdev_udc.in_ep[ep_idx].ep_enable = true;
  150. if (g_fsdev_udc.in_ep[ep_idx].ep_mps > g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len) {
  151. USB_ASSERT_MSG((g_fsdev_udc.pma_offset + g_fsdev_udc.in_ep[ep_idx].ep_mps) <= CONFIG_USB_FSDEV_RAM_SIZE,
  152. "Ep pma %02x overflow", ep->bEndpointAddress);
  153. g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  154. g_fsdev_udc.in_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset;
  155. /*Set the endpoint Transmit buffer address */
  156. PCD_SET_EP_TX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset);
  157. g_fsdev_udc.pma_offset += USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  158. }
  159. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  160. if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
  161. /* Configure NAK status for the Endpoint */
  162. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK);
  163. } else {
  164. /* Configure TX Endpoint to disabled state */
  165. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS);
  166. }
  167. }
  168. return 0;
  169. }
  170. int usbd_ep_close(uint8_t busid, const uint8_t ep)
  171. {
  172. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  173. if (USB_EP_DIR_IS_OUT(ep)) {
  174. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  175. /* Configure DISABLE status for the Endpoint*/
  176. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_DIS);
  177. } else {
  178. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  179. /* Configure DISABLE status for the Endpoint*/
  180. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS);
  181. }
  182. return 0;
  183. }
  184. int usbd_ep_set_stall(uint8_t busid, const uint8_t ep)
  185. {
  186. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  187. if (USB_EP_DIR_IS_OUT(ep)) {
  188. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_STALL);
  189. } else {
  190. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_STALL);
  191. }
  192. return 0;
  193. }
  194. int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep)
  195. {
  196. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  197. if (USB_EP_DIR_IS_OUT(ep)) {
  198. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  199. /* Configure VALID status for the Endpoint */
  200. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  201. } else {
  202. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  203. if (g_fsdev_udc.in_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
  204. /* Configure NAK status for the Endpoint */
  205. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK);
  206. }
  207. }
  208. return 0;
  209. }
  210. int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled)
  211. {
  212. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  213. if (USB_EP_DIR_IS_OUT(ep)) {
  214. if (PCD_GET_EP_RX_STATUS(USB, ep_idx) & USB_EP_RX_STALL) {
  215. *stalled = 1;
  216. } else {
  217. *stalled = 0;
  218. }
  219. } else {
  220. if (PCD_GET_EP_TX_STATUS(USB, ep_idx) & USB_EP_TX_STALL) {
  221. *stalled = 1;
  222. } else {
  223. *stalled = 0;
  224. }
  225. }
  226. return 0;
  227. }
  228. int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len)
  229. {
  230. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  231. if (!data && data_len) {
  232. return -1;
  233. }
  234. if (!g_fsdev_udc.in_ep[ep_idx].ep_enable) {
  235. return -2;
  236. }
  237. g_fsdev_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data;
  238. g_fsdev_udc.in_ep[ep_idx].xfer_len = data_len;
  239. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len = 0;
  240. data_len = MIN(data_len, g_fsdev_udc.in_ep[ep_idx].ep_mps);
  241. fsdev_write_pma(USB, (uint8_t *)data, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)data_len);
  242. PCD_SET_EP_TX_CNT(USB, ep_idx, (uint16_t)data_len);
  243. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID);
  244. return 0;
  245. }
  246. int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len)
  247. {
  248. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  249. if (!data && data_len) {
  250. return -1;
  251. }
  252. if (!g_fsdev_udc.out_ep[ep_idx].ep_enable) {
  253. return -2;
  254. }
  255. g_fsdev_udc.out_ep[ep_idx].xfer_buf = data;
  256. g_fsdev_udc.out_ep[ep_idx].xfer_len = data_len;
  257. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len = 0;
  258. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  259. return 0;
  260. }
  261. void USBD_IRQHandler(uint8_t busid)
  262. {
  263. uint16_t wIstr, wEPVal;
  264. uint8_t ep_idx;
  265. uint8_t read_count;
  266. uint16_t write_count;
  267. uint16_t store_ep[8];
  268. wIstr = USB->ISTR;
  269. if (wIstr & USB_ISTR_CTR) {
  270. while ((USB->ISTR & USB_ISTR_CTR) != 0U) {
  271. wIstr = USB->ISTR;
  272. /* extract highest priority endpoint number */
  273. ep_idx = (uint8_t)(wIstr & USB_ISTR_EP_ID);
  274. if (ep_idx == 0U) {
  275. if ((wIstr & USB_ISTR_DIR) == 0U) {
  276. PCD_CLEAR_TX_EP_CTR(USB, ep_idx);
  277. write_count = PCD_GET_EP_TX_CNT(USB, ep_idx);
  278. g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count;
  279. g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count;
  280. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count;
  281. usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len);
  282. if (g_fsdev_udc.setup.wLength == 0) {
  283. /* In status, start reading setup */
  284. usbd_ep_start_read(0, 0x00, NULL, 0);
  285. } else if (g_fsdev_udc.setup.wLength && ((g_fsdev_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) {
  286. /* In status, start reading setup */
  287. usbd_ep_start_read(0, 0x00, NULL, 0);
  288. }
  289. if ((g_fsdev_udc.dev_addr > 0U) && (write_count == 0U)) {
  290. USB->DADDR = ((uint16_t)g_fsdev_udc.dev_addr | USB_DADDR_EF);
  291. g_fsdev_udc.dev_addr = 0U;
  292. }
  293. } else {
  294. wEPVal = PCD_GET_ENDPOINT(USB, ep_idx);
  295. if ((wEPVal & USB_EP_SETUP) != 0U) {
  296. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  297. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  298. fsdev_read_pma(USB, (uint8_t *)&g_fsdev_udc.setup, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  299. usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_fsdev_udc.setup);
  300. } else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
  301. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  302. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  303. fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  304. g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count;
  305. g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count;
  306. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count;
  307. usbd_event_ep_out_complete_handler(0, ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len);
  308. if (read_count == 0) {
  309. /* Out status, start reading setup */
  310. usbd_ep_start_read(0, 0x00, NULL, 0);
  311. }
  312. }
  313. }
  314. } else {
  315. wEPVal = PCD_GET_ENDPOINT(USB, ep_idx);
  316. if ((wEPVal & USB_EP_CTR_RX) != 0U) {
  317. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  318. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  319. fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  320. g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count;
  321. g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count;
  322. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count;
  323. if ((read_count < g_fsdev_udc.out_ep[ep_idx].ep_mps) ||
  324. (g_fsdev_udc.out_ep[ep_idx].xfer_len == 0)) {
  325. usbd_event_ep_out_complete_handler(0, ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len);
  326. } else {
  327. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  328. }
  329. }
  330. if ((wEPVal & USB_EP_CTR_TX) != 0U) {
  331. PCD_CLEAR_TX_EP_CTR(USB, ep_idx);
  332. write_count = PCD_GET_EP_TX_CNT(USB, ep_idx);
  333. g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count;
  334. g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count;
  335. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count;
  336. if (g_fsdev_udc.in_ep[ep_idx].xfer_len == 0) {
  337. usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len);
  338. } else {
  339. write_count = MIN(g_fsdev_udc.in_ep[ep_idx].xfer_len, g_fsdev_udc.in_ep[ep_idx].ep_mps);
  340. fsdev_write_pma(USB, g_fsdev_udc.in_ep[ep_idx].xfer_buf, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)write_count);
  341. PCD_SET_EP_TX_CNT(USB, ep_idx, write_count);
  342. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID);
  343. }
  344. }
  345. }
  346. }
  347. }
  348. if (wIstr & USB_ISTR_RESET) {
  349. memset(&g_fsdev_udc, 0, sizeof(struct fsdev_udc));
  350. g_fsdev_udc.pma_offset = USB_BTABLE_SIZE;
  351. usbd_event_reset_handler(0);
  352. /* start reading setup packet */
  353. PCD_SET_EP_RX_STATUS(USB, 0, USB_EP_RX_VALID);
  354. USB->ISTR &= (uint16_t)(~USB_ISTR_RESET);
  355. }
  356. if (wIstr & USB_ISTR_PMAOVR) {
  357. USB->ISTR &= (uint16_t)(~USB_ISTR_PMAOVR);
  358. }
  359. if (wIstr & USB_ISTR_ERR) {
  360. USB->ISTR &= (uint16_t)(~USB_ISTR_ERR);
  361. }
  362. if (wIstr & USB_ISTR_WKUP) {
  363. USB->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
  364. USB->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
  365. USB->ISTR &= (uint16_t)(~USB_ISTR_WKUP);
  366. }
  367. if (wIstr & USB_ISTR_SUSP) {
  368. /* WA: To Clear Wakeup flag if raised with suspend signal */
  369. /* Store Endpoint register */
  370. for (uint8_t i = 0U; i < 8U; i++) {
  371. store_ep[i] = PCD_GET_ENDPOINT(USB, i);
  372. }
  373. /* FORCE RESET */
  374. USB->CNTR |= (uint16_t)(USB_CNTR_FRES);
  375. /* CLEAR RESET */
  376. USB->CNTR &= (uint16_t)(~USB_CNTR_FRES);
  377. /* wait for reset flag in ISTR */
  378. while ((USB->ISTR & USB_ISTR_RESET) == 0U) {
  379. }
  380. /* Clear Reset Flag */
  381. USB->ISTR &= (uint16_t)(~USB_ISTR_RESET);
  382. /* Restore Registre */
  383. for (uint8_t i = 0U; i < 8U; i++) {
  384. PCD_SET_ENDPOINT(USB, i, store_ep[i]);
  385. }
  386. /* Force low-power mode in the macrocell */
  387. USB->CNTR |= (uint16_t)USB_CNTR_FSUSP;
  388. /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
  389. USB->ISTR &= (uint16_t)(~USB_ISTR_SUSP);
  390. USB->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
  391. }
  392. #ifdef CONFIG_USBDEV_SOF_ENABLE
  393. if (wIstr & USB_ISTR_SOF) {
  394. USB->ISTR &= (uint16_t)(~USB_ISTR_SOF);
  395. usbd_event_sof_handler(0);
  396. }
  397. #endif
  398. if (wIstr & USB_ISTR_ESOF) {
  399. USB->ISTR &= (uint16_t)(~USB_ISTR_ESOF);
  400. }
  401. }
  402. static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
  403. {
  404. uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
  405. uint32_t BaseAddr = (uint32_t)USBx;
  406. uint32_t i, temp1, temp2;
  407. __IO uint16_t *pdwVal;
  408. uint8_t *pBuf = pbUsrBuf;
  409. pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
  410. for (i = n; i != 0U; i--) {
  411. temp1 = *pBuf;
  412. pBuf++;
  413. temp2 = temp1 | ((uint16_t)((uint16_t)*pBuf << 8));
  414. *pdwVal = (uint16_t)temp2;
  415. pdwVal++;
  416. #if PMA_ACCESS > 1U
  417. pdwVal++;
  418. #endif
  419. pBuf++;
  420. }
  421. }
  422. /**
  423. * @brief Copy data from packet memory area (PMA) to user memory buffer
  424. * @param USBx USB peripheral instance register address.
  425. * @param pbUsrBuf pointer to user memory area.
  426. * @param wPMABufAddr address into PMA.
  427. * @param wNBytes no. of bytes to be copied.
  428. * @retval None
  429. */
  430. static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
  431. {
  432. uint32_t n = (uint32_t)wNBytes >> 1;
  433. uint32_t BaseAddr = (uint32_t)USBx;
  434. uint32_t i, temp;
  435. __IO uint16_t *pdwVal;
  436. uint8_t *pBuf = pbUsrBuf;
  437. pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
  438. for (i = n; i != 0U; i--) {
  439. temp = *(__IO uint16_t *)pdwVal;
  440. pdwVal++;
  441. *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
  442. pBuf++;
  443. *pBuf = (uint8_t)((temp >> 8) & 0xFFU);
  444. pBuf++;
  445. #if PMA_ACCESS > 1U
  446. pdwVal++;
  447. #endif
  448. }
  449. if ((wNBytes % 2U) != 0U) {
  450. temp = *pdwVal;
  451. *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
  452. }
  453. }