clock_timer.c 12 KB

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  1. /*
  2. * Copyright (c) 2006-2024 RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2015-08-31 heyuanjie87 first version
  9. */
  10. #include <rtdevice.h>
  11. #include <rthw.h>
  12. #include <drivers/clock_time.h>
  13. #define DBG_TAG "clock_timer"
  14. #define DBG_LVL DBG_INFO
  15. #include <rtdbg.h>
  16. #ifdef RT_USING_DM
  17. void (*rt_clock_timer_us_delay)(rt_uint32_t us) = RT_NULL;
  18. rt_weak void rt_hw_us_delay(rt_uint32_t us)
  19. {
  20. if (rt_clock_timer_us_delay)
  21. {
  22. rt_clock_timer_us_delay(us);
  23. }
  24. else
  25. {
  26. LOG_E("Implemented at least in the libcpu");
  27. RT_ASSERT(0);
  28. }
  29. }
  30. #endif /* RT_USING_DM */
  31. static struct rt_clock_time_device _clock_timer_clock_dev;
  32. static rt_clock_timer_t *_clock_timer_owner = RT_NULL;
  33. static rt_uint64_t _clock_timer_clock_get_freq(struct rt_clock_time_device *dev)
  34. {
  35. RT_UNUSED(dev);
  36. if (_clock_timer_owner == RT_NULL)
  37. {
  38. return 0;
  39. }
  40. return (rt_uint64_t)_clock_timer_owner->freq;
  41. }
  42. static rt_uint64_t _clock_timer_clock_get_counter(struct rt_clock_time_device *dev)
  43. {
  44. RT_UNUSED(dev);
  45. if (_clock_timer_owner == RT_NULL ||
  46. _clock_timer_owner->ops == RT_NULL ||
  47. _clock_timer_owner->ops->count_get == RT_NULL)
  48. {
  49. return 0;
  50. }
  51. return (rt_uint64_t)_clock_timer_owner->ops->count_get(_clock_timer_owner);
  52. }
  53. static rt_err_t _clock_timer_clock_set_timeout(struct rt_clock_time_device *dev, rt_uint64_t delta)
  54. {
  55. RT_UNUSED(dev);
  56. if (_clock_timer_owner == RT_NULL ||
  57. _clock_timer_owner->ops == RT_NULL ||
  58. _clock_timer_owner->ops->start == RT_NULL)
  59. {
  60. return -RT_ENOSYS;
  61. }
  62. if (delta == 0)
  63. {
  64. if (_clock_timer_owner->ops->stop)
  65. {
  66. _clock_timer_owner->ops->stop(_clock_timer_owner);
  67. }
  68. return RT_EOK;
  69. }
  70. if (_clock_timer_owner->ops->stop)
  71. {
  72. _clock_timer_owner->ops->stop(_clock_timer_owner);
  73. }
  74. _clock_timer_owner->mode = CLOCK_TIMER_MODE_ONESHOT;
  75. if (delta > (rt_uint64_t)RT_UINT32_MAX)
  76. {
  77. delta = RT_UINT32_MAX;
  78. }
  79. return _clock_timer_owner->ops->start(_clock_timer_owner, (rt_uint32_t)delta, CLOCK_TIMER_MODE_ONESHOT);
  80. }
  81. static const struct rt_clock_time_ops _clock_timer_clock_ops =
  82. {
  83. _clock_timer_clock_get_freq,
  84. _clock_timer_clock_get_counter,
  85. _clock_timer_clock_set_timeout,
  86. };
  87. rt_inline rt_uint32_t timeout_calc(rt_clock_timer_t *timer, rt_clock_timerval_t *tv)
  88. {
  89. float overflow;
  90. float timeout;
  91. rt_uint32_t counter;
  92. int i, index = 0;
  93. float tv_sec;
  94. float devi_min = 1;
  95. float devi;
  96. /* changed to second */
  97. overflow = timer->info->maxcnt/(float)timer->freq;
  98. tv_sec = tv->sec + tv->usec/(float)1000000;
  99. if (tv_sec < (1/(float)timer->freq))
  100. {
  101. /* little timeout */
  102. i = 0;
  103. timeout = 1/(float)timer->freq;
  104. }
  105. else
  106. {
  107. for (i = 1; i > 0; i ++)
  108. {
  109. timeout = tv_sec/i;
  110. if (timeout <= overflow)
  111. {
  112. counter = (rt_uint32_t)(timeout * timer->freq);
  113. devi = tv_sec - (counter / (float)timer->freq) * i;
  114. /* Minimum calculation error */
  115. if (devi > devi_min)
  116. {
  117. i = index;
  118. timeout = tv_sec/i;
  119. break;
  120. }
  121. else if (devi == 0)
  122. {
  123. break;
  124. }
  125. else if (devi < devi_min)
  126. {
  127. devi_min = devi;
  128. index = i;
  129. }
  130. }
  131. }
  132. }
  133. timer->cycles = i;
  134. timer->reload = i;
  135. timer->period_sec = timeout;
  136. counter = (rt_uint32_t)(timeout * timer->freq);
  137. return counter;
  138. }
  139. static rt_err_t rt_clock_timer_init(struct rt_device *dev)
  140. {
  141. rt_err_t result = RT_EOK;
  142. rt_clock_timer_t *timer;
  143. timer = (rt_clock_timer_t *)dev;
  144. /* try to change to 1MHz */
  145. if ((1000000 <= timer->info->maxfreq) && (1000000 >= timer->info->minfreq))
  146. {
  147. timer->freq = 1000000;
  148. }
  149. else
  150. {
  151. timer->freq = timer->info->minfreq;
  152. }
  153. timer->mode = CLOCK_TIMER_MODE_ONESHOT;
  154. timer->cycles = 0;
  155. timer->overflow = 0;
  156. if (timer->ops->init)
  157. {
  158. timer->ops->init(timer, 1);
  159. }
  160. else
  161. {
  162. result = -RT_ENOSYS;
  163. }
  164. return result;
  165. }
  166. static rt_err_t rt_clock_timer_open(struct rt_device *dev, rt_uint16_t oflag)
  167. {
  168. rt_err_t result = RT_EOK;
  169. rt_clock_timer_t *timer;
  170. timer = (rt_clock_timer_t *)dev;
  171. if (timer->ops->control != RT_NULL)
  172. {
  173. timer->ops->control(timer, CLOCK_TIMER_CTRL_FREQ_SET, &timer->freq);
  174. }
  175. else
  176. {
  177. result = -RT_ENOSYS;
  178. }
  179. return result;
  180. }
  181. static rt_err_t rt_clock_timer_close(struct rt_device *dev)
  182. {
  183. rt_err_t result = RT_EOK;
  184. rt_clock_timer_t *timer;
  185. timer = (rt_clock_timer_t*)dev;
  186. if (timer->ops->init != RT_NULL)
  187. {
  188. timer->ops->init(timer, 0);
  189. }
  190. else
  191. {
  192. result = -RT_ENOSYS;
  193. }
  194. dev->flag &= ~RT_DEVICE_FLAG_ACTIVATED;
  195. dev->rx_indicate = RT_NULL;
  196. return result;
  197. }
  198. static rt_ssize_t rt_clock_timer_read(struct rt_device *dev, rt_off_t pos, void *buffer, rt_size_t size)
  199. {
  200. rt_clock_timer_t *timer;
  201. rt_clock_timerval_t tv;
  202. rt_uint32_t cnt;
  203. rt_base_t level;
  204. rt_int32_t overflow;
  205. float t;
  206. timer = (rt_clock_timer_t *)dev;
  207. if (timer->ops->count_get == RT_NULL)
  208. return 0;
  209. level = rt_hw_interrupt_disable();
  210. cnt = timer->ops->count_get(timer);
  211. overflow = timer->overflow;
  212. rt_hw_interrupt_enable(level);
  213. if (timer->info->cntmode == CLOCK_TIMER_CNTMODE_DW)
  214. {
  215. cnt = (rt_uint32_t)(timer->freq * timer->period_sec) - cnt;
  216. }
  217. if (timer->mode == CLOCK_TIMER_MODE_ONESHOT)
  218. {
  219. overflow = 0;
  220. }
  221. t = overflow * timer->period_sec + cnt/(float)timer->freq;
  222. tv.sec = (rt_int32_t)t;
  223. tv.usec = (rt_int32_t)((t - tv.sec) * 1000000);
  224. size = size > sizeof(tv)? sizeof(tv) : size;
  225. rt_memcpy(buffer, &tv, size);
  226. return size;
  227. }
  228. static rt_ssize_t rt_clock_timer_write(struct rt_device *dev, rt_off_t pos, const void *buffer, rt_size_t size)
  229. {
  230. rt_base_t level;
  231. rt_uint32_t t;
  232. rt_clock_timer_mode_t opm = CLOCK_TIMER_MODE_PERIOD;
  233. rt_clock_timer_t *timer;
  234. timer = (rt_clock_timer_t *)dev;
  235. if ((timer->ops->start == RT_NULL) || (timer->ops->stop == RT_NULL))
  236. return 0;
  237. if (size != sizeof(rt_clock_timerval_t))
  238. return 0;
  239. timer->ops->stop(timer);
  240. level = rt_hw_interrupt_disable();
  241. timer->overflow = 0;
  242. rt_hw_interrupt_enable(level);
  243. t = timeout_calc(timer, (rt_clock_timerval_t*)buffer);
  244. if ((timer->cycles <= 1) && (timer->mode == CLOCK_TIMER_MODE_ONESHOT))
  245. {
  246. opm = CLOCK_TIMER_MODE_ONESHOT;
  247. }
  248. if (timer->ops->start(timer, t, opm) != RT_EOK)
  249. size = 0;
  250. return size;
  251. }
  252. static rt_err_t rt_clock_timer_control(struct rt_device *dev, int cmd, void *args)
  253. {
  254. rt_base_t level;
  255. rt_err_t result = RT_EOK;
  256. rt_clock_timer_t *timer;
  257. timer = (rt_clock_timer_t *)dev;
  258. switch (cmd)
  259. {
  260. case CLOCK_TIMER_CTRL_STOP:
  261. {
  262. if (timer->ops->stop != RT_NULL)
  263. {
  264. timer->ops->stop(timer);
  265. }
  266. else
  267. {
  268. result = -RT_ENOSYS;
  269. }
  270. }
  271. break;
  272. case CLOCK_TIMER_CTRL_FREQ_SET:
  273. {
  274. rt_int32_t *f;
  275. if (args == RT_NULL)
  276. {
  277. result = -RT_EEMPTY;
  278. break;
  279. }
  280. f = (rt_int32_t*)args;
  281. if ((*f > timer->info->maxfreq) || (*f < timer->info->minfreq))
  282. {
  283. LOG_W("frequency setting out of range! It will maintain at %d Hz", timer->freq);
  284. result = -RT_EINVAL;
  285. break;
  286. }
  287. if (timer->ops->control != RT_NULL)
  288. {
  289. result = timer->ops->control(timer, cmd, args);
  290. if (result == RT_EOK)
  291. {
  292. level = rt_hw_interrupt_disable();
  293. timer->freq = *f;
  294. rt_hw_interrupt_enable(level);
  295. }
  296. }
  297. else
  298. {
  299. result = -RT_ENOSYS;
  300. }
  301. }
  302. break;
  303. case CLOCK_TIMER_CTRL_INFO_GET:
  304. {
  305. if (args == RT_NULL)
  306. {
  307. result = -RT_EEMPTY;
  308. break;
  309. }
  310. *((struct rt_clock_timer_info*)args) = *timer->info;
  311. }
  312. break;
  313. case CLOCK_TIMER_CTRL_MODE_SET:
  314. {
  315. rt_clock_timer_mode_t *m;
  316. if (args == RT_NULL)
  317. {
  318. result = -RT_EEMPTY;
  319. break;
  320. }
  321. m = (rt_clock_timer_mode_t*)args;
  322. if ((*m != CLOCK_TIMER_MODE_ONESHOT) && (*m != CLOCK_TIMER_MODE_PERIOD))
  323. {
  324. result = -RT_ERROR;
  325. break;
  326. }
  327. level = rt_hw_interrupt_disable();
  328. timer->mode = *m;
  329. rt_hw_interrupt_enable(level);
  330. }
  331. break;
  332. default:
  333. {
  334. if (timer->ops->control != RT_NULL)
  335. {
  336. result = timer->ops->control(timer, cmd, args);
  337. }
  338. else
  339. {
  340. result = -RT_ENOSYS;
  341. }
  342. }
  343. break;
  344. }
  345. return result;
  346. }
  347. void rt_clock_timer_isr(rt_clock_timer_t *timer)
  348. {
  349. rt_base_t level;
  350. RT_ASSERT(timer != RT_NULL);
  351. level = rt_hw_interrupt_disable();
  352. timer->overflow ++;
  353. if (timer->cycles != 0)
  354. {
  355. timer->cycles --;
  356. }
  357. if (timer->cycles == 0)
  358. {
  359. timer->cycles = timer->reload;
  360. rt_hw_interrupt_enable(level);
  361. if (timer->mode == CLOCK_TIMER_MODE_ONESHOT)
  362. {
  363. if (timer->ops->stop != RT_NULL)
  364. {
  365. timer->ops->stop(timer);
  366. }
  367. }
  368. if (timer == _clock_timer_owner)
  369. {
  370. rt_clock_time_event_isr();
  371. }
  372. if (timer->parent.rx_indicate != RT_NULL)
  373. {
  374. timer->parent.rx_indicate(&timer->parent, sizeof(struct rt_clock_timerval));
  375. }
  376. }
  377. else
  378. {
  379. rt_hw_interrupt_enable(level);
  380. }
  381. }
  382. #ifdef RT_USING_DEVICE_OPS
  383. const static struct rt_device_ops clock_timer_ops =
  384. {
  385. rt_clock_timer_init,
  386. rt_clock_timer_open,
  387. rt_clock_timer_close,
  388. rt_clock_timer_read,
  389. rt_clock_timer_write,
  390. rt_clock_timer_control
  391. };
  392. #endif
  393. rt_err_t rt_clock_timer_register(rt_clock_timer_t *timer, const char *name, void *user_data)
  394. {
  395. struct rt_device *device;
  396. rt_err_t result;
  397. rt_uint8_t caps = 0;
  398. RT_ASSERT(timer != RT_NULL);
  399. RT_ASSERT(timer->ops != RT_NULL);
  400. RT_ASSERT(timer->info != RT_NULL);
  401. device = &(timer->parent);
  402. device->type = RT_Device_Class_Timer;
  403. device->rx_indicate = RT_NULL;
  404. device->tx_complete = RT_NULL;
  405. #ifdef RT_USING_DEVICE_OPS
  406. device->ops = &clock_timer_ops;
  407. #else
  408. device->init = rt_clock_timer_init;
  409. device->open = rt_clock_timer_open;
  410. device->close = rt_clock_timer_close;
  411. device->read = rt_clock_timer_read;
  412. device->write = rt_clock_timer_write;
  413. device->control = rt_clock_timer_control;
  414. #endif
  415. device->user_data = user_data;
  416. result = rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STANDALONE);
  417. if (result != RT_EOK)
  418. {
  419. return result;
  420. }
  421. if (timer->ops->start)
  422. {
  423. caps |= RT_CLOCK_TIME_CAP_EVENT;
  424. }
  425. if (caps && _clock_timer_owner == RT_NULL)
  426. {
  427. char ct_name[RT_NAME_MAX];
  428. _clock_timer_owner = timer;
  429. _clock_timer_clock_dev.ops = &_clock_timer_clock_ops;
  430. _clock_timer_clock_dev.res_scale = RT_CLOCK_TIME_RESMUL;
  431. _clock_timer_clock_dev.caps = caps;
  432. rt_snprintf(ct_name, sizeof(ct_name), "clock_time_%s", name);
  433. rt_clock_time_device_register(&_clock_timer_clock_dev, ct_name, caps);
  434. if ((caps & RT_CLOCK_TIME_CAP_EVENT) && rt_clock_time_get_default_event() == RT_NULL)
  435. {
  436. rt_clock_time_set_default_event(&_clock_timer_clock_dev);
  437. if (!(device->flag & RT_DEVICE_FLAG_ACTIVATED))
  438. {
  439. rt_device_init(device);
  440. rt_device_open(device, RT_DEVICE_OFLAG_RDWR);
  441. }
  442. }
  443. }
  444. return RT_EOK;
  445. }