drv_uart.c 14 KB

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  1. /*
  2. * Copyright (c) 2019 Winner Microelectronics Co., Ltd.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-09-15 flyingcys 1st version
  9. */
  10. #include <rtthread.h>
  11. #include <rtdevice.h>
  12. #include "wm_io.h"
  13. #include "wm_uart.h"
  14. #include "wm_gpio_afsel.h"
  15. #include "wm_type_def.h"
  16. #include "wm_cpu.h"
  17. #include "drv_uart.h"
  18. #include "pin_map.h"
  19. #define WM600_UART0 (TLS_UART_REGS_T *) HR_UART0_BASE_ADDR
  20. #define WM600_UART1 (TLS_UART_REGS_T *) HR_UART1_BASE_ADDR
  21. #define WM600_UART2 (TLS_UART_REGS_T *) HR_UART2_BASE_ADDR
  22. static void wm_uart_reg_init(TLS_UART_REGS_T *UARTx)
  23. {
  24. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  25. if (UARTx == WM600_UART0)
  26. {
  27. /* disable auto flow control */
  28. tls_reg_write32(HR_UART0_FLOW_CTRL, 0);
  29. /* disable dma */
  30. tls_reg_write32(HR_UART0_DMA_CTRL, 0);
  31. /* one byte tx */
  32. tls_reg_write32(HR_UART0_FIFO_CTRL, 0);
  33. /* disable interrupt */
  34. tls_reg_write32(HR_UART0_INT_MASK, 0xFF);
  35. /* enable rx/timeout interrupt */
  36. tls_reg_write32(HR_UART0_INT_MASK, ~(3 << 2));
  37. }
  38. else if (UARTx == WM600_UART1)
  39. {
  40. /* 4 byte tx, 8 bytes rx */
  41. tls_reg_write32(HR_UART1_FIFO_CTRL, (0x01 << 2) | (0x02 << 4));
  42. /* enable rx timeout, disable rx dma, disable tx dma */
  43. tls_reg_write32(HR_UART1_DMA_CTRL, (8 << 3) | (1 << 2));
  44. /* enable rx/timeout interrupt */
  45. tls_reg_write32(HR_UART1_INT_MASK, ~(3 << 2));
  46. }
  47. else if (UARTx == WM600_UART2)
  48. {
  49. /* 4 byte tx, 8 bytes rx */
  50. tls_reg_write32(HR_UART2_FIFO_CTRL, (0x01 << 2) | (0x02 << 4));
  51. /* enable rx timeout, disable rx dma, disable tx dma */
  52. tls_reg_write32(HR_UART2_DMA_CTRL, (8 << 3) | (1 << 2));
  53. /* enable rx/timeout interrupt */
  54. tls_reg_write32(HR_UART2_INT_MASK, ~(3 << 2));
  55. UARTx->UR_LC &= ~(0x1000000);
  56. }
  57. }
  58. static void wm_uart_gpio_config(TLS_UART_REGS_T *UARTx)
  59. {
  60. #if defined(BSP_USING_UART1) || defined(BSP_USING_UART2)
  61. rt_int16_t gpio_pin;
  62. #endif
  63. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  64. if (UARTx == WM600_UART0)
  65. {
  66. /* UART0_TX-PA04 UART0_RX-PA05 */
  67. wm_uart0_tx_config(WM_IO_PA_04);
  68. wm_uart0_rx_config(WM_IO_PA_05);
  69. }
  70. #ifdef BSP_USING_UART1
  71. else if (UARTx == WM600_UART1)
  72. {
  73. gpio_pin = wm_get_pin(WM_UART1_RX_PIN);
  74. if (gpio_pin >= 0)
  75. {
  76. wm_uart1_rx_config((enum tls_io_name)gpio_pin);
  77. }
  78. gpio_pin = wm_get_pin(WM_UART1_TX_PIN);
  79. if (gpio_pin >= 0)
  80. {
  81. wm_uart1_tx_config((enum tls_io_name)gpio_pin);
  82. }
  83. }
  84. #endif
  85. #ifdef BSP_USING_UART2
  86. else if (UARTx == WM600_UART2)
  87. {
  88. gpio_pin = wm_get_pin(WM_UART2_RX_PIN);
  89. if (gpio_pin >= 0)
  90. {
  91. wm_uart2_rx_config((enum tls_io_name)gpio_pin);
  92. }
  93. gpio_pin = wm_get_pin(WM_UART2_TX_PIN);
  94. if (gpio_pin >= 0)
  95. {
  96. wm_uart2_tx_scio_config((enum tls_io_name)gpio_pin);
  97. }
  98. }
  99. #endif
  100. }
  101. static void wm_uart_irq_config(TLS_UART_REGS_T *UARTx)
  102. {
  103. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  104. /* config uart interrupt register */
  105. /* clear interrupt */
  106. UARTx->UR_INTS = 0xFFFFFFFF;
  107. /* enable interupt */
  108. UARTx->UR_INTM = 0x0;
  109. UARTx->UR_DMAC = (4UL << UDMA_RX_FIFO_TIMEOUT_SHIFT) | UDMA_RX_FIFO_TIMEOUT;
  110. /* config FIFO control */
  111. UARTx->UR_FIFOC = UFC_TX_FIFO_LVL_16_BYTE | UFC_RX_FIFO_LVL_16_BYTE | UFC_TX_FIFO_RESET | UFC_RX_FIFO_RESET;
  112. UARTx->UR_LC &= ~(ULCON_TX_EN | ULCON_RX_EN);
  113. UARTx->UR_LC |= ULCON_TX_EN | ULCON_RX_EN;
  114. }
  115. static int wm_uart_baudrate_set(TLS_UART_REGS_T *UARTx, u32 baudrate)
  116. {
  117. u32 value;
  118. u32 apbclk;
  119. tls_sys_clk sysclk;
  120. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  121. tls_sys_clk_get(&sysclk);
  122. apbclk = sysclk.apbclk * 1000000;
  123. value = (apbclk / (16 * baudrate) - 1) |
  124. (((apbclk % (baudrate * 16)) * 16 / (baudrate * 16)) << 16);
  125. UARTx->UR_BD = value;
  126. return WM_SUCCESS;
  127. }
  128. static int wm_uart_parity_set(TLS_UART_REGS_T *UARTx, TLS_UART_PMODE_T paritytype)
  129. {
  130. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  131. if (paritytype == TLS_UART_PMODE_DISABLED)
  132. UARTx->UR_LC &= ~ULCON_PMD_EN;
  133. else if (paritytype == TLS_UART_PMODE_EVEN)
  134. {
  135. UARTx->UR_LC &= ~ULCON_PMD_MASK;
  136. UARTx->UR_LC |= ULCON_PMD_EVEN;
  137. }
  138. else if (paritytype == TLS_UART_PMODE_ODD)
  139. {
  140. UARTx->UR_LC &= ~ULCON_PMD_MASK;
  141. UARTx->UR_LC |= ULCON_PMD_ODD;
  142. }
  143. else
  144. return WM_FAILED;
  145. return WM_SUCCESS;
  146. }
  147. static int wm_uart_stopbits_set(TLS_UART_REGS_T *UARTx, TLS_UART_STOPBITS_T stopbits)
  148. {
  149. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  150. if (stopbits == TLS_UART_TWO_STOPBITS)
  151. UARTx->UR_LC |= ULCON_STOP_2;
  152. else
  153. UARTx->UR_LC &= ~ULCON_STOP_2;
  154. return WM_SUCCESS;
  155. }
  156. static int wm_uart_databits_set(TLS_UART_REGS_T *UARTx, TLS_UART_CHSIZE_T charlength)
  157. {
  158. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  159. UARTx->UR_LC &= ~ULCON_WL_MASK;
  160. if (charlength == TLS_UART_CHSIZE_5BIT)
  161. UARTx->UR_LC |= ULCON_WL5;
  162. else if (charlength == TLS_UART_CHSIZE_6BIT)
  163. UARTx->UR_LC |= ULCON_WL6;
  164. else if (charlength == TLS_UART_CHSIZE_7BIT)
  165. UARTx->UR_LC |= ULCON_WL7;
  166. else if (charlength == TLS_UART_CHSIZE_8BIT)
  167. UARTx->UR_LC |= ULCON_WL8;
  168. else
  169. return WM_FAILED;
  170. return WM_SUCCESS;
  171. }
  172. static int wm_uart_flow_ctrl_set(TLS_UART_REGS_T *UARTx, TLS_UART_FLOW_CTRL_MODE_T flow_ctrl)
  173. {
  174. RT_ASSERT(UARTx == WM600_UART0 || UARTx == WM600_UART1 || UARTx == WM600_UART2);
  175. switch (flow_ctrl)
  176. {
  177. case TLS_UART_FLOW_CTRL_NONE:
  178. UARTx->UR_FC = 0;
  179. break;
  180. case TLS_UART_FLOW_CTRL_HARDWARE:
  181. UARTx->UR_FC = (1UL << 0) | (6UL << 2);
  182. break;
  183. default:
  184. break;
  185. }
  186. return WM_SUCCESS;
  187. }
  188. struct device_uart
  189. {
  190. TLS_UART_REGS_T volatile *uart_device;
  191. rt_uint32_t uart_irq_no;
  192. };
  193. static rt_err_t drv_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
  194. static rt_err_t drv_uart_control(struct rt_serial_device *serial, int cmd, void *arg);
  195. static int drv_uart_putc(struct rt_serial_device *serial, char c);
  196. static int drv_uart_getc(struct rt_serial_device *serial);
  197. static rt_size_t drv_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction);
  198. const struct rt_uart_ops _uart_ops =
  199. {
  200. drv_uart_configure,
  201. drv_uart_control,
  202. drv_uart_putc,
  203. drv_uart_getc,
  204. drv_uart_dma_transmit
  205. };
  206. /*
  207. * UART interface
  208. */
  209. static rt_err_t drv_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
  210. {
  211. struct device_uart *uart;
  212. u32 baud_rate;
  213. TLS_UART_PMODE_T parity;
  214. TLS_UART_STOPBITS_T stop_bits;
  215. TLS_UART_CHSIZE_T data_bits;
  216. RT_ASSERT(serial != RT_NULL && cfg != RT_NULL);
  217. serial->config = *cfg;
  218. uart = (struct device_uart *)serial->parent.user_data;
  219. RT_ASSERT(uart != RT_NULL);
  220. switch (cfg->baud_rate)
  221. {
  222. case BAUD_RATE_2000000:
  223. case BAUD_RATE_921600:
  224. case BAUD_RATE_460800:
  225. case BAUD_RATE_230400:
  226. case BAUD_RATE_115200:
  227. case BAUD_RATE_57600:
  228. case BAUD_RATE_38400:
  229. case BAUD_RATE_19200:
  230. case BAUD_RATE_9600:
  231. case BAUD_RATE_4800:
  232. case BAUD_RATE_2400:
  233. baud_rate = cfg->baud_rate;
  234. break;
  235. default:
  236. rt_kprintf("baudrate set failed... default rate:115200\r\n");
  237. baud_rate = BAUD_RATE_115200;
  238. break;
  239. }
  240. wm_uart_baudrate_set((TLS_UART_REGS_T *)uart->uart_device, baud_rate);
  241. switch (cfg->parity)
  242. {
  243. case PARITY_ODD:
  244. parity = TLS_UART_PMODE_ODD;
  245. break;
  246. case PARITY_EVEN:
  247. parity = TLS_UART_PMODE_EVEN;
  248. break;
  249. case PARITY_NONE:
  250. default:
  251. parity = TLS_UART_PMODE_DISABLED;
  252. break;
  253. }
  254. wm_uart_parity_set((TLS_UART_REGS_T *)uart->uart_device, parity);
  255. switch (cfg->stop_bits)
  256. {
  257. case STOP_BITS_2:
  258. stop_bits = TLS_UART_TWO_STOPBITS;
  259. break;
  260. case STOP_BITS_1:
  261. default:
  262. stop_bits = TLS_UART_ONE_STOPBITS;
  263. break;
  264. }
  265. wm_uart_stopbits_set((TLS_UART_REGS_T *)uart->uart_device, stop_bits);
  266. switch (cfg->data_bits)
  267. {
  268. case DATA_BITS_5:
  269. data_bits = TLS_UART_CHSIZE_5BIT;
  270. break;
  271. case DATA_BITS_6:
  272. data_bits = TLS_UART_CHSIZE_6BIT;
  273. break;
  274. case DATA_BITS_7:
  275. data_bits = TLS_UART_CHSIZE_7BIT;
  276. break;
  277. case DATA_BITS_8:
  278. default:
  279. data_bits = TLS_UART_CHSIZE_8BIT;
  280. break;
  281. }
  282. wm_uart_databits_set((TLS_UART_REGS_T *)uart->uart_device, data_bits);
  283. wm_uart_flow_ctrl_set((TLS_UART_REGS_T *)uart->uart_device, TLS_UART_FLOW_CTRL_NONE);
  284. return (RT_EOK);
  285. }
  286. static rt_err_t drv_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
  287. {
  288. struct device_uart *uart;
  289. RT_ASSERT(serial != RT_NULL);
  290. uart = (struct device_uart *)serial->parent.user_data;
  291. RT_ASSERT(uart != RT_NULL);
  292. switch (cmd)
  293. {
  294. case RT_DEVICE_CTRL_CLR_INT:
  295. /* Disable the UART Interrupt */
  296. tls_irq_disable(uart->uart_irq_no);
  297. break;
  298. case RT_DEVICE_CTRL_SET_INT:
  299. /* Enable the UART Interrupt */
  300. tls_irq_enable(uart->uart_irq_no);
  301. break;
  302. }
  303. return (RT_EOK);
  304. }
  305. static int drv_uart_putc(struct rt_serial_device *serial, char c)
  306. {
  307. struct device_uart *uart;
  308. RT_ASSERT(serial != RT_NULL);
  309. uart = (struct device_uart *)serial->parent.user_data;
  310. RT_ASSERT(uart != RT_NULL);
  311. while (uart->uart_device->UR_FIFOS & 0x3F); /* wait THR is empty */
  312. uart->uart_device->UR_TXW = (char)c;
  313. return (1);
  314. }
  315. static int drv_uart_getc(struct rt_serial_device *serial)
  316. {
  317. int ch;
  318. struct device_uart *uart;
  319. RT_ASSERT(serial != RT_NULL);
  320. uart = (struct device_uart *)serial->parent.user_data;
  321. RT_ASSERT(uart != RT_NULL);
  322. ch = -1;
  323. if (uart->uart_device->UR_FIFOS & UFS_RX_FIFO_CNT_MASK)
  324. ch = (int)uart->uart_device->UR_RXW;
  325. return ch;
  326. }
  327. static rt_size_t drv_uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
  328. {
  329. return (0);
  330. }
  331. static void drv_uart_irq_handler(struct rt_serial_device *serial)
  332. {
  333. u32 intr_src;
  334. struct device_uart *uart;
  335. RT_ASSERT(serial != RT_NULL);
  336. uart = (struct device_uart *)serial->parent.user_data;
  337. RT_ASSERT(uart != RT_NULL);
  338. /* check interrupt status */
  339. intr_src = uart->uart_device->UR_INTS;
  340. uart->uart_device->UR_INTS = intr_src;
  341. if ((intr_src & UART_RX_INT_FLAG) && (0 == (uart->uart_device->UR_INTM & UIS_RX_FIFO)))
  342. {
  343. rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
  344. }
  345. if (intr_src & UART_TX_INT_FLAG)
  346. {
  347. }
  348. if (intr_src & UIS_CTS_CHNG)
  349. {
  350. }
  351. }
  352. #ifdef BSP_USING_UART0
  353. static struct rt_serial_device serial0;
  354. static struct device_uart uart0 =
  355. {
  356. WM600_UART0,
  357. UART0_INT,
  358. };
  359. void UART0_IRQHandler(void)
  360. {
  361. /* enter interrupt */
  362. rt_interrupt_enter();
  363. drv_uart_irq_handler(&serial0);
  364. /* leave interrupt */
  365. rt_interrupt_leave();
  366. }
  367. #endif
  368. #ifdef BSP_USING_UART1
  369. static struct rt_serial_device serial1;
  370. static struct device_uart uart1 =
  371. {
  372. WM600_UART1,
  373. UART1_INT,
  374. };
  375. void UART1_IRQHandler(void)
  376. {
  377. /* enter interrupt */
  378. rt_interrupt_enter();
  379. drv_uart_irq_handler(&serial1);
  380. /* leave interrupt */
  381. rt_interrupt_leave();
  382. }
  383. #endif
  384. #ifdef BSP_USING_UART2
  385. static struct rt_serial_device serial2;
  386. static struct device_uart uart2 =
  387. {
  388. WM600_UART2,
  389. UART2_INT,
  390. };
  391. void UART2_IRQHandler(void)
  392. {
  393. /* enter interrupt */
  394. rt_interrupt_enter();
  395. drv_uart_irq_handler(&serial2);
  396. /* leave interrupt */
  397. rt_interrupt_leave();
  398. }
  399. #endif
  400. /*
  401. * UART Initiation
  402. */
  403. int wm_hw_uart_init(void)
  404. {
  405. struct rt_serial_device *serial;
  406. struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
  407. struct device_uart *uart;
  408. #ifdef BSP_USING_UART0
  409. {
  410. serial = &serial0;
  411. uart = &uart0;
  412. /* Init UART Hardware */
  413. wm_uart_gpio_config((TLS_UART_REGS_T *)uart->uart_device);
  414. wm_uart_reg_init((TLS_UART_REGS_T *)uart->uart_device);
  415. wm_uart_irq_config((TLS_UART_REGS_T *)uart->uart_device);
  416. serial->ops = &_uart_ops;
  417. serial->config = config;
  418. serial->config.baud_rate = 115200;
  419. rt_hw_serial_register(serial,
  420. "uart0",
  421. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  422. uart);
  423. }
  424. #endif /* BSP_USING_UART0 */
  425. #ifdef BSP_USING_UART1
  426. {
  427. serial = &serial1;
  428. uart = &uart1;
  429. /* Init UART Hardware */
  430. wm_uart_gpio_config((TLS_UART_REGS_T *)uart->uart_device);
  431. wm_uart_reg_init((TLS_UART_REGS_T *)uart->uart_device);
  432. wm_uart_irq_config((TLS_UART_REGS_T *)uart->uart_device);
  433. serial->ops = &_uart_ops;
  434. serial->config = config;
  435. serial->config.baud_rate = WM_UART1_BAUDRATE;
  436. rt_hw_serial_register(serial,
  437. "uart1",
  438. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  439. uart);
  440. }
  441. #endif /* BSP_USING_UART1 */
  442. #ifdef BSP_USING_UART2
  443. {
  444. serial = &serial2;
  445. uart = &uart2;
  446. /* Init UART Hardware */
  447. wm_uart_gpio_config((TLS_UART_REGS_T *)uart->uart_device);
  448. wm_uart_reg_init((TLS_UART_REGS_T *)uart->uart_device);
  449. wm_uart_irq_config((TLS_UART_REGS_T *)uart->uart_device);
  450. serial->ops = &_uart_ops;
  451. serial->config = config;
  452. serial->config.baud_rate = WM_UART2_BAUDRATE;
  453. rt_hw_serial_register(serial,
  454. "uart2",
  455. RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
  456. uart);
  457. }
  458. #endif /* BSP_USING_UART2 */
  459. return 0;
  460. }
  461. INIT_BOARD_EXPORT(wm_hw_uart_init);