psci.c 10 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-09-09 GuEe-GUI The first version
  9. * 2022-09-24 GuEe-GUI Add operations and fdt init support
  10. */
  11. #include <rtthread.h>
  12. #define DBG_TAG "osi.psci"
  13. #define DBG_LVL DBG_INFO
  14. #include <rtdbg.h>
  15. /* support cpu mpidr and smccc from libcpu */
  16. #include <cpu.h>
  17. #include <smccc.h>
  18. #include <psci.h>
  19. #include <drivers/ofw.h>
  20. #include <drivers/platform.h>
  21. #include <drivers/core/dm.h>
  22. #include <drivers/core/power.h>
  23. struct psci_ops
  24. {
  25. rt_uint32_t (*get_version)(void);
  26. rt_uint32_t (*cpu_on)(int cpuid, rt_ubase_t entry_point);
  27. rt_uint32_t (*cpu_off)(rt_uint32_t state);
  28. rt_uint32_t (*cpu_suspend)(rt_uint32_t power_state, rt_ubase_t entry_point);
  29. rt_uint32_t (*migrate)(int cpuid);
  30. rt_uint32_t (*get_affinity_info)(rt_ubase_t target_affinity, rt_ubase_t lowest_affinity_level);
  31. rt_uint32_t (*migrate_info_type)(void);
  32. };
  33. struct psci_0_1_func_ids
  34. {
  35. rt_uint32_t cpu_on;
  36. rt_uint32_t cpu_off;
  37. rt_uint32_t cpu_suspend;
  38. rt_uint32_t migrate;
  39. };
  40. typedef rt_err_t (*psci_init_ofw_handle)(struct rt_ofw_node *np);
  41. typedef rt_ubase_t (*psci_call_handle)(rt_uint32_t fn, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
  42. /* [40:63] and [24:31] must be zero, other is aff3 (64bit), aff2, aff1, aff0 */
  43. #ifdef ARCH_CPU_64BIT
  44. #define PSCI_FNC_ID(version_major, version_min, name) PSCI_##version_major##_##version_min##_FN64_##name
  45. #define MPIDR_MASK 0xff00ffffff
  46. #else
  47. #define PSCI_FNC_ID(version_major, version_min, name) PSCI_##version_major##_##version_min##_FN_##name
  48. #define MPIDR_MASK 0x00ffffff
  49. #endif
  50. static struct psci_ops _psci_ops = {};
  51. static struct psci_0_1_func_ids psci_0_1_func_ids = {};
  52. static psci_call_handle psci_call;
  53. /* PSCI SMCCC */
  54. static rt_ubase_t psci_smc_call(rt_uint32_t fn, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2)
  55. {
  56. struct arm_smccc_res_t res;
  57. arm_smccc_smc(fn, arg0, arg1, arg2, 0, 0, 0, 0, &res, RT_NULL);
  58. return res.a0;
  59. }
  60. static rt_ubase_t psci_hvc_call(rt_uint32_t fn, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2)
  61. {
  62. struct arm_smccc_res_t res;
  63. arm_smccc_hvc(fn, arg0, arg1, arg2, 0, 0, 0, 0, &res, RT_NULL);
  64. return res.a0;
  65. }
  66. /* PSCI VERSION */
  67. static rt_uint32_t psci_0_1_get_version(void)
  68. {
  69. return PSCI_VERSION(0, 1);
  70. }
  71. static rt_uint32_t psci_0_2_get_version(void)
  72. {
  73. return (rt_uint32_t)psci_call(PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0);
  74. }
  75. /* PSCI FEATURES */
  76. static rt_uint32_t psci_get_features(rt_uint32_t psci_func_id)
  77. {
  78. return (rt_uint32_t)psci_call(PSCI_1_0_FN_PSCI_FEATURES, psci_func_id, 0, 0);
  79. }
  80. /* PSCI CPU_ON */
  81. static rt_uint32_t psci_cpu_on(rt_uint32_t func_id, int cpuid, rt_ubase_t entry_point)
  82. {
  83. rt_ubase_t mpid = rt_cpu_mpidr_table[cpuid] & MPIDR_MASK;
  84. return (rt_uint32_t)psci_call(func_id, mpid, entry_point, 0);
  85. }
  86. static rt_uint32_t psci_0_1_cpu_on(int cpuid, rt_ubase_t entry_point)
  87. {
  88. return psci_cpu_on(psci_0_1_func_ids.cpu_on, cpuid, entry_point);
  89. }
  90. static rt_uint32_t psci_0_2_cpu_on(int cpuid, rt_ubase_t entry_point)
  91. {
  92. return psci_cpu_on(PSCI_FNC_ID(0, 2, CPU_ON), cpuid, entry_point);
  93. }
  94. /* PSCI CPU_OFF */
  95. static rt_uint32_t psci_cpu_off(rt_uint32_t func_id, rt_uint32_t state)
  96. {
  97. return (rt_uint32_t)psci_call(func_id, state, 0, 0);
  98. }
  99. static rt_uint32_t psci_0_1_cpu_off(rt_uint32_t state)
  100. {
  101. return psci_cpu_off(psci_0_1_func_ids.cpu_off, state);
  102. }
  103. static rt_uint32_t psci_0_2_cpu_off(rt_uint32_t state)
  104. {
  105. return psci_cpu_off(PSCI_0_2_FN_CPU_OFF, state);
  106. }
  107. /* PSCI CPU_SUSPEND */
  108. static rt_uint32_t psci_cpu_suspend(rt_uint32_t func_id, rt_uint32_t power_state, rt_ubase_t entry_point)
  109. {
  110. return (rt_uint32_t)psci_call(func_id, power_state, entry_point, 0);
  111. }
  112. static rt_uint32_t psci_0_1_cpu_suspend(rt_uint32_t power_state, rt_ubase_t entry_point)
  113. {
  114. return psci_cpu_suspend(psci_0_1_func_ids.cpu_suspend, power_state, entry_point);
  115. }
  116. static rt_uint32_t psci_0_2_cpu_suspend(rt_uint32_t power_state, rt_ubase_t entry_point)
  117. {
  118. return psci_cpu_suspend(PSCI_FNC_ID(0, 2, CPU_SUSPEND), power_state, entry_point);
  119. }
  120. /* PSCI CPU_MIGRATE */
  121. static rt_uint32_t psci_migrate(rt_uint32_t func_id, int cpuid)
  122. {
  123. rt_uint32_t ret = -PSCI_RET_INVALID_PARAMETERS;
  124. if (cpuid < RT_CPUS_NR)
  125. {
  126. rt_ubase_t mpid = rt_cpu_mpidr_table[cpuid] & MPIDR_MASK;
  127. ret = (rt_uint32_t)psci_call(func_id, mpid, 0, 0);
  128. }
  129. return ret;
  130. }
  131. static rt_uint32_t psci_0_1_migrate(int cpuid)
  132. {
  133. return psci_migrate(psci_0_1_func_ids.migrate, cpuid);
  134. }
  135. static rt_uint32_t psci_0_2_migrate(int cpuid)
  136. {
  137. return psci_migrate(PSCI_FNC_ID(0, 2, MIGRATE), cpuid);
  138. }
  139. /* PSCI AFFINITY_INFO */
  140. static rt_uint32_t psci_affinity_info(rt_ubase_t target_affinity, rt_ubase_t lowest_affinity_level)
  141. {
  142. return (rt_uint32_t)psci_call(PSCI_FNC_ID(0, 2, AFFINITY_INFO), target_affinity, lowest_affinity_level, 0);
  143. }
  144. /* PSCI MIGRATE_INFO_TYPE */
  145. static rt_uint32_t psci_migrate_info_type(void)
  146. {
  147. return (rt_uint32_t)psci_call(PSCI_0_2_FN_MIGRATE_INFO_TYPE, 0, 0, 0);
  148. }
  149. /* PSCI SYSTEM_OFF */
  150. void psci_system_off(void)
  151. {
  152. psci_call(PSCI_0_2_FN_SYSTEM_OFF, 0, 0, 0);
  153. }
  154. /* PSCI SYSTEM_RESET */
  155. void psci_system_reboot(void)
  156. {
  157. if (psci_get_features(PSCI_FNC_ID(1, 1, SYSTEM_RESET2)) != PSCI_RET_NOT_SUPPORTED)
  158. {
  159. /*
  160. * reset_type[31] = 0 (architectural)
  161. * reset_type[30:0] = 0 (SYSTEM_WARM_RESET)
  162. * cookie = 0 (ignored by the implementation)
  163. */
  164. psci_call(PSCI_FNC_ID(1, 1, SYSTEM_RESET2), 0, 0, 0);
  165. }
  166. else
  167. {
  168. psci_call(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0);
  169. }
  170. }
  171. #define PSCI_CALL_FN_RET(fn, ...) \
  172. ({ \
  173. rt_uint32_t rc; \
  174. rc = PSCI_RET_NOT_SUPPORTED; \
  175. if (_psci_ops.fn) \
  176. rc = _psci_ops.fn(__VA_ARGS__); \
  177. rc; \
  178. })
  179. #define PSCI_CALL_FN(fn, ...) \
  180. ({ \
  181. if (_psci_ops.fn) \
  182. _psci_ops.fn(__VA_ARGS__); \
  183. })
  184. rt_uint32_t rt_psci_get_version(void)
  185. {
  186. return PSCI_CALL_FN_RET(get_version);
  187. }
  188. rt_uint32_t rt_psci_cpu_on(int cpuid, rt_ubase_t entry_point)
  189. {
  190. return PSCI_CALL_FN_RET(cpu_on, cpuid, entry_point);
  191. }
  192. rt_uint32_t rt_psci_cpu_off(rt_uint32_t state)
  193. {
  194. return PSCI_CALL_FN_RET(cpu_off, state);
  195. }
  196. rt_uint32_t rt_psci_cpu_suspend(rt_uint32_t power_state, rt_ubase_t entry_point)
  197. {
  198. return PSCI_CALL_FN_RET(cpu_suspend, power_state, entry_point);
  199. }
  200. rt_uint32_t rt_psci_migrate(int cpuid)
  201. {
  202. return PSCI_CALL_FN_RET(migrate, cpuid);
  203. }
  204. rt_uint32_t rt_psci_get_affinity_info(rt_ubase_t target_affinity, rt_ubase_t lowest_affinity_level)
  205. {
  206. return PSCI_CALL_FN_RET(get_affinity_info, target_affinity, lowest_affinity_level);
  207. }
  208. rt_uint32_t rt_psci_migrate_info_type(void)
  209. {
  210. return PSCI_CALL_FN_RET(migrate_info_type);
  211. }
  212. #undef PSCI_CALL_FN_RET
  213. #undef PSCI_CALL_FN
  214. /* PSCI INIT */
  215. static rt_err_t psci_0_1_init(struct rt_ofw_node *np)
  216. {
  217. rt_err_t err = RT_EOK;
  218. rt_uint32_t func_id;
  219. _psci_ops.get_version = psci_0_1_get_version;
  220. if (!rt_ofw_prop_read_u32(np, "cpu_on", &func_id))
  221. {
  222. psci_0_1_func_ids.cpu_on = func_id;
  223. _psci_ops.cpu_on = psci_0_1_cpu_on;
  224. }
  225. if (!rt_ofw_prop_read_u32(np, "cpu_off", &func_id))
  226. {
  227. psci_0_1_func_ids.cpu_off = func_id;
  228. _psci_ops.cpu_off = psci_0_1_cpu_off;
  229. }
  230. if (!rt_ofw_prop_read_u32(np, "cpu_suspend", &func_id))
  231. {
  232. psci_0_1_func_ids.cpu_suspend = func_id;
  233. _psci_ops.cpu_suspend = psci_0_1_cpu_suspend;
  234. }
  235. if (!rt_ofw_prop_read_u32(np, "migrate", &func_id))
  236. {
  237. psci_0_1_func_ids.migrate = func_id;
  238. _psci_ops.migrate = psci_0_1_migrate;
  239. }
  240. return err;
  241. }
  242. static rt_err_t psci_0_2_init(struct rt_ofw_node *np)
  243. {
  244. rt_err_t err = RT_EOK;
  245. rt_uint32_t version = psci_0_2_get_version();
  246. if (version >= PSCI_VERSION(0, 2))
  247. {
  248. _psci_ops.get_version = psci_0_2_get_version;
  249. _psci_ops.cpu_on = psci_0_2_cpu_on;
  250. _psci_ops.cpu_off = psci_0_2_cpu_off;
  251. _psci_ops.cpu_suspend = psci_0_2_cpu_suspend;
  252. _psci_ops.migrate = psci_0_2_migrate;
  253. _psci_ops.get_affinity_info = psci_affinity_info;
  254. _psci_ops.migrate_info_type = psci_migrate_info_type;
  255. if (!rt_dm_machine_shutdown)
  256. {
  257. rt_dm_machine_shutdown = psci_system_off;
  258. }
  259. if (!rt_dm_machine_reset)
  260. {
  261. rt_dm_machine_reset = psci_system_reboot;
  262. }
  263. }
  264. else
  265. {
  266. LOG_E("PSCI version detected");
  267. err = -RT_EINVAL;
  268. }
  269. return err;
  270. }
  271. static rt_err_t psci_1_0_init(struct rt_ofw_node *np)
  272. {
  273. rt_err_t err;
  274. err = psci_0_2_init(np);
  275. return err;
  276. }
  277. static rt_err_t psci_ofw_init(struct rt_platform_device *pdev)
  278. {
  279. rt_err_t err = RT_EOK;
  280. const char *method;
  281. const struct rt_ofw_node_id *id = pdev->id;
  282. struct rt_ofw_node *np = pdev->parent.ofw_node;
  283. if (!rt_ofw_prop_read_string(np, "method", &method))
  284. {
  285. if (!rt_strcmp(method, "smc"))
  286. {
  287. psci_call = psci_smc_call;
  288. }
  289. else if (!rt_strcmp(method, "hvc"))
  290. {
  291. psci_call = psci_hvc_call;
  292. }
  293. else
  294. {
  295. LOG_E("Invalid \"method\" property: %s", method);
  296. err = -RT_EINVAL;
  297. }
  298. if (!err)
  299. {
  300. psci_init_ofw_handle psci_init = (psci_init_ofw_handle)id->data;
  301. err = psci_init(np);
  302. if (!err)
  303. {
  304. rt_uint32_t version = rt_psci_get_version();
  305. rt_ofw_data(np) = &_psci_ops;
  306. RT_UNUSED(version);
  307. LOG_I("Using PSCI v%d.%d Function IDs", PSCI_VERSION_MAJOR(version), PSCI_VERSION_MINOR(version));
  308. }
  309. }
  310. }
  311. else
  312. {
  313. err = -RT_ENOSYS;
  314. }
  315. return err;
  316. }
  317. static rt_err_t psci_probe(struct rt_platform_device *pdev)
  318. {
  319. rt_err_t err;
  320. err = psci_ofw_init(pdev);
  321. return err;
  322. }
  323. static const struct rt_ofw_node_id psci_ofw_ids[] =
  324. {
  325. { .compatible = "arm,psci", .data = psci_0_1_init },
  326. { .compatible = "arm,psci-0.2", .data = psci_0_2_init },
  327. { .compatible = "arm,psci-1.0", .data = psci_1_0_init },
  328. { /* sentinel */ }
  329. };
  330. static struct rt_platform_driver psci_driver =
  331. {
  332. .name = "arm-psci",
  333. .ids = psci_ofw_ids,
  334. .probe = psci_probe,
  335. };
  336. static int psci_drv_register(void)
  337. {
  338. rt_platform_driver_register(&psci_driver);
  339. return 0;
  340. }
  341. INIT_PLATFORM_EXPORT(psci_drv_register);