rt-thread/bsp/Infineon/xmc7200-kit_xmc7200_evk/board/linker_scripts/link.icf

/*******************************************************************************
* \file xmc7200_x8384_cm7.icf
* \version 1.0.0
*
* Linker file for the IAR compiler.
*
* The main purpose of the linker script is to describe how the sections in the
* input files should be mapped into the output file, and to control the memory
* layout of the output file.
*
* \note The entry point is fixed and starts at 0x10000000. The valid application
* image should be placed there.
*
* \note The linker files included with the PDL template projects must be generic
* and handle all common use cases. Your project may not use every section
* defined in the linker files. In that case you may see warnings during the
* build process. In your project, you can simply comment out or remove the
* relevant code in the linker file.
*
********************************************************************************
* \copyright
* Copyright 2021 Cypress Semiconductor Corporation
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/

define symbol sram_start_reserve                = 0;

define symbol sram_total_size                   = 0x00100000;
define symbol sram_private_for_srom             = 0x00000800; /* Private SRAM for SROM (e.g. API processing) */
define symbol sram_used_by_boot                 = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */

define symbol cm0plus_sram_reserve              = 0x00004000; /* 16K   : cm0 sram size */
define symbol cm7_0_sram_reserve                = 0x000FC000; /* 1008K : cm7_0 sram size */

define symbol code_flash_total_size             = 0x00830000; /* 8384K: total flash size */
define symbol cm0plus_code_flash_reserve        = 0x00080000; /* 512K : cm0 flash size */
define symbol cm7_0_code_flash_reserve          = 0x007B0000; /* 7872K: cm7_0 flash size */


define symbol code_flash_base_address           = 0x10000000;
define symbol sram_base_address                 = 0x28000000;

define symbol ecc_init_width                    = 8; /* Most restrictive native ECC width of all "normal" memories (SRAM, DTCM, ITCM) in any Traveo II derivate is used to keep the code generic */

define symbol cm7_heap_reserve                  =  0x00001000;
define symbol cm7_stack_reserve                 =  0x00001000;

/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;

/* The symbols below define the location and size of blocks of memory in the target.
 * Use these symbols to specify the memory regions available for allocation.
 */

/* The following symbols control RAM and flash memory allocation for the CM7 cores.
 * You can change the memory allocation by editing RAM and Flash values.
 * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
 * where 'xx' is the device group; for example, 'xmc7100d_x4160_cm0plus.icf'.
 * any changes here must also be aligned in file 'xmc7xxx_partition.h'.
 * after which cm0p core aplication must be build and flashed again.
 */
/* RAM */
define symbol __ICFEDIT_region_IRAM1_start__ = 0x28004000; // sram_base_address + cm0plus_sram_reserve;
define symbol __ICFEDIT_region_IRAM1_end__   = 0x280FFFFF; // cm7_0_sram_reserve;
define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;

/* Flash */
define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; // code_flash_base_address + cm0plus_code_flash_reserve
define symbol __ICFEDIT_region_IROM1_end__   = 0x1082FFFF; // cm7_0_code_flash_reserve
define symbol __ICFEDIT_region_IROM2_start__ = 0x0;
define symbol __ICFEDIT_region_IROM2_end__   = 0x0;

define symbol __ICFEDIT_region_EROM1_start__ = 0x0;
define symbol __ICFEDIT_region_EROM1_end__   = 0x0;
define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
define symbol __ICFEDIT_region_EROM3_end__   = 0x0;


define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
/*-Sizes-*/

define symbol __ICFEDIT_size_cstack__ = 0x00001000; //cm7_stack_reserve
define symbol __ICFEDIT_size_proc_stack__ = 0x0;

/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
define symbol __ICFEDIT_size_heap__ = 0x00001000; //cm7_heap_reserve

/**** End of ICF editor section. ###ICF###*/

define symbol heap_reserve                      = __ICFEDIT_size_heap__;
define symbol stack_reserve                     = (__ICFEDIT_size_cstack__ + (ecc_init_width - 1)) & (~((ecc_init_width - 1))); /* Ensure that stack size is an integer multiple of ECC init width (round up) */

/* SRAM reservations */
define symbol _base_SRAM_CM7_0                  = __ICFEDIT_region_IRAM1_start__;
define symbol _size_SRAM_CM7_0                  = __ICFEDIT_region_IRAM1_end__ - __ICFEDIT_region_IRAM1_start__ + 1;

/* Code flash reservations */
define symbol _base_CODE_FLASH_CM0P             = code_flash_base_address;
define symbol _size_CODE_FLASH_CM0P             = cm0plus_code_flash_reserve;
define symbol _base_CODE_FLASH_CM7_0            = __ICFEDIT_region_IROM1_start__;
define symbol _size_CODE_FLASH_CM7_0            = __ICFEDIT_region_IROM1_end__ - __ICFEDIT_region_IROM1_start__ + 1;


define symbol _base_SRAM                        = _base_SRAM_CM7_0;
define symbol _size_SRAM                        = _size_SRAM_CM7_0;
define symbol _base_CODE_FLASH                  = _base_CODE_FLASH_CM7_0;
define symbol _size_CODE_FLASH                  = _size_CODE_FLASH_CM7_0;


/*============================================================
 * Memory definitions
 *============================================================
 */

define memory mem with size = 4G;

define region SRAM                              = mem:[from _base_SRAM                  size _size_SRAM       ];
define region CODE_FLASH                        = mem:[from _base_CODE_FLASH            size _size_CODE_FLASH ];

/*============================================================
 * Block definitions
 *============================================================
 */
define block CSTACK         with alignment = 8, size = stack_reserve { };
define block HEAP           with expanding size, alignment = 8, minimum size = heap_reserve { };
define block HEAP_STACK     { block HEAP, last block CSTACK };
define block CM0P_RO with size = (_size_CODE_FLASH_CM0P)  { readonly section .cy_m0p_image };
define block CY_SHAREDMEM   with alignment = 32 { section .cy_sharedmem };

/*============================================================
 * Initialization
 *============================================================
 */
initialize by copy { readwrite };
do not initialize  { section .noinit, section .intvec_ram };

/*============================================================
 * Placement
 *============================================================
 */

/* Flash - Cortex-M0+ application image */
place at address (_base_CODE_FLASH_CM0P)  { block CM0P_RO };

/* Link location specific assignment of 'readonly' type sections to either SRAM or CODE_FLASH */
/* Note: .intvec must be the first section in ROM in order for __cm7_vector_base_linker_symbol to be correctly calculated! */

place at start of CODE_FLASH  { section .intvec };
place in          CODE_FLASH  { readonly };

place in          SRAM  { readwrite };
place in          SRAM  { block CY_SHAREDMEM };
place at end   of SRAM  { block HEAP_STACK };

keep {  section .intvec  };
keep {  section .cy_m0p_image  };

/* Following definitions ensure that SRAM will not be touched at all by startup ECC initialization when code is linked to SRAM,
 * use debugger script to initialize the SRAM before downloading the application or adjust below symbols to not include
 * the area of SRAM where "ROM type" sections are linked to
 */
define exported symbol __ecc_init_sram_start_address = start(SRAM);
define exported symbol __ecc_init_sram_end_address   = end(SRAM);

/* EOF */