drv_gpio.h 2.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293
  1. /*
  2. * Copyright (c) 2006-2025, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-08-20 BruceOu the first version
  9. */
  10. #ifndef __DRV_GPIO_H__
  11. #define __DRV_GPIO_H__
  12. #include <rtthread.h>
  13. #include <rtdevice.h>
  14. #include <board.h>
  15. #ifdef __cplusplus
  16. extern "C" {
  17. #endif
  18. #if defined SOC_SERIES_GD32F10x
  19. #include "gd32f10x_gpio.h"
  20. #elif defined SOC_SERIES_GD32F20x
  21. #include "gd32f20x_gpio.h"
  22. #elif defined SOC_SERIES_GD32F30x
  23. #include "gd32f30x_gpio.h"
  24. #elif defined SOC_SERIES_GD32F4xx
  25. #include "gd32f4xx_gpio.h"
  26. #elif defined SOC_SERIES_GD32H7xx
  27. #include "gd32h7xx_gpio.h"
  28. #elif defined SOC_SERIES_GD32H75e
  29. #include "gd32h75e_gpio.h"
  30. #elif defined SOC_SERIES_GD32E50x
  31. #include "gd32e50x_gpio.h"
  32. #elif defined SOC_SERIES_GD32F5xx
  33. #include "gd32f5xx_gpio.h"
  34. #elif defined SOC_SERIES_GD32E23x
  35. #include "gd32e23x_gpio.h"
  36. #endif
  37. #define __GD32_PORT(port) GPIO##port
  38. #if defined SOC_SERIES_GD32F4xx || defined SOC_SERIES_GD32F5xx || defined SOC_SERIES_GD32E23x || defined SOC_SERIES_GD32H75E || defined SOC_SERIES_GD32H7xx
  39. #define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \
  40. GPIO##port, GPIO_PIN_##pin, \
  41. EXTI_SOURCE_GPIO##port, \
  42. EXTI_SOURCE_PIN##pin, \
  43. EXTI_##pin}
  44. #else
  45. #define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \
  46. GPIO##port, GPIO_PIN_##pin, \
  47. GPIO_PORT_SOURCE_GPIO##port, \
  48. GPIO_PIN_SOURCE_##pin}
  49. #endif
  50. #define GD32_PIN_DEFAULT {-1, (rcu_periph_enum)0, 0, 0, 0, 0}
  51. #define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIO_BASE)/(0x0400UL) )) + PIN)
  52. #define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
  53. #define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
  54. #define PIN_GDPORT(pin) (GPIO_BASE + (0x400u * PIN_PORT(pin)))
  55. #define PIN_GDPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
  56. struct pin_index
  57. {
  58. rt_int16_t index;
  59. rcu_periph_enum clk;
  60. rt_uint32_t gpio_periph;
  61. rt_uint32_t pin;
  62. rt_uint8_t port_src;
  63. rt_uint8_t pin_src;
  64. rt_uint32_t exit_line;
  65. };
  66. struct pin_irq_map
  67. {
  68. rt_uint16_t pinbit;
  69. IRQn_Type irqno;
  70. };
  71. int get_pin_config(const char *pin_name, uint32_t *port, uint32_t *pin, rcu_periph_enum *clk);
  72. int pin_alternate_config(const char *alternate, uint32_t *af);
  73. #ifdef __cplusplus
  74. }
  75. #endif
  76. #endif /* __DRV_GPIO_H__ */