rt-thread/bsp/k230/drivers/interdrv/sysctl/sysctl_clock/sysctl_clk.h

/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 * 1. Redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef __SYSCTL_CLK_H__
#define __SYSCTL_CLK_H__

#include <stdint.h>
#include <stdbool.h>

/* See TRM 2.2.4 Table 2-2-9 */
typedef struct sysctl_clk {
    volatile uint32_t cpu0_clk_cfg;             /* 0x00 */
    volatile uint32_t reserved_0;               /* 0x04 */
    volatile uint32_t reserved_1;               /* 0x08 */
    volatile uint32_t reserved_2;               /* 0x0c */
    volatile uint32_t pmu_clk_cfg;              /* 0x10 */
    volatile uint32_t reserved0[1];             /* 0x14 */
    volatile uint32_t hs_clken_cfg;             /* 0x18 */
    volatile uint32_t hs_sdclk_cfg;             /* 0x1c */
    volatile uint32_t hs_spi_cfg;               /* 0x20 */
    volatile uint32_t ls_clken_cfg0;            /* 0x24 */
    volatile uint32_t ls_clken_cfg1;            /* 0x28 */
    volatile uint32_t uart_i2c_clkdiv_cfg;      /* 0x2c */
    volatile uint32_t ls_clkdiv_cfg;            /* 0x30 */
    volatile uint32_t reserved_3;               /* 0x34 */
    volatile uint32_t reserved_4;               /* 0x38 */
    volatile uint32_t reserved_5;               /* 0x3c */
    volatile uint32_t reserved_6;               /* 0x40 */
    volatile uint32_t reserved_7;               /* 0x44 */
    volatile uint32_t reserved1[2];             /* 0x48 0x4c */
    volatile uint32_t sysctl_clken_cfg;         /* 0x50 */
    volatile uint32_t timer_clk_cfg;            /* 0x54 */
    volatile uint32_t sysctl_clk_div_cfg;       /* 0x58 */
    volatile uint32_t shrm_clk_cfg;             /* 0x5c */
    volatile uint32_t ddr_clk_cfg;              /* 0x60 */
    volatile uint32_t reserved_8;               /* 0x64 */
    volatile uint32_t reserved_9;               /* 0x68 */
    volatile uint32_t reserved_10;              /* 0x6c */
    volatile uint32_t reserved_11;              /* 0x70 */
    volatile uint32_t reserved_12;              /* 0x74 */
    volatile uint32_t reserved_13;              /* 0x78 */
    volatile uint32_t reserved2[1];             /* 0x7c */
    volatile uint32_t sec_clk_div;              /* 0x80 */
    volatile uint32_t reserved3[31];            /* 0x84 0x88 0x8c 0x90 0x94 0x98 0x9c 0xa0-0xac 0xb0-0xbc 0xc0-0xcc 0xd0-0xdc 0xe0-0xec 0xf0-0xfc*/
    volatile uint32_t usb_test_clk_div;         /* 0x100 */
    volatile uint32_t dphy_test_clk_div;        /* 0x104 */
    volatile uint32_t spi2axi_clk_div;          /* 0x108 */
} sysctl_clk_t;

/*
 * Clock Tree and clock node table
 *
 * Abbreviations:
 * - D: DIV
 * - G: GATE
 * - M: MUX
 * - fD: fraDIV
 */
typedef enum {
    /*
     * First level is sysctl_boot / sysctrl_root module, which
     * is composed of osc24m, pll[0|1|2|3], pll[0|1|2|3]_[div2|div3|div4] (pllx
     * outputs 4 signals, namely pllx, div2, div3, and div4).
     * Plus timerx_pulse_in, which is an external pulse input through the soc
     * pin (pinmux) as a source of timer clock.
     *
     * - osc24m: fixed-clock
     * - pll[0|1|2|3]: clock generated by PLL
     * - pll[0|1|2|3]_[div2|div3|div4]: fixed-clock
     * - timerx_pulse_in: fixed-clock, maxsize is 1MHz
     *
     * osc24m ---+--> pll0 ---+--------> pll0 ------->+
     *           |            +--(D2)--> pll0_div2 -->|
     *           |            +--(D3)--> pll0_div3 -->|
     *           |            +--(D4)--> pll0_div4 -->|
     *           |                                    |
     *           +--> pll1 ---+--------> pll1 ------->|
     *           |            +--(D2)--> pll1_div2 -->|
     *           |            +--(D3)--> pll1_div3 -->|
     *           |            +--(D4)--> pll1_div4 -->|
     *           |                                    +--> sysctl_clock
     *           +--> pll2 ---+--------> pll2 ------->|
     *           |            +--(D2)--> pll2_div2 -->|
     *           |            +--(D3)--> pll2_div3 -->|
     *           |            +--(D4)--> pll2_div4 -->|
     *           |                                    |
     *           +--> pll3 ---+--------> pll3 ------->|
     *           |            +--(D2)--> pll3_div2 -->|
     *           |            +--(D3)--> pll3_div3 -->|
     *           |            +--(D4)--> pll3_div4 -->|
     *           |                                    |
     *           +----------------------------------->+
     *                                                |
     * timerx_pulse_in ------------------------------>+
     */
    SYSCTL_CLK_ROOT_OSC_IN = 0,       /* 24M */
    SYSCTL_CLK_ROOT_TIMERX_PULSE_IN,  /* 50M */
    SYSCTL_CLK_ROOT_PLL0,             /* 1.6G */
    SYSCTL_CLK_ROOT_PLL0_DIV_2,       /* 800M */
    SYSCTL_CLK_ROOT_PLL0_DIV_3,       /* 533M */
    SYSCTL_CLK_ROOT_PLL0_DIV_4,       /* 400M */
    SYSCTL_CLK_ROOT_PLL1,             /* 2.376G */
    SYSCTL_CLK_ROOT_PLL1_DIV_2,       /* 1.188G */
    SYSCTL_CLK_ROOT_PLL1_DIV_3,       /* 792M */
    SYSCTL_CLK_ROOT_PLL1_DIV_4,       /* 594M */
    SYSCTL_CLK_ROOT_PLL2,             /* 2.667G */
    SYSCTL_CLK_ROOT_PLL2_DIV_2,       /* 1.3335G */
    SYSCTL_CLK_ROOT_PLL2_DIV_3,       /* 889M */
    SYSCTL_CLK_ROOT_PLL2_DIV_4,       /* 666.75M */
    SYSCTL_CLK_ROOT_PLL3,             /* 1.6G */
    SYSCTL_CLK_ROOT_PLL3_DIV_2,       /* 800M */
    SYSCTL_CLK_ROOT_PLL3_DIV_3,       /* 533M */
    SYSCTL_CLK_ROOT_PLL3_DIV_4,       /* 400M */
    SYSCTL_CLK_ROOT_MAX,

    /*
     * Second level is sysctl_clock module, which is composed of several clock sub-trees
     * - CPU0: aclk/pliclk/pclk
     * - pmu system: pclk
     * - HS (High Speed) system: hs/sdx/ssix/usbx
     * - LS (Low Speed) system : ls/uartx/i2cx/gpio/pwm/jamlinkx/audio/adc/codec
     * - System Control (such as wdt, timer, iomux, mailbox): sysctl/wdtx/timer/iomux/mailbox/hdi/stc/ts
     * - Timer: timerx
     * - shrm (share memory) system: shrm/decompress/gsdma/nonai2d/pdma
     * - sec (security) system: aclk/fixclk/pclk
     * - usb test mode: clk480/clk100
     * - dphy dft mode clock: dphy_test_clk
     * - spi2axi clock: aclk
     */

    /*
     * cpu0 clock tree:
     *
     * pll0_div2 --(DG)--> cpu0_src --+--(DG)--> cpu0_plic
     *                                |--(D)---> cpu0_aclk
     *                                +--(G)---> cpu0_noc_ddrcp4
     * pll0_div4 --(DG)--> cpu0_pclk
     */

    /* root node: pll0_div2 */
    SYSCTL_CLK_CPU0_SRC,        /* cpu0 core，defualt 800MHz ---> select pll0_div_2 */
    SYSCTL_CLK_CPU0_PLIC,       /* cpu0 plic clk，400MHz */
    SYSCTL_CLK_CPU0_ACLK,       /* cpu0 axi clk，400MHz */
    SYSCTL_CLK_CPU0_NOC_DDRCP4, /* ddrc axi4clk & noc AXI clock，400MHz */
    /* root node: pll0_div4 */
    SYSCTL_CLK_CPU0_PCLK,       /* cpu0 apb pclk，200MHz */

    /*
     * pmu system clock tree:
     *
     * osc24m -->(G)--> pmu_pclk
     *
     * - pmu_pclk: pmu apb clk gate
     */
    SYSCTL_CLK_PMU_PCLK,

    /*
     * High-Speed system clock tree
     *
     * pll0_div4 --+--(D)--> hs_hclk_high_src --+--(G)----> hs_hclk_high_gate
     *             |                            |
     *             |                            +--(DG)--> hs_hclk_src --+--(G)--> sd0_ahb_gate
     *             |                                                     |--(G)--> sd1_ahb_gate
     *             |                                                     |--(G)--> ssi1_ahb_gate
     *             |                                                     |--(G)--> ssi2_ahb_gate
     *             |                                                     |--(G)--> usb0_ahb_gate
     *             |                                                     +--(G)--> usb1_ahb_gate
     *             |
     *             +--(DG)--> ssi0_axi
     *             |--(DG)--> ssi1
     *             |--(DG)--> ssi2
     *             +--(DG)--> qspi_axi_src --+--(G)--> ssi1_aclk_gate
     *             |                         |
     *             |                         +--(G)--> ssi2_aclk_gate
     *             |
     *             +--(DG)--> sd_card_src --+--(G)--> sd0_card_gate
     *                                      |
     *                                      +--(G)--> sd1_card_gate
     *
     * pll0_div2 --\
     *             (M)--(G)--> ssi0
     * pll2_div4 --/
     *
     *
     * pll2_div4 --(DG)--> sd_axi_src --+--(G)--> sd0_axi_gate
     *                                  |--(G)--> sd1_axi_gate
     *                                  |--(G)--> sd0_base_gate
     *                                  +--(G)--> sd1_base_gate
     *
     *
     *
     * osc24m -----------------------------------------\
     *                                                (M)--+--(G)--> usb0_ref_gate
     * pll0 --(D)--> pll0_div16 --(D)--> usb_ref_50m --/   |
     *                                                     +--(G)--> usb1_ref_gate
     *
     *
     * osc24m --(DG)--> sd_timer_src --+--(G)--> sd0_timer_gate
     *                                 |
     *                                 +--(G)--> sd1_timer_gate
     */

    /* root node: pll0_div4, through hs_hclk_high_src */
    SYSCTL_CLK_HS_HCLK_HIGH_SRC,
    SYSCTL_CLK_HS_HCLK_HIGH_GATE,
    SYSCTL_CLK_HS_HCLK_SRC,
    SYSCTL_CLK_SD0_AHB_GATE,
    SYSCTL_CLK_SD1_AHB_GATE,
    SYSCTL_CLK_USB0_AHB_GATE,
    SYSCTL_CLK_USB1_AHB_GATE,
    SYSCTL_CLK_SSI1_AHB_GATE,
    SYSCTL_CLK_SSI2_AHB_GATE,

    /* root node: pll0_div4 */
    SYSCTL_CLK_SSI0_AXI,
    SYSCTL_CLK_SSI1,
    SYSCTL_CLK_SSI2,
    SYSCTL_CLK_QSPI_AXI_SRC,
    SYSCTL_CLK_SSI1_ACLK_GATE,
    SYSCTL_CLK_SSI2_ACLK_GATE,

    /*root node: pll0_div4, through sd_card_src */
    SYSCTL_CLK_SD_CARD_SRC,
    SYSCTL_CLK_SD0_CARD_GATE,
    SYSCTL_CLK_SD1_CARD_GATE,

    /* root node: pll0_div2 MUX pll2_div4 */
    SYSCTL_CLK_SSI0, /* ospi core clk */

    /* root node: pll2_div4 */
    SYSCTL_CLK_SD_AXI_SRC,
    SYSCTL_CLK_SD0_AXI_GATE,
    SYSCTL_CLK_SD1_AXI_GATE,
    SYSCTL_CLK_SD0_BASE_GATE,
    SYSCTL_CLK_SD1_BASE_GATE,

    /* root node: pll0_div16 */
    SYSCTL_CLK_PLL0_DIV16,
    SYSCTL_CLK_USB_REF_50M, /* usbx reference clk */
    SYSCTL_CLK_USB0_REF_GATE,
    SYSCTL_CLK_USB1_REF_GATE,

    /* root node: osc24m */
    SYSCTL_CLK_SD_TIMER_SRC,
    SYSCTL_CLK_SD0_TIMER_GATE,
    SYSCTL_CLK_SD1_TIMER_GATE,

    /* Low-Speed system clock tree
     *
     *  pll0_div4 --(DG)--+--> ls_apb_src --+--(G) --> uart0_apb_gate
     *                    |                 +--(G) --> uart1_apb_gate
     *                    |                 +--(G) --> uart2_apb_gate
     *                    |                 +--(G) --> uart3_apb_gate
     *                    |                 +--(G) --> uart4_apb_gate
     *                    |                 +--(G) --> i2c0_apb_gate
     *                    |                 +--(G) --> i2c1_apb_gate
     *                    |                 +--(G) --> i2c2_apb_gate
     *                    |                 +--(G) --> i2c3_apb_gate
     *                    |                 +--(G) --> i2c4_apb_gate
     *                    |                 +--(G) --> gpio_apb_gate
     *                    |                 +--(G) --> pwm_apb_gate
     *                    |                 +--(G) --> jamlink0_apb_gate
     *                    |                 +--(G) --> jamlink1_apb_gate
     *                    |                 +--(G) --> jamlink2_apb_gate
     *                    |                 +--(G) --> jamlink3_apb_gate
     *                    |                 +--(G) --> audio_apb_gate
     *                    |                 +--(G) --> adc_apb_gate
     *                    |                 +--(G) --> codec_apb_gate
     *                    |
     *                    +--(DG)--> i2c0_core
     *                    +--(DG)--> i2c1_core
     *                    +--(DG)--> i2c2_core
     *                    +--(DG)--> i2c3_core
     *                    +--(DG)--> i2c4_core
     *                    +--(DG)--> codec_adc
     *                    +--(DG)--> codec_dac
     *                    +--(DG)--> audio_dev
     *                    +--(DG)--> pdm
     *                    +--(DG)--> adc
     *
     * pll0 --(D)--> pll0_div16 --+--(DG)--> uart0_core
     *                            +--(DG)--> uart1_core
     *                            +--(DG)--> uart2_core
     *                            +--(DG)--> uart3_core
     *                            +--(DG)--> uart4_core
     *
     * pll0 --(D)--> pll0_div16 --(D)--> jamlink_CO_div --+--(G)--> jamlink0_CO_gate
     *                                                    +--(G)--> jamlink1_CO_gate
     *                                                    +--(G)--> jamlink2_CO_gate
     *                                                    +--(G)--> jamlink3_CO_gate
     *
     * osc24m --(DG)--> gpio_debounce
     */

    /* root node: pll0_div4, through ls_apb_src */
    SYSCTL_CLK_LS_APB_SRC,
    SYSCTL_CLK_UART0_APB_GATE,
    SYSCTL_CLK_UART1_APB_GATE,
    SYSCTL_CLK_UART2_APB_GATE,
    SYSCTL_CLK_UART3_APB_GATE,
    SYSCTL_CLK_UART4_APB_GATE,
    SYSCTL_CLK_I2C0_APB_GATE,
    SYSCTL_CLK_I2C1_APB_GATE,
    SYSCTL_CLK_I2C2_APB_GATE,
    SYSCTL_CLK_I2C3_APB_GATE,
    SYSCTL_CLK_I2C4_APB_GATE,
    SYSCTL_CLK_GPIO_APB_GATE,
    SYSCTL_CLK_PWM_APB_GATE,
    SYSCTL_CLK_JAMLINK0_APB_GATE,
    SYSCTL_CLK_JAMLINK1_APB_GATE,
    SYSCTL_CLK_JAMLINK2_APB_GATE,
    SYSCTL_CLK_JAMLINK3_APB_GATE,
    SYSCTL_CLK_AUDIO_APB_GATE,
    SYSCTL_CLK_ADC_APB_GATE,
    SYSCTL_CLK_CODEC_APB_GATE,

    /* root node: pll0_div4 */
    SYSCTL_CLK_I2C0_CORE,
    SYSCTL_CLK_I2C1_CORE,
    SYSCTL_CLK_I2C2_CORE,
    SYSCTL_CLK_I2C3_CORE,
    SYSCTL_CLK_I2C4_CORE,
    SYSCTL_CLK_CODEC_ADC,
    SYSCTL_CLK_CODEC_DAC,
    SYSCTL_CLK_AUDIO_DEV,
    SYSCTL_CLK_PDM,
    SYSCTL_CLK_ADC,

    /* root node: pll0_div16 */
    SYSCTL_CLK_UART0_CORE,
    SYSCTL_CLK_UART1_CORE,
    SYSCTL_CLK_UART2_CORE,
    SYSCTL_CLK_UART3_CORE,
    SYSCTL_CLK_UART4_CORE,

    /* root node: pll0_div16, through jamlink_CO_div */
    SYSCTL_CLK_JAMLINK_CO_DIV,
    SYSCTL_CLK_JAMLINK0_CO_GATE,
    SYSCTL_CLK_JAMLINK1_CO_GATE,
    SYSCTL_CLK_JAMLINK2_CO_GATE,
    SYSCTL_CLK_JAMLINK3_CO_GATE,

    /* root node: osc24m */
    SYSCTL_CLK_GOIP_DEBOUNCE,

    /*
     * System Control clock tree
     *
     * pll0_div16 --> sysctl_apb_src --+--(G)--> wdt0_apb_gate
     *                                 +--(G)--> wdt1_apb_gate
     *                                 +--(G)--> timer_apb_gate
     *                                 +--(G)--> iomux_apb_gate
     *                                 +--(G)--> mailbox_apb_gate
     *
     * pll0_div4 --(DG)--> hdi_core
     *
     * pll1_div4 --(DG)--> timestamp
     *
     * osc24m --(D)--> temp_sensor
     *
     * osc24m --+--(DG)--> wdt0
     *          |
     *          +--(DG)--> wdt1
     */

     /* root node: pll0_div16, through sysctl_apb_src */
    SYSCTL_CLK_SYSCTRL_APB_SRC,
    SYSCTL_CLK_WDT0_APB_GATE,
    SYSCTL_CLK_WDT1_APB_GATE,
    SYSCTL_CLK_TIMER_APB_GATE,
    SYSCTL_CLK_IOMUX_APB_GATE,
    SYSCTL_CLK_MAILBOX_APB_GATE,

    /* root node: pll0_div4 */
    SYSCTL_CLK_HDI_CORE,

    /* root node: pll1_div4 */
    SYSCTL_CLK_TIMESTAMP,

    /* root node: osc24m */
    SYSCTL_CLK_TEMP_SENSOR,

    /* root node: osc24m */
    SYSCTL_CLK_WDT0,
    SYSCTL_CLK_WDT1,

    /*
     * timer clock tree
     *
     * pll0_div16 --(D)--> timer0_src --\
     *                                  (M)--(G)-->timer0
     * timerx_pulse_in -----------------/
     *
     * pll0_div16 --(D)--> timer1_src --\
     *                                  (M)--(G)-->timer1
     * timerx_pulse_in -----------------/
     *
     * pll0_div16 --(D)--> timer2_src --\
     *                                  (M)--(G)-->timer2
     * timerx_pulse_in -----------------/
     *
     * pll0_div16 --(D)--> timer3_src --\
     *                                  (M)--(G)-->timer3
     * timerx_pulse_in -----------------/
     *
     * pll0_div16 --(D)--> timer4_src --\
     *                                  (M)--(G)-->timer4
     * timerx_pulse_in -----------------/
     *
     * pll0_div16 --(D)--> timer5_src --\
     *                                  (M)--(G)-->timer5
     * timerx_pulse_in -----------------/
     */

    /* root node: pll0_div16 & timerx_pulse_in */
    SYSCTL_CLK_TIMERX_PULSE_IN,
    SYSCTL_CLK_TIMER0_SRC,
    SYSCTL_CLK_TIMER0,
    SYSCTL_CLK_TIMER1_SRC,
    SYSCTL_CLK_TIMER1,
    SYSCTL_CLK_TIMER2_SRC,
    SYSCTL_CLK_TIMER2,
    SYSCTL_CLK_TIMER3_SRC,
    SYSCTL_CLK_TIMER3,
    SYSCTL_CLK_TIMER4_SRC,
    SYSCTL_CLK_TIMER4,
    SYSCTL_CLK_TIMER5_SRC,
    SYSCTL_CLK_TIMER5,

    /*
     * shrm system clock tree
     *
     * pll0_div2 --\
     *             (M)--(G)--> shrm_src --+--(D)--> shrm_div2 --(G)--> shrm_axi_slave
     * pll3_div2 --/                      |
     *                                    +--(G)--> decompress_axi
     *
     * pll0_div4 -->(DG)--> shrm_apb
     *
     * pll0_div4 -->(G)--> shrm_axi_src --+--(G)--> gsdma_axi_gate
     *                                    +--(G)--> nonai2d_axi_gate
     *                                    +--(G)--> peri_dma_axi_gate
     */

    /* root node: pll0_div2 & pll3_div2 */
    SYSCTL_CLK_SHRM_SRC,
    SYSCTL_CLK_SHRM_DIV2,
    SYSCTL_CLK_SHRM_AXIS_SLAVE,
    SYSCTL_CLK_DECOMPRESS_AXI,

    /* root node: pll0_div4 */
    SYSCTL_CLK_SHRM_APB,

    /* root node: pll0_div4, through shrm_axi_src */
    SYSCTL_CLK_SHRM_AXI_SRC,
    SYSCTL_CLK_GSDMA_AXI_GATE,
    SYSCTL_CLK_NONAI2D_AXI_GATE,
    SYSCTL_CLK_PERI_DMA_AXI_GATE,

    /*
     * Security system clock tree
     *
     * pll0_div4 --(DG)--> sec_apb
     *
     * pll1_div4 --+--(DG)--> sec_fix
     *             |
     *             +--(DG)--> sec_axi
     */

    /* root node: pll0_div4 */
    SYSCTL_CLK_SEC_APB,

    /* root node: pll1_div4 */
    SYSCTL_CLK_SEC_FIX,
    SYSCTL_CLK_SEC_AXI,

    /*
     * usb test mode clock tree
     *
     * pll1 --(DG)--> usb_480m
     *
     * pll0_div4 --(DG)--> usb_100m
     */

    /* root node: pll1 */
    SYSCTL_CLK_USB_480M,

    /* root node: pll0_div4 */
    SYSCTL_CLK_USB_100M,

    /*
     * dphy dft mode clock tree
     *
     * pll0 --(DG)--> dphy_dft_mode
     */

    /* root node: pll0 */
    SYSCTL_CLK_DPHY_DFT_MODE,

    /*
     * spi2axi clock tree
     *
     * pll0_div4 --(DG)--> spi2axi_axi
     */

    /* root node: pll0_div4 */
    SYSCTL_CLK_SPI2AXI_AXI,

    SYSCTL_CLK_NODE_MAX,
} sysctl_clk_node_e;

#define SYSCTL_READ_ENABLE    (1 << 0)
#define SYSCTL_READ_DISABLE   (0 << 0)
#define SYSCTL_WRITE_ENABLE   (1 << 1)
#define SYSCTL_WRITE_DISABLE  (0 << 1)

/*
 * API for root clock. 24M, PLL0-3, these 5 clocks are root clocks
 * It is assumed here that the big core has read and write permissions to the
 * root clock, so the properties of clk are not judged in these APIs,
 * because these APIs are only for the root clock.
 */

/*
 * Get the bypass status of the PLL.
 * If it is bypas, the PLL output is 24M OSC clock.
 */
bool sysctl_boot_get_root_clk_bypass(sysctl_clk_node_e clk);
void sysctl_boot_set_root_clk_bypass(sysctl_clk_node_e clk, bool enable);

/* Enable pll, enable 24M clock&pll */
bool sysctl_boot_get_root_clk_en(sysctl_clk_node_e clk);
void sysctl_boot_set_root_clk_en(sysctl_clk_node_e clk, bool enable);

/* Get the phase-locked loop lock status */
bool sysctl_boot_get_root_clk_lock(sysctl_clk_node_e clk);

/* Get the root clock frequency */
uint32_t sysctl_boot_get_root_clk_freq(sysctl_clk_node_e clk);

/*
 * Set the PLL clock frequency
 * The formula for setting the PLL clock frequency is:
 * pll_out_freq = (double)OSC_CLOCK_FREQ_24M * (double)(fbdiv+1) / (double)(refdiv+1) / (double)(outdiv+1)
 */
bool sysctl_boot_set_root_clk_freq(sysctl_clk_node_e clk, uint32_t fbdiv, uint32_t refdiv, uint32_t outdiv, uint32_t bwadj);

/*
 * API for trunk and leaf nodes in the clock tree, i.e. clocks other than the five root clocks.
 */

/*
 * Set the leaf node clock source on the clock tree.
 * Please set it according to the clock tree.
 * Many clock nodes have only one clock source, so the setting will return false.
 */
bool sysctl_clk_set_leaf_parent(sysctl_clk_node_e leaf, sysctl_clk_node_e parent);

/* Get the clock source of the leaf node in the clock tree */
sysctl_clk_node_e sysctl_clk_get_leaf_parent(sysctl_clk_node_e leaf);

/*
 * Set the clock node enable.
 * Note: only set the enable of this clock node, and do not set the enable of
 * the upstream clock.
 * Difference from Linux kernel: Linux kernel clock framework will automatically
 * set the enable of the upstream clock. The test code does not have kernel
 * framework, so only the enable of the clock of this node is set.
 */
void sysctl_clk_set_leaf_en(sysctl_clk_node_e leaf, bool enable);

/* Get the enable status of this clock node */
bool sysctl_clk_get_leaf_en(sysctl_clk_node_e leaf);

/* Set the frequency division factor of this clock node */
bool sysctl_clk_set_leaf_div(sysctl_clk_node_e leaf, uint32_t numerator, uint32_t denominator);

/* Get the frequency division coefficient of this clock node */
double sysctl_clk_get_leaf_div(sysctl_clk_node_e leaf);

/*
 * Calculate clock freqency.
 * This API searches the entire clock path, calculates the frequency division
 * at each level starting from the clock source, and finally obtains the
 * current clock frequency.
 */
uint32_t sysctl_clk_get_leaf_freq(sysctl_clk_node_e leaf);

#endif /* __SYSCTL_CLK_H__ */