drv_spi.c 4.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164
  1. /*
  2. * Copyright (c) 2006-2024 RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2024-08-1 hywing The first version for MCXA
  9. */
  10. #include "rtdevice.h"
  11. #include "drv_spi.h"
  12. #include "fsl_lpspi.h"
  13. #ifdef RT_USING_SPI
  14. #define DBG_TAG "drv.spi"
  15. #define DBG_LVL DBG_INFO
  16. #include <rtdbg.h>
  17. enum
  18. {
  19. #ifdef BSP_USING_SPI0
  20. SPI0_INDEX,
  21. #endif
  22. #ifdef BSP_USING_SPI1
  23. SPI1_INDEX,
  24. #endif
  25. };
  26. struct lpc_spi
  27. {
  28. struct rt_spi_bus parent;
  29. LPSPI_Type *LPSPIx;
  30. clock_attach_id_t clock_attach_id;
  31. clock_div_name_t clock_div_name;
  32. clock_name_t clock_name;
  33. rt_sem_t sem;
  34. char *name;
  35. };
  36. static struct lpc_spi lpc_obj[] =
  37. {
  38. #ifdef BSP_USING_SPI0
  39. {
  40. .LPSPIx = LPSPI0,
  41. #if (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN))
  42. kFRO_LF_DIV_to_LPSPI0,
  43. #else
  44. .clock_attach_id = kFRO12M_to_LPSPI0,
  45. #endif
  46. .clock_div_name = kCLOCK_DivLPSPI0,
  47. .clock_name = kCLOCK_Fro12M,
  48. .name = "spi0",
  49. },
  50. #endif
  51. #ifdef BSP_USING_SPI1
  52. {
  53. .LPSPIx = LPSPI1,
  54. #if (defined(CPU_MCXA346VLH) || defined(CPU_MCXA346VLL) || defined(CPU_MCXA346VLQ) || defined(CPU_MCXA346VPN))
  55. kFRO_LF_DIV_to_LPSPI1,
  56. #else
  57. .clock_attach_id = kFRO12M_to_LPSPI1,
  58. #endif
  59. .clock_div_name = kCLOCK_DivLPSPI1,
  60. .clock_name = kCLOCK_Fro12M,
  61. .name = "spi1",
  62. },
  63. #endif
  64. };
  65. rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin)
  66. {
  67. struct rt_spi_device *spi_device = rt_malloc(sizeof(struct rt_spi_device));
  68. if (!spi_device)
  69. {
  70. return -RT_ENOMEM;
  71. }
  72. return rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, pin, NULL);
  73. }
  74. static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
  75. {
  76. return RT_EOK;
  77. }
  78. static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  79. {
  80. lpspi_transfer_t transfer = {0};
  81. status_t status;
  82. RT_ASSERT(device != RT_NULL);
  83. RT_ASSERT(device->bus != RT_NULL);
  84. RT_ASSERT(device->bus->parent.user_data != RT_NULL);
  85. struct lpc_spi *spi = device->bus->parent.user_data;
  86. if (message->cs_take)
  87. {
  88. rt_pin_write(device->cs_pin, PIN_LOW);
  89. }
  90. transfer.dataSize = message->length;
  91. transfer.rxData = (uint8_t *)(message->recv_buf);
  92. transfer.txData = (uint8_t *)(message->send_buf);
  93. transfer.configFlags = kLPSPI_MasterPcs0;
  94. // Use blocking transfer instead of DMA
  95. status = LPSPI_MasterTransferBlocking(spi->LPSPIx, &transfer);
  96. if (message->cs_release)
  97. {
  98. rt_pin_write(device->cs_pin, PIN_HIGH);
  99. }
  100. if (status != kStatus_Success)
  101. {
  102. return 0; // Transfer failed
  103. }
  104. return message->length;
  105. }
  106. static struct rt_spi_ops lpc_spi_ops =
  107. {
  108. .configure = spi_configure,
  109. .xfer = spixfer
  110. };
  111. int rt_hw_spi_init(void)
  112. {
  113. int i;
  114. for (i = 0; i < ARRAY_SIZE(lpc_obj); i++)
  115. {
  116. CLOCK_SetClockDiv(lpc_obj[i].clock_div_name, 1u);
  117. CLOCK_AttachClk(lpc_obj[i].clock_attach_id);
  118. lpc_obj[i].parent.parent.user_data = &lpc_obj[i];
  119. lpc_obj[i].sem = rt_sem_create("sem_spi", 0, RT_IPC_FLAG_FIFO);
  120. lpspi_master_config_t masterConfig;
  121. LPSPI_MasterGetDefaultConfig(&masterConfig);
  122. masterConfig.baudRate = 10 * 1000 * 1000;
  123. masterConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
  124. masterConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
  125. masterConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.baudRate * 1U;
  126. LPSPI_MasterInit(lpc_obj[i].LPSPIx, &masterConfig, CLOCK_GetFreq(lpc_obj[i].clock_name));
  127. rt_spi_bus_register(&lpc_obj[i].parent, lpc_obj[i].name, &lpc_spi_ops);
  128. }
  129. return RT_EOK;
  130. }
  131. INIT_DEVICE_EXPORT(rt_hw_spi_init);
  132. #endif /* RT_USING_SPI */