drv_i2c.c 12 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Email: opensource_embedded@phytium.com.cn
  7. *
  8. * Change Logs:
  9. * Date Author Notes
  10. * 2023-10-23 zhangyan first version
  11. *
  12. */
  13. #include "rtconfig.h"
  14. #include <rtdevice.h>
  15. #include <string.h>
  16. #define LOG_TAG "i2c_drv"
  17. #include "drv_log.h"
  18. #include "drv_i2c.h"
  19. #include "fi2c.h"
  20. #include "fi2c_hw.h"
  21. #include "fio_mux.h"
  22. #include "drivers/dev_i2c.h"
  23. #include "fparameters.h"
  24. #ifdef RT_USING_SMART
  25. #include <ioremap.h>
  26. #endif
  27. /*Please define the length of the mem_addr of the device*/
  28. #ifndef FI2C_DEVICE_MEMADDR_LEN
  29. #define FI2C_DEVICE_MEMADDR_LEN 2
  30. #endif
  31. #define FI2C_DEFAULT_ID 0
  32. #if defined(I2C_USE_MIO)
  33. #include "fmio_hw.h"
  34. #include "fmio.h"
  35. static FMioCtrl mio_handle;
  36. #endif
  37. struct phytium_i2c_bus
  38. {
  39. struct rt_i2c_bus_device device;
  40. FI2c i2c_handle;
  41. struct rt_i2c_msg *msg;
  42. const char *name;
  43. };
  44. #if defined(I2C_USE_CONTROLLER)
  45. static rt_err_t i2c_config(struct phytium_i2c_bus *i2c_bus)
  46. {
  47. RT_ASSERT(i2c_bus);
  48. FI2cConfig input_cfg;
  49. const FI2cConfig *config_p = NULL;
  50. FI2c *instance_p = &i2c_bus->i2c_handle;
  51. FError ret = FI2C_SUCCESS;
  52. /* Lookup default configs by instance id */
  53. config_p = FI2cLookupConfig(instance_p->config.instance_id);
  54. input_cfg = *config_p;
  55. #ifdef RT_USING_SMART
  56. input_cfg.base_addr = (uintptr)rt_ioremap((void *)input_cfg.base_addr, 0x1000);
  57. #endif
  58. input_cfg.speed_rate = FI2C_SPEED_STANDARD_RATE;
  59. input_cfg.work_mode = FI2C_MASTER;
  60. FI2cDeInitialize(&i2c_bus->i2c_handle);
  61. /* Initialization */
  62. ret = FI2cCfgInitialize(instance_p, &input_cfg);
  63. if (ret != FI2C_SUCCESS)
  64. {
  65. LOG_E("Init master I2c failed, ret: 0x%x", ret);
  66. return -RT_ERROR;
  67. }
  68. ret = FI2cSetAddress(&i2c_bus->i2c_handle, FI2C_MASTER, i2c_bus->i2c_handle.config.slave_addr);
  69. if (FI2C_SUCCESS != ret)
  70. {
  71. return -RT_ERROR;
  72. }
  73. ret = FI2cSetSpeed(&i2c_bus->i2c_handle, FI2C_SPEED_STANDARD_RATE, TRUE);
  74. if (FI2C_SUCCESS != ret)
  75. {
  76. return -RT_ERROR;
  77. }
  78. return RT_EOK;
  79. }
  80. #endif
  81. #if defined(I2C_USE_MIO)
  82. static rt_err_t i2c_mio_config(struct phytium_i2c_bus *i2c_bus)
  83. {
  84. RT_ASSERT(i2c_bus);
  85. FError ret = FI2C_SUCCESS;
  86. FI2cConfig i2c_config;
  87. FI2c *instance_p = &i2c_bus->i2c_handle;
  88. FIOPadSetMioMux(instance_p->config.instance_id);
  89. mio_handle.config = *FMioLookupConfig(instance_p->config.instance_id);
  90. #ifdef RT_USING_SMART
  91. mio_handle.config.func_base_addr = (uintptr)rt_ioremap((void *)mio_handle.config.func_base_addr, 0x1200);
  92. mio_handle.config.mio_base_addr = (uintptr)rt_ioremap((void *)mio_handle.config.mio_base_addr, 0x200);
  93. #endif
  94. ret = FMioFuncInit(&mio_handle, FMIO_FUNC_SET_I2C);
  95. if (ret != FT_SUCCESS)
  96. {
  97. LOG_E("MIO initialize error.");
  98. return -RT_ERROR;
  99. }
  100. /* Modify i2c configuration */
  101. rt_memset(&i2c_config, 0, sizeof(i2c_config));
  102. i2c_config.base_addr = FMioFuncGetAddress(&mio_handle, FMIO_FUNC_SET_I2C);
  103. i2c_config.irq_num = FMioFuncGetIrqNum(&mio_handle, FMIO_FUNC_SET_I2C);
  104. i2c_config.irq_prority = 0;
  105. i2c_config.ref_clk_hz = FMIO_CLK_FREQ_HZ;
  106. i2c_config.work_mode = FI2C_MASTER;
  107. i2c_config.use_7bit_addr = TRUE;
  108. i2c_config.speed_rate = FI2C_SPEED_STANDARD_RATE;
  109. i2c_config.auto_calc = TRUE;
  110. ret = FI2cCfgInitialize(instance_p, &i2c_config);
  111. if (FI2C_SUCCESS != ret)
  112. {
  113. LOG_E("Init mio master failed, ret: 0x%x", ret);
  114. return -RT_ERROR;
  115. }
  116. ret = FI2cSetAddress(instance_p, FI2C_MASTER, instance_p->config.slave_addr);
  117. if (FI2C_SUCCESS != ret)
  118. {
  119. return -RT_ERROR;
  120. }
  121. ret = FI2cSetSpeed(instance_p, FI2C_SPEED_STANDARD_RATE, TRUE);
  122. if (FI2C_SUCCESS != ret)
  123. {
  124. return -RT_ERROR;
  125. }
  126. mio_handle.is_ready = 0;
  127. rt_memset(&mio_handle, 0, sizeof(mio_handle));
  128. return RT_EOK;
  129. }
  130. #endif
  131. static rt_err_t phytium_i2c_set_speed(struct phytium_i2c_bus *i2c_bus, rt_uint32_t speed)
  132. {
  133. RT_ASSERT(i2c_bus);
  134. u32 ret;
  135. ret = FI2cSetSpeed(&i2c_bus->i2c_handle, speed, TRUE);
  136. if (ret != FI2C_SUCCESS)
  137. {
  138. LOG_E("Set i2c speed failed!\n");
  139. return -RT_ERROR;
  140. }
  141. return RT_EOK;
  142. }
  143. static rt_err_t i2c_bus_control(struct rt_i2c_bus_device *device, int cmd, void *args)
  144. {
  145. RT_ASSERT(device);
  146. struct phytium_i2c_bus *i2c_bus;
  147. i2c_bus = (struct phytium_i2c_bus *)(device);
  148. FI2cConfig *config_p;
  149. switch (cmd)
  150. {
  151. case RT_I2C_DEV_CTRL_CLK:
  152. phytium_i2c_set_speed(i2c_bus, *(rt_uint32_t *)args);
  153. break;
  154. case RT_I2C_DEV_CTRL_10BIT:
  155. config_p = &i2c_bus->i2c_handle.config;
  156. config_p->use_7bit_addr = FALSE;
  157. FI2cCfgInitialize(&i2c_bus->i2c_handle, config_p);
  158. break;
  159. default:
  160. return -RT_EIO;
  161. }
  162. return RT_EOK;
  163. }
  164. static rt_ssize_t i2c_master_xfer(struct rt_i2c_bus_device *device, struct rt_i2c_msg msgs[], rt_uint32_t num)
  165. {
  166. RT_ASSERT(device);
  167. u32 ret;
  168. struct rt_i2c_msg *pmsg;
  169. rt_ssize_t i;
  170. struct phytium_i2c_bus *i2c_bus;
  171. i2c_bus = (struct phytium_i2c_bus *)(device);
  172. uintptr mem_addr = 0;
  173. for (i = 0; i < num; i++)
  174. {
  175. pmsg = &msgs[i];
  176. for (u32 j = 0; j <FI2C_DEVICE_MEMADDR_LEN; j++)
  177. {
  178. mem_addr |= msgs[i].buf[j] << (8 * (FI2C_DEVICE_MEMADDR_LEN - 1 - j));
  179. }
  180. i2c_bus->i2c_handle.config.slave_addr = pmsg->addr;
  181. if (pmsg->flags & RT_I2C_RD)
  182. {
  183. rt_thread_delay(100);
  184. ret = FI2cMasterReadPoll(&i2c_bus->i2c_handle, mem_addr, FI2C_DEVICE_MEMADDR_LEN, &pmsg->buf[0], pmsg->len - FI2C_DEVICE_MEMADDR_LEN);
  185. if (ret != FI2C_SUCCESS)
  186. {
  187. LOG_E("I2C master read failed!\n");
  188. return -RT_ERROR;
  189. }
  190. }
  191. else
  192. {
  193. rt_thread_delay(100);
  194. ret = FI2cMasterWritePoll(&i2c_bus->i2c_handle, mem_addr, FI2C_DEVICE_MEMADDR_LEN, &pmsg->buf[FI2C_DEVICE_MEMADDR_LEN], pmsg->len - FI2C_DEVICE_MEMADDR_LEN);
  195. if (ret != FI2C_SUCCESS)
  196. {
  197. LOG_E("I2C master write failed!\n");
  198. return -RT_ERROR;
  199. }
  200. }
  201. }
  202. return i;
  203. }
  204. static const struct rt_i2c_bus_device_ops _i2c_ops =
  205. {
  206. .master_xfer = i2c_master_xfer,
  207. .slave_xfer = NULL,
  208. .i2c_bus_control = i2c_bus_control
  209. };
  210. #if defined(I2C_USE_CONTROLLER)
  211. static int i2c_controller_init(struct phytium_i2c_bus *i2c_controller_bus)
  212. {
  213. rt_err_t ret = RT_EOK;
  214. ret = i2c_config(i2c_controller_bus);
  215. if (ret != RT_EOK)
  216. {
  217. LOG_E("I2C config failed.\n");
  218. return -RT_ERROR;
  219. }
  220. i2c_controller_bus->device.ops = &_i2c_ops;
  221. ret = rt_i2c_bus_device_register(&i2c_controller_bus->device, i2c_controller_bus->name);
  222. RT_ASSERT(RT_EOK == ret);
  223. LOG_D("I2C bus reg success.\n");
  224. return ret;
  225. }
  226. #endif
  227. #if defined(I2C_USE_MIO)
  228. static int i2c_mio_init(struct phytium_i2c_bus *i2c_mio_bus)
  229. {
  230. rt_err_t ret = RT_EOK;
  231. ret = i2c_mio_config(i2c_mio_bus);
  232. if (ret != RT_EOK)
  233. {
  234. LOG_E("I2C mio config failed.\n");
  235. return -RT_ERROR;
  236. }
  237. i2c_mio_bus->device.ops = &_i2c_ops;
  238. ret = rt_i2c_bus_device_register(&i2c_mio_bus->device, i2c_mio_bus->name);
  239. RT_ASSERT(RT_EOK == ret);
  240. LOG_D("I2C mio bus reg success.\n");
  241. return ret;
  242. }
  243. #endif
  244. #if defined(RT_USING_I2C0)
  245. static struct phytium_i2c_bus i2c_controller0_bus;
  246. #endif
  247. #if defined(RT_USING_I2C1)
  248. static struct phytium_i2c_bus i2c_controller1_bus;
  249. #endif
  250. #if defined(RT_USING_I2C2)
  251. static struct phytium_i2c_bus i2c_controller2_bus;
  252. #endif
  253. #if defined(RT_USING_I2C3)
  254. static struct phytium_i2c_bus i2c_controller3_bus;
  255. #endif
  256. #if defined(RT_USING_MIO0)
  257. static struct phytium_i2c_bus i2c_mio0_bus;
  258. #endif
  259. #if defined(RT_USING_MIO1)
  260. static struct phytium_i2c_bus i2c_mio1_bus;
  261. #endif
  262. #if defined(RT_USING_MIO2)
  263. static struct phytium_i2c_bus i2c_mio2_bus;
  264. #endif
  265. #if defined(RT_USING_MIO3)
  266. static struct phytium_i2c_bus i2c_mio3_bus;
  267. #endif
  268. #if defined(RT_USING_MIO4)
  269. static struct phytium_i2c_bus i2c_mio4_bus;
  270. #endif
  271. #if defined(RT_USING_MIO5)
  272. static struct phytium_i2c_bus i2c_mio5_bus;
  273. #endif
  274. #if defined(RT_USING_MIO6)
  275. static struct phytium_i2c_bus i2c_mio6_bus;
  276. #endif
  277. #if defined(RT_USING_MIO7)
  278. static struct phytium_i2c_bus i2c_mio7_bus;
  279. #endif
  280. #if defined(RT_USING_MIO8)
  281. static struct phytium_i2c_bus i2c_mio8_bus;
  282. #endif
  283. #if defined(RT_USING_MIO9)
  284. static struct phytium_i2c_bus i2c_mio9_bus;
  285. #endif
  286. #if defined(RT_USING_MIO10)
  287. static struct phytium_i2c_bus i2c_mio10_bus;
  288. #endif
  289. #if defined(RT_USING_MIO11)
  290. static struct phytium_i2c_bus i2c_mio11_bus;
  291. #endif
  292. #if defined(RT_USING_MIO12)
  293. static struct phytium_i2c_bus i2c_mio12_bus;
  294. #endif
  295. #if defined(RT_USING_MIO13)
  296. static struct phytium_i2c_bus i2c_mio13_bus;
  297. #endif
  298. #if defined(RT_USING_MIO14)
  299. static struct phytium_i2c_bus i2c_mio14_bus;
  300. #endif
  301. #if defined(RT_USING_MIO15)
  302. static struct phytium_i2c_bus i2c_mio15_bus;
  303. #endif
  304. int rt_hw_i2c_init(void)
  305. {
  306. #if defined(RT_USING_I2C0)
  307. i2c_controller0_bus.name = "I2C0";
  308. i2c_controller0_bus.i2c_handle.config.instance_id = FI2C0_ID;
  309. i2c_controller_init(&i2c_controller0_bus);
  310. #endif
  311. #if defined(RT_USING_I2C1)
  312. i2c_controller1_bus.name = "I2C1";
  313. i2c_controller1_bus.i2c_handle.config.instance_id = FI2C1_ID;
  314. i2c_controller_init(&i2c_controller1_bus);
  315. #endif
  316. #if defined(RT_USING_I2C2)
  317. i2c_controller2_bus.name = "I2C2";
  318. i2c_controller2_bus.i2c_handle.config.instance_id = FI2C2_ID;
  319. i2c_controller_init(&i2c_controller2_bus);
  320. #endif
  321. #if defined(RT_USING_I2C3)
  322. i2c_controller3_bus.name = "I2C3";
  323. i2c_controller3_bus.i2c_handle.config.instance_id = FI2C3_ID;
  324. i2c_controller_init(&i2c_controller3_bus);
  325. #endif
  326. #if defined(RT_USING_MIO0)
  327. i2c_mio0_bus.name = "MIO0";
  328. i2c_mio0_bus.i2c_handle.config.instance_id = FMIO0_ID;
  329. i2c_mio_init(&i2c_mio0_bus);
  330. #endif
  331. #if defined(RT_USING_MIO1)
  332. i2c_mio1_bus.name = "MIO1";
  333. i2c_mio1_bus.i2c_handle.config.instance_id = FMIO1_ID;
  334. i2c_mio_init(&i2c_mio1_bus);
  335. #endif
  336. #if defined(RT_USING_MIO2)
  337. i2c_mio2_bus.name = "MIO2";
  338. i2c_mio2_bus.i2c_handle.config.instance_id = FMIO2_ID;
  339. i2c_mio_init(&i2c_mio2_bus);
  340. #endif
  341. #if defined(RT_USING_MIO3)
  342. i2c_mio3_bus.name = "MIO3";
  343. i2c_mio3_bus.i2c_handle.config.instance_id = FMIO3_ID;
  344. i2c_mio_init(&i2c_mio3_bus);
  345. #endif
  346. #if defined(RT_USING_MIO4)
  347. i2c_mio4_bus.name = "MIO4";
  348. i2c_mio4_bus.i2c_handle.config.instance_id = FMIO4_ID;
  349. i2c_mio_init(&i2c_mio4_bus);
  350. #endif
  351. #if defined(RT_USING_MIO5)
  352. i2c_mio5_bus.name = "MIO5";
  353. i2c_mio5_bus.i2c_handle.config.instance_id = FMIO5_ID;
  354. i2c_mio_init(&i2c_mio5_bus);
  355. #endif
  356. #if defined(RT_USING_MIO6)
  357. i2c_mio6_bus.name = "MIO6";
  358. i2c_mio6_bus.i2c_handle.config.instance_id = FMIO6_ID;
  359. i2c_mio_init(&i2c_mio6_bus);
  360. #endif
  361. #if defined(RT_USING_MIO7)
  362. i2c_mio7_bus.name = "MIO2";
  363. i2c_mio7_bus.i2c_handle.config.instance_id = FMIO7_ID;
  364. i2c_mio_init(&i2c_mio7_bus);
  365. #endif
  366. #if defined(RT_USING_MIO8)
  367. i2c_mio8_bus.name = "MIO8";
  368. i2c_mio8_bus.i2c_handle.config.instance_id = FMIO8_ID;
  369. i2c_mio_init(&i2c_mio8_bus);
  370. #endif
  371. #if defined(RT_USING_MIO9)
  372. i2c_mio9_bus.name = "MIO9";
  373. i2c_mio9_bus.i2c_handle.config.instance_id = FMIO9_ID;
  374. i2c_mio_init(&i2c_mio9_bus);
  375. #endif
  376. #if defined(RT_USING_MIO10)
  377. i2c_mio10_bus.name = "MIO10";
  378. i2c_mio10_bus.i2c_handle.config.instance_id = FMIO10_ID;
  379. i2c_mio_init(&i2c_mio10_bus);
  380. #endif
  381. #if defined(RT_USING_MIO11)
  382. i2c_mio11_bus.name = "MIO11";
  383. i2c_mio11_bus.i2c_handle.config.instance_id = FMIO11_ID;
  384. i2c_mio_init(&i2c_mio11_bus);
  385. #endif
  386. #if defined(RT_USING_MIO12)
  387. i2c_mio12_bus.name = "MIO12";
  388. i2c_mio12_bus.i2c_handle.config.instance_id = FMIO12_ID;
  389. i2c_mio_init(&i2c_mio12_bus);
  390. #endif
  391. #if defined(RT_USING_MIO13)
  392. i2c_mio13_bus.name = "MIO13";
  393. i2c_mio13_bus.i2c_handle.config.instance_id = FMIO13_ID;
  394. i2c_mio_init(&i2c_mio13_bus);
  395. #endif
  396. #if defined(RT_USING_MIO14)
  397. i2c_mio14_bus.name = "MIO14";
  398. i2c_mio14_bus.i2c_handle.config.instance_id = FMIO14_ID;
  399. i2c_mio_init(&i2c_mio14_bus);
  400. #endif
  401. #if defined(RT_USING_MIO15)
  402. i2c_mio15_bus.name = "MIO15";
  403. i2c_mio15_bus.i2c_handle.config.instance_id = FMIO15_ID;
  404. i2c_mio_init(&i2c_mio15_bus);
  405. #endif
  406. return 0;
  407. }
  408. INIT_DEVICE_EXPORT(rt_hw_i2c_init);