drv_i2c_msg.c 7.1 KB

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  1. /*
  2. * Copyright (c) 2006-2023, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Email: opensource_embedded@phytium.com.cn
  7. *
  8. * Change Logs:
  9. * Date Author Notes
  10. * 2023-10-23 zhangyan first version
  11. *
  12. */
  13. #include "rtconfig.h"
  14. #include <rtdevice.h>
  15. #include <string.h>
  16. #define LOG_TAG "i2c_drv_msg"
  17. #include "drv_log.h"
  18. #include "drv_i2c_msg.h"
  19. #include "fi2c_msg.h"
  20. #include "fi2c_msg_hw.h"
  21. #include "fi2c_msg_master.h"
  22. #include "fio_mux.h"
  23. #include "drivers/dev_i2c.h"
  24. #include "fparameters.h"
  25. #ifdef RT_USING_SMART
  26. #include <ioremap.h>
  27. #endif
  28. /*Please define the length of the mem_addr of the device*/
  29. #ifndef FI2C_DEVICE_MEMADDR_LEN
  30. #define FI2C_DEVICE_MEMADDR_LEN 2
  31. #endif
  32. #define I2C_TIMEOUT_MS 1000
  33. struct phytium_i2c_msg_bus
  34. {
  35. struct rt_i2c_bus_device device;
  36. FI2cMsgCtrl i2c_handle;
  37. struct rt_i2c_msg *msg;
  38. const char *name;
  39. };
  40. static rt_err_t i2c_msg_config(struct phytium_i2c_msg_bus *i2c_bus)
  41. {
  42. RT_ASSERT(i2c_bus);
  43. FI2cMsgConfig input_cfg;
  44. const FI2cMsgConfig *config_p = NULL;
  45. FI2cMsgCtrl *instance_p = &i2c_bus->i2c_handle;
  46. rt_uint32_t cpu_id = rt_hw_cpu_id();
  47. FError ret = FI2C_MSG_SUCCESS;
  48. FIOPadSetI2CMux(instance_p->config.instance_id);
  49. /* Lookup default configs by instance id */
  50. config_p = FI2cMsgLookupConfig(instance_p->config.instance_id);
  51. input_cfg = *config_p;
  52. #ifdef RT_USING_SMART
  53. input_cfg.msg.shmem = (uintptr)rt_ioremap((void *)input_cfg.msg.shmem, 0x1000);
  54. input_cfg.msg.regfile= (uintptr)rt_ioremap((void *)input_cfg.msg.regfile, 0x1000);
  55. #endif
  56. /* Initialization */
  57. ret = FI2cMsgCfgInitialize(instance_p, &input_cfg);
  58. if (ret != FI2C_MSG_SUCCESS)
  59. {
  60. LOG_E("FI2cMsgCfgInitialize failed, ret = %d", ret);
  61. return -RT_ERROR;
  62. }
  63. instance_p->speed_mode = FI2C_STANDARD_SPEED;
  64. instance_p->timeout_ms = I2C_TIMEOUT_MS;
  65. instance_p->clk_clock_frequency = FI2C_CLK_FREQ_HZ;
  66. rt_hw_interrupt_set_target_cpus(instance_p->config.irq_num, cpu_id);
  67. rt_hw_interrupt_set_priority(instance_p->config.irq_num, instance_p->config.irq_prority);
  68. rt_hw_interrupt_install(instance_p->config.irq_num, FI2cMsgMasterRegfileIsr, instance_p, i2c_bus->name);
  69. rt_hw_interrupt_umask(instance_p->config.irq_num);
  70. ret = FI2cMsgMasterVirtProbe(instance_p);
  71. if (ret != FI2C_MSG_SUCCESS)
  72. {
  73. LOG_E("FI2cMsgMasterVirtProbe failed, ret = %d", ret);
  74. return ret;
  75. }
  76. return RT_EOK;
  77. }
  78. static rt_err_t phytium_i2c_set_speed(struct phytium_i2c_msg_bus *i2c_bus, rt_uint32_t speed)
  79. {
  80. RT_ASSERT(i2c_bus);
  81. FI2cMsgCtrl *instance_p = &i2c_bus->i2c_handle;
  82. switch (speed)
  83. {
  84. case FI2C_SPEED_STANDARD_RATE:
  85. instance_p->speed_mode = FI2C_STANDARD_SPEED;
  86. break;
  87. case FI2C_SPEED_FAST_RATE:
  88. instance_p->speed_mode = FI2C_FAST_SPEED;
  89. break;
  90. case FI2C_SPEED_HIGH_RATE:
  91. instance_p->speed_mode = FI2C_HIGH_SPEED;
  92. break;
  93. default:
  94. return -RT_EIO;
  95. }
  96. FI2cMsgSetBusSpeed(instance_p, instance_p->speed_mode, TRUE);
  97. return RT_EOK;
  98. }
  99. static rt_err_t i2c_msg_bus_control(struct rt_i2c_bus_device *device, int cmd, void *args)
  100. {
  101. RT_ASSERT(device);
  102. struct phytium_i2c_msg_bus *i2c_bus;
  103. i2c_bus = (struct phytium_i2c_msg_bus *)(device);
  104. FI2cMsgConfig *config_p;
  105. switch (cmd)
  106. {
  107. case RT_I2C_DEV_CTRL_CLK:
  108. phytium_i2c_set_speed(i2c_bus, *(rt_uint32_t *)args);
  109. break;
  110. case RT_I2C_DEV_CTRL_10BIT:
  111. break;
  112. default:
  113. return -RT_EIO;
  114. }
  115. return RT_EOK;
  116. }
  117. static rt_ssize_t i2c_msg_master_xfer(struct rt_i2c_bus_device *device, struct rt_i2c_msg msgs[], rt_uint32_t num)
  118. {
  119. RT_ASSERT(device);
  120. u32 ret;
  121. struct rt_i2c_msg *pmsg;
  122. rt_ssize_t i;
  123. struct phytium_i2c_msg_bus *i2c_bus;
  124. i2c_bus = (struct phytium_i2c_msg_bus *)(device);
  125. FI2cMsgCtrl *instance_p = &i2c_bus->i2c_handle;
  126. for (i = 0; i < num; i++)
  127. {
  128. pmsg = &msgs[i];
  129. if (pmsg->flags & RT_I2C_RD)
  130. {
  131. /*When performing a read operation, first write to the input memaddr, and then read*/
  132. struct FI2cMsg msg[2];
  133. msg[0].addr = pmsg->addr;
  134. msg[0].flags = FI2C_MSG_WD;
  135. msg[0].len = FI2C_DEVICE_MEMADDR_LEN;
  136. msg[0].buf = pmsg->buf;
  137. msg[1].addr = pmsg->addr;
  138. msg[1].flags = FI2C_MSG_RD;
  139. msg[1].len = pmsg->len;
  140. msg[1].buf = pmsg->buf;
  141. ret = FI2cMsgMasterVirtXfer(instance_p, msg, 2);
  142. if (ret != FI2C_MSG_SUCCESS)
  143. {
  144. LOG_E("FI2cMsgMasterVirtProbe read failed, ret = %d", ret);
  145. }
  146. }
  147. else
  148. {
  149. struct FI2cMsg msg;
  150. msg.addr = pmsg->addr;
  151. msg.buf = pmsg->buf;
  152. msg.len = pmsg->len;
  153. msg.flags = FI2C_MSG_WD;
  154. ret = FI2cMsgMasterVirtXfer(instance_p, &msg, 1); /*num = 1 ,只需发送一次写命令*/
  155. if (ret != FI2C_MSG_SUCCESS)
  156. {
  157. LOG_E("FI2cMsgMasterVirtProbe write failed, ret = %d", ret);
  158. }
  159. }
  160. }
  161. return i;
  162. }
  163. static const struct rt_i2c_bus_device_ops _i2c_ops =
  164. {
  165. .master_xfer = i2c_msg_master_xfer,
  166. .slave_xfer = NULL,
  167. .i2c_bus_control = i2c_msg_bus_control
  168. };
  169. static int i2c_msg_controller_init(struct phytium_i2c_msg_bus *i2c_controller_bus)
  170. {
  171. rt_err_t ret = RT_EOK;
  172. ret = i2c_msg_config(i2c_controller_bus);
  173. if (ret != RT_EOK)
  174. {
  175. LOG_E("I2C config failed.\n");
  176. return -RT_ERROR;
  177. }
  178. i2c_controller_bus->device.ops = &_i2c_ops;
  179. ret = rt_i2c_bus_device_register(&i2c_controller_bus->device, i2c_controller_bus->name);
  180. RT_ASSERT(RT_EOK == ret);
  181. LOG_D("I2C bus reg success.\n");
  182. return ret;
  183. }
  184. #if defined(RT_USING_I2C0_MSG)
  185. static struct phytium_i2c_msg_bus i2c_msg_controller0_bus;
  186. #endif
  187. #if defined(RT_USING_I2C1_MSG)
  188. static struct phytium_i2c_msg_bus i2c_msg_controller1_bus;
  189. #endif
  190. #if defined(RT_USING_I2C2_MSG)
  191. static struct phytium_i2c_msg_bus i2c_msg_controller2_bus;
  192. #endif
  193. #if defined(RT_USING_I2C3_MSG)
  194. static struct phytium_i2c_msg_bus i2c_msg_controller3_bus;
  195. #endif
  196. int rt_hw_i2c_msg_init(void)
  197. {
  198. #if defined(RT_USING_I2C0_MSG)
  199. i2c_msg_controller0_bus.name = "I2C0_MSG";
  200. i2c_msg_controller0_bus.i2c_handle.config.instance_id = FI2C0_MSG_ID;
  201. i2c_msg_controller_init(&i2c_msg_controller0_bus);
  202. #endif
  203. #if defined(RT_USING_I2C1_MSG)
  204. i2c_msg_controller1_bus.name = "I2C1_MSG";
  205. i2c_msg_controller1_bus.i2c_handle.config.instance_id = FI2C1_MSG_ID;
  206. i2c_msg_controller_init(&i2c_msg_controller1_bus);
  207. #endif
  208. #if defined(RT_USING_I2C2_MSG)
  209. i2c_msg_controller2_bus.name = "I2C2_MSG";
  210. i2c_msg_controller2_bus.i2c_handle.config.instance_id = FI2C2_MSG_ID;
  211. i2c_msg_controller_init(&i2c_msg_controller2_bus);
  212. #endif
  213. #if defined(RT_USING_I2C3_MSG)
  214. i2c_msg_controller3_bus.name = "I2C3_MSG";
  215. i2c_msg_controller3_bus.i2c_handle.config.instance_id = FI2C3_MSG_ID;
  216. i2c_msg_controller_init(&i2c_msg_controller3_bus);
  217. #endif
  218. return 0;
  219. }
  220. INIT_DEVICE_EXPORT(rt_hw_i2c_msg_init);