drv_fdcan.c 24 KB

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  1. /*
  2. * Copyright (c) 2006-2018, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2020-02-24 heyuan the first version
  9. * 2020-08-17 malongwei Fix something
  10. * 2025-10-27 pandafeng Fix some bugs
  11. */
  12. #include "drv_fdcan.h"
  13. #if defined(RT_USING_CAN) && defined(RT_CAN_USING_CANFD)
  14. #if defined(BSP_USING_FDCAN1) || defined(BSP_USING_FDCAN2)
  15. //#define DRV_DEBUG
  16. #define LOG_TAG "drv_fdcan"
  17. #include <drv_log.h>
  18. #ifdef BSP_USING_FDCAN1
  19. static stm32_fdcan_t st_DrvCan1=
  20. {
  21. .name = "fdcan1",
  22. .fdcanHandle.Instance = FDCAN1,
  23. };
  24. #endif
  25. #ifdef BSP_USING_FDCAN2
  26. static stm32_fdcan_t st_DrvCan2=
  27. {
  28. .name = "fdcan2",
  29. .fdcanHandle.Instance = FDCAN2,
  30. };
  31. #endif
  32. /* 40MHz CAN clock */
  33. static const stm32_fdcan_timing_t st_FDCAN_ArbTiming[] =
  34. {
  35. {CAN1MBaud, {1, 29, 10, 8, 0}}, /* 1Mbps */
  36. {CAN800kBaud, {1, 37, 12, 8, 0}}, /* 800kbps */
  37. {CAN500kBaud, {1, 59, 20, 8, 0}}, /* 500kbps */
  38. {CAN250kBaud, {2, 63, 16, 8, 0}}, /* 250kbps */
  39. {CAN125kBaud, {5, 55, 8, 8, 0}}, /* 125kbps */
  40. {CAN100kBaud, {8, 41, 8, 8, 0}}, /* 100kbps */
  41. {CAN50kBaud, {16, 41, 8, 8, 0}}, /* 50kbps */
  42. {CAN20kBaud, {40,41,8,8,0}}, /* 20kbps */
  43. {CAN10kBaud, {100,31,8,8,0}} /* 10kbps */
  44. };
  45. /* 40MHz CAN clock */
  46. static const stm32_fdcan_timing_t st_FDCAN_DataTiming[] =
  47. {
  48. {CAN1MBaud * 8, {1, 3, 1, 1, 0}}, /* 8Mbps */
  49. {CAN500kBaud *8, {1, 7, 2, 1, 0}}, /* 4Mbps */
  50. {CAN250kBaud * 8, {4, 3, 1, 1, 0}}, /* 2Mbps */
  51. {CAN125kBaud *8, {1, 31, 8, 1, 0}}, /* 1Mkbps */
  52. {CAN100kBaud*8, {2, 19, 5, 1, 0}}, /* 800kbps */
  53. {CAN50kBaud *8, {5, 15, 4, 1, 0}}, /* 400kbps */
  54. };
  55. /**
  56. * @brief Convert CAN-FD frame length to DLC (Data Length Code)
  57. *
  58. * CAN-FD DLC mapping (length → DLC):
  59. * Length 0~8 -> DLC 0~8
  60. * Length 9~12 -> DLC 9
  61. * Length 13~16 -> DLC 10
  62. * Length 17~20 -> DLC 11
  63. * Length 21~24 -> DLC 12
  64. * Length 25~32 -> DLC 13
  65. * Length 33~48 -> DLC 14
  66. * Length 49~64 -> DLC 15
  67. *
  68. * @param len Frame length in bytes (0~64)
  69. * @return DLC code (0~15)
  70. */
  71. uint8_t length_to_dlc(uint8_t len) {
  72. return (len <= 8) ? len :
  73. (len <= 12) ? 9 :
  74. (len <= 16) ? 10 :
  75. (len <= 20) ? 11 :
  76. (len <= 24) ? 12 :
  77. (len <= 32) ? 13 :
  78. (len <= 48) ? 14 : 15;
  79. }
  80. /**
  81. * @brief 获取 FDCAN 仲裁段波特率配置索引
  82. */
  83. static uint32_t _inline_get_ArbBaudIndex(uint32_t baud_rate)
  84. {
  85. uint32_t len = sizeof(st_FDCAN_ArbTiming) / sizeof(st_FDCAN_ArbTiming[0]);
  86. for (uint32_t i = 0; i < len; i++)
  87. {
  88. if (st_FDCAN_ArbTiming[i].u32Baudrate == baud_rate)
  89. return i;
  90. }
  91. return -1;
  92. }
  93. /**
  94. * @brief Get the index of the FDCAN data segment bitrate configuration.
  95. *
  96. * @param baud_rate The desired data phase baud rate (in bps).
  97. * @retval uint32_t Index of the matching data segment configuration.
  98. * Returns -1 if no matching configuration is found.
  99. */
  100. static uint32_t _inline_get_DataBaudIndex(uint32_t baud_rate)
  101. {
  102. uint32_t len = sizeof(st_FDCAN_DataTiming) / sizeof(st_FDCAN_DataTiming[0]);
  103. for (uint32_t i = 0; i < len; i++)
  104. {
  105. if (st_FDCAN_DataTiming[i].u32Baudrate == baud_rate)
  106. return i;
  107. }
  108. return -1;
  109. }
  110. static rt_err_t _inline_can_config(struct rt_can_device *can, struct can_configure *cfg)
  111. {
  112. stm32_fdcan_t *pdrv_can;
  113. rt_uint32_t tmp_u32Index;
  114. RT_ASSERT(can);
  115. RT_ASSERT(cfg);
  116. pdrv_can = (stm32_fdcan_t *)can->parent.user_data;
  117. RT_ASSERT(pdrv_can);
  118. pdrv_can->fdcanHandle.Init.FrameFormat = FDCAN_FRAME_FD_BRS;
  119. pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_NORMAL;
  120. pdrv_can->fdcanHandle.Init.AutoRetransmission = ENABLE;
  121. pdrv_can->fdcanHandle.Init.TransmitPause = DISABLE;
  122. pdrv_can->fdcanHandle.Init.ProtocolException = ENABLE;
  123. switch (cfg->mode)
  124. {
  125. case RT_CAN_MODE_NORMAL:
  126. pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_NORMAL;
  127. break;
  128. case RT_CAN_MODE_LISTEN:
  129. pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_BUS_MONITORING;
  130. break;
  131. case RT_CAN_MODE_LOOPBACK:
  132. pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_INTERNAL_LOOPBACK;
  133. break;
  134. default:
  135. pdrv_can->fdcanHandle.Init.Mode = FDCAN_MODE_NORMAL;
  136. break;
  137. }
  138. uint32_t arb_idx = _inline_get_ArbBaudIndex(cfg->baud_rate);
  139. if (arb_idx == (uint32_t)-1)
  140. {
  141. LOG_E("not support %d baudrate", cfg->baud_rate);
  142. return -RT_ERROR;
  143. }
  144. /* FDCAN arbitration segment */
  145. pdrv_can->fdcanHandle.Init.NominalPrescaler = st_FDCAN_ArbTiming[arb_idx].cam_bit_timing.prescaler;
  146. pdrv_can->fdcanHandle.Init.NominalSyncJumpWidth = st_FDCAN_ArbTiming[arb_idx].cam_bit_timing.num_sjw;
  147. pdrv_can->fdcanHandle.Init.NominalTimeSeg1 = st_FDCAN_ArbTiming[arb_idx].cam_bit_timing.num_seg1;
  148. pdrv_can->fdcanHandle.Init.NominalTimeSeg2 = st_FDCAN_ArbTiming[arb_idx].cam_bit_timing.num_seg2;
  149. #ifdef RT_CAN_USING_CANFD
  150. if(cfg->enable_canfd) {
  151. uint32_t data_idx = _inline_get_DataBaudIndex(cfg->baud_rate_fd);
  152. if (data_idx == (uint32_t)-1)
  153. {
  154. LOG_E("not support %d baudrate", cfg->baud_rate_fd);
  155. return -RT_ERROR;
  156. }
  157. /* 数据段 */
  158. pdrv_can->fdcanHandle.Init.DataPrescaler = st_FDCAN_DataTiming[data_idx].cam_bit_timing.prescaler;
  159. pdrv_can->fdcanHandle.Init.DataSyncJumpWidth = st_FDCAN_DataTiming[data_idx].cam_bit_timing.num_sjw;
  160. pdrv_can->fdcanHandle.Init.DataTimeSeg1 = st_FDCAN_DataTiming[data_idx].cam_bit_timing.num_seg1;
  161. pdrv_can->fdcanHandle.Init.DataTimeSeg2 = st_FDCAN_DataTiming[data_idx].cam_bit_timing.num_seg2;
  162. }
  163. #endif
  164. /* Configure Message RAM */
  165. if(pdrv_can->fdcanHandle.Instance == FDCAN1)
  166. {
  167. pdrv_can->fdcanHandle.Init.MessageRAMOffset = 0;
  168. }
  169. else
  170. {
  171. pdrv_can->fdcanHandle.Init.MessageRAMOffset = 1280;
  172. }
  173. pdrv_can->fdcanHandle.Init.StdFiltersNbr = 2;
  174. pdrv_can->fdcanHandle.Init.ExtFiltersNbr = 2;
  175. pdrv_can->fdcanHandle.Init.RxFifo0ElmtsNbr = 1;
  176. pdrv_can->fdcanHandle.Init.RxFifo0ElmtSize = FDCAN_DATA_BYTES_64;
  177. pdrv_can->fdcanHandle.Init.RxFifo1ElmtsNbr = 0;
  178. pdrv_can->fdcanHandle.Init.RxFifo1ElmtSize = FDCAN_DATA_BYTES_64;
  179. pdrv_can->fdcanHandle.Init.RxBuffersNbr = 0;
  180. pdrv_can->fdcanHandle.Init.RxBufferSize = FDCAN_DATA_BYTES_64;
  181. pdrv_can->fdcanHandle.Init.TxEventsNbr = 0;
  182. pdrv_can->fdcanHandle.Init.TxBuffersNbr = 3;
  183. pdrv_can->fdcanHandle.Init.TxFifoQueueElmtsNbr = 0;
  184. pdrv_can->fdcanHandle.Init.TxFifoQueueMode = FDCAN_TX_FIFO_OPERATION;
  185. pdrv_can->fdcanHandle.Init.TxElmtSize = FDCAN_DATA_BYTES_64;
  186. if (HAL_FDCAN_Init(&pdrv_can->fdcanHandle) != HAL_OK)
  187. {
  188. return -RT_ERROR;
  189. }
  190. /* default filter config */
  191. HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle , &pdrv_can->FilterConfig);
  192. /*init fdcan tx header*/
  193. pdrv_can->TxHeader.Identifier = 0x000000;
  194. pdrv_can->TxHeader.IdType = FDCAN_EXTENDED_ID;
  195. pdrv_can->TxHeader.TxFrameType = FDCAN_DATA_FRAME;
  196. pdrv_can->TxHeader.DataLength = FDCAN_DLC_BYTES_8;
  197. pdrv_can->TxHeader.ErrorStateIndicator = FDCAN_ESI_ACTIVE;
  198. pdrv_can->TxHeader.BitRateSwitch = FDCAN_BRS_OFF;
  199. pdrv_can->TxHeader.FDFormat = FDCAN_CLASSIC_CAN;
  200. pdrv_can->TxHeader.TxEventFifoControl = FDCAN_NO_TX_EVENTS;
  201. pdrv_can->TxHeader.MessageMarker = 0;
  202. /* can start */
  203. HAL_FDCAN_Start(&pdrv_can->fdcanHandle);
  204. return RT_EOK;
  205. }
  206. static rt_err_t _inline_can_filter_config(stm32_fdcan_t *pdrv_can,struct rt_can_filter_config *puser_can_filter_config)
  207. {
  208. int tmp_i32IndexCount;
  209. RT_ASSERT(pdrv_can);
  210. RT_ASSERT(puser_can_filter_config);
  211. /* get default filter */
  212. for (tmp_i32IndexCount = 0; tmp_i32IndexCount < puser_can_filter_config->count; tmp_i32IndexCount++)
  213. {
  214. pdrv_can->FilterConfig.FilterIndex = puser_can_filter_config->items[tmp_i32IndexCount].hdr_bank;
  215. pdrv_can->FilterConfig.FilterID1 = puser_can_filter_config->items[tmp_i32IndexCount].id;
  216. pdrv_can->FilterConfig.FilterID2 = puser_can_filter_config->items[tmp_i32IndexCount].mask;
  217. if(puser_can_filter_config->items[tmp_i32IndexCount].ide == RT_CAN_EXTID)
  218. {
  219. pdrv_can->FilterConfig.IdType = FDCAN_EXTENDED_ID;
  220. }
  221. else
  222. {
  223. pdrv_can->FilterConfig.IdType = FDCAN_STANDARD_ID;
  224. }
  225. pdrv_can->FilterConfig.FilterType = FDCAN_FILTER_MASK;
  226. pdrv_can->FilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
  227. if(HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle , &pdrv_can->FilterConfig) != HAL_OK)
  228. {
  229. return -RT_ERROR;
  230. }
  231. }
  232. return RT_EOK;
  233. }
  234. static rt_err_t _inline_can_control(struct rt_can_device *can, int cmd, void *arg)
  235. {
  236. rt_uint32_t argval;
  237. stm32_fdcan_t *pdrv_can;
  238. struct rt_can_filter_config *filter_cfg;
  239. RT_ASSERT(can != RT_NULL);
  240. pdrv_can = (stm32_fdcan_t *)can->parent.user_data;
  241. RT_ASSERT(pdrv_can != RT_NULL);
  242. switch (cmd) {
  243. case RT_DEVICE_CTRL_CLR_INT:
  244. argval = (rt_uint32_t) arg;
  245. if (argval == RT_DEVICE_FLAG_INT_RX) {
  246. HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE);
  247. } else if (argval == RT_DEVICE_FLAG_INT_TX) {
  248. HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_FIFO_EMPTY);
  249. HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE);
  250. } else if (argval == RT_DEVICE_CAN_INT_ERR) {
  251. HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_WARNING);
  252. HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_PASSIVE);
  253. HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_LOGGING_OVERFLOW);
  254. HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_BUS_OFF);
  255. HAL_FDCAN_DeactivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ARB_PROTOCOL_ERROR);
  256. }
  257. break;
  258. case RT_DEVICE_CTRL_SET_INT:
  259. argval = (rt_uint32_t) arg;
  260. if (argval == RT_DEVICE_FLAG_INT_RX) {
  261. HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE,
  262. FDCAN_INTERRUPT_LINE0);
  263. HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_RX_FIFO0_NEW_MESSAGE, 0);
  264. if (FDCAN1 == pdrv_can->fdcanHandle.Instance) {
  265. HAL_NVIC_SetPriority(FDCAN1_IT0_IRQn, 0, 1);
  266. HAL_NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
  267. } else {
  268. HAL_NVIC_SetPriority(FDCAN2_IT0_IRQn, 0, 1);
  269. HAL_NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
  270. }
  271. } else if (argval == RT_DEVICE_FLAG_INT_TX) {
  272. HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_INTERRUPT_LINE1);
  273. HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_TX_BUFFER0);
  274. HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_TX_BUFFER1);
  275. HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_TX_COMPLETE, FDCAN_TX_BUFFER2);
  276. if (FDCAN1 == pdrv_can->fdcanHandle.Instance) {
  277. HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 0, 2);
  278. HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
  279. } else {
  280. HAL_NVIC_SetPriority(FDCAN2_IT1_IRQn, 0, 2);
  281. HAL_NVIC_EnableIRQ(FDCAN2_IT1_IRQn);
  282. }
  283. } else if (argval == RT_DEVICE_CAN_INT_ERR) {
  284. HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_BUS_OFF, FDCAN_INTERRUPT_LINE1);
  285. HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_WARNING, FDCAN_INTERRUPT_LINE1);
  286. HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_PASSIVE, FDCAN_INTERRUPT_LINE1);
  287. HAL_FDCAN_ConfigInterruptLines(&pdrv_can->fdcanHandle, FDCAN_IT_ARB_PROTOCOL_ERROR,
  288. FDCAN_INTERRUPT_LINE1);
  289. HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_BUS_OFF, 0);
  290. HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_WARNING, 0);
  291. HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ERROR_PASSIVE, 0);
  292. HAL_FDCAN_ActivateNotification(&pdrv_can->fdcanHandle, FDCAN_IT_ARB_PROTOCOL_ERROR, 0);
  293. if (FDCAN1 == pdrv_can->fdcanHandle.Instance) {
  294. HAL_NVIC_SetPriority(FDCAN1_IT1_IRQn, 0, 2);
  295. HAL_NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
  296. } else {
  297. HAL_NVIC_SetPriority(FDCAN2_IT1_IRQn, 0, 2);
  298. HAL_NVIC_EnableIRQ(FDCAN2_IT1_IRQn);
  299. }
  300. }
  301. break;
  302. case RT_CAN_CMD_SET_FILTER:
  303. if (RT_NULL == arg) {
  304. /* default filter config */
  305. HAL_FDCAN_ConfigFilter(&pdrv_can->fdcanHandle, &pdrv_can->FilterConfig);
  306. } else {
  307. filter_cfg = (struct rt_can_filter_config *) arg;
  308. _inline_can_filter_config(pdrv_can, filter_cfg);
  309. }
  310. break;
  311. case RT_CAN_CMD_SET_MODE:
  312. argval = (rt_uint32_t) arg;
  313. if (argval != RT_CAN_MODE_NORMAL &&
  314. argval != RT_CAN_MODE_LISTEN &&
  315. argval != RT_CAN_MODE_LOOPBACK &&
  316. argval != RT_CAN_MODE_LOOPBACKANLISTEN) {
  317. return -RT_ERROR;
  318. }
  319. if (argval != pdrv_can->device.config.mode) {
  320. pdrv_can->device.config.mode = argval;
  321. return _inline_can_config(&pdrv_can->device, &pdrv_can->device.config);
  322. }
  323. break;
  324. case RT_CAN_CMD_SET_BAUD:
  325. argval = (rt_uint32_t) arg;
  326. uint32_t arb_idx = _inline_get_ArbBaudIndex(argval);
  327. if (arb_idx == (uint32_t) -1) {
  328. return -RT_ERROR;
  329. }
  330. if (argval != pdrv_can->device.config.baud_rate) {
  331. pdrv_can->device.config.baud_rate = argval;
  332. return _inline_can_config(&pdrv_can->device, &pdrv_can->device.config);
  333. }
  334. break;
  335. case RT_CAN_CMD_SET_PRIV:
  336. argval = (rt_uint32_t) arg;
  337. if (argval != RT_CAN_MODE_PRIV &&
  338. argval != RT_CAN_MODE_NOPRIV) {
  339. return -RT_ERROR;
  340. }
  341. if (argval != pdrv_can->device.config.privmode) {
  342. pdrv_can->device.config.privmode = argval;
  343. return RT_EOK;
  344. }
  345. break;
  346. case RT_CAN_CMD_GET_STATUS: {
  347. rt_uint32_t tmp_u32Errcount;
  348. rt_uint32_t tmp_u32status;
  349. tmp_u32Errcount = pdrv_can->fdcanHandle.Instance->ECR;
  350. tmp_u32status = pdrv_can->fdcanHandle.Instance->PSR;
  351. pdrv_can->device.status.rcverrcnt = (tmp_u32Errcount >> 8) & 0x000000ff;
  352. pdrv_can->device.status.snderrcnt = (tmp_u32Errcount) & 0x000000ff;
  353. pdrv_can->device.status.lasterrtype = tmp_u32status & 0x000000007;
  354. rt_memcpy(arg, &pdrv_can->device.status, sizeof(pdrv_can->device.status));
  355. }
  356. break;
  357. case RT_CAN_CMD_SET_BAUD_FD: {
  358. argval = (rt_uint32_t) arg;
  359. uint32_t data_idx = _inline_get_DataBaudIndex(argval);
  360. if (data_idx == (uint32_t) -1) {
  361. return -RT_ERROR;
  362. }
  363. if (argval != pdrv_can->device.config.baud_rate_fd) {
  364. pdrv_can->device.config.baud_rate_fd = argval;
  365. return _inline_can_config(&pdrv_can->device, &pdrv_can->device.config);
  366. }
  367. }
  368. }
  369. return RT_EOK;
  370. }
  371. static int _inline_can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
  372. {
  373. stm32_fdcan_t *pdrv_can;
  374. struct rt_can_msg *pmsg;
  375. uint32_t tmp_u32DataLen;
  376. RT_ASSERT(can);
  377. RT_ASSERT(buf);
  378. pdrv_can = (stm32_fdcan_t *)can->parent.user_data;
  379. RT_ASSERT(pdrv_can);
  380. pmsg = (struct rt_can_msg *) buf;
  381. /* Check the parameters */
  382. tmp_u32DataLen = length_to_dlc( pmsg->len);
  383. if(pmsg->ide == RT_CAN_EXTID)
  384. {
  385. pdrv_can->TxHeader.IdType = FDCAN_EXTENDED_ID;
  386. }
  387. else
  388. {
  389. pdrv_can->TxHeader.IdType = FDCAN_STANDARD_ID;
  390. }
  391. if (RT_CAN_DTR == pmsg->rtr)
  392. {
  393. pdrv_can->TxHeader.TxFrameType = FDCAN_DATA_FRAME;
  394. }
  395. else
  396. {
  397. pdrv_can->TxHeader.TxFrameType = FDCAN_REMOTE_FRAME;
  398. }
  399. pdrv_can->TxHeader.Identifier = pmsg->id;
  400. pdrv_can->TxHeader.DataLength = tmp_u32DataLen;
  401. if (pmsg->fd_frame == 1)
  402. {
  403. pdrv_can->TxHeader.FDFormat = FDCAN_FD_CAN;
  404. }
  405. else {
  406. pdrv_can->TxHeader.FDFormat = FDCAN_CLASSIC_CAN;
  407. }
  408. if(HAL_FDCAN_AddMessageToTxBuffer(&pdrv_can->fdcanHandle, &pdrv_can->TxHeader, pmsg->data, FDCAN_TX_BUFFER0 + box_num) != HAL_OK)
  409. {
  410. return -RT_ERROR;
  411. }
  412. else
  413. {
  414. /* Request transmission */
  415. HAL_FDCAN_EnableTxBufferRequest(&pdrv_can->fdcanHandle,FDCAN_TX_BUFFER0+box_num);
  416. return RT_EOK;
  417. }
  418. }
  419. static int _inline_can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
  420. {
  421. struct rt_can_msg *pmsg;
  422. stm32_fdcan_t *pdrv_can;
  423. RT_ASSERT(can);
  424. RT_ASSERT(buf);
  425. pdrv_can = (stm32_fdcan_t *)can->parent.user_data;
  426. pmsg = (struct rt_can_msg *) buf;
  427. if(HAL_FDCAN_GetRxMessage(&pdrv_can->fdcanHandle,FDCAN_RX_FIFO0+fifo, &pdrv_can->RxHeader, pmsg->data) != HAL_OK)
  428. {
  429. return 0;
  430. }
  431. else
  432. {
  433. if(pdrv_can->RxHeader.IdType == FDCAN_EXTENDED_ID)
  434. {
  435. pmsg->ide = RT_CAN_EXTID;
  436. }
  437. else
  438. {
  439. pmsg->ide = RT_CAN_STDID;
  440. }
  441. if(pdrv_can->RxHeader.RxFrameType == FDCAN_DATA_FRAME)
  442. {
  443. pmsg->rtr = RT_CAN_DTR;
  444. }
  445. else
  446. {
  447. pmsg->rtr = RT_CAN_RTR;
  448. }
  449. pmsg->id = pdrv_can->RxHeader.Identifier;
  450. pmsg->len = pdrv_can->RxHeader.DataLength;
  451. pmsg->hdr_index = pdrv_can->RxHeader.FilterIndex;
  452. #ifdef RT_CAN_USING_CANFD
  453. pmsg->fd_frame = (pdrv_can->RxHeader.FDFormat >> 16) && 0x20;
  454. pmsg->brs = (pdrv_can->RxHeader.BitRateSwitch >> 16) && 0x10;
  455. #endif
  456. return sizeof(struct rt_can_msg);
  457. }
  458. }
  459. static const struct rt_can_ops _can_ops =
  460. {
  461. _inline_can_config,
  462. _inline_can_control,
  463. _inline_can_sendmsg,
  464. _inline_can_recvmsg,
  465. };
  466. void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs)
  467. {
  468. if((RxFifo0ITs & FDCAN_IT_RX_FIFO0_NEW_MESSAGE) != RESET)
  469. {
  470. if(hfdcan->Instance == FDCAN1)
  471. {
  472. #ifdef BSP_USING_FDCAN1
  473. //CAN1
  474. /* Retreive Rx messages from RX FIFO0 */
  475. rt_hw_can_isr(&st_DrvCan1.device, RT_CAN_EVENT_RX_IND | 0 << 8);
  476. #endif
  477. }
  478. else
  479. {
  480. #ifdef BSP_USING_FDCAN2
  481. //CAN2
  482. /* Retreive Rx messages from RX FIFO0 */
  483. rt_hw_can_isr(&st_DrvCan2.device, RT_CAN_EVENT_RX_IND | 0 << 8);
  484. #endif
  485. }
  486. }
  487. }
  488. void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes)
  489. {
  490. if(hfdcan->Instance == FDCAN1)
  491. {
  492. #ifdef BSP_USING_FDCAN1
  493. //can1
  494. rt_hw_can_isr(&st_DrvCan1.device, RT_CAN_EVENT_TX_DONE | ((BufferIndexes-1) << 8));
  495. #endif
  496. }
  497. else
  498. {
  499. #ifdef BSP_USING_FDCAN2
  500. //can2
  501. rt_hw_can_isr(&st_DrvCan2.device, RT_CAN_EVENT_TX_DONE | ((BufferIndexes-1) << 8));
  502. #endif
  503. }
  504. }
  505. void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan)
  506. {
  507. if(hfdcan->Instance == FDCAN1)
  508. {
  509. #ifdef BSP_USING_FDCAN1
  510. rt_hw_can_isr(&st_DrvCan1.device, RT_CAN_EVENT_TX_DONE);
  511. #endif
  512. }
  513. else
  514. {
  515. #ifdef BSP_USING_FDCAN2
  516. rt_hw_can_isr(&st_DrvCan2.device, RT_CAN_EVENT_TX_DONE);
  517. #endif
  518. }
  519. }
  520. void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan)
  521. {
  522. rt_uint32_t tmp_u32Errcount;
  523. rt_uint32_t tmp_u32status;
  524. uint32_t ret = HAL_FDCAN_GetError(hfdcan);
  525. if(hfdcan->Instance == FDCAN1)
  526. {
  527. #ifdef BSP_USING_FDCAN1
  528. if((ret & FDCAN_IT_ARB_PROTOCOL_ERROR) &&
  529. (hfdcan->Instance->CCCR & FDCAN_CCCR_INIT_Msk))
  530. {
  531. //hfdcan->Instance->CCCR |= FDCAN_CCCR_CCE_Msk;
  532. hfdcan->Instance->CCCR &= ~FDCAN_CCCR_INIT_Msk;
  533. st_DrvCan1.device.status.errcode = 0xff;
  534. }
  535. else
  536. {
  537. tmp_u32Errcount = st_DrvCan1.fdcanHandle.Instance->ECR;
  538. tmp_u32status = st_DrvCan1.fdcanHandle.Instance->PSR;
  539. st_DrvCan1.device.status.rcverrcnt = (tmp_u32Errcount>>8)&0x000000ff;
  540. st_DrvCan1.device.status.snderrcnt = (tmp_u32Errcount)&0x000000ff;
  541. st_DrvCan1.device.status.lasterrtype = tmp_u32status&0x000000007;
  542. rt_hw_can_isr(&st_DrvCan1.device, RT_CAN_EVENT_TX_FAIL);
  543. }
  544. #endif /*BSP_USING_FDCAN1*/
  545. }
  546. else
  547. {
  548. #ifdef BSP_USING_FDCAN2
  549. if( (ret & FDCAN_IT_ARB_PROTOCOL_ERROR) &&
  550. (hfdcan->Instance->CCCR & FDCAN_CCCR_INIT_Msk))
  551. {
  552. //hfdcan->Instance->CCCR |= FDCAN_CCCR_CCE_Msk;
  553. hfdcan->Instance->CCCR &= ~FDCAN_CCCR_INIT_Msk;
  554. st_DrvCan2.device.status.errcode = 0xff;
  555. }
  556. else
  557. {
  558. //can2
  559. tmp_u32Errcount = st_DrvCan2.fdcanHandle.Instance->ECR;
  560. tmp_u32status = st_DrvCan2.fdcanHandle.Instance->PSR;
  561. st_DrvCan2.device.status.rcverrcnt = (tmp_u32Errcount>>8)&0x000000ff;
  562. st_DrvCan2.device.status.snderrcnt = (tmp_u32Errcount)&0x000000ff;
  563. st_DrvCan2.device.status.lasterrtype = tmp_u32status&0x000000007;
  564. rt_hw_can_isr(&st_DrvCan2.device, RT_CAN_EVENT_TX_FAIL);
  565. }
  566. #endif /*BSP_USING_FDCAN2*/
  567. }
  568. }
  569. #ifdef BSP_USING_FDCAN1
  570. void FDCAN1_IT0_IRQHandler(void) /* FDCAN1 interrupt line 0 */
  571. {
  572. rt_interrupt_enter();
  573. HAL_FDCAN_IRQHandler(&st_DrvCan1.fdcanHandle);
  574. rt_interrupt_leave();
  575. }
  576. void FDCAN1_IT1_IRQHandler(void) /* FDCAN1 interrupt line 1 */
  577. {
  578. rt_interrupt_enter();
  579. HAL_FDCAN_IRQHandler(&st_DrvCan1.fdcanHandle);
  580. rt_interrupt_leave();
  581. }
  582. #endif /*BSP_USING_FDCAN1*/
  583. #ifdef BSP_USING_FDCAN2
  584. void FDCAN2_IT0_IRQHandler(void) /* FDCAN2 interrupt line 0 */
  585. {
  586. rt_interrupt_enter();
  587. HAL_FDCAN_IRQHandler(&st_DrvCan2.fdcanHandle);
  588. rt_interrupt_leave();
  589. }
  590. void FDCAN2_IT1_IRQHandler(void) /* FDCAN2 interrupt line 1 */
  591. {
  592. rt_interrupt_enter();
  593. HAL_FDCAN_IRQHandler(&st_DrvCan2.fdcanHandle);
  594. rt_interrupt_leave();
  595. }
  596. #endif/*BSP_USING_FDCAN2*/
  597. static int rt_hw_can_init(void)
  598. {
  599. struct can_configure config;
  600. config.baud_rate = CAN1MBaud;
  601. config.msgboxsz = 48;
  602. config.sndboxnumber = 1;
  603. config.mode = RT_CAN_MODE_NORMAL;
  604. config.privmode = RT_CAN_MODE_NOPRIV;
  605. config.ticks = 50;
  606. #ifdef RT_CAN_USING_HDR
  607. config.maxhdr = 14;
  608. #endif
  609. #ifdef RT_CAN_USING_CANFD
  610. config.baud_rate_fd = CAN1MBaud * 8;
  611. config.enable_canfd = 1;
  612. #endif
  613. /* config default filter */
  614. FDCAN_FilterTypeDef sFilterConfig;
  615. sFilterConfig.IdType = FDCAN_STANDARD_ID;
  616. sFilterConfig.FilterIndex = 0;
  617. sFilterConfig.FilterType = FDCAN_FILTER_MASK;
  618. sFilterConfig.FilterConfig = FDCAN_FILTER_TO_RXFIFO0;
  619. sFilterConfig.FilterID1 = 0;
  620. sFilterConfig.FilterID2 = 0x7FF;
  621. #ifdef BSP_USING_FDCAN1
  622. st_DrvCan1.FilterConfig = sFilterConfig;
  623. st_DrvCan1.device.config = config;
  624. /* register FDCAN1 device */
  625. rt_hw_can_register(&st_DrvCan1.device, st_DrvCan1.name, &_can_ops, &st_DrvCan1);
  626. #endif /* BSP_USING_FDCAN1 */
  627. #ifdef BSP_USING_FDCAN2
  628. st_DrvCan2.FilterConfig = sFilterConfig;
  629. st_DrvCan2.device.config = config;
  630. /* register FDCAN2 device */
  631. rt_hw_can_register(&st_DrvCan2.device, st_DrvCan2.name, &_can_ops, &st_DrvCan2);
  632. #endif /* BSP_USING_FDCAN2 */
  633. return 0;
  634. }
  635. INIT_BOARD_EXPORT(rt_hw_can_init);
  636. #endif /* BSP_USING_FDCAN1 || BSP_USING_FDCAN2 */
  637. #endif /* RT_USING_CAN */