drv_gpio.c 11 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-7-20 wudiyidashi first version
  9. */
  10. #include <board.h>
  11. #include "drv_gpio.h"
  12. #ifdef RT_USING_PIN
  13. #define PIN_NUM(port, no) (((((port)&0xFu) << 4) | ((no)&0xFu)))
  14. #define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
  15. #define PIN_NO(pin) ((uint8_t)((pin)&0xFu))
  16. #define PIN_STPORT(pin) ((GPIO_Type *)(GPIOA_BASE + (0x40u * PIN_PORT(pin))))
  17. #define PIN_STPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
  18. #define PIN_STPORT_MAX 4u
  19. /*
  20. --GPIO-- | EXTI INPUT | --EXTI--
  21. PA0~PA3 | EXTI_ASEL[1:0] | EXTI[0]
  22. PA4~PA7 | EXTI_ASEL[3:2] | EXTI[1]
  23. PA8~PA11 | EXTI_ASEL[5:4] | EXTI[2]
  24. PA12~PA15| EXTI_ASEL[7:6] | EXTI[3]
  25. PB0~PB3 | EXTI_BSEL[1:0] | EXTI[4]
  26. PB4~PB7 | EXTI_BSEL[3:2] | EXTI[5]
  27. PB8~PB11 | EXTI_BSEL[5:4] | EXTI[6]
  28. PB12~PB15 | EXTI_BSEL[7:6] | EXTI[7]
  29. PC0~PC3 | EXTI_CSEL[1:0] | EXTI[8]
  30. PC4~PC7 | EXTI_CSEL[3:2] | EXTI[9]
  31. PC8~PC11 | EXTI_CSEL[5:4] | EXTI[10]
  32. PC12 | - | EXTI[11]
  33. PD0~PD3 | EXTI_DSEL[1:0] | EXTI[12]
  34. PD4~PD7 | EXTI_DSEL[3:2] | EXTI[13]
  35. PD8~PD11 | EXTI_DSEL[5:4] | EXTI[14]
  36. PD12 | - | EXTI[15]
  37. {PIN_NUM(PA3),FL_GPIO_EXTI_LINE_0}
  38. {PIN_NUM(PA7),FL_GPIO_EXTI_LINE_0}
  39. ...
  40. {PIN_NUM(PD12),FL_GPIO_EXTI_LINE_0}
  41. */
  42. static const struct pin_irq_map pin_irq_map[] =
  43. {
  44. {3, FL_GPIO_EXTI_LINE_0},
  45. {7, FL_GPIO_EXTI_LINE_1},
  46. {11, FL_GPIO_EXTI_LINE_2},
  47. {15, FL_GPIO_EXTI_LINE_3},
  48. {19, FL_GPIO_EXTI_LINE_4},
  49. {23, FL_GPIO_EXTI_LINE_5},
  50. {27, FL_GPIO_EXTI_LINE_6},
  51. {31, FL_GPIO_EXTI_LINE_7},
  52. {35, FL_GPIO_EXTI_LINE_8},
  53. {39, FL_GPIO_EXTI_LINE_9},
  54. {43, FL_GPIO_EXTI_LINE_10},
  55. {44, FL_GPIO_EXTI_LINE_11},
  56. {51, FL_GPIO_EXTI_LINE_12},
  57. {55, FL_GPIO_EXTI_LINE_13},
  58. {59, FL_GPIO_EXTI_LINE_14},
  59. {60, FL_GPIO_EXTI_LINE_15},
  60. };
  61. static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
  62. {
  63. {-1, 0, RT_NULL, RT_NULL},
  64. {-1, 0, RT_NULL, RT_NULL},
  65. {-1, 0, RT_NULL, RT_NULL},
  66. {-1, 0, RT_NULL, RT_NULL},
  67. {-1, 0, RT_NULL, RT_NULL},
  68. {-1, 0, RT_NULL, RT_NULL},
  69. {-1, 0, RT_NULL, RT_NULL},
  70. {-1, 0, RT_NULL, RT_NULL},
  71. {-1, 0, RT_NULL, RT_NULL},
  72. {-1, 0, RT_NULL, RT_NULL},
  73. {-1, 0, RT_NULL, RT_NULL},
  74. {-1, 0, RT_NULL, RT_NULL},
  75. {-1, 0, RT_NULL, RT_NULL},
  76. {-1, 0, RT_NULL, RT_NULL},
  77. {-1, 0, RT_NULL, RT_NULL},
  78. {-1, 0, RT_NULL, RT_NULL},
  79. };
  80. static uint32_t pin_irq_enable_mask = 0;
  81. #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
  82. static rt_base_t fm33_pin_get(const char *name)
  83. {
  84. rt_base_t pin = 0;
  85. int hw_port_num, hw_pin_num = 0;
  86. int i, name_len;
  87. name_len = rt_strlen(name);
  88. if ((name_len < 4) || (name_len >= 6))
  89. {
  90. return -RT_EINVAL;
  91. }
  92. if ((name[0] != 'P') || (name[2] != '.'))
  93. {
  94. return -RT_EINVAL;
  95. }
  96. if ((name[1] >= 'A') && (name[1] <= 'Z'))
  97. {
  98. hw_port_num = (int)(name[1] - 'A');
  99. }
  100. else
  101. {
  102. return -RT_EINVAL;
  103. }
  104. for (i = 3; i < name_len; i++)
  105. {
  106. hw_pin_num *= 10;
  107. hw_pin_num += name[i] - '0';
  108. }
  109. pin = PIN_NUM(hw_port_num, hw_pin_num);
  110. return pin;
  111. }
  112. static void fm33_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
  113. {
  114. GPIO_Type *gpio_port;
  115. uint16_t gpio_pin;
  116. if (PIN_PORT(pin) < PIN_STPORT_MAX)
  117. {
  118. gpio_port = PIN_STPORT(pin);
  119. gpio_pin = PIN_STPIN(pin);
  120. if (value == PIN_LOW)
  121. {
  122. FL_GPIO_ResetOutputPin(gpio_port, gpio_pin);
  123. }
  124. else
  125. {
  126. FL_GPIO_SetOutputPin(gpio_port, gpio_pin);
  127. }
  128. }
  129. }
  130. static rt_ssize_t fm33_pin_read(rt_device_t dev, rt_base_t pin)
  131. {
  132. GPIO_Type *gpio_port;
  133. uint16_t gpio_pin;
  134. rt_ssize_t value = PIN_LOW;
  135. if (PIN_PORT(pin) < PIN_STPORT_MAX)
  136. {
  137. gpio_port = PIN_STPORT(pin);
  138. gpio_pin = PIN_STPIN(pin);
  139. value = FL_GPIO_GetInputPin(gpio_port, gpio_pin);
  140. }
  141. else
  142. {
  143. value = -RT_EINVAL;
  144. }
  145. return value;
  146. }
  147. static void fm33_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
  148. {
  149. FL_GPIO_InitTypeDef GPIO_InitStruct;
  150. if (PIN_PORT(pin) >= PIN_STPORT_MAX)
  151. {
  152. return;
  153. }
  154. /* Configure GPIO_InitStructure */
  155. GPIO_InitStruct.pin = PIN_STPIN(pin);
  156. GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
  157. GPIO_InitStruct.pull = FL_DISABLE;
  158. GPIO_InitStruct.remapPin = FL_DISABLE;
  159. if (mode == PIN_MODE_OUTPUT)
  160. {
  161. /* output setting */
  162. GPIO_InitStruct.mode = FL_GPIO_MODE_OUTPUT;
  163. GPIO_InitStruct.pull = FL_DISABLE;
  164. }
  165. else if (mode == PIN_MODE_INPUT)
  166. {
  167. /* input setting: not pull. */
  168. GPIO_InitStruct.mode = FL_GPIO_MODE_INPUT;
  169. GPIO_InitStruct.pull = FL_DISABLE;
  170. }
  171. else if (mode == PIN_MODE_INPUT_PULLUP)
  172. {
  173. /* input setting: pull up. */
  174. GPIO_InitStruct.mode = FL_GPIO_MODE_INPUT;
  175. GPIO_InitStruct.pull = FL_ENABLE;
  176. }
  177. else if (mode == PIN_MODE_INPUT_PULLDOWN)
  178. {
  179. /* input setting: pull down. */
  180. GPIO_InitStruct.mode = FL_GPIO_MODE_INPUT;
  181. GPIO_InitStruct.pull = FL_DISABLE;
  182. }
  183. else if (mode == PIN_MODE_OUTPUT_OD)
  184. {
  185. /* output setting: od. */
  186. GPIO_InitStruct.mode = FL_GPIO_OUTPUT_OPENDRAIN;
  187. GPIO_InitStruct.pull = FL_DISABLE;
  188. }
  189. FL_GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
  190. }
  191. rt_inline rt_int32_t pin2irqindex(rt_uint32_t pin)
  192. {
  193. rt_uint8_t irqindex;
  194. for (irqindex = 4 * PIN_PORT(pin); irqindex <= ITEM_NUM(pin_irq_map); irqindex++)
  195. {
  196. if (pin_irq_map[irqindex].pin >= pin && pin_irq_map[irqindex - 1].pin < pin)
  197. {
  198. return irqindex;
  199. }
  200. }
  201. return -1;
  202. }
  203. rt_inline const struct pin_irq_map *get_pin_irq_map(rt_base_t pin)
  204. {
  205. rt_int32_t mapindex;
  206. mapindex = pin2irqindex(pin);
  207. if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
  208. {
  209. return RT_NULL;
  210. }
  211. return &pin_irq_map[mapindex];
  212. };
  213. static rt_err_t fm33_pin_attach_irq(struct rt_device *device, rt_base_t pin,
  214. rt_uint8_t mode, void (*hdr)(void *args), void *args)
  215. {
  216. rt_base_t level;
  217. rt_int32_t irqindex = -1;
  218. if (PIN_PORT(pin) >= PIN_STPORT_MAX)
  219. {
  220. return -RT_ENOSYS;
  221. }
  222. irqindex = pin2irqindex(pin);
  223. if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
  224. {
  225. return -RT_ENOSYS;
  226. }
  227. level = rt_hw_interrupt_disable();
  228. if (pin_irq_hdr_tab[irqindex].pin == pin &&
  229. pin_irq_hdr_tab[irqindex].hdr == hdr &&
  230. pin_irq_hdr_tab[irqindex].mode == mode &&
  231. pin_irq_hdr_tab[irqindex].args == args)
  232. {
  233. rt_hw_interrupt_enable(level);
  234. return RT_EOK;
  235. }
  236. if (pin_irq_hdr_tab[irqindex].pin != -1)
  237. {
  238. rt_hw_interrupt_enable(level);
  239. return -RT_EBUSY;
  240. }
  241. pin_irq_hdr_tab[irqindex].pin = pin;
  242. pin_irq_hdr_tab[irqindex].hdr = hdr;
  243. pin_irq_hdr_tab[irqindex].mode = mode;
  244. pin_irq_hdr_tab[irqindex].args = args;
  245. rt_hw_interrupt_enable(level);
  246. return RT_EOK;
  247. }
  248. static rt_err_t fm33_pin_dettach_irq(struct rt_device *device, rt_base_t pin)
  249. {
  250. rt_base_t level;
  251. rt_int32_t irqindex = -1;
  252. if (PIN_PORT(pin) >= PIN_STPORT_MAX)
  253. {
  254. return -RT_ENOSYS;
  255. }
  256. irqindex = pin2irqindex(PIN_STPIN(pin));
  257. if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
  258. {
  259. return -RT_ENOSYS;
  260. }
  261. level = rt_hw_interrupt_disable();
  262. if (pin_irq_hdr_tab[irqindex].pin == -1)
  263. {
  264. rt_hw_interrupt_enable(level);
  265. return RT_EOK;
  266. }
  267. pin_irq_hdr_tab[irqindex].pin = -1;
  268. pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
  269. pin_irq_hdr_tab[irqindex].mode = 0;
  270. pin_irq_hdr_tab[irqindex].args = RT_NULL;
  271. rt_hw_interrupt_enable(level);
  272. return RT_EOK;
  273. }
  274. static rt_err_t fm33_pin_irq_enable(struct rt_device *device, rt_base_t pin,
  275. rt_uint8_t enabled)
  276. {
  277. const struct pin_irq_map *irqmap;
  278. rt_base_t level;
  279. rt_int8_t irqindex = 0;
  280. FL_GPIO_InitTypeDef GPIO_InitStruct;
  281. FL_EXTI_InitTypeDef extiInitStruct = {0};
  282. FL_EXTI_CommonInitTypeDef extiCommonInitStruct = {0};
  283. FL_RCC_EnableEXTIOnSleep();
  284. extiCommonInitStruct.clockSource = FL_RCC_EXTI_CLK_SOURCE_HCLK;
  285. FL_EXTI_CommonInit(&extiCommonInitStruct);
  286. if (PIN_PORT(pin) >= PIN_STPORT_MAX)
  287. {
  288. return -RT_ENOSYS;
  289. }
  290. if (enabled == PIN_IRQ_ENABLE)
  291. {
  292. if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
  293. {
  294. return -RT_ENOSYS;
  295. }
  296. irqindex = pin2irqindex(pin);
  297. irqmap = &pin_irq_map[irqindex];
  298. level = rt_hw_interrupt_disable();
  299. if (pin_irq_hdr_tab[irqindex].pin == -1)
  300. {
  301. rt_hw_interrupt_enable(level);
  302. return -RT_ENOSYS;
  303. }
  304. /* Configure GPIO_InitStructure */
  305. GPIO_InitStruct.pin = PIN_STPIN(pin);
  306. GPIO_InitStruct.mode = FL_GPIO_MODE_INPUT;
  307. GPIO_InitStruct.outputType = FL_GPIO_OUTPUT_PUSHPULL;
  308. GPIO_InitStruct.pull = FL_DISABLE;
  309. GPIO_InitStruct.remapPin = FL_DISABLE;
  310. extiInitStruct.input = pin - pin_irq_map[irqindex - 1].pin - 1;
  311. extiInitStruct.filter = FL_ENABLE;
  312. switch (pin_irq_hdr_tab[irqindex].mode)
  313. {
  314. case PIN_IRQ_MODE_RISING:
  315. extiInitStruct.triggerEdge = FL_GPIO_EXTI_TRIGGER_EDGE_RISING;
  316. break;
  317. case PIN_IRQ_MODE_FALLING:
  318. extiInitStruct.triggerEdge = FL_GPIO_EXTI_TRIGGER_EDGE_FALLING;
  319. break;
  320. case PIN_IRQ_MODE_RISING_FALLING:
  321. extiInitStruct.triggerEdge = FL_GPIO_EXTI_TRIGGER_EDGE_BOTH;
  322. break;
  323. }
  324. FL_GPIO_Init(PIN_STPORT(pin), &GPIO_InitStruct);
  325. FL_EXTI_Init(irqmap->irqno, &extiInitStruct);
  326. NVIC_DisableIRQ(GPIO_IRQn);
  327. NVIC_SetPriority(GPIO_IRQn, 2);
  328. NVIC_EnableIRQ(GPIO_IRQn);
  329. pin_irq_enable_mask |= irqmap->irqno;
  330. rt_hw_interrupt_enable(level);
  331. }
  332. else if (enabled == PIN_IRQ_DISABLE)
  333. {
  334. irqmap = get_pin_irq_map(PIN_STPIN(pin));
  335. if (irqmap == RT_NULL)
  336. {
  337. return -RT_ENOSYS;
  338. }
  339. level = rt_hw_interrupt_disable();
  340. FL_GPIO_DeInit(PIN_STPORT(pin), PIN_STPIN(pin));
  341. pin_irq_enable_mask &= ~irqmap->irqno;
  342. NVIC_DisableIRQ(GPIO_IRQn);
  343. rt_hw_interrupt_enable(level);
  344. }
  345. else
  346. {
  347. return -RT_ENOSYS;
  348. }
  349. return RT_EOK;
  350. }
  351. const static struct rt_pin_ops _fm33_pin_ops =
  352. {
  353. fm33_pin_mode,
  354. fm33_pin_write,
  355. fm33_pin_read,
  356. fm33_pin_attach_irq,
  357. fm33_pin_dettach_irq,
  358. fm33_pin_irq_enable,
  359. fm33_pin_get,
  360. };
  361. rt_inline void pin_irq_hdr(int irqno)
  362. {
  363. if (pin_irq_hdr_tab[irqno].hdr)
  364. {
  365. pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
  366. }
  367. }
  368. void GPIO_IRQHandler(void)
  369. {
  370. rt_interrupt_enter();
  371. for (uint8_t extinum = 0; extinum < 16; ++extinum)
  372. {
  373. if (FL_GPIO_IsActiveFlag_EXTI(GPIO, 0x1U << extinum))
  374. {
  375. FL_GPIO_ClearFlag_EXTI(GPIO, 0x1U << extinum);
  376. pin_irq_hdr(extinum);
  377. }
  378. }
  379. rt_interrupt_leave();
  380. }
  381. int rt_hw_pin_init(void)
  382. {
  383. return rt_device_pin_register("pin", &_fm33_pin_ops, RT_NULL);
  384. }
  385. #endif /* RT_USING_PIN */