drv_i2c.c 18 KB

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  1. /*
  2. * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-04-28 CDT first version
  9. */
  10. /*******************************************************************************
  11. * Include files
  12. ******************************************************************************/
  13. #include <rtthread.h>
  14. #include <rthw.h>
  15. #ifdef RT_USING_I2C
  16. #if defined(BSP_USING_I2C1) || defined(BSP_USING_I2C2) || defined(BSP_USING_I2C3) || \
  17. defined(BSP_USING_I2C4) || defined(BSP_USING_I2C5) || defined(BSP_USING_I2C6)
  18. #include "drv_i2c.h"
  19. /*******************************************************************************
  20. * Local type definitions ('typedef')
  21. ******************************************************************************/
  22. /*******************************************************************************
  23. * Local pre-processor symbols/macros ('#define')
  24. ******************************************************************************/
  25. #ifndef HC32_I2C_DEBUG
  26. #define I2C_PRINT_DBG(fmt, args...)
  27. #define I2C_PRINT_ERR(fmt, args...) rt_kprintf(fmt, ##args);
  28. #else
  29. #define I2C_PRINT_DBG(fmt, args...) rt_kprintf(fmt, ##args);
  30. #define I2C_PRINT_ERR(fmt, args...) rt_kprintf(fmt, ##args);
  31. #endif
  32. #define I2C_TIMEOUT ((uint32_t)0x10000)
  33. #define FCG_I2C_CLK FCG_Fcg1PeriphClockCmd
  34. /*******************************************************************************
  35. * Global variable definitions (declared in header file with 'extern')
  36. ******************************************************************************/
  37. extern rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx);
  38. /*******************************************************************************
  39. * Local function prototypes ('static')
  40. ******************************************************************************/
  41. enum
  42. {
  43. #ifdef BSP_USING_I2C1
  44. I2C1_INDEX,
  45. #endif
  46. #ifdef BSP_USING_I2C2
  47. I2C2_INDEX,
  48. #endif
  49. #ifdef BSP_USING_I2C3
  50. I2C3_INDEX,
  51. #endif
  52. #ifdef BSP_USING_I2C4
  53. I2C4_INDEX,
  54. #endif
  55. #ifdef BSP_USING_I2C5
  56. I2C5_INDEX,
  57. #endif
  58. #ifdef BSP_USING_I2C6
  59. I2C6_INDEX,
  60. #endif
  61. };
  62. static struct hc32_i2c_config i2c_config[] =
  63. {
  64. #ifdef BSP_USING_I2C1
  65. I2C1_CONFIG,
  66. #endif
  67. #ifdef BSP_USING_I2C2
  68. I2C2_CONFIG,
  69. #endif
  70. #ifdef BSP_USING_I2C3
  71. I2C3_CONFIG,
  72. #endif
  73. #ifdef BSP_USING_I2C4
  74. I2C4_CONFIG,
  75. #endif
  76. #ifdef BSP_USING_I2C5
  77. I2C5_CONFIG,
  78. #endif
  79. #ifdef BSP_USING_I2C6
  80. I2C6_CONFIG,
  81. #endif
  82. };
  83. static void hc32_i2c_dma_configure(struct rt_i2c_bus_device *bus);
  84. static struct hc32_i2c i2c_objs[sizeof(i2c_config) / sizeof(i2c_config[0])] = {0};
  85. /*******************************************************************************
  86. * Function implementation - global ('extern') and local ('static')
  87. ******************************************************************************/
  88. static rt_err_t hc32_i2c_configure(struct rt_i2c_bus_device *bus)
  89. {
  90. int ret = -RT_ERROR;
  91. stc_i2c_init_t i2c_init;
  92. float32_t f32Error = 0.0F;
  93. rt_uint32_t I2cSrcClk;
  94. rt_uint32_t I2cClkDiv;
  95. rt_uint32_t I2cClkDivReg;
  96. RT_ASSERT(RT_NULL != bus);
  97. struct hc32_i2c *i2c_obj = rt_container_of(bus, struct hc32_i2c, i2c_bus);
  98. /* Enable I2C clock */
  99. FCG_I2C_CLK(i2c_obj->config->clock, ENABLE);
  100. if (RT_EOK != rt_hw_board_i2c_init(i2c_obj->config->Instance))
  101. {
  102. return -RT_ERROR;
  103. }
  104. I2C_DeInit(i2c_obj->config->Instance);
  105. I2cSrcClk = I2C_SRC_CLK;
  106. I2cClkDiv = I2cSrcClk / i2c_obj->config->baudrate / I2C_WIDTH_MAX_IMME;
  107. for (I2cClkDivReg = I2C_CLK_DIV1; I2cClkDivReg <= I2C_CLK_DIV128; I2cClkDivReg++)
  108. {
  109. if (I2cClkDiv < (1UL << I2cClkDivReg))
  110. {
  111. break;
  112. }
  113. }
  114. i2c_init.u32ClockDiv = I2cClkDivReg;
  115. i2c_init.u32SclTime = 400UL * I2cSrcClk / (1UL << I2cClkDivReg) / 1000000000UL; /* SCL time is about 400nS in EVB board */
  116. i2c_init.u32Baudrate = i2c_obj->config->baudrate;
  117. ret = I2C_Init(i2c_obj->config->Instance, &i2c_init, &f32Error);
  118. if (RT_EOK == ret)
  119. {
  120. I2C_BusWaitCmd(i2c_obj->config->Instance, ENABLE);
  121. I2C_Cmd(i2c_obj->config->Instance, ENABLE);
  122. }
  123. if ((i2c_obj->i2c_dma_flag & I2C_USING_TX_DMA_FLAG) || (i2c_obj->i2c_dma_flag & I2C_USING_RX_DMA_FLAG))
  124. {
  125. hc32_i2c_dma_configure(bus);
  126. }
  127. return ret;
  128. }
  129. static void hc32_hw_i2c_reset(struct hc32_i2c *i2c_obj)
  130. {
  131. I2C_SWResetCmd(i2c_obj->config->Instance, ENABLE);
  132. I2C_SWResetCmd(i2c_obj->config->Instance, DISABLE);
  133. }
  134. static int hc32_hw_i2c_start(struct hc32_i2c *i2c_obj)
  135. {
  136. if (LL_OK != I2C_Start(i2c_obj->config->Instance, i2c_obj->config->timeout))
  137. {
  138. return -RT_ERROR;
  139. }
  140. return RT_EOK;
  141. }
  142. static int hc32_hw_i2c_restart(struct hc32_i2c *i2c_obj)
  143. {
  144. if (LL_OK != I2C_Restart(i2c_obj->config->Instance, i2c_obj->config->timeout))
  145. {
  146. return -RT_ERROR;
  147. }
  148. return RT_EOK;
  149. }
  150. static int hc32_hw_i2c_send_addr(struct hc32_i2c *i2c_obj,
  151. struct rt_i2c_msg *msg)
  152. {
  153. rt_uint8_t dir = ((msg->flags & RT_I2C_RD) == RT_I2C_RD) ? (I2C_DIR_RX) : (I2C_DIR_TX);
  154. if (LL_OK != I2C_TransAddr(i2c_obj->config->Instance, msg->addr, dir, i2c_obj->config->timeout))
  155. {
  156. return -RT_ERROR;
  157. }
  158. return RT_EOK;
  159. }
  160. static int hc32_hw_i2c_stop(struct hc32_i2c *i2c_obj)
  161. {
  162. if (LL_OK != I2C_Stop(i2c_obj->config->Instance, i2c_obj->config->timeout))
  163. {
  164. return -RT_ERROR;
  165. }
  166. return RT_EOK;
  167. }
  168. static void hc32_i2c_get_dma_info(void)
  169. {
  170. #ifdef BSP_I2C1_TX_USING_DMA
  171. static struct dma_config i2c1_tx_dma = I2C1_TX_DMA_CONFIG;
  172. i2c_objs[I2C1_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG;
  173. i2c_config[I2C1_INDEX].i2c_tx_dma = &i2c1_tx_dma;
  174. #endif
  175. #ifdef BSP_I2C1_RX_USING_DMA
  176. static struct dma_config i2c1_rx_dma = I2C1_RX_DMA_CONFIG;
  177. i2c_objs[I2C1_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG;
  178. i2c_config[I2C1_INDEX].i2c_rx_dma = &i2c1_rx_dma;
  179. #endif
  180. #ifdef BSP_I2C2_TX_USING_DMA
  181. static struct dma_config i2c2_tx_dma = I2C2_TX_DMA_CONFIG;
  182. i2c_objs[I2C2_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG;
  183. i2c_config[I2C2_INDEX].i2c_tx_dma = &i2c2_tx_dma;
  184. #endif
  185. #ifdef BSP_I2C2_RX_USING_DMA
  186. static struct dma_config i2c2_rx_dma = I2C2_RX_DMA_CONFIG;
  187. i2c_objs[I2C2_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG;
  188. i2c_config[I2C2_INDEX].i2c_rx_dma = &i2c2_rx_dma;
  189. #endif
  190. #ifdef BSP_I2C3_TX_USING_DMA
  191. static struct dma_config i2c3_tx_dma = I2C3_TX_DMA_CONFIG;
  192. i2c_objs[I2C3_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG;
  193. i2c_config[I2C3_INDEX].i2c_tx_dma = &i2c3_tx_dma;
  194. #endif
  195. #ifdef BSP_I2C3_RX_USING_DMA
  196. static struct dma_config i2c3_rx_dma = I2C3_RX_DMA_CONFIG;
  197. i2c_objs[I2C3_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG;
  198. i2c_config[I2C3_INDEX].i2c_rx_dma = &i2c3_rx_dma;
  199. #endif
  200. #ifdef BSP_I2C4_TX_USING_DMA
  201. static struct dma_config i2c4_tx_dma = I2C4_TX_DMA_CONFIG;
  202. i2c_objs[I2C4_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG;
  203. i2c_config[I2C4_INDEX].i2c_tx_dma = &i2c4_tx_dma;
  204. #endif
  205. #ifdef BSP_I2C4_RX_USING_DMA
  206. static struct dma_config i2c4_rx_dma = I2C4_RX_DMA_CONFIG;
  207. i2c_objs[I2C4_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG;
  208. i2c_config[I2C4_INDEX].i2c_rx_dma = &i2c4_rx_dma;
  209. #endif
  210. #ifdef BSP_I2C5_TX_USING_DMA
  211. static struct dma_config i2c5_tx_dma = I2C5_TX_DMA_CONFIG;
  212. i2c_objs[I2C5_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG;
  213. i2c_config[I2C5_INDEX].i2c_tx_dma = &i2c5_tx_dma;
  214. #endif
  215. #ifdef BSP_I2C5_RX_USING_DMA
  216. static struct dma_config i2c5_rx_dma = I2C5_RX_DMA_CONFIG;
  217. i2c_objs[I2C5_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG;
  218. i2c_config[I2C5_INDEX].i2c_rx_dma = &i2c5_rx_dma;
  219. #endif
  220. #ifdef BSP_I2C6_TX_USING_DMA
  221. static struct dma_config i2c6_tx_dma = I2C6_TX_DMA_CONFIG;
  222. i2c_objs[I2C6_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG;
  223. i2c_config[I2C6_INDEX].i2c_tx_dma = &i2c6_tx_dma;
  224. #endif
  225. #ifdef BSP_I2C6_RX_USING_DMA
  226. static struct dma_config i2c6_rx_dma = I2C6_RX_DMA_CONFIG;
  227. i2c_objs[I2C6_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG;
  228. i2c_config[I2C6_INDEX].i2c_rx_dma = &i2c6_rx_dma;
  229. #endif
  230. }
  231. static void hc32_i2c_dma_configure(struct rt_i2c_bus_device *bus)
  232. {
  233. stc_dma_init_t stcDmaInit;
  234. struct hc32_i2c *i2c_obj = rt_container_of(bus, struct hc32_i2c, i2c_bus);
  235. if (i2c_obj->i2c_dma_flag & I2C_USING_TX_DMA_FLAG)
  236. {
  237. /* DMA/AOS FCG enable */
  238. FCG_Fcg0PeriphClockCmd(i2c_obj->config->i2c_tx_dma->clock, ENABLE);
  239. (void)DMA_StructInit(&stcDmaInit);
  240. stcDmaInit.u32BlockSize = 1UL;
  241. stcDmaInit.u32TransCount = 0UL;
  242. stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT;
  243. /* Configure TX */
  244. stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_INC;
  245. stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_FIX;
  246. stcDmaInit.u32SrcAddr = (uint32_t)NULL;
  247. stcDmaInit.u32DestAddr = (uint32_t)(&i2c_obj->config->Instance->DTR);
  248. if (LL_OK != DMA_Init(i2c_obj->config->i2c_tx_dma->Instance, i2c_obj->config->i2c_tx_dma->channel, &stcDmaInit))
  249. {
  250. I2C_PRINT_ERR("[%s:%d]I2C TX DMA init error!\n", __func__, __LINE__);
  251. }
  252. AOS_SetTriggerEventSrc(i2c_obj->config->i2c_tx_dma->trigger_select, i2c_obj->config->i2c_tx_dma->trigger_event);
  253. /* Enable DMA unit */
  254. DMA_Cmd(i2c_obj->config->i2c_tx_dma->Instance, ENABLE);
  255. }
  256. if (i2c_obj->i2c_dma_flag & I2C_USING_RX_DMA_FLAG)
  257. {
  258. /* DMA/AOS FCG enable */
  259. FCG_Fcg0PeriphClockCmd(i2c_obj->config->i2c_rx_dma->clock, ENABLE);
  260. (void)DMA_StructInit(&stcDmaInit);
  261. stcDmaInit.u32BlockSize = 1UL;
  262. stcDmaInit.u32TransCount = 0UL;
  263. stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT;
  264. /* Configure RX */
  265. stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_FIX;
  266. stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_INC;
  267. stcDmaInit.u32SrcAddr = (uint32_t)(&i2c_obj->config->Instance->DRR);
  268. stcDmaInit.u32DestAddr = (uint32_t)NULL;
  269. if (LL_OK != DMA_Init(i2c_obj->config->i2c_rx_dma->Instance, i2c_obj->config->i2c_rx_dma->channel, &stcDmaInit))
  270. {
  271. I2C_PRINT_ERR("[%s:%d]I2C RX DMA init error!\n", __func__, __LINE__);
  272. }
  273. AOS_SetTriggerEventSrc(i2c_obj->config->i2c_rx_dma->trigger_select, i2c_obj->config->i2c_rx_dma->trigger_event);
  274. /* Enable DMA unit */
  275. DMA_Cmd(i2c_obj->config->i2c_rx_dma->Instance, ENABLE);
  276. }
  277. }
  278. static int I2C_Master_Transmit_DMA(struct hc32_i2c *i2c_obj, struct rt_i2c_msg *msg)
  279. {
  280. rt_uint32_t timeCnt;
  281. struct dma_config *i2c_tx_dma;
  282. i2c_tx_dma = i2c_obj->config->i2c_tx_dma;
  283. if (msg->len > 1U)
  284. {
  285. DMA_ClearTransCompleteStatus(i2c_tx_dma->Instance, i2c_tx_dma->flag);
  286. (void)DMA_SetTransCount(i2c_tx_dma->Instance, i2c_tx_dma->channel, msg->len - 1U);
  287. (void)DMA_SetSrcAddr(i2c_tx_dma->Instance, i2c_tx_dma->channel, (uint32_t)(&msg->buf[1]));
  288. (void)DMA_ChCmd(i2c_tx_dma->Instance, i2c_tx_dma->channel, ENABLE);
  289. }
  290. I2C_WriteData(i2c_obj->config->Instance, msg->buf[0]);
  291. if (msg->len > 1U)
  292. {
  293. timeCnt = 0;
  294. /* wait DMA transfer completed */
  295. while (RESET == DMA_GetTransCompleteStatus(i2c_tx_dma->Instance, i2c_tx_dma->flag) && (timeCnt < i2c_obj->config->timeout))
  296. {
  297. rt_thread_mdelay(1);
  298. timeCnt++;
  299. }
  300. if (timeCnt >= i2c_obj->config->timeout)
  301. {
  302. return -RT_ETIMEOUT;
  303. }
  304. }
  305. /* wait last I2C data transfer completed */
  306. timeCnt = 0;
  307. while ((LL_OK != I2C_WaitStatus(i2c_obj->config->Instance, I2C_FLAG_TX_CPLT, SET, 1)) && (timeCnt < i2c_obj->config->timeout))
  308. {
  309. rt_thread_mdelay(1);
  310. timeCnt++;
  311. }
  312. if (timeCnt >= i2c_obj->config->timeout)
  313. {
  314. return -RT_ETIMEOUT;
  315. }
  316. return RT_EOK;
  317. }
  318. static int I2C_Master_Receive_DMA(struct hc32_i2c *i2c_obj, struct rt_i2c_msg *msg)
  319. {
  320. rt_uint32_t timeCnt;
  321. struct dma_config *i2c_rx_dma;
  322. i2c_rx_dma = i2c_obj->config->i2c_rx_dma;
  323. if (1UL == msg->len)
  324. {
  325. I2C_AckConfig(i2c_obj->config->Instance, I2C_NACK);
  326. }
  327. else if (msg->len > 2U)
  328. {
  329. DMA_ClearTransCompleteStatus(i2c_rx_dma->Instance, i2c_rx_dma->flag);
  330. (void)DMA_SetTransCount(i2c_rx_dma->Instance, i2c_rx_dma->channel, msg->len - 2U);
  331. (void)DMA_SetDestAddr(i2c_rx_dma->Instance, i2c_rx_dma->channel, (uint32_t)(&msg->buf[0]));
  332. (void)DMA_ChCmd(i2c_rx_dma->Instance, i2c_rx_dma->channel, ENABLE);
  333. }
  334. if (msg->len > 2U)
  335. {
  336. timeCnt = 0;
  337. /* Wait DMA finish */
  338. while ((RESET == DMA_GetTransCompleteStatus(i2c_rx_dma->Instance, i2c_rx_dma->flag)) && (timeCnt < i2c_obj->config->timeout))
  339. {
  340. /* Need add timeout release process here */
  341. rt_thread_mdelay(1);
  342. timeCnt++;
  343. }
  344. if (timeCnt >= i2c_obj->config->timeout)
  345. {
  346. return -RT_ETIMEOUT;
  347. }
  348. }
  349. if (msg->len > 1U)
  350. {
  351. timeCnt = 0;
  352. /* Wait data receive finish */
  353. while ((LL_OK != I2C_WaitStatus(i2c_obj->config->Instance, I2C_FLAG_RX_FULL, SET, 1)) && (timeCnt < i2c_obj->config->timeout))
  354. {
  355. rt_thread_mdelay(1);
  356. timeCnt++;
  357. }
  358. if (timeCnt >= i2c_obj->config->timeout)
  359. {
  360. return -RT_ETIMEOUT;
  361. }
  362. I2C_AckConfig(i2c_obj->config->Instance, I2C_NACK);
  363. msg->buf[msg->len - 2U] = I2C_ReadData(i2c_obj->config->Instance);
  364. }
  365. timeCnt = 0;
  366. /* Wait last data receive finish */
  367. while ((LL_OK != I2C_WaitStatus(i2c_obj->config->Instance, I2C_FLAG_RX_FULL, SET, 1)) && (timeCnt < i2c_obj->config->timeout))
  368. {
  369. rt_thread_mdelay(1);
  370. timeCnt++;
  371. }
  372. if (timeCnt >= i2c_obj->config->timeout)
  373. {
  374. return -RT_ETIMEOUT;
  375. }
  376. /* Stop before read last data */
  377. I2C_ClearStatus(i2c_obj->config->Instance, I2C_FLAG_STOP);
  378. I2C_GenerateStop(i2c_obj->config->Instance);
  379. /* read data from register */
  380. msg->buf[msg->len - 1U] = I2C_ReadData(i2c_obj->config->Instance);
  381. timeCnt = 0;
  382. while ((LL_OK != I2C_WaitStatus(i2c_obj->config->Instance, I2C_FLAG_STOP, SET, 1)) && (timeCnt < i2c_obj->config->timeout))
  383. {
  384. rt_thread_mdelay(1);
  385. timeCnt++;
  386. }
  387. if (timeCnt >= i2c_obj->config->timeout)
  388. {
  389. return -RT_ETIMEOUT;
  390. }
  391. I2C_AckConfig(i2c_obj->config->Instance, I2C_ACK);
  392. return RT_EOK;
  393. }
  394. static int I2C_Master_Transmit(struct hc32_i2c *i2c_obj,
  395. struct rt_i2c_msg *msg)
  396. {
  397. return I2C_TransData(i2c_obj->config->Instance, msg->buf, msg->len, i2c_obj->config->timeout);
  398. }
  399. static int I2C_Master_Receive(struct hc32_i2c *i2c_obj,
  400. struct rt_i2c_msg *msg)
  401. {
  402. if (msg->len == 1UL)
  403. {
  404. I2C_AckConfig(i2c_obj->config->Instance, I2C_NACK);
  405. }
  406. return I2C_MasterReceiveDataAndStop(i2c_obj->config->Instance, msg->buf, msg->len, i2c_obj->config->timeout);
  407. }
  408. static int hc32_i2c_write(struct hc32_i2c *i2c_obj,
  409. struct rt_i2c_msg *msg)
  410. {
  411. int ret;
  412. if (i2c_obj->i2c_dma_flag & I2C_USING_TX_DMA_FLAG)
  413. {
  414. ret = I2C_Master_Transmit_DMA(i2c_obj, msg);
  415. }
  416. else
  417. {
  418. ret = I2C_Master_Transmit(i2c_obj, msg);
  419. }
  420. return ret;
  421. }
  422. static int hc32_i2c_read(struct hc32_i2c *i2c_obj,
  423. struct rt_i2c_msg *msg)
  424. {
  425. int ret;
  426. if (i2c_obj->i2c_dma_flag & I2C_USING_RX_DMA_FLAG)
  427. {
  428. ret = I2C_Master_Receive_DMA(i2c_obj, msg);
  429. }
  430. else
  431. {
  432. ret = I2C_Master_Receive(i2c_obj, msg);
  433. }
  434. return ret;
  435. }
  436. static rt_ssize_t hc32_i2c_master_xfer(struct rt_i2c_bus_device *bus,
  437. struct rt_i2c_msg msgs[],
  438. rt_uint32_t num)
  439. {
  440. rt_int32_t i, ret;
  441. rt_uint16_t ignore_nack;
  442. struct rt_i2c_msg *msg = msgs;
  443. struct hc32_i2c *i2c_obj;
  444. RT_ASSERT((msgs != RT_NULL) && (bus != RT_NULL));
  445. i2c_obj = rt_container_of(bus, struct hc32_i2c, i2c_bus);
  446. if (num == 0)
  447. {
  448. return 0;
  449. }
  450. for (i = 0; i < num; i++)
  451. {
  452. msg = &msgs[i];
  453. ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
  454. if (!(msg->flags & RT_I2C_NO_START))
  455. {
  456. if (SET == I2C_GetStatus(i2c_obj->config->Instance, I2C_FLAG_BUSY))
  457. {
  458. hc32_hw_i2c_restart(i2c_obj);
  459. }
  460. else
  461. {
  462. hc32_hw_i2c_reset(i2c_obj);
  463. hc32_hw_i2c_start(i2c_obj);
  464. }
  465. /* addr R or W */
  466. ret = hc32_hw_i2c_send_addr(i2c_obj, msg);
  467. if ((ret != RT_EOK) && !ignore_nack)
  468. {
  469. I2C_PRINT_DBG("receive NACK from device addr 0x%02x msg %d", msgs[i].addr, i);
  470. goto out;
  471. }
  472. }
  473. if (msg->flags & RT_I2C_RD)
  474. {
  475. ret = hc32_i2c_read(i2c_obj, msg);
  476. if (ret != RT_EOK)
  477. {
  478. I2C_PRINT_ERR("[%s:%d]I2C Read error!\n", __func__, __LINE__);
  479. goto out;
  480. }
  481. }
  482. else
  483. {
  484. ret = hc32_i2c_write(i2c_obj, msg);
  485. if (ret != RT_EOK)
  486. {
  487. I2C_PRINT_ERR("[%s:%d]I2C Write error!\n", __func__, __LINE__);
  488. goto out;
  489. }
  490. }
  491. }
  492. ret = i;
  493. out:
  494. if (!(msg->flags & RT_I2C_NO_STOP))
  495. {
  496. hc32_hw_i2c_stop(i2c_obj);
  497. I2C_PRINT_DBG("send stop condition\n");
  498. }
  499. return ret;
  500. }
  501. static const struct rt_i2c_bus_device_ops hc32_i2c_ops =
  502. {
  503. .master_xfer = hc32_i2c_master_xfer,
  504. RT_NULL,
  505. RT_NULL
  506. };
  507. int hc32_hw_i2c_init(void)
  508. {
  509. int ret = -RT_ERROR;
  510. rt_size_t obj_num = sizeof(i2c_objs) / sizeof(struct hc32_i2c);
  511. I2C_PRINT_DBG("%s start\n", __func__);
  512. for (int i = 0; i < obj_num; i++)
  513. {
  514. i2c_objs[i].i2c_bus.ops = &hc32_i2c_ops;
  515. i2c_objs[i].config = &i2c_config[i];
  516. i2c_objs[i].i2c_bus.timeout = i2c_config[i].timeout;
  517. hc32_i2c_get_dma_info();
  518. if (i2c_objs[i].i2c_dma_flag & I2C_USING_TX_DMA_FLAG)
  519. {
  520. i2c_objs[i].config->i2c_tx_dma = i2c_config[i].i2c_tx_dma;
  521. }
  522. if ((i2c_objs[i].i2c_dma_flag & I2C_USING_RX_DMA_FLAG))
  523. {
  524. i2c_objs[i].config->i2c_rx_dma = i2c_config[i].i2c_rx_dma;
  525. }
  526. hc32_i2c_configure(&i2c_objs[i].i2c_bus);
  527. ret = rt_i2c_bus_device_register(&i2c_objs[i].i2c_bus, i2c_objs[i].config->name);
  528. RT_ASSERT(ret == RT_EOK);
  529. }
  530. I2C_PRINT_DBG("%s end\n", __func__);
  531. return ret;
  532. }
  533. INIT_BOARD_EXPORT(hc32_hw_i2c_init);
  534. #endif
  535. #endif /* RT_USING_I2C */