drv_usbd.c 26 KB

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  1. /*
  2. * Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2023-02-14 CDT first version
  9. * 2025-07-25 CDT support HC32F4A8
  10. */
  11. /*******************************************************************************
  12. * Include files
  13. ******************************************************************************/
  14. #include <rtthread.h>
  15. #include <rtdevice.h>
  16. #if defined(BSP_USING_USBD)
  17. //#define DRV_DEBUG
  18. #define LOG_TAG "drv.usbd"
  19. #include <drv_log.h>
  20. #include "board_config.h"
  21. #include "irq_config.h"
  22. #include "drv_usbd.h"
  23. #if defined(HC32F472)
  24. #define USBFS_VBUS_INT_PIN (rt_base_t)(((rt_uint16_t)USBF_VBUS_PORT * 16) + __CLZ(__RBIT(USBF_VBUS_PIN)))
  25. #endif
  26. #if !defined(BSP_USING_USBD_HS)
  27. extern rt_err_t rt_hw_usbfs_board_init(void);
  28. #else
  29. extern rt_err_t rt_hw_usbhs_board_init(void);
  30. #endif
  31. extern void rt_hw_us_delay(rt_uint32_t us);
  32. static usb_core_instance _hc32_usbd;
  33. static struct udcd _hc32_udc;
  34. static struct ep_id _ep_pool[] =
  35. {
  36. {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED },
  37. {0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED},
  38. {0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED},
  39. {0x2, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED},
  40. {0x2, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED},
  41. {0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED},
  42. {0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED},
  43. {0x4, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED},
  44. {0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED},
  45. {0x5, USB_EP_ATTR_ISOC, USB_DIR_IN, 64, ID_UNASSIGNED},
  46. {0x5, USB_EP_ATTR_ISOC, USB_DIR_OUT, 64, ID_UNASSIGNED},
  47. #if defined (HC32F4A0) || defined(HC32F4A8)
  48. {0x6, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED},
  49. {0x6, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED},
  50. {0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED},
  51. {0x7, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED},
  52. {0x8, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED},
  53. {0x8, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED},
  54. {0x9, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED},
  55. {0x9, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED},
  56. {0xA, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED},
  57. {0xA, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED},
  58. {0xB, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED},
  59. {0xB, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED},
  60. {0xC, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED},
  61. {0xC, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED},
  62. {0xD, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED},
  63. {0xD, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED},
  64. {0xE, USB_EP_ATTR_ISOC, USB_DIR_IN, 64, ID_UNASSIGNED},
  65. {0xE, USB_EP_ATTR_ISOC, USB_DIR_OUT, 64, ID_UNASSIGNED},
  66. {0xF, USB_EP_ATTR_ISOC, USB_DIR_IN, 64, ID_UNASSIGNED},
  67. {0xF, USB_EP_ATTR_ISOC, USB_DIR_OUT, 64, ID_UNASSIGNED},
  68. #endif
  69. {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED },
  70. };
  71. __WEAK void usb_udelay(const uint32_t usec)
  72. {
  73. rt_hw_us_delay(usec);
  74. }
  75. __WEAK void usb_mdelay(const uint32_t msec)
  76. {
  77. rt_thread_mdelay(msec);
  78. }
  79. static void usb_opendevep(usb_core_instance *pdev, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
  80. {
  81. USB_DEV_EP *ep;
  82. __IO uint8_t tmp_1, tmp_2;
  83. tmp_1 = ep_addr >> 7; /* EP type, it is IN(=1) or OUT(=0) */
  84. tmp_2 = ep_addr & 0x7FU; /* EP number */
  85. if (tmp_1 == 1U)
  86. {
  87. ep = &pdev->dev.in_ep[tmp_2];
  88. }
  89. else
  90. {
  91. ep = &pdev->dev.out_ep[tmp_2];
  92. }
  93. ep->epidx = tmp_2;
  94. ep->ep_dir = tmp_1;
  95. ep->maxpacket = ep_mps;
  96. ep->trans_type = ep_type;
  97. if (tmp_1 == 1U)
  98. {
  99. /* Assign a Tx FIFO */
  100. ep->tx_fifo_num = tmp_2;
  101. }
  102. /* Set initial data PID. */
  103. if (ep_type == EP_TYPE_BULK)
  104. {
  105. ep->data_pid_start = 0U;
  106. }
  107. usb_epactive(&pdev->regs, ep);
  108. }
  109. static void usb_shutdevep(usb_core_instance *pdev, uint8_t ep_addr)
  110. {
  111. USB_DEV_EP *ep;
  112. __IO uint8_t tmp_1, tmp_2;
  113. tmp_1 = ep_addr >> 7; /* EP type, it is IN(=1) or OUT(=0) */
  114. tmp_2 = ep_addr & 0x7FU; /* EP number */
  115. if (tmp_1 == 1U)
  116. {
  117. ep = &pdev->dev.in_ep[tmp_2];
  118. }
  119. else
  120. {
  121. ep = &pdev->dev.out_ep[tmp_2];
  122. }
  123. ep->epidx = tmp_2;
  124. ep->ep_dir = tmp_1;
  125. usb_epdeactive(&pdev->regs, ep);
  126. }
  127. static void usb_readytorx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len)
  128. {
  129. USB_DEV_EP *ep;
  130. __IO uint8_t tmp_1;
  131. tmp_1 = ep_addr & 0x7FU; /* EP number */
  132. ep = &pdev->dev.out_ep[tmp_1];
  133. /* setup and start the Xfer */
  134. ep->xfer_buff = pbuf;
  135. ep->xfer_len = (uint32_t)buf_len;
  136. ep->xfer_count = 0UL;
  137. ep->ep_dir = 0U;
  138. ep->epidx = tmp_1;
  139. if (pdev->basic_cfgs.dmaen == 1U)
  140. {
  141. ep->dma_addr = (uint32_t)pbuf;
  142. }
  143. if (tmp_1 == 0U)
  144. {
  145. usb_ep0transbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen);
  146. }
  147. else
  148. {
  149. usb_epntransbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen);
  150. }
  151. }
  152. static void usb_deveptx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint32_t buf_len)
  153. {
  154. USB_DEV_EP *ep;
  155. __IO uint8_t tmp_1;
  156. tmp_1 = ep_addr & 0x7FU; /* EP number */
  157. ep = &pdev->dev.in_ep[tmp_1];
  158. /* Setup and start the Transfer */
  159. ep->ep_dir = 1U;
  160. ep->epidx = tmp_1;
  161. ep->xfer_buff = pbuf;
  162. ep->dma_addr = (uint32_t)pbuf;
  163. ep->xfer_count = 0UL;
  164. ep->xfer_len = buf_len;
  165. if (tmp_1 == 0U)
  166. {
  167. usb_ep0transbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen);
  168. }
  169. else
  170. {
  171. usb_epntransbegin(&pdev->regs, ep, pdev->basic_cfgs.dmaen);
  172. }
  173. }
  174. static void usb_stalldevep(usb_core_instance *pdev, uint8_t epnum)
  175. {
  176. USB_DEV_EP *ep;
  177. __IO uint8_t tmp_1, tmp_2;
  178. tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */
  179. tmp_2 = epnum & 0x7FU; /* EP number */
  180. if (tmp_1 != 0U)
  181. {
  182. ep = &pdev->dev.in_ep[tmp_2];
  183. }
  184. else
  185. {
  186. ep = &pdev->dev.out_ep[tmp_2];
  187. }
  188. ep->ep_stall = 1U;
  189. ep->epidx = tmp_2;
  190. if (tmp_1 != 0U)
  191. {
  192. ep->ep_dir = 1U;
  193. }
  194. else
  195. {
  196. ep->ep_dir = 0U;
  197. }
  198. usb_setepstall(&pdev->regs, ep);
  199. }
  200. static void usb_clrstall(usb_core_instance *pdev, uint8_t epnum)
  201. {
  202. USB_DEV_EP *ep;
  203. __IO uint8_t tmp_1, tmp_2;
  204. tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */
  205. tmp_2 = epnum & 0x7FU; /* EP number */
  206. if (tmp_1 != 0U)
  207. {
  208. ep = &pdev->dev.in_ep[tmp_2];
  209. }
  210. else
  211. {
  212. ep = &pdev->dev.out_ep[tmp_2];
  213. }
  214. ep->ep_stall = 0U;
  215. ep->epidx = tmp_2;
  216. if (tmp_1 != 0U)
  217. {
  218. ep->ep_dir = 1U;
  219. }
  220. else
  221. {
  222. ep->ep_dir = 0U;
  223. }
  224. usb_clearepstall(&pdev->regs, ep);
  225. }
  226. static void usb_dev_rst(usb_core_instance *pdev)
  227. {
  228. usb_opendevep(pdev, 0x00U, USB_MAX_EP0_SIZE, EP_TYPE_CTRL);
  229. usb_opendevep(pdev, 0x80U, USB_MAX_EP0_SIZE, EP_TYPE_CTRL);
  230. rt_usbd_reset_handler(&_hc32_udc);
  231. LOG_D("USB Reset");
  232. }
  233. static void usb_ctrlconn(usb_core_instance *pdev, uint8_t conn)
  234. {
  235. __IO uint8_t tmp_1;
  236. tmp_1 = conn;
  237. if (tmp_1 != 0U)
  238. {
  239. rt_usbd_connect_handler(&_hc32_udc);
  240. LOG_D("USB Connect");
  241. }
  242. else
  243. {
  244. rt_usbd_disconnect_handler(&_hc32_udc);
  245. LOG_D("USB Disconnect");
  246. }
  247. }
  248. static void usb_dev_susp(usb_core_instance *pdev)
  249. {
  250. LOG_D("USB Suspend");
  251. }
  252. static void usb_dev_resume(usb_core_instance *pdev)
  253. {
  254. LOG_D("USB Resume");
  255. }
  256. static void usb_sof_process(usb_core_instance *pdev)
  257. {
  258. rt_usbd_sof_handler(&_hc32_udc);
  259. }
  260. static void usb_setup_process(usb_core_instance *pdev)
  261. {
  262. rt_usbd_ep0_setup_handler(&_hc32_udc, (struct urequest *)pdev->dev.setup_pkt_buf);
  263. }
  264. static void usb_dataout_process(usb_core_instance *pdev, uint8_t epnum)
  265. {
  266. if (epnum != 0)
  267. {
  268. rt_usbd_ep_out_handler(&_hc32_udc, epnum, pdev->dev.out_ep[epnum].xfer_count);
  269. }
  270. else
  271. {
  272. rt_usbd_ep0_out_handler(&_hc32_udc, pdev->dev.out_ep[0].xfer_count);
  273. }
  274. }
  275. static void usb_datain_process(usb_core_instance *pdev, uint8_t epnum)
  276. {
  277. if (epnum == 0)
  278. {
  279. rt_usbd_ep0_in_handler(&_hc32_udc);
  280. }
  281. else
  282. {
  283. rt_usbd_ep_in_handler(&_hc32_udc, 0x80 | epnum, pdev->dev.in_ep[epnum].xfer_count);
  284. }
  285. }
  286. static void usb_isoinincomplt_process(usb_core_instance *pdev)
  287. {
  288. /* reserved */
  289. }
  290. static void usb_isooutincomplt_process(usb_core_instance *pdev)
  291. {
  292. /* reserved */
  293. }
  294. static usb_dev_int_cbk_typedef dev_int_cbk =
  295. {
  296. &usb_dev_rst,
  297. &usb_ctrlconn,
  298. &usb_dev_susp,
  299. &usb_dev_resume,
  300. &usb_sof_process,
  301. &usb_setup_process,
  302. &usb_dataout_process,
  303. &usb_datain_process,
  304. &usb_isoinincomplt_process,
  305. &usb_isooutincomplt_process
  306. };
  307. static usb_dev_int_cbk_typedef *dev_int_cbkpr = &dev_int_cbk;
  308. static uint32_t usb_rddevinep(usb_core_instance *pdev, uint8_t epnum)
  309. {
  310. uint32_t u32diepmsk;
  311. uint32_t u32diepempmsk;
  312. u32diepmsk = READ_REG32(pdev->regs.DREGS->DIEPMSK);
  313. u32diepempmsk = READ_REG32(pdev->regs.DREGS->DIEPEMPMSK);
  314. u32diepmsk |= (((u32diepempmsk >> epnum) & 0x1UL) << 7U);
  315. return (READ_REG32(pdev->regs.INEP_REGS[epnum]->DIEPINT) & u32diepmsk);
  316. }
  317. static void usb_wrblanktxfifo(usb_core_instance *pdev, uint32_t epnum)
  318. {
  319. USB_DEV_EP *ep;
  320. uint32_t u32Len;
  321. uint32_t u32Len32b;
  322. uint16_t u16spclen;
  323. uint32_t u32diepempmsk;
  324. ep = &pdev->dev.in_ep[epnum];
  325. u32Len = ep->xfer_len - ep->xfer_count;
  326. if (u32Len > ep->maxpacket)
  327. {
  328. u32Len = ep->maxpacket;
  329. }
  330. u32Len32b = (u32Len + 3UL) >> 2;
  331. u16spclen = usb_rdineptxfspcavail(pdev, epnum);
  332. while ((u16spclen >= u32Len32b) && (ep->xfer_count < ep->xfer_len))
  333. {
  334. u32Len = ep->xfer_len - ep->xfer_count;
  335. if (u32Len > ep->maxpacket)
  336. {
  337. u32Len = ep->maxpacket;
  338. }
  339. u32Len32b = (u32Len + 3UL) >> 2;
  340. usb_wrpkt(&pdev->regs, ep->xfer_buff, (uint8_t)epnum, (uint16_t)u32Len, pdev->basic_cfgs.dmaen);
  341. ep->xfer_buff += u32Len;
  342. ep->xfer_count += u32Len;
  343. u16spclen = usb_rdineptxfspcavail(pdev, epnum);
  344. }
  345. if (u32Len == 0UL)
  346. {
  347. u32diepempmsk = 0x01UL << epnum;
  348. CLR_REG32_BIT(pdev->regs.DREGS->DIEPEMPMSK, u32diepempmsk);
  349. }
  350. }
  351. #if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F4A8)
  352. #ifdef VBUS_SENSING_ENABLED
  353. static void usb_sessionrequest_isr(usb_core_instance *pdev)
  354. {
  355. dev_int_cbkpr->devctrlconnect(pdev, 1U);
  356. WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_VBUSVINT);
  357. if (0U != pdev->basic_cfgs.low_power)
  358. {
  359. CLR_REG32_BIT(*pdev->regs.GCCTL, USBFS_GCCTL_STPPCLK | USBFS_GCCTL_GATEHCLK);
  360. }
  361. }
  362. #endif
  363. #endif
  364. static void usb_resume_isr(usb_core_instance *pdev)
  365. {
  366. if (0U != pdev->basic_cfgs.low_power)
  367. {
  368. CLR_REG32_BIT(*pdev->regs.GCCTL, USBFS_GCCTL_STPPCLK | USBFS_GCCTL_GATEHCLK);
  369. }
  370. CLR_REG32_BIT(pdev->regs.DREGS->DCTL, USBFS_DCTL_RWUSIG);
  371. dev_int_cbkpr->Resume(pdev);
  372. WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_WKUINT);
  373. }
  374. static void usb_susp_isr(usb_core_instance *pdev)
  375. {
  376. uint32_t u32dsts;
  377. u32dsts = READ_REG32(pdev->regs.DREGS->DSTS);
  378. if ((u32dsts & 1UL) != 0UL)
  379. {
  380. dev_int_cbkpr->Suspend(pdev);
  381. }
  382. WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_USBSUSP);
  383. }
  384. static void usb_inep_isr(usb_core_instance *pdev)
  385. {
  386. uint32_t u32diepint;
  387. uint32_t u32EpIntr;
  388. uint8_t u8epnum;
  389. uint32_t u32diepempmsk;
  390. u32EpIntr = usb_getalliepintr(&pdev->regs);
  391. u8epnum = 0U;
  392. while ((0U != u32EpIntr) && (u8epnum < USB_MAX_TX_FIFOS))
  393. {
  394. if ((u32EpIntr & 0x1UL) != 0UL)
  395. {
  396. u32diepint = usb_rddevinep(pdev, u8epnum);
  397. if ((u32diepint & XFER_COMPL) != 0UL)
  398. {
  399. u32diepempmsk = 1UL << u8epnum;
  400. CLR_REG32_BIT(pdev->regs.DREGS->DIEPEMPMSK, u32diepempmsk);
  401. WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, XFER_COMPL);
  402. dev_int_cbkpr->DataInStage(pdev, u8epnum);
  403. if (pdev->basic_cfgs.dmaen == 1U)
  404. {
  405. if ((pdev->dev.device_state == USB_EP0_STATUS_IN) && (u8epnum == 0U))
  406. {
  407. pdev->dev.out_ep[0].xfer_len = 64U;
  408. pdev->dev.out_ep[0].rem_data_len = 64U;
  409. pdev->dev.out_ep[0].total_data_len = 64U;
  410. usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf);
  411. pdev->dev.device_state = USB_EP0_IDLE;
  412. }
  413. }
  414. }
  415. if ((u32diepint & EPDISABLED) != 0UL)
  416. {
  417. WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, EPDISABLED);
  418. }
  419. if ((u32diepint & TIME_OUT) != 0UL)
  420. {
  421. WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, TIME_OUT);
  422. }
  423. if ((u32diepint & INTKNTXFEMP) != 0UL)
  424. {
  425. WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, INTKNTXFEMP);
  426. }
  427. if ((u32diepint & INEPNAKEFF) != 0UL)
  428. {
  429. WRITE_REG32(pdev->regs.INEP_REGS[u8epnum]->DIEPINT, INEPNAKEFF);
  430. }
  431. if ((u32diepint & TXFEMP) != 0UL)
  432. {
  433. usb_wrblanktxfifo(pdev, u8epnum);
  434. }
  435. }
  436. u8epnum++;
  437. u32EpIntr >>= 1U;
  438. }
  439. }
  440. static void usb_outep_isr(usb_core_instance *pdev)
  441. {
  442. uint32_t u32EpIntr;
  443. uint32_t u32doepint;
  444. uint8_t u8epnum = 0U;
  445. uint32_t u32Xfer;
  446. uint32_t u32ReadEpSize;
  447. u32EpIntr = usb_getalloepintr(&pdev->regs);
  448. while ((u32EpIntr != 0UL) && (u8epnum < USB_MAX_TX_FIFOS))
  449. {
  450. if ((u32EpIntr & 0x1UL) != 0UL)
  451. {
  452. u32doepint = usb_getoepintbit(&pdev->regs, u8epnum);
  453. if ((u32doepint & XFER_COMPL) != 0UL)
  454. {
  455. WRITE_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPINT, XFER_COMPL);
  456. if (pdev->basic_cfgs.dmaen == 1U)
  457. {
  458. u32ReadEpSize = (READ_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPTSIZ) & USBFS_DOEPTSIZ_XFRSIZ);
  459. u32Xfer = LL_MIN(pdev->dev.out_ep[u8epnum].maxpacket, pdev->dev.out_ep[u8epnum].xfer_len);
  460. pdev->dev.out_ep[u8epnum].xfer_count = u32Xfer - u32ReadEpSize;
  461. if (u8epnum != 0U)
  462. {
  463. pdev->dev.out_ep[u8epnum].xfer_count = pdev->dev.out_ep[u8epnum].xfer_len - u32ReadEpSize;
  464. }
  465. }
  466. dev_int_cbkpr->DataOutStage(pdev, u8epnum);
  467. if (pdev->basic_cfgs.dmaen == 1U)
  468. {
  469. if ((pdev->dev.device_state == USB_EP0_STATUS_OUT) && (u8epnum == 0U))
  470. {
  471. pdev->dev.out_ep[0].xfer_len = 64U;
  472. pdev->dev.out_ep[0].rem_data_len = 64U;
  473. pdev->dev.out_ep[0].total_data_len = 64U;
  474. usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf);
  475. pdev->dev.device_state = USB_EP0_IDLE;
  476. }
  477. }
  478. }
  479. if ((u32doepint & EPDISABLED) != 0UL)
  480. {
  481. WRITE_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPINT, EPDISABLED);
  482. }
  483. if (u8epnum == 0U)
  484. {
  485. u32doepint = usb_getoepintbit(&pdev->regs, u8epnum);
  486. if ((u32doepint & SETUP_BIT) != 0UL)
  487. {
  488. dev_int_cbkpr->SetupStage(pdev);
  489. WRITE_REG32(pdev->regs.OUTEP_REGS[u8epnum]->DOEPINT, SETUP_BIT);
  490. }
  491. }
  492. }
  493. u8epnum++;
  494. u32EpIntr >>= 1U;
  495. }
  496. }
  497. static void usb_sof_isr(usb_core_instance *pdev)
  498. {
  499. dev_int_cbkpr->SOF(pdev);
  500. WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_SOF);
  501. }
  502. static void usb_rxstsqlvl_isr(usb_core_instance *pdev)
  503. {
  504. uint32_t u32grxsts;
  505. USB_DEV_EP *ep;
  506. uint8_t u8epnum;
  507. uint8_t u8PktStatus;
  508. uint16_t u16ByteCnt;
  509. CLR_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTMSK_RXFNEM);
  510. u32grxsts = READ_REG32(pdev->regs.GREGS->GRXSTSP);
  511. u8epnum = (uint8_t)(u32grxsts & USBFS_GRXSTSP_CHNUM_EPNUM);
  512. u8PktStatus = (uint8_t)((u32grxsts & USBFS_GRXSTSP_PKTSTS) >> USBFS_GRXSTSP_PKTSTS_POS);
  513. u16ByteCnt = (uint16_t)((u32grxsts & USBFS_GRXSTSP_BCNT) >> USBFS_GRXSTSP_BCNT_POS);
  514. ep = &pdev->dev.out_ep[u8epnum];
  515. switch (u8PktStatus)
  516. {
  517. case STS_DATA_UPDT:
  518. if (0U != u16ByteCnt)
  519. {
  520. RT_ASSERT(RT_IS_ALIGN((uint32_t)ep->xfer_buff, 4UL));
  521. usb_rdpkt(&pdev->regs, ep->xfer_buff, u16ByteCnt);
  522. ep->xfer_buff += u16ByteCnt;
  523. ep->xfer_count += u16ByteCnt;
  524. }
  525. else
  526. {
  527. ;
  528. }
  529. break;
  530. case STS_SETUP_UPDT:
  531. /* Copy the setup packet received in FIFO into the setup buffer in RAM */
  532. usb_rdpkt(&pdev->regs, pdev->dev.setup_pkt_buf, 8U);
  533. ep->xfer_count += u16ByteCnt;
  534. break;
  535. case STS_GOUT_NAK:
  536. case STS_XFER_COMP:
  537. case STS_SETUP_COMP:
  538. break;
  539. default:
  540. break;
  541. }
  542. SET_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTMSK_RXFNEM);
  543. }
  544. static void usb_reset_isr(usb_core_instance *pdev)
  545. {
  546. uint32_t i;
  547. CLR_REG32_BIT(pdev->regs.DREGS->DCTL, USBFS_DCTL_RWUSIG);
  548. usb_txfifoflush(&pdev->regs, 0UL);
  549. for (i = 0UL; i < pdev->basic_cfgs.dev_epnum ; i++)
  550. {
  551. WRITE_REG32(pdev->regs.INEP_REGS[i]->DIEPINT, 0xFFUL);
  552. WRITE_REG32(pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFFUL);
  553. }
  554. WRITE_REG32(pdev->regs.DREGS->DAINT, 0xFFFFFFFFUL);
  555. WRITE_REG32(pdev->regs.DREGS->DAINTMSK, 1UL | (1UL << USBFS_DAINTMSK_OEPINTM_POS));
  556. WRITE_REG32(pdev->regs.DREGS->DOEPMSK, USBFS_DOEPMSK_STUPM | USBFS_DOEPMSK_XFRCM | USBFS_DOEPMSK_EPDM);
  557. #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
  558. WRITE_REG32(pdev->regs.DREGS->DOUTEP1MSK, USBFS_DOEPMSK_STUPM | USBFS_DOEPMSK_XFRCM | USBFS_DOEPMSK_EPDM);
  559. #endif
  560. WRITE_REG32(pdev->regs.DREGS->DIEPMSK, USBFS_DIEPMSK_XFRCM | USBFS_DIEPMSK_TOM | USBFS_DIEPMSK_EPDM);
  561. #ifdef USB_OTG_HS_DEDICATED_EP1_ENABLED
  562. WRITE_REG32(pdev->regs.DREGS->DINEP1MSK, USBFS_DIEPMSK_XFRCM | USBFS_DIEPMSK_TOM | USBFS_DIEPMSK_EPDM);
  563. #endif
  564. CLR_REG32_BIT(pdev->regs.DREGS->DCFG, USBFS_DCFG_DAD);
  565. pdev->dev.out_ep[0].xfer_len = 64U;
  566. pdev->dev.out_ep[0].rem_data_len = 64U;
  567. pdev->dev.out_ep[0].total_data_len = 64U;
  568. usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf);
  569. WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_USBRST);
  570. dev_int_cbkpr->Reset(pdev);
  571. }
  572. static void usb_enumfinish_isr(usb_core_instance *pdev)
  573. {
  574. usb_ep0activate(&pdev->regs);
  575. usb_setaroundtim(pdev);
  576. WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_ENUMDNE);
  577. }
  578. static void usb_isoinincomplt_isr(usb_core_instance *pdev)
  579. {
  580. dev_int_cbkpr->IsoINIncomplete(pdev);
  581. WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_IISOIXFR);
  582. }
  583. static void usb_isooutincomplt_isr(usb_core_instance *pdev)
  584. {
  585. dev_int_cbkpr->IsoOUTIncomplete(pdev);
  586. WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_IPXFR_INCOMPISOOUT);
  587. }
  588. static void usb_isr_handler(usb_core_instance *pdev)
  589. {
  590. uint32_t u32gintsts;
  591. if (0U == usb_getcurmod(&pdev->regs))
  592. {
  593. u32gintsts = usb_getcoreintr(&pdev->regs);
  594. if (u32gintsts == 0UL)
  595. {
  596. return;
  597. }
  598. if ((u32gintsts & OUTEP_INT) != 0UL)
  599. {
  600. usb_outep_isr(pdev);
  601. }
  602. if ((u32gintsts & INEP_INT) != 0UL)
  603. {
  604. usb_inep_isr(pdev);
  605. }
  606. if ((u32gintsts & MODEMIS_INT) != 0UL)
  607. {
  608. WRITE_REG32(pdev->regs.GREGS->GINTSTS, MODEMIS_INT);
  609. }
  610. if ((u32gintsts & WAKEUP_INT) != 0UL)
  611. {
  612. usb_resume_isr(pdev);
  613. }
  614. if ((u32gintsts & USBSUSP_INT) != 0UL)
  615. {
  616. usb_susp_isr(pdev);
  617. }
  618. if ((u32gintsts & SOF_INT) != 0UL)
  619. {
  620. usb_sof_isr(pdev);
  621. }
  622. if ((u32gintsts & RXFLVL_INT) != 0UL)
  623. {
  624. usb_rxstsqlvl_isr(pdev);
  625. }
  626. if ((u32gintsts & USBRST_INT) != 0UL)
  627. {
  628. usb_reset_isr(pdev);
  629. }
  630. if ((u32gintsts & ENUMDONE_INT) != 0UL)
  631. {
  632. usb_enumfinish_isr(pdev);
  633. }
  634. if ((u32gintsts & INCOMPLSOIN) != 0UL)
  635. {
  636. usb_isoinincomplt_isr(pdev);
  637. }
  638. if ((u32gintsts & INCOMPLSOOUT) != 0UL)
  639. {
  640. usb_isooutincomplt_isr(pdev);
  641. }
  642. #if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F4A8)
  643. #ifdef VBUS_SENSING_ENABLED
  644. if ((u32gintsts & VBUSV_INT) != 0UL)
  645. {
  646. usb_sessionrequest_isr(pdev);
  647. }
  648. #endif
  649. #endif
  650. }
  651. }
  652. static void usbd_irq_handler(void)
  653. {
  654. rt_interrupt_enter();
  655. usb_isr_handler(&_hc32_usbd);
  656. rt_interrupt_leave();
  657. }
  658. #if defined(HC32F472)
  659. void USBFS_Handler(void)
  660. {
  661. usbd_irq_handler();
  662. }
  663. #ifdef VBUS_SENSING_ENABLED
  664. static void vbus_irq_handler(void *args)
  665. {
  666. if (PIN_LOW == rt_pin_read(USBFS_VBUS_INT_PIN))
  667. {
  668. SET_REG32_BIT(_hc32_usbd.regs.DREGS->DCTL, USBFS_DCTL_SDIS);
  669. }
  670. else
  671. {
  672. CLR_REG32_BIT(_hc32_usbd.regs.DREGS->DCTL, USBFS_DCTL_SDIS);
  673. }
  674. }
  675. #endif
  676. #endif
  677. static rt_err_t _usbd_ep_set_stall(rt_uint8_t address)
  678. {
  679. usb_stalldevep(&_hc32_usbd, address);
  680. return RT_EOK;
  681. }
  682. static rt_err_t _usbd_ep_clear_stall(rt_uint8_t address)
  683. {
  684. usb_clrstall(&_hc32_usbd, address);
  685. return RT_EOK;
  686. }
  687. static rt_err_t _usbd_set_address(rt_uint8_t address)
  688. {
  689. usb_devaddrset(&_hc32_usbd.regs, address);
  690. return RT_EOK;
  691. }
  692. static rt_err_t _usbd_set_config(rt_uint8_t address)
  693. {
  694. return RT_EOK;
  695. }
  696. static rt_err_t _usbd_ep_enable(uep_t ep)
  697. {
  698. RT_ASSERT(ep != RT_NULL);
  699. RT_ASSERT(ep->ep_desc != RT_NULL);
  700. usb_opendevep(&_hc32_usbd, ep->ep_desc->bEndpointAddress,
  701. ep->ep_desc->wMaxPacketSize, ep->ep_desc->bmAttributes);
  702. return RT_EOK;
  703. }
  704. static rt_err_t _usbd_ep_disable(uep_t ep)
  705. {
  706. RT_ASSERT(ep != RT_NULL);
  707. RT_ASSERT(ep->ep_desc != RT_NULL);
  708. usb_shutdevep(&_hc32_usbd, ep->ep_desc->bEndpointAddress);
  709. return RT_EOK;
  710. }
  711. static rt_ssize_t _usbd_ep_read(rt_uint8_t address, void *buffer)
  712. {
  713. rt_size_t size = 0;
  714. RT_ASSERT(buffer != RT_NULL);
  715. return size;
  716. }
  717. static rt_ssize_t _usbd_ep_read_prepare(rt_uint8_t address, void *buffer, rt_size_t size)
  718. {
  719. usb_readytorx(&_hc32_usbd, address, buffer, size);
  720. return size;
  721. }
  722. static rt_ssize_t _usbd_ep_write(rt_uint8_t address, void *buffer, rt_size_t size)
  723. {
  724. usb_deveptx(&_hc32_usbd, address, buffer, size);
  725. return size;
  726. }
  727. static rt_err_t _usbd_ep0_send_status(void)
  728. {
  729. usb_deveptx(&_hc32_usbd, 0x00, NULL, 0);
  730. return RT_EOK;
  731. }
  732. static rt_err_t _usbd_suspend(void)
  733. {
  734. return RT_EOK;
  735. }
  736. static rt_err_t _usbd_wakeup(void)
  737. {
  738. return RT_EOK;
  739. }
  740. static rt_err_t _usbd_init(rt_device_t device)
  741. {
  742. usb_core_instance *pdev;
  743. stc_usb_port_identify stcPortIdentify;
  744. struct hc32_irq_config irq_config;
  745. pdev = (usb_core_instance *)device->user_data;
  746. #if !defined(BSP_USING_USBD_HS)
  747. rt_hw_usbfs_board_init();
  748. FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBFS, ENABLE);
  749. #else
  750. rt_hw_usbhs_board_init();
  751. FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_USBHS, ENABLE);
  752. #endif
  753. /* Parameters */
  754. #if !defined(BSP_USING_USBD_HS)
  755. stcPortIdentify.u8CoreID = USBFS_CORE_ID;
  756. #else
  757. stcPortIdentify.u8CoreID = USBHS_CORE_ID;
  758. #endif
  759. #if defined (HC32F4A0) || defined(HC32F4A8)
  760. #if !defined(BSP_USING_USBHS_PHY_EXTERN)
  761. stcPortIdentify.u8PhyType = USBHS_PHY_EMBED;
  762. #else
  763. stcPortIdentify.u8PhyType = USBHS_PHY_EXT;
  764. #endif
  765. #endif
  766. usb_setregaddr(&pdev->regs, &stcPortIdentify, &pdev->basic_cfgs);
  767. usb_gintdis(&pdev->regs);
  768. /*Init the Core (common init.) */
  769. usb_initusbcore(&pdev->regs, &pdev->basic_cfgs);
  770. /* Force Device Mode*/
  771. usb_modeset(&pdev->regs, DEVICE_MODE);
  772. /* Init Device */
  773. usb_devmodeinit(&pdev->regs, &pdev->basic_cfgs);
  774. /* Enable USB Global interrupt */
  775. usb_ginten(&pdev->regs);
  776. /* NVIC Config */
  777. #if !defined(BSP_USING_USBD_HS)
  778. irq_config.irq_num = BSP_USBFS_GLB_IRQ_NUM;
  779. irq_config.int_src = INT_SRC_USBFS_GLB;
  780. irq_config.irq_prio = BSP_USBFS_GLB_IRQ_PRIO;
  781. #else
  782. irq_config.irq_num = BSP_USBHS_GLB_IRQ_NUM;
  783. irq_config.int_src = INT_SRC_USBHS_GLB;
  784. irq_config.irq_prio = BSP_USBHS_GLB_IRQ_PRIO;
  785. #endif
  786. /* register interrupt */
  787. hc32_install_irq_handler(&irq_config,
  788. usbd_irq_handler,
  789. RT_TRUE);
  790. #if defined(HC32F472)
  791. #ifdef VBUS_SENSING_ENABLED
  792. /* VBUS Extint config */
  793. rt_pin_mode(USBFS_VBUS_INT_PIN, PIN_MODE_INPUT);
  794. rt_pin_attach_irq(USBFS_VBUS_INT_PIN, PIN_IRQ_MODE_RISING_FALLING, vbus_irq_handler, (void *)"callbackargs");
  795. rt_pin_irq_enable(USBFS_VBUS_INT_PIN, PIN_IRQ_ENABLE);
  796. #endif
  797. #endif
  798. return RT_EOK;
  799. }
  800. const static struct udcd_ops _udc_ops =
  801. {
  802. _usbd_set_address,
  803. _usbd_set_config,
  804. _usbd_ep_set_stall,
  805. _usbd_ep_clear_stall,
  806. _usbd_ep_enable,
  807. _usbd_ep_disable,
  808. _usbd_ep_read_prepare,
  809. _usbd_ep_read,
  810. _usbd_ep_write,
  811. _usbd_ep0_send_status,
  812. _usbd_suspend,
  813. _usbd_wakeup,
  814. };
  815. #ifdef RT_USING_DEVICE_OPS
  816. const static struct rt_device_ops _ops =
  817. {
  818. _usbd_init,
  819. RT_NULL,
  820. RT_NULL,
  821. RT_NULL,
  822. RT_NULL,
  823. RT_NULL,
  824. };
  825. #endif
  826. int rt_hw_usbd_init(void)
  827. {
  828. rt_memset((void *)&_hc32_udc, 0, sizeof(struct udcd));
  829. _hc32_udc.parent.type = RT_Device_Class_USBDevice;
  830. #ifdef RT_USING_DEVICE_OPS
  831. _hc32_udc.parent.ops = &_ops;
  832. #else
  833. _hc32_udc.parent.init = _usbd_init;
  834. #endif
  835. _hc32_udc.parent.user_data = &_hc32_usbd;
  836. _hc32_udc.ops = &_udc_ops;
  837. /* Register endpoint infomation */
  838. _hc32_udc.ep_pool = _ep_pool;
  839. _hc32_udc.ep0.id = &_ep_pool[0];
  840. #ifdef BSP_USBD_SPEED_HS
  841. _hc32_udc.device_is_hs = RT_TRUE;
  842. #endif
  843. rt_device_register((rt_device_t)&_hc32_udc, "usbd", 0);
  844. rt_usb_device_init();
  845. return RT_EOK;
  846. }
  847. INIT_DEVICE_EXPORT(rt_hw_usbd_init);
  848. #endif /* BSP_USING_USBD */