test_pm.c 16 KB

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  1. /*
  2. * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2024-12-30 CDT first version
  9. */
  10. /*
  11. * 功能
  12. * 程序清单:这是一个 PM 设备使用例程
  13. * 例程导出了 pm_sample_init 命令到控制终端
  14. * 命令调用格式:pm_sample_init
  15. *
  16. * 展示RTT休眠模式的进入和退出
  17. * hc32 drv_pm 支持的RTT休眠模式包括: idle、deep、standby、shutdown
  18. * 每种休眠模式与芯片低功耗模式的对应关系是:
  19. * RTT | HC32
  20. * -----------------------|----------
  21. * PM_SLEEP_MODE_IDLE | 睡眠模式
  22. * PM_SLEEP_MODE_DEEP | 停止模式
  23. * PM_SLEEP_MODE_STANDBY | 掉电模式1或2(可配,默认配置是模式1)
  24. * PM_SLEEP_MODE_SHUTDOWN | 掉电模式3或4(可配,默认配置是模式3)
  25. *
  26. * 操作步骤1:
  27. * 1)按下WKUP按键: MCU进入休眠模式
  28. * 2)再按下WKUP按键:MCU退出休眠模式
  29. * 3)重复上述按键操作,MCU循环进入休眠模式(deep、standby、shutdown、idle)和退出对应的休眠模式。
  30. * 每次进入休眠模式前,MCU打印 "sleep:" + 休眠模式名称
  31. * 每次退出休眠模式后,MCU打印 "wake from sleep:" + 休眠模式名称
  32. * 操作步骤2:
  33. * 1)支持运行模式切换的芯片循环切换 低速->高速->低速 运行模式,对应时钟输出口输出对应模式下的时钟信号
  34. */
  35. #include <rtthread.h>
  36. #include <rtdevice.h>
  37. #include <board.h>
  38. #include <drivers/lptimer.h>
  39. #if defined(BSP_USING_PM)
  40. #if defined (HC32F4A0) || defined (HC32F4A8)
  41. #define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS)
  42. #define BSP_KEY_PORT (GPIO_PORT_A)
  43. #define BSP_KEY_PIN (GPIO_PIN_00)
  44. #define BSP_KEY_EXTINT (EXTINT_CH00)
  45. #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ0)
  46. #define BSP_KEY_IRQn (INT001_IRQn)
  47. #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH0)
  48. #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ0)
  49. #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP0)
  50. #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP00)
  51. #define LED_GREEN_PORT (GPIO_PORT_C)
  52. #define LED_GREEN_PIN (GPIO_PIN_09)
  53. #define MCO_PORT (GPIO_PORT_A)
  54. #define MCO_PIN (GPIO_PIN_08)
  55. #define MCO_GPIO_FUNC (GPIO_FUNC_1)
  56. #elif defined (HC32F460)
  57. #define PLL_SRC ((CM_CMU->PLLCFGR & CMU_PLLCFGR_PLLSRC) >> CMU_PLLCFGR_PLLSRC_POS)
  58. #define BSP_KEY_PORT (GPIO_PORT_B) /* Key10 */
  59. #define BSP_KEY_PIN (GPIO_PIN_01)
  60. #define BSP_KEY_EXTINT (EXTINT_CH01)
  61. #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ1)
  62. #define BSP_KEY_IRQn (INT001_IRQn)
  63. #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH1)
  64. #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ1)
  65. #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1)
  66. #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP01)
  67. #define LED_GREEN_PORT (GPIO_PORT_D)
  68. #define LED_GREEN_PIN (GPIO_PIN_04)
  69. #define MCO_PORT (GPIO_PORT_A)
  70. #define MCO_PIN (GPIO_PIN_08)
  71. #define MCO_GPIO_FUNC (GPIO_FUNC_1)
  72. #elif defined (HC32F448)
  73. #define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS)
  74. #define BSP_KEY_PORT (GPIO_PORT_B) /* Key5 */
  75. #define BSP_KEY_PIN (GPIO_PIN_06)
  76. #define BSP_KEY_EXTINT (EXTINT_CH06)
  77. #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ6)
  78. #define BSP_KEY_IRQn (INT001_IRQn)
  79. #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH6)
  80. #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ6)
  81. #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1)
  82. #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP12)
  83. #define LED_GREEN_PORT (GPIO_PORT_A)
  84. #define LED_GREEN_PIN (GPIO_PIN_02)
  85. #define MCO_PORT (GPIO_PORT_A)
  86. #define MCO_PIN (GPIO_PIN_08)
  87. #define MCO_GPIO_FUNC (GPIO_FUNC_1)
  88. #elif defined (HC32F472)
  89. #define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS)
  90. #define BSP_KEY_PORT (GPIO_PORT_B) /* Key5 */
  91. #define BSP_KEY_PIN (GPIO_PIN_05)
  92. #define BSP_KEY_EXTINT (EXTINT_CH05)
  93. #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ5)
  94. #define BSP_KEY_IRQn (INT001_IRQn)
  95. #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH5)
  96. #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ5)
  97. #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1)
  98. #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP11)
  99. #define LED_GREEN_PORT (GPIO_PORT_C)
  100. #define LED_GREEN_PIN (GPIO_PIN_09)
  101. #elif defined (HC32F334)
  102. #define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS)
  103. #define BSP_KEY_PORT (GPIO_PORT_B) /* Key5 */
  104. #define BSP_KEY_PIN (GPIO_PIN_09)
  105. #define BSP_KEY_EXTINT (EXTINT_CH09)
  106. #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ9)
  107. #define BSP_KEY_IRQn (INT001_IRQn)
  108. #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH9)
  109. #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ9)
  110. #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP2)
  111. #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP21)
  112. #define LED_GREEN_PORT (GPIO_PORT_C)
  113. #define LED_GREEN_PIN (GPIO_PIN_13)
  114. #endif
  115. #define KEYCNT_BACKUP_ADDR (uint32_t *)(0x200F0010)
  116. #define KEYCNT_CMD_SLEEP_NONE (0)
  117. #define KEYCNT_CMD_SLEEP_IDLE (1)
  118. #define KEYCNT_CMD_SLEEP_DEEP (3)
  119. #define KEYCNT_CMD_SLEEP_STANDBY (5)
  120. #define KEYCNT_CMD_SLEEP_SHUTDOWN (7)
  121. #define PM_DBG
  122. #if defined PM_DBG
  123. #define pm_dbg rt_kprintf
  124. #else
  125. #define pm_dbg
  126. #endif
  127. static volatile uint32_t g_keycnt_cmd;
  128. static volatile rt_bool_t g_wkup_flag = RT_FALSE;
  129. static void KEY_IrqHandler(void)
  130. {
  131. if (SET == EXTINT_GetExtIntStatus(BSP_KEY_EXTINT))
  132. {
  133. EXTINT_ClearExtIntStatus(BSP_KEY_EXTINT);
  134. __DSB();
  135. __ISB();
  136. }
  137. if (g_wkup_flag)
  138. {
  139. g_wkup_flag = RT_FALSE;
  140. return;
  141. }
  142. g_keycnt_cmd++;
  143. pm_dbg("g_keycnt_cmd =%d, ", g_keycnt_cmd);
  144. pm_dbg("recv sleep request\n");
  145. NVIC_DisableIRQ(BSP_KEY_IRQn);
  146. NVIC_ClearPendingIRQ(BSP_KEY_IRQn);
  147. }
  148. static void _key_int_init(void)
  149. {
  150. stc_extint_init_t stcExtIntInit;
  151. stc_irq_signin_config_t stcIrqSignConfig;
  152. stc_gpio_init_t stcGpioInit;
  153. /* configuration structure initialization */
  154. (void)GPIO_StructInit(&stcGpioInit);
  155. stcGpioInit.u16ExtInt = PIN_EXTINT_ON;
  156. stcGpioInit.u16PullUp = PIN_PU_ON;
  157. /* GPIO config */
  158. (void)GPIO_Init(BSP_KEY_PORT, BSP_KEY_PIN, &stcGpioInit);
  159. /* Extint config */
  160. (void)EXTINT_StructInit(&stcExtIntInit);
  161. stcExtIntInit.u32Edge = EXTINT_TRIG_FALLING;
  162. (void)EXTINT_Init(BSP_KEY_EXTINT, &stcExtIntInit);
  163. /* IRQ sign-in */
  164. stcIrqSignConfig.enIntSrc = BSP_KEY_INT_SRC;
  165. stcIrqSignConfig.enIRQn = BSP_KEY_IRQn;
  166. stcIrqSignConfig.pfnCallback = KEY_IrqHandler;
  167. (void)INTC_IrqSignIn(&stcIrqSignConfig);
  168. /* NVIC config */
  169. NVIC_ClearPendingIRQ(stcIrqSignConfig.enIRQn);
  170. NVIC_SetPriority(stcIrqSignConfig.enIRQn, DDL_IRQ_PRIO_DEFAULT);
  171. NVIC_EnableIRQ(stcIrqSignConfig.enIRQn);
  172. }
  173. static void _wkup_cfg_sleep_deep()
  174. {
  175. INTC_WakeupSrcCmd(BSP_KEY_INTC_STOP_WKUP_EXTINT, ENABLE);
  176. }
  177. static void _wkup_cfg_sleep_standby(void)
  178. {
  179. PWC_PD_SetWakeupTriggerEdge(BSP_KEY_PWC_PD_WKUP_TRIG_WKUP, PWC_PD_WKUP_TRIG_FALLING);
  180. PWC_PD_WakeupCmd(BSP_KEY_PWC_PD_WKUP_WKUP, ENABLE);
  181. PWC_PD_ClearWakeupStatus(PWC_PD_WKUP_FLAG_ALL);
  182. }
  183. static void _wkup_cfg_sleep_shutdown(void)
  184. {
  185. PWC_PD_SetWakeupTriggerEdge(BSP_KEY_PWC_PD_WKUP_TRIG_WKUP, PWC_PD_WKUP_TRIG_FALLING);
  186. PWC_PD_WakeupCmd(BSP_KEY_PWC_PD_WKUP_WKUP, ENABLE);
  187. }
  188. static void _sleep_enter_event_idle(void)
  189. {
  190. rt_kprintf("sleep: idle\n");
  191. }
  192. static void _sleep_enter_event_deep(void)
  193. {
  194. _wkup_cfg_sleep_deep();
  195. rt_kprintf("sleep: deep\n");
  196. DDL_DelayMS(50);
  197. }
  198. static void _sleep_enter_event_standby(void)
  199. {
  200. _wkup_cfg_sleep_standby();
  201. #if defined (HC32F4A0) || defined (HC32F4A8)
  202. PWC_BKR_Write(0, g_keycnt_cmd & 0xFF);
  203. #endif
  204. *KEYCNT_BACKUP_ADDR = g_keycnt_cmd;
  205. rt_kprintf("sleep: standby\n");
  206. DDL_DelayMS(50);
  207. }
  208. static void _sleep_enter_event_shutdown(void)
  209. {
  210. _wkup_cfg_sleep_shutdown();
  211. *KEYCNT_BACKUP_ADDR = g_keycnt_cmd;
  212. rt_kprintf("sleep: shutdown\n");
  213. DDL_DelayMS(50);
  214. }
  215. static void _sleep_exit_event_idle(void)
  216. {
  217. rt_pm_release(PM_SLEEP_MODE_IDLE);
  218. rt_pm_request(PM_SLEEP_MODE_NONE);
  219. rt_kprintf("wakeup from sleep: idle\n");
  220. }
  221. static void _sleep_exit_event_deep(void)
  222. {
  223. #if defined (HC32F460)
  224. PWC_STOP_ClockRecover();
  225. #endif
  226. rt_pm_release(PM_SLEEP_MODE_DEEP);
  227. rt_pm_request(PM_SLEEP_MODE_NONE);
  228. rt_kprintf("wakeup from sleep: deep\n");
  229. }
  230. typedef void (*notify)(void);
  231. static notify sleep_enter_func[PM_SLEEP_MODE_MAX] =
  232. {
  233. RT_NULL,
  234. _sleep_enter_event_idle,
  235. RT_NULL,
  236. _sleep_enter_event_deep,
  237. _sleep_enter_event_standby,
  238. _sleep_enter_event_shutdown,
  239. };
  240. static notify sleep_exit_func[PM_SLEEP_MODE_MAX] =
  241. {
  242. RT_NULL,
  243. _sleep_exit_event_idle,
  244. RT_NULL,
  245. _sleep_exit_event_deep,
  246. RT_NULL,
  247. RT_NULL,
  248. };
  249. static void _notify_func(uint8_t event, uint8_t mode, void *data)
  250. {
  251. if (event == RT_PM_ENTER_SLEEP)
  252. {
  253. SysTick_Suspend();
  254. if (sleep_enter_func[mode] == RT_NULL)
  255. {
  256. return;
  257. }
  258. GPIO_ResetPins(LED_GREEN_PORT, LED_GREEN_PIN);
  259. sleep_enter_func[mode]();
  260. }
  261. else
  262. {
  263. SysTick_Resume();
  264. if (sleep_exit_func[mode] != RT_NULL)
  265. {
  266. sleep_exit_func[mode]();
  267. }
  268. g_keycnt_cmd++;
  269. g_wkup_flag = RT_TRUE;
  270. pm_dbg("g_keycnt_cmd =%d, ", g_keycnt_cmd);
  271. NVIC_EnableIRQ(BSP_KEY_IRQn);
  272. }
  273. }
  274. static void pm_cmd_handler(void *parameter)
  275. {
  276. rt_uint8_t sleep_mode = PM_SLEEP_MODE_NONE;
  277. while (1)
  278. {
  279. if ((KEYCNT_CMD_SLEEP_IDLE == g_keycnt_cmd) || (KEYCNT_CMD_SLEEP_DEEP == g_keycnt_cmd) || \
  280. (KEYCNT_CMD_SLEEP_STANDBY == g_keycnt_cmd) || (KEYCNT_CMD_SLEEP_SHUTDOWN == g_keycnt_cmd))
  281. {
  282. switch (g_keycnt_cmd)
  283. {
  284. case KEYCNT_CMD_SLEEP_IDLE:
  285. sleep_mode = PM_SLEEP_MODE_IDLE;
  286. break;
  287. case KEYCNT_CMD_SLEEP_DEEP:
  288. sleep_mode = PM_SLEEP_MODE_DEEP;
  289. break;
  290. case KEYCNT_CMD_SLEEP_STANDBY:
  291. sleep_mode = PM_SLEEP_MODE_STANDBY;
  292. break;
  293. case KEYCNT_CMD_SLEEP_SHUTDOWN:
  294. sleep_mode = PM_SLEEP_MODE_SHUTDOWN;
  295. break;
  296. default:
  297. break;
  298. }
  299. rt_pm_request(sleep_mode);
  300. rt_pm_release(PM_SLEEP_MODE_NONE);
  301. rt_thread_mdelay(500);
  302. }
  303. else
  304. {
  305. rt_thread_mdelay(50);
  306. }
  307. }
  308. }
  309. #if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8)
  310. static void pm_run_main(void *parameter)
  311. {
  312. static rt_uint8_t run_index = 0;
  313. char *speed[] = {"low", "high"};
  314. const rt_uint8_t run_mode[] = {PM_RUN_MODE_LOW_SPEED, PM_RUN_MODE_HIGH_SPEED};
  315. GPIO_SetFunc(MCO_PORT, MCO_PIN, MCO_GPIO_FUNC);
  316. /* Configure clock output system clock */
  317. CLK_MCOConfig(CLK_MCO1, CLK_MCO_SRC_HCLK, CLK_MCO_DIV8);
  318. /* MCO1 output enable */
  319. CLK_MCOCmd(CLK_MCO1, ENABLE);
  320. while (1)
  321. {
  322. rt_pm_run_enter(run_mode[run_index]);
  323. rt_thread_mdelay(100);
  324. rt_kprintf("system clock switch to %s speed\n\n", speed[run_index]);
  325. if (++run_index >= ARRAY_SZ(run_mode))
  326. {
  327. run_index = 0;
  328. }
  329. rt_thread_mdelay(3000);
  330. }
  331. }
  332. #endif
  333. static void _keycnt_cmd_init_after_power_on(void)
  334. {
  335. en_flag_status_t wkup_from_ptwk = PWC_PD_GetWakeupStatus(PWC_PD_WKUP_FLAG_WKUP0);
  336. #if defined (HC32F4A0) || defined (HC32F4A8)
  337. en_flag_status_t bakram_pd = PWC_BKR_GetStatus(PWC_BACKUP_RAM_FLAG_RAMPDF);
  338. uint8_t bkr0 = PWC_BKR_Read(0);
  339. if (bakram_pd == RT_TRUE)
  340. {
  341. g_keycnt_cmd = KEYCNT_CMD_SLEEP_NONE;
  342. }
  343. else
  344. #endif
  345. {
  346. g_keycnt_cmd = *KEYCNT_BACKUP_ADDR;
  347. if (g_keycnt_cmd == KEYCNT_CMD_SLEEP_STANDBY)
  348. {
  349. if (wkup_from_ptwk)
  350. {
  351. g_keycnt_cmd++;
  352. pm_dbg("g_keycnt_cmd =%d, ", g_keycnt_cmd);
  353. rt_kprintf("wakeup from sleep: standby\n\n");
  354. }
  355. else
  356. {
  357. g_keycnt_cmd = KEYCNT_CMD_SLEEP_NONE;
  358. }
  359. }
  360. else if (g_keycnt_cmd >= KEYCNT_CMD_SLEEP_SHUTDOWN)
  361. {
  362. if ((g_keycnt_cmd == KEYCNT_CMD_SLEEP_SHUTDOWN) && wkup_from_ptwk)
  363. {
  364. pm_dbg("g_keycnt_cmd =%d \n", KEYCNT_CMD_SLEEP_NONE);
  365. rt_kprintf("wakeup from sleep: shutdown\n\n");
  366. }
  367. g_keycnt_cmd = KEYCNT_CMD_SLEEP_NONE;
  368. }
  369. }
  370. pm_dbg("KEYCNT_BACKUP_ADDR addr =0x%p,value = %d\n", KEYCNT_BACKUP_ADDR, *KEYCNT_BACKUP_ADDR);
  371. pm_dbg("wkup_from_ptwk = %d\n", wkup_from_ptwk);
  372. #if defined (HC32F4A0) || defined (HC32F4A8)
  373. pm_dbg("bakram_pd = %d\n", bakram_pd);
  374. pm_dbg("bkr0 = %d\n", bkr0);
  375. #endif
  376. }
  377. static void _vbat_init(void)
  378. {
  379. #if defined (HC32F4A0) || defined (HC32F4A8)
  380. while (PWC_BKR_GetStatus(PWC_BACKUP_RAM_FLAG_RAMVALID) == RESET)
  381. {
  382. rt_thread_delay(10);
  383. }
  384. FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SRAMB, ENABLE);
  385. #elif defined (HC32F448) || defined (HC32F334)
  386. FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SRAMB, ENABLE);
  387. #elif defined (HC32F460)
  388. FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SRAMRET, ENABLE);
  389. #elif defined (HC32F472)
  390. FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SRAMRET, ENABLE);
  391. #endif
  392. pm_dbg("vbat init success\n");
  393. }
  394. int pm_sample_init(void)
  395. {
  396. pm_dbg("pm_sample_init\n\n");
  397. _keycnt_cmd_init_after_power_on();
  398. _vbat_init();
  399. _key_int_init();
  400. rt_pm_notify_set(_notify_func, NULL);
  401. rt_thread_t thread = rt_thread_create("pm_cmd_handler", pm_cmd_handler, RT_NULL, 1024, 25, 10);
  402. if (thread != RT_NULL)
  403. {
  404. rt_thread_startup(thread);
  405. }
  406. else
  407. {
  408. rt_kprintf("create pm sample thread failed!\n");
  409. }
  410. #if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8)
  411. thread = rt_thread_create("pm_run_main", pm_run_main, RT_NULL, 1024, 25, 10);
  412. if (thread != RT_NULL)
  413. {
  414. rt_thread_startup(thread);
  415. }
  416. else
  417. {
  418. rt_kprintf("create pm run thread failed!\n");
  419. }
  420. #endif
  421. return RT_EOK;
  422. }
  423. MSH_CMD_EXPORT(pm_sample_init, pm sample init);
  424. #endif /* end of BSP_USING_PM */