drv_gpio.c 10 KB

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  1. /*
  2. * Copyright (C) 2021, Huada Semiconductor Co., Ltd.
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2021-08-19 pjq first version
  9. */
  10. #include <rtthread.h>
  11. #include "rthw.h"
  12. #ifdef RT_USING_PIN
  13. #include "gpio.h"
  14. #include "drv_gpio.h"
  15. #include "interrupts_hc32l136.h"
  16. #define GPIO_PIN_INDEX(pin) ((uint8_t)((pin) & 0x0F))
  17. #define GPIO_PORT(pin) ((uint8_t)(((pin) >> 4) * 0x40u))
  18. #define GPIO_PIN(pin) ((uint16_t)(GPIO_PIN_INDEX(pin)))
  19. #define PIN_NUM(port, pin) (((((port) / 0x40u) << 4) | ((pin) & 0x0F)))
  20. #define PIN_MAX_NUM ((GpioPortD / 0x40u * 16) + (GpioPin15 + 1))
  21. struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
  22. {
  23. {-1, 0, RT_NULL, RT_NULL},
  24. {-1, 0, RT_NULL, RT_NULL},
  25. {-1, 0, RT_NULL, RT_NULL},
  26. {-1, 0, RT_NULL, RT_NULL},
  27. {-1, 0, RT_NULL, RT_NULL},
  28. {-1, 0, RT_NULL, RT_NULL},
  29. {-1, 0, RT_NULL, RT_NULL},
  30. {-1, 0, RT_NULL, RT_NULL},
  31. {-1, 0, RT_NULL, RT_NULL},
  32. {-1, 0, RT_NULL, RT_NULL},
  33. {-1, 0, RT_NULL, RT_NULL},
  34. {-1, 0, RT_NULL, RT_NULL},
  35. {-1, 0, RT_NULL, RT_NULL},
  36. {-1, 0, RT_NULL, RT_NULL},
  37. {-1, 0, RT_NULL, RT_NULL},
  38. {-1, 0, RT_NULL, RT_NULL},
  39. {-1, 0, RT_NULL, RT_NULL},
  40. {-1, 0, RT_NULL, RT_NULL},
  41. {-1, 0, RT_NULL, RT_NULL},
  42. {-1, 0, RT_NULL, RT_NULL},
  43. {-1, 0, RT_NULL, RT_NULL},
  44. {-1, 0, RT_NULL, RT_NULL},
  45. {-1, 0, RT_NULL, RT_NULL},
  46. {-1, 0, RT_NULL, RT_NULL},
  47. {-1, 0, RT_NULL, RT_NULL},
  48. {-1, 0, RT_NULL, RT_NULL},
  49. {-1, 0, RT_NULL, RT_NULL},
  50. {-1, 0, RT_NULL, RT_NULL},
  51. {-1, 0, RT_NULL, RT_NULL},
  52. {-1, 0, RT_NULL, RT_NULL},
  53. {-1, 0, RT_NULL, RT_NULL},
  54. {-1, 0, RT_NULL, RT_NULL},
  55. {-1, 0, RT_NULL, RT_NULL},
  56. {-1, 0, RT_NULL, RT_NULL},
  57. {-1, 0, RT_NULL, RT_NULL},
  58. {-1, 0, RT_NULL, RT_NULL},
  59. {-1, 0, RT_NULL, RT_NULL},
  60. {-1, 0, RT_NULL, RT_NULL},
  61. {-1, 0, RT_NULL, RT_NULL},
  62. {-1, 0, RT_NULL, RT_NULL},
  63. {-1, 0, RT_NULL, RT_NULL},
  64. {-1, 0, RT_NULL, RT_NULL},
  65. {-1, 0, RT_NULL, RT_NULL},
  66. {-1, 0, RT_NULL, RT_NULL},
  67. {-1, 0, RT_NULL, RT_NULL},
  68. {-1, 0, RT_NULL, RT_NULL},
  69. {-1, 0, RT_NULL, RT_NULL},
  70. {-1, 0, RT_NULL, RT_NULL},
  71. {-1, 0, RT_NULL, RT_NULL},
  72. {-1, 0, RT_NULL, RT_NULL},
  73. {-1, 0, RT_NULL, RT_NULL},
  74. {-1, 0, RT_NULL, RT_NULL},
  75. {-1, 0, RT_NULL, RT_NULL},
  76. {-1, 0, RT_NULL, RT_NULL},
  77. {-1, 0, RT_NULL, RT_NULL},
  78. {-1, 0, RT_NULL, RT_NULL},
  79. {-1, 0, RT_NULL, RT_NULL},
  80. {-1, 0, RT_NULL, RT_NULL},
  81. {-1, 0, RT_NULL, RT_NULL},
  82. {-1, 0, RT_NULL, RT_NULL},
  83. {-1, 0, RT_NULL, RT_NULL},
  84. {-1, 0, RT_NULL, RT_NULL},
  85. {-1, 0, RT_NULL, RT_NULL},
  86. {-1, 0, RT_NULL, RT_NULL},
  87. };
  88. static void pin_irq_handler(en_gpio_port_t port, en_gpio_pin_t pin)
  89. {
  90. rt_int32_t irqindex = -1;
  91. irqindex = PIN_NUM(port, pin);
  92. if (pin_irq_hdr_tab[irqindex].hdr)
  93. {
  94. pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args);
  95. }
  96. }
  97. void Gpio_IRQHandler(uint8_t u8Param)
  98. {
  99. en_gpio_pin_t i;
  100. en_gpio_port_t enPort;
  101. enPort = (en_gpio_port_t)(GpioPortA + (GpioPortB - GpioPortA) * u8Param);
  102. rt_interrupt_enter();
  103. for (i=GpioPin0; i<=GpioPin15; i++)
  104. {
  105. if(TRUE == Gpio_GetIrqStatus(enPort, i))
  106. {
  107. Gpio_ClearIrq(enPort, i);
  108. pin_irq_handler(enPort, i);
  109. }
  110. }
  111. rt_interrupt_leave();
  112. }
  113. static void _pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
  114. {
  115. uint8_t gpio_port;
  116. uint16_t gpio_pin;
  117. if (pin < PIN_MAX_NUM)
  118. {
  119. gpio_port = GPIO_PORT(pin);
  120. gpio_pin = GPIO_PIN(pin);
  121. if (PIN_LOW == value)
  122. {
  123. Gpio_WriteOutputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, FALSE);
  124. }
  125. else
  126. {
  127. Gpio_WriteOutputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, TRUE);
  128. }
  129. }
  130. }
  131. static rt_ssize_t _pin_read(rt_device_t dev, rt_base_t pin)
  132. {
  133. uint8_t gpio_port;
  134. uint16_t gpio_pin;
  135. rt_ssize_t value = PIN_LOW;
  136. if (pin < PIN_MAX_NUM)
  137. {
  138. gpio_port = GPIO_PORT(pin);
  139. gpio_pin = GPIO_PIN(pin);
  140. if (FALSE == Gpio_GetInputIO((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin))
  141. {
  142. value = PIN_LOW;
  143. }
  144. else
  145. {
  146. value = PIN_HIGH;
  147. }
  148. }
  149. else
  150. {
  151. value = -RT_EINVAL;
  152. }
  153. return value;
  154. }
  155. static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
  156. {
  157. uint8_t gpio_port;
  158. uint16_t gpio_pin;
  159. stc_gpio_config_t pstcGpioCfg;
  160. memset(&pstcGpioCfg, 0, sizeof(pstcGpioCfg));
  161. if (pin >= PIN_MAX_NUM)
  162. {
  163. return;
  164. }
  165. switch (mode)
  166. {
  167. case PIN_MODE_OUTPUT:
  168. pstcGpioCfg.enDir = GpioDirOut;
  169. pstcGpioCfg.enDrv = GpioDrvL;
  170. pstcGpioCfg.enCtrlMode = GpioAHB;
  171. break;
  172. case PIN_MODE_INPUT:
  173. pstcGpioCfg.enDir = GpioDirIn;
  174. pstcGpioCfg.enDrv = GpioDrvL;
  175. pstcGpioCfg.enPuPd = GpioPu;
  176. pstcGpioCfg.enOD = GpioOdDisable;
  177. pstcGpioCfg.enCtrlMode = GpioAHB;
  178. break;
  179. case PIN_MODE_INPUT_PULLUP:
  180. pstcGpioCfg.enDir = GpioDirIn;
  181. pstcGpioCfg.enDrv = GpioDrvL;
  182. pstcGpioCfg.enPuPd = GpioPu;
  183. pstcGpioCfg.enOD = GpioOdDisable;
  184. pstcGpioCfg.enCtrlMode = GpioAHB;
  185. break;
  186. case PIN_MODE_INPUT_PULLDOWN:
  187. pstcGpioCfg.enDir = GpioDirIn;
  188. pstcGpioCfg.enDrv = GpioDrvL;
  189. pstcGpioCfg.enPuPd = GpioPd;
  190. pstcGpioCfg.enOD = GpioOdDisable;
  191. pstcGpioCfg.enCtrlMode = GpioAHB;
  192. break;
  193. case PIN_MODE_OUTPUT_OD:
  194. pstcGpioCfg.enDir = GpioDirOut;
  195. pstcGpioCfg.enDrv = GpioDrvL;
  196. pstcGpioCfg.enOD = GpioOdEnable;
  197. pstcGpioCfg.enCtrlMode = GpioAHB;
  198. break;
  199. default:
  200. break;
  201. }
  202. gpio_port = GPIO_PORT(pin);
  203. gpio_pin = GPIO_PIN(pin);
  204. Gpio_Init((en_gpio_port_t)gpio_port, (en_gpio_pin_t)gpio_pin, &pstcGpioCfg);
  205. }
  206. static rt_err_t _pin_attach_irq(struct rt_device *device, rt_base_t pin,
  207. rt_uint8_t mode, void (*hdr)(void *args), void *args)
  208. {
  209. rt_base_t level;
  210. rt_int32_t irqindex = -1;
  211. if (pin >= PIN_MAX_NUM)
  212. {
  213. return -RT_ENOSYS;
  214. }
  215. irqindex = pin;
  216. level = rt_hw_interrupt_disable();
  217. if (pin_irq_hdr_tab[irqindex].pin == pin &&
  218. pin_irq_hdr_tab[irqindex].hdr == hdr &&
  219. pin_irq_hdr_tab[irqindex].mode == mode &&
  220. pin_irq_hdr_tab[irqindex].args == args)
  221. {
  222. rt_hw_interrupt_enable(level);
  223. return RT_EOK;
  224. }
  225. if (pin_irq_hdr_tab[irqindex].pin != -1)
  226. {
  227. rt_hw_interrupt_enable(level);
  228. return -RT_EBUSY;
  229. }
  230. pin_irq_hdr_tab[irqindex].pin = pin;
  231. pin_irq_hdr_tab[irqindex].hdr = hdr;
  232. pin_irq_hdr_tab[irqindex].mode = mode;
  233. pin_irq_hdr_tab[irqindex].args = args;
  234. rt_hw_interrupt_enable(level);
  235. return RT_EOK;
  236. }
  237. static rt_err_t _pin_detach_irq(struct rt_device *device, rt_base_t pin)
  238. {
  239. rt_base_t level;
  240. rt_int32_t irqindex = -1;
  241. if (pin >= PIN_MAX_NUM)
  242. {
  243. return -RT_ENOSYS;
  244. }
  245. irqindex = pin;
  246. level = rt_hw_interrupt_disable();
  247. if (pin_irq_hdr_tab[irqindex].pin == -1)
  248. {
  249. rt_hw_interrupt_enable(level);
  250. return RT_EOK;
  251. }
  252. pin_irq_hdr_tab[irqindex].pin = -1;
  253. pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
  254. pin_irq_hdr_tab[irqindex].mode = 0;
  255. pin_irq_hdr_tab[irqindex].args = RT_NULL;
  256. rt_hw_interrupt_enable(level);
  257. return RT_EOK;
  258. }
  259. static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
  260. {
  261. rt_base_t level;
  262. en_gpio_port_t gpio_port;
  263. en_gpio_pin_t gpio_pin;
  264. rt_int32_t irqindex;
  265. stc_gpio_config_t pstcGpioCfg;
  266. if ((pin >= PIN_MAX_NUM) || ((PIN_IRQ_ENABLE != enabled) && (PIN_IRQ_DISABLE != enabled)))
  267. {
  268. return -RT_ENOSYS;
  269. }
  270. irqindex = pin;
  271. gpio_port = (en_gpio_port_t)GPIO_PORT(pin);
  272. gpio_pin = (en_gpio_pin_t)GPIO_PIN(pin);
  273. if (enabled == PIN_IRQ_ENABLE)
  274. {
  275. level = rt_hw_interrupt_disable();
  276. if (pin_irq_hdr_tab[irqindex].pin == -1)
  277. {
  278. rt_hw_interrupt_enable(level);
  279. return -RT_ENOSYS;
  280. }
  281. /* Exint config */
  282. pstcGpioCfg.enDir = GpioDirIn;
  283. pstcGpioCfg.enDrv = GpioDrvL;
  284. pstcGpioCfg.enPuPd = GpioPu;
  285. pstcGpioCfg.enOD = GpioOdDisable;
  286. pstcGpioCfg.enCtrlMode = GpioAHB;
  287. Gpio_Init(gpio_port, gpio_pin, &pstcGpioCfg);
  288. Gpio_ClearIrq(gpio_port, gpio_pin);
  289. switch (pin_irq_hdr_tab[irqindex].mode)
  290. {
  291. case PIN_IRQ_MODE_RISING:
  292. Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqRising);
  293. break;
  294. case PIN_IRQ_MODE_FALLING:
  295. Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqFalling);
  296. break;
  297. case PIN_IRQ_MODE_HIGH_LEVEL:
  298. Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqHigh);
  299. break;
  300. case PIN_IRQ_MODE_LOW_LEVEL:
  301. Gpio_EnableIrq(gpio_port, gpio_pin, GpioIrqLow);
  302. break;
  303. }
  304. EnableNvic((IRQn_Type)(pin / 16), IrqLevel3, TRUE);
  305. rt_hw_interrupt_enable(level);
  306. }
  307. else
  308. {
  309. level = rt_hw_interrupt_disable();
  310. switch (pin_irq_hdr_tab[irqindex].mode)
  311. {
  312. case PIN_IRQ_MODE_RISING:
  313. Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqRising);
  314. break;
  315. case PIN_IRQ_MODE_FALLING:
  316. Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqFalling);
  317. break;
  318. case PIN_IRQ_MODE_RISING_FALLING:
  319. break;
  320. case PIN_IRQ_MODE_LOW_LEVEL:
  321. Gpio_DisableIrq(gpio_port, gpio_pin, GpioIrqLow);
  322. break;
  323. }
  324. rt_hw_interrupt_enable(level);
  325. }
  326. return RT_EOK;
  327. }
  328. static const struct rt_pin_ops _pin_ops =
  329. {
  330. _pin_mode,
  331. _pin_write,
  332. _pin_read,
  333. _pin_attach_irq,
  334. _pin_detach_irq,
  335. _pin_irq_enable,
  336. };
  337. int rt_hw_pin_init(void)
  338. {
  339. Sysctrl_SetPeripheralGate(SysctrlPeripheralGpio, TRUE);
  340. return rt_device_pin_register("pin", &_pin_ops, RT_NULL);
  341. }
  342. INIT_BOARD_EXPORT(rt_hw_pin_init);
  343. #endif /* RT_USING_PIN */