reg_dmm.h 4.0 KB

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  1. /** @file reg_dmm.h
  2. * @brief DMM Register Layer Header File
  3. * @date 29.May.2013
  4. * @version 03.05.02
  5. *
  6. * This file contains:
  7. * - Definitions
  8. * - Types
  9. * - Interface Prototypes
  10. * .
  11. * which are relevant for the DMM driver.
  12. */
  13. /* (c) Texas Instruments 2009-2013, All rights reserved. */
  14. #ifndef __REG_DMM_H__
  15. #define __REG_DMM_H__
  16. #include "sys_common.h"
  17. #include "gio.h"
  18. /* USER CODE BEGIN (0) */
  19. /* USER CODE END */
  20. /* Dmm Register Frame Definition */
  21. /** @struct dmmBase
  22. * @brief DMM Base Register Definition
  23. *
  24. * This structure is used to access the DMM module registers.
  25. */
  26. /** @typedef dmmBASE_t
  27. * @brief DMM Register Frame Type Definition
  28. *
  29. * This type is used to access the DMM Registers.
  30. */
  31. typedef volatile struct dmmBase
  32. {
  33. uint32 GLBCTRL; /**< 0x0000: Global control register 0 */
  34. uint32 INTSET; /**< 0x0004: DMM Interrupt Set Register */
  35. uint32 INTCLR; /**< 0x0008: DMM Interrupt Clear Register */
  36. uint32 INTLVL; /**< 0x000C: DMM Interrupt Level Register */
  37. uint32 INTFLG; /**< 0x0010: DMM Interrupt Flag Register */
  38. uint32 OFF1; /**< 0x0014: DMM Interrupt Offset 1 Register */
  39. uint32 OFF2; /**< 0x0018: DMM Interrupt Offset 2 Register */
  40. uint32 DDMDEST; /**< 0x001C: DMM Direct Data Mode Destination Register */
  41. uint32 DDMBL; /**< 0x0020: DMM Direct Data Mode Blocksize Register */
  42. uint32 DDMPT; /**< 0x0024: DMM Direct Data Mode Pointer Register */
  43. uint32 INTPT; /**< 0x0028: DMM Direct Data Mode Interrupt Pointer Register */
  44. uint32 DEST0REG1; /**< 0x002C: DMM Destination 0 Region 1 */
  45. uint32 DEST0BL1; /**< 0x0030: DMM Destination 0 Blocksize 1 */
  46. uint32 DEST0REG2; /**< 0x0034: DMM Destination 0 Region 2 */
  47. uint32 DEST0BL2; /**< 0x0038: DMM Destination 0 Blocksize 2 */
  48. uint32 DEST1REG1; /**< 0x003C: DMM Destination 1 Region 1 */
  49. uint32 DEST1BL1; /**< 0x0040: DMM Destination 1 Blocksize 1 */
  50. uint32 DEST1REG2; /**< 0x0044: DMM Destination 1 Region 2 */
  51. uint32 DEST1BL2; /**< 0x0048: DMM Destination 1 Blocksize 2 */
  52. uint32 DEST2REG1; /**< 0x004C: DMM Destination 2 Region 1 */
  53. uint32 DEST2BL1; /**< 0x0050: DMM Destination 2 Blocksize 1 */
  54. uint32 DEST2REG2; /**< 0x0054: DMM Destination 2 Region 2 */
  55. uint32 DEST2BL2; /**< 0x0058: DMM Destination 2 Blocksize 2 */
  56. uint32 DEST3REG1; /**< 0x005C: DMM Destination 3 Region 1 */
  57. uint32 DEST3BL1; /**< 0x0060: DMM Destination 3 Blocksize 1 */
  58. uint32 DEST3REG2; /**< 0x0064: DMM Destination 3 Region 2 */
  59. uint32 DEST3BL2; /**< 0x0068: DMM Destination 3 Blocksize 2 */
  60. uint32 PC0; /**< 0x006C: DMM Pin Control 0 */
  61. uint32 PC1; /**< 0x0070: DMM Pin Control 1 */
  62. uint32 PC2; /**< 0x0074: DMM Pin Control 2 */
  63. uint32 PC3; /**< 0x0078: DMM Pin Control 3 */
  64. uint32 PC4; /**< 0x007C: DMM Pin Control 4 */
  65. uint32 PC5; /**< 0x0080: DMM Pin Control 5 */
  66. uint32 PC6; /**< 0x0084: DMM Pin Control 6 */
  67. uint32 PC7; /**< 0x0088: DMM Pin Control 7 */
  68. uint32 PC8; /**< 0x008C: DMM Pin Control 8 */
  69. } dmmBASE_t;
  70. /** @def dmmREG
  71. * @brief DMM Register Frame Pointer
  72. *
  73. * This pointer is used by the DMM driver to access the DMM module registers.
  74. */
  75. #define dmmREG ((dmmBASE_t *)0xFFFFF700U)
  76. /** @def dmmPORT
  77. * @brief DMM Port Register Pointer
  78. *
  79. * Pointer used by the GIO driver to access I/O PORT of DMM
  80. * (use the GIO drivers to access the port pins).
  81. */
  82. #define dmmPORT ((gioPORT_t *)0xFFFFF738U)
  83. /* USER CODE BEGIN (1) */
  84. /* USER CODE END */
  85. #endif