context_gcc.S 3.2 KB

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  1. #ifndef __ASSEMBLY__
  2. #define __ASSEMBLY__
  3. #endif
  4. #include <p32xxxx.h>
  5. #include "../common/mips_def.h"
  6. #include "../common/stackframe.h"
  7. .section ".text", "ax"
  8. .set noat
  9. .set noreorder
  10. /*
  11. * rt_base_t rt_hw_interrupt_disable()
  12. */
  13. .globl rt_hw_interrupt_disable
  14. rt_hw_interrupt_disable:
  15. mfc0 v0, CP0_STATUS /* v0 = status */
  16. addiu v1, zero, -2 /* v1 = 0-2 = 0xFFFFFFFE */
  17. and v1, v0, v1 /* v1 = v0 & 0xFFFFFFFE */
  18. mtc0 v1, CP0_STATUS /* status = v1 */
  19. jr ra
  20. nop
  21. /*
  22. * void rt_hw_interrupt_enable(rt_base_t level)
  23. */
  24. .globl rt_hw_interrupt_enable
  25. rt_hw_interrupt_enable:
  26. mtc0 a0, CP0_STATUS
  27. jr ra
  28. nop
  29. /*
  30. * void rt_hw_context_switch_to(rt_uint32 to)/*
  31. * a0 --> to
  32. */
  33. .globl rt_hw_context_switch_to
  34. rt_hw_context_switch_to:
  35. lw sp, 0(a0) /* get new task stack pointer */
  36. RESTORE_ALL_AND_RET
  37. /*
  38. * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
  39. * a0 --> from
  40. * a1 --> to
  41. */
  42. .globl rt_hw_context_switch
  43. rt_hw_context_switch:
  44. mtc0 ra, CP0_EPC
  45. SAVE_ALL
  46. sw sp, 0(a0) /* store sp in preempted tasks TCB */
  47. lw sp, 0(a1) /* get new task stack pointer */
  48. RESTORE_ALL_AND_RET
  49. /*
  50. * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
  51. */
  52. .globl rt_thread_switch_interrupt_flag
  53. .globl rt_interrupt_from_thread
  54. .globl rt_interrupt_to_thread
  55. .globl rt_hw_context_switch_interrupt
  56. rt_hw_context_switch_interrupt:
  57. la t0, rt_thread_switch_interrupt_flag
  58. lw t1, 0(t0)
  59. nop
  60. bnez t1, _reswitch
  61. nop
  62. li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */
  63. sw t1, 0(t0)
  64. la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */
  65. sw a0, 0(t0)
  66. _reswitch:
  67. la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */
  68. sw a1, 0(t0)
  69. /* trigger the soft exception (causes context switch) */
  70. mfc0 t0, CP0_CAUSE /* t0 = Cause */
  71. ori t0, t0, (1<<8) /* t0 |= (1<<8) */
  72. mtc0 t0, CP0_CAUSE /* cause = t0 */
  73. addiu t1, zero, -257 /* t1 = ~(1<<8) */
  74. and t0, t0, t1 /* t0 &= t1 */
  75. mtc0 t0, CP0_CAUSE /* cause = t0 */
  76. jr ra
  77. nop
  78. /*
  79. * void __ISR(_CORE_SOFTWARE_0_VECTOR, ipl2) CoreSW0Handler(void)
  80. */
  81. .section ".text", "ax"
  82. .set noreorder
  83. .set noat
  84. .ent CoreSW0Handler
  85. .globl CoreSW0Handler
  86. CoreSW0Handler:
  87. SAVE_ALL
  88. /* mCS0ClearIntFlag(); */
  89. la t0, IFS0CLR /* t0 = IFS0CLR */
  90. addiu t1,zero,0x02 /* t1 = (1<<2) */
  91. sw t1, 0(t0) /* IFS0CLR = t1 */
  92. la k0, rt_thread_switch_interrupt_flag
  93. sw zero, 0(k0) /* clear flag */
  94. /*
  95. * switch to the new thread
  96. */
  97. la k0, rt_interrupt_from_thread
  98. lw k1, 0(k0)
  99. nop
  100. sw sp, 0(k1) /* store sp in preempted tasks's TCB */
  101. la k0, rt_interrupt_to_thread
  102. lw k1, 0(k0)
  103. nop
  104. lw sp, 0(k1) /* get new task's stack pointer */
  105. RESTORE_ALL_AND_RET
  106. .end CoreSW0Handler