os.c 10 KB

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  1. #include <os.h>
  2. #include <rtthread.h>
  3. #include <rthw.h>
  4. #ifdef RT_USING_SMART
  5. #include <mmu.h>
  6. #include <lwp_arch.h>
  7. #else
  8. #define PV_OFFSET 0
  9. #endif
  10. #include <cache.h>
  11. #include <hal_atomic.h>
  12. #include <hal_interrupt.h>
  13. #include <ktimer.h>
  14. #include <typedef.h>
  15. #define TIMER_FREQ (24000000)
  16. typedef unsigned long cycles_t;
  17. #ifndef CSR_TIME
  18. #define CSR_TIME 0xc01
  19. #endif
  20. #ifdef __ASSEMBLY__
  21. #define __ASM_STR(x) x
  22. #else
  23. #define __ASM_STR(x) #x
  24. #endif
  25. #define csr_read(csr) \
  26. ({ \
  27. register unsigned long __v; \
  28. __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
  29. : "=r" (__v) : \
  30. : "memory"); \
  31. __v; \
  32. })
  33. static inline cycles_t get_cycles(void)
  34. {
  35. return csr_read(CSR_TIME);
  36. }
  37. static inline uint64_t get_cycles64(void)
  38. {
  39. return get_cycles();
  40. }
  41. static inline uint32_t arch_timer_get_cntfrq(void)
  42. {
  43. uint32_t val = TIMER_FREQ;
  44. return val;
  45. }
  46. static inline uint64_t arch_counter_get_cntpct(void)
  47. {
  48. uint64_t cval;
  49. cval = get_cycles64();
  50. return cval;
  51. }
  52. rt_weak int msleep(unsigned int msecs)
  53. {
  54. rt_thread_mdelay(msecs);
  55. return 0;
  56. }
  57. rt_weak int usleep(unsigned int usecs)
  58. {
  59. int tickDiv = 1000 * (1000 / CONFIG_HZ);
  60. int ticks = usecs / tickDiv;
  61. int msecs = usecs % tickDiv;
  62. if (ticks)
  63. {
  64. rt_thread_delay(ticks);
  65. }
  66. if (msecs)
  67. {
  68. rt_hw_us_delay(usecs);
  69. }
  70. return 0;
  71. }
  72. unsigned long awos_arch_virt_to_phys(unsigned long virtaddr)
  73. {
  74. return virtaddr - PV_OFFSET;
  75. }
  76. unsigned long awos_arch_phys_to_virt(unsigned long physaddr)
  77. {
  78. return physaddr + PV_OFFSET;
  79. }
  80. #include <interrupt.h>
  81. void enable_irq(unsigned int irq)
  82. {
  83. rt_hw_interrupt_umask(irq);
  84. }
  85. void disable_irq(unsigned int irq)
  86. {
  87. rt_hw_interrupt_mask(irq);
  88. }
  89. const void *free_irq(unsigned int irq, void *dev_id)
  90. {
  91. const void *ret = RT_NULL;
  92. return ret;
  93. }
  94. int request_threaded_irq(unsigned int irq, irq_handler_t handler,
  95. irq_handler_t thread_fn, unsigned long irqflags,
  96. const char *devname, void *dev_id)
  97. {
  98. rt_hw_interrupt_install(irq, (rt_isr_handler_t)handler, dev_id, devname);
  99. return 0;
  100. }
  101. void awos_arch_mems_flush_icache_region(unsigned long start, unsigned long len)
  102. {
  103. rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void *)start, len);
  104. }
  105. void awos_arch_mems_clean_dcache_region(unsigned long start, unsigned long len)
  106. {
  107. rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void *)start, len);
  108. }
  109. void awos_arch_mems_clean_flush_dcache_region(unsigned long start, unsigned long len)
  110. {
  111. rt_hw_cpu_dcache_clean_and_invalidate((void *)start, len);
  112. }
  113. void awos_arch_mems_flush_dcache_region(unsigned long start, unsigned long len)
  114. {
  115. rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)start, len);
  116. }
  117. void awos_arch_clean_flush_cache(void)
  118. {
  119. rt_hw_cpu_dcache_clean_all();
  120. rt_hw_cpu_icache_invalidate_all();
  121. }
  122. void awos_arch_clean_flush_cache_region(unsigned long start, unsigned long len)
  123. {
  124. rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, (void *)start, len);
  125. rt_hw_cpu_icache_ops(RT_HW_CACHE_INVALIDATE, (void *)start, len);
  126. }
  127. void awos_arch_flush_cache(void)
  128. {
  129. rt_hw_cpu_dcache_invalidate_all();
  130. rt_hw_cpu_icache_invalidate_all();
  131. }
  132. void awos_arch_clean_dcache(void)
  133. {
  134. rt_hw_cpu_dcache_clean_all();
  135. }
  136. void awos_arch_clean_flush_dcache(void)
  137. {
  138. rt_hw_cpu_dcache_clean_all();
  139. rt_hw_cpu_dcache_invalidate_all();
  140. }
  141. void awos_arch_flush_dcache(void)
  142. {
  143. rt_hw_cpu_dcache_invalidate_all();
  144. }
  145. void awos_arch_flush_icache_all(void)
  146. {
  147. rt_hw_cpu_icache_invalidate_all();
  148. }
  149. rt_weak int32_t hal_spi_gpio_cfg_count(const char *secname)
  150. {
  151. rt_kprintf("FUNCTION:%s not implemented.\n", __FUNCTION__);
  152. return 0;
  153. }
  154. int32_t esCFG_GetGPIOSecKeyCount(char *GPIOSecName)
  155. {
  156. int id;
  157. if (!rt_strcmp(GPIOSecName, "pwm1") || !rt_strcmp(GPIOSecName, "pwm2") || !rt_strcmp(GPIOSecName, "pwm7"))
  158. {
  159. return 1;
  160. }
  161. else if (!rt_strcmp(GPIOSecName, "sdc0") || !rt_strcmp(GPIOSecName, "sdc1"))
  162. {
  163. return 6;
  164. }
  165. else if (!rt_strcmp(GPIOSecName, "spi0"))
  166. {
  167. return hal_spi_gpio_cfg_count(GPIOSecName);
  168. }
  169. else if (sscanf(GPIOSecName, "twi%d", &id) == 1)
  170. {
  171. return 2;
  172. }
  173. return 0;
  174. }
  175. rt_weak int hal_spi_gpio_cfg_load(user_gpio_set_t *gpio_cfg, int32_t GPIONum, int id)
  176. {
  177. rt_kprintf("FUNCTION:%s not implemented.\n", __FUNCTION__);
  178. return -1;
  179. }
  180. rt_weak int hal_i2c_gpio_cfg_load(user_gpio_set_t *gpio_cfg, int32_t GPIONum, int id)
  181. {
  182. rt_kprintf("FUNCTION:%s not implemented.\n", __FUNCTION__);
  183. return -1;
  184. }
  185. #define CFG_GPIO_PORT(p) ((p) - 'A' + 1)
  186. int32_t esCFG_GetGPIOSecData(char *GPIOSecName, void *pGPIOCfg, int32_t GPIONum)
  187. {
  188. user_gpio_set_t *gpio_cfg = (user_gpio_set_t *) pGPIOCfg;
  189. int i;
  190. int id;
  191. if (!rt_strcmp(GPIOSecName, "pwm1"))
  192. {
  193. rt_strncpy(gpio_cfg->gpio_name, "PB6", 4);
  194. gpio_cfg->data = 0;
  195. gpio_cfg->drv_level = 3;
  196. gpio_cfg->mul_sel = 5; // PWM
  197. gpio_cfg->port = CFG_GPIO_PORT('B'); // PORT-G
  198. gpio_cfg->port_num = 6; // PG13
  199. gpio_cfg->pull = 0; // pull disable
  200. }
  201. else if (!rt_strcmp(GPIOSecName, "pwm2"))
  202. {
  203. rt_strncpy(gpio_cfg->gpio_name, "PG13", 5);
  204. gpio_cfg->data = 0;
  205. gpio_cfg->drv_level = 3;
  206. gpio_cfg->mul_sel = 5; // PWM
  207. gpio_cfg->port = CFG_GPIO_PORT('G'); // PORT-G
  208. gpio_cfg->port_num = 13; // PG13
  209. gpio_cfg->pull = 0; // pull disable
  210. }
  211. else if (!rt_strcmp(GPIOSecName, "pwm7"))
  212. {
  213. rt_strncpy(gpio_cfg->gpio_name, "PD22", 5);
  214. gpio_cfg->data = 0;
  215. gpio_cfg->drv_level = 3;
  216. gpio_cfg->mul_sel = 5; // PWM
  217. gpio_cfg->port = CFG_GPIO_PORT('D'); // PORT-D
  218. gpio_cfg->port_num = 22; // PD22
  219. gpio_cfg->pull = 0; // pull disable
  220. }
  221. else if (!rt_strcmp(GPIOSecName, "sdc0"))
  222. {
  223. /*
  224. [sdc0]
  225. ;sdc0_used = 1
  226. ;bus-width = 4
  227. sdc0_d1 = port:PF00<2><1><1><default>
  228. sdc0_d0 = port:PF01<2><1><1><default>
  229. sdc0_clk = port:PF02<2><1><1><default>
  230. sdc0_cmd = port:PF03<2><1><1><default>
  231. sdc0_d3 = port:PF04<2><1><1><default>
  232. sdc0_d2 = port:PF05<2><1><1><default>
  233. */
  234. for (i = 0; i < GPIONum; i++)
  235. {
  236. strcpy(gpio_cfg->gpio_name, GPIOSecName);
  237. gpio_cfg->port = CFG_GPIO_PORT('F');
  238. gpio_cfg->port_num = i;
  239. gpio_cfg->mul_sel = 2;
  240. gpio_cfg->pull = 1;
  241. gpio_cfg->drv_level = 1;
  242. gpio_cfg->data = 0;
  243. gpio_cfg++;
  244. }
  245. }
  246. else if (!rt_strcmp(GPIOSecName, "sdc1"))
  247. {
  248. /*
  249. [sdc1]
  250. ;sdc1_used = 1
  251. ;bus-width= 4
  252. sdc1_clk = port:PG00<2><1><1><default>
  253. sdc1_cmd = port:PG01<2><1><1><default>
  254. sdc1_d0 = port:PG02<2><1><1><default>
  255. sdc1_d1 = port:PG03<2><1><1><default>
  256. sdc1_d2 = port:PG04<2><1><1><default>
  257. sdc1_d3 = port:PG05<2><1><1><default>
  258. */
  259. for (i = 0; i < GPIONum; i++)
  260. {
  261. strcpy(gpio_cfg->gpio_name, GPIOSecName);
  262. gpio_cfg->port = CFG_GPIO_PORT('G');
  263. gpio_cfg->port_num = i;
  264. gpio_cfg->mul_sel = 2;
  265. gpio_cfg->pull = 1;
  266. gpio_cfg->drv_level = 1;
  267. gpio_cfg->data = 0;
  268. gpio_cfg++;
  269. }
  270. }
  271. else if (sscanf(GPIOSecName, "spi%d", &id) == 1)
  272. {
  273. return hal_spi_gpio_cfg_load(gpio_cfg, GPIONum, id);
  274. }
  275. else if (sscanf(GPIOSecName, "twi%d", &id) == 1)
  276. {
  277. extern int hal_i2c_gpio_cfg_load(user_gpio_set_t *gpio_cfg, int32_t GPIONum, int id);
  278. return hal_i2c_gpio_cfg_load(gpio_cfg, GPIONum, id);
  279. }
  280. return 0;
  281. }
  282. int32_t esCFG_GetKeyValue(char *SecName, char *KeyName, int32_t Value[], int32_t Count)
  283. {
  284. if (!rt_strcmp("target", SecName))
  285. {
  286. /*
  287. [target]
  288. boot_clock = 1008
  289. storage_type = 1
  290. */
  291. if (!rt_strcmp("storage_type", KeyName))
  292. {
  293. if (Count == 1)
  294. {
  295. *Value = 1;
  296. return 0;
  297. }
  298. }
  299. else if (!rt_strcmp("boot_clock", KeyName))
  300. {
  301. if (Count == 1)
  302. {
  303. *Value = 1008;
  304. return 0;
  305. }
  306. }
  307. }
  308. else if (!rt_strcmp("card_product", SecName))
  309. {
  310. /*
  311. [card_product]
  312. card_product_used = 1
  313. card_product_storage = 3
  314. */
  315. if (!rt_strcmp("card_product_used", KeyName))
  316. {
  317. if (Count == 1)
  318. {
  319. *Value = 1;
  320. return 0;
  321. }
  322. } else if (!rt_strcmp("card_product_storage", KeyName))
  323. {
  324. if (Count == 1)
  325. {
  326. *Value = 3;
  327. return 0;
  328. }
  329. }
  330. }
  331. else if (!rt_strcmp("sdcard_global", SecName))
  332. {
  333. /*
  334. [sdcard_global]
  335. used_card_no = 0x01
  336. ;used_card_no = 0x01, when use card0
  337. ;used_card_no = 0x02, when use card1
  338. ;used_card_no = 0x03, when use card0 & card1
  339. internal_card = 0x00
  340. ;internal_card = 0x00, 无内置卡内置卡
  341. ;internal_card = 0x01, card0 做内置卡
  342. ;internal_card = 0x02, card1 做内置卡
  343. */
  344. if (!rt_strcmp("internal_card", KeyName))
  345. {
  346. *Value = 0x01;
  347. return 0;
  348. } else if (!rt_strcmp("used_card_no", KeyName))
  349. {
  350. *Value = 0x03;
  351. return 0;
  352. }
  353. }
  354. return -1;
  355. }
  356. int do_gettimeofday(struct timespec64 *ts)
  357. {
  358. if (ts)
  359. {
  360. ts->tv_sec = rt_tick_get() / RT_TICK_PER_SECOND;
  361. ts->tv_nsec = (rt_tick_get() % RT_TICK_PER_SECOND) * (1000000000 / RT_TICK_PER_SECOND);
  362. }
  363. return 0;
  364. }
  365. int eLIBs_printf(const char *fmt, ...)
  366. {
  367. va_list args;
  368. rt_size_t length;
  369. static char rt_log_buf[RT_CONSOLEBUF_SIZE];
  370. va_start(args, fmt);
  371. length = rt_vsnprintf(rt_log_buf, sizeof(rt_log_buf) - 1, fmt, args);
  372. if (length > RT_CONSOLEBUF_SIZE - 1)
  373. length = RT_CONSOLEBUF_SIZE - 1;
  374. va_end(args);
  375. rt_kputs(rt_log_buf);
  376. }