sun8iw20-codec.c 38 KB

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  1. /*
  2. * Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
  3. *
  4. * Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
  5. * the the people's Republic of China and other countries.
  6. * All Allwinner Technology Co.,Ltd. trademarks are used with permission.
  7. *
  8. * DISCLAIMER
  9. * THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
  10. * IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
  11. * IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
  12. * ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
  13. * ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
  14. * COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
  15. * YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
  16. *
  17. *
  18. * THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
  19. * PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
  20. * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
  21. * THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
  22. * OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  23. * IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  24. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  26. * LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
  27. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  28. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  30. * OF THE POSSIBILITY OF SUCH DAMAGE.
  31. */
  32. #include <hal_timer.h>
  33. #include <stdio.h>
  34. #include <stdlib.h>
  35. #include <string.h>
  36. #include <init.h>
  37. #include <log.h>
  38. #include <sound/snd_core.h>
  39. #include <sound/snd_pcm.h>
  40. #include <sound/pcm_common.h>
  41. #include <hal_gpio.h>
  42. #include <sound/snd_dma.h>
  43. #include <sound/dma_wrap.h>
  44. #include <hal_dma.h>
  45. #include <hal_clk.h>
  46. #include <hal_reset.h>
  47. #include <sunxi_hal_timer.h>
  48. /* #include "hal_clk.h" */
  49. #include "sunxi-codec.h"
  50. #include "sun8iw20-codec.h"
  51. struct snd_codec sunxi_audiocodec;
  52. static struct sunxi_codec_param default_param = {
  53. .digital_vol = 0x0,
  54. .lineout_vol = 0x0,
  55. .mic1gain = 0x0,
  56. .mic2gain = 0x0,
  57. .mic3gain = 0x0,
  58. .lineingain = 0x0,
  59. .gpio_spk = GPIOB(7),
  60. .pa_msleep_time = 160,
  61. .pa_level = GPIO_DATA_HIGH,
  62. .adcdrc_cfg = 0,
  63. .adchpf_cfg = 1,
  64. .dacdrc_cfg = 0,
  65. .dachpf_cfg = 0,
  66. };
  67. static const struct sample_rate sample_rate_conv[] = {
  68. {44100, 0},
  69. {48000, 0},
  70. {8000, 5},
  71. {32000, 1},
  72. {22050, 2},
  73. {24000, 2},
  74. {16000, 3},
  75. {11025, 4},
  76. {12000, 4},
  77. {192000, 6},
  78. {96000, 7},
  79. {88200, 7}, /* audio spec do not supply 88.2k */
  80. };
  81. #ifdef SUNXI_CODEC_DAP_ENABLE
  82. static void adcdrc_config(struct snd_codec *codec)
  83. {
  84. /* Left peak filter attack time */
  85. snd_codec_write(codec, SUNXI_ADC_DRC_LPFHAT, (0x000B77BF >> 16) & 0xFFFF);
  86. snd_codec_write(codec, SUNXI_ADC_DRC_LPFLAT, 0x000B77BF & 0xFFFF);
  87. /* Right peak filter attack time */
  88. snd_codec_write(codec, SUNXI_ADC_DRC_RPFHAT, (0x000B77BF >> 16) & 0xFFFF);
  89. snd_codec_write(codec, SUNXI_ADC_DRC_RPFLAT, 0x000B77BF & 0xFFFF);
  90. /* Left peak filter release time */
  91. snd_codec_write(codec, SUNXI_ADC_DRC_LPFHRT, (0x00FFE1F8 >> 16) & 0xFFFF);
  92. snd_codec_write(codec, SUNXI_ADC_DRC_LPFLRT, 0x00FFE1F8 & 0xFFFF);
  93. /* Right peak filter release time */
  94. snd_codec_write(codec, SUNXI_ADC_DRC_RPFHRT, (0x00FFE1F8 >> 16) & 0xFFFF);
  95. snd_codec_write(codec, SUNXI_ADC_DRC_RPFLRT, 0x00FFE1F8 & 0xFFFF);
  96. /* Left RMS filter attack time */
  97. snd_codec_write(codec, SUNXI_ADC_DRC_LPFHAT, (0x00012BAF >> 16) & 0xFFFF);
  98. snd_codec_write(codec, SUNXI_ADC_DRC_LPFLAT, 0x00012BAF & 0xFFFF);
  99. /* Right RMS filter attack time */
  100. snd_codec_write(codec, SUNXI_ADC_DRC_RPFHAT, (0x00012BAF >> 16) & 0xFFFF);
  101. snd_codec_write(codec, SUNXI_ADC_DRC_RPFLAT, 0x00012BAF & 0xFFFF);
  102. /* smooth filter attack time */
  103. snd_codec_write(codec, SUNXI_ADC_DRC_SFHAT, (0x00017665 >> 16) & 0xFFFF);
  104. snd_codec_write(codec, SUNXI_ADC_DRC_SFLAT, 0x00017665 & 0xFFFF);
  105. /* gain smooth filter release time */
  106. snd_codec_write(codec, SUNXI_ADC_DRC_SFHRT, (0x00000F04 >> 16) & 0xFFFF);
  107. snd_codec_write(codec, SUNXI_ADC_DRC_SFLRT, 0x00000F04 & 0xFFFF);
  108. /* OPL */
  109. snd_codec_write(codec, SUNXI_ADC_DRC_HOPL, (0xFBD8FBA7 >> 16) & 0xFFFF);
  110. snd_codec_write(codec, SUNXI_ADC_DRC_LOPL, 0xFBD8FBA7 & 0xFFFF);
  111. /* OPC */
  112. snd_codec_write(codec, SUNXI_ADC_DRC_HOPC, (0xF95B2C3F >> 16) & 0xFFFF);
  113. snd_codec_write(codec, SUNXI_ADC_DRC_LOPC, 0xF95B2C3F & 0xFFFF);
  114. /* OPE */
  115. snd_codec_write(codec, SUNXI_ADC_DRC_HOPE, (0xF45F8D6E >> 16) & 0xFFFF);
  116. snd_codec_write(codec, SUNXI_ADC_DRC_LOPE, 0xF45F8D6E & 0xFFFF);
  117. /* LT */
  118. snd_codec_write(codec, SUNXI_ADC_DRC_HLT, (0x01A934F0 >> 16) & 0xFFFF);
  119. snd_codec_write(codec, SUNXI_ADC_DRC_LLT, 0x01A934F0 & 0xFFFF);
  120. /* CT */
  121. snd_codec_write(codec, SUNXI_ADC_DRC_HCT, (0x06A4D3C0 >> 16) & 0xFFFF);
  122. snd_codec_write(codec, SUNXI_ADC_DRC_LCT, 0x06A4D3C0 & 0xFFFF);
  123. /* ET */
  124. snd_codec_write(codec, SUNXI_ADC_DRC_HET, (0x0BA07291 >> 16) & 0xFFFF);
  125. snd_codec_write(codec, SUNXI_ADC_DRC_LET, 0x0BA07291 & 0xFFFF);
  126. /* Ki */
  127. snd_codec_write(codec, SUNXI_ADC_DRC_HKI, (0x00051EB8 >> 16) & 0xFFFF);
  128. snd_codec_write(codec, SUNXI_ADC_DRC_LKI, 0x00051EB8 & 0xFFFF);
  129. /* Kc */
  130. snd_codec_write(codec, SUNXI_ADC_DRC_HKC, (0x00800000 >> 16) & 0xFFFF);
  131. snd_codec_write(codec, SUNXI_ADC_DRC_LKC, 0x00800000 & 0xFFFF);
  132. /* Kn */
  133. snd_codec_write(codec, SUNXI_ADC_DRC_HKN, (0x01000000 >> 16) & 0xFFFF);
  134. snd_codec_write(codec, SUNXI_ADC_DRC_LKN, 0x01000000 & 0xFFFF);
  135. /* Ke */
  136. snd_codec_write(codec, SUNXI_ADC_DRC_HKE, (0x0000F45F >> 16) & 0xFFFF);
  137. snd_codec_write(codec, SUNXI_ADC_DRC_LKE, 0x0000F45F & 0xFFFF);
  138. }
  139. static void adcdrc_enable(struct snd_codec *codec, bool on)
  140. {
  141. struct sunxi_codec_info *sunxi_codec = codec->private_data;
  142. if (on) {
  143. snd_codec_update_bits(codec, SUNXI_ADC_DAP_CTL,
  144. (0x1 << ADC_DRC0_EN | 0x1 << ADC_DRC1_EN),
  145. (0x1 << ADC_DRC0_EN | 0x1 << ADC_DRC1_EN));
  146. } else {
  147. snd_codec_update_bits(codec, SUNXI_ADC_DAP_CTL,
  148. (0x1 << ADC_DRC0_EN | 0x1 << ADC_DRC1_EN),
  149. (0x0 << ADC_DRC0_EN | 0x0 << ADC_DRC1_EN));
  150. }
  151. }
  152. static void adchpf_config(struct snd_codec *codec)
  153. {
  154. /* HPF */
  155. snd_codec_write(codec, SUNXI_ADC_DRC_HHPFC, (0xFFFAC1 >> 16) & 0xFFFF);
  156. snd_codec_write(codec, SUNXI_ADC_DRC_LHPFC, 0xFFFAC1 & 0xFFFF);
  157. }
  158. static void adchpf_enable(struct snd_codec *codec, bool on)
  159. {
  160. struct sunxi_codec_info *sunxi_codec = codec->private_data;
  161. if (on) {
  162. snd_codec_update_bits(codec, SUNXI_ADC_DAP_CTL,
  163. (0x1 << ADC_HPF0_EN | 0x1 << ADC_HPF1_EN),
  164. (0x1 << ADC_HPF0_EN | 0x1 << ADC_HPF1_EN));
  165. } else {
  166. snd_codec_update_bits(codec, SUNXI_ADC_DAP_CTL,
  167. (0x1 << ADC_HPF0_EN | 0x1 << ADC_HPF1_EN),
  168. (0x0 << ADC_HPF0_EN | 0x0 << ADC_HPF1_EN));
  169. }
  170. }
  171. static void dacdrc_config(struct snd_codec *codec)
  172. {
  173. /* Left peak filter attack time */
  174. snd_codec_write(codec, SUNXI_DAC_DRC_LPFHAT, (0x000B77BF >> 16) & 0xFFFF);
  175. snd_codec_write(codec, SUNXI_DAC_DRC_LPFLAT, 0x000B77BF & 0xFFFF);
  176. /* Right peak filter attack time */
  177. snd_codec_write(codec, SUNXI_DAC_DRC_RPFHAT, (0x000B77F0 >> 16) & 0xFFFF);
  178. snd_codec_write(codec, SUNXI_DAC_DRC_RPFLAT, 0x000B77F0 & 0xFFFF);
  179. /* Left peak filter release time */
  180. snd_codec_write(codec, SUNXI_DAC_DRC_LPFHRT, (0x00FFE1F8 >> 16) & 0xFFFF);
  181. snd_codec_write(codec, SUNXI_DAC_DRC_LPFLRT, 0x00FFE1F8 & 0xFFFF);
  182. /* Right peak filter release time */
  183. snd_codec_write(codec, SUNXI_DAC_DRC_RPFHRT, (0x00FFE1F8 >> 16) & 0xFFFF);
  184. snd_codec_write(codec, SUNXI_DAC_DRC_RPFLRT, 0x00FFE1F8 & 0xFFFF);
  185. /* Left RMS filter attack time */
  186. snd_codec_write(codec, SUNXI_DAC_DRC_LRMSHAT, (0x00012BB0 >> 16) & 0xFFFF);
  187. snd_codec_write(codec, SUNXI_DAC_DRC_LRMSLAT, 0x00012BB0 & 0xFFFF);
  188. /* Right RMS filter attack time */
  189. snd_codec_write(codec, SUNXI_DAC_DRC_RRMSHAT, (0x00012BB0 >> 16) & 0xFFFF);
  190. snd_codec_write(codec, SUNXI_DAC_DRC_RRMSLAT, 0x00012BB0 & 0xFFFF);
  191. /* smooth filter attack time */
  192. snd_codec_write(codec, SUNXI_DAC_DRC_SFHAT, (0x00017665 >> 16) & 0xFFFF);
  193. snd_codec_write(codec, SUNXI_DAC_DRC_SFLAT, 0x00017665 & 0xFFFF);
  194. /* gain smooth filter release time */
  195. snd_codec_write(codec, SUNXI_DAC_DRC_SFHRT, (0x00000F04 >> 16) & 0xFFFF);
  196. snd_codec_write(codec, SUNXI_DAC_DRC_SFLRT, 0x00000F04 & 0xFFFF);
  197. /* OPL */
  198. snd_codec_write(codec, SUNXI_DAC_DRC_HOPL, (0xFF641741 >> 16) & 0xFFFF);
  199. snd_codec_write(codec, SUNXI_DAC_DRC_LOPL, 0xFF641741 & 0xFFFF);
  200. /* OPC */
  201. snd_codec_write(codec, SUNXI_DAC_DRC_HOPC, (0xF9E8E88C >> 16) & 0xFFFF);
  202. snd_codec_write(codec, SUNXI_DAC_DRC_LOPC, 0xF9E8E88C & 0xFFFF);
  203. /* OPE */
  204. snd_codec_write(codec, SUNXI_DAC_DRC_HOPE, (0xF5DE3D14 >> 16) & 0xFFFF);
  205. snd_codec_write(codec, SUNXI_DAC_DRC_LOPE, 0xF5DE3D14 & 0xFFFF);
  206. /* LT */
  207. snd_codec_write(codec, SUNXI_DAC_DRC_HLT, (0x0336110B >> 16) & 0xFFFF);
  208. snd_codec_write(codec, SUNXI_DAC_DRC_LLT, 0x0336110B & 0xFFFF);
  209. /* CT */
  210. snd_codec_write(codec, SUNXI_DAC_DRC_HCT, (0x08BF6C28 >> 16) & 0xFFFF);
  211. snd_codec_write(codec, SUNXI_DAC_DRC_LCT, 0x08BF6C28 & 0xFFFF);
  212. /* ET */
  213. snd_codec_write(codec, SUNXI_DAC_DRC_HET, (0x0C9F9255 >> 16) & 0xFFFF);
  214. snd_codec_write(codec, SUNXI_DAC_DRC_LET, 0x0C9F9255 & 0xFFFF);
  215. /* Ki */
  216. snd_codec_write(codec, SUNXI_DAC_DRC_HKI, (0x001A7B96 >> 16) & 0xFFFF);
  217. snd_codec_write(codec, SUNXI_DAC_DRC_LKI, 0x001A7B96 & 0xFFFF);
  218. /* Kc */
  219. snd_codec_write(codec, SUNXI_DAC_DRC_HKC, (0x00FD70A5 >> 16) & 0xFFFF);
  220. snd_codec_write(codec, SUNXI_DAC_DRC_LKC, 0x00FD70A5 & 0xFFFF);
  221. /* Kn */
  222. snd_codec_write(codec, SUNXI_DAC_DRC_HKN, (0x010AF8B0 >> 16) & 0xFFFF);
  223. snd_codec_write(codec, SUNXI_DAC_DRC_LKN, 0x010AF8B0 & 0xFFFF);
  224. /* Ke */
  225. snd_codec_write(codec, SUNXI_DAC_DRC_HKE, (0x06286BA0 >> 16) & 0xFFFF);
  226. snd_codec_write(codec, SUNXI_DAC_DRC_LKE, 0x06286BA0 & 0xFFFF);
  227. /* MXG */
  228. snd_codec_write(codec, SUNXI_DAC_DRC_MXGHS, (0x035269E0 >> 16) & 0xFFFF);
  229. snd_codec_write(codec, SUNXI_DAC_DRC_MXGLS, 0x035269E0 & 0xFFFF);
  230. /* MNG */
  231. snd_codec_write(codec, SUNXI_DAC_DRC_MNGHS, (0xF95B2C3F >> 16) & 0xFFFF);
  232. snd_codec_write(codec, SUNXI_DAC_DRC_MNGLS, 0xF95B2C3F & 0xFFFF);
  233. /* EPS */
  234. snd_codec_write(codec, SUNXI_DAC_DRC_EPSHC, (0x00025600 >> 16) & 0xFFFF);
  235. snd_codec_write(codec, SUNXI_DAC_DRC_EPSLC, 0x00025600 & 0xFFFF);
  236. }
  237. static void dacdrc_enable(struct snd_codec *codec, bool on)
  238. {
  239. struct sunxi_codec_info *sunxi_codec = codec->private_data;
  240. if (on) {
  241. /* detect noise when ET enable */
  242. snd_codec_update_bits(codec, SUNXI_DAC_DRC_CTRL,
  243. (0x1 << DAC_DRC_NOISE_DET_EN),
  244. (0x1 << DAC_DRC_NOISE_DET_EN));
  245. /* 0x0:RMS filter; 0x1:Peak filter */
  246. snd_codec_update_bits(codec, SUNXI_DAC_DRC_CTRL,
  247. (0x1 << DAC_DRC_SIGNAL_SEL),
  248. (0x1 << DAC_DRC_SIGNAL_SEL));
  249. snd_codec_update_bits(codec, SUNXI_DAC_DRC_CTRL,
  250. (0x1 << DAC_DRC_GAIN_MAX_EN),
  251. (0x1 << DAC_DRC_GAIN_MAX_EN));
  252. snd_codec_update_bits(codec, SUNXI_DAC_DRC_CTRL,
  253. (0x1 << DAC_DRC_GAIN_MIN_EN),
  254. (0x1 << DAC_DRC_GAIN_MIN_EN));
  255. /* delay function enable */
  256. snd_codec_update_bits(codec, SUNXI_DAC_DRC_CTRL,
  257. (0x1 << DAC_DRC_DELAY_BUF_EN),
  258. (0x1 << DAC_DRC_DELAY_BUF_EN));
  259. snd_codec_update_bits(codec, SUNXI_DAC_DRC_CTRL,
  260. (0x1 << DAC_DRC_LT_EN),
  261. (0x1 << DAC_DRC_LT_EN));
  262. snd_codec_update_bits(codec, SUNXI_DAC_DRC_CTRL,
  263. (0x1 << DAC_DRC_ET_EN),
  264. (0x1 << DAC_DRC_ET_EN));
  265. snd_codec_update_bits(codec, SUNXI_DAC_DAP_CTL,
  266. (0x1 << DDAP_DRC_EN),
  267. (0x1 << DDAP_DRC_EN));
  268. } else {
  269. snd_codec_update_bits(codec, SUNXI_DAC_DAP_CTL,
  270. (0x1 << DDAP_DRC_EN),
  271. (0x0 << DDAP_DRC_EN));
  272. /* detect noise when ET enable */
  273. snd_codec_update_bits(codec, SUNXI_DAC_DRC_CTRL,
  274. (0x1 << DAC_DRC_NOISE_DET_EN),
  275. (0x0 << DAC_DRC_NOISE_DET_EN));
  276. /* 0x0:RMS filter; 0x1:Peak filter */
  277. snd_codec_update_bits(codec, SUNXI_DAC_DRC_CTRL,
  278. (0x1 << DAC_DRC_SIGNAL_SEL),
  279. (0x0 << DAC_DRC_SIGNAL_SEL));
  280. /* delay function enable */
  281. snd_codec_update_bits(codec, SUNXI_DAC_DRC_CTRL,
  282. (0x1 << DAC_DRC_DELAY_BUF_EN),
  283. (0x0 << DAC_DRC_DELAY_BUF_EN));
  284. snd_codec_update_bits(codec, SUNXI_DAC_DRC_CTRL,
  285. (0x1 << DAC_DRC_GAIN_MAX_EN),
  286. (0x0 << DAC_DRC_GAIN_MAX_EN));
  287. snd_codec_update_bits(codec, SUNXI_DAC_DRC_CTRL,
  288. (0x1 << DAC_DRC_GAIN_MIN_EN),
  289. (0x0 << DAC_DRC_GAIN_MIN_EN));
  290. snd_codec_update_bits(codec, SUNXI_DAC_DRC_CTRL,
  291. (0x1 << DAC_DRC_LT_EN),
  292. (0x0 << DAC_DRC_LT_EN));
  293. snd_codec_update_bits(codec, SUNXI_DAC_DRC_CTRL,
  294. (0x1 << DAC_DRC_ET_EN),
  295. (0x0 << DAC_DRC_ET_EN));
  296. }
  297. }
  298. static void dachpf_config(struct snd_codec *codec)
  299. {
  300. /* HPF */
  301. snd_codec_write(codec, SUNXI_DAC_DRC_HHPFC, (0xFFFAC1 >> 16) & 0xFFFF);
  302. snd_codec_write(codec, SUNXI_DAC_DRC_LHPFC, 0xFFFAC1 & 0xFFFF);
  303. }
  304. static void dachpf_enable(struct snd_codec *codec, bool on)
  305. {
  306. struct sunxi_codec_info *sunxi_codec = codec->private_data;
  307. if (on) {
  308. snd_codec_update_bits(codec, SUNXI_DAC_DAP_CTL,
  309. (0x1 << DDAP_HPF_EN),
  310. (0x1 << DDAP_HPF_EN));
  311. } else {
  312. snd_codec_update_bits(codec, SUNXI_DAC_DAP_CTL,
  313. (0x1 << DDAP_HPF_EN),
  314. (0x0 << DDAP_HPF_EN));
  315. }
  316. }
  317. #endif
  318. static const char * const codec_format_function[] = {
  319. "hub_disable", "hub_enable"};
  320. static const char * const codec_switch[] = {
  321. "Off", "On"};
  322. static int suxni_ctl_mic_set(struct snd_kcontrol *kcontrol, unsigned long val)
  323. {
  324. if (kcontrol->type != SND_CTL_ELEM_TYPE_ENUMERATED) {
  325. snd_err("invalid kcontrol type = %d.\n", kcontrol->type);
  326. return -EINVAL;
  327. }
  328. if (val >= kcontrol->items) {
  329. snd_err("invalid kcontrol items = %ld.\n", val);
  330. return -EINVAL;
  331. }
  332. struct snd_codec *codec = kcontrol->private_data;
  333. snd_codec_update_bits(codec, kcontrol->reg,
  334. (kcontrol->mask << kcontrol->shift),
  335. ((unsigned int)val << kcontrol->shift));
  336. snd_codec_update_bits(codec, kcontrol->reg,
  337. (kcontrol->mask << MIC_PGA_EN), (val<<MIC_PGA_EN));
  338. kcontrol->value = val & kcontrol->mask;
  339. return 0;
  340. }
  341. static struct snd_kcontrol sunxi_codec_controls[] = {
  342. SND_CTL_ENUM("codec hub mode",
  343. ARRAY_SIZE(codec_format_function), codec_format_function,
  344. SUNXI_DAC_DPC, DAC_HUB_EN),
  345. SND_CTL_KCONTROL("digital volume", SUNXI_DAC_DPC, DVOL, 0x3F),
  346. SND_CTL_ENUM("DAC digital volume switch",
  347. ARRAY_SIZE(codec_switch), codec_switch,
  348. SUNXI_DAC_VOL_CTL, DAC_VOL_SEL),
  349. SND_CTL_KCONTROL("DACL digital volume", SUNXI_DAC_VOL_CTL,
  350. DAC_VOL_L, 0xFF),
  351. SND_CTL_KCONTROL("DACR digital volume", SUNXI_DAC_VOL_CTL,
  352. DAC_VOL_R, 0xFF),
  353. SND_CTL_KCONTROL("MIC1 gain volume", SUNXI_ADC1_ANA_CTL,
  354. ADC_PGA_GAIN_CTL, 0x1F),
  355. SND_CTL_KCONTROL("MIC2 gain volume", SUNXI_ADC2_ANA_CTL,
  356. ADC_PGA_GAIN_CTL, 0x1F),
  357. SND_CTL_KCONTROL("MIC3 gain volume", SUNXI_ADC3_ANA_CTL,
  358. ADC_PGA_GAIN_CTL, 0x1F),
  359. SND_CTL_KCONTROL("FM Left gain volume", SUNXI_ADC1_ANA_CTL,
  360. FMINL_GAIN, 0x1),
  361. SND_CTL_KCONTROL("FM Right gain volume", SUNXI_ADC2_ANA_CTL,
  362. FMINR_GAIN, 0x1),
  363. SND_CTL_KCONTROL("Line Right gain volume", SUNXI_ADC2_ANA_CTL,
  364. LIENINL_GAIN, 0x1),
  365. SND_CTL_KCONTROL("Line Left gain volume", SUNXI_ADC2_ANA_CTL,
  366. LIENINR_GAIN, 0x1),
  367. SND_CTL_ENUM("ADC1_2 digital volume switch",
  368. ARRAY_SIZE(codec_switch), codec_switch,
  369. SUNXI_ADC_DIG_CTL, ADC1_2_VOL_EN),
  370. SND_CTL_ENUM("ADC3 digital volume switch",
  371. ARRAY_SIZE(codec_switch), codec_switch,
  372. SUNXI_ADC_DIG_CTL, ADC3_VOL_EN),
  373. SND_CTL_KCONTROL("ADC1 digital volume", SUNXI_ADC_VOL_CTL1,
  374. ADC1_VOL, 0xFF),
  375. SND_CTL_KCONTROL("ADC2 digital volume", SUNXI_ADC_VOL_CTL1,
  376. ADC2_VOL, 0xFF),
  377. SND_CTL_KCONTROL("ADC3 digital volume", SUNXI_ADC_VOL_CTL1,
  378. ADC3_VOL, 0xFF),
  379. SND_CTL_ENUM_VALUE_EXT("MIC1 input switch", ARRAY_SIZE(codec_switch),
  380. codec_switch, SUNXI_ADC1_ANA_CTL, MIC_SIN_EN, 0x1,
  381. NULL, suxni_ctl_mic_set),
  382. SND_CTL_ENUM_VALUE_EXT("MIC2 input switch", ARRAY_SIZE(codec_switch),
  383. codec_switch, SUNXI_ADC2_ANA_CTL, MIC_SIN_EN, 0x1,
  384. NULL, suxni_ctl_mic_set),
  385. SND_CTL_ENUM_VALUE_EXT("MIC3 input switch", ARRAY_SIZE(codec_switch),
  386. codec_switch, SUNXI_ADC3_ANA_CTL, MIC_SIN_EN, 0x1,
  387. NULL, suxni_ctl_mic_set),
  388. SND_CTL_ENUM("FM input L switch", ARRAY_SIZE(codec_switch),
  389. codec_switch, SUNXI_ADC1_ANA_CTL, FMINL_EN),
  390. SND_CTL_ENUM("FM input R switch", ARRAY_SIZE(codec_switch),
  391. codec_switch, SUNXI_ADC2_ANA_CTL, FMINR_EN),
  392. SND_CTL_ENUM("LINE input L switch", ARRAY_SIZE(codec_switch),
  393. codec_switch, SUNXI_ADC1_ANA_CTL, LIENINL_EN),
  394. SND_CTL_ENUM("LINE input R switch", ARRAY_SIZE(codec_switch),
  395. codec_switch, SUNXI_ADC2_ANA_CTL, LIENINR_EN),
  396. SND_CTL_KCONTROL("HPOUT gain volume", SUNXI_HP_ANA_CTL, HP_GAIN, 0x7),
  397. };
  398. static void sunxi_codec_init(struct snd_codec *codec)
  399. {
  400. struct sunxi_codec_info *sunxi_codec = codec->private_data;
  401. struct sunxi_codec_param *param = &sunxi_codec->param;
  402. unsigned int ret;
  403. snd_codec_update_bits(codec, SUNXI_POWER_ANA_CTL,
  404. (0x1<<HPLDO_EN), (0x1<<HPLDO_EN));
  405. /* Disable HPF(high passed filter) */
  406. snd_codec_update_bits(codec, SUNXI_DAC_DPC,
  407. (1 << HPF_EN), (0x0 << HPF_EN));
  408. /* Enable ADCFDT to overcome niose at the beginning */
  409. snd_codec_update_bits(codec, SUNXI_ADC_FIFOC,
  410. (0x7 << ADCDFEN), (0x7 << ADCDFEN));
  411. /* init the mic pga and vol params */
  412. snd_codec_update_bits(codec, SUNXI_DAC_ANA_CTL,
  413. 0x1F << LINEOUT_VOL,
  414. param->lineout_vol << LINEOUT_VOL);
  415. /* DAC_VOL_SEL enable */
  416. snd_codec_update_bits(codec, SUNXI_DAC_VOL_CTL,
  417. (0x1 << DAC_VOL_SEL), (0x1 << DAC_VOL_SEL));
  418. snd_codec_update_bits(codec, SUNXI_DAC_DPC,
  419. 0x3F << DVOL,
  420. param->digital_vol << DVOL);
  421. snd_codec_update_bits(codec, SUNXI_ADC1_ANA_CTL,
  422. 0x1F << ADC_PGA_GAIN_CTL,
  423. param->mic1gain << ADC_PGA_GAIN_CTL);
  424. snd_codec_update_bits(codec, SUNXI_ADC2_ANA_CTL,
  425. 0x1F << ADC_PGA_GAIN_CTL,
  426. param->mic2gain << ADC_PGA_GAIN_CTL);
  427. snd_codec_update_bits(codec, SUNXI_ADC3_ANA_CTL,
  428. 0x1F << ADC_PGA_GAIN_CTL,
  429. param->mic3gain << ADC_PGA_GAIN_CTL);
  430. /* RAMP mannual control enable */
  431. snd_codec_update_bits(codec, SUNXI_RAMP_ANA_CTL,
  432. (0x1<<RMCEN), (0x1<<RMCEN));
  433. /* HPOUT has no RAMP function */
  434. snd_codec_update_bits(codec, SUNXI_HP_ANA_CTL,
  435. (0x1<<RAMPEN), (0x0<<RAMPEN));
  436. #ifdef SUNXI_CODEC_DAP_ENABLE
  437. if (param->dacdrc_cfg || param->dachpf_cfg) {
  438. snd_codec_update_bits(codec, SUNXI_DAC_DAP_CTL,
  439. (0x1 << DDAP_EN), (0x1 << DDAP_EN));
  440. }
  441. if (param->adcdrc_cfg || param->adchpf_cfg) {
  442. snd_codec_update_bits(codec, SUNXI_ADC_DAP_CTL,
  443. (0x1 << ADC_DAP0_EN | 0x1 << ADC_DAP1_EN),
  444. (0x1 << ADC_DAP0_EN | 0x1 << ADC_DAP1_EN));
  445. }
  446. if (param->adcdrc_cfg) {
  447. adcdrc_config(codec);
  448. adcdrc_enable(codec, 1);
  449. }
  450. if (param->adchpf_cfg) {
  451. adchpf_config(codec);
  452. adchpf_enable(codec, 1);
  453. }
  454. if (param->dacdrc_cfg) {
  455. dacdrc_config(codec);
  456. dacdrc_enable(codec, 1);
  457. }
  458. if (param->dachpf_cfg) {
  459. dachpf_config(codec);
  460. dachpf_enable(codec, 1);
  461. }
  462. #endif
  463. }
  464. static int sunxi_codec_dapm_control(struct snd_pcm_substream *substream,
  465. struct snd_dai *dai, int onoff)
  466. {
  467. struct snd_codec *codec = dai->component;
  468. struct sunxi_codec_info *sunxi_codec = codec->private_data;
  469. struct sunxi_codec_param *param = &sunxi_codec->param;
  470. if (substream->dapm_state == onoff)
  471. return 0;
  472. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  473. /*
  474. * Playback:
  475. * Playback --> DAC --> DAC_DIFFER --> HPOUT --> External Speaker
  476. */
  477. if (onoff) {
  478. snd_codec_update_bits(codec, SUNXI_HP_ANA_CTL,
  479. (0x1<<HPFB_BUF_EN) | (0x1<<HPFB_IN_EN),
  480. (0x1<<HPFB_BUF_EN) | (0x1<<HPFB_IN_EN));
  481. /* ramp out enable */
  482. snd_codec_update_bits(codec, SUNXI_HP_ANA_CTL,
  483. (0x1<<RAMP_OUT_EN) | (0x1<<RSWITCH),
  484. (0x1<<RAMP_OUT_EN) | (0x1<<RSWITCH));
  485. /* digital DAC enable */
  486. snd_codec_update_bits(codec, SUNXI_DAC_DPC,
  487. (0x1<<EN_DAC), (0x1<<EN_DAC));
  488. /* analog DAC enable */
  489. snd_codec_update_bits(codec, SUNXI_DAC_ANA_CTL,
  490. (0x1<<DACLEN) | (0x1<<DACREN),
  491. (0x1<<DACLEN) | (0x1<<DACREN));
  492. /* HEADPONEOUT */
  493. snd_codec_update_bits(codec, SUNXI_HP_ANA_CTL,
  494. (0x1<<HP_DRVEN) | (0x1<<HP_DRVOUTEN),
  495. (0x1<<HP_DRVEN) | (0x1<<HP_DRVOUTEN));
  496. /* Playback on */
  497. snd_codec_update_bits(codec, SUNXI_POWER_ANA_CTL,
  498. (0x1<<HPLDO_EN), (0x1<<HPLDO_EN));
  499. if (param->gpio_spk > 0) {
  500. hal_gpio_set_direction(param->gpio_spk, GPIO_MUXSEL_OUT);
  501. hal_gpio_set_data(param->gpio_spk, param->pa_level);
  502. hal_msleep(param->pa_msleep_time);
  503. }
  504. } else {
  505. /* Playback off */
  506. if (param->gpio_spk > 0) {
  507. hal_gpio_set_direction(param->gpio_spk, GPIO_MUXSEL_OUT);
  508. hal_gpio_set_data(param->gpio_spk, !param->pa_level);
  509. }
  510. /* HEADPONE_EN */
  511. snd_codec_update_bits(codec, SUNXI_HP_ANA_CTL,
  512. (0x1<<HP_DRVEN), (0x0<<HP_DRVEN));
  513. /* power off */
  514. /* note: HPLDO is always open to avoid KEY_ADC sampling fail */
  515. /* snd_codec_update_bits(codec, SUNXI_POWER_ANA_CTL, */
  516. /* (0x1<<HPLDO_EN), (0x0<<HPLDO_EN)); */
  517. hal_msleep(30);
  518. /* HEADPONE_OUT */
  519. snd_codec_update_bits(codec, SUNXI_HP_ANA_CTL,
  520. (0x1<<HP_DRVOUTEN), (0x0<<HP_DRVOUTEN));
  521. /* analog DAC */
  522. snd_codec_update_bits(codec, SUNXI_DAC_ANA_CTL,
  523. (0x1<<DACLEN) | (0x1<<DACREN),
  524. (0x0<<DACLEN) | (0x0<<DACREN));
  525. /* digital DAC */
  526. snd_codec_update_bits(codec, SUNXI_DAC_DPC,
  527. (0x1<<EN_DAC), (0x0<<EN_DAC));
  528. snd_codec_update_bits(codec, SUNXI_HP_ANA_CTL,
  529. (0x1<<RAMP_OUT_EN) | (0x1<<RSWITCH),
  530. (0x0<<RAMP_OUT_EN) | (0x0<<RSWITCH));
  531. snd_codec_update_bits(codec, SUNXI_HP_ANA_CTL,
  532. (0x1<<HPFB_BUF_EN) | (0x1<<HPFB_IN_EN),
  533. (0x0<<HPFB_BUF_EN) | (0x0<<HPFB_IN_EN));
  534. }
  535. } else {
  536. /*
  537. * Capture:
  538. * Capture <-- ADC <-- Input Mixer <-- MIC PGA <-- MIC <-- MainMic Bias
  539. * Capture <-- ADC <-- Input Mixer <-- LINEIN PGA <-- LINEIN <-- MainMic Bias
  540. * Capture <-- ADC <-- Input Mixer <-- FMIN PGA <-- FMIN <-- MainMic Bias
  541. */
  542. unsigned int channels = 0;
  543. channels = substream->runtime->channels;
  544. snd_print("channels = %u\n", channels);
  545. if (onoff) {
  546. /* Capture on */
  547. hal_msleep(100);
  548. /* digital ADC enable */
  549. snd_codec_update_bits(codec, SUNXI_ADC_FIFOC,
  550. (0x1<<EN_AD), (0x1<<EN_AD));
  551. switch (channels) {
  552. case 3:
  553. /* analog ADC enable */
  554. snd_codec_update_bits(codec, SUNXI_ADC3_ANA_CTL,
  555. (0x1<<ADC_EN), (0x1<<ADC_EN));
  556. // fall through
  557. case 2:
  558. /* analog ADCL enable */
  559. snd_codec_update_bits(codec, SUNXI_ADC2_ANA_CTL,
  560. (0x1<<ADC_EN), (0x1<<ADC_EN));
  561. // fall through
  562. case 1:
  563. /* analog ADCL enable */
  564. snd_codec_update_bits(codec, SUNXI_ADC1_ANA_CTL,
  565. (0x1<<ADC_EN), (0x1<<ADC_EN));
  566. break;
  567. default:
  568. snd_err("unknown channels:%u\n", channels);
  569. return -1;
  570. }
  571. } else {
  572. /* Capture off */
  573. switch (channels) {
  574. case 3:
  575. /* analog ADC disable */
  576. snd_codec_update_bits(codec, SUNXI_ADC3_ANA_CTL,
  577. (0x1<<ADC_EN), (0x0<<ADC_EN));
  578. // fall through
  579. case 2:
  580. /* analog ADCL disable */
  581. snd_codec_update_bits(codec, SUNXI_ADC2_ANA_CTL,
  582. (0x1<<ADC_EN), (0x0<<ADC_EN));
  583. // fall through
  584. case 1:
  585. /* analog ADCL disable */
  586. snd_codec_update_bits(codec, SUNXI_ADC1_ANA_CTL,
  587. (0x1<<ADC_EN), (0x0<<ADC_EN));
  588. break;
  589. default:
  590. snd_err("unknown channels:%u\n", channels);
  591. return -1;
  592. }
  593. /* digital ADC enable */
  594. snd_codec_update_bits(codec, SUNXI_ADC_FIFOC,
  595. (0x1<<EN_AD), (0x0<<EN_AD));
  596. }
  597. }
  598. substream->dapm_state = onoff;
  599. return 0;
  600. }
  601. static int sunxi_codec_startup(struct snd_pcm_substream *substream,
  602. struct snd_dai *dai)
  603. {
  604. struct snd_codec *codec = dai->component;
  605. struct sunxi_codec_info *sunxi_codec = codec->private_data;
  606. // struct sunxi_codec_param *param = codec->param;
  607. snd_print("\n");
  608. return 0;
  609. }
  610. static int sunxi_codec_hw_params(struct snd_pcm_substream *substream,
  611. struct snd_pcm_hw_params *params, struct snd_dai *dai)
  612. {
  613. struct snd_codec *codec = dai->component;
  614. struct sunxi_codec_info *sunxi_codec = codec->private_data;
  615. struct sunxi_codec_param *codec_param = &sunxi_codec->param;
  616. int i = 0;
  617. snd_print("\n");
  618. switch (params_format(params)) {
  619. case SND_PCM_FORMAT_S16_LE:
  620. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  621. snd_codec_update_bits(codec, SUNXI_DAC_FIFOC,
  622. (3 << FIFO_MODE), (3 << FIFO_MODE));
  623. snd_codec_update_bits(codec, SUNXI_DAC_FIFOC,
  624. (1 << TX_SAMPLE_BITS), (0 << TX_SAMPLE_BITS));
  625. } else {
  626. snd_codec_update_bits(codec, SUNXI_ADC_FIFOC,
  627. (1 << RX_FIFO_MODE), (1 << RX_FIFO_MODE));
  628. snd_codec_update_bits(codec, SUNXI_ADC_FIFOC,
  629. (1 << RX_SAMPLE_BITS), (0 << RX_SAMPLE_BITS));
  630. }
  631. break;
  632. case SND_PCM_FORMAT_S24_LE:
  633. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  634. snd_codec_update_bits(codec, SUNXI_DAC_FIFOC,
  635. (3 << FIFO_MODE), (0 << FIFO_MODE));
  636. snd_codec_update_bits(codec, SUNXI_DAC_FIFOC,
  637. (1 << TX_SAMPLE_BITS), (1 << TX_SAMPLE_BITS));
  638. } else {
  639. snd_codec_update_bits(codec, SUNXI_ADC_FIFOC,
  640. (1 << RX_FIFO_MODE), (0 << RX_FIFO_MODE));
  641. snd_codec_update_bits(codec, SUNXI_ADC_FIFOC,
  642. (1 << RX_SAMPLE_BITS), (1 << RX_SAMPLE_BITS));
  643. }
  644. break;
  645. default:
  646. break;
  647. }
  648. for (i = 0; i < ARRAY_SIZE(sample_rate_conv); i++) {
  649. if (sample_rate_conv[i].samplerate == params_rate(params)) {
  650. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  651. snd_codec_update_bits(codec, SUNXI_DAC_FIFOC,
  652. (0x7 << DAC_FS),
  653. (sample_rate_conv[i].rate_bit << DAC_FS));
  654. } else {
  655. if (sample_rate_conv[i].samplerate > 48000)
  656. return -EINVAL;
  657. snd_codec_update_bits(codec, SUNXI_ADC_FIFOC,
  658. (0x7 << ADC_FS),
  659. (sample_rate_conv[i].rate_bit<<ADC_FS));
  660. }
  661. }
  662. }
  663. /* reset the adchpf func setting for different sampling */
  664. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  665. if (codec_param->adchpf_cfg) {
  666. if (params_rate(params) == 16000) {
  667. snd_codec_write(codec, SUNXI_ADC_DRC_HHPFC,
  668. (0x00F623A5 >> 16) & 0xFFFF);
  669. snd_codec_write(codec, SUNXI_ADC_DRC_LHPFC,
  670. 0x00F623A5 & 0xFFFF);
  671. } else if (params_rate(params) == 44100) {
  672. snd_codec_write(codec, SUNXI_ADC_DRC_HHPFC,
  673. (0x00FC60DB >> 16) & 0xFFFF);
  674. snd_codec_write(codec, SUNXI_ADC_DRC_LHPFC,
  675. 0x00FC60DB & 0xFFFF);
  676. } else {
  677. snd_codec_write(codec, SUNXI_ADC_DRC_HHPFC,
  678. (0x00FCABB3 >> 16) & 0xFFFF);
  679. snd_codec_write(codec, SUNXI_ADC_DRC_LHPFC,
  680. 0x00FCABB3 & 0xFFFF);
  681. }
  682. }
  683. }
  684. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  685. switch (params_channels(params)) {
  686. case 1:
  687. snd_codec_update_bits(codec, SUNXI_DAC_FIFOC,
  688. (1<<DAC_MONO_EN), 1<<DAC_MONO_EN);
  689. break;
  690. case 2:
  691. snd_codec_update_bits(codec, SUNXI_DAC_FIFOC,
  692. (1<<DAC_MONO_EN), (0<<DAC_MONO_EN));
  693. break;
  694. default:
  695. snd_err("cannot support the channels:%u.\n",
  696. params_channels(params));
  697. return -EINVAL;
  698. }
  699. } else {
  700. switch (params_channels(params)) {
  701. case 3:
  702. case 2:
  703. case 1:
  704. snd_codec_update_bits(codec, SUNXI_ADC_DIG_CTL,
  705. (0x7<<ADC_CHANNEL_EN),
  706. (((0x1<<params_channels(params))-1)<<ADC_CHANNEL_EN));
  707. break;
  708. default:
  709. snd_err("capture only support 1 channel\n");
  710. return -EINVAL;
  711. }
  712. }
  713. return 0;
  714. }
  715. static int sunxi_codec_set_sysclk(struct snd_dai *dai,
  716. int clk_id, unsigned int freq, int dir)
  717. {
  718. struct snd_codec *codec = dai->component;
  719. struct sunxi_codec_info *sunxi_codec = codec->private_data;
  720. snd_print("\n");
  721. if (hal_clk_set_rate(sunxi_codec->pllclk, freq)) {
  722. snd_err("set pllclk rate %u failed\n", freq);
  723. return -EINVAL;
  724. }
  725. return 0;
  726. }
  727. static void sunxi_codec_shutdown(struct snd_pcm_substream *substream,
  728. struct snd_dai *dai)
  729. {
  730. return ;
  731. }
  732. static int sunxi_codec_prepare(struct snd_pcm_substream *substream,
  733. struct snd_dai *dai)
  734. {
  735. struct snd_codec *codec = dai->component;
  736. snd_print("\n");
  737. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  738. snd_codec_update_bits(codec, SUNXI_DAC_FIFOC,
  739. (1 << FIFO_FLUSH), (1 << FIFO_FLUSH));
  740. snd_codec_write(codec, SUNXI_DAC_FIFOS,
  741. (1 << DAC_TXE_INT | 1 << DAC_TXU_INT | 1 << DAC_TXO_INT));
  742. snd_codec_write(codec, SUNXI_DAC_CNT, 0);
  743. } else {
  744. snd_codec_update_bits(codec, SUNXI_ADC_FIFOC,
  745. (1 << ADC_FIFO_FLUSH), (1 << ADC_FIFO_FLUSH));
  746. snd_codec_write(codec, SUNXI_ADC_FIFOS,
  747. (1 << ADC_RXA_INT | 1 << ADC_RXO_INT));
  748. snd_codec_write(codec, SUNXI_ADC_CNT, 0);
  749. }
  750. return 0;
  751. }
  752. static int sunxi_codec_trigger(struct snd_pcm_substream *substream,
  753. int cmd, struct snd_dai *dai)
  754. {
  755. struct snd_codec *codec = dai->component;
  756. struct sunxi_codec_info *sunxi_codec = codec->private_data;
  757. unsigned int sync_mode = 0;
  758. int adc_sync_flag = 0;
  759. uint32_t __cpsr;
  760. snd_print("\n");
  761. switch (cmd) {
  762. case SNDRV_PCM_TRIGGER_START:
  763. case SNDRV_PCM_TRIGGER_RESUME:
  764. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  765. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  766. snd_codec_update_bits(codec, SUNXI_DAC_FIFOC,
  767. (1 << DAC_DRQ_EN), (1 << DAC_DRQ_EN));
  768. }
  769. else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  770. snd_codec_update_bits(codec, SUNXI_ADC_FIFOC,
  771. (1 << ADC_DRQ_EN), (1 << ADC_DRQ_EN));
  772. }
  773. break;
  774. case SNDRV_PCM_TRIGGER_STOP:
  775. case SNDRV_PCM_TRIGGER_SUSPEND:
  776. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  777. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  778. snd_codec_update_bits(codec, SUNXI_DAC_FIFOC,
  779. (1 << DAC_DRQ_EN), (0 << DAC_DRQ_EN));
  780. }
  781. else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
  782. snd_codec_update_bits(codec, SUNXI_ADC_FIFOC,
  783. (1 << ADC_DRQ_EN), (0 << ADC_DRQ_EN));
  784. }
  785. break;
  786. default:
  787. return -EINVAL;
  788. }
  789. return 0;
  790. }
  791. static struct snd_dai_ops sun8iw20_codec_dai_ops = {
  792. .startup = sunxi_codec_startup,
  793. .hw_params = sunxi_codec_hw_params,
  794. .shutdown = sunxi_codec_shutdown,
  795. .set_sysclk = sunxi_codec_set_sysclk,
  796. .trigger = sunxi_codec_trigger,
  797. .prepare = sunxi_codec_prepare,
  798. .dapm_control = sunxi_codec_dapm_control,
  799. };
  800. static struct snd_dai sun8iw20_codec_dai[] = {
  801. {
  802. .name = "sun8iw20codec",
  803. .playback = {
  804. .stream_name = "Playback",
  805. .channels_min = 1,
  806. .channels_max = 2,
  807. .rates = SNDRV_PCM_RATE_8000_192000
  808. | SNDRV_PCM_RATE_KNOT,
  809. .formats = SNDRV_PCM_FMTBIT_S16_LE
  810. | SNDRV_PCM_FMTBIT_S24_LE,
  811. .rate_min = 8000,
  812. .rate_max = 192000,
  813. },
  814. .capture = {
  815. .stream_name = "Capture",
  816. .channels_min = 1,
  817. .channels_max = 3,
  818. .rates = SNDRV_PCM_RATE_8000_48000
  819. | SNDRV_PCM_RATE_KNOT,
  820. .formats = SNDRV_PCM_FMTBIT_S16_LE
  821. | SNDRV_PCM_FMTBIT_S24_LE,
  822. .rate_min = 8000,
  823. .rate_max = 48000,
  824. },
  825. .ops = &sun8iw20_codec_dai_ops,
  826. },
  827. };
  828. static void sunxi_jack_detect(void *param)
  829. {
  830. struct sunxi_codec_info *sunxi_codec = param;
  831. struct sunxi_codec_param *codec_param = &sunxi_codec->param;
  832. gpio_data_t gpio_status;
  833. if (codec_param->gpio_spk > 0) {
  834. hal_gpio_set_direction(codec_param->gpio_spk, GPIO_MUXSEL_OUT);
  835. hal_gpio_get_data(SUNXI_CODEC_JACK_DET, &gpio_status);
  836. if (gpio_status) {
  837. /* jack plug out */
  838. hal_gpio_set_data(codec_param->gpio_spk, codec_param->pa_level);
  839. } else {
  840. /* jack plug in */
  841. hal_gpio_set_data(codec_param->gpio_spk, !codec_param->pa_level);
  842. }
  843. }
  844. }
  845. static irqreturn_t sunxi_jack_irq_handler(int irq, void *ptr)
  846. {
  847. struct sunxi_codec_info *sunxi_codec = ptr;
  848. hal_timer_set_oneshot(SUNXI_TMR0, 300000, sunxi_jack_detect, sunxi_codec);
  849. return 0;
  850. }
  851. static int sun8iw20_codec_probe(struct snd_codec *codec)
  852. {
  853. struct sunxi_codec_info *sunxi_codec = NULL;
  854. struct reset_control *reset;
  855. hal_clk_status_t ret;
  856. if (!codec->codec_dai)
  857. return -1;
  858. sunxi_codec = snd_malloc(sizeof(struct sunxi_codec_info));
  859. if (!sunxi_codec) {
  860. snd_err("no memory\n");
  861. return -ENOMEM;
  862. }
  863. codec->private_data = (void *)sunxi_codec;
  864. snd_print("codec para init\n");
  865. /* get codec para from board config? */
  866. sunxi_codec->param = default_param;
  867. codec->codec_base_addr = (void *)SUNXI_CODEC_BASE_ADDR;
  868. codec->codec_dai->component = codec;
  869. reset = hal_reset_control_get(HAL_SUNXI_RESET, RST_BUS_AUDIO_CODEC);
  870. hal_reset_control_deassert(reset);
  871. hal_reset_control_put(reset);
  872. sunxi_codec->busclk = hal_clock_get(HAL_SUNXI_CCU, CLK_BUS_AUDIO_CODEC);
  873. sunxi_codec->moduleclk = hal_clock_get(HAL_SUNXI_CCU, CLK_AUDIO_DAC);
  874. sunxi_codec->moduleclk1 = hal_clock_get(HAL_SUNXI_CCU, CLK_AUDIO_ADC);
  875. sunxi_codec->pllclk = hal_clock_get(HAL_SUNXI_CCU, CLK_PLL_AUDIO0);
  876. hal_clk_set_parent(sunxi_codec->moduleclk, sunxi_codec->pllclk);
  877. hal_clk_set_parent(sunxi_codec->moduleclk1, sunxi_codec->pllclk);
  878. ret = hal_clock_enable(sunxi_codec->pllclk);
  879. if (ret != HAL_CLK_STATUS_OK)
  880. snd_err("pllclk clock enable failed.\n");
  881. ret = hal_clock_enable(sunxi_codec->busclk);
  882. if (ret != HAL_CLK_STATUS_OK)
  883. snd_err("busclk clock enable failed.\n");
  884. ret = hal_clock_enable(sunxi_codec->moduleclk);
  885. if (ret != HAL_CLK_STATUS_OK)
  886. snd_err("moduleclk clock enable failed.\n");
  887. ret = hal_clock_enable(sunxi_codec->moduleclk1);
  888. if (ret != HAL_CLK_STATUS_OK)
  889. snd_err("moduleclk1 clock enable failed.\n");
  890. sunxi_codec_init(codec);
  891. #ifdef SUNXI_ADC_DAUDIO_SYNC
  892. adc_daudio_sync_codec = codec;
  893. #endif
  894. hal_timer_init(SUNXI_TMR0);
  895. if (hal_gpio_to_irq(SUNXI_CODEC_JACK_DET, &sunxi_codec->irq) < 0)
  896. snd_err("sunxi jack gpio to irq err.\n");
  897. if (hal_gpio_irq_request(sunxi_codec->irq, sunxi_jack_irq_handler, IRQ_TYPE_EDGE_FALLING, sunxi_codec) < 0)
  898. snd_err("sunxi jack irq request err.\n");
  899. sunxi_jack_detect(sunxi_codec);
  900. if (hal_gpio_irq_enable(sunxi_codec->irq) < 0)
  901. snd_err("sunxi jack irq enable err.\n");
  902. return 0;
  903. }
  904. static int sun8iw20_codec_remove(struct snd_codec *codec)
  905. {
  906. struct sunxi_codec_info *sunxi_codec = codec->private_data;
  907. struct sunxi_codec_param *param = &sunxi_codec->param;
  908. if (param->adcdrc_cfg)
  909. adcdrc_enable(codec, 0);
  910. if (param->adchpf_cfg)
  911. adchpf_enable(codec, 0);
  912. if (param->dacdrc_cfg)
  913. dacdrc_enable(codec, 0);
  914. if (param->dachpf_cfg)
  915. dachpf_enable(codec, 0);
  916. hal_clock_disable(sunxi_codec->moduleclk);
  917. hal_clock_disable(sunxi_codec->moduleclk1);
  918. hal_clock_disable(sunxi_codec->pllclk);
  919. hal_gpio_irq_disable(sunxi_codec->irq);
  920. hal_gpio_irq_free(sunxi_codec->irq);
  921. hal_timer_uninit(SUNXI_TMR0);
  922. snd_free(sunxi_codec);
  923. codec->private_data = NULL;
  924. return 0;
  925. }
  926. struct snd_codec sunxi_audiocodec = {
  927. .name = "audiocodec",
  928. .codec_dai = sun8iw20_codec_dai,
  929. .codec_dai_num = ARRAY_SIZE(sun8iw20_codec_dai),
  930. .private_data = NULL,
  931. .probe = sun8iw20_codec_probe,
  932. .remove = sun8iw20_codec_remove,
  933. .controls = sunxi_codec_controls,
  934. .num_controls = ARRAY_SIZE(sunxi_codec_controls),
  935. };