start.S 2.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131
  1. /*
  2. * Copyright (c) 2006-2024, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2024/01/11 flyingcys The first version
  9. */
  10. #include "riscv-virt.h"
  11. .org 0
  12. .section .vectors, "ax"
  13. .globl _start
  14. .type _start,@function
  15. _start:
  16. .cfi_startproc
  17. .cfi_undefined ra
  18. .option push
  19. .option norelax
  20. // la gp, __global_pointer$
  21. .option pop
  22. // Continue primary hart
  23. csrr a0, mhartid
  24. li a1, PRIM_HART
  25. bne a0, a1, secondary
  26. li x1, 0
  27. li x2, 0
  28. li x3, 0
  29. li x4, 0
  30. li x5, 0
  31. li x6, 0
  32. li x7, 0
  33. li x8, 0
  34. li x9, 0
  35. li x10, 0
  36. li x11, 0
  37. li x12, 0
  38. li x13, 0
  39. li x14, 0
  40. li x15, 0
  41. li x16, 0
  42. li x17, 0
  43. li x18, 0
  44. li x19, 0
  45. li x20, 0
  46. li x21, 0
  47. li x22, 0
  48. li x23, 0
  49. li x24, 0
  50. li x25, 0
  51. li x26, 0
  52. li x27, 0
  53. li x28, 0
  54. li x29, 0
  55. li x30, 0
  56. li x31, 0
  57. // enable interrupt
  58. // li x3, 0x880
  59. // csrw mie, x3
  60. csrw mie, 0
  61. csrw mip, 0
  62. la t0, trap_entry
  63. csrw mtvec, t0
  64. #ifndef RISCV_QEMU
  65. // invalidate all memory for BTB,BHT,DCACHE,ICACHE
  66. li x3, 0x30013
  67. csrs mcor, x3
  68. // enable ICACHE,DCACHE,BHT,BTB,RAS,WA
  69. li x3, 0x7f
  70. csrs mhcr, x3
  71. // enable data_cache_prefetch, amr
  72. li x3, 0x610c
  73. csrs mhint, x3 #mhint
  74. #endif
  75. # enable fp
  76. li x3, 0x1 << 13
  77. csrs mstatus, x3
  78. // Primary hart
  79. la sp, _stack_top
  80. // Load data section
  81. la a0, _data_lma
  82. la a1, _data
  83. la a2, _edata
  84. bgeu a1, a2, 2f
  85. 1:
  86. LOAD t0, (a0)
  87. STOR t0, (a1)
  88. addi a0, a0, REGSIZE
  89. addi a1, a1, REGSIZE
  90. bltu a1, a2, 1b
  91. 2:
  92. // Clear bss section
  93. la a0, _bss
  94. la a1, _ebss
  95. bgeu a0, a1, 2f
  96. 1:
  97. // reduce branch time, be sure about bss alignment in linker script
  98. STOR zero, 0x00 (a0)
  99. STOR zero, 0x08 (a0)
  100. STOR zero, 0x10 (a0)
  101. STOR zero, 0x18 (a0)
  102. STOR zero, 0x20 (a0)
  103. STOR zero, 0x28 (a0)
  104. STOR zero, 0x30 (a0)
  105. STOR zero, 0x38 (a0)
  106. addi a0, a0, REGSIZE * 8
  107. bltu a0, a1, 1b
  108. 2:
  109. // argc, argv, envp is 0
  110. li a0, 0
  111. li a1, 0
  112. li a2, 0
  113. jal entry
  114. 1:
  115. wfi
  116. j 1b
  117. secondary:
  118. // TODO: Multicore is not supported
  119. wfi
  120. j secondary
  121. .cfi_endproc