rt-thread/bsp/rdk/s100/drivers/drv_can.h

#ifndef DRV_CAN_H__
#define DRV_CAN_H__

#include "rtthread.h"
#include "rtdevice.h"

#define FLEXCAN_RXIMR_COUNT                   (32U)
#define FLEXCAN_HR_TIME_STAMP_COUNT           (128U)
#define FLEXCAN_ERFFEL_COUNT                  (128U)

/*==================================================================================================
*                                      DEFINES AND MACROS
==================================================================================================*/
/* @brief Frames available in Rx FIFO flag shift */
#define FLEXCAN_IP_LEGACY_RXFIFO_FRAME_AVAILABLE  (5U)
/* @brief Rx FIFO warning flag shift */
#define FLEXCAN_IP_LEGACY_RXFIFO_WARNING          (6U)
/* @brief Rx FIFO overflow flag shift */
#define FLEXCAN_IP_LEGACY_RXFIFO_OVERFLOW         (7U)
/* @brief Frames available in Enhanced Rx FIFO flag shift */
#define FLEXCAN_IP_ENHANCED_RXFIFO_FRAME_AVAILABLE     (28U)
/* @brief Enhanced Rx FIFO Watermark Indication flag shift */
#define FLEXCAN_IP_ENHANCED_RXFIFO_WATERMARK           (29U)
/* @brief Enhanced Rx FIFO Overflow  flag shift */
#define FLEXCAN_IP_ENHANCED_RXFIFO_OVERFLOW            (30U)
/* @brief Enhanced Rx FIFO Underflow flag shift */
#define FLEXCAN_IP_ENHANCED_RXFIFO_UNDERFLOW           (31U)
/* @brief FlexCAN Enhanced Fifo Embedded RAM address offset */
#define FLEXCAN_IP_FEATURE_ENHANCED_FIFO_RAM_OFFSET        (0x00002000u)

/* @brief FlexCAN Enhanced Fifo Embedded RAM count */
#define FLEXCAN_IP_FEATURE_ENHANCED_FIFO_RAM_COUNT         (640u)

/* @brief FlexCAN Embedded RAM address offset */
#define FLEXCAN_IP_FEATURE_RAM_OFFSET                      (0x00000080u)

/* @brief FlexCAN Expandable Embedded RAM address offset */
#define FLEXCAN_IP_FEATURE_EXP_RAM_OFFSET                  (0x00001000u)

/* @brief FlexCAN Enhanced Fifo filter Embedded RAM address offset */
#define FLEXCAN_IP_FEATURE_ENHANCED_FIFO_FILTER_RAM_OFFSET     (0x00003000U)

/* @brief FlexCAN Rx SMB Timestamp Embedded RAM address offset */
#define FLEXCAN_IP_FEATURE_RXSMB_TIMESTAMP_RAM_OFFSET          (0xC20U)

/* @brief FlexCAN Rx SMB Timestamp Embedded RAM count */
#define FLEXCAN_IP_FEATURE_RXSMB_TIMESTAMP_RAM_COUNT           (2U)

/* @brief FlexCAN SMB 1 Embedded RAM count */
#define FLEXCAN_IP_FEATURE_SMB_1_RAM_COUNT                     (120U)

/* @brief FlexCAN SMB 2 Embedded RAM address offset */
#define FLEXCAN_IP_FEATURE_SMB_2_RAM_OFFSET                    (0xF28U)

/* @brief FlexCAN SMB 2 Embedded RAM count */
#define FLEXCAN_IP_FEATURE_SMB_2_RAM_COUNT                     (54U)

#define FLEXCAN_IP_ALL_INT                     (0x3B0006U)
#define FLEXCAN_IP_RAM1n_COUNT                 (512U)

typedef struct
{
    volatile rt_uint32_t MCR;
    volatile rt_uint32_t CTRL1;
    volatile rt_uint32_t TIMER;
    rt_uint8_t RESERVED_0[4];
    volatile rt_uint32_t RXMGMASK;
    volatile rt_uint32_t RX14MASK;
    volatile rt_uint32_t RX15MASK;
    volatile rt_uint32_t ECR;
    volatile rt_uint32_t ESR1;
    volatile rt_uint32_t IMASK2;
    volatile rt_uint32_t IMASK1;
    volatile rt_uint32_t IFLAG2;
    volatile rt_uint32_t IFLAG1;
    volatile rt_uint32_t CTRL2;
    volatile const rt_uint32_t ESR2;
    rt_uint8_t RESERVED_1[8];
    volatile const rt_uint32_t CRCR;
    volatile rt_uint32_t RXFGMASK;
    volatile const rt_uint32_t RXFIR;
    volatile rt_uint32_t CBT;
    rt_uint8_t RESERVED_2[20];
    volatile rt_uint32_t IMASK4;
    volatile rt_uint32_t IMASK3;
    volatile rt_uint32_t IFLAG4;
    volatile rt_uint32_t IFLAG3;
    rt_uint8_t RESERVED_3[2056];
    volatile rt_uint32_t RXIMR[FLEXCAN_RXIMR_COUNT];
    rt_uint8_t RESERVED_4[480];
    volatile rt_uint32_t MECR;
    volatile rt_uint32_t ERRIAR;
    volatile rt_uint32_t ERRIDPR;
    volatile rt_uint32_t ERRIPPR;
    volatile const rt_uint32_t RERRAR;
    volatile const rt_uint32_t RERRDR;
    volatile const rt_uint32_t RERRSYNR;
    volatile rt_uint32_t ERRSR;
    rt_uint8_t RESERVED_5[240];
    volatile rt_uint32_t EPRS;
    volatile rt_uint32_t ENCBT;
    volatile rt_uint32_t EDCBT;
    volatile rt_uint32_t ETDC;
    volatile rt_uint32_t FDCTRL;
    volatile rt_uint32_t FDCBT;
    volatile const rt_uint32_t FDCRC;
    volatile rt_uint32_t ERFCR;
    volatile rt_uint32_t ERFIER;
    volatile rt_uint32_t ERFSR;
    rt_uint8_t RESERVED_6[24];
    volatile rt_uint32_t HR_TIME_STAMP[FLEXCAN_HR_TIME_STAMP_COUNT];
    rt_uint8_t RESERVED_7[8656];
    volatile rt_uint32_t ERFFEL[FLEXCAN_ERFFEL_COUNT];
    volatile rt_uint32_t TSV;
    volatile rt_uint32_t TSCTRL;
    volatile rt_uint32_t TSLCNT;
    volatile rt_uint32_t HREOI;
    volatile rt_uint32_t BITEOI;
    volatile rt_uint32_t TSIFLAG;
} s100_can_regs_t;

/* ----------------------------------------------------------------------------
   -- FLEXCAN Register Masks
   ---------------------------------------------------------------------------- */
#define FLEXCAN_MCR_MAXMB_MASK                   (0x7FU)
#define FLEXCAN_MCR_MAXMB_SHIFT                  (0U)
#define FLEXCAN_MCR_MAXMB_WIDTH                  (7U)
#define FLEXCAN_MCR_MAXMB(x)                     (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_MAXMB_SHIFT)) & FLEXCAN_MCR_MAXMB_MASK)

#define FLEXCAN_MCR_IDAM_MASK                    (0x300U)
#define FLEXCAN_MCR_IDAM_SHIFT                   (8U)
#define FLEXCAN_MCR_IDAM_WIDTH                   (2U)
#define FLEXCAN_MCR_IDAM(x)                      (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_IDAM_SHIFT)) & FLEXCAN_MCR_IDAM_MASK)

#define FLEXCAN_MCR_FDEN_MASK                    (0x800U)
#define FLEXCAN_MCR_FDEN_SHIFT                   (11U)
#define FLEXCAN_MCR_FDEN_WIDTH                   (1U)
#define FLEXCAN_MCR_FDEN(x)                      (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_FDEN_SHIFT)) & FLEXCAN_MCR_FDEN_MASK)

#define FLEXCAN_MCR_AEN_MASK                     (0x1000U)
#define FLEXCAN_MCR_AEN_SHIFT                    (12U)
#define FLEXCAN_MCR_AEN_WIDTH                    (1U)
#define FLEXCAN_MCR_AEN(x)                       (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_AEN_SHIFT)) & FLEXCAN_MCR_AEN_MASK)

#define FLEXCAN_MCR_LPRIOEN_MASK                 (0x2000U)
#define FLEXCAN_MCR_LPRIOEN_SHIFT                (13U)
#define FLEXCAN_MCR_LPRIOEN_WIDTH                (1U)
#define FLEXCAN_MCR_LPRIOEN(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_LPRIOEN_SHIFT)) & FLEXCAN_MCR_LPRIOEN_MASK)

#define FLEXCAN_MCR_DMA_MASK                     (0x8000U)
#define FLEXCAN_MCR_DMA_SHIFT                    (15U)
#define FLEXCAN_MCR_DMA_WIDTH                    (1U)
#define FLEXCAN_MCR_DMA(x)                       (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_DMA_SHIFT)) & FLEXCAN_MCR_DMA_MASK)

#define FLEXCAN_MCR_IRMQ_MASK                    (0x10000U)
#define FLEXCAN_MCR_IRMQ_SHIFT                   (16U)
#define FLEXCAN_MCR_IRMQ_WIDTH                   (1U)
#define FLEXCAN_MCR_IRMQ(x)                      (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_IRMQ_SHIFT)) & FLEXCAN_MCR_IRMQ_MASK)

#define FLEXCAN_MCR_SRXDIS_MASK                  (0x20000U)
#define FLEXCAN_MCR_SRXDIS_SHIFT                 (17U)
#define FLEXCAN_MCR_SRXDIS_WIDTH                 (1U)
#define FLEXCAN_MCR_SRXDIS(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_SRXDIS_SHIFT)) & FLEXCAN_MCR_SRXDIS_MASK)

#define FLEXCAN_MCR_LPMACK_MASK                  (0x100000U)
#define FLEXCAN_MCR_LPMACK_SHIFT                 (20U)
#define FLEXCAN_MCR_LPMACK_WIDTH                 (1U)
#define FLEXCAN_MCR_LPMACK(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_LPMACK_SHIFT)) & FLEXCAN_MCR_LPMACK_MASK)

#define FLEXCAN_MCR_WRNEN_MASK                   (0x200000U)
#define FLEXCAN_MCR_WRNEN_SHIFT                  (21U)
#define FLEXCAN_MCR_WRNEN_WIDTH                  (1U)
#define FLEXCAN_MCR_WRNEN(x)                     (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_WRNEN_SHIFT)) & FLEXCAN_MCR_WRNEN_MASK)

#define FLEXCAN_MCR_FRZACK_MASK                  (0x1000000U)
#define FLEXCAN_MCR_FRZACK_SHIFT                 (24U)
#define FLEXCAN_MCR_FRZACK_WIDTH                 (1U)
#define FLEXCAN_MCR_FRZACK(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_FRZACK_SHIFT)) & FLEXCAN_MCR_FRZACK_MASK)

#define FLEXCAN_MCR_SOFTRST_MASK                 (0x2000000U)
#define FLEXCAN_MCR_SOFTRST_SHIFT                (25U)
#define FLEXCAN_MCR_SOFTRST_WIDTH                (1U)
#define FLEXCAN_MCR_SOFTRST(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_SOFTRST_SHIFT)) & FLEXCAN_MCR_SOFTRST_MASK)

#define FLEXCAN_MCR_NOTRDY_MASK                  (0x8000000U)
#define FLEXCAN_MCR_NOTRDY_SHIFT                 (27U)
#define FLEXCAN_MCR_NOTRDY_WIDTH                 (1U)
#define FLEXCAN_MCR_NOTRDY(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_NOTRDY_SHIFT)) & FLEXCAN_MCR_NOTRDY_MASK)

#define FLEXCAN_MCR_HALT_MASK                    (0x10000000U)
#define FLEXCAN_MCR_HALT_SHIFT                   (28U)
#define FLEXCAN_MCR_HALT_WIDTH                   (1U)
#define FLEXCAN_MCR_HALT(x)                      (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_HALT_SHIFT)) & FLEXCAN_MCR_HALT_MASK)

#define FLEXCAN_MCR_RFEN_MASK                    (0x20000000U)
#define FLEXCAN_MCR_RFEN_SHIFT                   (29U)
#define FLEXCAN_MCR_RFEN_WIDTH                   (1U)
#define FLEXCAN_MCR_RFEN(x)                      (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_RFEN_SHIFT)) & FLEXCAN_MCR_RFEN_MASK)

#define FLEXCAN_MCR_FRZ_MASK                     (0x40000000U)
#define FLEXCAN_MCR_FRZ_SHIFT                    (30U)
#define FLEXCAN_MCR_FRZ_WIDTH                    (1U)
#define FLEXCAN_MCR_FRZ(x)                       (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_FRZ_SHIFT)) & FLEXCAN_MCR_FRZ_MASK)

#define FLEXCAN_MCR_MDIS_MASK                    (0x80000000U)
#define FLEXCAN_MCR_MDIS_SHIFT                   (31U)
#define FLEXCAN_MCR_MDIS_WIDTH                   (1U)
#define FLEXCAN_MCR_MDIS(x)                      (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MCR_MDIS_SHIFT)) & FLEXCAN_MCR_MDIS_MASK)

#define FLEXCAN_CTRL1_PROPSEG_MASK               (0x7U)
#define FLEXCAN_CTRL1_PROPSEG_SHIFT              (0U)
#define FLEXCAN_CTRL1_PROPSEG_WIDTH              (3U)
#define FLEXCAN_CTRL1_PROPSEG(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_PROPSEG_SHIFT)) & FLEXCAN_CTRL1_PROPSEG_MASK)

#define FLEXCAN_CTRL1_LOM_MASK                   (0x8U)
#define FLEXCAN_CTRL1_LOM_SHIFT                  (3U)
#define FLEXCAN_CTRL1_LOM_WIDTH                  (1U)
#define FLEXCAN_CTRL1_LOM(x)                     (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_LOM_SHIFT)) & FLEXCAN_CTRL1_LOM_MASK)

#define FLEXCAN_CTRL1_LBUF_MASK                  (0x10U)
#define FLEXCAN_CTRL1_LBUF_SHIFT                 (4U)
#define FLEXCAN_CTRL1_LBUF_WIDTH                 (1U)
#define FLEXCAN_CTRL1_LBUF(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_LBUF_SHIFT)) & FLEXCAN_CTRL1_LBUF_MASK)

#define FLEXCAN_CTRL1_TSYN_MASK                  (0x20U)
#define FLEXCAN_CTRL1_TSYN_SHIFT                 (5U)
#define FLEXCAN_CTRL1_TSYN_WIDTH                 (1U)
#define FLEXCAN_CTRL1_TSYN(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_TSYN_SHIFT)) & FLEXCAN_CTRL1_TSYN_MASK)

#define FLEXCAN_CTRL1_BOFFREC_MASK               (0x40U)
#define FLEXCAN_CTRL1_BOFFREC_SHIFT              (6U)
#define FLEXCAN_CTRL1_BOFFREC_WIDTH              (1U)
#define FLEXCAN_CTRL1_BOFFREC(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_BOFFREC_SHIFT)) & FLEXCAN_CTRL1_BOFFREC_MASK)

#define FLEXCAN_CTRL1_SMP_MASK                   (0x80U)
#define FLEXCAN_CTRL1_SMP_SHIFT                  (7U)
#define FLEXCAN_CTRL1_SMP_WIDTH                  (1U)
#define FLEXCAN_CTRL1_SMP(x)                     (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_SMP_SHIFT)) & FLEXCAN_CTRL1_SMP_MASK)

#define FLEXCAN_CTRL1_CLKSRC_MASK                (0x2000U)/* zjh add */
#define FLEXCAN_CTRL1_CLKSRC_SHIFT                 (13U)
#define FLEXCAN_CTRL1_CLKSRC(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_CLKSRC_SHIFT)) & FLEXCAN_CTRL1_CLKSRC_MASK)


#define FLEXCAN_CTRL1_RWRNMSK_MASK               (0x400U)
#define FLEXCAN_CTRL1_RWRNMSK_SHIFT              (10U)
#define FLEXCAN_CTRL1_RWRNMSK_WIDTH              (1U)
#define FLEXCAN_CTRL1_RWRNMSK(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_RWRNMSK_SHIFT)) & FLEXCAN_CTRL1_RWRNMSK_MASK)

#define FLEXCAN_CTRL1_TWRNMSK_MASK               (0x800U)
#define FLEXCAN_CTRL1_TWRNMSK_SHIFT              (11U)
#define FLEXCAN_CTRL1_TWRNMSK_WIDTH              (1U)
#define FLEXCAN_CTRL1_TWRNMSK(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_TWRNMSK_SHIFT)) & FLEXCAN_CTRL1_TWRNMSK_MASK)

#define FLEXCAN_CTRL1_LPB_MASK                   (0x1000U)
#define FLEXCAN_CTRL1_LPB_SHIFT                  (12U)
#define FLEXCAN_CTRL1_LPB_WIDTH                  (1U)
#define FLEXCAN_CTRL1_LPB(x)                     (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_LPB_SHIFT)) & FLEXCAN_CTRL1_LPB_MASK)

#define FLEXCAN_CTRL1_ERRMSK_MASK                (0x4000U)
#define FLEXCAN_CTRL1_ERRMSK_SHIFT               (14U)
#define FLEXCAN_CTRL1_ERRMSK_WIDTH               (1U)
#define FLEXCAN_CTRL1_ERRMSK(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_ERRMSK_SHIFT)) & FLEXCAN_CTRL1_ERRMSK_MASK)

#define FLEXCAN_CTRL1_BOFFMSK_MASK               (0x8000U)
#define FLEXCAN_CTRL1_BOFFMSK_SHIFT              (15U)
#define FLEXCAN_CTRL1_BOFFMSK_WIDTH              (1U)
#define FLEXCAN_CTRL1_BOFFMSK(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_BOFFMSK_SHIFT)) & FLEXCAN_CTRL1_BOFFMSK_MASK)

#define FLEXCAN_CTRL1_PSEG2_MASK                 (0x70000U)
#define FLEXCAN_CTRL1_PSEG2_SHIFT                (16U)
#define FLEXCAN_CTRL1_PSEG2_WIDTH                (3U)
#define FLEXCAN_CTRL1_PSEG2(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_PSEG2_SHIFT)) & FLEXCAN_CTRL1_PSEG2_MASK)

#define FLEXCAN_CTRL1_PSEG1_MASK                 (0x380000U)
#define FLEXCAN_CTRL1_PSEG1_SHIFT                (19U)
#define FLEXCAN_CTRL1_PSEG1_WIDTH                (3U)
#define FLEXCAN_CTRL1_PSEG1(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_PSEG1_SHIFT)) & FLEXCAN_CTRL1_PSEG1_MASK)

#define FLEXCAN_CTRL1_RJW_MASK                   (0xC00000U)
#define FLEXCAN_CTRL1_RJW_SHIFT                  (22U)
#define FLEXCAN_CTRL1_RJW_WIDTH                  (2U)
#define FLEXCAN_CTRL1_RJW(x)                     (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_RJW_SHIFT)) & FLEXCAN_CTRL1_RJW_MASK)

#define FLEXCAN_CTRL1_PRESDIV_MASK               (0xFF000000U)
#define FLEXCAN_CTRL1_PRESDIV_SHIFT              (24U)
#define FLEXCAN_CTRL1_PRESDIV_WIDTH              (8U)
#define FLEXCAN_CTRL1_PRESDIV(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL1_PRESDIV_SHIFT)) & FLEXCAN_CTRL1_PRESDIV_MASK)

#define FLEXCAN_TIMER_TIMER_MASK                 (0xFFFFU)
#define FLEXCAN_TIMER_TIMER_SHIFT                (0U)
#define FLEXCAN_TIMER_TIMER_WIDTH                (16U)
#define FLEXCAN_TIMER_TIMER(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_TIMER_TIMER_SHIFT)) & FLEXCAN_TIMER_TIMER_MASK)

#define FLEXCAN_RXMGMASK_MG_MASK                 (0xFFFFFFFFU)
#define FLEXCAN_RXMGMASK_MG_SHIFT                (0U)
#define FLEXCAN_RXMGMASK_MG_WIDTH                (32U)
#define FLEXCAN_RXMGMASK_MG(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RXMGMASK_MG_SHIFT)) & FLEXCAN_RXMGMASK_MG_MASK)

#define FLEXCAN_RX14MASK_RX14M_MASK              (0xFFFFFFFFU)
#define FLEXCAN_RX14MASK_RX14M_SHIFT             (0U)
#define FLEXCAN_RX14MASK_RX14M_WIDTH             (32U)
#define FLEXCAN_RX14MASK_RX14M(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RX14MASK_RX14M_SHIFT)) & FLEXCAN_RX14MASK_RX14M_MASK)

#define FLEXCAN_RX15MASK_RX15M_MASK              (0xFFFFFFFFU)
#define FLEXCAN_RX15MASK_RX15M_SHIFT             (0U)
#define FLEXCAN_RX15MASK_RX15M_WIDTH             (32U)
#define FLEXCAN_RX15MASK_RX15M(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RX15MASK_RX15M_SHIFT)) & FLEXCAN_RX15MASK_RX15M_MASK)

#define FLEXCAN_ECR_TXERRCNT_MASK                (0xFFU)
#define FLEXCAN_ECR_TXERRCNT_SHIFT               (0U)
#define FLEXCAN_ECR_TXERRCNT_WIDTH               (8U)
#define FLEXCAN_ECR_TXERRCNT(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ECR_TXERRCNT_SHIFT)) & FLEXCAN_ECR_TXERRCNT_MASK)

#define FLEXCAN_ECR_RXERRCNT_MASK                (0xFF00U)
#define FLEXCAN_ECR_RXERRCNT_SHIFT               (8U)
#define FLEXCAN_ECR_RXERRCNT_WIDTH               (8U)
#define FLEXCAN_ECR_RXERRCNT(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ECR_RXERRCNT_SHIFT)) & FLEXCAN_ECR_RXERRCNT_MASK)

#define FLEXCAN_ECR_TXERRCNT_FAST_MASK           (0xFF0000U)
#define FLEXCAN_ECR_TXERRCNT_FAST_SHIFT          (16U)
#define FLEXCAN_ECR_TXERRCNT_FAST_WIDTH          (8U)
#define FLEXCAN_ECR_TXERRCNT_FAST(x)             (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ECR_TXERRCNT_FAST_SHIFT)) & FLEXCAN_ECR_TXERRCNT_FAST_MASK)

#define FLEXCAN_ECR_RXERRCNT_FAST_MASK           (0xFF000000U)
#define FLEXCAN_ECR_RXERRCNT_FAST_SHIFT          (24U)
#define FLEXCAN_ECR_RXERRCNT_FAST_WIDTH          (8U)
#define FLEXCAN_ECR_RXERRCNT_FAST(x)             (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ECR_RXERRCNT_FAST_SHIFT)) & FLEXCAN_ECR_RXERRCNT_FAST_MASK)

#define FLEXCAN_ESR1_ERRINT_MASK                 (0x2U)
#define FLEXCAN_ESR1_ERRINT_SHIFT                (1U)
#define FLEXCAN_ESR1_ERRINT_WIDTH                (1U)
#define FLEXCAN_ESR1_ERRINT(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_ERRINT_SHIFT)) & FLEXCAN_ESR1_ERRINT_MASK)

#define FLEXCAN_ESR1_BOFFINT_MASK                (0x4U)
#define FLEXCAN_ESR1_BOFFINT_SHIFT               (2U)
#define FLEXCAN_ESR1_BOFFINT_WIDTH               (1U)
#define FLEXCAN_ESR1_BOFFINT(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_BOFFINT_SHIFT)) & FLEXCAN_ESR1_BOFFINT_MASK)

#define FLEXCAN_ESR1_RX_MASK                     (0x8U)
#define FLEXCAN_ESR1_RX_SHIFT                    (3U)
#define FLEXCAN_ESR1_RX_WIDTH                    (1U)
#define FLEXCAN_ESR1_RX(x)                       (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_RX_SHIFT)) & FLEXCAN_ESR1_RX_MASK)

#define FLEXCAN_ESR1_FLTCONF_MASK                (0x30U)
#define FLEXCAN_ESR1_FLTCONF_SHIFT               (4U)
#define FLEXCAN_ESR1_FLTCONF_WIDTH               (2U)
#define FLEXCAN_ESR1_FLTCONF(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_FLTCONF_SHIFT)) & FLEXCAN_ESR1_FLTCONF_MASK)

#define FLEXCAN_ESR1_TX_MASK                     (0x40U)
#define FLEXCAN_ESR1_TX_SHIFT                    (6U)
#define FLEXCAN_ESR1_TX_WIDTH                    (1U)
#define FLEXCAN_ESR1_TX(x)                       (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_TX_SHIFT)) & FLEXCAN_ESR1_TX_MASK)

#define FLEXCAN_ESR1_IDLE_MASK                   (0x80U)
#define FLEXCAN_ESR1_IDLE_SHIFT                  (7U)
#define FLEXCAN_ESR1_IDLE_WIDTH                  (1U)
#define FLEXCAN_ESR1_IDLE(x)                     (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_IDLE_SHIFT)) & FLEXCAN_ESR1_IDLE_MASK)

#define FLEXCAN_ESR1_RXWRN_MASK                  (0x100U)
#define FLEXCAN_ESR1_RXWRN_SHIFT                 (8U)
#define FLEXCAN_ESR1_RXWRN_WIDTH                 (1U)
#define FLEXCAN_ESR1_RXWRN(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_RXWRN_SHIFT)) & FLEXCAN_ESR1_RXWRN_MASK)

#define FLEXCAN_ESR1_TXWRN_MASK                  (0x200U)
#define FLEXCAN_ESR1_TXWRN_SHIFT                 (9U)
#define FLEXCAN_ESR1_TXWRN_WIDTH                 (1U)
#define FLEXCAN_ESR1_TXWRN(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_TXWRN_SHIFT)) & FLEXCAN_ESR1_TXWRN_MASK)

#define FLEXCAN_ESR1_STFERR_MASK                 (0x400U)
#define FLEXCAN_ESR1_STFERR_SHIFT                (10U)
#define FLEXCAN_ESR1_STFERR_WIDTH                (1U)
#define FLEXCAN_ESR1_STFERR(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_STFERR_SHIFT)) & FLEXCAN_ESR1_STFERR_MASK)

#define FLEXCAN_ESR1_FRMERR_MASK                 (0x800U)
#define FLEXCAN_ESR1_FRMERR_SHIFT                (11U)
#define FLEXCAN_ESR1_FRMERR_WIDTH                (1U)
#define FLEXCAN_ESR1_FRMERR(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_FRMERR_SHIFT)) & FLEXCAN_ESR1_FRMERR_MASK)

#define FLEXCAN_ESR1_CRCERR_MASK                 (0x1000U)
#define FLEXCAN_ESR1_CRCERR_SHIFT                (12U)
#define FLEXCAN_ESR1_CRCERR_WIDTH                (1U)
#define FLEXCAN_ESR1_CRCERR(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_CRCERR_SHIFT)) & FLEXCAN_ESR1_CRCERR_MASK)

#define FLEXCAN_ESR1_ACKERR_MASK                 (0x2000U)
#define FLEXCAN_ESR1_ACKERR_SHIFT                (13U)
#define FLEXCAN_ESR1_ACKERR_WIDTH                (1U)
#define FLEXCAN_ESR1_ACKERR(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_ACKERR_SHIFT)) & FLEXCAN_ESR1_ACKERR_MASK)

#define FLEXCAN_ESR1_BIT0ERR_MASK                (0x4000U)
#define FLEXCAN_ESR1_BIT0ERR_SHIFT               (14U)
#define FLEXCAN_ESR1_BIT0ERR_WIDTH               (1U)
#define FLEXCAN_ESR1_BIT0ERR(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_BIT0ERR_SHIFT)) & FLEXCAN_ESR1_BIT0ERR_MASK)

#define FLEXCAN_ESR1_BIT1ERR_MASK                (0x8000U)
#define FLEXCAN_ESR1_BIT1ERR_SHIFT               (15U)
#define FLEXCAN_ESR1_BIT1ERR_WIDTH               (1U)
#define FLEXCAN_ESR1_BIT1ERR(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_BIT1ERR_SHIFT)) & FLEXCAN_ESR1_BIT1ERR_MASK)

#define FLEXCAN_ESR1_RWRNINT_MASK                (0x10000U)
#define FLEXCAN_ESR1_RWRNINT_SHIFT               (16U)
#define FLEXCAN_ESR1_RWRNINT_WIDTH               (1U)
#define FLEXCAN_ESR1_RWRNINT(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_RWRNINT_SHIFT)) & FLEXCAN_ESR1_RWRNINT_MASK)

#define FLEXCAN_ESR1_TWRNINT_MASK                (0x20000U)
#define FLEXCAN_ESR1_TWRNINT_SHIFT               (17U)
#define FLEXCAN_ESR1_TWRNINT_WIDTH               (1U)
#define FLEXCAN_ESR1_TWRNINT(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_TWRNINT_SHIFT)) & FLEXCAN_ESR1_TWRNINT_MASK)

#define FLEXCAN_ESR1_SYNCH_MASK                  (0x40000U)
#define FLEXCAN_ESR1_SYNCH_SHIFT                 (18U)
#define FLEXCAN_ESR1_SYNCH_WIDTH                 (1U)
#define FLEXCAN_ESR1_SYNCH(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_SYNCH_SHIFT)) & FLEXCAN_ESR1_SYNCH_MASK)

#define FLEXCAN_ESR1_BOFFDONEINT_MASK            (0x80000U)
#define FLEXCAN_ESR1_BOFFDONEINT_SHIFT           (19U)
#define FLEXCAN_ESR1_BOFFDONEINT_WIDTH           (1U)
#define FLEXCAN_ESR1_BOFFDONEINT(x)              (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_BOFFDONEINT_SHIFT)) & FLEXCAN_ESR1_BOFFDONEINT_MASK)

#define FLEXCAN_ESR1_ERRINT_FAST_MASK            (0x100000U)
#define FLEXCAN_ESR1_ERRINT_FAST_SHIFT           (20U)
#define FLEXCAN_ESR1_ERRINT_FAST_WIDTH           (1U)
#define FLEXCAN_ESR1_ERRINT_FAST(x)              (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_ERRINT_FAST_SHIFT)) & FLEXCAN_ESR1_ERRINT_FAST_MASK)

#define FLEXCAN_ESR1_ERROVR_MASK                 (0x200000U)
#define FLEXCAN_ESR1_ERROVR_SHIFT                (21U)
#define FLEXCAN_ESR1_ERROVR_WIDTH                (1U)
#define FLEXCAN_ESR1_ERROVR(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_ERROVR_SHIFT)) & FLEXCAN_ESR1_ERROVR_MASK)

#define FLEXCAN_ESR1_STFERR_FAST_MASK            (0x4000000U)
#define FLEXCAN_ESR1_STFERR_FAST_SHIFT           (26U)
#define FLEXCAN_ESR1_STFERR_FAST_WIDTH           (1U)
#define FLEXCAN_ESR1_STFERR_FAST(x)              (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_STFERR_FAST_SHIFT)) & FLEXCAN_ESR1_STFERR_FAST_MASK)

#define FLEXCAN_ESR1_FRMERR_FAST_MASK            (0x8000000U)
#define FLEXCAN_ESR1_FRMERR_FAST_SHIFT           (27U)
#define FLEXCAN_ESR1_FRMERR_FAST_WIDTH           (1U)
#define FLEXCAN_ESR1_FRMERR_FAST(x)              (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_FRMERR_FAST_SHIFT)) & FLEXCAN_ESR1_FRMERR_FAST_MASK)

#define FLEXCAN_ESR1_CRCERR_FAST_MASK            (0x10000000U)
#define FLEXCAN_ESR1_CRCERR_FAST_SHIFT           (28U)
#define FLEXCAN_ESR1_CRCERR_FAST_WIDTH           (1U)
#define FLEXCAN_ESR1_CRCERR_FAST(x)              (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_CRCERR_FAST_SHIFT)) & FLEXCAN_ESR1_CRCERR_FAST_MASK)

#define FLEXCAN_ESR1_BIT0ERR_FAST_MASK           (0x40000000U)
#define FLEXCAN_ESR1_BIT0ERR_FAST_SHIFT          (30U)
#define FLEXCAN_ESR1_BIT0ERR_FAST_WIDTH          (1U)
#define FLEXCAN_ESR1_BIT0ERR_FAST(x)             (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_BIT0ERR_FAST_SHIFT)) & FLEXCAN_ESR1_BIT0ERR_FAST_MASK)

#define FLEXCAN_ESR1_BIT1ERR_FAST_MASK           (0x80000000U)
#define FLEXCAN_ESR1_BIT1ERR_FAST_SHIFT          (31U)
#define FLEXCAN_ESR1_BIT1ERR_FAST_WIDTH          (1U)
#define FLEXCAN_ESR1_BIT1ERR_FAST(x)             (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR1_BIT1ERR_FAST_SHIFT)) & FLEXCAN_ESR1_BIT1ERR_FAST_MASK)

#define FLEXCAN_IMASK2_BUF63TO32M_MASK           (0xFFFFFFFFU)
#define FLEXCAN_IMASK2_BUF63TO32M_SHIFT          (0U)
#define FLEXCAN_IMASK2_BUF63TO32M_WIDTH          (32U)
#define FLEXCAN_IMASK2_BUF63TO32M(x)             (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_IMASK2_BUF63TO32M_SHIFT)) & FLEXCAN_IMASK2_BUF63TO32M_MASK)

#define FLEXCAN_IMASK1_BUF31TO0M_MASK            (0xFFFFFFFFU)
#define FLEXCAN_IMASK1_BUF31TO0M_SHIFT           (0U)
#define FLEXCAN_IMASK1_BUF31TO0M_WIDTH           (32U)
#define FLEXCAN_IMASK1_BUF31TO0M(x)              (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_IMASK1_BUF31TO0M_SHIFT)) & FLEXCAN_IMASK1_BUF31TO0M_MASK)

#define FLEXCAN_IFLAG2_BUF63TO32I_MASK           (0xFFFFFFFFU)
#define FLEXCAN_IFLAG2_BUF63TO32I_SHIFT          (0U)
#define FLEXCAN_IFLAG2_BUF63TO32I_WIDTH          (32U)
#define FLEXCAN_IFLAG2_BUF63TO32I(x)             (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_IFLAG2_BUF63TO32I_SHIFT)) & FLEXCAN_IFLAG2_BUF63TO32I_MASK)

#define FLEXCAN_IFLAG1_BUF0I_MASK                (0x1U)
#define FLEXCAN_IFLAG1_BUF0I_SHIFT               (0U)
#define FLEXCAN_IFLAG1_BUF0I_WIDTH               (1U)
#define FLEXCAN_IFLAG1_BUF0I(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_IFLAG1_BUF0I_SHIFT)) & FLEXCAN_IFLAG1_BUF0I_MASK)

#define FLEXCAN_IFLAG1_BUF4TO1I_MASK             (0x1EU)
#define FLEXCAN_IFLAG1_BUF4TO1I_SHIFT            (1U)
#define FLEXCAN_IFLAG1_BUF4TO1I_WIDTH            (4U)
#define FLEXCAN_IFLAG1_BUF4TO1I(x)               (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_IFLAG1_BUF4TO1I_SHIFT)) & FLEXCAN_IFLAG1_BUF4TO1I_MASK)

#define FLEXCAN_IFLAG1_BUF5I_MASK                (0x20U)
#define FLEXCAN_IFLAG1_BUF5I_SHIFT               (5U)
#define FLEXCAN_IFLAG1_BUF5I_WIDTH               (1U)
#define FLEXCAN_IFLAG1_BUF5I(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_IFLAG1_BUF5I_SHIFT)) & FLEXCAN_IFLAG1_BUF5I_MASK)

#define FLEXCAN_IFLAG1_BUF6I_MASK                (0x40U)
#define FLEXCAN_IFLAG1_BUF6I_SHIFT               (6U)
#define FLEXCAN_IFLAG1_BUF6I_WIDTH               (1U)
#define FLEXCAN_IFLAG1_BUF6I(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_IFLAG1_BUF6I_SHIFT)) & FLEXCAN_IFLAG1_BUF6I_MASK)

#define FLEXCAN_IFLAG1_BUF7I_MASK                (0x80U)
#define FLEXCAN_IFLAG1_BUF7I_SHIFT               (7U)
#define FLEXCAN_IFLAG1_BUF7I_WIDTH               (1U)
#define FLEXCAN_IFLAG1_BUF7I(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_IFLAG1_BUF7I_SHIFT)) & FLEXCAN_IFLAG1_BUF7I_MASK)

#define FLEXCAN_IFLAG1_BUF31TO8I_MASK            (0xFFFFFF00U)
#define FLEXCAN_IFLAG1_BUF31TO8I_SHIFT           (8U)
#define FLEXCAN_IFLAG1_BUF31TO8I_WIDTH           (24U)
#define FLEXCAN_IFLAG1_BUF31TO8I(x)              (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_IFLAG1_BUF31TO8I_SHIFT)) & FLEXCAN_IFLAG1_BUF31TO8I_MASK)

#define FLEXCAN_CTRL2_TSTAMPCAP_MASK             (0xC0U)
#define FLEXCAN_CTRL2_TSTAMPCAP_SHIFT            (6U)
#define FLEXCAN_CTRL2_TSTAMPCAP_WIDTH            (2U)
#define FLEXCAN_CTRL2_TSTAMPCAP(x)               (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_TSTAMPCAP_SHIFT)) & FLEXCAN_CTRL2_TSTAMPCAP_MASK)

#define FLEXCAN_CTRL2_MBTSBASE_MASK              (0x300U)
#define FLEXCAN_CTRL2_MBTSBASE_SHIFT             (8U)
#define FLEXCAN_CTRL2_MBTSBASE_WIDTH             (2U)
#define FLEXCAN_CTRL2_MBTSBASE(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_MBTSBASE_SHIFT)) & FLEXCAN_CTRL2_MBTSBASE_MASK)

#define FLEXCAN_CTRL2_EDFLTDIS_MASK              (0x800U)
#define FLEXCAN_CTRL2_EDFLTDIS_SHIFT             (11U)
#define FLEXCAN_CTRL2_EDFLTDIS_WIDTH             (1U)
#define FLEXCAN_CTRL2_EDFLTDIS(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_EDFLTDIS_SHIFT)) & FLEXCAN_CTRL2_EDFLTDIS_MASK)

#define FLEXCAN_CTRL2_ISOCANFDEN_MASK            (0x1000U)
#define FLEXCAN_CTRL2_ISOCANFDEN_SHIFT           (12U)
#define FLEXCAN_CTRL2_ISOCANFDEN_WIDTH           (1U)
#define FLEXCAN_CTRL2_ISOCANFDEN(x)              (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_ISOCANFDEN_SHIFT)) & FLEXCAN_CTRL2_ISOCANFDEN_MASK)

#define FLEXCAN_CTRL2_BTE_MASK                   (0x2000U)
#define FLEXCAN_CTRL2_BTE_SHIFT                  (13U)
#define FLEXCAN_CTRL2_BTE_WIDTH                  (1U)
#define FLEXCAN_CTRL2_BTE(x)                     (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_BTE_SHIFT)) & FLEXCAN_CTRL2_BTE_MASK)

#define FLEXCAN_CTRL2_PREXCEN_MASK               (0x4000U)
#define FLEXCAN_CTRL2_PREXCEN_SHIFT              (14U)
#define FLEXCAN_CTRL2_PREXCEN_WIDTH              (1U)
#define FLEXCAN_CTRL2_PREXCEN(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_PREXCEN_SHIFT)) & FLEXCAN_CTRL2_PREXCEN_MASK)

#define FLEXCAN_CTRL2_TIMER_SRC_MASK             (0x8000U)
#define FLEXCAN_CTRL2_TIMER_SRC_SHIFT            (15U)
#define FLEXCAN_CTRL2_TIMER_SRC_WIDTH            (1U)
#define FLEXCAN_CTRL2_TIMER_SRC(x)               (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_TIMER_SRC_SHIFT)) & FLEXCAN_CTRL2_TIMER_SRC_MASK)

#define FLEXCAN_CTRL2_EACEN_MASK                 (0x10000U)
#define FLEXCAN_CTRL2_EACEN_SHIFT                (16U)
#define FLEXCAN_CTRL2_EACEN_WIDTH                (1U)
#define FLEXCAN_CTRL2_EACEN(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_EACEN_SHIFT)) & FLEXCAN_CTRL2_EACEN_MASK)

#define FLEXCAN_CTRL2_RRS_MASK                   (0x20000U)
#define FLEXCAN_CTRL2_RRS_SHIFT                  (17U)
#define FLEXCAN_CTRL2_RRS_WIDTH                  (1U)
#define FLEXCAN_CTRL2_RRS(x)                     (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_RRS_SHIFT)) & FLEXCAN_CTRL2_RRS_MASK)

#define FLEXCAN_CTRL2_MRP_MASK                   (0x40000U)
#define FLEXCAN_CTRL2_MRP_SHIFT                  (18U)
#define FLEXCAN_CTRL2_MRP_WIDTH                  (1U)
#define FLEXCAN_CTRL2_MRP(x)                     (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_MRP_SHIFT)) & FLEXCAN_CTRL2_MRP_MASK)

#define FLEXCAN_CTRL2_TASD_MASK                  (0xF80000U)
#define FLEXCAN_CTRL2_TASD_SHIFT                 (19U)
#define FLEXCAN_CTRL2_TASD_WIDTH                 (5U)
#define FLEXCAN_CTRL2_TASD(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_TASD_SHIFT)) & FLEXCAN_CTRL2_TASD_MASK)

#define FLEXCAN_CTRL2_RFFN_MASK                  (0xF000000U)
#define FLEXCAN_CTRL2_RFFN_SHIFT                 (24U)
#define FLEXCAN_CTRL2_RFFN_WIDTH                 (4U)
#define FLEXCAN_CTRL2_RFFN(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_RFFN_SHIFT)) & FLEXCAN_CTRL2_RFFN_MASK)

#define FLEXCAN_CTRL2_WRMFRZ_MASK                (0x10000000U)
#define FLEXCAN_CTRL2_WRMFRZ_SHIFT               (28U)
#define FLEXCAN_CTRL2_WRMFRZ_WIDTH               (1U)
#define FLEXCAN_CTRL2_WRMFRZ(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_WRMFRZ_SHIFT)) & FLEXCAN_CTRL2_WRMFRZ_MASK)

#define FLEXCAN_CTRL2_ECRWRE_MASK                (0x20000000U)
#define FLEXCAN_CTRL2_ECRWRE_SHIFT               (29U)
#define FLEXCAN_CTRL2_ECRWRE_WIDTH               (1U)
#define FLEXCAN_CTRL2_ECRWRE(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_ECRWRE_SHIFT)) & FLEXCAN_CTRL2_ECRWRE_MASK)

#define FLEXCAN_CTRL2_BOFFDONEMSK_MASK           (0x40000000U)
#define FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT          (30U)
#define FLEXCAN_CTRL2_BOFFDONEMSK_WIDTH          (1U)
#define FLEXCAN_CTRL2_BOFFDONEMSK(x)             (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_BOFFDONEMSK_SHIFT)) & FLEXCAN_CTRL2_BOFFDONEMSK_MASK)

#define FLEXCAN_CTRL2_ERRMSK_FAST_MASK           (0x80000000U)
#define FLEXCAN_CTRL2_ERRMSK_FAST_SHIFT          (31U)
#define FLEXCAN_CTRL2_ERRMSK_FAST_WIDTH          (1U)
#define FLEXCAN_CTRL2_ERRMSK_FAST(x)             (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CTRL2_ERRMSK_FAST_SHIFT)) & FLEXCAN_CTRL2_ERRMSK_FAST_MASK)

#define FLEXCAN_ESR2_IMB_MASK                    (0x2000U)
#define FLEXCAN_ESR2_IMB_SHIFT                   (13U)
#define FLEXCAN_ESR2_IMB_WIDTH                   (1U)
#define FLEXCAN_ESR2_IMB(x)                      (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR2_IMB_SHIFT)) & FLEXCAN_ESR2_IMB_MASK)

#define FLEXCAN_ESR2_VPS_MASK                    (0x4000U)
#define FLEXCAN_ESR2_VPS_SHIFT                   (14U)
#define FLEXCAN_ESR2_VPS_WIDTH                   (1U)
#define FLEXCAN_ESR2_VPS(x)                      (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR2_VPS_SHIFT)) & FLEXCAN_ESR2_VPS_MASK)

#define FLEXCAN_ESR2_LPTM_MASK                   (0x7F0000U)
#define FLEXCAN_ESR2_LPTM_SHIFT                  (16U)
#define FLEXCAN_ESR2_LPTM_WIDTH                  (7U)
#define FLEXCAN_ESR2_LPTM(x)                     (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ESR2_LPTM_SHIFT)) & FLEXCAN_ESR2_LPTM_MASK)

#define FLEXCAN_CRCR_TXCRC_MASK                  (0x7FFFU)
#define FLEXCAN_CRCR_TXCRC_SHIFT                 (0U)
#define FLEXCAN_CRCR_TXCRC_WIDTH                 (15U)
#define FLEXCAN_CRCR_TXCRC(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CRCR_TXCRC_SHIFT)) & FLEXCAN_CRCR_TXCRC_MASK)

#define FLEXCAN_CRCR_MBCRC_MASK                  (0x7F0000U)
#define FLEXCAN_CRCR_MBCRC_SHIFT                 (16U)
#define FLEXCAN_CRCR_MBCRC_WIDTH                 (7U)
#define FLEXCAN_CRCR_MBCRC(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CRCR_MBCRC_SHIFT)) & FLEXCAN_CRCR_MBCRC_MASK)

#define FLEXCAN_RXFGMASK_FGM_MASK                (0xFFFFFFFFU)
#define FLEXCAN_RXFGMASK_FGM_SHIFT               (0U)
#define FLEXCAN_RXFGMASK_FGM_WIDTH               (32U)
#define FLEXCAN_RXFGMASK_FGM(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RXFGMASK_FGM_SHIFT)) & FLEXCAN_RXFGMASK_FGM_MASK)

#define FLEXCAN_RXFIR_IDHIT_MASK                 (0x1FFU)
#define FLEXCAN_RXFIR_IDHIT_SHIFT                (0U)
#define FLEXCAN_RXFIR_IDHIT_WIDTH                (9U)
#define FLEXCAN_RXFIR_IDHIT(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RXFIR_IDHIT_SHIFT)) & FLEXCAN_RXFIR_IDHIT_MASK)

#define FLEXCAN_CBT_EPSEG2_MASK                  (0x1FU)
#define FLEXCAN_CBT_EPSEG2_SHIFT                 (0U)
#define FLEXCAN_CBT_EPSEG2_WIDTH                 (5U)
#define FLEXCAN_CBT_EPSEG2(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CBT_EPSEG2_SHIFT)) & FLEXCAN_CBT_EPSEG2_MASK)

#define FLEXCAN_CBT_EPSEG1_MASK                  (0x3E0U)
#define FLEXCAN_CBT_EPSEG1_SHIFT                 (5U)
#define FLEXCAN_CBT_EPSEG1_WIDTH                 (5U)
#define FLEXCAN_CBT_EPSEG1(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CBT_EPSEG1_SHIFT)) & FLEXCAN_CBT_EPSEG1_MASK)

#define FLEXCAN_CBT_EPROPSEG_MASK                (0xFC00U)
#define FLEXCAN_CBT_EPROPSEG_SHIFT               (10U)
#define FLEXCAN_CBT_EPROPSEG_WIDTH               (6U)
#define FLEXCAN_CBT_EPROPSEG(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CBT_EPROPSEG_SHIFT)) & FLEXCAN_CBT_EPROPSEG_MASK)

#define FLEXCAN_CBT_ERJW_MASK                    (0x1F0000U)
#define FLEXCAN_CBT_ERJW_SHIFT                   (16U)
#define FLEXCAN_CBT_ERJW_WIDTH                   (5U)
#define FLEXCAN_CBT_ERJW(x)                      (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CBT_ERJW_SHIFT)) & FLEXCAN_CBT_ERJW_MASK)

#define FLEXCAN_CBT_EPRESDIV_MASK                (0x7FE00000U)
#define FLEXCAN_CBT_EPRESDIV_SHIFT               (21U)
#define FLEXCAN_CBT_EPRESDIV_WIDTH               (10U)
#define FLEXCAN_CBT_EPRESDIV(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CBT_EPRESDIV_SHIFT)) & FLEXCAN_CBT_EPRESDIV_MASK)

#define FLEXCAN_CBT_BTF_MASK                     (0x80000000U)
#define FLEXCAN_CBT_BTF_SHIFT                    (31U)
#define FLEXCAN_CBT_BTF_WIDTH                    (1U)
#define FLEXCAN_CBT_BTF(x)                       (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_CBT_BTF_SHIFT)) & FLEXCAN_CBT_BTF_MASK)

#define FLEXCAN_IMASK4_BUF127TO96M_MASK          (0xFFFFFFFFU)
#define FLEXCAN_IMASK4_BUF127TO96M_SHIFT         (0U)
#define FLEXCAN_IMASK4_BUF127TO96M_WIDTH         (32U)
#define FLEXCAN_IMASK4_BUF127TO96M(x)            (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_IMASK4_BUF127TO96M_SHIFT)) & FLEXCAN_IMASK4_BUF127TO96M_MASK)

#define FLEXCAN_IMASK3_BUF95TO64M_MASK           (0xFFFFFFFFU)
#define FLEXCAN_IMASK3_BUF95TO64M_SHIFT          (0U)
#define FLEXCAN_IMASK3_BUF95TO64M_WIDTH          (32U)
#define FLEXCAN_IMASK3_BUF95TO64M(x)             (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_IMASK3_BUF95TO64M_SHIFT)) & FLEXCAN_IMASK3_BUF95TO64M_MASK)

#define FLEXCAN_IFLAG4_BUF127TO96_MASK           (0xFFFFFFFFU)
#define FLEXCAN_IFLAG4_BUF127TO96_SHIFT          (0U)
#define FLEXCAN_IFLAG4_BUF127TO96_WIDTH          (32U)
#define FLEXCAN_IFLAG4_BUF127TO96(x)             (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_IFLAG4_BUF127TO96_SHIFT)) & FLEXCAN_IFLAG4_BUF127TO96_MASK)

#define FLEXCAN_IFLAG3_BUF95TO64_MASK            (0xFFFFFFFFU)
#define FLEXCAN_IFLAG3_BUF95TO64_SHIFT           (0U)
#define FLEXCAN_IFLAG3_BUF95TO64_WIDTH           (32U)
#define FLEXCAN_IFLAG3_BUF95TO64(x)              (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_IFLAG3_BUF95TO64_SHIFT)) & FLEXCAN_IFLAG3_BUF95TO64_MASK)

#define FLEXCAN_RXIMR_MI_MASK                    (0xFFFFFFFFU)
#define FLEXCAN_RXIMR_MI_SHIFT                   (0U)
#define FLEXCAN_RXIMR_MI_WIDTH                   (32U)
#define FLEXCAN_RXIMR_MI(x)                      (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RXIMR_MI_SHIFT)) & FLEXCAN_RXIMR_MI_MASK)

#define FLEXCAN_MECR_NCEFAFRZ_MASK               (0x80U)
#define FLEXCAN_MECR_NCEFAFRZ_SHIFT              (7U)
#define FLEXCAN_MECR_NCEFAFRZ_WIDTH              (1U)
#define FLEXCAN_MECR_NCEFAFRZ(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MECR_NCEFAFRZ_SHIFT)) & FLEXCAN_MECR_NCEFAFRZ_MASK)

#define FLEXCAN_MECR_ECCDIS_MASK                 (0x100U)
#define FLEXCAN_MECR_ECCDIS_SHIFT                (8U)
#define FLEXCAN_MECR_ECCDIS_WIDTH                (1U)
#define FLEXCAN_MECR_ECCDIS(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MECR_ECCDIS_SHIFT)) & FLEXCAN_MECR_ECCDIS_MASK)

#define FLEXCAN_MECR_RERRDIS_MASK                (0x200U)
#define FLEXCAN_MECR_RERRDIS_SHIFT               (9U)
#define FLEXCAN_MECR_RERRDIS_WIDTH               (1U)
#define FLEXCAN_MECR_RERRDIS(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MECR_RERRDIS_SHIFT)) & FLEXCAN_MECR_RERRDIS_MASK)

#define FLEXCAN_MECR_EXTERRIE_MASK               (0x2000U)
#define FLEXCAN_MECR_EXTERRIE_SHIFT              (13U)
#define FLEXCAN_MECR_EXTERRIE_WIDTH              (1U)
#define FLEXCAN_MECR_EXTERRIE(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MECR_EXTERRIE_SHIFT)) & FLEXCAN_MECR_EXTERRIE_MASK)

#define FLEXCAN_MECR_FAERRIE_MASK                (0x4000U)
#define FLEXCAN_MECR_FAERRIE_SHIFT               (14U)
#define FLEXCAN_MECR_FAERRIE_WIDTH               (1U)
#define FLEXCAN_MECR_FAERRIE(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MECR_FAERRIE_SHIFT)) & FLEXCAN_MECR_FAERRIE_MASK)

#define FLEXCAN_MECR_HAERRIE_MASK                (0x8000U)
#define FLEXCAN_MECR_HAERRIE_SHIFT               (15U)
#define FLEXCAN_MECR_HAERRIE_WIDTH               (1U)
#define FLEXCAN_MECR_HAERRIE(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MECR_HAERRIE_SHIFT)) & FLEXCAN_MECR_HAERRIE_MASK)

#define FLEXCAN_MECR_CEI_MASK                    (0x10000U)
#define FLEXCAN_MECR_CEI_SHIFT                   (16U)
#define FLEXCAN_MECR_CEI_WIDTH                   (1U)
#define FLEXCAN_MECR_CEI(x)                      (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MECR_CEI_SHIFT)) & FLEXCAN_MECR_CEI_MASK)

#define FLEXCAN_MECR_FANCEI_MASK                 (0x40000U)
#define FLEXCAN_MECR_FANCEI_SHIFT                (18U)
#define FLEXCAN_MECR_FANCEI_WIDTH                (1U)
#define FLEXCAN_MECR_FANCEI(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MECR_FANCEI_SHIFT)) & FLEXCAN_MECR_FANCEI_MASK)

#define FLEXCAN_MECR_HANCEI_MASK                 (0x80000U)
#define FLEXCAN_MECR_HANCEI_SHIFT                (19U)
#define FLEXCAN_MECR_HANCEI_WIDTH                (1U)
#define FLEXCAN_MECR_HANCEI(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MECR_HANCEI_SHIFT)) & FLEXCAN_MECR_HANCEI_MASK)

#define FLEXCAN_MECR_ECRWRDIS_MASK               (0x80000000U)
#define FLEXCAN_MECR_ECRWRDIS_SHIFT              (31U)
#define FLEXCAN_MECR_ECRWRDIS_WIDTH              (1U)
#define FLEXCAN_MECR_ECRWRDIS(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_MECR_ECRWRDIS_SHIFT)) & FLEXCAN_MECR_ECRWRDIS_MASK)

#define FLEXCAN_ERRIAR_INJADDR_L_MASK            (0x3U)
#define FLEXCAN_ERRIAR_INJADDR_L_SHIFT           (0U)
#define FLEXCAN_ERRIAR_INJADDR_L_WIDTH           (2U)
#define FLEXCAN_ERRIAR_INJADDR_L(x)              (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERRIAR_INJADDR_L_SHIFT)) & FLEXCAN_ERRIAR_INJADDR_L_MASK)

#define FLEXCAN_ERRIAR_INJADDR_H_MASK            (0x3FFCU)
#define FLEXCAN_ERRIAR_INJADDR_H_SHIFT           (2U)
#define FLEXCAN_ERRIAR_INJADDR_H_WIDTH           (12U)
#define FLEXCAN_ERRIAR_INJADDR_H(x)              (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERRIAR_INJADDR_H_SHIFT)) & FLEXCAN_ERRIAR_INJADDR_H_MASK)

#define FLEXCAN_ERRIDPR_DFLIP_MASK               (0xFFFFFFFFU)
#define FLEXCAN_ERRIDPR_DFLIP_SHIFT              (0U)
#define FLEXCAN_ERRIDPR_DFLIP_WIDTH              (32U)
#define FLEXCAN_ERRIDPR_DFLIP(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERRIDPR_DFLIP_SHIFT)) & FLEXCAN_ERRIDPR_DFLIP_MASK)

#define FLEXCAN_ERRIPPR_PFLIP0_MASK              (0x1FU)
#define FLEXCAN_ERRIPPR_PFLIP0_SHIFT             (0U)
#define FLEXCAN_ERRIPPR_PFLIP0_WIDTH             (5U)
#define FLEXCAN_ERRIPPR_PFLIP0(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERRIPPR_PFLIP0_SHIFT)) & FLEXCAN_ERRIPPR_PFLIP0_MASK)

#define FLEXCAN_ERRIPPR_PFLIP1_MASK              (0x1F00U)
#define FLEXCAN_ERRIPPR_PFLIP1_SHIFT             (8U)
#define FLEXCAN_ERRIPPR_PFLIP1_WIDTH             (5U)
#define FLEXCAN_ERRIPPR_PFLIP1(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERRIPPR_PFLIP1_SHIFT)) & FLEXCAN_ERRIPPR_PFLIP1_MASK)

#define FLEXCAN_ERRIPPR_PFLIP2_MASK              (0x1F0000U)
#define FLEXCAN_ERRIPPR_PFLIP2_SHIFT             (16U)
#define FLEXCAN_ERRIPPR_PFLIP2_WIDTH             (5U)
#define FLEXCAN_ERRIPPR_PFLIP2(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERRIPPR_PFLIP2_SHIFT)) & FLEXCAN_ERRIPPR_PFLIP2_MASK)

#define FLEXCAN_ERRIPPR_PFLIP3_MASK              (0x1F000000U)
#define FLEXCAN_ERRIPPR_PFLIP3_SHIFT             (24U)
#define FLEXCAN_ERRIPPR_PFLIP3_WIDTH             (5U)
#define FLEXCAN_ERRIPPR_PFLIP3(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERRIPPR_PFLIP3_SHIFT)) & FLEXCAN_ERRIPPR_PFLIP3_MASK)

#define FLEXCAN_RERRAR_ERRADDR_MASK              (0x3FFFU)
#define FLEXCAN_RERRAR_ERRADDR_SHIFT             (0U)
#define FLEXCAN_RERRAR_ERRADDR_WIDTH             (14U)
#define FLEXCAN_RERRAR_ERRADDR(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RERRAR_ERRADDR_SHIFT)) & FLEXCAN_RERRAR_ERRADDR_MASK)

#define FLEXCAN_RERRAR_SAID_MASK                 (0x70000U)
#define FLEXCAN_RERRAR_SAID_SHIFT                (16U)
#define FLEXCAN_RERRAR_SAID_WIDTH                (3U)
#define FLEXCAN_RERRAR_SAID(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RERRAR_SAID_SHIFT)) & FLEXCAN_RERRAR_SAID_MASK)

#define FLEXCAN_RERRAR_NCE_MASK                  (0x1000000U)
#define FLEXCAN_RERRAR_NCE_SHIFT                 (24U)
#define FLEXCAN_RERRAR_NCE_WIDTH                 (1U)
#define FLEXCAN_RERRAR_NCE(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RERRAR_NCE_SHIFT)) & FLEXCAN_RERRAR_NCE_MASK)

#define FLEXCAN_RERRDR_RDATA_MASK                (0xFFFFFFFFU)
#define FLEXCAN_RERRDR_RDATA_SHIFT               (0U)
#define FLEXCAN_RERRDR_RDATA_WIDTH               (32U)
#define FLEXCAN_RERRDR_RDATA(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RERRDR_RDATA_SHIFT)) & FLEXCAN_RERRDR_RDATA_MASK)

#define FLEXCAN_RERRSYNR_SYND0_MASK              (0x1FU)
#define FLEXCAN_RERRSYNR_SYND0_SHIFT             (0U)
#define FLEXCAN_RERRSYNR_SYND0_WIDTH             (5U)
#define FLEXCAN_RERRSYNR_SYND0(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RERRSYNR_SYND0_SHIFT)) & FLEXCAN_RERRSYNR_SYND0_MASK)

#define FLEXCAN_RERRSYNR_BE0_MASK                (0x80U)
#define FLEXCAN_RERRSYNR_BE0_SHIFT               (7U)
#define FLEXCAN_RERRSYNR_BE0_WIDTH               (1U)
#define FLEXCAN_RERRSYNR_BE0(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RERRSYNR_BE0_SHIFT)) & FLEXCAN_RERRSYNR_BE0_MASK)

#define FLEXCAN_RERRSYNR_SYND1_MASK              (0x1F00U)
#define FLEXCAN_RERRSYNR_SYND1_SHIFT             (8U)
#define FLEXCAN_RERRSYNR_SYND1_WIDTH             (5U)
#define FLEXCAN_RERRSYNR_SYND1(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RERRSYNR_SYND1_SHIFT)) & FLEXCAN_RERRSYNR_SYND1_MASK)

#define FLEXCAN_RERRSYNR_BE1_MASK                (0x8000U)
#define FLEXCAN_RERRSYNR_BE1_SHIFT               (15U)
#define FLEXCAN_RERRSYNR_BE1_WIDTH               (1U)
#define FLEXCAN_RERRSYNR_BE1(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RERRSYNR_BE1_SHIFT)) & FLEXCAN_RERRSYNR_BE1_MASK)

#define FLEXCAN_RERRSYNR_SYND2_MASK              (0x1F0000U)
#define FLEXCAN_RERRSYNR_SYND2_SHIFT             (16U)
#define FLEXCAN_RERRSYNR_SYND2_WIDTH             (5U)
#define FLEXCAN_RERRSYNR_SYND2(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RERRSYNR_SYND2_SHIFT)) & FLEXCAN_RERRSYNR_SYND2_MASK)

#define FLEXCAN_RERRSYNR_BE2_MASK                (0x800000U)
#define FLEXCAN_RERRSYNR_BE2_SHIFT               (23U)
#define FLEXCAN_RERRSYNR_BE2_WIDTH               (1U)
#define FLEXCAN_RERRSYNR_BE2(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RERRSYNR_BE2_SHIFT)) & FLEXCAN_RERRSYNR_BE2_MASK)

#define FLEXCAN_RERRSYNR_SYND3_MASK              (0x1F000000U)
#define FLEXCAN_RERRSYNR_SYND3_SHIFT             (24U)
#define FLEXCAN_RERRSYNR_SYND3_WIDTH             (5U)
#define FLEXCAN_RERRSYNR_SYND3(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RERRSYNR_SYND3_SHIFT)) & FLEXCAN_RERRSYNR_SYND3_MASK)

#define FLEXCAN_RERRSYNR_BE3_MASK                (0x80000000U)
#define FLEXCAN_RERRSYNR_BE3_SHIFT               (31U)
#define FLEXCAN_RERRSYNR_BE3_WIDTH               (1U)
#define FLEXCAN_RERRSYNR_BE3(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_RERRSYNR_BE3_SHIFT)) & FLEXCAN_RERRSYNR_BE3_MASK)

#define FLEXCAN_ERRSR_CEIOF_MASK                 (0x1U)
#define FLEXCAN_ERRSR_CEIOF_SHIFT                (0U)
#define FLEXCAN_ERRSR_CEIOF_WIDTH                (1U)
#define FLEXCAN_ERRSR_CEIOF(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERRSR_CEIOF_SHIFT)) & FLEXCAN_ERRSR_CEIOF_MASK)

#define FLEXCAN_ERRSR_FANCEIOF_MASK              (0x4U)
#define FLEXCAN_ERRSR_FANCEIOF_SHIFT             (2U)
#define FLEXCAN_ERRSR_FANCEIOF_WIDTH             (1U)
#define FLEXCAN_ERRSR_FANCEIOF(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERRSR_FANCEIOF_SHIFT)) & FLEXCAN_ERRSR_FANCEIOF_MASK)

#define FLEXCAN_ERRSR_HANCEIOF_MASK              (0x8U)
#define FLEXCAN_ERRSR_HANCEIOF_SHIFT             (3U)
#define FLEXCAN_ERRSR_HANCEIOF_WIDTH             (1U)
#define FLEXCAN_ERRSR_HANCEIOF(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERRSR_HANCEIOF_SHIFT)) & FLEXCAN_ERRSR_HANCEIOF_MASK)

#define FLEXCAN_ERRSR_CEIF_MASK                  (0x10000U)
#define FLEXCAN_ERRSR_CEIF_SHIFT                 (16U)
#define FLEXCAN_ERRSR_CEIF_WIDTH                 (1U)
#define FLEXCAN_ERRSR_CEIF(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERRSR_CEIF_SHIFT)) & FLEXCAN_ERRSR_CEIF_MASK)

#define FLEXCAN_ERRSR_FANCEIF_MASK               (0x40000U)
#define FLEXCAN_ERRSR_FANCEIF_SHIFT              (18U)
#define FLEXCAN_ERRSR_FANCEIF_WIDTH              (1U)
#define FLEXCAN_ERRSR_FANCEIF(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERRSR_FANCEIF_SHIFT)) & FLEXCAN_ERRSR_FANCEIF_MASK)

#define FLEXCAN_ERRSR_HANCEIF_MASK               (0x80000U)
#define FLEXCAN_ERRSR_HANCEIF_SHIFT              (19U)
#define FLEXCAN_ERRSR_HANCEIF_WIDTH              (1U)
#define FLEXCAN_ERRSR_HANCEIF(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERRSR_HANCEIF_SHIFT)) & FLEXCAN_ERRSR_HANCEIF_MASK)

#define FLEXCAN_EPRS_ENPRESDIV_MASK              (0x3FFU)
#define FLEXCAN_EPRS_ENPRESDIV_SHIFT             (0U)
#define FLEXCAN_EPRS_ENPRESDIV_WIDTH             (10U)
#define FLEXCAN_EPRS_ENPRESDIV(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_EPRS_ENPRESDIV_SHIFT)) & FLEXCAN_EPRS_ENPRESDIV_MASK)

#define FLEXCAN_EPRS_EDPRESDIV_MASK              (0x3FF0000U)
#define FLEXCAN_EPRS_EDPRESDIV_SHIFT             (16U)
#define FLEXCAN_EPRS_EDPRESDIV_WIDTH             (10U)
#define FLEXCAN_EPRS_EDPRESDIV(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_EPRS_EDPRESDIV_SHIFT)) & FLEXCAN_EPRS_EDPRESDIV_MASK)

#define FLEXCAN_ENCBT_NTSEG1_MASK                (0xFFU)
#define FLEXCAN_ENCBT_NTSEG1_SHIFT               (0U)
#define FLEXCAN_ENCBT_NTSEG1_WIDTH               (8U)
#define FLEXCAN_ENCBT_NTSEG1(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ENCBT_NTSEG1_SHIFT)) & FLEXCAN_ENCBT_NTSEG1_MASK)

#define FLEXCAN_ENCBT_NTSEG2_MASK                (0x7F000U)
#define FLEXCAN_ENCBT_NTSEG2_SHIFT               (12U)
#define FLEXCAN_ENCBT_NTSEG2_WIDTH               (7U)
#define FLEXCAN_ENCBT_NTSEG2(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ENCBT_NTSEG2_SHIFT)) & FLEXCAN_ENCBT_NTSEG2_MASK)

#define FLEXCAN_ENCBT_NRJW_MASK                  (0x1FC00000U)
#define FLEXCAN_ENCBT_NRJW_SHIFT                 (22U)
#define FLEXCAN_ENCBT_NRJW_WIDTH                 (7U)
#define FLEXCAN_ENCBT_NRJW(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ENCBT_NRJW_SHIFT)) & FLEXCAN_ENCBT_NRJW_MASK)

#define FLEXCAN_EDCBT_DTSEG1_MASK                (0x1FU)
#define FLEXCAN_EDCBT_DTSEG1_SHIFT               (0U)
#define FLEXCAN_EDCBT_DTSEG1_WIDTH               (5U)
#define FLEXCAN_EDCBT_DTSEG1(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_EDCBT_DTSEG1_SHIFT)) & FLEXCAN_EDCBT_DTSEG1_MASK)

#define FLEXCAN_EDCBT_DTSEG2_MASK                (0xF000U)
#define FLEXCAN_EDCBT_DTSEG2_SHIFT               (12U)
#define FLEXCAN_EDCBT_DTSEG2_WIDTH               (4U)
#define FLEXCAN_EDCBT_DTSEG2(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_EDCBT_DTSEG2_SHIFT)) & FLEXCAN_EDCBT_DTSEG2_MASK)

#define FLEXCAN_EDCBT_DRJW_MASK                  (0x3C00000U)
#define FLEXCAN_EDCBT_DRJW_SHIFT                 (22U)
#define FLEXCAN_EDCBT_DRJW_WIDTH                 (4U)
#define FLEXCAN_EDCBT_DRJW(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_EDCBT_DRJW_SHIFT)) & FLEXCAN_EDCBT_DRJW_MASK)

#define FLEXCAN_ETDC_ETDCVAL_MASK                (0xFFU)
#define FLEXCAN_ETDC_ETDCVAL_SHIFT               (0U)
#define FLEXCAN_ETDC_ETDCVAL_WIDTH               (8U)
#define FLEXCAN_ETDC_ETDCVAL(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ETDC_ETDCVAL_SHIFT)) & FLEXCAN_ETDC_ETDCVAL_MASK)

#define FLEXCAN_ETDC_ETDCFAIL_MASK               (0x8000U)
#define FLEXCAN_ETDC_ETDCFAIL_SHIFT              (15U)
#define FLEXCAN_ETDC_ETDCFAIL_WIDTH              (1U)
#define FLEXCAN_ETDC_ETDCFAIL(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ETDC_ETDCFAIL_SHIFT)) & FLEXCAN_ETDC_ETDCFAIL_MASK)

#define FLEXCAN_ETDC_ETDCOFF_MASK                (0x7F0000U)
#define FLEXCAN_ETDC_ETDCOFF_SHIFT               (16U)
#define FLEXCAN_ETDC_ETDCOFF_WIDTH               (7U)
#define FLEXCAN_ETDC_ETDCOFF(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ETDC_ETDCOFF_SHIFT)) & FLEXCAN_ETDC_ETDCOFF_MASK)

#define FLEXCAN_ETDC_TDMDIS_MASK                 (0x40000000U)
#define FLEXCAN_ETDC_TDMDIS_SHIFT                (30U)
#define FLEXCAN_ETDC_TDMDIS_WIDTH                (1U)
#define FLEXCAN_ETDC_TDMDIS(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ETDC_TDMDIS_SHIFT)) & FLEXCAN_ETDC_TDMDIS_MASK)

#define FLEXCAN_ETDC_ETDCEN_MASK                 (0x80000000U)
#define FLEXCAN_ETDC_ETDCEN_SHIFT                (31U)
#define FLEXCAN_ETDC_ETDCEN_WIDTH                (1U)
#define FLEXCAN_ETDC_ETDCEN(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ETDC_ETDCEN_SHIFT)) & FLEXCAN_ETDC_ETDCEN_MASK)

#define FLEXCAN_FDCTRL_TDCVAL_MASK               (0x3FU)
#define FLEXCAN_FDCTRL_TDCVAL_SHIFT              (0U)
#define FLEXCAN_FDCTRL_TDCVAL_WIDTH              (6U)
#define FLEXCAN_FDCTRL_TDCVAL(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCTRL_TDCVAL_SHIFT)) & FLEXCAN_FDCTRL_TDCVAL_MASK)

#define FLEXCAN_FDCTRL_TDCOFF_MASK               (0x1F00U)
#define FLEXCAN_FDCTRL_TDCOFF_SHIFT              (8U)
#define FLEXCAN_FDCTRL_TDCOFF_WIDTH              (5U)
#define FLEXCAN_FDCTRL_TDCOFF(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCTRL_TDCOFF_SHIFT)) & FLEXCAN_FDCTRL_TDCOFF_MASK)

#define FLEXCAN_FDCTRL_TDCFAIL_MASK              (0x4000U)
#define FLEXCAN_FDCTRL_TDCFAIL_SHIFT             (14U)
#define FLEXCAN_FDCTRL_TDCFAIL_WIDTH             (1U)
#define FLEXCAN_FDCTRL_TDCFAIL(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCTRL_TDCFAIL_SHIFT)) & FLEXCAN_FDCTRL_TDCFAIL_MASK)

#define FLEXCAN_FDCTRL_TDCEN_MASK                (0x8000U)
#define FLEXCAN_FDCTRL_TDCEN_SHIFT               (15U)
#define FLEXCAN_FDCTRL_TDCEN_WIDTH               (1U)
#define FLEXCAN_FDCTRL_TDCEN(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCTRL_TDCEN_SHIFT)) & FLEXCAN_FDCTRL_TDCEN_MASK)

#define FLEXCAN_FDCTRL_MBDSR0_MASK               (0x30000U)
#define FLEXCAN_FDCTRL_MBDSR0_SHIFT              (16U)
#define FLEXCAN_FDCTRL_MBDSR0_WIDTH              (2U)
#define FLEXCAN_FDCTRL_MBDSR0(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCTRL_MBDSR0_SHIFT)) & FLEXCAN_FDCTRL_MBDSR0_MASK)

#define FLEXCAN_FDCTRL_MBDSR1_MASK               (0x180000U)
#define FLEXCAN_FDCTRL_MBDSR1_SHIFT              (19U)
#define FLEXCAN_FDCTRL_MBDSR1_WIDTH              (2U)
#define FLEXCAN_FDCTRL_MBDSR1(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCTRL_MBDSR1_SHIFT)) & FLEXCAN_FDCTRL_MBDSR1_MASK)

#define FLEXCAN_FDCTRL_MBDSR2_MASK               (0xC00000U)
#define FLEXCAN_FDCTRL_MBDSR2_SHIFT              (22U)
#define FLEXCAN_FDCTRL_MBDSR2_WIDTH              (2U)
#define FLEXCAN_FDCTRL_MBDSR2(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCTRL_MBDSR2_SHIFT)) & FLEXCAN_FDCTRL_MBDSR2_MASK)

#define FLEXCAN_FDCTRL_MBDSR3_MASK               (0x6000000U)
#define FLEXCAN_FDCTRL_MBDSR3_SHIFT              (25U)
#define FLEXCAN_FDCTRL_MBDSR3_WIDTH              (2U)
#define FLEXCAN_FDCTRL_MBDSR3(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCTRL_MBDSR3_SHIFT)) & FLEXCAN_FDCTRL_MBDSR3_MASK)

#define FLEXCAN_FDCTRL_FDRATE_MASK               (0x80000000U)
#define FLEXCAN_FDCTRL_FDRATE_SHIFT              (31U)
#define FLEXCAN_FDCTRL_FDRATE_WIDTH              (1U)
#define FLEXCAN_FDCTRL_FDRATE(x)                 (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCTRL_FDRATE_SHIFT)) & FLEXCAN_FDCTRL_FDRATE_MASK)

#define FLEXCAN_FDCBT_FPSEG2_MASK                (0x7U)
#define FLEXCAN_FDCBT_FPSEG2_SHIFT               (0U)
#define FLEXCAN_FDCBT_FPSEG2_WIDTH               (3U)
#define FLEXCAN_FDCBT_FPSEG2(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCBT_FPSEG2_SHIFT)) & FLEXCAN_FDCBT_FPSEG2_MASK)

#define FLEXCAN_FDCBT_FPSEG1_MASK                (0xE0U)
#define FLEXCAN_FDCBT_FPSEG1_SHIFT               (5U)
#define FLEXCAN_FDCBT_FPSEG1_WIDTH               (3U)
#define FLEXCAN_FDCBT_FPSEG1(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCBT_FPSEG1_SHIFT)) & FLEXCAN_FDCBT_FPSEG1_MASK)

#define FLEXCAN_FDCBT_FPROPSEG_MASK              (0x7C00U)
#define FLEXCAN_FDCBT_FPROPSEG_SHIFT             (10U)
#define FLEXCAN_FDCBT_FPROPSEG_WIDTH             (5U)
#define FLEXCAN_FDCBT_FPROPSEG(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCBT_FPROPSEG_SHIFT)) & FLEXCAN_FDCBT_FPROPSEG_MASK)

#define FLEXCAN_FDCBT_FRJW_MASK                  (0x70000U)
#define FLEXCAN_FDCBT_FRJW_SHIFT                 (16U)
#define FLEXCAN_FDCBT_FRJW_WIDTH                 (3U)
#define FLEXCAN_FDCBT_FRJW(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCBT_FRJW_SHIFT)) & FLEXCAN_FDCBT_FRJW_MASK)

#define FLEXCAN_FDCBT_FPRESDIV_MASK              (0x3FF00000U)
#define FLEXCAN_FDCBT_FPRESDIV_SHIFT             (20U)
#define FLEXCAN_FDCBT_FPRESDIV_WIDTH             (10U)
#define FLEXCAN_FDCBT_FPRESDIV(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCBT_FPRESDIV_SHIFT)) & FLEXCAN_FDCBT_FPRESDIV_MASK)

#define FLEXCAN_FDCRC_FD_TXCRC_MASK              (0x1FFFFFU)
#define FLEXCAN_FDCRC_FD_TXCRC_SHIFT             (0U)
#define FLEXCAN_FDCRC_FD_TXCRC_WIDTH             (21U)
#define FLEXCAN_FDCRC_FD_TXCRC(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCRC_FD_TXCRC_SHIFT)) & FLEXCAN_FDCRC_FD_TXCRC_MASK)

#define FLEXCAN_FDCRC_FD_MBCRC_MASK              (0x7F000000U)
#define FLEXCAN_FDCRC_FD_MBCRC_SHIFT             (24U)
#define FLEXCAN_FDCRC_FD_MBCRC_WIDTH             (7U)
#define FLEXCAN_FDCRC_FD_MBCRC(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_FDCRC_FD_MBCRC_SHIFT)) & FLEXCAN_FDCRC_FD_MBCRC_MASK)

#define FLEXCAN_ERFCR_ERFWM_MASK                 (0x1FU)
#define FLEXCAN_ERFCR_ERFWM_SHIFT                (0U)
#define FLEXCAN_ERFCR_ERFWM_WIDTH                (5U)
#define FLEXCAN_ERFCR_ERFWM(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFCR_ERFWM_SHIFT)) & FLEXCAN_ERFCR_ERFWM_MASK)

#define FLEXCAN_ERFCR_NFE_MASK                   (0x3F00U)
#define FLEXCAN_ERFCR_NFE_SHIFT                  (8U)
#define FLEXCAN_ERFCR_NFE_WIDTH                  (6U)
#define FLEXCAN_ERFCR_NFE(x)                     (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFCR_NFE_SHIFT)) & FLEXCAN_ERFCR_NFE_MASK)

#define FLEXCAN_ERFCR_NEXIF_MASK                 (0x7F0000U)
#define FLEXCAN_ERFCR_NEXIF_SHIFT                (16U)
#define FLEXCAN_ERFCR_NEXIF_WIDTH                (7U)
#define FLEXCAN_ERFCR_NEXIF(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFCR_NEXIF_SHIFT)) & FLEXCAN_ERFCR_NEXIF_MASK)

#define FLEXCAN_ERFCR_DMALW_MASK                 (0x7C000000U)
#define FLEXCAN_ERFCR_DMALW_SHIFT                (26U)
#define FLEXCAN_ERFCR_DMALW_WIDTH                (5U)
#define FLEXCAN_ERFCR_DMALW(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFCR_DMALW_SHIFT)) & FLEXCAN_ERFCR_DMALW_MASK)

#define FLEXCAN_ERFCR_ERFEN_MASK                 (0x80000000U)
#define FLEXCAN_ERFCR_ERFEN_SHIFT                (31U)
#define FLEXCAN_ERFCR_ERFEN_WIDTH                (1U)
#define FLEXCAN_ERFCR_ERFEN(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFCR_ERFEN_SHIFT)) & FLEXCAN_ERFCR_ERFEN_MASK)

#define FLEXCAN_ERFIER_ERFDAIE_MASK              (0x10000000U)
#define FLEXCAN_ERFIER_ERFDAIE_SHIFT             (28U)
#define FLEXCAN_ERFIER_ERFDAIE_WIDTH             (1U)
#define FLEXCAN_ERFIER_ERFDAIE(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFIER_ERFDAIE_SHIFT)) & FLEXCAN_ERFIER_ERFDAIE_MASK)

#define FLEXCAN_ERFIER_ERFWMIIE_MASK             (0x20000000U)
#define FLEXCAN_ERFIER_ERFWMIIE_SHIFT            (29U)
#define FLEXCAN_ERFIER_ERFWMIIE_WIDTH            (1U)
#define FLEXCAN_ERFIER_ERFWMIIE(x)               (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFIER_ERFWMIIE_SHIFT)) & FLEXCAN_ERFIER_ERFWMIIE_MASK)

#define FLEXCAN_ERFIER_ERFOVFIE_MASK             (0x40000000U)
#define FLEXCAN_ERFIER_ERFOVFIE_SHIFT            (30U)
#define FLEXCAN_ERFIER_ERFOVFIE_WIDTH            (1U)
#define FLEXCAN_ERFIER_ERFOVFIE(x)               (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFIER_ERFOVFIE_SHIFT)) & FLEXCAN_ERFIER_ERFOVFIE_MASK)

#define FLEXCAN_ERFIER_ERFUFWIE_MASK             (0x80000000U)
#define FLEXCAN_ERFIER_ERFUFWIE_SHIFT            (31U)
#define FLEXCAN_ERFIER_ERFUFWIE_WIDTH            (1U)
#define FLEXCAN_ERFIER_ERFUFWIE(x)               (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFIER_ERFUFWIE_SHIFT)) & FLEXCAN_ERFIER_ERFUFWIE_MASK)

#define FLEXCAN_ERFSR_ERFEL_MASK                 (0x3FU)
#define FLEXCAN_ERFSR_ERFEL_SHIFT                (0U)
#define FLEXCAN_ERFSR_ERFEL_WIDTH                (6U)
#define FLEXCAN_ERFSR_ERFEL(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFSR_ERFEL_SHIFT)) & FLEXCAN_ERFSR_ERFEL_MASK)

#define FLEXCAN_ERFSR_ERFF_MASK                  (0x10000U)
#define FLEXCAN_ERFSR_ERFF_SHIFT                 (16U)
#define FLEXCAN_ERFSR_ERFF_WIDTH                 (1U)
#define FLEXCAN_ERFSR_ERFF(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFSR_ERFF_SHIFT)) & FLEXCAN_ERFSR_ERFF_MASK)

#define FLEXCAN_ERFSR_ERFE_MASK                  (0x20000U)
#define FLEXCAN_ERFSR_ERFE_SHIFT                 (17U)
#define FLEXCAN_ERFSR_ERFE_WIDTH                 (1U)
#define FLEXCAN_ERFSR_ERFE(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFSR_ERFE_SHIFT)) & FLEXCAN_ERFSR_ERFE_MASK)

#define FLEXCAN_ERFSR_ERFCLR_MASK                (0x8000000U)
#define FLEXCAN_ERFSR_ERFCLR_SHIFT               (27U)
#define FLEXCAN_ERFSR_ERFCLR_WIDTH               (1U)
#define FLEXCAN_ERFSR_ERFCLR(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFSR_ERFCLR_SHIFT)) & FLEXCAN_ERFSR_ERFCLR_MASK)

#define FLEXCAN_ERFSR_ERFDA_MASK                 (0x10000000U)
#define FLEXCAN_ERFSR_ERFDA_SHIFT                (28U)
#define FLEXCAN_ERFSR_ERFDA_WIDTH                (1U)
#define FLEXCAN_ERFSR_ERFDA(x)                   (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFSR_ERFDA_SHIFT)) & FLEXCAN_ERFSR_ERFDA_MASK)

#define FLEXCAN_ERFSR_ERFWMI_MASK                (0x20000000U)
#define FLEXCAN_ERFSR_ERFWMI_SHIFT               (29U)
#define FLEXCAN_ERFSR_ERFWMI_WIDTH               (1U)
#define FLEXCAN_ERFSR_ERFWMI(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFSR_ERFWMI_SHIFT)) & FLEXCAN_ERFSR_ERFWMI_MASK)

#define FLEXCAN_ERFSR_ERFOVF_MASK                (0x40000000U)
#define FLEXCAN_ERFSR_ERFOVF_SHIFT               (30U)
#define FLEXCAN_ERFSR_ERFOVF_WIDTH               (1U)
#define FLEXCAN_ERFSR_ERFOVF(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFSR_ERFOVF_SHIFT)) & FLEXCAN_ERFSR_ERFOVF_MASK)

#define FLEXCAN_ERFSR_ERFUFW_MASK                (0x80000000U)
#define FLEXCAN_ERFSR_ERFUFW_SHIFT               (31U)
#define FLEXCAN_ERFSR_ERFUFW_WIDTH               (1U)
#define FLEXCAN_ERFSR_ERFUFW(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFSR_ERFUFW_SHIFT)) & FLEXCAN_ERFSR_ERFUFW_MASK)

#define FLEXCAN_HR_TIME_STAMP_TS_MASK            (0xFFFFFFFFU)
#define FLEXCAN_HR_TIME_STAMP_TS_SHIFT           (0U)
#define FLEXCAN_HR_TIME_STAMP_TS_WIDTH           (32U)
#define FLEXCAN_HR_TIME_STAMP_TS(x)              (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_HR_TIME_STAMP_TS_SHIFT)) & FLEXCAN_HR_TIME_STAMP_TS_MASK)

#define FLEXCAN_ERFFEL_FEL_MASK                  (0xFFFFFFFFU)
#define FLEXCAN_ERFFEL_FEL_SHIFT                 (0U)
#define FLEXCAN_ERFFEL_FEL_WIDTH                 (32U)
#define FLEXCAN_ERFFEL_FEL(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_ERFFEL_FEL_SHIFT)) & FLEXCAN_ERFFEL_FEL_MASK)

#define FLEXCAN_TSCTRL_REFRESH_MASK              (0x8U)
#define FLEXCAN_TSCTRL_REFRESH_SHIFT             (3U)
#define FLEXCAN_TSCTRL_REFRESH_WIDTH             (1U)
#define FLEXCAN_TSCTRL_REFRESH(x)                (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_TSCTRL_REFRESH_SHIFT)) & FLEXCAN_TSCTRL_REFRESH_MASK)

#define FLEXCAN_TSCTRL_SRC_MASK                  (0x10U)
#define FLEXCAN_TSCTRL_SRC_SHIFT                 (4U)
#define FLEXCAN_TSCTRL_SRC_WIDTH                 (1U)
#define FLEXCAN_TSCTRL_SRC(x)                    (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_TSCTRL_SRC_SHIFT)) & FLEXCAN_TSCTRL_SRC_MASK)

#define FLEXCAN_TSCTRL_PSLVE_MASK                (0x20U)
#define FLEXCAN_TSCTRL_PSLVE_SHIFT               (5U)
#define FLEXCAN_TSCTRL_PSLVE_WIDTH               (1U)
#define FLEXCAN_TSCTRL_PSLVE(x)                  (((rt_uint32_t)(((rt_uint32_t)(x)) << FLEXCAN_TSCTRL_PSLVE_SHIFT)) & FLEXCAN_TSCTRL_PSLVE_MASK)


/* Default value for register */
/**
* @brief Default value for the MCR register
*/
#define FLEXCAN_IP_MCR_DEFAULT_VALUE_U32               ((rt_uint32_t)0xD890000FU)

/**
* @brief Default value for the CTRL1 register
*/
#define FLEXCAN_IP_CTRL1_DEFAULT_VALUE_U32             ((rt_uint32_t)0x00000000U)

/**
* @brief Default value for the TIMER register
*/
#define FLEXCAN_IP_TIMER_DEFAULT_VALUE_U32             ((rt_uint32_t)0x00000000U)

/**
* @brief Default value for the ECR register
*/
#define FLEXCAN_IP_ECR_DEFAULT_VALUE_U32               ((rt_uint32_t)0x00000000U)

/**
* @brief Default value for the ESR1 register
*/
#define FLEXCAN_IP_ESR1_DEFAULT_VALUE_U32              ((rt_uint32_t)0x003B0006U)

/**
* @brief Default value for the IMASKx register
*/
#define FLEXCAN_IP_IMASK_DEFAULT_VALUE_U32             ((rt_uint32_t)0x00000000U)

/**
* @brief Default value for the IFLAG4 register
*/
#define FLEXCAN_IP_IFLAG_DEFAULT_VALUE_U32             ((rt_uint32_t)0xFFFFFFFFU)

/**
* @brief Default value for the CTRL2 register
*/
#define FLEXCAN_IP_CTRL2_DEFAULT_VALUE_U32             ((rt_uint32_t)0x00100000U)

/**
* @brief Default value for the CTRL2 register
*/
#define FLEXCAN_IP_CBT_DEFAULT_VALUE_U32               ((rt_uint32_t)0x00000000U)

/**
* @brief Default value for the MECR register
*/
#define FLEXCAN_IP_MECR_DEFAULT_VALUE_U32              ((rt_uint32_t)0x000C0080U)

/**
* @brief Default value for the ERRIAR register
*/
#define FLEXCAN_IP_ERRIAR_DEFAULT_VALUE_U32            ((rt_uint32_t)0x00000000U)

/**
* @brief Default value for the ERRIDPR register
*/
#define FLEXCAN_IP_ERRIDPR_DEFAULT_VALUE_U32           ((rt_uint32_t)0x00000000U)

/**
* @brief Default value for the ERRIPPR register
*/
#define FLEXCAN_IP_ERRIPPR_DEFAULT_VALUE_U32           ((rt_uint32_t)0x00000000U)

/**
* @brief Default value for the ERRSR register
*/
#define FLEXCAN_IP_ERRSR_DEFAULT_VALUE_U32             ((rt_uint32_t)0x000D000DU)

/**
* @brief Default value for the FDCTRL register
*/
#define FLEXCAN_IP_FDCTRL_DEFAULT_VALUE_U32            ((rt_uint32_t)0x80004100U)

/**
* @brief Default value for the FDCBT register
*/
#define FLEXCAN_IP_FDCBT_DEFAULT_VALUE_U32             ((rt_uint32_t)0x00000000U)

/**
* @brief Default value for the ERFCR register
*/
#define FLEXCAN_IP_ERFCR_DEFAULT_VALUE_U32            ((rt_uint32_t)0x00000000U)

/**
* @brief Default value for the ERFIER register
*/
#define FLEXCAN_IP_ERFIER_DEFAULT_VALUE_U32            ((rt_uint32_t)0x00000000U)

/**
* @brief Default value for the ERFSR register
*/
#define FLEXCAN_IP_ERFSR_DEFAULT_VALUE_U32             ((rt_uint32_t)0xF8000000U)

/**
* @brief Default value for the EPRS register
*/
#define FLEXCAN_IP_EPRS_DEFAULT_VALUE_U32              ((rt_uint32_t)0x00000000U)

/**
* @brief Default value for the ENCBT register
*/
#define FLEXCAN_IP_ENCBT_DEFAULT_VALUE_U32             ((rt_uint32_t)0x00000000U)

/**
* @brief Default value for the EDCBT register
*/
#define FLEXCAN_IP_EDCBT_DEFAULT_VALUE_U32             ((rt_uint32_t)0x00000000U)

/**
* @brief Default value for the ETDC register
*/
#define FLEXCAN_IP_ETDC_DEFAULT_VALUE_U32              ((rt_uint32_t)0x00000000U)

/* @brief number of CAN peripheral has Enhanced Rx FIFO mode */
#define FLEXCAN_IP_FEATURE_ENHANCED_RX_FIFO_NUM            (10U)

/* @brief number of CAN peripheral has expandable memory */
#define FLEXCAN_IP_FEATURE_EXPANDABLE_MEMORY_NUM           (6U)

#endif