drv_qspi.c 11 KB

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  1. /*
  2. * Copyright (c) 2006-2025, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2018-11-27 zylx first version
  9. * 2025-12-14 LinuxMint-User resolve QSPI interface type mismatch
  10. */
  11. #include "board.h"
  12. #include "drv_qspi.h"
  13. #include "drv_config.h"
  14. #ifdef RT_USING_QSPI
  15. #define DRV_DEBUG
  16. #define LOG_TAG "drv.qspi"
  17. #include <drv_log.h>
  18. #if defined(BSP_USING_QSPI)
  19. struct stm32_qspi_bus
  20. {
  21. QSPI_HandleTypeDef QSPI_Handler;
  22. char *bus_name;
  23. #ifdef BSP_QSPI_USING_DMA
  24. DMA_HandleTypeDef hdma_quadspi;
  25. #endif
  26. };
  27. struct rt_spi_bus _qspi_bus1;
  28. struct stm32_qspi_bus _stm32_qspi_bus;
  29. static int stm32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configuration *qspi_cfg)
  30. {
  31. int result = RT_EOK;
  32. unsigned int i = 1;
  33. RT_ASSERT(device != RT_NULL);
  34. RT_ASSERT(qspi_cfg != RT_NULL);
  35. struct rt_spi_configuration *cfg = &qspi_cfg->parent;
  36. struct stm32_qspi_bus *qspi_bus = device->parent.bus->parent.user_data;
  37. rt_memset(&qspi_bus->QSPI_Handler, 0, sizeof(qspi_bus->QSPI_Handler));
  38. QSPI_HandleTypeDef QSPI_Handler_config = QSPI_BUS_CONFIG;
  39. qspi_bus->QSPI_Handler = QSPI_Handler_config;
  40. #if defined(SOC_SERIES_STM32MP1)
  41. while (cfg->max_hz < HAL_RCC_GetACLKFreq() / (i + 1))
  42. #else
  43. while (cfg->max_hz < HAL_RCC_GetHCLKFreq() / (i + 1))
  44. #endif
  45. {
  46. i++;
  47. if (i == 255)
  48. {
  49. LOG_E("QSPI init failed, QSPI frequency(%d) is too low.", cfg->max_hz);
  50. return -RT_ERROR;
  51. }
  52. }
  53. /* 80/(1+i) */
  54. qspi_bus->QSPI_Handler.Init.ClockPrescaler = i;
  55. if (!(cfg->mode & RT_SPI_CPOL))
  56. {
  57. /* QSPI MODE0 */
  58. qspi_bus->QSPI_Handler.Init.ClockMode = QSPI_CLOCK_MODE_0;
  59. }
  60. else
  61. {
  62. /* QSPI MODE3 */
  63. qspi_bus->QSPI_Handler.Init.ClockMode = QSPI_CLOCK_MODE_3;
  64. }
  65. /* flash size */
  66. qspi_bus->QSPI_Handler.Init.FlashSize = POSITION_VAL(qspi_cfg->medium_size) - 1;
  67. result = HAL_QSPI_Init(&qspi_bus->QSPI_Handler);
  68. if (result == HAL_OK)
  69. {
  70. LOG_D("qspi init success!");
  71. }
  72. else
  73. {
  74. LOG_E("qspi init failed (%d)!", result);
  75. }
  76. #ifdef BSP_QSPI_USING_DMA
  77. /* QSPI interrupts must be enabled when using the HAL_QSPI_Receive_DMA */
  78. HAL_NVIC_SetPriority(QSPI_IRQn, 0, 0);
  79. HAL_NVIC_EnableIRQ(QSPI_IRQn);
  80. HAL_NVIC_SetPriority(QSPI_DMA_IRQ, 0, 0);
  81. HAL_NVIC_EnableIRQ(QSPI_DMA_IRQ);
  82. /* init QSPI DMA */
  83. if(QSPI_DMA_RCC == RCC_AHB1ENR_DMA1EN)
  84. {
  85. __HAL_RCC_DMA1_CLK_ENABLE();
  86. }
  87. else
  88. {
  89. __HAL_RCC_DMA2_CLK_ENABLE();
  90. }
  91. HAL_DMA_DeInit(qspi_bus->QSPI_Handler.hdma);
  92. DMA_HandleTypeDef hdma_quadspi_config = QSPI_DMA_CONFIG;
  93. qspi_bus->hdma_quadspi = hdma_quadspi_config;
  94. if (HAL_DMA_Init(&qspi_bus->hdma_quadspi) != HAL_OK)
  95. {
  96. LOG_E("qspi dma init failed (%d)!", result);
  97. }
  98. __HAL_LINKDMA(&qspi_bus->QSPI_Handler, hdma, qspi_bus->hdma_quadspi);
  99. #endif /* BSP_QSPI_USING_DMA */
  100. return result;
  101. }
  102. static void qspi_send_cmd(struct stm32_qspi_bus *qspi_bus, struct rt_qspi_message *message)
  103. {
  104. RT_ASSERT(qspi_bus != RT_NULL);
  105. RT_ASSERT(message != RT_NULL);
  106. QSPI_CommandTypeDef Cmdhandler;
  107. /* set QSPI cmd struct */
  108. Cmdhandler.Instruction = message->instruction.content;
  109. Cmdhandler.Address = message->address.content;
  110. Cmdhandler.DummyCycles = message->dummy_cycles;
  111. if (message->instruction.qspi_lines == 0)
  112. {
  113. Cmdhandler.InstructionMode = QSPI_INSTRUCTION_NONE;
  114. }
  115. else if (message->instruction.qspi_lines == 1)
  116. {
  117. Cmdhandler.InstructionMode = QSPI_INSTRUCTION_1_LINE;
  118. }
  119. else if (message->instruction.qspi_lines == 2)
  120. {
  121. Cmdhandler.InstructionMode = QSPI_INSTRUCTION_2_LINES;
  122. }
  123. else if (message->instruction.qspi_lines == 4)
  124. {
  125. Cmdhandler.InstructionMode = QSPI_INSTRUCTION_4_LINES;
  126. }
  127. if (message->address.qspi_lines == 0)
  128. {
  129. Cmdhandler.AddressMode = QSPI_ADDRESS_NONE;
  130. }
  131. else if (message->address.qspi_lines == 1)
  132. {
  133. Cmdhandler.AddressMode = QSPI_ADDRESS_1_LINE;
  134. }
  135. else if (message->address.qspi_lines == 2)
  136. {
  137. Cmdhandler.AddressMode = QSPI_ADDRESS_2_LINES;
  138. }
  139. else if (message->address.qspi_lines == 4)
  140. {
  141. Cmdhandler.AddressMode = QSPI_ADDRESS_4_LINES;
  142. }
  143. if (message->address.size == 24)
  144. {
  145. Cmdhandler.AddressSize = QSPI_ADDRESS_24_BITS;
  146. }
  147. else
  148. {
  149. Cmdhandler.AddressSize = QSPI_ADDRESS_32_BITS;
  150. }
  151. if (message->qspi_data_lines == 0)
  152. {
  153. Cmdhandler.DataMode = QSPI_DATA_NONE;
  154. }
  155. else if (message->qspi_data_lines == 1)
  156. {
  157. Cmdhandler.DataMode = QSPI_DATA_1_LINE;
  158. }
  159. else if (message->qspi_data_lines == 2)
  160. {
  161. Cmdhandler.DataMode = QSPI_DATA_2_LINES;
  162. }
  163. else if (message->qspi_data_lines == 4)
  164. {
  165. Cmdhandler.DataMode = QSPI_DATA_4_LINES;
  166. }
  167. Cmdhandler.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
  168. Cmdhandler.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
  169. Cmdhandler.DdrMode = QSPI_DDR_MODE_DISABLE;
  170. Cmdhandler.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
  171. Cmdhandler.NbData = message->parent.length;
  172. HAL_QSPI_Command(&qspi_bus->QSPI_Handler, &Cmdhandler, 5000);
  173. }
  174. static rt_ssize_t qspixfer(struct rt_spi_device *device, struct rt_spi_message *message)
  175. {
  176. rt_ssize_t result = 0;
  177. RT_ASSERT(device != RT_NULL);
  178. RT_ASSERT(device->bus != RT_NULL);
  179. struct rt_qspi_message *qspi_message = (struct rt_qspi_message *)message;
  180. struct stm32_qspi_bus *qspi_bus = device->bus->parent.user_data;
  181. const rt_uint8_t *sndb = message->send_buf;
  182. rt_uint8_t *rcvb = message->recv_buf;
  183. rt_int32_t length = message->length;
  184. #ifdef BSP_QSPI_USING_SOFTCS
  185. if (message->cs_take && (device->cs_pin != PIN_NONE))
  186. {
  187. rt_pin_write(device->cs_pin, PIN_LOW);
  188. }
  189. #endif
  190. /* send data */
  191. if (sndb)
  192. {
  193. qspi_send_cmd(qspi_bus, qspi_message);
  194. if (qspi_message->parent.length != 0)
  195. {
  196. if (HAL_QSPI_Transmit(&qspi_bus->QSPI_Handler, (rt_uint8_t *)sndb, 5000) == HAL_OK)
  197. {
  198. result = length;
  199. }
  200. else
  201. {
  202. LOG_E("QSPI send data failed(%d)!", qspi_bus->QSPI_Handler.ErrorCode);
  203. qspi_bus->QSPI_Handler.State = HAL_QSPI_STATE_READY;
  204. result = -RT_ERROR;
  205. goto __exit;
  206. }
  207. }
  208. else
  209. {
  210. result = 1;
  211. }
  212. }
  213. else if (rcvb)/* recv data */
  214. {
  215. qspi_send_cmd(qspi_bus, qspi_message);
  216. #ifdef BSP_QSPI_USING_DMA
  217. if (HAL_QSPI_Receive_DMA(&qspi_bus->QSPI_Handler, rcvb) == HAL_OK)
  218. #else
  219. if (HAL_QSPI_Receive(&qspi_bus->QSPI_Handler, rcvb, 5000) == HAL_OK)
  220. #endif
  221. {
  222. result = length;
  223. #ifdef BSP_QSPI_USING_DMA
  224. while (qspi_bus->QSPI_Handler.RxXferCount != 0);
  225. #endif
  226. }
  227. else
  228. {
  229. LOG_E("QSPI recv data failed(%d)!", qspi_bus->QSPI_Handler.ErrorCode);
  230. qspi_bus->QSPI_Handler.State = HAL_QSPI_STATE_READY;
  231. result = -RT_ERROR;
  232. goto __exit;
  233. }
  234. }
  235. __exit:
  236. #ifdef BSP_QSPI_USING_SOFTCS
  237. if (message->cs_release && (device->cs_pin != PIN_NONE))
  238. {
  239. rt_pin_write(device->cs_pin, PIN_HIGH);
  240. }
  241. #endif
  242. return result;
  243. }
  244. static rt_err_t qspi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
  245. {
  246. RT_ASSERT(device != RT_NULL);
  247. RT_ASSERT(configuration != RT_NULL);
  248. struct rt_qspi_device *qspi_device = (struct rt_qspi_device *)device;
  249. return stm32_qspi_init(qspi_device, &qspi_device->config);
  250. }
  251. static const struct rt_spi_ops stm32_qspi_ops =
  252. {
  253. .configure = qspi_configure,
  254. .xfer = qspixfer,
  255. };
  256. static int stm32_qspi_register_bus(struct stm32_qspi_bus *qspi_bus, const char *name)
  257. {
  258. RT_ASSERT(qspi_bus != RT_NULL);
  259. RT_ASSERT(name != RT_NULL);
  260. _qspi_bus1.parent.user_data = qspi_bus;
  261. return rt_qspi_bus_register(&_qspi_bus1, name, &stm32_qspi_ops);
  262. }
  263. /**
  264. * @brief This function attach device to QSPI bus.
  265. * @param device_name QSPI device name
  266. * @param cs_pin QSPI cs pin number
  267. * @param data_line_width QSPI data lines width, such as 1, 2, 4
  268. * @param enter_qspi_mode Callback function that lets FLASH enter QSPI mode
  269. * @param exit_qspi_mode Callback function that lets FLASH exit QSPI mode
  270. * @retval 0 : success
  271. * -1 : failed
  272. */
  273. rt_err_t rt_hw_qspi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)())
  274. {
  275. struct rt_qspi_device *qspi_device = RT_NULL;
  276. rt_err_t result = RT_EOK;
  277. RT_ASSERT(bus_name != RT_NULL);
  278. RT_ASSERT(device_name != RT_NULL);
  279. RT_ASSERT(data_line_width == 1 || data_line_width == 2 || data_line_width == 4);
  280. qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
  281. if (qspi_device == RT_NULL)
  282. {
  283. LOG_E("no memory, qspi bus attach device failed!");
  284. result = -RT_ENOMEM;
  285. goto __exit;
  286. }
  287. /* Safe type conversion to resolve interface contract mismatch.
  288. * Caller ensures the function pointer is compatible via adapter pattern.
  289. */
  290. if (enter_qspi_mode != RT_NULL)
  291. {
  292. qspi_device->enter_qspi_mode = (void (*)(struct rt_qspi_device *))enter_qspi_mode;
  293. }
  294. else
  295. {
  296. qspi_device->enter_qspi_mode = RT_NULL;
  297. }
  298. if (exit_qspi_mode != RT_NULL)
  299. {
  300. qspi_device->exit_qspi_mode = (void (*)(struct rt_qspi_device *))exit_qspi_mode;
  301. }
  302. else
  303. {
  304. qspi_device->exit_qspi_mode = RT_NULL;
  305. }
  306. qspi_device->config.qspi_dl_width = data_line_width;
  307. #ifdef BSP_QSPI_USING_SOFTCS
  308. result = rt_spi_bus_attach_device_cspin(&qspi_device->parent, device_name, bus_name, cs_pin, RT_NULL);
  309. #else
  310. result = rt_spi_bus_attach_device_cspin(&qspi_device->parent, device_name, bus_name, PIN_NONE, RT_NULL);
  311. #endif /* BSP_QSPI_USING_SOFTCS */
  312. __exit:
  313. if (result != RT_EOK)
  314. {
  315. if (qspi_device)
  316. {
  317. rt_free(qspi_device);
  318. }
  319. }
  320. return result;
  321. }
  322. #ifdef BSP_QSPI_USING_DMA
  323. void QSPI_IRQHandler(void)
  324. {
  325. /* enter interrupt */
  326. rt_interrupt_enter();
  327. HAL_QSPI_IRQHandler(&_stm32_qspi_bus.QSPI_Handler);
  328. /* leave interrupt */
  329. rt_interrupt_leave();
  330. }
  331. void QSPI_DMA_IRQHandler(void)
  332. {
  333. /* enter interrupt */
  334. rt_interrupt_enter();
  335. HAL_DMA_IRQHandler(&_stm32_qspi_bus.hdma_quadspi);
  336. /* leave interrupt */
  337. rt_interrupt_leave();
  338. }
  339. #endif /* BSP_QSPI_USING_DMA */
  340. static int rt_hw_qspi_bus_init(void)
  341. {
  342. return stm32_qspi_register_bus(&_stm32_qspi_bus, "qspi1");
  343. }
  344. INIT_BOARD_EXPORT(rt_hw_qspi_bus_init);
  345. #endif /* BSP_USING_QSPI */
  346. #endif /* RT_USING_QSPI */