pic.c 28 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-08-24 GuEe-GUI first version
  9. */
  10. #include <rthw.h>
  11. #include <rtthread.h>
  12. #define DBG_TAG "rtdm.pic"
  13. #define DBG_LVL DBG_INFO
  14. #include <rtdbg.h>
  15. #include <drivers/pic.h>
  16. #ifdef RT_USING_PIC_STATISTICS
  17. #include <ktime.h>
  18. #endif
  19. struct irq_traps
  20. {
  21. rt_list_t list;
  22. void *data;
  23. rt_bool_t (*handler)(void *);
  24. };
  25. /* reserved ipi */
  26. static int _pirq_hash_idx = RT_MAX_IPI;
  27. static struct rt_pic_irq _pirq_hash[MAX_HANDLERS] =
  28. {
  29. [0 ... MAX_HANDLERS - 1] =
  30. {
  31. .irq = -1,
  32. .hwirq = -1,
  33. .mode = RT_IRQ_MODE_NONE,
  34. .priority = RT_UINT32_MAX,
  35. .rw_lock = { },
  36. }
  37. };
  38. static RT_DEFINE_SPINLOCK(_pic_lock);
  39. static rt_size_t _pic_name_max = sizeof("PIC");
  40. static rt_list_t _pic_nodes = RT_LIST_OBJECT_INIT(_pic_nodes);
  41. static rt_list_t _traps_nodes = RT_LIST_OBJECT_INIT(_traps_nodes);
  42. static struct rt_pic_irq *irq2pirq(int irq)
  43. {
  44. struct rt_pic_irq *pirq = RT_NULL;
  45. if ((irq >= 0) && (irq < MAX_HANDLERS))
  46. {
  47. pirq = &_pirq_hash[irq];
  48. if (pirq->irq < 0)
  49. {
  50. pirq = RT_NULL;
  51. }
  52. }
  53. if (!pirq)
  54. {
  55. LOG_E("irq = %d is invalid", irq);
  56. }
  57. return pirq;
  58. }
  59. static void append_pic(struct rt_pic *pic)
  60. {
  61. int pic_name_len = rt_strlen(pic->ops->name);
  62. rt_list_insert_before(&_pic_nodes, &pic->list);
  63. if (pic_name_len > _pic_name_max)
  64. {
  65. _pic_name_max = pic_name_len;
  66. }
  67. }
  68. void rt_pic_default_name(struct rt_pic *pic)
  69. {
  70. if (pic)
  71. {
  72. #if RT_NAME_MAX > 0
  73. rt_strncpy(pic->parent.name, "PIC", RT_NAME_MAX - 1);
  74. pic->parent.name[RT_NAME_MAX - 1] = '\0';
  75. #else
  76. pic->parent.name = "PIC";
  77. #endif
  78. }
  79. }
  80. struct rt_pic *rt_pic_dynamic_cast(void *ptr)
  81. {
  82. struct rt_pic *pic = RT_NULL, *tmp = RT_NULL;
  83. if (ptr)
  84. {
  85. struct rt_object *obj = ptr;
  86. if (obj->type == RT_Object_Class_Unknown)
  87. {
  88. tmp = (void *)obj;
  89. }
  90. else if (obj->type == RT_Object_Class_Device)
  91. {
  92. tmp = (void *)obj + sizeof(struct rt_device);
  93. }
  94. else
  95. {
  96. tmp = (void *)obj + sizeof(struct rt_object);
  97. }
  98. if (tmp && !rt_strcmp(tmp->parent.name, "PIC"))
  99. {
  100. pic = tmp;
  101. }
  102. }
  103. return pic;
  104. }
  105. rt_err_t rt_pic_linear_irq(struct rt_pic *pic, rt_size_t irq_nr)
  106. {
  107. rt_err_t err = RT_EOK;
  108. if (pic && pic->ops && pic->ops->name)
  109. {
  110. rt_ubase_t level = rt_spin_lock_irqsave(&_pic_lock);
  111. if (_pirq_hash_idx + irq_nr <= RT_ARRAY_SIZE(_pirq_hash))
  112. {
  113. rt_list_init(&pic->list);
  114. rt_pic_default_name(pic);
  115. pic->parent.type = RT_Object_Class_Unknown;
  116. pic->irq_start = _pirq_hash_idx;
  117. pic->irq_nr = irq_nr;
  118. pic->pirqs = &_pirq_hash[_pirq_hash_idx];
  119. _pirq_hash_idx += irq_nr;
  120. append_pic(pic);
  121. LOG_D("%s alloc irqs ranges [%d, %d]", pic->ops->name,
  122. pic->irq_start, pic->irq_start + pic->irq_nr);
  123. }
  124. else
  125. {
  126. LOG_E("%s alloc %d irqs is overflow", pic->ops->name, irq_nr);
  127. err = -RT_EEMPTY;
  128. }
  129. rt_spin_unlock_irqrestore(&_pic_lock, level);
  130. }
  131. else
  132. {
  133. err = -RT_EINVAL;
  134. }
  135. return err;
  136. }
  137. rt_err_t rt_pic_cancel_irq(struct rt_pic *pic)
  138. {
  139. rt_err_t err = RT_EOK;
  140. if (pic && pic->pirqs)
  141. {
  142. rt_ubase_t level = rt_spin_lock_irqsave(&_pic_lock);
  143. /*
  144. * This is only to make system runtime safely,
  145. * we don't recommend PICs to unregister.
  146. */
  147. rt_list_remove(&pic->list);
  148. rt_spin_unlock_irqrestore(&_pic_lock, level);
  149. }
  150. else
  151. {
  152. err = -RT_EINVAL;
  153. }
  154. return err;
  155. }
  156. static void config_pirq(struct rt_pic *pic, struct rt_pic_irq *pirq, int irq, int hwirq)
  157. {
  158. rt_ubase_t level = rt_spin_lock_irqsave(&pirq->rw_lock);
  159. if (pirq->irq < 0)
  160. {
  161. rt_list_init(&pirq->list);
  162. rt_list_init(&pirq->children_nodes);
  163. rt_list_init(&pirq->isr.list);
  164. }
  165. else if (pirq->pic != pic)
  166. {
  167. RT_ASSERT(rt_list_isempty(&pirq->list) == RT_TRUE);
  168. RT_ASSERT(rt_list_isempty(&pirq->children_nodes) == RT_TRUE);
  169. RT_ASSERT(rt_list_isempty(&pirq->isr.list) == RT_TRUE);
  170. }
  171. pirq->irq = irq;
  172. pirq->hwirq = hwirq;
  173. pirq->pic = pic;
  174. rt_spin_unlock_irqrestore(&pirq->rw_lock, level);
  175. }
  176. int rt_pic_config_ipi(struct rt_pic *pic, int ipi_index, int hwirq)
  177. {
  178. int ipi = ipi_index;
  179. struct rt_pic_irq *pirq;
  180. if (pic && ipi < RT_MAX_IPI && hwirq >= 0 && pic->ops->irq_send_ipi)
  181. {
  182. pirq = &_pirq_hash[ipi];
  183. config_pirq(pic, pirq, ipi, hwirq);
  184. for (int cpuid = 0; cpuid < RT_CPUS_NR; ++cpuid)
  185. {
  186. RT_IRQ_AFFINITY_SET(pirq->affinity, cpuid);
  187. }
  188. LOG_D("%s config %s %d to hwirq %d", pic->ops->name, "ipi", ipi, hwirq);
  189. }
  190. else
  191. {
  192. ipi = -RT_EINVAL;
  193. }
  194. return ipi;
  195. }
  196. int rt_pic_config_irq(struct rt_pic *pic, int irq_index, int hwirq)
  197. {
  198. int irq;
  199. if (pic && hwirq >= 0)
  200. {
  201. irq = pic->irq_start + irq_index;
  202. if (irq >= 0 && irq < MAX_HANDLERS)
  203. {
  204. config_pirq(pic, &_pirq_hash[irq], irq, hwirq);
  205. LOG_D("%s config %s %d to hwirq %d", pic->ops->name, "irq", irq, hwirq);
  206. }
  207. else
  208. {
  209. irq = -RT_ERROR;
  210. }
  211. }
  212. else
  213. {
  214. irq = -RT_EINVAL;
  215. }
  216. return irq;
  217. }
  218. struct rt_pic_irq *rt_pic_find_ipi(struct rt_pic *pic, int ipi_index)
  219. {
  220. struct rt_pic_irq *pirq = &_pirq_hash[ipi_index];
  221. RT_ASSERT(ipi_index < RT_MAX_IPI);
  222. RT_ASSERT(pirq->pic == pic);
  223. return pirq;
  224. }
  225. struct rt_pic_irq *rt_pic_find_pirq(struct rt_pic *pic, int irq)
  226. {
  227. if (pic && irq >= pic->irq_start && irq <= pic->irq_start + pic->irq_nr)
  228. {
  229. return &pic->pirqs[irq - pic->irq_start];
  230. }
  231. return RT_NULL;
  232. }
  233. rt_err_t rt_pic_cascade(struct rt_pic_irq *pirq, int parent_irq)
  234. {
  235. rt_err_t err = RT_EOK;
  236. if (pirq && !pirq->parent && parent_irq >= 0)
  237. {
  238. struct rt_pic_irq *parent;
  239. rt_spin_lock(&pirq->rw_lock);
  240. parent = irq2pirq(parent_irq);
  241. if (parent)
  242. {
  243. pirq->parent = parent;
  244. pirq->priority = parent->priority;
  245. rt_memcpy(&pirq->affinity, &parent->affinity, sizeof(pirq->affinity));
  246. }
  247. rt_spin_unlock(&pirq->rw_lock);
  248. if (parent && pirq->pic->ops->flags & RT_PIC_F_IRQ_ROUTING)
  249. {
  250. rt_spin_lock(&parent->rw_lock);
  251. rt_list_insert_before(&parent->children_nodes, &pirq->list);
  252. rt_spin_unlock(&parent->rw_lock);
  253. }
  254. }
  255. else
  256. {
  257. err = -RT_EINVAL;
  258. }
  259. return err;
  260. }
  261. rt_err_t rt_pic_uncascade(struct rt_pic_irq *pirq)
  262. {
  263. rt_err_t err = RT_EOK;
  264. if (pirq && pirq->parent)
  265. {
  266. struct rt_pic_irq *parent;
  267. rt_spin_lock(&pirq->rw_lock);
  268. parent = pirq->parent;
  269. pirq->parent = RT_NULL;
  270. rt_spin_unlock(&pirq->rw_lock);
  271. if (parent && pirq->pic->ops->flags & RT_PIC_F_IRQ_ROUTING)
  272. {
  273. rt_spin_lock(&parent->rw_lock);
  274. rt_list_remove(&pirq->list);
  275. rt_spin_unlock(&parent->rw_lock);
  276. }
  277. }
  278. else
  279. {
  280. err = -RT_EINVAL;
  281. }
  282. return err;
  283. }
  284. rt_err_t rt_pic_attach_irq(int irq, rt_isr_handler_t handler, void *uid, const char *name, int flags)
  285. {
  286. rt_err_t err = -RT_EINVAL;
  287. struct rt_pic_irq *pirq;
  288. if (handler && name && (pirq = irq2pirq(irq)))
  289. {
  290. struct rt_pic_isr *isr = RT_NULL;
  291. rt_ubase_t level = rt_spin_lock_irqsave(&pirq->rw_lock);
  292. err = RT_EOK;
  293. if (!pirq->isr.action.handler)
  294. {
  295. /* first attach */
  296. isr = &pirq->isr;
  297. rt_list_init(&isr->list);
  298. }
  299. else
  300. {
  301. rt_spin_unlock_irqrestore(&pirq->rw_lock, level);
  302. if ((isr = rt_malloc(sizeof(*isr))))
  303. {
  304. rt_list_init(&isr->list);
  305. level = rt_spin_lock_irqsave(&pirq->rw_lock);
  306. rt_list_insert_after(&pirq->isr.list, &isr->list);
  307. }
  308. else
  309. {
  310. LOG_E("No memory to save '%s' isr", name);
  311. err = -RT_ERROR;
  312. }
  313. }
  314. if (!err)
  315. {
  316. isr->flags = flags;
  317. isr->action.handler = handler;
  318. isr->action.param = uid;
  319. #ifdef RT_USING_INTERRUPT_INFO
  320. isr->action.counter = 0;
  321. rt_strncpy(isr->action.name, name, RT_NAME_MAX - 1);
  322. isr->action.name[RT_NAME_MAX - 1] = '\0';
  323. #ifdef RT_USING_SMP
  324. rt_memset(isr->action.cpu_counter, 0, sizeof(isr->action.cpu_counter));
  325. #endif
  326. #endif
  327. rt_spin_unlock_irqrestore(&pirq->rw_lock, level);
  328. }
  329. }
  330. return err;
  331. }
  332. rt_err_t rt_pic_detach_irq(int irq, void *uid)
  333. {
  334. rt_err_t err = -RT_EINVAL;
  335. struct rt_pic_irq *pirq = irq2pirq(irq);
  336. if (pirq)
  337. {
  338. rt_bool_t will_free = RT_FALSE;
  339. struct rt_pic_isr *isr = RT_NULL;
  340. rt_ubase_t level = rt_spin_lock_irqsave(&pirq->rw_lock);
  341. isr = &pirq->isr;
  342. if (isr->action.param == uid)
  343. {
  344. if (rt_list_isempty(&isr->list))
  345. {
  346. isr->action.handler = RT_NULL;
  347. isr->action.param = RT_NULL;
  348. }
  349. else
  350. {
  351. struct rt_pic_isr *next_isr = rt_list_first_entry(&isr->list, struct rt_pic_isr, list);
  352. rt_list_remove(&next_isr->list);
  353. isr->action.handler = next_isr->action.handler;
  354. isr->action.param = next_isr->action.param;
  355. #ifdef RT_USING_INTERRUPT_INFO
  356. isr->action.counter = next_isr->action.counter;
  357. rt_strncpy(isr->action.name, next_isr->action.name, RT_NAME_MAX);
  358. #ifdef RT_USING_SMP
  359. rt_memcpy(isr->action.cpu_counter, next_isr->action.cpu_counter, sizeof(next_isr->action.cpu_counter));
  360. #endif
  361. #endif
  362. isr = next_isr;
  363. will_free = RT_TRUE;
  364. }
  365. err = RT_EOK;
  366. }
  367. else
  368. {
  369. rt_list_for_each_entry(isr, &pirq->isr.list, list)
  370. {
  371. if (isr->action.param == uid)
  372. {
  373. err = RT_EOK;
  374. will_free = RT_TRUE;
  375. rt_list_remove(&isr->list);
  376. break;
  377. }
  378. }
  379. }
  380. rt_spin_unlock_irqrestore(&pirq->rw_lock, level);
  381. if (will_free)
  382. {
  383. rt_free(isr);
  384. }
  385. }
  386. return err;
  387. }
  388. rt_err_t rt_pic_add_traps(rt_bool_t (*handler)(void *), void *data)
  389. {
  390. rt_err_t err = -RT_EINVAL;
  391. if (handler)
  392. {
  393. struct irq_traps *traps = rt_malloc(sizeof(*traps));
  394. if (traps)
  395. {
  396. rt_ubase_t level = rt_hw_interrupt_disable();
  397. rt_list_init(&traps->list);
  398. traps->data = data;
  399. traps->handler = handler;
  400. rt_list_insert_before(&_traps_nodes, &traps->list);
  401. err = RT_EOK;
  402. rt_hw_interrupt_enable(level);
  403. }
  404. else
  405. {
  406. LOG_E("No memory to save '%p' handler", handler);
  407. err = -RT_ENOMEM;
  408. }
  409. }
  410. return err;
  411. }
  412. rt_err_t rt_pic_do_traps(void)
  413. {
  414. rt_err_t err = -RT_ERROR;
  415. struct irq_traps *traps;
  416. rt_interrupt_enter();
  417. rt_list_for_each_entry(traps, &_traps_nodes, list)
  418. {
  419. if (traps->handler(traps->data))
  420. {
  421. err = RT_EOK;
  422. break;
  423. }
  424. }
  425. rt_interrupt_leave();
  426. return err;
  427. }
  428. rt_err_t rt_pic_handle_isr(struct rt_pic_irq *pirq)
  429. {
  430. rt_err_t err = -RT_EEMPTY;
  431. rt_list_t *handler_nodes;
  432. struct rt_irq_desc *action;
  433. #ifdef RT_USING_PIC_STATISTICS
  434. struct timespec ts;
  435. rt_ubase_t irq_time_ns;
  436. rt_ubase_t current_irq_begin;
  437. #endif
  438. RT_ASSERT(pirq != RT_NULL);
  439. RT_ASSERT(pirq->pic != RT_NULL);
  440. #ifdef RT_USING_PIC_STATISTICS
  441. rt_ktime_boottime_get_ns(&ts);
  442. current_irq_begin = ts.tv_sec * (1000UL * 1000 * 1000) + ts.tv_nsec;
  443. #endif
  444. handler_nodes = &pirq->isr.list;
  445. action = &pirq->isr.action;
  446. if (!rt_list_isempty(&pirq->children_nodes))
  447. {
  448. struct rt_pic_irq *child;
  449. rt_list_for_each_entry(child, &pirq->children_nodes, list)
  450. {
  451. if (child->pic->ops->irq_ack)
  452. {
  453. child->pic->ops->irq_ack(child);
  454. }
  455. err = rt_pic_handle_isr(child);
  456. if (child->pic->ops->irq_eoi)
  457. {
  458. child->pic->ops->irq_eoi(child);
  459. }
  460. }
  461. }
  462. if (action->handler)
  463. {
  464. action->handler(pirq->irq, action->param);
  465. #ifdef RT_USING_INTERRUPT_INFO
  466. action->counter++;
  467. #ifdef RT_USING_SMP
  468. action->cpu_counter[rt_hw_cpu_id()]++;
  469. #endif
  470. #endif
  471. if (!rt_list_isempty(handler_nodes))
  472. {
  473. struct rt_pic_isr *isr;
  474. rt_list_for_each_entry(isr, handler_nodes, list)
  475. {
  476. action = &isr->action;
  477. RT_ASSERT(action->handler != RT_NULL);
  478. action->handler(pirq->irq, action->param);
  479. #ifdef RT_USING_INTERRUPT_INFO
  480. action->counter++;
  481. #ifdef RT_USING_SMP
  482. action->cpu_counter[rt_hw_cpu_id()]++;
  483. #endif
  484. #endif
  485. }
  486. }
  487. err = RT_EOK;
  488. }
  489. #ifdef RT_USING_PIC_STATISTICS
  490. rt_ktime_boottime_get_ns(&ts);
  491. irq_time_ns = ts.tv_sec * (1000UL * 1000 * 1000) + ts.tv_nsec - current_irq_begin;
  492. pirq->stat.sum_irq_time_ns += irq_time_ns;
  493. if (irq_time_ns < pirq->stat.min_irq_time_ns || pirq->stat.min_irq_time_ns == 0)
  494. {
  495. pirq->stat.min_irq_time_ns = irq_time_ns;
  496. }
  497. if (irq_time_ns > pirq->stat.max_irq_time_ns)
  498. {
  499. pirq->stat.max_irq_time_ns = irq_time_ns;
  500. }
  501. #endif
  502. return err;
  503. }
  504. rt_weak rt_err_t rt_pic_user_extends(struct rt_pic *pic)
  505. {
  506. return -RT_ENOSYS;
  507. }
  508. rt_err_t rt_pic_irq_init(void)
  509. {
  510. rt_err_t err = RT_EOK;
  511. struct rt_pic *pic;
  512. rt_list_for_each_entry(pic, &_pic_nodes, list)
  513. {
  514. if (pic->ops->irq_init)
  515. {
  516. err = pic->ops->irq_init(pic);
  517. if (err)
  518. {
  519. LOG_E("PIC = %s init fail", pic->ops->name);
  520. break;
  521. }
  522. }
  523. }
  524. return err;
  525. }
  526. rt_err_t rt_pic_irq_finit(void)
  527. {
  528. rt_err_t err = RT_EOK;
  529. struct rt_pic *pic;
  530. rt_list_for_each_entry(pic, &_pic_nodes, list)
  531. {
  532. if (pic->ops->irq_finit)
  533. {
  534. err = pic->ops->irq_finit(pic);
  535. if (err)
  536. {
  537. LOG_E("PIC = %s finit fail", pic->ops->name);
  538. break;
  539. }
  540. }
  541. }
  542. return err;
  543. }
  544. void rt_pic_irq_enable(int irq)
  545. {
  546. struct rt_pic_irq *pirq = irq2pirq(irq);
  547. RT_ASSERT(pirq != RT_NULL);
  548. rt_hw_spin_lock(&pirq->rw_lock.lock);
  549. if (pirq->pic->ops->irq_enable)
  550. {
  551. pirq->pic->ops->irq_enable(pirq);
  552. }
  553. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  554. }
  555. void rt_pic_irq_disable(int irq)
  556. {
  557. struct rt_pic_irq *pirq = irq2pirq(irq);
  558. RT_ASSERT(pirq != RT_NULL);
  559. rt_hw_spin_lock(&pirq->rw_lock.lock);
  560. if (pirq->pic->ops->irq_disable)
  561. {
  562. pirq->pic->ops->irq_disable(pirq);
  563. }
  564. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  565. }
  566. void rt_pic_irq_ack(int irq)
  567. {
  568. struct rt_pic_irq *pirq = irq2pirq(irq);
  569. RT_ASSERT(pirq != RT_NULL);
  570. rt_hw_spin_lock(&pirq->rw_lock.lock);
  571. if (pirq->pic->ops->irq_ack)
  572. {
  573. pirq->pic->ops->irq_ack(pirq);
  574. }
  575. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  576. }
  577. void rt_pic_irq_mask(int irq)
  578. {
  579. struct rt_pic_irq *pirq = irq2pirq(irq);
  580. RT_ASSERT(pirq != RT_NULL);
  581. rt_hw_spin_lock(&pirq->rw_lock.lock);
  582. if (pirq->pic->ops->irq_mask)
  583. {
  584. pirq->pic->ops->irq_mask(pirq);
  585. }
  586. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  587. }
  588. void rt_pic_irq_unmask(int irq)
  589. {
  590. struct rt_pic_irq *pirq = irq2pirq(irq);
  591. RT_ASSERT(pirq != RT_NULL);
  592. rt_hw_spin_lock(&pirq->rw_lock.lock);
  593. if (pirq->pic->ops->irq_unmask)
  594. {
  595. pirq->pic->ops->irq_unmask(pirq);
  596. }
  597. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  598. }
  599. void rt_pic_irq_eoi(int irq)
  600. {
  601. struct rt_pic_irq *pirq = irq2pirq(irq);
  602. RT_ASSERT(pirq != RT_NULL);
  603. rt_hw_spin_lock(&pirq->rw_lock.lock);
  604. if (pirq->pic->ops->irq_eoi)
  605. {
  606. pirq->pic->ops->irq_eoi(pirq);
  607. }
  608. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  609. }
  610. rt_err_t rt_pic_irq_set_priority(int irq, rt_uint32_t priority)
  611. {
  612. rt_err_t err = -RT_EINVAL;
  613. struct rt_pic_irq *pirq = irq2pirq(irq);
  614. if (pirq)
  615. {
  616. rt_hw_spin_lock(&pirq->rw_lock.lock);
  617. if (pirq->pic->ops->irq_set_priority)
  618. {
  619. err = pirq->pic->ops->irq_set_priority(pirq, priority);
  620. if (!err)
  621. {
  622. pirq->priority = priority;
  623. }
  624. }
  625. else
  626. {
  627. err = -RT_ENOSYS;
  628. }
  629. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  630. }
  631. return err;
  632. }
  633. rt_uint32_t rt_pic_irq_get_priority(int irq)
  634. {
  635. rt_uint32_t priority = RT_UINT32_MAX;
  636. struct rt_pic_irq *pirq = irq2pirq(irq);
  637. if (pirq)
  638. {
  639. rt_hw_spin_lock(&pirq->rw_lock.lock);
  640. priority = pirq->priority;
  641. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  642. }
  643. return priority;
  644. }
  645. rt_err_t rt_pic_irq_set_affinity(int irq, rt_bitmap_t *affinity)
  646. {
  647. rt_err_t err = -RT_EINVAL;
  648. struct rt_pic_irq *pirq;
  649. if (affinity && (pirq = irq2pirq(irq)))
  650. {
  651. rt_hw_spin_lock(&pirq->rw_lock.lock);
  652. if (pirq->pic->ops->irq_set_affinity)
  653. {
  654. err = pirq->pic->ops->irq_set_affinity(pirq, affinity);
  655. if (!err)
  656. {
  657. rt_memcpy(pirq->affinity, affinity, sizeof(pirq->affinity));
  658. }
  659. }
  660. else
  661. {
  662. err = -RT_ENOSYS;
  663. }
  664. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  665. }
  666. return err;
  667. }
  668. rt_err_t rt_pic_irq_get_affinity(int irq, rt_bitmap_t *out_affinity)
  669. {
  670. rt_err_t err = -RT_EINVAL;
  671. struct rt_pic_irq *pirq;
  672. if (out_affinity && (pirq = irq2pirq(irq)))
  673. {
  674. rt_hw_spin_lock(&pirq->rw_lock.lock);
  675. rt_memcpy(out_affinity, pirq->affinity, sizeof(pirq->affinity));
  676. err = RT_EOK;
  677. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  678. }
  679. return err;
  680. }
  681. rt_err_t rt_pic_irq_set_triger_mode(int irq, rt_uint32_t mode)
  682. {
  683. rt_err_t err = -RT_EINVAL;
  684. struct rt_pic_irq *pirq;
  685. if ((~mode & RT_IRQ_MODE_MASK) && (pirq = irq2pirq(irq)))
  686. {
  687. rt_hw_spin_lock(&pirq->rw_lock.lock);
  688. if (pirq->pic->ops->irq_set_triger_mode)
  689. {
  690. err = pirq->pic->ops->irq_set_triger_mode(pirq, mode);
  691. if (!err)
  692. {
  693. pirq->mode = mode;
  694. }
  695. }
  696. else
  697. {
  698. err = -RT_ENOSYS;
  699. }
  700. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  701. }
  702. return err;
  703. }
  704. rt_uint32_t rt_pic_irq_get_triger_mode(int irq)
  705. {
  706. rt_uint32_t mode = RT_UINT32_MAX;
  707. struct rt_pic_irq *pirq = irq2pirq(irq);
  708. if (pirq)
  709. {
  710. rt_hw_spin_lock(&pirq->rw_lock.lock);
  711. mode = pirq->mode;
  712. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  713. }
  714. return mode;
  715. }
  716. void rt_pic_irq_send_ipi(int irq, rt_bitmap_t *cpumask)
  717. {
  718. struct rt_pic_irq *pirq;
  719. if (cpumask && (pirq = irq2pirq(irq)))
  720. {
  721. rt_hw_spin_lock(&pirq->rw_lock.lock);
  722. if (pirq->pic->ops->irq_send_ipi)
  723. {
  724. pirq->pic->ops->irq_send_ipi(pirq, cpumask);
  725. }
  726. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  727. }
  728. }
  729. rt_err_t rt_pic_irq_set_state_raw(struct rt_pic *pic, int hwirq, int type, rt_bool_t state)
  730. {
  731. rt_err_t err;
  732. if (pic && hwirq >= 0)
  733. {
  734. if (pic->ops->irq_set_state)
  735. {
  736. err = pic->ops->irq_set_state(pic, hwirq, type, state);
  737. }
  738. else
  739. {
  740. err = -RT_ENOSYS;
  741. }
  742. }
  743. else
  744. {
  745. err = -RT_EINVAL;
  746. }
  747. return err;
  748. }
  749. rt_err_t rt_pic_irq_get_state_raw(struct rt_pic *pic, int hwirq, int type, rt_bool_t *out_state)
  750. {
  751. rt_err_t err;
  752. if (pic && hwirq >= 0)
  753. {
  754. if (pic->ops->irq_get_state)
  755. {
  756. rt_bool_t state;
  757. if (!(err = pic->ops->irq_get_state(pic, hwirq, type, &state)) && out_state)
  758. {
  759. *out_state = state;
  760. }
  761. }
  762. else
  763. {
  764. err = -RT_ENOSYS;
  765. }
  766. }
  767. else
  768. {
  769. err = -RT_EINVAL;
  770. }
  771. return err;
  772. }
  773. rt_err_t rt_pic_irq_set_state(int irq, int type, rt_bool_t state)
  774. {
  775. rt_err_t err;
  776. struct rt_pic_irq *pirq = irq2pirq(irq);
  777. RT_ASSERT(pirq != RT_NULL);
  778. rt_hw_spin_lock(&pirq->rw_lock.lock);
  779. err = rt_pic_irq_set_state_raw(pirq->pic, pirq->hwirq, type, state);
  780. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  781. return err;
  782. }
  783. rt_err_t rt_pic_irq_get_state(int irq, int type, rt_bool_t *out_state)
  784. {
  785. rt_err_t err;
  786. struct rt_pic_irq *pirq = irq2pirq(irq);
  787. RT_ASSERT(pirq != RT_NULL);
  788. rt_hw_spin_lock(&pirq->rw_lock.lock);
  789. err = rt_pic_irq_get_state_raw(pirq->pic, pirq->hwirq, type, out_state);
  790. rt_hw_spin_unlock(&pirq->rw_lock.lock);
  791. return err;
  792. }
  793. void rt_pic_irq_parent_enable(struct rt_pic_irq *pirq)
  794. {
  795. RT_ASSERT(pirq != RT_NULL);
  796. pirq = pirq->parent;
  797. if (pirq->pic->ops->irq_enable)
  798. {
  799. pirq->pic->ops->irq_enable(pirq);
  800. }
  801. }
  802. void rt_pic_irq_parent_disable(struct rt_pic_irq *pirq)
  803. {
  804. RT_ASSERT(pirq != RT_NULL);
  805. pirq = pirq->parent;
  806. if (pirq->pic->ops->irq_disable)
  807. {
  808. pirq->pic->ops->irq_disable(pirq);
  809. }
  810. }
  811. void rt_pic_irq_parent_ack(struct rt_pic_irq *pirq)
  812. {
  813. RT_ASSERT(pirq != RT_NULL);
  814. pirq = pirq->parent;
  815. if (pirq->pic->ops->irq_ack)
  816. {
  817. pirq->pic->ops->irq_ack(pirq);
  818. }
  819. }
  820. void rt_pic_irq_parent_mask(struct rt_pic_irq *pirq)
  821. {
  822. RT_ASSERT(pirq != RT_NULL);
  823. pirq = pirq->parent;
  824. if (pirq->pic->ops->irq_mask)
  825. {
  826. pirq->pic->ops->irq_mask(pirq);
  827. }
  828. }
  829. void rt_pic_irq_parent_unmask(struct rt_pic_irq *pirq)
  830. {
  831. RT_ASSERT(pirq != RT_NULL);
  832. pirq = pirq->parent;
  833. if (pirq->pic->ops->irq_unmask)
  834. {
  835. pirq->pic->ops->irq_unmask(pirq);
  836. }
  837. }
  838. void rt_pic_irq_parent_eoi(struct rt_pic_irq *pirq)
  839. {
  840. RT_ASSERT(pirq != RT_NULL);
  841. pirq = pirq->parent;
  842. if (pirq->pic->ops->irq_eoi)
  843. {
  844. pirq->pic->ops->irq_eoi(pirq);
  845. }
  846. }
  847. rt_err_t rt_pic_irq_parent_set_priority(struct rt_pic_irq *pirq, rt_uint32_t priority)
  848. {
  849. rt_err_t err = -RT_ENOSYS;
  850. RT_ASSERT(pirq != RT_NULL);
  851. pirq = pirq->parent;
  852. if (pirq->pic->ops->irq_set_priority)
  853. {
  854. if (!(err = pirq->pic->ops->irq_set_priority(pirq, priority)))
  855. {
  856. pirq->priority = priority;
  857. }
  858. }
  859. return err;
  860. }
  861. rt_err_t rt_pic_irq_parent_set_affinity(struct rt_pic_irq *pirq, rt_bitmap_t *affinity)
  862. {
  863. rt_err_t err = -RT_ENOSYS;
  864. RT_ASSERT(pirq != RT_NULL);
  865. pirq = pirq->parent;
  866. if (pirq->pic->ops->irq_set_affinity)
  867. {
  868. if (!(err = pirq->pic->ops->irq_set_affinity(pirq, affinity)))
  869. {
  870. rt_memcpy(pirq->affinity, affinity, sizeof(pirq->affinity));
  871. }
  872. }
  873. return err;
  874. }
  875. rt_err_t rt_pic_irq_parent_set_triger_mode(struct rt_pic_irq *pirq, rt_uint32_t mode)
  876. {
  877. rt_err_t err = -RT_ENOSYS;
  878. RT_ASSERT(pirq != RT_NULL);
  879. pirq = pirq->parent;
  880. if (pirq->pic->ops->irq_set_triger_mode)
  881. {
  882. if (!(err = pirq->pic->ops->irq_set_triger_mode(pirq, mode)))
  883. {
  884. pirq->mode = mode;
  885. }
  886. }
  887. return err;
  888. }
  889. #ifdef RT_USING_OFW
  890. RT_OFW_STUB_RANGE_EXPORT(pic, _pic_ofw_start, _pic_ofw_end);
  891. static rt_err_t ofw_pic_init(void)
  892. {
  893. struct rt_ofw_node *ic_np;
  894. rt_ofw_foreach_node_by_prop(ic_np, "interrupt-controller")
  895. {
  896. rt_ofw_stub_probe_range(ic_np, &_pic_ofw_start, &_pic_ofw_end);
  897. }
  898. return RT_EOK;
  899. }
  900. #else
  901. static rt_err_t ofw_pic_init(void)
  902. {
  903. return RT_EOK;
  904. }
  905. #endif /* !RT_USING_OFW */
  906. rt_err_t rt_pic_init(void)
  907. {
  908. rt_err_t err;
  909. LOG_D("init start");
  910. err = ofw_pic_init();
  911. LOG_D("init end");
  912. return err;
  913. }
  914. #if defined(RT_USING_CONSOLE) && defined(RT_USING_MSH)
  915. static int list_irq(int argc, char**argv)
  916. {
  917. rt_size_t irq_nr = 0;
  918. rt_bool_t dump_all = RT_FALSE;
  919. const char *const irq_modes[] =
  920. {
  921. [RT_IRQ_MODE_NONE] = "None",
  922. [RT_IRQ_MODE_EDGE_RISING] = "Edge-Rising",
  923. [RT_IRQ_MODE_EDGE_FALLING] = "Edge-Falling",
  924. [RT_IRQ_MODE_EDGE_BOTH] = "Edge-Both",
  925. [RT_IRQ_MODE_LEVEL_HIGH] = "Level-High",
  926. [RT_IRQ_MODE_LEVEL_LOW] = "Level-Low",
  927. };
  928. static char info[RT_CONSOLEBUF_SIZE];
  929. #ifdef RT_USING_SMP
  930. static char cpumask[RT_CPUS_NR + 1] = { [RT_CPUS_NR] = '\0' };
  931. #endif
  932. if (argc > 1)
  933. {
  934. if (!rt_strcmp(argv[1], "all"))
  935. {
  936. dump_all = RT_TRUE;
  937. }
  938. }
  939. rt_kprintf("%-*.s %-*.s %s %-*.s %-*.s %-*.s %-*.sUsers%-*.s",
  940. 6, "IRQ",
  941. 6, "HW-IRQ",
  942. "MSI",
  943. _pic_name_max, "PIC",
  944. 12, "Mode",
  945. #ifdef RT_USING_SMP
  946. rt_max(RT_CPUS_NR, 4), "CPUs",
  947. #else
  948. 0, 0,
  949. #endif
  950. #ifdef RT_USING_INTERRUPT_INFO
  951. 11, "Count",
  952. 5, ""
  953. #else
  954. 0, 0,
  955. 10, "-Number"
  956. #endif
  957. );
  958. #if defined(RT_USING_SMP) && defined(RT_USING_INTERRUPT_INFO)
  959. for (int i = 0; i < RT_CPUS_NR; i++)
  960. {
  961. rt_kprintf(" cpu%2d ", i);
  962. }
  963. #endif
  964. #ifdef RT_USING_PIC_STATISTICS
  965. rt_kprintf(" max/ns avg/ns min/ns");
  966. #endif
  967. rt_kputs("\n");
  968. for (int i = 0; i < RT_ARRAY_SIZE(_pirq_hash); ++i)
  969. {
  970. struct rt_pic_irq *pirq = &_pirq_hash[i];
  971. if (!pirq->pic || !(dump_all || pirq->isr.action.handler))
  972. {
  973. continue;
  974. }
  975. rt_snprintf(info, sizeof(info), "%-6d %-6d %c %-*.s %-*.s ",
  976. pirq->irq,
  977. pirq->hwirq,
  978. pirq->msi_desc ? 'Y' : 'N',
  979. _pic_name_max, pirq->pic->ops->name,
  980. 12, irq_modes[pirq->mode]);
  981. #ifdef RT_USING_SMP
  982. for (int group = 0, id = 0; group < RT_ARRAY_SIZE(pirq->affinity); ++group)
  983. {
  984. rt_bitmap_t mask = pirq->affinity[group];
  985. for (int idx = 0; id < RT_CPUS_NR && idx < RT_BITMAP_BIT_LEN(1); ++idx, ++id)
  986. {
  987. cpumask[RT_ARRAY_SIZE(cpumask) - id - 2] = '0' + ((mask >> idx) & 1);
  988. }
  989. }
  990. #endif /* RT_USING_SMP */
  991. rt_kputs(info);
  992. #ifdef RT_USING_SMP
  993. if (RT_CPUS_NR < 4)
  994. {
  995. rt_memset(&cpumask[RT_CPUS_NR], ' ', 4 - RT_CPUS_NR);
  996. }
  997. rt_kputs(cpumask);
  998. if (RT_CPUS_NR < 4)
  999. {
  1000. rt_kprintf("%-*.s", 4 - RT_CPUS_NR, " ");
  1001. }
  1002. #endif
  1003. #ifdef RT_USING_INTERRUPT_INFO
  1004. rt_kprintf(" %-10d ", pirq->isr.action.counter);
  1005. rt_kprintf("%-*.s", 10, pirq->isr.action.name);
  1006. #ifdef RT_USING_SMP
  1007. for (int cpuid = 0; cpuid < RT_CPUS_NR; cpuid++)
  1008. {
  1009. rt_kprintf(" %-10d", pirq->isr.action.cpu_counter[cpuid]);
  1010. }
  1011. #endif
  1012. #ifdef RT_USING_PIC_STATISTICS
  1013. rt_kprintf(" %-10d %-10d %-10d", pirq->stat.max_irq_time_ns, pirq->stat.sum_irq_time_ns/pirq->isr.action.counter, pirq->stat.min_irq_time_ns);
  1014. #endif
  1015. rt_kputs("\n");
  1016. if (!rt_list_isempty(&pirq->isr.list))
  1017. {
  1018. struct rt_pic_isr *repeat_isr;
  1019. rt_list_for_each_entry(repeat_isr, &pirq->isr.list, list)
  1020. {
  1021. rt_kputs(info);
  1022. #ifdef RT_USING_SMP
  1023. rt_kputs(cpumask);
  1024. #endif
  1025. rt_kprintf(" %-10d ", repeat_isr->action.counter);
  1026. rt_kprintf("%-*.s", 10, repeat_isr->action.name);
  1027. #ifdef RT_USING_SMP
  1028. for (int cpuid = 0; cpuid < RT_CPUS_NR; cpuid++)
  1029. {
  1030. rt_kprintf(" %-10d", repeat_isr->action.cpu_counter[cpuid]);
  1031. }
  1032. #endif
  1033. #ifdef RT_USING_PIC_STATISTICS
  1034. rt_kprintf(" --- --- ---");
  1035. #endif
  1036. rt_kputs("\n");
  1037. }
  1038. }
  1039. #else
  1040. rt_kprintf(" %d\n", rt_list_len(&pirq->isr.list));
  1041. #endif
  1042. ++irq_nr;
  1043. }
  1044. rt_kprintf("%d IRQs found\n", irq_nr);
  1045. return 0;
  1046. }
  1047. MSH_CMD_EXPORT(list_irq, dump using or args = all of irq information);
  1048. #endif /* RT_USING_CONSOLE && RT_USING_MSH */