rtc-hym8563.c 18 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-12-06 GuEe-GUI first version
  9. */
  10. #include "rtc_dm.h"
  11. #define DBG_TAG "rtc.hym8563"
  12. #define DBG_LVL DBG_INFO
  13. #include <rtdbg.h>
  14. #define HYM8563_CTL1 0x00
  15. #define HYM8563_CTL1_TEST RT_BIT(7)
  16. #define HYM8563_CTL1_STOP RT_BIT(5)
  17. #define HYM8563_CTL1_TESTC RT_BIT(3)
  18. #define HYM8563_CTL2 0x01
  19. #define HYM8563_CTL2_TI_TP RT_BIT(4)
  20. #define HYM8563_CTL2_AF RT_BIT(3)
  21. #define HYM8563_CTL2_TF RT_BIT(2)
  22. #define HYM8563_CTL2_AIE RT_BIT(1)
  23. #define HYM8563_CTL2_TIE RT_BIT(0)
  24. #define HYM8563_SEC 0x02
  25. #define HYM8563_SEC_VL RT_BIT(7)
  26. #define HYM8563_SEC_MASK 0x7f
  27. #define HYM8563_MIN 0x03
  28. #define HYM8563_MIN_MASK 0x7f
  29. #define HYM8563_HOUR 0x04
  30. #define HYM8563_HOUR_MASK 0x3f
  31. #define HYM8563_DAY 0x05
  32. #define HYM8563_DAY_MASK 0x3f
  33. #define HYM8563_WEEKDAY 0x06
  34. #define HYM8563_WEEKDAY_MASK 0x07
  35. #define HYM8563_MONTH 0x07
  36. #define HYM8563_MONTH_CENTURY RT_BIT(7)
  37. #define HYM8563_MONTH_MASK 0x1f
  38. #define HYM8563_YEAR 0x08
  39. #define HYM8563_ALM_MIN 0x09
  40. #define HYM8563_ALM_HOUR 0x0a
  41. #define HYM8563_ALM_DAY 0x0b
  42. #define HYM8563_ALM_WEEK 0x0c
  43. /* Each alarm check can be disabled by setting this bit in the register */
  44. #define HYM8563_ALM_BIT_DISABLE RT_BIT(7)
  45. #define HYM8563_CLKOUT 0x0d
  46. #define HYM8563_CLKOUT_ENABLE RT_BIT(7)
  47. #define HYM8563_CLKOUT_32768 0
  48. #define HYM8563_CLKOUT_1024 1
  49. #define HYM8563_CLKOUT_32 2
  50. #define HYM8563_CLKOUT_1 3
  51. #define HYM8563_CLKOUT_MASK 3
  52. #define HYM8563_TMR_CTL 0x0e
  53. #define HYM8563_TMR_CTL_ENABLE RT_BIT(7)
  54. #define HYM8563_TMR_CTL_4096 0
  55. #define HYM8563_TMR_CTL_64 1
  56. #define HYM8563_TMR_CTL_1 2
  57. #define HYM8563_TMR_CTL_1_60 3
  58. #define HYM8563_TMR_CTL_MASK 3
  59. #define HYM8563_TMR_CNT 0x0f
  60. struct hym8563_rtc
  61. {
  62. struct rt_device parent;
  63. struct rt_clk_node clkout_hw;
  64. struct rt_clk_cell cell;
  65. struct rt_clk_cell *cells[1];
  66. int irq;
  67. struct rt_i2c_client *client;
  68. struct rt_thread *irq_thread;
  69. struct rt_rtc_wkalarm wkalarm;
  70. };
  71. #define raw_to_hym8563_rtc(raw) rt_container_of(raw, struct hym8563_rtc, parent)
  72. #define raw_to_hym8563_clkout(raw) rt_container_of(raw, struct hym8563_rtc, clkout_hw)
  73. static rt_int32_t i2c_smbus_read_byte_data(struct rt_i2c_client *client,
  74. rt_uint8_t command)
  75. {
  76. rt_int32_t res;
  77. rt_uint8_t ret = 0;
  78. struct rt_i2c_msg msg[2];
  79. msg[0].buf = &command;
  80. msg[0].addr = client->client_addr;
  81. msg[0].len = 1;
  82. msg[0].flags = RT_I2C_WR;
  83. msg[1].buf = &ret;
  84. msg[1].addr = client->client_addr;
  85. msg[1].len = 1;
  86. msg[1].flags = RT_I2C_RD;
  87. res = rt_i2c_transfer(client->bus, msg, 2);
  88. return res == 2 ? ret : res;
  89. }
  90. static rt_int32_t i2c_smbus_write_byte_data(struct rt_i2c_client *client,
  91. rt_uint8_t command, rt_uint8_t value)
  92. {
  93. rt_int32_t res;
  94. struct rt_i2c_msg msg[1];
  95. rt_uint8_t data[2] = { command, value };
  96. msg[0].buf = data;
  97. msg[0].addr = client->client_addr;
  98. msg[0].len = 2;
  99. msg[0].flags = RT_I2C_WR;
  100. res = rt_i2c_transfer(client->bus, msg, 1);
  101. return res == 1 ? 0 : res;
  102. }
  103. /* Returns the number of read bytes */
  104. static rt_int32_t i2c_smbus_read_i2c_block_data(struct rt_i2c_client *client,
  105. rt_uint8_t command, rt_uint8_t length, rt_uint8_t *values)
  106. {
  107. struct rt_i2c_msg msg[2];
  108. msg[0].buf = &command;
  109. msg[0].addr = client->client_addr;
  110. msg[0].len = 1;
  111. msg[0].flags = RT_I2C_WR;
  112. msg[1].buf = values;
  113. msg[1].addr = client->client_addr;
  114. msg[1].len = length;
  115. msg[1].flags = RT_I2C_RD;
  116. return rt_i2c_transfer(client->bus, msg, 2);
  117. }
  118. static rt_int32_t i2c_smbus_write_i2c_block_data(struct rt_i2c_client *client,
  119. rt_uint8_t command, rt_uint8_t length, const rt_uint8_t *values)
  120. {
  121. rt_uint8_t data[32];
  122. struct rt_i2c_msg msg[1];
  123. length = rt_min_t(rt_uint8_t, length, RT_ARRAY_SIZE(data) - 1);
  124. data[0] = command;
  125. rt_memcpy(&data[1], values, length);
  126. msg[0].buf = data;
  127. msg[0].addr = client->client_addr;
  128. msg[0].len = length + 1;
  129. msg[0].flags = RT_I2C_WR;
  130. return rt_i2c_transfer(client->bus, msg, 1);
  131. }
  132. static void hym8563_rtc_read_time(struct hym8563_rtc *hym8563, time_t *sec)
  133. {
  134. struct tm tm;
  135. rt_uint8_t buf[7];
  136. if (i2c_smbus_read_i2c_block_data(hym8563->client, HYM8563_SEC, 7, buf) < 0)
  137. {
  138. return;
  139. }
  140. if (buf[0] & HYM8563_SEC_VL)
  141. {
  142. LOG_D("no valid clock/calendar values available");
  143. }
  144. tm.tm_sec = rt_bcd2bin(buf[0] & HYM8563_SEC_MASK);
  145. tm.tm_min = rt_bcd2bin(buf[1] & HYM8563_MIN_MASK);
  146. tm.tm_hour = rt_bcd2bin(buf[2] & HYM8563_HOUR_MASK);
  147. tm.tm_mday = rt_bcd2bin(buf[3] & HYM8563_DAY_MASK);
  148. tm.tm_wday = rt_bcd2bin(buf[4] & HYM8563_WEEKDAY_MASK); /* 0 = Sun */
  149. tm.tm_mon = rt_bcd2bin(buf[5] & HYM8563_MONTH_MASK) - 1; /* 0 = Jan */
  150. tm.tm_year = rt_bcd2bin(buf[6]) + 100;
  151. *sec = timegm(&tm);
  152. }
  153. static void hym8563_rtc_set_time(struct hym8563_rtc *hym8563, time_t *sec)
  154. {
  155. struct tm *tm;
  156. rt_uint8_t buf[7];
  157. struct rt_i2c_client *client = hym8563->client;
  158. tm = localtime(sec);
  159. /* Years >= 2100 are to far in the future, 19XX is to early */
  160. if (tm->tm_year < 100 || tm->tm_year >= 200)
  161. {
  162. return;
  163. }
  164. buf[0] = rt_bin2bcd(tm->tm_sec);
  165. buf[1] = rt_bin2bcd(tm->tm_min);
  166. buf[2] = rt_bin2bcd(tm->tm_hour);
  167. buf[3] = rt_bin2bcd(tm->tm_mday);
  168. buf[4] = rt_bin2bcd(tm->tm_wday);
  169. buf[5] = rt_bin2bcd(tm->tm_mon + 1);
  170. /*
  171. * While the HYM8563 has a century flag in the month register,
  172. * it does not seem to carry it over a subsequent write/read.
  173. * So we'll limit ourself to 100 years, starting at 2000 for now.
  174. */
  175. buf[6] = rt_bin2bcd(tm->tm_year - 100);
  176. /* CTL1 only contains TEST-mode bits apart from stop, so no need to read the value first */
  177. if (i2c_smbus_write_byte_data(client, HYM8563_CTL1, HYM8563_CTL1_STOP) < 0)
  178. {
  179. return;
  180. }
  181. if (i2c_smbus_write_i2c_block_data(client, HYM8563_SEC, 7, buf) < 0)
  182. {
  183. return;
  184. }
  185. if (i2c_smbus_write_byte_data(client, HYM8563_CTL1, 0) < 0)
  186. {
  187. return;
  188. }
  189. }
  190. static int hym8563_rtc_alarm_irq_enable(struct hym8563_rtc *hym8563, rt_bool_t enabled)
  191. {
  192. int data;
  193. struct rt_i2c_client *client = hym8563->client;
  194. data = i2c_smbus_read_byte_data(client, HYM8563_CTL2);
  195. if (data < 0)
  196. {
  197. return data;
  198. }
  199. if (enabled)
  200. {
  201. data |= HYM8563_CTL2_AIE;
  202. }
  203. else
  204. {
  205. data &= ~HYM8563_CTL2_AIE;
  206. }
  207. return i2c_smbus_write_byte_data(client, HYM8563_CTL2, data);
  208. };
  209. static int hym8563_rtc_read_alarm(struct hym8563_rtc *hym8563,
  210. struct rt_rtc_wkalarm *alarm)
  211. {
  212. int res;
  213. rt_uint8_t buf[4];
  214. struct rt_i2c_client *client = hym8563->client;
  215. res = i2c_smbus_read_i2c_block_data(client, HYM8563_ALM_MIN, 4, buf);
  216. if (res < 0)
  217. {
  218. return res;
  219. }
  220. /* The alarm only has a minute accuracy */
  221. alarm->tm_sec = 0;
  222. alarm->tm_min = (buf[0] & HYM8563_ALM_BIT_DISABLE) ?
  223. -1 : rt_bcd2bin(buf[0] & HYM8563_MIN_MASK);
  224. alarm->tm_hour = (buf[1] & HYM8563_ALM_BIT_DISABLE) ?
  225. -1 : rt_bcd2bin(buf[1] & HYM8563_HOUR_MASK);
  226. alarm->tm_mday = (buf[2] & HYM8563_ALM_BIT_DISABLE) ?
  227. -1 : rt_bcd2bin(buf[2] & HYM8563_DAY_MASK);
  228. /*
  229. * alarm->tm_wday = (buf[3] & HYM8563_ALM_BIT_DISABLE) ?
  230. * -1 : rt_bcd2bin(buf[3] & HYM8563_WEEKDAY_MASK);
  231. */
  232. res = i2c_smbus_read_byte_data(client, HYM8563_CTL2);
  233. if (res < 0)
  234. {
  235. return res;
  236. }
  237. alarm->enable = res & HYM8563_CTL2_AIE ? RT_TRUE : RT_FALSE;
  238. return 0;
  239. }
  240. static int hym8563_rtc_set_alarm(struct hym8563_rtc *hym8563,
  241. struct rt_rtc_wkalarm *alarm)
  242. {
  243. int res;
  244. rt_uint8_t buf[4];
  245. struct rt_i2c_client *client = hym8563->client;
  246. struct rt_rtc_wkalarm *wkalarm = &hym8563->wkalarm;
  247. res = i2c_smbus_read_byte_data(client, HYM8563_CTL2);
  248. if (res < 0)
  249. {
  250. return res;
  251. }
  252. res &= ~HYM8563_CTL2_AIE;
  253. res = i2c_smbus_write_byte_data(client, HYM8563_CTL2, res);
  254. if (res < 0)
  255. {
  256. return res;
  257. }
  258. buf[0] = (alarm->tm_min < 60 && alarm->tm_min >= 0) ?
  259. rt_bin2bcd(alarm->tm_min) : HYM8563_ALM_BIT_DISABLE;
  260. buf[1] = (alarm->tm_hour < 24 && alarm->tm_hour >= 0) ?
  261. rt_bin2bcd(alarm->tm_hour) : HYM8563_ALM_BIT_DISABLE;
  262. buf[2] = (alarm->tm_mday <= 31 && alarm->tm_mday >= 1) ?
  263. rt_bin2bcd(alarm->tm_mday) : HYM8563_ALM_BIT_DISABLE;
  264. /*
  265. * buf[3] = (alarm->tm_wday < 7 && alarm->tm_wday >= 0) ?
  266. * rt_bin2bcd(alarm->tm_wday) : HYM8563_ALM_BIT_DISABLE;
  267. */
  268. res = i2c_smbus_write_i2c_block_data(client, HYM8563_ALM_MIN, 4, buf);
  269. if (res < 0)
  270. {
  271. return res;
  272. }
  273. res = hym8563_rtc_alarm_irq_enable(hym8563, alarm->enable);
  274. if (!(res < 0))
  275. {
  276. wkalarm->enable = alarm->enable;
  277. wkalarm->tm_hour = alarm->tm_hour;
  278. wkalarm->tm_min = alarm->tm_min;
  279. wkalarm->tm_sec = alarm->tm_sec;
  280. }
  281. return res;
  282. }
  283. static rt_err_t hym8563_rtc_control(rt_device_t dev, int cmd, void *args)
  284. {
  285. rt_err_t err = RT_EOK;
  286. struct hym8563_rtc *hym8563 = raw_to_hym8563_rtc(dev);
  287. if (!args)
  288. {
  289. return -RT_EINVAL;
  290. }
  291. switch (cmd)
  292. {
  293. case RT_DEVICE_CTRL_RTC_GET_TIME:
  294. hym8563_rtc_read_time(hym8563, args);
  295. break;
  296. case RT_DEVICE_CTRL_RTC_SET_TIME:
  297. hym8563_rtc_set_time(hym8563, args);
  298. break;
  299. case RT_DEVICE_CTRL_RTC_GET_TIMEVAL:
  300. hym8563_rtc_read_time(hym8563, (time_t *)&((struct timeval *)args)->tv_sec);
  301. break;
  302. case RT_DEVICE_CTRL_RTC_SET_TIMEVAL:
  303. hym8563_rtc_set_time(hym8563, (time_t *)&((struct timeval *)args)->tv_sec);
  304. break;
  305. case RT_DEVICE_CTRL_RTC_GET_ALARM:
  306. err = hym8563_rtc_read_alarm(hym8563, args);
  307. break;
  308. case RT_DEVICE_CTRL_RTC_SET_ALARM:
  309. err = hym8563_rtc_set_alarm(hym8563, args);
  310. break;
  311. default:
  312. err = -RT_EINVAL;
  313. break;
  314. }
  315. return err;
  316. }
  317. #ifdef RT_USING_DEVICE_OPS
  318. const static struct rt_device_ops hym8563_rtc_ops =
  319. {
  320. .control = hym8563_rtc_control,
  321. };
  322. #endif
  323. static void hym8563_rtc_thread_isr(void *param)
  324. {
  325. int data, res;
  326. struct hym8563_rtc *hym8563 = param;
  327. struct rt_i2c_client *client = hym8563->client;
  328. while (RT_TRUE)
  329. {
  330. rt_thread_suspend(hym8563->irq_thread);
  331. rt_schedule();
  332. data = i2c_smbus_read_byte_data(client, HYM8563_CTL2);
  333. if (data < 0)
  334. {
  335. LOG_E("IRQ: error %sing i2c data %d", "read", data);
  336. return;
  337. }
  338. data &= ~HYM8563_CTL2_AF;
  339. res = i2c_smbus_write_byte_data(client, HYM8563_CTL2, data);
  340. if (res < 0)
  341. {
  342. LOG_E("IRQ: error %sing i2c data %d", "writ", res);
  343. return;
  344. }
  345. rt_alarm_update(&hym8563->parent, 1);
  346. }
  347. }
  348. static void hym8563_rtc_isr(int irqno, void *param)
  349. {
  350. struct hym8563_rtc *hym8563 = param;
  351. rt_thread_resume(hym8563->irq_thread);
  352. }
  353. static const int clkout_rates[] =
  354. {
  355. 32768, 1024, 32, 1,
  356. };
  357. static int hym8563_clkout_control(struct hym8563_rtc *hym8563, rt_bool_t enable)
  358. {
  359. int res = i2c_smbus_read_byte_data(hym8563->client, HYM8563_CLKOUT);
  360. if (res < 0)
  361. {
  362. return res;
  363. }
  364. if (enable)
  365. {
  366. res |= HYM8563_CLKOUT_ENABLE;
  367. }
  368. else
  369. {
  370. res &= ~HYM8563_CLKOUT_ENABLE;
  371. }
  372. return i2c_smbus_write_byte_data(hym8563->client, HYM8563_CLKOUT, res);
  373. }
  374. static rt_err_t hym8563_clkout_prepare(struct rt_clk_cell *cell)
  375. {
  376. struct hym8563_rtc *hym8563 = raw_to_hym8563_clkout(cell->clk_np);
  377. return hym8563_clkout_control(hym8563, RT_TRUE);
  378. }
  379. static void hym8563_clkout_unprepare(struct rt_clk_cell *cell)
  380. {
  381. struct hym8563_rtc *hym8563 = raw_to_hym8563_clkout(cell->clk_np);
  382. hym8563_clkout_control(hym8563, RT_FALSE);
  383. }
  384. static rt_bool_t hym8563_clkout_is_prepared(struct rt_clk_cell *cell)
  385. {
  386. int res;
  387. struct hym8563_rtc *hym8563 = raw_to_hym8563_clkout(cell->clk_np);
  388. res = i2c_smbus_read_byte_data(hym8563->client, HYM8563_CLKOUT);
  389. if (res < 0)
  390. {
  391. return RT_FALSE;
  392. }
  393. return !!(res & HYM8563_CLKOUT_ENABLE);
  394. }
  395. static rt_ubase_t hym8563_clkout_recalc_rate(struct rt_clk_cell *cell, rt_ubase_t parent_rate)
  396. {
  397. int res;
  398. struct hym8563_rtc *hym8563 = raw_to_hym8563_clkout(cell->clk_np);
  399. res = i2c_smbus_read_byte_data(hym8563->client, HYM8563_CLKOUT);
  400. if (res < 0)
  401. {
  402. return res;
  403. }
  404. res &= HYM8563_CLKOUT_MASK;
  405. return clkout_rates[res];
  406. }
  407. static rt_base_t hym8563_clkout_round_rate(struct rt_clk_cell *cell, rt_ubase_t drate,
  408. rt_ubase_t *prate)
  409. {
  410. for (int i = 0; i < RT_ARRAY_SIZE(clkout_rates); ++i)
  411. {
  412. if (clkout_rates[i] <= drate)
  413. {
  414. return clkout_rates[i];
  415. }
  416. }
  417. return 0;
  418. }
  419. static rt_err_t hym8563_clkout_set_rate(struct rt_clk_cell *cell, rt_ubase_t rate,
  420. rt_ubase_t parent_rate)
  421. {
  422. int res;
  423. struct hym8563_rtc *hym8563 = raw_to_hym8563_clkout(cell->clk_np);
  424. res = i2c_smbus_read_byte_data(hym8563->client, HYM8563_CLKOUT);
  425. if (res < 0)
  426. {
  427. return res;
  428. }
  429. for (int i = 0; i < RT_ARRAY_SIZE(clkout_rates); ++i)
  430. {
  431. if (clkout_rates[i] == rate)
  432. {
  433. res &= ~HYM8563_CLKOUT_MASK;
  434. res |= i;
  435. res = i2c_smbus_write_byte_data(hym8563->client, HYM8563_CLKOUT, res);
  436. return res >= 0 ? RT_EOK : res;
  437. }
  438. }
  439. return -RT_EINVAL;
  440. }
  441. static const struct rt_clk_ops hym8563_clkout_ops =
  442. {
  443. .prepare = hym8563_clkout_prepare,
  444. .unprepare = hym8563_clkout_unprepare,
  445. .is_prepared = hym8563_clkout_is_prepared,
  446. .recalc_rate = hym8563_clkout_recalc_rate,
  447. .round_rate = hym8563_clkout_round_rate,
  448. .set_rate = hym8563_clkout_set_rate,
  449. };
  450. static void hym8563_clkout_register_clk(struct hym8563_rtc *hym8563, struct rt_device *dev)
  451. {
  452. if (i2c_smbus_write_byte_data(hym8563->client, HYM8563_CLKOUT, 0) < 0)
  453. {
  454. return;
  455. }
  456. hym8563->cells[0] = &hym8563->cell;
  457. hym8563->cell.name = "hym8563-clkout";
  458. hym8563->cell.ops = &hym8563_clkout_ops;
  459. rt_dm_dev_prop_read_string(dev, "clock-output-names", &hym8563->cell.name);
  460. hym8563->clkout_hw.dev = dev;
  461. hym8563->clkout_hw.cells_nr = 1;
  462. hym8563->clkout_hw.cells = hym8563->cells;
  463. if (rt_clk_register(&hym8563->clkout_hw))
  464. {
  465. return;
  466. }
  467. }
  468. static rt_err_t hym8563_init_device(struct rt_i2c_client *client)
  469. {
  470. int res;
  471. /* Clear stop flag if present */
  472. res = i2c_smbus_write_byte_data(client, HYM8563_CTL1, 0);
  473. if (res < 0)
  474. {
  475. return res;
  476. }
  477. res = i2c_smbus_read_byte_data(client, HYM8563_CTL2);
  478. if (res < 0)
  479. {
  480. return res;
  481. }
  482. /* Disable alarm and timer interrupts */
  483. res &= ~HYM8563_CTL2_AIE;
  484. res &= ~HYM8563_CTL2_TIE;
  485. /* Clear any pending alarm and timer flags */
  486. if (res & HYM8563_CTL2_AF)
  487. {
  488. res &= ~HYM8563_CTL2_AF;
  489. }
  490. if (res & HYM8563_CTL2_TF)
  491. {
  492. res &= ~HYM8563_CTL2_TF;
  493. }
  494. res &= ~HYM8563_CTL2_TI_TP;
  495. return i2c_smbus_write_byte_data(client, HYM8563_CTL2, res);
  496. }
  497. static rt_err_t hym8563_rtc_probe(struct rt_i2c_client *client)
  498. {
  499. rt_err_t err;
  500. rt_int32_t res;
  501. const char *dev_name;
  502. struct rt_device *dev = &client->parent;
  503. struct hym8563_rtc *hym8563 = rt_calloc(1, sizeof(*hym8563));
  504. if (!hym8563)
  505. {
  506. return -RT_ENOMEM;
  507. }
  508. if ((res = hym8563_init_device(client)) < 0)
  509. {
  510. err = res;
  511. goto _fail;
  512. }
  513. hym8563->irq = rt_dm_dev_get_irq(dev, 0);
  514. hym8563->client = client;
  515. /* check state of calendar information */
  516. if ((res = i2c_smbus_read_byte_data(client, HYM8563_SEC)) < 0)
  517. {
  518. err = res;
  519. goto _fail;
  520. }
  521. LOG_D("rtc information is %s", (res & HYM8563_SEC_VL) ? "invalid" : "valid");
  522. if (hym8563->irq >= 0)
  523. {
  524. hym8563->irq_thread = rt_thread_create("rtc-hym8563", &hym8563_rtc_thread_isr,
  525. hym8563, DM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX / 2, 10);
  526. if (!hym8563->irq_thread)
  527. {
  528. err = -RT_ERROR;
  529. LOG_E("Create RTC IRQ thread fail");
  530. goto _fail;
  531. }
  532. rt_thread_startup(hym8563->irq_thread);
  533. rt_hw_interrupt_install(hym8563->irq, hym8563_rtc_isr, hym8563, "rtc-hym8563");
  534. rt_hw_interrupt_umask(hym8563->irq);
  535. }
  536. dev->user_data = hym8563;
  537. hym8563->parent.type = RT_Device_Class_RTC;
  538. #ifdef RT_USING_DEVICE_OPS
  539. hym8563->parent.ops = &hym8563_rtc_ops;
  540. #else
  541. hym8563->parent.control = hym8563_rtc_control;
  542. #endif
  543. rtc_dev_set_name(&hym8563->parent);
  544. dev_name = rt_dm_dev_get_name(&hym8563->parent);
  545. rt_device_register(&hym8563->parent, dev_name, RT_DEVICE_FLAG_RDWR);
  546. hym8563_clkout_register_clk(hym8563, dev);
  547. return RT_EOK;
  548. _fail:
  549. if (hym8563->irq_thread)
  550. {
  551. rt_thread_delete(hym8563->irq_thread);
  552. }
  553. rt_free(hym8563);
  554. return err;
  555. }
  556. static rt_err_t hym8563_rtc_remove(struct rt_i2c_client *client)
  557. {
  558. struct hym8563_rtc *hym8563 = client->parent.user_data;
  559. rt_dm_dev_unbind_fwdata(&client->parent, RT_NULL);
  560. if (hym8563->irq >= 0)
  561. {
  562. if (hym8563->wkalarm.enable)
  563. {
  564. hym8563_rtc_alarm_irq_enable(hym8563, RT_FALSE);
  565. }
  566. rt_hw_interrupt_mask(hym8563->irq);
  567. rt_pic_detach_irq(hym8563->irq, hym8563);
  568. rt_thread_delete(hym8563->irq_thread);
  569. }
  570. if (hym8563->cells[0])
  571. {
  572. rt_clk_unregister(&hym8563->clkout_hw);
  573. }
  574. rt_device_unregister(&hym8563->parent);
  575. rt_free(hym8563);
  576. return RT_EOK;
  577. }
  578. static const struct rt_i2c_device_id hym8563_rtc_ids[] =
  579. {
  580. { .name = "hym8563" },
  581. { /* sentinel */ },
  582. };
  583. static const struct rt_ofw_node_id hym8563_rtc_ofw_ids[] =
  584. {
  585. { .compatible = "haoyu,hym8563" },
  586. { /* sentinel */ },
  587. };
  588. static struct rt_i2c_driver hym8563_rtc_driver =
  589. {
  590. .ids = hym8563_rtc_ids,
  591. .ofw_ids = hym8563_rtc_ofw_ids,
  592. .probe = hym8563_rtc_probe,
  593. .remove = hym8563_rtc_remove,
  594. };
  595. RT_I2C_DRIVER_EXPORT(hym8563_rtc_driver);