rtc-pl031.c 6.4 KB

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  1. /*
  2. * Copyright (c) 2006-2022, RT-Thread Development Team
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. *
  6. * Change Logs:
  7. * Date Author Notes
  8. * 2022-11-26 GuEe-GUI first version
  9. */
  10. #include "rtc_dm.h"
  11. #define PL031_DR 0x00 /* data read register */
  12. #define PL031_MR 0x04 /* match register */
  13. #define PL031_LR 0x08 /* data load register */
  14. #define PL031_CR 0x0c /* control register */
  15. #define PL031_IMSC 0x10 /* interrupt mask and set register */
  16. #define PL031_RIS 0x14 /* raw interrupt status register */
  17. #define PL031_MIS 0x18 /* masked interrupt status register */
  18. #define PL031_ICR 0x1c /* interrupt clear register */
  19. #define PL031_CR_OPEN 1
  20. #define PL031_CR_CLOSE 0
  21. #define PL031_BIT_AI RT_BIT(0) /* Alarm interrupt bit */
  22. #define PL031_BIT_PI RT_BIT(1) /* Periodic interrupt bit. ST variants only. */
  23. struct pl031
  24. {
  25. struct rt_device parent;
  26. int irq;
  27. void *base;
  28. struct rt_clk *pclk;
  29. struct rt_rtc_wkalarm wkalarm;
  30. };
  31. #define raw_to_pl031(raw) rt_container_of(raw, struct pl031, parent)
  32. rt_inline rt_uint32_t pl031_read(struct pl031 *pl031, int offset)
  33. {
  34. return HWREG32(pl031->base + offset);
  35. }
  36. rt_inline void pl031_write(struct pl031 *pl031, int offset, rt_uint32_t value)
  37. {
  38. HWREG32(pl031->base + offset) = value;
  39. }
  40. static void pl031_isr(int irqno, void *param)
  41. {
  42. struct pl031 *pl031 = param;
  43. rt_uint32_t rtcmis = pl031_read(pl031, PL031_MIS);
  44. if (rtcmis & PL031_BIT_AI)
  45. {
  46. pl031_write(pl031, PL031_ICR, PL031_BIT_AI);
  47. rt_alarm_update(&pl031->parent, 1);
  48. }
  49. }
  50. static void pl031_get_secs(struct pl031 *pl031, time_t *sec)
  51. {
  52. *(rt_uint32_t *)sec = pl031_read(pl031, PL031_DR);
  53. }
  54. static void pl031_set_secs(struct pl031 *pl031, time_t *sec)
  55. {
  56. pl031_write(pl031, PL031_LR, *(rt_uint32_t *)sec);
  57. }
  58. static void pl031_get_alarm(struct pl031 *pl031, struct rt_rtc_wkalarm *alarm)
  59. {
  60. *alarm = pl031->wkalarm;
  61. alarm->enable = pl031_read(pl031, PL031_IMSC) & PL031_BIT_AI;
  62. }
  63. static void pl031_set_alarm(struct pl031 *pl031, struct rt_rtc_wkalarm *alarm)
  64. {
  65. rt_uint32_t imsc, time;
  66. struct rt_rtc_wkalarm *wkalarm = &pl031->wkalarm;
  67. wkalarm->enable = alarm->enable;
  68. wkalarm->tm_hour = alarm->tm_hour;
  69. wkalarm->tm_min = alarm->tm_min;
  70. wkalarm->tm_sec = alarm->tm_sec;
  71. time = pl031_read(pl031, PL031_DR);
  72. /* Get alarm time */
  73. time += alarm->tm_hour * 3600 + alarm->tm_min * 60 + alarm->tm_sec;
  74. pl031_write(pl031, PL031_MR, time);
  75. /* Clear any pending alarm interrupts. */
  76. pl031_write(pl031, PL031_ICR, PL031_BIT_AI);
  77. imsc = pl031_read(pl031, PL031_IMSC);
  78. if (alarm->enable)
  79. {
  80. pl031_write(pl031, PL031_IMSC, imsc | PL031_BIT_AI);
  81. }
  82. else
  83. {
  84. pl031_write(pl031, PL031_IMSC, imsc & ~PL031_BIT_AI);
  85. }
  86. }
  87. static void pl031_get_timeval(struct pl031 *pl031, struct timeval *tv)
  88. {
  89. tv->tv_sec = pl031_read(pl031, PL031_DR);
  90. }
  91. static void pl031_set_timeval(struct pl031 *pl031, struct timeval *tv)
  92. {
  93. pl031_write(pl031, PL031_LR, *(rt_uint32_t *)&tv->tv_sec);
  94. }
  95. static rt_err_t pl031_init(rt_device_t dev)
  96. {
  97. struct pl031 *pl031 = raw_to_pl031(dev);
  98. pl031_write(pl031, PL031_CR, PL031_CR_OPEN);
  99. return RT_EOK;
  100. }
  101. static rt_err_t pl031_control(rt_device_t dev, int cmd, void *args)
  102. {
  103. rt_err_t err = RT_EOK;
  104. struct pl031 *pl031 = raw_to_pl031(dev);
  105. if (!args)
  106. {
  107. return -RT_EINVAL;
  108. }
  109. switch (cmd)
  110. {
  111. case RT_DEVICE_CTRL_RTC_GET_TIME:
  112. pl031_get_secs(pl031, args);
  113. break;
  114. case RT_DEVICE_CTRL_RTC_SET_TIME:
  115. pl031_set_secs(pl031, args);
  116. break;
  117. case RT_DEVICE_CTRL_RTC_GET_TIMEVAL:
  118. pl031_get_timeval(pl031, args);
  119. break;
  120. case RT_DEVICE_CTRL_RTC_SET_TIMEVAL:
  121. pl031_set_timeval(pl031, args);
  122. break;
  123. case RT_DEVICE_CTRL_RTC_GET_ALARM:
  124. pl031_get_alarm(pl031, args);
  125. break;
  126. case RT_DEVICE_CTRL_RTC_SET_ALARM:
  127. pl031_set_alarm(pl031, args);
  128. break;
  129. default:
  130. err = -RT_EINVAL;
  131. break;
  132. }
  133. return err;
  134. }
  135. #ifdef RT_USING_DEVICE_OPS
  136. const static struct rt_device_ops pl031_rtc_ops =
  137. {
  138. .init = pl031_init,
  139. .control = pl031_control,
  140. };
  141. #endif
  142. static rt_err_t pl031_probe(struct rt_platform_device *pdev)
  143. {
  144. rt_err_t err = RT_EOK;
  145. const char *dev_name;
  146. struct rt_device *dev = &pdev->parent;
  147. struct pl031 *pl031 = rt_calloc(1, sizeof(*pl031));
  148. if (!pl031)
  149. {
  150. return -RT_ENOMEM;
  151. }
  152. pl031->base = rt_dm_dev_iomap(dev, 0);
  153. if (!pl031->base)
  154. {
  155. err = -RT_EIO;
  156. goto _fail;
  157. }
  158. pl031->irq = rt_dm_dev_get_irq(dev, 0);
  159. if (pl031->irq < 0)
  160. {
  161. err = pl031->irq;
  162. goto _fail;
  163. }
  164. pl031->pclk = rt_clk_get_by_name(dev, "apb_pclk");
  165. if (rt_is_err(pl031->pclk))
  166. {
  167. err = rt_ptr_err(pl031->pclk);
  168. goto _fail;
  169. }
  170. if ((err = rt_clk_prepare_enable(pl031->pclk)))
  171. {
  172. goto _fail;
  173. }
  174. dev->user_data = pl031;
  175. pl031->parent.type = RT_Device_Class_RTC;
  176. #ifdef RT_USING_DEVICE_OPS
  177. pl031->parent.ops = &pl031_rtc_ops;
  178. #else
  179. pl031->parent.init = pl031_init;
  180. pl031->parent.control = pl031_control;
  181. #endif
  182. rtc_dev_set_name(&pl031->parent);
  183. dev_name = rt_dm_dev_get_name(&pl031->parent);
  184. rt_device_register(&pl031->parent, dev_name, RT_DEVICE_FLAG_RDWR);
  185. rt_hw_interrupt_install(pl031->irq, pl031_isr, pl031, "rtc-pl031");
  186. rt_hw_interrupt_umask(pl031->irq);
  187. return RT_EOK;
  188. _fail:
  189. if (pl031->base)
  190. {
  191. rt_iounmap(pl031->base);
  192. }
  193. if (!rt_is_err_or_null(pl031->pclk))
  194. {
  195. rt_clk_disable_unprepare(pl031->pclk);
  196. rt_clk_put(pl031->pclk);
  197. }
  198. rt_free(pl031);
  199. return err;
  200. }
  201. static rt_err_t pl031_remove(struct rt_platform_device *pdev)
  202. {
  203. struct pl031 *pl031 = pdev->parent.user_data;
  204. rt_hw_interrupt_mask(pl031->irq);
  205. rt_pic_detach_irq(pl031->irq, pl031);
  206. rt_device_unregister(&pl031->parent);
  207. rt_clk_disable_unprepare(pl031->pclk);
  208. rt_clk_put(pl031->pclk);
  209. rt_free(pl031);
  210. return RT_EOK;
  211. }
  212. static const struct rt_ofw_node_id pl031_ofw_ids[] =
  213. {
  214. { .compatible = "arm,pl031" },
  215. { /* sentinel */ }
  216. };
  217. static struct rt_platform_driver pl031_driver =
  218. {
  219. .name = "rtc-pl031",
  220. .ids = pl031_ofw_ids,
  221. .probe = pl031_probe,
  222. .remove = pl031_remove,
  223. };
  224. RT_PLATFORM_DRIVER_EXPORT(pl031_driver);