portASM.S 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337
  1. /*
  2. * FreeRTOS Kernel <DEVELOPMENT BRANCH>
  3. * Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
  4. *
  5. * SPDX-License-Identifier: MIT
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a copy of
  8. * this software and associated documentation files (the "Software"), to deal in
  9. * the Software without restriction, including without limitation the rights to
  10. * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
  11. * the Software, and to permit persons to whom the Software is furnished to do so,
  12. * subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in all
  15. * copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
  19. * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
  20. * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
  21. * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  22. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * https://www.FreeRTOS.org
  25. * https://github.com/FreeRTOS
  26. *
  27. */
  28. .text
  29. .arm
  30. .set SYS_MODE, 0x1f
  31. .set SVC_MODE, 0x13
  32. .set IRQ_MODE, 0x12
  33. /* Hardware registers. */
  34. .extern ulICCIAR
  35. .extern ulICCEOIR
  36. .extern ulICCPMR
  37. /* Variables and functions. */
  38. .extern ulMaxAPIPriorityMask
  39. .extern _freertos_vector_table
  40. .extern pxCurrentTCB
  41. .extern vTaskSwitchContext
  42. .extern vApplicationIRQHandler
  43. .extern ulPortInterruptNesting
  44. #if defined( __ARM_FP )
  45. .extern ulPortTaskHasFPUContext
  46. #endif /* __ARM_FP */
  47. .global FreeRTOS_IRQ_Handler
  48. .global FreeRTOS_SWI_Handler
  49. .global vPortRestoreTaskContext
  50. .macro portSAVE_CONTEXT
  51. /* Save the LR and SPSR onto the system mode stack before switching to
  52. system mode to save the remaining system mode registers. */
  53. SRSDB sp!, #SYS_MODE
  54. CPS #SYS_MODE
  55. PUSH {R0-R12, R14}
  56. /* Push the critical nesting count. */
  57. LDR R2, ulCriticalNestingConst
  58. LDR R1, [R2]
  59. PUSH {R1}
  60. #if defined( __ARM_FP )
  61. /* Does the task have a floating point context that needs saving? If
  62. ulPortTaskHasFPUContext is 0 then no. */
  63. LDR R2, ulPortTaskHasFPUContextConst
  64. LDR R3, [R2]
  65. CMP R3, #0
  66. /* Save the floating point context, if any. */
  67. FMRXNE R1, FPSCR
  68. PUSHNE {R1}
  69. VPUSHNE {D0-D15}
  70. /* Save ulPortTaskHasFPUContext itself. */
  71. PUSH {R3}
  72. #endif /* __ARM_FP */
  73. /* Save the stack pointer in the TCB. */
  74. LDR R0, pxCurrentTCBConst
  75. LDR R1, [R0]
  76. STR SP, [R1]
  77. .endm
  78. ; /**********************************************************************/
  79. .macro portRESTORE_CONTEXT
  80. /* Set the SP to point to the stack of the task being restored. */
  81. LDR R0, pxCurrentTCBConst
  82. LDR R1, [R0]
  83. LDR SP, [R1]
  84. #if defined( __ARM_FP )
  85. /*
  86. * Is there a floating point context to restore? If the restored
  87. * ulPortTaskHasFPUContext is zero then no.
  88. */
  89. LDR R0, ulPortTaskHasFPUContextConst
  90. POP {R1}
  91. STR R1, [R0]
  92. CMP R1, #0
  93. /* Restore the floating point context, if any. */
  94. VPOPNE {D0-D15}
  95. POPNE {R0}
  96. VMSRNE FPSCR, R0
  97. #endif /* __ARM_FP */
  98. /* Restore the critical section nesting depth. */
  99. LDR R0, ulCriticalNestingConst
  100. POP {R1}
  101. STR R1, [R0]
  102. /* Ensure the priority mask is correct for the critical nesting depth. */
  103. LDR R2, ulICCPMRConst
  104. LDR R2, [R2]
  105. CMP R1, #0
  106. MOVEQ R4, #255
  107. LDRNE R4, ulMaxAPIPriorityMaskConst
  108. LDRNE R4, [R4]
  109. STR R4, [R2]
  110. /* Restore all system mode registers other than the SP (which is already
  111. being used). */
  112. POP {R0-R12, R14}
  113. /* Return to the task code, loading CPSR on the way. */
  114. RFEIA sp!
  115. .endm
  116. /******************************************************************************
  117. * SVC handler is used to start the scheduler.
  118. *****************************************************************************/
  119. .align 4
  120. .type FreeRTOS_SWI_Handler, %function
  121. FreeRTOS_SWI_Handler:
  122. /* Save the context of the current task and select a new task to run. */
  123. portSAVE_CONTEXT
  124. /* Ensure bit 2 of the stack pointer is clear. */
  125. MOV r2, sp
  126. AND r2, r2, #4
  127. SUB sp, sp, r2
  128. LDR R0, vTaskSwitchContextConst
  129. BLX R0
  130. portRESTORE_CONTEXT
  131. /******************************************************************************
  132. * vPortRestoreTaskContext is used to start the scheduler.
  133. *****************************************************************************/
  134. .type vPortRestoreTaskContext, %function
  135. vPortRestoreTaskContext:
  136. /* Switch to system mode. */
  137. CPS #SYS_MODE
  138. portRESTORE_CONTEXT
  139. .align 4
  140. .type FreeRTOS_IRQ_Handler, %function
  141. FreeRTOS_IRQ_Handler:
  142. /* Return to the interrupted instruction. */
  143. SUB lr, lr, #4
  144. /* Push the return address and SPSR. */
  145. PUSH {lr}
  146. MRS lr, SPSR
  147. PUSH {lr}
  148. /* Change to supervisor mode to allow reentry. */
  149. CPS #SVC_MODE
  150. /* Push used registers. */
  151. PUSH {r0-r4, r12}
  152. /* Increment nesting count. r3 holds the address of ulPortInterruptNesting
  153. for future use. r1 holds the original ulPortInterruptNesting value for
  154. future use. */
  155. LDR r3, ulPortInterruptNestingConst
  156. LDR r1, [r3]
  157. ADD r4, r1, #1
  158. STR r4, [r3]
  159. /* Read value from the interrupt acknowledge register, which is stored in r0
  160. for future parameter and interrupt clearing use. */
  161. LDR r2, ulICCIARConst
  162. LDR r2, [r2]
  163. LDR r0, [r2]
  164. /* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
  165. future use. _RB_ Is this ever needed provided the start of the stack is
  166. alligned on an 8-byte boundary? */
  167. MOV r2, sp
  168. AND r2, r2, #4
  169. SUB sp, sp, r2
  170. /* Call the interrupt handler. */
  171. PUSH {r0-r4, lr}
  172. LDR r1, vApplicationIRQHandlerConst
  173. BLX r1
  174. POP {r0-r4, lr}
  175. ADD sp, sp, r2
  176. CPSID i
  177. DSB
  178. ISB
  179. /* Write the value read from ICCIAR to ICCEOIR. */
  180. LDR r4, ulICCEOIRConst
  181. LDR r4, [r4]
  182. STR r0, [r4]
  183. /* Restore the old nesting count. */
  184. STR r1, [r3]
  185. /* A context switch is never performed if the nesting count is not 0. */
  186. CMP r1, #0
  187. BNE exit_without_switch
  188. /* Did the interrupt request a context switch? r1 holds the address of
  189. ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
  190. use. */
  191. LDR r1, =ulPortYieldRequired
  192. LDR r0, [r1]
  193. CMP r0, #0
  194. BNE switch_before_exit
  195. exit_without_switch:
  196. /* No context switch. Restore used registers, LR_irq and SPSR before
  197. returning. */
  198. POP {r0-r4, r12}
  199. CPS #IRQ_MODE
  200. POP {LR}
  201. MSR SPSR_cxsf, LR
  202. POP {LR}
  203. MOVS PC, LR
  204. switch_before_exit:
  205. /* A context switch is to be performed. Clear the context switch pending
  206. flag. */
  207. MOV r0, #0
  208. STR r0, [r1]
  209. /* Restore used registers, LR-irq and SPSR before saving the context
  210. to the task stack. */
  211. POP {r0-r4, r12}
  212. CPS #IRQ_MODE
  213. POP {LR}
  214. MSR SPSR_cxsf, LR
  215. POP {LR}
  216. portSAVE_CONTEXT
  217. /* Ensure bit 2 of the stack pointer is clear. */
  218. MOV r2, sp
  219. AND r2, r2, #4
  220. SUB sp, sp, r2
  221. /* Call the function that selects the new task to execute.
  222. vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
  223. instructions, or 8 byte aligned stack allocated data. LR does not need
  224. saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
  225. LDR R0, vTaskSwitchContextConst
  226. BLX R0
  227. /* Restore the context of, and branch to, the task selected to execute
  228. next. */
  229. portRESTORE_CONTEXT
  230. /******************************************************************************
  231. * If the application provides an implementation of vApplicationIRQHandler(),
  232. * then it will get called directly without saving the FPU registers on
  233. * interrupt entry, and this weak implementation of
  234. * vApplicationIRQHandler() will not get called.
  235. *
  236. * If the application provides its own implementation of
  237. * vApplicationFPUSafeIRQHandler() then this implementation of
  238. * vApplicationIRQHandler() will be called, save the FPU registers, and then
  239. * call vApplicationFPUSafeIRQHandler().
  240. *
  241. * Therefore, if the application writer wants FPU registers to be saved on
  242. * interrupt entry their IRQ handler must be called
  243. * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
  244. * FPU registers to be saved on interrupt entry their IRQ handler must be
  245. * called vApplicationIRQHandler().
  246. *****************************************************************************/
  247. .align 4
  248. .weak vApplicationIRQHandler
  249. .type vApplicationIRQHandler, %function
  250. vApplicationIRQHandler:
  251. PUSH {LR}
  252. #if defined( __ARM_FP )
  253. FMRX R1, FPSCR
  254. VPUSH {D0-D15}
  255. PUSH {R1}
  256. LDR r1, vApplicationFPUSafeIRQHandlerConst
  257. BLX r1
  258. POP {R0}
  259. VPOP {D0-D15}
  260. VMSR FPSCR, R0
  261. #endif /* __ARM_FP */
  262. POP {PC}
  263. ulICCIARConst: .word ulICCIAR
  264. ulICCEOIRConst: .word ulICCEOIR
  265. ulICCPMRConst: .word ulICCPMR
  266. pxCurrentTCBConst: .word pxCurrentTCB
  267. ulCriticalNestingConst: .word ulCriticalNesting
  268. #if defined( __ARM_FP )
  269. ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
  270. vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler
  271. #endif /* __ARM_FP */
  272. ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
  273. vTaskSwitchContextConst: .word vTaskSwitchContext
  274. vApplicationIRQHandlerConst: .word vApplicationIRQHandler
  275. ulPortInterruptNestingConst: .word ulPortInterruptNesting
  276. .end