6.9.1

examples/freertos/arm-cm/dpp_ek-tm4c123gxl/bsp.c

@@ -1,7 +1,7 @@
 /*****************************************************************************
 * Product: DPP example, EK-TM4C123GXL board, FreeRTOS kernel
 * Last updated for version 6.9.1
-* Last updated on  2020-09-22
+* Last updated on  2020-10-06
 *
 *                    Q u a n t u m  L e a P s
 *                    ------------------------
@@ -51,6 +51,10 @@ Q_DEFINE_THIS_FILE  /* define the name of this file for assertions */
 #define BTN_SW1     (1U << 4)
 #define BTN_SW2     (1U << 0)
 
+/* "RTOS-aware" interrupt priorities for FreeRTOS on ARM Cortex-M, NOTE1 */
+#define RTOS_AWARE_ISR_CMSIS_PRI \
+    (configMAX_SYSCALL_INTERRUPT_PRIORITY >> (8-__NVIC_PRIO_BITS))
+
 /* Local-scope objects ------------------------------------------------------*/
 static uint32_t l_rnd; // random seed
 
@@ -359,8 +363,8 @@ void QF_onStartup(void) {
     * DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
     */
     NVIC_SetPriority(UART0_IRQn,     0U); /* kernel unaware interrupt */
-    NVIC_SetPriority(GPIOA_IRQn,     QF_AWARE_ISR_CMSIS_PRI);
-    NVIC_SetPriority(SysTick_IRQn,   QF_AWARE_ISR_CMSIS_PRI + 1U);
+    NVIC_SetPriority(GPIOA_IRQn,     RTOS_AWARE_ISR_CMSIS_PRI);
+    NVIC_SetPriority(SysTick_IRQn,   RTOS_AWARE_ISR_CMSIS_PRI + 1U);
     /* ... */
 
     /* enable IRQs... */

examples/freertos/arm-cm/dpp_nucleo-h743zi/bsp.c

@@ -1,7 +1,7 @@
 /*****************************************************************************
 * Product: DPP example, NUCLEO-H743ZI board, FreeRTOS kernel
 * Last updated for version 6.9.1
-* Last updated on  2020-09-22
+* Last updated on  2020-10-06
 *
 *                    Q u a n t u m  L e a P s
 *                    ------------------------
@@ -44,6 +44,10 @@
 
 Q_DEFINE_THIS_FILE /* define the name of this file for assertions */
 
+/* "RTOS-aware" interrupt priorities for FreeRTOS on ARM Cortex-M, NOTE1 */
+#define RTOS_AWARE_ISR_CMSIS_PRI \
+    (configMAX_SYSCALL_INTERRUPT_PRIORITY >> (8-__NVIC_PRIO_BITS))
+
 /* Local-scope objects -----------------------------------------------------*/
 static uint32_t l_rnd; /* random seed */
 
@@ -340,10 +344,8 @@ void QF_onStartup(void) {
     * DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
     */
     NVIC_SetPriority(USART3_IRQn,  0U); /* kernel unaware interrupt */
-    NVIC_SetPriority(EXTI0_IRQn,
-        (configMAX_SYSCALL_INTERRUPT_PRIORITY >> (8-__NVIC_PRIO_BITS)));
-    NVIC_SetPriority(SysTick_IRQn,
-        (configMAX_SYSCALL_INTERRUPT_PRIORITY >> (8-__NVIC_PRIO_BITS)) + 1U);
+    NVIC_SetPriority(EXTI0_IRQn,   RTOS_AWARE_ISR_CMSIS_PRI);
+    NVIC_SetPriority(SysTick_IRQn, RTOS_AWARE_ISR_CMSIS_PRI + 1U);
     /* ... */
 
     /* enable IRQs... */

examples/freertos/arm-cm/dpp_stm32f746g-discovery/bsp.c

@@ -1,7 +1,7 @@
 /*****************************************************************************
 * Product: DPP example, STM32746G-Discovery board, FreeRTOS kernel
 * Last updated for version 6.9.1
-* Last updated on  2020-09-22
+* Last updated on  2020-10-06
 *
 *                    Q u a n t u m  L e a P s
 *                    ------------------------
@@ -42,6 +42,10 @@
 
 Q_DEFINE_THIS_FILE /* define the name of this file for assertions */
 
+/* "RTOS-aware" interrupt priorities for FreeRTOS on ARM Cortex-M, NOTE1 */
+#define RTOS_AWARE_ISR_CMSIS_PRI \
+    (configMAX_SYSCALL_INTERRUPT_PRIORITY >> (8-__NVIC_PRIO_BITS))
+
 /* Local-scope objects -----------------------------------------------------*/
 static uint32_t l_rnd; /* random seed */
 
@@ -336,10 +340,8 @@ void QF_onStartup(void) {
     * DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
     */
     NVIC_SetPriority(USART1_IRQn,  0U); /* kernel unaware interrupt */
-    NVIC_SetPriority(EXTI0_IRQn,
-        (configMAX_SYSCALL_INTERRUPT_PRIORITY >> (8-__NVIC_PRIO_BITS)));
-    NVIC_SetPriority(SysTick_IRQn,
-        (configMAX_SYSCALL_INTERRUPT_PRIORITY >> (8-__NVIC_PRIO_BITS)) + 1U);
+    NVIC_SetPriority(EXTI0_IRQn,   RTOS_AWARE_ISR_CMSIS_PRI);
+    NVIC_SetPriority(SysTick_IRQn, RTOS_AWARE_ISR_CMSIS_PRI + 1U);
     /* ... */
 
     /* enable IRQs... */

examples/qutest/target_efm32/qutest_port.c

@@ -1,7 +1,7 @@
 /*****************************************************************************
 * Product: QUTEST port for the EFM32-SLSTK3401A board
-* Last updated for version 6.8.0
-* Last updated on  2020-01-18
+* Last updated for version 6.9.1
+* Last updated on  2020-10-06
 *
 *                    Q u a n t u m  L e a P s
 *                    ------------------------
@@ -49,18 +49,6 @@
 
 //Q_DEFINE_THIS_MODULE("qutest_port")
 
-/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-* Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
-* DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
-*/
-enum KernelUnawareISRs { /* see NOTE00 */
-    USART0_RX_PRIO,
-    /* ... */
-    MAX_KERNEL_UNAWARE_CMSIS_PRI  /* keep always last */
-};
-/* "kernel-unaware" interrupts can't overlap "kernel-aware" interrupts */
-//Q_ASSERT_COMPILE(MAX_KERNEL_UNAWARE_CMSIS_PRI <= QF_AWARE_ISR_CMSIS_PRI);
-
 /* ISRs defined in this BSP ------------------------------------------------*/
 void USART0_RX_IRQHandler(void);
 
@@ -145,12 +133,14 @@ uint8_t QS_onStartup(void const *arg) {
     /* Enable RX interrupts */
     USART_IntEnable(l_USART0, USART_IF_RXDATAV);
 
-    /* enable the UART RX interrupt... */
+    /* explicitly set NVIC priorities of all Cortex-M interrupts used */
     NVIC_SetPriorityGrouping(0U);
-    NVIC_SetPriority(USART0_RX_IRQn, USART0_RX_PRIO);
+    NVIC_SetPriority(USART0_RX_IRQn, 0U); /* kernel unaware interrupt */
+
+    /* enable the UART RX interrupt... */
     NVIC_EnableIRQ(USART0_RX_IRQn); /* UART0 interrupt used for QS-RX */
 
-    return (uint8_t)1; /* return success */
+    return 1U; /* return success */
 }
 /*..........................................................................*/
 void QS_onCleanup(void) {

examples/qutest/target_tm4c123/qutest_port.c

@@ -1,7 +1,7 @@
 /*****************************************************************************
 * Product: QUTEST port for the EK-TM4C123GXL board
-* Last updated for version 6.8.0
-* Last updated on  2020-01-18
+* Last updated for version 6.9.1
+* Last updated on  2020-10-06
 *
 *                    Q u a n t u m  L e a P s
 *                    ------------------------
@@ -49,18 +49,6 @@
 
 //Q_DEFINE_THIS_MODULE("qutest_port")
 
-/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! CAUTION !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-* Assign a priority to EVERY ISR explicitly by calling NVIC_SetPriority().
-* DO NOT LEAVE THE ISR PRIORITIES AT THE DEFAULT VALUE!
-*/
-enum KernelUnawareISRs { /* see NOTE00 */
-    UART0_PRIO,
-    /* ... */
-    MAX_KERNEL_UNAWARE_CMSIS_PRI  /* keep always last */
-};
-/* "kernel-unaware" interrupts can't overlap "kernel-aware" interrupts */
-//Q_ASSERT_COMPILE(MAX_KERNEL_UNAWARE_CMSIS_PRI <= QF_AWARE_ISR_CMSIS_PRI);
-
 /* ISRs defined in this BSP ------------------------------------------------*/
 void UART0_IRQHandler(void);
 
@@ -180,12 +168,14 @@ uint8_t QS_onStartup(void const *arg) {
     UART0->IM   |= (1U << 4) | (1U << 6); /* enable RX and RX-TO interrupt */
     UART0->IFLS |= (0x2U << 2);    /* interrupt on RX FIFO half-full */
 
-    /* enable the UART RX interrupt... */
+    /* explicitly set NVIC priorities of all Cortex-M interrupts used */
     NVIC_SetPriorityGrouping(0U);
-    NVIC_SetPriority(UART0_IRQn, UART0_PRIO);
+    NVIC_SetPriority(UART0_IRQn, 0U); /* kernel unaware interrupt */
+
+    /* enable the UART RX interrupt... */
     NVIC_EnableIRQ(UART0_IRQn);  /* UART0 interrupt used for QS-RX */
 
-    return (uint8_t)1; /* return success */
+    return 1U; /* return success */
 }
 /*..........................................................................*/
 void QS_onCleanup(void) {

examples/ucos-ii/arm-cm/dpp_ek-tm4c123gxl/bsp.c

@@ -383,6 +383,6 @@ void QS_onCommand(uint8_t cmdId,
 /*****************************************************************************
 * NOTE1:
 * All ISRs that make system calls MUST be prioritized as "kernel-aware".
-* On Cortex-M3/4/7 this means ISR priorities with numerical valuses higher
+* On Cortex-M3/4/7 this means ISR priorities with numerical values higher
 * or equal CPU_CFG_KA_IPL_BOUNDARY.
 */

include/qpc.h

@@ -149,7 +149,7 @@ extern "C" {
 
 /*! @deprecated call to the QMSM_DISPATCH() operation;
 * instead use: QHSM_DISPATCH() */
-#define QMSM_DISPATCH(me_, e_) QHSM_DISPATCH((me_), (e_))
+#define QMSM_DISPATCH(me_, e_) QHSM_DISPATCH((me_), (e_), 0U)
 
 /****************************************************************************/
 #if (QP_API_VERSION < 540)