6.4.0

3rd_party/FreeRTOS/License/license.txt

@@ -17,7 +17,7 @@ source file.
 License text:
 -------------
 
-Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 Permission is hereby granted, free of charge, to any person obtaining a copy of
 this software and associated documentation files (the "Software"), to deal in
 the Software without restriction, including without limitation the rights to

3rd_party/FreeRTOS/Source/croutine.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/event_groups.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/include/FreeRTOS.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -156,6 +156,10 @@ extern "C" {
     #define INCLUDE_uxTaskGetStackHighWaterMark 0
 #endif
 
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark2
+    #define INCLUDE_uxTaskGetStackHighWaterMark2 0
+#endif
+
 #ifndef INCLUDE_eTaskGetState
     #define INCLUDE_eTaskGetState 0
 #endif
@@ -758,8 +762,12 @@ extern "C" {
     #define portTASK_USES_FLOATING_POINT()
 #endif
 
-#ifndef portTASK_CALLS_SECURE_FUNCTIONS
-    #define portTASK_CALLS_SECURE_FUNCTIONS()
+#ifndef portALLOCATE_SECURE_CONTEXT
+    #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+#endif
+
+#ifndef portHAS_STACK_OVERFLOW_CHECKING
+    #define portHAS_STACK_OVERFLOW_CHECKING 0
 #endif
 
 #ifndef configUSE_TIME_SLICING
@@ -950,6 +958,75 @@ point support. */
     #define configUSE_TASK_FPU_SUPPORT 1
 #endif
 
+/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is
+currently used in ARMv8M ports. */
+#ifndef configENABLE_MPU
+    #define configENABLE_MPU 0
+#endif
+
+/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is
+currently used in ARMv8M ports. */
+#ifndef configENABLE_FPU
+    #define configENABLE_FPU 1
+#endif
+
+/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.
+This is currently used in ARMv8M ports. */
+#ifndef configENABLE_TRUSTZONE
+    #define configENABLE_TRUSTZONE 1
+#endif
+
+/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on
+the Secure Side only. */
+#ifndef configRUN_FREERTOS_SECURE_ONLY
+    #define configRUN_FREERTOS_SECURE_ONLY 0
+#endif
+
+/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
+ * dynamically allocated RAM, in which case when any task is deleted it is known
+ * that both the task's stack and TCB need to be freed.  Sometimes the
+ * FreeRTOSConfig.h settings only allow a task to be created using statically
+ * allocated RAM, in which case when any task is deleted it is known that neither
+ * the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h
+ * settings allow a task to be created using either statically or dynamically
+ * allocated RAM, in which case a member of the TCB is used to record whether the
+ * stack and/or TCB were allocated statically or dynamically, so when a task is
+ * deleted the RAM that was allocated dynamically is freed again and no attempt is
+ * made to free the RAM that was allocated statically.
+ * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
+ * task to be created using either statically or dynamically allocated RAM.  Note
+ * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
+ * a statically allocated stack and a dynamically allocated TCB.
+ *
+ * The following table lists various combinations of portUSING_MPU_WRAPPERS,
+ * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and
+ * when it is possible to have both static and dynamic allocation:
+ *  +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | MPU | Dynamic | Static |     Available Functions     |       Possible Allocations        | Both Dynamic and | Need Free |
+ * |     |         |        |                             |                                   | Static Possible  |           |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | 0   | 0       | 1      | xTaskCreateStatic           | TCB - Static, Stack - Static      | No               | No        |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0   | 1       | 0      | xTaskCreate                 | TCB - Dynamic, Stack - Dynamic    | No               | Yes       |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateStatic           | 2. TCB - Static, Stack - Static   |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 0       | 1      | xTaskCreateStatic,          | TCB - Static, Stack - Static      | No               | No        |
+ * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 1       | 0      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateRestricted       | 2. TCB - Dynamic, Stack - Static  |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateStatic,          | 2. TCB - Dynamic, Stack - Static  |                  |           |
+ * |     |         |        | xTaskCreateRestricted,      | 3. TCB - Static, Stack - Static   |                  |           |
+ * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ */
+#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE    ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \
+                                                      ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )
+
 /*
  * In line with software engineering best practice, FreeRTOS implements a strict
  * data hiding policy, so the real structures used by FreeRTOS to maintain the
@@ -962,25 +1039,40 @@ point support. */
  */
 struct xSTATIC_LIST_ITEM
 {
-    TickType_t xDummy1;
-    void *pvDummy2[ 4 ];
+    #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+        TickType_t xDummy1;
+    #endif
+    TickType_t xDummy2;
+    void *pvDummy3[ 4 ];
+    #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+        TickType_t xDummy4;
+    #endif
 };
 typedef struct xSTATIC_LIST_ITEM StaticListItem_t;
 
 /* See the comments above the struct xSTATIC_LIST_ITEM definition. */
 struct xSTATIC_MINI_LIST_ITEM
 {
-    TickType_t xDummy1;
-    void *pvDummy2[ 2 ];
+    #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+        TickType_t xDummy1;
+    #endif
+    TickType_t xDummy2;
+    void *pvDummy3[ 2 ];
 };
 typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;
 
 /* See the comments above the struct xSTATIC_LIST_ITEM definition. */
 typedef struct xSTATIC_LIST
 {
-    UBaseType_t uxDummy1;
-    void *pvDummy2;
-    StaticMiniListItem_t xDummy3;
+    #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+        TickType_t xDummy1;
+    #endif
+    UBaseType_t uxDummy2;
+    void *pvDummy3;
+    StaticMiniListItem_t xDummy4;
+    #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+        TickType_t xDummy5;
+    #endif
 } StaticList_t;
 
 /*
@@ -1034,7 +1126,7 @@ typedef struct xSTATIC_TCB
         uint32_t         ulDummy18;
         uint8_t         ucDummy19;
     #endif
-    #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+    #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
         uint8_t            uxDummy20;
     #endif
 
@@ -1138,16 +1230,12 @@ typedef struct xSTATIC_TIMER
     void                *pvDummy1;
     StaticListItem_t    xDummy2;
     TickType_t            xDummy3;
-    UBaseType_t            uxDummy4;
     void                 *pvDummy5;
     TaskFunction_t        pvDummy6;
     #if( configUSE_TRACE_FACILITY == 1 )
         UBaseType_t        uxDummy7;
     #endif
-
-    #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-        uint8_t         ucDummy8;
-    #endif
+    uint8_t             ucDummy8;
 
 } StaticTimer_t;
 

3rd_party/FreeRTOS/Source/include/StackMacros.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/include/croutine.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/include/deprecated_definitions.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/include/event_groups.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/include/list.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/include/message_buffer.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/include/mpu_prototypes.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -38,117 +38,118 @@
 #define MPU_PROTOTYPES_H
 
 /* MPU versions of tasks.h API functions. */
-BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask );
-TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer );
-BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );
-BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );
-void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
-void MPU_vTaskDelete( TaskHandle_t xTaskToDelete );
-void MPU_vTaskDelay( const TickType_t xTicksToDelay );
-void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement );
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask );
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask );
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask );
-void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
-void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend );
-void MPU_vTaskResume( TaskHandle_t xTaskToResume );
-void MPU_vTaskStartScheduler( void );
-void MPU_vTaskSuspendAll( void );
-BaseType_t MPU_xTaskResumeAll( void );
-TickType_t MPU_xTaskGetTickCount( void );
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void );
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery );
-TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery );
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask );
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue );
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex );
-BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void );
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime );
-void MPU_vTaskList( char * pcWriteBuffer );
-void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer );
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue );
-BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
-uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
-BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask );
-BaseType_t MPU_xTaskIncrementTick( void );
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void );
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
-void MPU_vTaskMissedYield( void );
-BaseType_t MPU_xTaskGetSchedulerState( void );
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
 
 /* MPU versions of queue.h API functions. */
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition );
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait );
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait );
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait );
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue );
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue );
-void MPU_vQueueDelete( QueueHandle_t xQueue );
-QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType );
-QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue );
-QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount );
-QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue );
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore );
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait );
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex );
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName );
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue );
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue );
-QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType );
-QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType );
-QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength );
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );
-BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait );
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue );
-void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber );
-UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue );
-uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue );
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
 
 /* MPU versions of timers.h API functions. */
-TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction );
-TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer );
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer );
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer );
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void );
-BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait );
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer );
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer );
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer );
-BaseType_t MPU_xTimerCreateTimerTask( void );
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait );
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
 
 /* MPU versions of event_group.h API functions. */
-EventGroupHandle_t MPU_xEventGroupCreate( void );
-EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer );
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait );
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait );
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup );
-UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup );
+EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
 
 /* MPU versions of message/stream_buffer.h API functions. */
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait );
-size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken );
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait );
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer );
-size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken );
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
-StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer );
-StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer );
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
 
 
 

3rd_party/FreeRTOS/Source/include/mpu_wrappers.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -67,6 +67,7 @@ only for ports that are using the MPU. */
         #define pcTaskGetName                            MPU_pcTaskGetName
         #define xTaskGetHandle                            MPU_xTaskGetHandle
         #define uxTaskGetStackHighWaterMark                MPU_uxTaskGetStackHighWaterMark
+        #define uxTaskGetStackHighWaterMark2            MPU_uxTaskGetStackHighWaterMark2
         #define vTaskSetApplicationTaskTag                MPU_vTaskSetApplicationTaskTag
         #define xTaskGetApplicationTaskTag                MPU_xTaskGetApplicationTaskTag
         #define vTaskSetThreadLocalStoragePointer        MPU_vTaskSetThreadLocalStoragePointer
@@ -76,6 +77,7 @@ only for ports that are using the MPU. */
         #define uxTaskGetSystemState                    MPU_uxTaskGetSystemState
         #define vTaskList                                MPU_vTaskList
         #define vTaskGetRunTimeStats                    MPU_vTaskGetRunTimeStats
+        #define xTaskGetIdleRunTimeCounter                MPU_xTaskGetIdleRunTimeCounter
         #define xTaskGenericNotify                        MPU_xTaskGenericNotify
         #define xTaskNotifyWait                            MPU_xTaskNotifyWait
         #define ulTaskNotifyTake                        MPU_ulTaskNotifyTake
@@ -124,6 +126,7 @@ only for ports that are using the MPU. */
         #define xTimerGetTimerDaemonTaskHandle            MPU_xTimerGetTimerDaemonTaskHandle
         #define xTimerPendFunctionCall                    MPU_xTimerPendFunctionCall
         #define pcTimerGetName                            MPU_pcTimerGetName
+        #define vTimerSetReloadMode                        MPU_vTimerSetReloadMode
         #define xTimerGetPeriod                            MPU_xTimerGetPeriod
         #define xTimerGetExpiryTime                        MPU_xTimerGetExpiryTime
         #define xTimerGenericCommand                    MPU_xTimerGenericCommand
@@ -140,10 +143,8 @@ only for ports that are using the MPU. */
         /* Map standard message/stream_buffer.h API functions to the MPU
         equivalents. */
         #define xStreamBufferSend                        MPU_xStreamBufferSend
-        #define xStreamBufferSendFromISR                MPU_xStreamBufferSendFromISR
         #define xStreamBufferReceive                    MPU_xStreamBufferReceive
         #define xStreamBufferNextMessageLengthBytes        MPU_xStreamBufferNextMessageLengthBytes
-        #define xStreamBufferReceiveFromISR                MPU_xStreamBufferReceiveFromISR
         #define vStreamBufferDelete                        MPU_vStreamBufferDelete
         #define xStreamBufferIsFull                        MPU_xStreamBufferIsFull
         #define xStreamBufferIsEmpty                    MPU_xStreamBufferIsEmpty
@@ -160,12 +161,14 @@ only for ports that are using the MPU. */
         (useful when using statically allocated objects). */
         #define PRIVILEGED_FUNCTION
         #define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+        #define FREERTOS_SYSTEM_CALL
 
     #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
 
         /* Ensure API functions go in the privileged execution section. */
         #define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
         #define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+        #define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
 
     #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
 
@@ -173,6 +176,7 @@ only for ports that are using the MPU. */
 
     #define PRIVILEGED_FUNCTION
     #define PRIVILEGED_DATA
+    #define FREERTOS_SYSTEM_CALL
     #define portUSING_MPU_WRAPPERS 0
 
 #endif /* portUSING_MPU_WRAPPERS */

3rd_party/FreeRTOS/Source/include/portable.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -97,9 +97,17 @@ extern "C" {
  *
  */
 #if( portUSING_MPU_WRAPPERS == 1 )
-    StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+    #if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+        StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+    #else
+        StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+    #endif
 #else
-    StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+    #if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+        StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+    #else
+        StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+    #endif
 #endif
 
 /* Used by heap_5.c. */

3rd_party/FreeRTOS/Source/include/projdefs.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/include/queue.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/include/semphr.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/include/stack_macros.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/include/stream_buffer.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/include/task.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -43,10 +43,18 @@ extern "C" {
  * MACROS AND DEFINITIONS
  *----------------------------------------------------------*/
 
-#define tskKERNEL_VERSION_NUMBER "V10.1.1"
+#define tskKERNEL_VERSION_NUMBER "V10.2.0"
 #define tskKERNEL_VERSION_MAJOR 10
-#define tskKERNEL_VERSION_MINOR 1
-#define tskKERNEL_VERSION_BUILD 1
+#define tskKERNEL_VERSION_MINOR 2
+#define tskKERNEL_VERSION_BUILD 0
+
+/* MPU region parameters passed in ulParameters
+ * of MemoryRegion_t struct. */
+#define tskMPU_REGION_READ_ONLY            ( 1UL << 0UL )
+#define tskMPU_REGION_READ_WRITE        ( 1UL << 1UL )
+#define tskMPU_REGION_EXECUTE_NEVER        ( 1UL << 2UL )
+#define tskMPU_REGION_NORMAL_MEMORY        ( 1UL << 3UL )
+#define tskMPU_REGION_DEVICE_MEMORY        ( 1UL << 4UL )
 
 /**
  * task. h
@@ -114,7 +122,7 @@ typedef struct xTASK_PARAMETERS
 {
     TaskFunction_t pvTaskCode;
     const char * const pcName;    /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-    uint16_t usStackDepth;
+    configSTACK_DEPTH_TYPE usStackDepth;
     void *pvParameters;
     UBaseType_t uxPriority;
     StackType_t *puxStackBuffer;
@@ -376,9 +384,9 @@ is used in assert() statements. */
  * memory to be allocated dynamically.
  *
  * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
- * be created and pdPASS is returned.  If either pxStackBuffer or pxTaskBuffer
- * are NULL then the task will not be created and
- * errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY is returned.
+ * be created and a handle to the created task is returned.  If either
+ * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
+ * NULL is returned.
  *
  * Example usage:
    <pre>
@@ -1413,6 +1421,12 @@ TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*
  * a value of 1 means 4 bytes) since the task started.  The smaller the returned
  * number the closer the task has come to overflowing its stack.
  *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
  * @param xTask Handle of the task associated with the stack to be checked.
  * Set xTask to NULL to check the stack of the calling task.
  *
@@ -1422,6 +1436,33 @@ TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*
  */
 UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
 
+/**
+ * task.h
+ * <PRE>configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );</PRE>
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
 /* When using trace macros it is sometimes necessary to include task.h before
 FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
 so the following two prototypes will cause a compilation error.  This can be
@@ -1444,9 +1485,20 @@ constant. */
          * task.h
          * <pre>void xTaskGetApplicationTaskTag( TaskHandle_t xTask );</pre>
          *
-         * Returns the pxHookFunction value assigned to the task xTask.
+         * Returns the pxHookFunction value assigned to the task xTask.  Do not
+         * call from an interrupt service routine - call
+         * xTaskGetApplicationTaskTagFromISR() instead.
          */
         TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+        /**
+         * task.h
+         * <pre>void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );</pre>
+         *
+         * Returns the pxHookFunction value assigned to the task xTask.  Can
+         * be called from an interrupt service routine.
+         */
+        TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
     #endif /* configUSE_APPLICATION_TASK_TAG ==1 */
 #endif /* ifdef configUSE_APPLICATION_TASK_TAG */
 
@@ -1684,6 +1736,36 @@ void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unquali
  */
 void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 
+/**
+* task. h
+* <PRE>TickType_t xTaskGetIdleRunTimeCounter( void );</PRE>
+*
+* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+* must both be defined as 1 for this function to be available.  The application
+* must also then provide definitions for
+* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+* to configure a peripheral timer/counter and return the timers current count
+* value respectively.  The counter should be at least 10 times the frequency of
+* the tick count.
+*
+* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+* accumulated execution time being stored for each task.  The resolution
+* of the accumulated time value depends on the frequency of the timer
+* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+* execution time of each task into a buffer, xTaskGetIdleRunTimeCounter()
+* returns the total execution time of just the idle task.
+*
+* @return The total run time of the idle task.  This is the amount of time the
+* idle task has actually been executing.  The unit of time is dependent on the
+* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+* portGET_RUN_TIME_COUNTER_VALUE() macros.
+*
+* \defgroup xTaskGetIdleRunTimeCounter xTaskGetIdleRunTimeCounter
+* \ingroup TaskUtils
+*/
+TickType_t xTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+
 /**
  * task. h
  * <PRE>BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );</PRE>
@@ -2302,7 +2384,7 @@ void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVIL
 void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
 
 /*
- * Only avilable when configUSE_TICKLESS_IDLE is set to 1.
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
  * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
  * specific sleep function to determine if it is ok to proceed with the sleep,
  * and if it is ok to proceed, if it is ok to sleep indefinitely.

3rd_party/FreeRTOS/Source/include/timers.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -1231,6 +1231,23 @@ BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvPar
  */
 const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
 
+/**
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
+ *
+ * Updates a timer to be either an autoreload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being updated.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the timer's period (see the
+ * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ */
+void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+
 /**
  * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
  *

3rd_party/FreeRTOS/Source/list.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/ARMv8M/ReadMe.txt

@@ -0,0 +1,10 @@
+This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
+Do not use the files located here!  These file are copied into separate
+FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
+FreeRTOS release.
+
+If your Cortex-M33 application uses TrustZone then use the files from the
+FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
+
+If your Cortex-M33 application does not use TrustZone then use the files from
+the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.

3rd_party/FreeRTOS/Source/portable/ARMv8M/copy_files.py

@@ -0,0 +1,91 @@
+#/*
+# * FreeRTOS Kernel V10.2.0
+# * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+# *
+# * Permission is hereby granted, free of charge, to any person obtaining a copy of
+# * this software and associated documentation files (the "Software"), to deal in
+# * the Software without restriction, including without limitation the rights to
+# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+# * the Software, and to permit persons to whom the Software is furnished to do so,
+# * subject to the following conditions:
+# *
+# * The above copyright notice and this permission notice shall be included in all
+# * copies or substantial portions of the Software.
+# *
+# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+# *
+# * http://www.FreeRTOS.org
+# * http://aws.amazon.com/freertos
+# *
+# * 1 tab == 4 spaces!
+# */
+
+import os
+import shutil
+
+_THIS_FILE_DIRECTORY_ = os.path.dirname(os.path.realpath(__file__))
+_FREERTOS_PORTABLE_DIRECTORY_ = os.path.dirname(_THIS_FILE_DIRECTORY_)
+
+_COMPILERS_ = ['GCC', 'IAR']
+_ARCH_NS_ = ['ARM_CM33', 'ARM_CM33_NTZ']
+_ARCH_S_ = ['ARM_CM33']
+
+# Files to be complied in the Secure Project
+_SECURE_FILE_PATHS_ = [
+    os.path.join('secure', 'context'),
+    os.path.join('secure', 'context', 'portable', '_COMPILER_ARCH_'),
+    os.path.join('secure', 'heap'),
+    os.path.join('secure', 'init'),
+    os.path.join('secure', 'macros')
+]
+
+# Files to be complied in the Non-Secure Project
+_NONSECURE_FILE_PATHS_ = [
+    'non_secure',
+    os.path.join('non_secure', 'portable', '_COMPILER_ARCH_')
+]
+
+def copy_files_in_dir(src_abs_path, dst_abs_path):
+    for src_file in os.listdir(src_abs_path):
+        src_file_abs_path = os.path.join(src_abs_path, src_file)
+        if os.path.isfile(src_file_abs_path) and src_file != 'ReadMe.txt':
+            if not os.path.exists(dst_abs_path):
+                os.makedirs(dst_abs_path)
+            print('Copying {}...'.format(os.path.basename(src_file_abs_path)))
+            shutil.copy2(src_file_abs_path, dst_abs_path)
+
+
+def copy_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path):
+    _COMPILER_ARCH_ = os.path.join(compiler, arch)
+    for src_path in src_paths:
+        src_path_sanitized = src_path.replace('_COMPILER_ARCH_', _COMPILER_ARCH_ )
+
+        src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path_sanitized)
+        dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, _COMPILER_ARCH_, dst_path)
+
+        copy_files_in_dir(src_abs_path, dst_abs_path)
+
+
+def copy_files():
+    # Copy Secure Files
+    for compiler in _COMPILERS_:
+        for arch in _ARCH_S_:
+            copy_files_for_compiler_and_arch(compiler, arch, _SECURE_FILE_PATHS_, 'secure')
+
+    # Copy Non-Secure Files
+    for compiler in _COMPILERS_:
+        for arch in _ARCH_NS_:
+            copy_files_for_compiler_and_arch(compiler, arch, _NONSECURE_FILE_PATHS_, 'non_secure')
+
+
+def main():
+    copy_files()
+
+
+if __name__ == '__main__':
+    main()

3rd_party/FreeRTOS/Source/portable/ARMv8M/non_secure/ReadMe.txt

@@ -0,0 +1,11 @@
+This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
+Do not use the files located here!  These file are copied into separate
+FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
+FreeRTOS release.
+
+If your Cortex-M33 application uses TrustZone then use the files from the
+FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
+
+If your Cortex-M33 application does not use TrustZone then use the files from
+the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
+

3rd_party/FreeRTOS/Source/portable/ARMv8M/non_secure/port.c

@@ -0,0 +1,897 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+    /* Secure components includes. */
+    #include "secure_context.h"
+    #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *        configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *        configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *        configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL                ( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD                ( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE        ( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL                    ( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2                    ( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK                ( 0x00000004 )
+#define portNVIC_SYSTICK_INT                ( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE                ( 0x00000001 )
+#define portNVIC_PENDSVSET                    ( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                    ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE            ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR                            ( ( volatile uint32_t * ) 0xe000ed88 )    /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE                ( 3UL )
+#define portCPACR_CP11_VALUE                portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS                    ( 20UL )
+#define portCPACR_CP11_POS                    ( 22UL )
+
+#define portFPCCR                            ( ( volatile uint32_t * ) 0xe000ef34 )    /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS                    ( 31UL )
+#define portFPCCR_ASPEN_MASK                ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS                    ( 30UL )
+#define portFPCCR_LSPEN_MASK                ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG                    ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                    ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                        ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG                    ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                    ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG                    ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                    ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG                    ( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                    ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG                    ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                    ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG                    ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                    ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK            ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK            ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS                ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS                ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS                ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS                ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS                ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS                ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS                ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS                ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0            ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1            ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2            ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3            ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4            ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5            ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6            ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7            ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE        ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE                        ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE            ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR                    ( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
+    #define portINITIAL_EXC_RETURN            ( 0xfffffffd )
+#else
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
+    #define portINITIAL_EXC_RETURN            ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK            ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED        ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS            configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS            prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS                1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT                0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
+    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
+    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
+    volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Stop and reset the SysTick. */
+    *( portNVIC_SYSTICK_CTRL ) = 0UL;
+    *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, then stop here so
+     * application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being
+         * defined but never called.  ulDummy is used purely to quieten other
+         * warnings about code appearing after this function is called - making
+         * ulDummy volatile makes the compiler think the function could return
+         * and therefore not output an 'unreachable code' warning for code that
+         * appears after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+    #if defined( __ARMCC_VERSION )
+        /* Declaration when these variable are defined in code instead of being
+         * exported from linker scripts. */
+        extern uint32_t * __privileged_functions_start__;
+        extern uint32_t * __privileged_functions_end__;
+        extern uint32_t * __syscalls_flash_start__;
+        extern uint32_t * __unprivileged_flash_end__;
+        extern uint32_t * __privileged_sram_start__;
+        extern uint32_t * __privileged_sram_end__;
+    #else
+        /* Declaration when these variable are exported from linker scripts. */
+        extern uint32_t __privileged_functions_start__[];
+        extern uint32_t __privileged_functions_end__[];
+        extern uint32_t __syscalls_flash_start__[];
+        extern uint32_t __unprivileged_flash_end__[];
+        extern uint32_t __privileged_sram_start__[];
+        extern uint32_t __privileged_sram_end__[];
+    #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Check that the MPU is present. */
+        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+        {
+            /* MAIR0 - Index 0. */
+            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+            /* MAIR0 - Index 1. */
+            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+            /* Setup privileged flash as Read Only so that privileged tasks can
+             * read it but not modify. */
+            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG =    ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                                ( portMPU_REGION_NON_SHAREABLE ) |
+                                ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+            portMPU_RLAR_REG =    ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                                ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged flash and system calls flash as Read Only by
+             * both privileged and unprivileged tasks. All tasks can read it but
+             * no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG =    ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                                ( portMPU_REGION_NON_SHAREABLE ) |
+                                ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG =    ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                                ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup RAM containing kernel data for privileged access only. */
+            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+            portMPU_RBAR_REG =    ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                                ( portMPU_REGION_NON_SHAREABLE ) |
+                                ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                                ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG =    ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                                ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                ( portMPU_RLAR_REGION_ENABLE );
+
+            /* By default allow everything to access the general peripherals.
+             * The system peripherals and registers are protected. */
+            portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;
+            portMPU_RBAR_REG =    ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |
+                                ( portMPU_REGION_NON_SHAREABLE ) |
+                                ( portMPU_REGION_READ_WRITE ) |
+                                ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG =    ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |
+                                ( portMPU_RLAR_ATTR_INDEX1 ) |
+                                ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Enable mem fault. */
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+            /* Enable MPU with privileged background access i.e. unmapped
+             * regions have privileged access. */
+            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if( configENABLE_TRUSTZONE == 1 )
+        {
+            /* Enable non-secure access to the FPU. */
+            SecureInit_EnableNSFPUAccess();
+        }
+        #endif /* configENABLE_TRUSTZONE */
+
+        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+         * unprivileged code should be able to access FPU. CP11 should be
+         * programmed to the same value as CP10. */
+        *( portCPACR ) |=    (    ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+                                ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+                            );
+
+        /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+         * context on exception entry and restore on exception return.
+         * LSPEN = 1 ==> Enable lazy context save of FP state. */
+        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+    }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Set a PendSV to request a context switch. */
+    *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile( "dsb" ::: "memory" );
+    __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile( "dsb" ::: "memory" );
+    __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */
+{
+#if( configENABLE_MPU == 1 )
+    #if defined( __ARMCC_VERSION )
+        /* Declaration when these variable are defined in code instead of being
+         * exported from linker scripts. */
+        extern uint32_t * __syscalls_flash_start__;
+        extern uint32_t * __syscalls_flash_end__;
+    #else
+        /* Declaration when these variable are exported from linker scripts. */
+        extern uint32_t __syscalls_flash_start__[];
+        extern uint32_t __syscalls_flash_end__[];
+    #endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+    uint32_t ulR0;
+    #if( configENABLE_MPU == 1 )
+        uint32_t ulControl, ulIsTaskPrivileged;
+    #endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+     * R12, LR, PC, xPSR. */
+    ulPC = pulCallerStackAddress[ 6 ];
+    ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        #if( configENABLE_TRUSTZONE == 1 )
+            case portSVC_ALLOCATE_SECURE_CONTEXT:
+            {
+                /* R0 contains the stack size passed as parameter to the
+                 * vPortAllocateSecureContext function. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                #if( configENABLE_MPU == 1 )
+                {
+                    /* Read the CONTROL register value. */
+                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+                    /* The task that raised the SVC is privileged if Bit[0]
+                     * in the CONTROL register is 0. */
+                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+                    /* Allocate and load a context for the secure task. */
+                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+                }
+                #else
+                {
+                    /* Allocate and load a context for the secure task. */
+                    xSecureContext = SecureContext_AllocateContext( ulR0 );
+                }
+                #endif /* configENABLE_MPU */
+
+                configASSERT( xSecureContext != NULL );
+                SecureContext_LoadContext( xSecureContext );
+            }
+            break;
+
+            case portSVC_FREE_SECURE_CONTEXT:
+            {
+                /* R0 contains the secure context handle to be freed. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                /* Free the secure context. */
+                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+            }
+            break;
+        #endif /* configENABLE_TRUSTZONE */
+
+        case portSVC_START_SCHEDULER:
+        {
+            #if( configENABLE_TRUSTZONE == 1 )
+            {
+                /* De-prioritize the non-secure exceptions so that the
+                 * non-secure pendSV runs at the lowest priority. */
+                SecureInit_DePrioritizeNSExceptions();
+
+                /* Initialize the secure context management system. */
+                SecureContext_Init();
+            }
+            #endif /* configENABLE_TRUSTZONE */
+
+            #if( configENABLE_FPU == 1 )
+            {
+                /* Setup the Floating Point Unit (FPU). */
+                prvSetupFPU();
+            }
+            #endif /* configENABLE_FPU */
+
+            /* Setup the context of the first task so that the first task starts
+             * executing. */
+            vRestoreContextOfFirstTask();
+        }
+        break;
+
+        #if( configENABLE_MPU == 1 )
+            case portSVC_RAISE_PRIVILEGE:
+            {
+                /* Only raise the privilege, if the svc was raised from any of
+                 * the system calls. */
+                if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+                    ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+                {
+                    vRaisePrivilege();
+                }
+            }
+            break;
+        #endif /* configENABLE_MPU */
+
+        default:
+        {
+            /* Incorrect SVC call. */
+            configASSERT( pdFALSE );
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+    StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+    StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    #if( portPRELOAD_REGISTERS == 0 )
+    {
+        pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+        *pxTopOfStack = portINITIAL_XPSR;                            /* xPSR */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pxCode;                        /* PC */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;    /* LR */
+        pxTopOfStack -= 5;                                            /* R12, R3, R2 and R1. */
+        *pxTopOfStack = ( StackType_t ) pvParameters;                /* R0 */
+        pxTopOfStack -= 9;                                            /* R11..R4, EXC_RETURN. */
+        *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+        #if( configENABLE_MPU == 1 )
+        {
+            pxTopOfStack--;
+            if( xRunPrivileged == pdTRUE )
+            {
+                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;        /* Slot used to hold this task's CONTROL value. */
+            }
+            else
+            {
+                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;    /* Slot used to hold this task's CONTROL value. */
+            }
+        }
+        #endif /* configENABLE_MPU */
+
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pxEndOfStack;    /* Slot used to hold this task's PSPLIM value. */
+
+        #if( configENABLE_TRUSTZONE == 1 )
+        {
+            pxTopOfStack--;
+            *pxTopOfStack = portNO_SECURE_CONTEXT;        /* Slot used to hold this task's xSecureContext value. */
+        }
+        #endif /* configENABLE_TRUSTZONE */
+    }
+    #else /* portPRELOAD_REGISTERS */
+    {
+        pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+        *pxTopOfStack = portINITIAL_XPSR;                            /* xPSR */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pxCode;                        /* PC */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;    /* LR */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x12121212UL;                /* R12 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x03030303UL;                /* R3 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x02020202UL;                /* R2 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x01010101UL;                /* R1 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pvParameters;                /* R0 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x11111111UL;                /* R11 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x10101010UL;                /* R10 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x09090909UL;                /* R09 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x08080808UL;                /* R08 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x07070707UL;                /* R07 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x06060606UL;                /* R06 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x05050505UL;                /* R05 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x04040404UL;                /* R04 */
+        pxTopOfStack--;
+        *pxTopOfStack = portINITIAL_EXC_RETURN;                        /* EXC_RETURN */
+
+        #if( configENABLE_MPU == 1 )
+        {
+            pxTopOfStack--;
+            if( xRunPrivileged == pdTRUE )
+            {
+                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;        /* Slot used to hold this task's CONTROL value. */
+            }
+            else
+            {
+                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;    /* Slot used to hold this task's CONTROL value. */
+            }
+        }
+        #endif /* configENABLE_MPU */
+
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pxEndOfStack;    /* Slot used to hold this task's PSPLIM value. */
+
+        #if( configENABLE_TRUSTZONE == 1 )
+        {
+            pxTopOfStack--;
+            *pxTopOfStack = portNO_SECURE_CONTEXT;        /* Slot used to hold this task's xSecureContext value. */
+        }
+        #endif /* configENABLE_TRUSTZONE */
+    }
+    #endif /* portPRELOAD_REGISTERS */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+    *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+    #if( configENABLE_MPU == 1 )
+    {
+        /* Setup the Memory Protection Unit (MPU). */
+        prvSetupMPU();
+    }
+    #endif /* configENABLE_MPU */
+
+    /* Start the timer that generates the tick ISR. Interrupts are disabled
+     * here already. */
+    prvSetupTimerInterrupt();
+
+    /* Initialize the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    /* Start the first task. */
+    vStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing. Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. Call
+     * vTaskSwitchContext() so link time optimization does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here. */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+    {
+    uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+    int32_t lIndex = 0;
+
+        /* Setup MAIR0. */
+        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that
+         * the stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            /* Define the region that allows access to the stack. */
+            ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+            xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =    ( ulRegionStartAddress ) |
+                                                            ( portMPU_REGION_NON_SHAREABLE ) |
+                                                            ( portMPU_REGION_READ_WRITE ) |
+                                                            ( portMPU_REGION_EXECUTE_NEVER );
+
+            xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =    ( ulRegionEndAddress ) |
+                                                            ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                                            ( portMPU_RLAR_REGION_ENABLE );
+        }
+
+        /* User supplied configurable regions. */
+        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+        {
+            /* If xRegions is NULL i.e. the task has not specified any MPU
+             * region, the else part ensures that all the configurable MPU
+             * regions are invalidated. */
+            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+            {
+                /* Translate the generic region definition contained in xRegions
+                 * into the ARMv8 specific MPU settings that are then stored in
+                 * xMPUSettings. */
+                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+                ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+                /* Start address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =    ( ulRegionStartAddress ) |
+                                                                            ( portMPU_REGION_NON_SHAREABLE );
+
+                /* RO/RW. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+                }
+                else
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+                }
+
+                /* XN. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+                }
+
+                /* End Address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =    ( ulRegionEndAddress ) |
+                                                                            ( portMPU_RLAR_REGION_ENABLE );
+
+                /* Normal memory/ Device memory. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+                {
+                    /* Attr1 in MAIR0 is configured as device memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+                }
+                else
+                {
+                    /* Attr1 in MAIR0 is configured as normal memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+                }
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c

@@ -0,0 +1,381 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Portasm includes. */
+#include "portasm.h"
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    .syntax unified                                    \n"
+    "                                                    \n"
+    "    ldr  r2, pxCurrentTCBConst2                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    "    ldr  r3, [r2]                                    \n" /* Read pxCurrentTCB. */
+    "    ldr  r0, [r3]                                    \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    adds r3, #4                                        \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+    "    ldr  r4, [r3]                                    \n" /* r4 = *r3 i.e. r4 = MAIR0. */
+    "    ldr  r2, xMAIR0Const2                            \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+    "    str  r4, [r2]                                    \n" /* Program MAIR0. */
+    "    ldr  r2, xRNRConst2                                \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+    "    movs r4, #4                                        \n" /* r4 = 4. */
+    "    str  r4, [r2]                                    \n" /* Program RNR = 4. */
+    "    adds r3, #4                                        \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+    "    ldr  r2, xRBARConst2                            \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+    "    ldmia r3!, {r4-r11}                                \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+    "    stmia r2!, {r4-r11}                                \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    ldm  r0!, {r1-r4}                                \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+    "    ldr  r5, xSecureContextConst2                    \n"
+    "    str  r1, [r5]                                    \n" /* Set xSecureContext to this task's value for the same. */
+    "    msr  psplim, r2                                    \n" /* Set this task's PSPLIM value. */
+    "    msr  control, r3                                \n" /* Set this task's CONTROL value. */
+    "    adds r0, #32                                    \n" /* Discard everything up to r0. */
+    "    msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+    "    isb                                                \n"
+    "    bx   r4                                            \n" /* Finally, branch to EXC_RETURN. */
+    #else /* configENABLE_MPU */
+    "    ldm  r0!, {r1-r3}                                \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+    "    ldr  r4, xSecureContextConst2                    \n"
+    "    str  r1, [r4]                                    \n" /* Set xSecureContext to this task's value for the same. */
+    "    msr  psplim, r2                                    \n" /* Set this task's PSPLIM value. */
+    "    movs r1, #2                                        \n" /* r1 = 2. */
+    "    msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+    "    adds r0, #32                                    \n" /* Discard everything up to r0. */
+    "    msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+    "    isb                                                \n"
+    "    bx   r3                                            \n" /* Finally, branch to EXC_RETURN. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    "    .align 4                                        \n"
+    "pxCurrentTCBConst2: .word pxCurrentTCB                \n"
+    "xSecureContextConst2: .word xSecureContext            \n"
+    #if( configENABLE_MPU == 1 )
+    "xMAIR0Const2: .word 0xe000edc0                        \n"
+    "xRNRConst2: .word 0xe000ed98                        \n"
+    "xRBARConst2: .word 0xe000ed9c                        \n"
+    #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+    "    mrs r0, control                                    \n" /* r0 = CONTROL. */
+    "    tst r0, #1                                        \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+    "    ite ne                                            \n"
+    "    movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+    "    moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+    "    bx lr                                            \n" /* Return. */
+    "                                                    \n"
+    "    .align 4                                        \n"
+    ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+     __asm volatile
+    (
+    "    mrs r0, control                                    \n" /* Read the CONTROL register. */
+    "    bic r0, #1                                        \n" /* Clear the bit 0. */
+    "    msr control, r0                                    \n" /* Write back the new CONTROL value. */
+    "    bx lr                                            \n" /* Return to the caller. */
+    ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+    "    mrs r0, control                                    \n" /* r0 = CONTROL. */
+    "    orr r0, #1                                        \n" /* r0 = r0 | 1. */
+    "    msr control, r0                                    \n" /* CONTROL = r0. */
+    "    bx lr                                            \n" /* Return to the caller. */
+    :::"r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    ldr r0, xVTORConst                                \n" /* Use the NVIC offset register to locate the stack. */
+    "    ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+    "    ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+    "    msr msp, r0                                        \n" /* Set the MSP back to the start of the stack. */
+    "    cpsie i                                            \n" /* Globally enable interrupts. */
+    "    cpsie f                                            \n"
+    "    dsb                                                \n"
+    "    isb                                                \n"
+    "    svc %0                                            \n" /* System call to start the first task. */
+    "    nop                                                \n"
+    "                                                    \n"
+    "   .align 4                                        \n"
+    "xVTORConst: .word 0xe000ed08                        \n"
+    :: "i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    mrs r0, PRIMASK                                    \n"
+    "    cpsid i                                            \n"
+    "    bx lr                                            \n"
+    ::: "memory"
+    );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+    /* To avoid compiler warnings.  The return statement will never be reached,
+     * but some compilers warn if it is not included, while others won't compile
+     * if it is. */
+    return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    msr PRIMASK, r0                                    \n"
+    "    bx lr                                            \n"
+    ::: "memory"
+    );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+    /* Just to avoid compiler warning.  ulMask is used from the asm code but
+     * the compiler can't see that.  Some compilers generate warnings without
+     * the following line, while others generate warnings if the line is
+     * included. */
+    ( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    .syntax unified                                    \n"
+    "    .extern SecureContext_SaveContext                \n"
+    "    .extern SecureContext_LoadContext                \n"
+    "                                                    \n"
+    "    mrs r1, psp                                        \n" /* Read PSP in r1. */
+    "    ldr r2, xSecureContextConst                        \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+    "    ldr r0, [r2]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+    "                                                    \n"
+    "    cbz r0, save_ns_context                            \n" /* No secure context to save. */
+    "    push {r0-r2, r14}                                \n"
+    "    bl SecureContext_SaveContext                    \n"
+    "    pop {r0-r3}                                        \n" /* LR is now in r3. */
+    "    mov lr, r3                                        \n" /* LR = r3. */
+    "    lsls r2, r3, #25                                \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+    "    bpl save_ns_context                                \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+    "    ldr r3, pxCurrentTCBConst                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    "    ldr r2, [r3]                                    \n" /* Read pxCurrentTCB. */
+    #if( configENABLE_MPU == 1 )
+    "    subs r1, r1, #16                                \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+    "    str r1, [r2]                                    \n" /* Save the new top of stack in TCB. */
+    "    mrs r2, psplim                                    \n" /* r2 = PSPLIM. */
+    "    mrs r3, control                                    \n" /* r3 = CONTROL. */
+    "    mov r4, lr                                        \n" /* r4 = LR/EXC_RETURN. */
+    "    stmia r1!, {r0, r2-r4}                            \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+    #else /* configENABLE_MPU */
+    "    subs r1, r1, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+    "    str r1, [r2]                                    \n" /* Save the new top of stack in TCB. */
+    "    mrs r2, psplim                                    \n" /* r2 = PSPLIM. */
+    "    mov r3, lr                                        \n" /* r3 = LR/EXC_RETURN. */
+    "    stmia r1!, {r0, r2-r3}                            \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+    #endif /* configENABLE_MPU */
+    "    b select_next_task                                \n"
+    "                                                    \n"
+    " save_ns_context:                                    \n"
+    "    ldr r3, pxCurrentTCBConst                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    "    ldr r2, [r3]                                    \n" /* Read pxCurrentTCB. */
+    #if( configENABLE_FPU == 1 )
+    "    tst lr, #0x10                                    \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+    "    it eq                                            \n"
+    "    vstmdbeq r1!, {s16-s31}                            \n" /* Store the FPU registers which are not saved automatically. */
+    #endif /* configENABLE_FPU */
+    #if( configENABLE_MPU == 1 )
+    "    subs r1, r1, #48                                \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+    "    str r1, [r2]                                    \n" /* Save the new top of stack in TCB. */
+    "    adds r1, r1, #16                                \n" /* r1 = r1 + 16. */
+    "    stm r1, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
+    "    mrs r2, psplim                                    \n" /* r2 = PSPLIM. */
+    "    mrs r3, control                                    \n" /* r3 = CONTROL. */
+    "    mov r4, lr                                        \n" /* r4 = LR/EXC_RETURN. */
+    "    subs r1, r1, #16                                \n" /* r1 = r1 - 16. */
+    "    stm r1, {r0, r2-r4}                                \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+    #else /* configENABLE_MPU */
+    "    subs r1, r1, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+    "    str r1, [r2]                                    \n" /* Save the new top of stack in TCB. */
+    "    adds r1, r1, #12                                \n" /* r1 = r1 + 12. */
+    "    stm r1, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
+    "    mrs r2, psplim                                    \n" /* r2 = PSPLIM. */
+    "    mov r3, lr                                        \n" /* r3 = LR/EXC_RETURN. */
+    "    subs r1, r1, #12                                \n" /* r1 = r1 - 12. */
+    "    stmia r1!, {r0, r2-r3}                            \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    " select_next_task:                                    \n"
+    "    cpsid i                                            \n"
+    "    bl vTaskSwitchContext                            \n"
+    "    cpsie i                                            \n"
+    "                                                    \n"
+    "    ldr r2, pxCurrentTCBConst                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    "    ldr r3, [r2]                                    \n" /* Read pxCurrentTCB. */
+    "    ldr r1, [r3]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    adds r3, #4                                        \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+    "    ldr r4, [r3]                                    \n" /* r4 = *r3 i.e. r4 = MAIR0. */
+    "    ldr r2, xMAIR0Const                                \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+    "    str r4, [r2]                                    \n" /* Program MAIR0. */
+    "    ldr r2, xRNRConst                                \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+    "    movs r4, #4                                        \n" /* r4 = 4. */
+    "    str r4, [r2]                                    \n" /* Program RNR = 4. */
+    "    adds r3, #4                                        \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+    "    ldr  r2, xRBARConst                                \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+    "    ldmia r3!, {r4-r11}                                \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+    "    stmia r2!, {r4-r11}                                \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    ldmia r1!, {r0, r2-r4}                            \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+    "    msr psplim, r2                                    \n" /* Restore the PSPLIM register value for the task. */
+    "    msr control, r3                                    \n" /* Restore the CONTROL register value for the task. */
+    "    mov lr, r4                                        \n" /* LR = r4. */
+    "    ldr r2, xSecureContextConst                        \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+    "    str r0, [r2]                                    \n" /* Restore the task's xSecureContext. */
+    "    cbz r0, restore_ns_context                        \n" /* If there is no secure context for the task, restore the non-secure context. */
+    "    push {r1,r4}                                    \n"
+    "    bl SecureContext_LoadContext                    \n" /* Restore the secure context. */
+    "    pop {r1,r4}                                        \n"
+    "    mov lr, r4                                        \n" /* LR = r4. */
+    "    lsls r2, r4, #25                                \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+    "    bpl restore_ns_context                            \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+    "    msr psp, r1                                        \n" /* Remember the new top of stack for the task. */
+    "    bx lr                                            \n"
+    #else /* configENABLE_MPU */
+    "    ldmia r1!, {r0, r2-r3}                            \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+    "    msr psplim, r2                                    \n" /* Restore the PSPLIM register value for the task. */
+    "    mov lr, r3                                        \n" /* LR = r3. */
+    "    ldr r2, xSecureContextConst                        \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+    "    str r0, [r2]                                    \n" /* Restore the task's xSecureContext. */
+    "    cbz r0, restore_ns_context                        \n" /* If there is no secure context for the task, restore the non-secure context. */
+    "    push {r1,r3}                                    \n"
+    "    bl SecureContext_LoadContext                    \n" /* Restore the secure context. */
+    "    pop {r1,r3}                                        \n"
+    "    mov lr, r3                                        \n" /* LR = r3. */
+    "    lsls r2, r3, #25                                \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+    "    bpl restore_ns_context                            \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+    "    msr psp, r1                                        \n" /* Remember the new top of stack for the task. */
+    "    bx lr                                            \n"
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    " restore_ns_context:                                \n"
+    "    ldmia r1!, {r4-r11}                                \n" /* Restore the registers that are not automatically restored. */
+    #if( configENABLE_FPU == 1 )
+    "    tst lr, #0x10                                    \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+    "    it eq                                            \n"
+    "    vldmiaeq r1!, {s16-s31}                            \n" /* Restore the FPU registers which are not restored automatically. */
+    #endif /* configENABLE_FPU */
+    "    msr psp, r1                                        \n" /* Remember the new top of stack for the task. */
+    "    bx lr                                            \n"
+    "                                                    \n"
+    "    .align 4                                        \n"
+    "pxCurrentTCBConst: .word pxCurrentTCB                \n"
+    "xSecureContextConst: .word xSecureContext            \n"
+    #if( configENABLE_MPU == 1 )
+    "xMAIR0Const: .word 0xe000edc0                        \n"
+    "xRNRConst: .word 0xe000ed98                        \n"
+    "xRBARConst: .word 0xe000ed9c                        \n"
+    #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    tst lr, #4                                        \n"
+    "    ite eq                                            \n"
+    "    mrseq r0, msp                                    \n"
+    "    mrsne r0, psp                                    \n"
+    "    ldr r1, svchandler_address_const                \n"
+    "    bx r1                                            \n"
+    "                                                    \n"
+    "    .align 4                                        \n"
+    "svchandler_address_const: .word vPortSVCHandler_C    \n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+    "    svc %0                                            \n" /* Secure context is allocated in the supervisor call. */
+    "    bx lr                                            \n" /* Return. */
+    :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    ldr r1, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
+    "    ldr r0, [r1]                                    \n" /* The first item on the stack is the task's xSecureContext. */
+    "    cmp r0, #0                                        \n" /* Raise svc if task's xSecureContext is not NULL. */
+    "    it ne                                            \n"
+    "    svcne %0                                        \n" /* Secure context is freed in the supervisor call. */
+    "    bx lr                                            \n" /* Return. */
+    :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c

@@ -0,0 +1,285 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Portasm includes. */
+#include "portasm.h"
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    .syntax unified                                    \n"
+    "                                                    \n"
+    "    ldr  r2, pxCurrentTCBConst2                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    "    ldr  r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+    "    ldr  r0, [r1]                                    \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    adds r1, #4                                        \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+    "    ldr  r3, [r1]                                    \n" /* r3 = *r1 i.e. r3 = MAIR0. */
+    "    ldr  r2, xMAIR0Const2                            \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+    "    str  r3, [r2]                                    \n" /* Program MAIR0. */
+    "    ldr  r2, xRNRConst2                                \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+    "    movs r3, #4                                        \n" /* r3 = 4. */
+    "    str  r3, [r2]                                    \n" /* Program RNR = 4. */
+    "    adds r1, #4                                        \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+    "    ldr  r2, xRBARConst2                            \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+    "    ldmia r1!, {r4-r11}                                \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+    "    stmia r2!, {r4-r11}                                \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    ldm  r0!, {r1-r3}                                \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+    "    msr  psplim, r1                                    \n" /* Set this task's PSPLIM value. */
+    "    msr  control, r2                                \n" /* Set this task's CONTROL value. */
+    "    adds r0, #32                                    \n" /* Discard everything up to r0. */
+    "    msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+    "    isb                                                \n"
+    "    bx   r3                                            \n" /* Finally, branch to EXC_RETURN. */
+    #else /* configENABLE_MPU */
+    "    ldm  r0!, {r1-r2}                                \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+    "    msr  psplim, r1                                    \n" /* Set this task's PSPLIM value. */
+    "    movs r1, #2                                        \n" /* r1 = 2. */
+    "    msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+    "    adds r0, #32                                    \n" /* Discard everything up to r0. */
+    "    msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+    "    isb                                                \n"
+    "    bx   r2                                            \n" /* Finally, branch to EXC_RETURN. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    "    .align 4                                        \n"
+    "pxCurrentTCBConst2: .word pxCurrentTCB                \n"
+    #if( configENABLE_MPU == 1 )
+    "xMAIR0Const2: .word 0xe000edc0                        \n"
+    "xRNRConst2: .word 0xe000ed98                        \n"
+    "xRBARConst2: .word 0xe000ed9c                        \n"
+    #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+    "    mrs r0, control                                    \n" /* r0 = CONTROL. */
+    "    tst r0, #1                                        \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+    "    ite ne                                            \n"
+    "    movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+    "    moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+    "    bx lr                                            \n" /* Return. */
+    "                                                    \n"
+    "    .align 4                                        \n"
+    ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+     __asm volatile
+    (
+    "    mrs  r0, control                                \n" /* Read the CONTROL register. */
+    "    bic r0, #1                                        \n" /* Clear the bit 0. */
+    "    msr  control, r0                                \n" /* Write back the new CONTROL value. */
+    "    bx lr                                            \n" /* Return to the caller. */
+    ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+    "    mrs r0, control                                    \n" /* r0 = CONTROL. */
+    "    orr r0, #1                                        \n" /* r0 = r0 | 1. */
+    "    msr control, r0                                    \n" /* CONTROL = r0. */
+    "    bx lr                                            \n" /* Return to the caller. */
+    :::"r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    ldr r0, xVTORConst                                \n" /* Use the NVIC offset register to locate the stack. */
+    "    ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+    "    ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+    "    msr msp, r0                                        \n" /* Set the MSP back to the start of the stack. */
+    "    cpsie i                                            \n" /* Globally enable interrupts. */
+    "    cpsie f                                            \n"
+    "    dsb                                                \n"
+    "    isb                                                \n"
+    "    svc %0                                            \n" /* System call to start the first task. */
+    "    nop                                                \n"
+    "                                                    \n"
+    "   .align 4                                        \n"
+    "xVTORConst: .word 0xe000ed08                        \n"
+    :: "i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    mrs r0, PRIMASK                                    \n"
+    "    cpsid i                                            \n"
+    "    bx lr                                            \n"
+    ::: "memory"
+    );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+    /* To avoid compiler warnings.  The return statement will never be reached,
+     * but some compilers warn if it is not included, while others won't compile
+     * if it is. */
+    return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    msr PRIMASK, r0                                    \n"
+    "    bx lr                                            \n"
+    ::: "memory"
+    );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+    /* Just to avoid compiler warning.  ulMask is used from the asm code but
+     * the compiler can't see that.  Some compilers generate warnings without
+     * the following line, while others generate warnings if the line is
+     * included. */
+    ( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    .syntax unified                                    \n"
+    "                                                    \n"
+    "    mrs r0, psp                                        \n" /* Read PSP in r0. */
+    #if( configENABLE_FPU == 1 )
+    "    tst lr, #0x10                                    \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+    "    it eq                                            \n"
+    "    vstmdbeq r0!, {s16-s31}                            \n" /* Store the FPU registers which are not saved automatically. */
+    #endif /* configENABLE_FPU */
+    #if( configENABLE_MPU == 1 )
+    "    mrs r1, psplim                                    \n" /* r1 = PSPLIM. */
+    "    mrs r2, control                                    \n" /* r2 = CONTROL. */
+    "    mov r3, lr                                        \n" /* r3 = LR/EXC_RETURN. */
+    "    stmdb r0!, {r1-r11}                                \n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+    #else /* configENABLE_MPU */
+    "    mrs r2, psplim                                    \n" /* r2 = PSPLIM. */
+    "    mov r3, lr                                        \n" /* r3 = LR/EXC_RETURN. */
+    "    stmdb r0!, {r2-r11}                                \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    "    ldr r2, pxCurrentTCBConst                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    "    ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+    "    str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
+    "                                                    \n"
+    "    cpsid i                                            \n"
+    "    bl vTaskSwitchContext                            \n"
+    "    cpsie i                                            \n"
+    "                                                    \n"
+    "    ldr r2, pxCurrentTCBConst                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    "    ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+    "    ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    adds r1, #4                                        \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+    "    ldr r3, [r1]                                    \n" /* r3 = *r1 i.e. r3 = MAIR0. */
+    "    ldr r2, xMAIR0Const                                \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+    "    str r3, [r2]                                    \n" /* Program MAIR0. */
+    "    ldr r2, xRNRConst                                \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+    "    movs r3, #4                                        \n" /* r3 = 4. */
+    "    str r3, [r2]                                    \n" /* Program RNR = 4. */
+    "    adds r1, #4                                        \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+    "    ldr r2, xRBARConst                                \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+    "    ldmia r1!, {r4-r11}                                \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+    "    stmia r2!, {r4-r11}                                \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    ldmia r0!, {r1-r11}                                \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+    #else /* configENABLE_MPU */
+    "    ldmia r0!, {r2-r11}                                \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    #if( configENABLE_FPU == 1 )
+    "    tst r3, #0x10                                    \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+    "    it eq                                            \n"
+    "    vldmiaeq r0!, {s16-s31}                            \n" /* Restore the FPU registers which are not restored automatically. */
+    #endif /* configENABLE_FPU */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    msr psplim, r1                                    \n" /* Restore the PSPLIM register value for the task. */
+    "    msr control, r2                                    \n" /* Restore the CONTROL register value for the task. */
+    #else /* configENABLE_MPU */
+    "    msr psplim, r2                                    \n" /* Restore the PSPLIM register value for the task. */
+    #endif /* configENABLE_MPU */
+    "    msr psp, r0                                        \n" /* Remember the new top of stack for the task. */
+    "    bx r3                                            \n"
+    "                                                    \n"
+    "    .align 4                                        \n"
+    "pxCurrentTCBConst: .word pxCurrentTCB                \n"
+    "xMAIR0Const: .word 0xe000edc0                        \n"
+    "xRNRConst: .word 0xe000ed98                        \n"
+    "xRBARConst: .word 0xe000ed9c                        \n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "     tst lr, #4                                        \n"
+    "     ite eq                                            \n"
+    "     mrseq r0, msp                                    \n"
+    "     mrsne r0, psp                                    \n"
+    "     ldr r1, svchandler_address_const                \n"
+    "     bx r1                                            \n"
+    "                                                    \n"
+    "     .align 4                                        \n"
+    "svchandler_address_const: .word vPortSVCHandler_C    \n"
+    );
+}
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s

@@ -0,0 +1,302 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+    EXTERN pxCurrentTCB
+    EXTERN xSecureContext
+    EXTERN vTaskSwitchContext
+    EXTERN vPortSVCHandler_C
+    EXTERN SecureContext_SaveContext
+    EXTERN SecureContext_LoadContext
+
+    PUBLIC xIsPrivileged
+    PUBLIC vResetPrivilege
+    PUBLIC vPortAllocateSecureContext
+    PUBLIC vRestoreContextOfFirstTask
+    PUBLIC vRaisePrivilege
+    PUBLIC vStartFirstTask
+    PUBLIC ulSetInterruptMaskFromISR
+    PUBLIC vClearInterruptMaskFromISR
+    PUBLIC PendSV_Handler
+    PUBLIC SVC_Handler
+    PUBLIC vPortFreeSecureContext
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+    SECTION .text:CODE:NOROOT(2)
+    THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+    mrs r0, control                            /* r0 = CONTROL. */
+    tst r0, #1                                /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+    ite ne
+    movne r0, #0                            /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+    moveq r0, #1                            /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+    bx lr                                    /* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+    mrs r0, control                            /* r0 = CONTROL. */
+    orr r0, r0, #1                            /* r0 = r0 | 1. */
+    msr control, r0                            /* CONTROL = r0. */
+    bx lr                                    /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vPortAllocateSecureContext:
+    svc 0                                    /* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+    bx lr                                    /* Return. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+    SECTION privileged_functions:CODE:NOROOT(2)
+    THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+    ldr  r2, =pxCurrentTCB                    /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    ldr  r3, [r2]                            /* Read pxCurrentTCB. */
+    ldr  r0, [r3]                            /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+    adds r3, #4                                /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+    ldr  r4, [r3]                            /* r4 = *r3 i.e. r4 = MAIR0. */
+    ldr  r2, =0xe000edc0                    /* r2 = 0xe000edc0 [Location of MAIR0]. */
+    str  r4, [r2]                            /* Program MAIR0. */
+    ldr  r2, =0xe000ed98                    /* r2 = 0xe000ed98 [Location of RNR]. */
+    movs r4, #4                                /* r4 = 4. */
+    str  r4, [r2]                            /* Program RNR = 4. */
+    adds r3, #4                                /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+    ldr  r2, =0xe000ed9c                    /* r2 = 0xe000ed9c [Location of RBAR]. */
+    ldmia r3!, {r4-r11}                        /* Read 4 set of RBAR/RLAR registers from TCB. */
+    stmia r2!, {r4-r11}                        /* Write 4 set of RBAR/RLAR registers using alias registers. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+    ldm  r0!, {r1-r4}                        /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+    ldr  r5, =xSecureContext
+    str  r1, [r5]                            /* Set xSecureContext to this task's value for the same. */
+    msr  psplim, r2                            /* Set this task's PSPLIM value. */
+    msr  control, r3                        /* Set this task's CONTROL value. */
+    adds r0, #32                            /* Discard everything up to r0. */
+    msr  psp, r0                            /* This is now the new top of stack to use in the task. */
+    isb
+    bx   r4                                    /* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+    ldm  r0!, {r1-r3}                        /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+    ldr  r4, =xSecureContext
+    str  r1, [r4]                            /* Set xSecureContext to this task's value for the same. */
+    msr  psplim, r2                            /* Set this task's PSPLIM value. */
+    movs r1, #2                                /* r1 = 2. */
+    msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
+    adds r0, #32                            /* Discard everything up to r0. */
+    msr  psp, r0                            /* This is now the new top of stack to use in the task. */
+    isb
+    bx   r3                                    /* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+    mrs  r0, control                        /* Read the CONTROL register. */
+    bic r0, r0, #1                            /* Clear the bit 0. */
+    msr  control, r0                        /* Write back the new CONTROL value. */
+    bx lr                                    /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+    ldr r0, =0xe000ed08                        /* Use the NVIC offset register to locate the stack. */
+    ldr r0, [r0]                            /* Read the VTOR register which gives the address of vector table. */
+    ldr r0, [r0]                            /* The first entry in vector table is stack pointer. */
+    msr msp, r0                                /* Set the MSP back to the start of the stack. */
+    cpsie i                                    /* Globally enable interrupts. */
+    cpsie f
+    dsb
+    isb
+    svc 2                                    /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+    mrs r0, PRIMASK
+    cpsid i
+    bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+    msr PRIMASK, r0
+    bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+    mrs r1, psp                                /* Read PSP in r1. */
+    ldr r2, =xSecureContext                    /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+    ldr r0, [r2]                            /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+
+    cbz r0, save_ns_context                    /* No secure context to save. */
+    push {r0-r2, r14}
+    bl SecureContext_SaveContext
+    pop {r0-r3}                                /* LR is now in r3. */
+    mov lr, r3                                /* LR = r3. */
+    lsls r2, r3, #25                        /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+    bpl save_ns_context                        /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+    ldr r3, =pxCurrentTCB                    /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    ldr r2, [r3]                            /* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+    subs r1, r1, #16                        /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+    str r1, [r2]                            /* Save the new top of stack in TCB. */
+    mrs r2, psplim                            /* r2 = PSPLIM. */
+    mrs r3, control                            /* r3 = CONTROL. */
+    mov r4, lr                                /* r4 = LR/EXC_RETURN. */
+    stmia r1!, {r0, r2-r4}                    /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+#else /* configENABLE_MPU */
+    subs r1, r1, #12                        /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+    str r1, [r2]                            /* Save the new top of stack in TCB. */
+    mrs r2, psplim                            /* r2 = PSPLIM. */
+    mov r3, lr                                /* r3 = LR/EXC_RETURN. */
+    stmia r1!, {r0, r2-r3}                    /* Store xSecureContext, PSPLIM and LR on the stack. */
+#endif /* configENABLE_MPU */
+    b select_next_task
+
+    save_ns_context:
+        ldr r3, =pxCurrentTCB                /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        ldr r2, [r3]                        /* Read pxCurrentTCB. */
+    #if ( configENABLE_FPU == 1 )
+        tst lr, #0x10                        /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+        it eq
+        vstmdbeq r1!, {s16-s31}                /* Store the FPU registers which are not saved automatically. */
+    #endif /* configENABLE_FPU */
+    #if ( configENABLE_MPU == 1 )
+        subs r1, r1, #48                    /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+        str r1, [r2]                        /* Save the new top of stack in TCB. */
+        adds r1, r1, #16                    /* r1 = r1 + 16. */
+        stm r1, {r4-r11}                    /* Store the registers that are not saved automatically. */
+        mrs r2, psplim                        /* r2 = PSPLIM. */
+        mrs r3, control                        /* r3 = CONTROL. */
+        mov r4, lr                            /* r4 = LR/EXC_RETURN. */
+        subs r1, r1, #16                    /* r1 = r1 - 16. */
+        stm r1, {r0, r2-r4}                    /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+    #else /* configENABLE_MPU */
+        subs r1, r1, #44                    /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+        str r1, [r2]                        /* Save the new top of stack in TCB. */
+        adds r1, r1, #12                    /* r1 = r1 + 12. */
+        stm r1, {r4-r11}                    /* Store the registers that are not saved automatically. */
+        mrs r2, psplim                        /* r2 = PSPLIM. */
+        mov r3, lr                            /* r3 = LR/EXC_RETURN. */
+        subs r1, r1, #12                    /* r1 = r1 - 12. */
+        stmia r1!, {r0, r2-r3}                /* Store xSecureContext, PSPLIM and LR on the stack. */
+    #endif /* configENABLE_MPU */
+
+    select_next_task:
+        cpsid i
+        bl vTaskSwitchContext
+        cpsie i
+
+        ldr r2, =pxCurrentTCB                /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        ldr r3, [r2]                        /* Read pxCurrentTCB. */
+        ldr r1, [r3]                        /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+
+    #if ( configENABLE_MPU == 1 )
+        adds r3, #4                            /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+        ldr r4, [r3]                        /* r4 = *r3 i.e. r4 = MAIR0. */
+        ldr r2, =0xe000edc0                    /* r2 = 0xe000edc0 [Location of MAIR0]. */
+        str r4, [r2]                        /* Program MAIR0. */
+        ldr r2, =0xe000ed98                    /* r2 = 0xe000ed98 [Location of RNR]. */
+        movs r4, #4                            /* r4 = 4. */
+        str r4, [r2]                        /* Program RNR = 4. */
+        adds r3, #4                            /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+        ldr  r2, =0xe000ed9c                /* r2 = 0xe000ed9c [Location of RBAR]. */
+        ldmia r3!, {r4-r11}                    /* Read 4 sets of RBAR/RLAR registers from TCB. */
+        stmia r2!, {r4-r11}                    /* Write 4 set of RBAR/RLAR registers using alias registers. */
+    #endif /* configENABLE_MPU */
+
+    #if ( configENABLE_MPU == 1 )
+        ldmia r1!, {r0, r2-r4}                /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+        msr psplim, r2                        /* Restore the PSPLIM register value for the task. */
+        msr control, r3                        /* Restore the CONTROL register value for the task. */
+        mov lr, r4                            /* LR = r4. */
+        ldr r2, =xSecureContext                /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+        str r0, [r2]                        /* Restore the task's xSecureContext. */
+        cbz r0, restore_ns_context            /* If there is no secure context for the task, restore the non-secure context. */
+        push {r1,r4}
+        bl SecureContext_LoadContext        /* Restore the secure context. */
+        pop {r1,r4}
+        mov lr, r4                            /* LR = r4. */
+        lsls r2, r4, #25                    /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        bpl restore_ns_context                /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+        msr psp, r1                            /* Remember the new top of stack for the task. */
+        bx lr
+    #else /* configENABLE_MPU */
+        ldmia r1!, {r0, r2-r3}                /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+        msr psplim, r2                        /* Restore the PSPLIM register value for the task. */
+        mov lr, r3                            /* LR = r3. */
+        ldr r2, =xSecureContext                /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+        str r0, [r2]                        /* Restore the task's xSecureContext. */
+        cbz r0, restore_ns_context            /* If there is no secure context for the task, restore the non-secure context. */
+        push {r1,r3}
+        bl SecureContext_LoadContext        /* Restore the secure context. */
+        pop {r1,r3}
+        mov lr, r3                            /* LR = r3. */
+        lsls r2, r3, #25                    /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        bpl restore_ns_context                /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+        msr psp, r1                            /* Remember the new top of stack for the task. */
+        bx lr
+    #endif /* configENABLE_MPU */
+
+    restore_ns_context:
+        ldmia r1!, {r4-r11}                    /* Restore the registers that are not automatically restored. */
+    #if ( configENABLE_FPU == 1 )
+        tst lr, #0x10                        /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+        it eq
+        vldmiaeq r1!, {s16-s31}                /* Restore the FPU registers which are not restored automatically. */
+    #endif /* configENABLE_FPU */
+        msr psp, r1                            /* Remember the new top of stack for the task. */
+        bx lr
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+    tst lr, #4
+    ite eq
+    mrseq r0, msp
+    mrsne r0, psp
+    b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+vPortFreeSecureContext:
+    /* r0 = uint32_t *pulTCB. */
+    ldr r1, [r0]                            /* The first item in the TCB is the top of the stack. */
+    ldr r0, [r1]                            /* The first item on the stack is the task's xSecureContext. */
+    cmp r0, #0                                /* Raise svc if task's xSecureContext is not NULL. */
+    it ne
+    svcne 1                                    /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+    bx lr                                    /* Return. */
+/*-----------------------------------------------------------*/
+
+    END

3rd_party/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s

@@ -0,0 +1,218 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+    EXTERN pxCurrentTCB
+    EXTERN vTaskSwitchContext
+    EXTERN vPortSVCHandler_C
+
+    PUBLIC xIsPrivileged
+    PUBLIC vResetPrivilege
+    PUBLIC vRestoreContextOfFirstTask
+    PUBLIC vRaisePrivilege
+    PUBLIC vStartFirstTask
+    PUBLIC ulSetInterruptMaskFromISR
+    PUBLIC vClearInterruptMaskFromISR
+    PUBLIC PendSV_Handler
+    PUBLIC SVC_Handler
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+    SECTION .text:CODE:NOROOT(2)
+    THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+    mrs r0, control                            /* r0 = CONTROL. */
+    tst r0, #1                                /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+    ite ne
+    movne r0, #0                            /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+    moveq r0, #1                            /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+    bx lr                                    /* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+    mrs r0, control                            /* r0 = CONTROL. */
+    orr r0, r0, #1                            /* r0 = r0 | 1. */
+    msr control, r0                            /* CONTROL = r0. */
+    bx lr                                    /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+    SECTION privileged_functions:CODE:NOROOT(2)
+    THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+    ldr  r2, =pxCurrentTCB                    /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    ldr  r1, [r2]                            /* Read pxCurrentTCB. */
+    ldr  r0, [r1]                            /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+    adds r1, #4                                /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+    ldr r3, [r1]                            /* r3 = *r1 i.e. r3 = MAIR0. */
+    ldr r2, =0xe000edc0                        /* r2 = 0xe000edc0 [Location of MAIR0]. */
+    str r3, [r2]                            /* Program MAIR0. */
+    ldr r2, =0xe000ed98                        /* r2 = 0xe000ed98 [Location of RNR]. */
+    movs r3, #4                                /* r3 = 4. */
+    str r3, [r2]                            /* Program RNR = 4. */
+    adds r1, #4                                /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+    ldr r2, =0xe000ed9c                        /* r2 = 0xe000ed9c [Location of RBAR]. */
+    ldmia r1!, {r4-r11}                        /* Read 4 sets of RBAR/RLAR registers from TCB. */
+    stmia r2!, {r4-r11}                        /* Write 4 set of RBAR/RLAR registers using alias registers. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+    ldm  r0!, {r1-r3}                        /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+    msr  psplim, r1                            /* Set this task's PSPLIM value. */
+    msr  control, r2                        /* Set this task's CONTROL value. */
+    adds r0, #32                            /* Discard everything up to r0. */
+    msr  psp, r0                            /* This is now the new top of stack to use in the task. */
+    isb
+    bx   r3                                    /* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+    ldm  r0!, {r1-r2}                        /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+    msr  psplim, r1                            /* Set this task's PSPLIM value. */
+    movs r1, #2                                /* r1 = 2. */
+    msr  CONTROL, r1                        /* Switch to use PSP in the thread mode. */
+    adds r0, #32                            /* Discard everything up to r0. */
+    msr  psp, r0                            /* This is now the new top of stack to use in the task. */
+    isb
+    bx   r2                                    /* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+    mrs  r0, control                        /* Read the CONTROL register. */
+    bic r0, r0, #1                            /* Clear the bit 0. */
+    msr  control, r0                        /* Write back the new CONTROL value. */
+    bx lr                                    /* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+    ldr r0, =0xe000ed08                        /* Use the NVIC offset register to locate the stack. */
+    ldr r0, [r0]                            /* Read the VTOR register which gives the address of vector table. */
+    ldr r0, [r0]                            /* The first entry in vector table is stack pointer. */
+    msr msp, r0                                /* Set the MSP back to the start of the stack. */
+    cpsie i                                    /* Globally enable interrupts. */
+    cpsie f
+    dsb
+    isb
+    svc 2                                    /* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR:
+    mrs r0, PRIMASK
+    cpsid i
+    bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR:
+    msr PRIMASK, r0
+    bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+    mrs r0, psp                                /* Read PSP in r0. */
+#if ( configENABLE_FPU == 1 )
+    tst lr, #0x10                            /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+    it eq
+    vstmdbeq r0!, {s16-s31}                    /* Store the FPU registers which are not saved automatically. */
+#endif /* configENABLE_FPU */
+#if ( configENABLE_MPU == 1 )
+    mrs r1, psplim                            /* r1 = PSPLIM. */
+    mrs r2, control                            /* r2 = CONTROL. */
+    mov r3, lr                                /* r3 = LR/EXC_RETURN. */
+    stmdb r0!, {r1-r11}                        /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+#else /* configENABLE_MPU */
+    mrs r2, psplim                            /* r2 = PSPLIM. */
+    mov r3, lr                                /* r3 = LR/EXC_RETURN. */
+    stmdb r0!, {r2-r11}                        /* Store on the stack - PSPLIM, LR and registers that are not automatically. */
+#endif /* configENABLE_MPU */
+
+    ldr r2, =pxCurrentTCB                    /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    ldr r1, [r2]                            /* Read pxCurrentTCB. */
+    str r0, [r1]                            /* Save the new top of stack in TCB. */
+
+    cpsid i
+    bl vTaskSwitchContext
+    cpsie i
+
+    ldr r2, =pxCurrentTCB                    /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    ldr r1, [r2]                            /* Read pxCurrentTCB. */
+    ldr r0, [r1]                            /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+    adds r1, #4                                /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+    ldr r3, [r1]                            /* r3 = *r1 i.e. r3 = MAIR0. */
+    ldr r2, =0xe000edc0                        /* r2 = 0xe000edc0 [Location of MAIR0]. */
+    str r3, [r2]                            /* Program MAIR0. */
+    ldr r2, =0xe000ed98                        /* r2 = 0xe000ed98 [Location of RNR]. */
+    movs r3, #4                                /* r3 = 4. */
+    str r3, [r2]                            /* Program RNR = 4. */
+    adds r1, #4                                /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+    ldr r2, =0xe000ed9c                        /* r2 = 0xe000ed9c [Location of RBAR]. */
+    ldmia r1!, {r4-r11}                        /* Read 4 sets of RBAR/RLAR registers from TCB. */
+    stmia r2!, {r4-r11}                        /* Write 4 set of RBAR/RLAR registers using alias registers. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+    ldmia r0!, {r1-r11}                        /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+#else /* configENABLE_MPU */
+    ldmia r0!, {r2-r11}                        /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+    tst r3, #0x10                            /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+    it eq
+    vldmiaeq r0!, {s16-s31}                    /* Restore the FPU registers which are not restored automatically. */
+#endif /* configENABLE_FPU */
+
+ #if ( configENABLE_MPU == 1 )
+    msr psplim, r1                            /* Restore the PSPLIM register value for the task. */
+    msr control, r2                            /* Restore the CONTROL register value for the task. */
+#else /* configENABLE_MPU */
+    msr psplim, r2                            /* Restore the PSPLIM register value for the task. */
+#endif /* configENABLE_MPU */
+    msr psp, r0                                /* Remember the new top of stack for the task. */
+    bx r3
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+    tst lr, #4
+    ite eq
+    mrseq r0, msp
+    mrsne r0, psp
+    b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+    END

3rd_party/FreeRTOS/Source/portable/ARMv8M/non_secure/portasm.h

@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */

3rd_party/FreeRTOS/Source/portable/ARMv8M/non_secure/portmacro.h

@@ -0,0 +1,295 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+    #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+    #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+    #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR                                            char
+#define portFLOAT                                            float
+#define portDOUBLE                                            double
+#define portLONG                                            long
+#define portSHORT                                            short
+#define portSTACK_TYPE                                        uint32_t
+#define portBASE_TYPE                                        long
+
+typedef portSTACK_TYPE                                        StackType_t;
+typedef long                                                BaseType_t;
+typedef unsigned long                                        UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t )                    0xffff
+#else
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t )                    0xffffffffUL
+
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC                            1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portSTACK_GROWTH                                    ( -1 )
+#define portTICK_PERIOD_MS                                    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT                                    8
+#define portNOP()
+#define portINLINE                                            __inline
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE                                inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING                        1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );
+    extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+    extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+    extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+    #define portUSING_MPU_WRAPPERS                            1
+    #define portPRIVILEGE_BIT                                ( 0x80000000UL )
+#else
+    #define portPRIVILEGE_BIT                                ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION                            ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION                        ( 1UL )
+#define portPRIVILEGED_RAM_REGION                            ( 2UL )
+#define portUNPRIVILEGED_DEVICE_REGION                        ( 3UL )
+#define portSTACK_REGION                                    ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION                        ( 5UL )
+#define portLAST_CONFIGURABLE_REGION                        ( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS                        ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS                                ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Devices Region. */
+#define portDEVICE_REGION_START_ADDRESS                        ( 0x50000000 )
+#define portDEVICE_REGION_END_ADDRESS                        ( 0x5FFFFFFF )
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *                01 --> Device-nGnRE
+ *                10 --> Device-nGRE
+ *                11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE                        ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE                            ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE                            ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE                            ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE                    ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE            ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE                        ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE                        ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE                        ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE                ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE                            ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY                    ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY                            ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER                        ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+    uint32_t ulRBAR;    /**< RBAR for the region. */
+    uint32_t ulRLAR;    /**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+    uint32_t ulMAIR0;    /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+    MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT                        0
+#define portSVC_FREE_SECURE_CONTEXT                            1
+#define portSVC_START_SCHEDULER                                2
+#define portSVC_RAISE_PRIVILEGE                                3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()                                            vPortYield()
+#define portNVIC_INT_CTRL_REG                                ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT                                ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )                                portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()                    ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)                vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()                            __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()                                __asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()                                vPortEnterCritical()
+#define portEXIT_CRITICAL()                                    vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )        void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
+    #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
+    #define portCLEAN_UP_TCB( pxTCB )                            vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+    #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+    #define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
+    #define portIS_PRIVILEGED()                                    xIsPrivileged()
+
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
+    #define portRAISE_PRIVILEGE()                                __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
+    #define portRESET_PRIVILEGE()                                vResetPrivilege()
+#else
+    #define portIS_PRIVILEGED()
+    #define portRAISE_PRIVILEGE()
+    #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */

3rd_party/FreeRTOS/Source/portable/ARMv8M/secure/ReadMe.txt

@@ -0,0 +1,10 @@
+This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
+Do not use the files located here!  These file are copied into separate
+FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
+FreeRTOS release.
+
+If your Cortex-M33 application uses TrustZone then use the files from the
+FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
+
+If your Cortex-M33 application does not use TrustZone then use the files from
+the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.

3rd_party/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c

@@ -0,0 +1,88 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+    /* xSecureContextHandle value is in r0. */
+    __asm volatile
+    (
+    "    .syntax unified                            \n"
+    "                                            \n"
+    "    mrs r1, ipsr                            \n" /* r1 = IPSR. */
+    "    cbz r1, load_ctx_therad_mode            \n" /* Do nothing if the processor is running in the Thread Mode. */
+    "    ldmia r0!, {r1, r2}                        \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+    #if( configENABLE_MPU == 1 )
+    "    ldmia r1!, {r3}                            \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+    "    msr control, r3                            \n" /* CONTROL = r3. */
+    #endif /* configENABLE_MPU */
+    "    msr psplim, r2                            \n" /* PSPLIM = r2. */
+    "    msr psp, r1                                \n" /* PSP = r1. */
+    "                                            \n"
+    " load_ctx_therad_mode:                        \n"
+    "    nop                                        \n"
+    "                                            \n"
+    :::"r0", "r1", "r2"
+    );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+    /* xSecureContextHandle value is in r0. */
+    __asm volatile
+    (
+    "    .syntax unified                            \n"
+    "                                            \n"
+    "    mrs r1, ipsr                            \n" /* r1 = IPSR. */
+    "    cbz r1, save_ctx_therad_mode            \n" /* Do nothing if the processor is running in the Thread Mode. */
+    "    mrs r1, psp                                \n" /* r1 = PSP. */
+    #if( configENABLE_FPU == 1 )
+    "    vstmdb r1!, {s0}                        \n" /* Trigger the defferred stacking of FPU registers. */
+    "    vldmia r1!, {s0}                        \n" /* Nullify the effect of the pervious statement. */
+    #endif /* configENABLE_FPU */
+    #if( configENABLE_MPU == 1 )
+    "    mrs r2, control                            \n" /* r2 = CONTROL. */
+    "    stmdb r1!, {r2}                            \n" /* Store CONTROL value on the stack. */
+    #endif /* configENABLE_MPU */
+    "    str r1, [r0]                            \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+    "    movs r1, %0                                \n" /* r1 = securecontextNO_STACK. */
+    "    msr psplim, r1                            \n" /* PSPLIM = securecontextNO_STACK. */
+    "    msr psp, r1                                \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+    "                                            \n"
+    " save_ctx_therad_mode:                        \n"
+    "    nop                                        \n"
+    "                                            \n"
+    :: "i" ( securecontextNO_STACK ) : "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c

@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/* Functions implemented in assembler file. */
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+    SecureContext_LoadContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+    SecureContext_SaveContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s

@@ -0,0 +1,73 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+    SECTION .text:CODE:NOROOT(2)
+    THUMB
+
+    PUBLIC SecureContext_LoadContextAsm
+    PUBLIC SecureContext_SaveContextAsm
+/*-----------------------------------------------------------*/
+
+SecureContext_LoadContextAsm:
+    /* xSecureContextHandle value is in r0. */
+    mrs r1, ipsr                            /* r1 = IPSR. */
+    cbz r1, load_ctx_therad_mode            /* Do nothing if the processor is running in the Thread Mode. */
+    ldmia r0!, {r1, r2}                        /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+#if ( configENABLE_MPU == 1 )
+    ldmia r1!, {r3}                            /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+    msr control, r3                            /* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+    msr psplim, r2                            /* PSPLIM = r2. */
+    msr psp, r1                                /* PSP = r1. */
+
+    load_ctx_therad_mode:
+        bx lr
+/*-----------------------------------------------------------*/
+
+SecureContext_SaveContextAsm:
+    /* xSecureContextHandle value is in r0. */
+    mrs r1, ipsr                            /* r1 = IPSR. */
+    cbz r1, save_ctx_therad_mode            /* Do nothing if the processor is running in the Thread Mode. */
+    mrs r1, psp                                /* r1 = PSP. */
+#if ( configENABLE_FPU == 1 )
+    vstmdb r1!, {s0}                        /* Trigger the defferred stacking of FPU registers. */
+    vldmia r1!, {s0}                        /* Nullify the effect of the pervious statement. */
+#endif /* configENABLE_FPU */
+#if ( configENABLE_MPU == 1 )
+    mrs r2, control                            /* r2 = CONTROL. */
+    stmdb r1!, {r2}                            /* Store CONTROL value on the stack. */
+#endif /* configENABLE_MPU */
+    str r1, [r0]                            /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+    movs r1, #0                                /* r1 = securecontextNO_STACK. */
+    msr psplim, r1                            /* PSPLIM = securecontextNO_STACK. */
+    msr psp, r1                                /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+    save_ctx_therad_mode:
+        bx lr
+/*-----------------------------------------------------------*/
+
+    END

3rd_party/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.c

@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED        0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED        0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+    uint8_t *pucCurrentStackPointer;    /**< Current value of stack pointer (PSP). */
+    uint8_t *pucStackLimit;                /**< Last location of the stack memory (PSPLIM). */
+    uint8_t *pucStackStart;                /**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* No stack for thread mode until a task's context is loaded. */
+        secureportSET_PSPLIM( securecontextNO_STACK );
+        secureportSET_PSP( securecontextNO_STACK );
+
+        #if( configENABLE_MPU == 1 )
+        {
+            /* Configure thread mode to use PSP and to be unprivileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+        }
+        #else /* configENABLE_MPU */
+        {
+            /* Configure thread mode to use PSP and to be privileged.. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+        }
+        #endif /* configENABLE_MPU */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+    uint8_t *pucStackMemory = NULL;
+    uint32_t ulIPSR;
+    SecureContextHandle_t xSecureContextHandle = NULL;
+    #if( configENABLE_MPU == 1 )
+        uint32_t *pulCurrentStackPointer = NULL;
+    #endif /* configENABLE_MPU */
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Allocate the context structure. */
+        xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+        if( xSecureContextHandle != NULL )
+        {
+            /* Allocate the stack space. */
+            pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+            if( pucStackMemory != NULL )
+            {
+                /* Since stack grows down, the starting point will be the last
+                 * location. Note that this location is next to the last
+                 * allocated byte because the hardware decrements the stack
+                 * pointer before writing i.e. if stack pointer is 0x2, a push
+                 * operation will decrement the stack pointer to 0x1 and then
+                 * write at 0x1. */
+                xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+                /* The stack cannot go beyond this location. This value is
+                 * programmed in the PSPLIM register on context switch.*/
+                xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+                #if( configENABLE_MPU == 1 )
+                {
+                    /* Store the correct CONTROL value for the task on the stack.
+                     * This value is programmed in the CONTROL register on
+                     * context switch. */
+                    pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+                    pulCurrentStackPointer--;
+                    if( ulIsTaskPrivileged )
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+                    }
+                    else
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                    }
+
+                    /* Store the current stack pointer. This value is programmed in
+                     * the PSP register on context switch. */
+                    xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                }
+                #else /* configENABLE_MPU */
+                {
+                    /* Current SP is set to the starting of the stack. This
+                     * value programmed in the PSP register on context switch. */
+                    xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+                }
+                #endif /* configENABLE_MPU */
+            }
+            else
+            {
+                /* Free the context to avoid memory leak and make sure to return
+                 * NULL to indicate failure. */
+                vPortFree( xSecureContextHandle );
+                xSecureContextHandle = NULL;
+            }
+        }
+    }
+
+    return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Ensure that valid parameters are passed. */
+        secureportASSERT( xSecureContextHandle != NULL );
+
+        /* Free the stack space. */
+        vPortFree( xSecureContextHandle->pucStackLimit );
+
+        /* Free the context itself. */
+        vPortFree( xSecureContextHandle );
+    }
+}
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.h

@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK    0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext*    SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */

3rd_party/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.c

@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE        ( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+    #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+    #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+    #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE            ( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+    /* The application writer has already defined the array used for the RTOS
+     * heap - probably so it can be placed in a special segment or address. */
+    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+    struct A_BLOCK_LINK *pxNextFreeBlock;    /**< The next free block in the list. */
+    size_t xBlockSize;                        /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+    /* Ensure the heap starts on a correctly aligned boundary. */
+    uxAddress = ( size_t ) ucHeap;
+
+    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+    {
+        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+    }
+
+    pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+    /* xStart is used to hold a pointer to the first item in the list of free
+     * blocks.  The void cast is used to prevent compiler warnings. */
+    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+    xStart.xBlockSize = ( size_t ) 0;
+
+    /* pxEnd is used to mark the end of the list of free blocks and is inserted
+     * at the end of the heap space. */
+    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+    uxAddress -= xHeapStructSize;
+    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+    pxEnd = ( void * ) uxAddress;
+    pxEnd->xBlockSize = 0;
+    pxEnd->pxNextFreeBlock = NULL;
+
+    /* To start with there is a single free block that is sized to take up the
+     * entire heap space, minus the space taken by pxEnd. */
+    pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+    /* Only one block exists - and it covers the entire usable heap space. */
+    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+    /* Work out the position of the top bit in a size_t variable. */
+    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+    /* Iterate through the list until a block is found that has a higher address
+     * than the block being inserted. */
+    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+    {
+        /* Nothing to do here, just iterate to the right position. */
+    }
+
+    /* Do the block being inserted, and the block it is being inserted after
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxIterator;
+    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+    {
+        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+        pxBlockToInsert = pxIterator;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Do the block being inserted, and the block it is being inserted before
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxBlockToInsert;
+    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+    {
+        if( pxIterator->pxNextFreeBlock != pxEnd )
+        {
+            /* Form one big block from the two blocks. */
+            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+        }
+        else
+        {
+            pxBlockToInsert->pxNextFreeBlock = pxEnd;
+        }
+    }
+    else
+    {
+        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+    }
+
+    /* If the block being inserted plugged a gab, so was merged with the block
+     * before and the block after, then it's pxNextFreeBlock pointer will have
+     * already been set, and should not be set here as that would make it point
+     * to itself. */
+    if( pxIterator != pxBlockToInsert )
+    {
+        pxIterator->pxNextFreeBlock = pxBlockToInsert;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+    /* If this is the first call to malloc then the heap will require
+     * initialisation to setup the list of free blocks. */
+    if( pxEnd == NULL )
+    {
+        prvHeapInit();
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    {
+        /* The wanted size is increased so it can contain a BlockLink_t
+         * structure in addition to the requested amount of bytes. */
+        if( xWantedSize > 0 )
+        {
+            xWantedSize += xHeapStructSize;
+
+            /* Ensure that blocks are always aligned to the required number of
+             * bytes. */
+            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+            {
+                /* Byte alignment required. */
+                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+        {
+            /* Traverse the list from the start (lowest address) block until
+             * one of adequate size is found. */
+            pxPreviousBlock = &xStart;
+            pxBlock = xStart.pxNextFreeBlock;
+            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+            {
+                pxPreviousBlock = pxBlock;
+                pxBlock = pxBlock->pxNextFreeBlock;
+            }
+
+            /* If the end marker was reached then a block of adequate size was
+             * not found. */
+            if( pxBlock != pxEnd )
+            {
+                /* Return the memory space pointed to - jumping over the
+                 * BlockLink_t structure at its start. */
+                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+                /* This block is being returned for use so must be taken out
+                 * of the list of free blocks. */
+                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+                /* If the block is larger than required it can be split into
+                 * two. */
+                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+                {
+                    /* This block is to be split into two.  Create a new
+                     * block following the number of bytes requested. The void
+                     * cast is used to prevent byte alignment warnings from the
+                     * compiler. */
+                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+                    /* Calculate the sizes of two blocks split from the single
+                     * block. */
+                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+                    pxBlock->xBlockSize = xWantedSize;
+
+                    /* Insert the new block into the list of free blocks. */
+                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+                {
+                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* The block is being returned - it is allocated and owned by
+                 * the application and has no "next" block. */
+                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                pxBlock->pxNextFreeBlock = NULL;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    traceMALLOC( pvReturn, xWantedSize );
+
+    #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
+        {
+            extern void vApplicationMallocFailedHook( void );
+            vApplicationMallocFailedHook();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    #endif
+
+    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+    return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+    if( pv != NULL )
+    {
+        /* The memory being freed will have an BlockLink_t structure immediately
+         * before it. */
+        puc -= xHeapStructSize;
+
+        /* This casting is to keep the compiler from issuing warnings. */
+        pxLink = ( void * ) puc;
+
+        /* Check the block is actually allocated. */
+        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        {
+            if( pxLink->pxNextFreeBlock == NULL )
+            {
+                /* The block is being returned to the heap - it is no longer
+                 * allocated. */
+                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+                secureportDISABLE_NON_SECURE_INTERRUPTS();
+                {
+                    /* Add this block to the list of free blocks. */
+                    xFreeBytesRemaining += pxLink->xBlockSize;
+                    traceFREE( pv, pxLink->xBlockSize );
+                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+                }
+                secureportENABLE_NON_SECURE_INTERRUPTS();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+    return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+    return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+    /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.h

@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */

3rd_party/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.c

@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR                    ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS        ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK        ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR                        ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS            ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK            ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS                ( 26UL )
+#define secureinitFPCCR_TS_MASK                ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR                        ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS            ( 10UL )
+#define secureinitNSACR_CP10_MASK            ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS            ( 11UL )
+#define secureinitNSACR_CP11_MASK            ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+    uint32_t ulIPSR;
+
+     /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        *( secureinitSCB_AIRCR ) =    ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+                                    ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+                                    ( ( 0x1UL    << secureinitSCB_AIRCR_PRIS_POS )    & secureinitSCB_AIRCR_PRIS_MASK );
+    }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+    uint32_t ulIPSR;
+
+     /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+         * permitted. CP11 should be programmed to the same value as CP10. */
+        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+         * that we can enable/disable lazy stacking in port.c file. */
+        *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+         * registers (S16-S31) are also pushed to stack on exception entry and
+         * restored on exception return. */
+        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+    }
+}
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.h

@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */

3rd_party/FreeRTOS/Source/portable/ARMv8M/secure/macros/secure_port_macros.h

@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT                    8
+#define secureportBYTE_ALIGNMENT_MASK                ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+    #define secureportNON_SECURE_CALLABLE            __cmse_nonsecure_entry
+#else
+    #define secureportNON_SECURE_CALLABLE            __attribute__((cmse_nonsecure_entry))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+    __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+    __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+    __asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+    __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+    __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+    __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+    __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+    __asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL        0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )                        \
+    if( ( x ) == 0 )                                \
+    {                                                \
+        secureportDISABLE_SECURE_INTERRUPTS();        \
+        secureportDISABLE_NON_SECURE_INTERRUPTS();    \
+        for( ;; );                                    \
+    }
+
+#endif /* __SECURE_PORT_MACROS_H__ */

3rd_party/FreeRTOS/Source/portable/CCS/ARM_CM3/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/CCS/ARM_CM3/portasm.asm

@@ -1,6 +1,6 @@
 ;/*
-; * FreeRTOS Kernel V10.1.1
-; * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * FreeRTOS Kernel V10.2.0
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
 ; * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/CCS/ARM_CM3/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/CCS/ARM_CM4F/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/CCS/ARM_CM4F/portasm.asm

@@ -1,6 +1,6 @@
 ;/*
-; * FreeRTOS Kernel V10.1.1
-; * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * FreeRTOS Kernel V10.2.0
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
 ; * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/CCS/ARM_CM4F/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portASM.asm

@@ -1,6 +1,6 @@
 ;/*
-; * FreeRTOS Kernel V10.1.1
-; * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * FreeRTOS Kernel V10.2.0
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
 ; * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/CCS/MSP430X/data_model.h

@@ -1,6 +1,6 @@
 ;/*
-; * FreeRTOS Kernel V10.1.1
-; * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * FreeRTOS Kernel V10.2.0
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
 ; * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/CCS/MSP430X/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/CCS/MSP430X/portext.asm

@@ -1,6 +1,6 @@
 ;/*
-; * FreeRTOS Kernel V10.1.1
-; * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * FreeRTOS Kernel V10.2.0
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
 ; * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/CCS/MSP430X/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CA9/portASM.S

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/port.c

@@ -0,0 +1,897 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+    /* Secure components includes. */
+    #include "secure_context.h"
+    #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *        configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *        configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *        configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL                ( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD                ( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE        ( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL                    ( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2                    ( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK                ( 0x00000004 )
+#define portNVIC_SYSTICK_INT                ( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE                ( 0x00000001 )
+#define portNVIC_PENDSVSET                    ( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                    ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE            ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR                            ( ( volatile uint32_t * ) 0xe000ed88 )    /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE                ( 3UL )
+#define portCPACR_CP11_VALUE                portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS                    ( 20UL )
+#define portCPACR_CP11_POS                    ( 22UL )
+
+#define portFPCCR                            ( ( volatile uint32_t * ) 0xe000ef34 )    /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS                    ( 31UL )
+#define portFPCCR_ASPEN_MASK                ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS                    ( 30UL )
+#define portFPCCR_LSPEN_MASK                ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG                    ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                    ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                        ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG                    ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                    ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG                    ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                    ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG                    ( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                    ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG                    ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                    ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG                    ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                    ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK            ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK            ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS                ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS                ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS                ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS                ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS                ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS                ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS                ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS                ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0            ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1            ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2            ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3            ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4            ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5            ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6            ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7            ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE        ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE                        ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE            ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR                    ( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
+    #define portINITIAL_EXC_RETURN            ( 0xfffffffd )
+#else
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
+    #define portINITIAL_EXC_RETURN            ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK            ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED        ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS            configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS            prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS                1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT                0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
+    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
+    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
+    volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Stop and reset the SysTick. */
+    *( portNVIC_SYSTICK_CTRL ) = 0UL;
+    *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, then stop here so
+     * application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being
+         * defined but never called.  ulDummy is used purely to quieten other
+         * warnings about code appearing after this function is called - making
+         * ulDummy volatile makes the compiler think the function could return
+         * and therefore not output an 'unreachable code' warning for code that
+         * appears after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+    #if defined( __ARMCC_VERSION )
+        /* Declaration when these variable are defined in code instead of being
+         * exported from linker scripts. */
+        extern uint32_t * __privileged_functions_start__;
+        extern uint32_t * __privileged_functions_end__;
+        extern uint32_t * __syscalls_flash_start__;
+        extern uint32_t * __unprivileged_flash_end__;
+        extern uint32_t * __privileged_sram_start__;
+        extern uint32_t * __privileged_sram_end__;
+    #else
+        /* Declaration when these variable are exported from linker scripts. */
+        extern uint32_t __privileged_functions_start__[];
+        extern uint32_t __privileged_functions_end__[];
+        extern uint32_t __syscalls_flash_start__[];
+        extern uint32_t __unprivileged_flash_end__[];
+        extern uint32_t __privileged_sram_start__[];
+        extern uint32_t __privileged_sram_end__[];
+    #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Check that the MPU is present. */
+        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+        {
+            /* MAIR0 - Index 0. */
+            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+            /* MAIR0 - Index 1. */
+            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+            /* Setup privileged flash as Read Only so that privileged tasks can
+             * read it but not modify. */
+            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG =    ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                                ( portMPU_REGION_NON_SHAREABLE ) |
+                                ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+            portMPU_RLAR_REG =    ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                                ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged flash and system calls flash as Read Only by
+             * both privileged and unprivileged tasks. All tasks can read it but
+             * no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG =    ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                                ( portMPU_REGION_NON_SHAREABLE ) |
+                                ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG =    ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                                ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup RAM containing kernel data for privileged access only. */
+            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+            portMPU_RBAR_REG =    ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                                ( portMPU_REGION_NON_SHAREABLE ) |
+                                ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                                ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG =    ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                                ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                ( portMPU_RLAR_REGION_ENABLE );
+
+            /* By default allow everything to access the general peripherals.
+             * The system peripherals and registers are protected. */
+            portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;
+            portMPU_RBAR_REG =    ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |
+                                ( portMPU_REGION_NON_SHAREABLE ) |
+                                ( portMPU_REGION_READ_WRITE ) |
+                                ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG =    ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |
+                                ( portMPU_RLAR_ATTR_INDEX1 ) |
+                                ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Enable mem fault. */
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+            /* Enable MPU with privileged background access i.e. unmapped
+             * regions have privileged access. */
+            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if( configENABLE_TRUSTZONE == 1 )
+        {
+            /* Enable non-secure access to the FPU. */
+            SecureInit_EnableNSFPUAccess();
+        }
+        #endif /* configENABLE_TRUSTZONE */
+
+        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+         * unprivileged code should be able to access FPU. CP11 should be
+         * programmed to the same value as CP10. */
+        *( portCPACR ) |=    (    ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+                                ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+                            );
+
+        /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+         * context on exception entry and restore on exception return.
+         * LSPEN = 1 ==> Enable lazy context save of FP state. */
+        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+    }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Set a PendSV to request a context switch. */
+    *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile( "dsb" ::: "memory" );
+    __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile( "dsb" ::: "memory" );
+    __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */
+{
+#if( configENABLE_MPU == 1 )
+    #if defined( __ARMCC_VERSION )
+        /* Declaration when these variable are defined in code instead of being
+         * exported from linker scripts. */
+        extern uint32_t * __syscalls_flash_start__;
+        extern uint32_t * __syscalls_flash_end__;
+    #else
+        /* Declaration when these variable are exported from linker scripts. */
+        extern uint32_t __syscalls_flash_start__[];
+        extern uint32_t __syscalls_flash_end__[];
+    #endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+    uint32_t ulR0;
+    #if( configENABLE_MPU == 1 )
+        uint32_t ulControl, ulIsTaskPrivileged;
+    #endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+     * R12, LR, PC, xPSR. */
+    ulPC = pulCallerStackAddress[ 6 ];
+    ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        #if( configENABLE_TRUSTZONE == 1 )
+            case portSVC_ALLOCATE_SECURE_CONTEXT:
+            {
+                /* R0 contains the stack size passed as parameter to the
+                 * vPortAllocateSecureContext function. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                #if( configENABLE_MPU == 1 )
+                {
+                    /* Read the CONTROL register value. */
+                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+                    /* The task that raised the SVC is privileged if Bit[0]
+                     * in the CONTROL register is 0. */
+                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+                    /* Allocate and load a context for the secure task. */
+                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+                }
+                #else
+                {
+                    /* Allocate and load a context for the secure task. */
+                    xSecureContext = SecureContext_AllocateContext( ulR0 );
+                }
+                #endif /* configENABLE_MPU */
+
+                configASSERT( xSecureContext != NULL );
+                SecureContext_LoadContext( xSecureContext );
+            }
+            break;
+
+            case portSVC_FREE_SECURE_CONTEXT:
+            {
+                /* R0 contains the secure context handle to be freed. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                /* Free the secure context. */
+                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+            }
+            break;
+        #endif /* configENABLE_TRUSTZONE */
+
+        case portSVC_START_SCHEDULER:
+        {
+            #if( configENABLE_TRUSTZONE == 1 )
+            {
+                /* De-prioritize the non-secure exceptions so that the
+                 * non-secure pendSV runs at the lowest priority. */
+                SecureInit_DePrioritizeNSExceptions();
+
+                /* Initialize the secure context management system. */
+                SecureContext_Init();
+            }
+            #endif /* configENABLE_TRUSTZONE */
+
+            #if( configENABLE_FPU == 1 )
+            {
+                /* Setup the Floating Point Unit (FPU). */
+                prvSetupFPU();
+            }
+            #endif /* configENABLE_FPU */
+
+            /* Setup the context of the first task so that the first task starts
+             * executing. */
+            vRestoreContextOfFirstTask();
+        }
+        break;
+
+        #if( configENABLE_MPU == 1 )
+            case portSVC_RAISE_PRIVILEGE:
+            {
+                /* Only raise the privilege, if the svc was raised from any of
+                 * the system calls. */
+                if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+                    ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+                {
+                    vRaisePrivilege();
+                }
+            }
+            break;
+        #endif /* configENABLE_MPU */
+
+        default:
+        {
+            /* Incorrect SVC call. */
+            configASSERT( pdFALSE );
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+    StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+    StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    #if( portPRELOAD_REGISTERS == 0 )
+    {
+        pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+        *pxTopOfStack = portINITIAL_XPSR;                            /* xPSR */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pxCode;                        /* PC */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;    /* LR */
+        pxTopOfStack -= 5;                                            /* R12, R3, R2 and R1. */
+        *pxTopOfStack = ( StackType_t ) pvParameters;                /* R0 */
+        pxTopOfStack -= 9;                                            /* R11..R4, EXC_RETURN. */
+        *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+        #if( configENABLE_MPU == 1 )
+        {
+            pxTopOfStack--;
+            if( xRunPrivileged == pdTRUE )
+            {
+                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;        /* Slot used to hold this task's CONTROL value. */
+            }
+            else
+            {
+                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;    /* Slot used to hold this task's CONTROL value. */
+            }
+        }
+        #endif /* configENABLE_MPU */
+
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pxEndOfStack;    /* Slot used to hold this task's PSPLIM value. */
+
+        #if( configENABLE_TRUSTZONE == 1 )
+        {
+            pxTopOfStack--;
+            *pxTopOfStack = portNO_SECURE_CONTEXT;        /* Slot used to hold this task's xSecureContext value. */
+        }
+        #endif /* configENABLE_TRUSTZONE */
+    }
+    #else /* portPRELOAD_REGISTERS */
+    {
+        pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+        *pxTopOfStack = portINITIAL_XPSR;                            /* xPSR */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pxCode;                        /* PC */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;    /* LR */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x12121212UL;                /* R12 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x03030303UL;                /* R3 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x02020202UL;                /* R2 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x01010101UL;                /* R1 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pvParameters;                /* R0 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x11111111UL;                /* R11 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x10101010UL;                /* R10 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x09090909UL;                /* R09 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x08080808UL;                /* R08 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x07070707UL;                /* R07 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x06060606UL;                /* R06 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x05050505UL;                /* R05 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x04040404UL;                /* R04 */
+        pxTopOfStack--;
+        *pxTopOfStack = portINITIAL_EXC_RETURN;                        /* EXC_RETURN */
+
+        #if( configENABLE_MPU == 1 )
+        {
+            pxTopOfStack--;
+            if( xRunPrivileged == pdTRUE )
+            {
+                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;        /* Slot used to hold this task's CONTROL value. */
+            }
+            else
+            {
+                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;    /* Slot used to hold this task's CONTROL value. */
+            }
+        }
+        #endif /* configENABLE_MPU */
+
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pxEndOfStack;    /* Slot used to hold this task's PSPLIM value. */
+
+        #if( configENABLE_TRUSTZONE == 1 )
+        {
+            pxTopOfStack--;
+            *pxTopOfStack = portNO_SECURE_CONTEXT;        /* Slot used to hold this task's xSecureContext value. */
+        }
+        #endif /* configENABLE_TRUSTZONE */
+    }
+    #endif /* portPRELOAD_REGISTERS */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+    *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+    #if( configENABLE_MPU == 1 )
+    {
+        /* Setup the Memory Protection Unit (MPU). */
+        prvSetupMPU();
+    }
+    #endif /* configENABLE_MPU */
+
+    /* Start the timer that generates the tick ISR. Interrupts are disabled
+     * here already. */
+    prvSetupTimerInterrupt();
+
+    /* Initialize the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    /* Start the first task. */
+    vStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing. Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. Call
+     * vTaskSwitchContext() so link time optimization does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here. */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+    {
+    uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+    int32_t lIndex = 0;
+
+        /* Setup MAIR0. */
+        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that
+         * the stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            /* Define the region that allows access to the stack. */
+            ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+            xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =    ( ulRegionStartAddress ) |
+                                                            ( portMPU_REGION_NON_SHAREABLE ) |
+                                                            ( portMPU_REGION_READ_WRITE ) |
+                                                            ( portMPU_REGION_EXECUTE_NEVER );
+
+            xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =    ( ulRegionEndAddress ) |
+                                                            ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                                            ( portMPU_RLAR_REGION_ENABLE );
+        }
+
+        /* User supplied configurable regions. */
+        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+        {
+            /* If xRegions is NULL i.e. the task has not specified any MPU
+             * region, the else part ensures that all the configurable MPU
+             * regions are invalidated. */
+            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+            {
+                /* Translate the generic region definition contained in xRegions
+                 * into the ARMv8 specific MPU settings that are then stored in
+                 * xMPUSettings. */
+                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+                ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+                /* Start address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =    ( ulRegionStartAddress ) |
+                                                                            ( portMPU_REGION_NON_SHAREABLE );
+
+                /* RO/RW. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+                }
+                else
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+                }
+
+                /* XN. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+                }
+
+                /* End Address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =    ( ulRegionEndAddress ) |
+                                                                            ( portMPU_RLAR_REGION_ENABLE );
+
+                /* Normal memory/ Device memory. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+                {
+                    /* Attr1 in MAIR0 is configured as device memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+                }
+                else
+                {
+                    /* Attr1 in MAIR0 is configured as normal memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+                }
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c

@@ -0,0 +1,381 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Portasm includes. */
+#include "portasm.h"
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    .syntax unified                                    \n"
+    "                                                    \n"
+    "    ldr  r2, pxCurrentTCBConst2                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    "    ldr  r3, [r2]                                    \n" /* Read pxCurrentTCB. */
+    "    ldr  r0, [r3]                                    \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    adds r3, #4                                        \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+    "    ldr  r4, [r3]                                    \n" /* r4 = *r3 i.e. r4 = MAIR0. */
+    "    ldr  r2, xMAIR0Const2                            \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+    "    str  r4, [r2]                                    \n" /* Program MAIR0. */
+    "    ldr  r2, xRNRConst2                                \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+    "    movs r4, #4                                        \n" /* r4 = 4. */
+    "    str  r4, [r2]                                    \n" /* Program RNR = 4. */
+    "    adds r3, #4                                        \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+    "    ldr  r2, xRBARConst2                            \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+    "    ldmia r3!, {r4-r11}                                \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+    "    stmia r2!, {r4-r11}                                \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    ldm  r0!, {r1-r4}                                \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+    "    ldr  r5, xSecureContextConst2                    \n"
+    "    str  r1, [r5]                                    \n" /* Set xSecureContext to this task's value for the same. */
+    "    msr  psplim, r2                                    \n" /* Set this task's PSPLIM value. */
+    "    msr  control, r3                                \n" /* Set this task's CONTROL value. */
+    "    adds r0, #32                                    \n" /* Discard everything up to r0. */
+    "    msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+    "    isb                                                \n"
+    "    bx   r4                                            \n" /* Finally, branch to EXC_RETURN. */
+    #else /* configENABLE_MPU */
+    "    ldm  r0!, {r1-r3}                                \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+    "    ldr  r4, xSecureContextConst2                    \n"
+    "    str  r1, [r4]                                    \n" /* Set xSecureContext to this task's value for the same. */
+    "    msr  psplim, r2                                    \n" /* Set this task's PSPLIM value. */
+    "    movs r1, #2                                        \n" /* r1 = 2. */
+    "    msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+    "    adds r0, #32                                    \n" /* Discard everything up to r0. */
+    "    msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+    "    isb                                                \n"
+    "    bx   r3                                            \n" /* Finally, branch to EXC_RETURN. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    "    .align 4                                        \n"
+    "pxCurrentTCBConst2: .word pxCurrentTCB                \n"
+    "xSecureContextConst2: .word xSecureContext            \n"
+    #if( configENABLE_MPU == 1 )
+    "xMAIR0Const2: .word 0xe000edc0                        \n"
+    "xRNRConst2: .word 0xe000ed98                        \n"
+    "xRBARConst2: .word 0xe000ed9c                        \n"
+    #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+    "    mrs r0, control                                    \n" /* r0 = CONTROL. */
+    "    tst r0, #1                                        \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+    "    ite ne                                            \n"
+    "    movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+    "    moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+    "    bx lr                                            \n" /* Return. */
+    "                                                    \n"
+    "    .align 4                                        \n"
+    ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+     __asm volatile
+    (
+    "    mrs r0, control                                    \n" /* Read the CONTROL register. */
+    "    bic r0, #1                                        \n" /* Clear the bit 0. */
+    "    msr control, r0                                    \n" /* Write back the new CONTROL value. */
+    "    bx lr                                            \n" /* Return to the caller. */
+    ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+    "    mrs r0, control                                    \n" /* r0 = CONTROL. */
+    "    orr r0, #1                                        \n" /* r0 = r0 | 1. */
+    "    msr control, r0                                    \n" /* CONTROL = r0. */
+    "    bx lr                                            \n" /* Return to the caller. */
+    :::"r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    ldr r0, xVTORConst                                \n" /* Use the NVIC offset register to locate the stack. */
+    "    ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+    "    ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+    "    msr msp, r0                                        \n" /* Set the MSP back to the start of the stack. */
+    "    cpsie i                                            \n" /* Globally enable interrupts. */
+    "    cpsie f                                            \n"
+    "    dsb                                                \n"
+    "    isb                                                \n"
+    "    svc %0                                            \n" /* System call to start the first task. */
+    "    nop                                                \n"
+    "                                                    \n"
+    "   .align 4                                        \n"
+    "xVTORConst: .word 0xe000ed08                        \n"
+    :: "i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    mrs r0, PRIMASK                                    \n"
+    "    cpsid i                                            \n"
+    "    bx lr                                            \n"
+    ::: "memory"
+    );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+    /* To avoid compiler warnings.  The return statement will never be reached,
+     * but some compilers warn if it is not included, while others won't compile
+     * if it is. */
+    return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    msr PRIMASK, r0                                    \n"
+    "    bx lr                                            \n"
+    ::: "memory"
+    );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+    /* Just to avoid compiler warning.  ulMask is used from the asm code but
+     * the compiler can't see that.  Some compilers generate warnings without
+     * the following line, while others generate warnings if the line is
+     * included. */
+    ( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    .syntax unified                                    \n"
+    "    .extern SecureContext_SaveContext                \n"
+    "    .extern SecureContext_LoadContext                \n"
+    "                                                    \n"
+    "    mrs r1, psp                                        \n" /* Read PSP in r1. */
+    "    ldr r2, xSecureContextConst                        \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+    "    ldr r0, [r2]                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+    "                                                    \n"
+    "    cbz r0, save_ns_context                            \n" /* No secure context to save. */
+    "    push {r0-r2, r14}                                \n"
+    "    bl SecureContext_SaveContext                    \n"
+    "    pop {r0-r3}                                        \n" /* LR is now in r3. */
+    "    mov lr, r3                                        \n" /* LR = r3. */
+    "    lsls r2, r3, #25                                \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+    "    bpl save_ns_context                                \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+    "    ldr r3, pxCurrentTCBConst                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    "    ldr r2, [r3]                                    \n" /* Read pxCurrentTCB. */
+    #if( configENABLE_MPU == 1 )
+    "    subs r1, r1, #16                                \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+    "    str r1, [r2]                                    \n" /* Save the new top of stack in TCB. */
+    "    mrs r2, psplim                                    \n" /* r2 = PSPLIM. */
+    "    mrs r3, control                                    \n" /* r3 = CONTROL. */
+    "    mov r4, lr                                        \n" /* r4 = LR/EXC_RETURN. */
+    "    stmia r1!, {r0, r2-r4}                            \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+    #else /* configENABLE_MPU */
+    "    subs r1, r1, #12                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
+    "    str r1, [r2]                                    \n" /* Save the new top of stack in TCB. */
+    "    mrs r2, psplim                                    \n" /* r2 = PSPLIM. */
+    "    mov r3, lr                                        \n" /* r3 = LR/EXC_RETURN. */
+    "    stmia r1!, {r0, r2-r3}                            \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+    #endif /* configENABLE_MPU */
+    "    b select_next_task                                \n"
+    "                                                    \n"
+    " save_ns_context:                                    \n"
+    "    ldr r3, pxCurrentTCBConst                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    "    ldr r2, [r3]                                    \n" /* Read pxCurrentTCB. */
+    #if( configENABLE_FPU == 1 )
+    "    tst lr, #0x10                                    \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+    "    it eq                                            \n"
+    "    vstmdbeq r1!, {s16-s31}                            \n" /* Store the FPU registers which are not saved automatically. */
+    #endif /* configENABLE_FPU */
+    #if( configENABLE_MPU == 1 )
+    "    subs r1, r1, #48                                \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+    "    str r1, [r2]                                    \n" /* Save the new top of stack in TCB. */
+    "    adds r1, r1, #16                                \n" /* r1 = r1 + 16. */
+    "    stm r1, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
+    "    mrs r2, psplim                                    \n" /* r2 = PSPLIM. */
+    "    mrs r3, control                                    \n" /* r3 = CONTROL. */
+    "    mov r4, lr                                        \n" /* r4 = LR/EXC_RETURN. */
+    "    subs r1, r1, #16                                \n" /* r1 = r1 - 16. */
+    "    stm r1, {r0, r2-r4}                                \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+    #else /* configENABLE_MPU */
+    "    subs r1, r1, #44                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+    "    str r1, [r2]                                    \n" /* Save the new top of stack in TCB. */
+    "    adds r1, r1, #12                                \n" /* r1 = r1 + 12. */
+    "    stm r1, {r4-r11}                                \n" /* Store the registers that are not saved automatically. */
+    "    mrs r2, psplim                                    \n" /* r2 = PSPLIM. */
+    "    mov r3, lr                                        \n" /* r3 = LR/EXC_RETURN. */
+    "    subs r1, r1, #12                                \n" /* r1 = r1 - 12. */
+    "    stmia r1!, {r0, r2-r3}                            \n" /* Store xSecureContext, PSPLIM and LR on the stack. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    " select_next_task:                                    \n"
+    "    cpsid i                                            \n"
+    "    bl vTaskSwitchContext                            \n"
+    "    cpsie i                                            \n"
+    "                                                    \n"
+    "    ldr r2, pxCurrentTCBConst                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    "    ldr r3, [r2]                                    \n" /* Read pxCurrentTCB. */
+    "    ldr r1, [r3]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    adds r3, #4                                        \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+    "    ldr r4, [r3]                                    \n" /* r4 = *r3 i.e. r4 = MAIR0. */
+    "    ldr r2, xMAIR0Const                                \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+    "    str r4, [r2]                                    \n" /* Program MAIR0. */
+    "    ldr r2, xRNRConst                                \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+    "    movs r4, #4                                        \n" /* r4 = 4. */
+    "    str r4, [r2]                                    \n" /* Program RNR = 4. */
+    "    adds r3, #4                                        \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+    "    ldr  r2, xRBARConst                                \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+    "    ldmia r3!, {r4-r11}                                \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+    "    stmia r2!, {r4-r11}                                \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    ldmia r1!, {r0, r2-r4}                            \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+    "    msr psplim, r2                                    \n" /* Restore the PSPLIM register value for the task. */
+    "    msr control, r3                                    \n" /* Restore the CONTROL register value for the task. */
+    "    mov lr, r4                                        \n" /* LR = r4. */
+    "    ldr r2, xSecureContextConst                        \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+    "    str r0, [r2]                                    \n" /* Restore the task's xSecureContext. */
+    "    cbz r0, restore_ns_context                        \n" /* If there is no secure context for the task, restore the non-secure context. */
+    "    push {r1,r4}                                    \n"
+    "    bl SecureContext_LoadContext                    \n" /* Restore the secure context. */
+    "    pop {r1,r4}                                        \n"
+    "    mov lr, r4                                        \n" /* LR = r4. */
+    "    lsls r2, r4, #25                                \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+    "    bpl restore_ns_context                            \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+    "    msr psp, r1                                        \n" /* Remember the new top of stack for the task. */
+    "    bx lr                                            \n"
+    #else /* configENABLE_MPU */
+    "    ldmia r1!, {r0, r2-r3}                            \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+    "    msr psplim, r2                                    \n" /* Restore the PSPLIM register value for the task. */
+    "    mov lr, r3                                        \n" /* LR = r3. */
+    "    ldr r2, xSecureContextConst                        \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
+    "    str r0, [r2]                                    \n" /* Restore the task's xSecureContext. */
+    "    cbz r0, restore_ns_context                        \n" /* If there is no secure context for the task, restore the non-secure context. */
+    "    push {r1,r3}                                    \n"
+    "    bl SecureContext_LoadContext                    \n" /* Restore the secure context. */
+    "    pop {r1,r3}                                        \n"
+    "    mov lr, r3                                        \n" /* LR = r3. */
+    "    lsls r2, r3, #25                                \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+    "    bpl restore_ns_context                            \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+    "    msr psp, r1                                        \n" /* Remember the new top of stack for the task. */
+    "    bx lr                                            \n"
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    " restore_ns_context:                                \n"
+    "    ldmia r1!, {r4-r11}                                \n" /* Restore the registers that are not automatically restored. */
+    #if( configENABLE_FPU == 1 )
+    "    tst lr, #0x10                                    \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+    "    it eq                                            \n"
+    "    vldmiaeq r1!, {s16-s31}                            \n" /* Restore the FPU registers which are not restored automatically. */
+    #endif /* configENABLE_FPU */
+    "    msr psp, r1                                        \n" /* Remember the new top of stack for the task. */
+    "    bx lr                                            \n"
+    "                                                    \n"
+    "    .align 4                                        \n"
+    "pxCurrentTCBConst: .word pxCurrentTCB                \n"
+    "xSecureContextConst: .word xSecureContext            \n"
+    #if( configENABLE_MPU == 1 )
+    "xMAIR0Const: .word 0xe000edc0                        \n"
+    "xRNRConst: .word 0xe000ed98                        \n"
+    "xRBARConst: .word 0xe000ed9c                        \n"
+    #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    tst lr, #4                                        \n"
+    "    ite eq                                            \n"
+    "    mrseq r0, msp                                    \n"
+    "    mrsne r0, psp                                    \n"
+    "    ldr r1, svchandler_address_const                \n"
+    "    bx r1                                            \n"
+    "                                                    \n"
+    "    .align 4                                        \n"
+    "svchandler_address_const: .word vPortSVCHandler_C    \n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+    "    svc %0                                            \n" /* Secure context is allocated in the supervisor call. */
+    "    bx lr                                            \n" /* Return. */
+    :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    ldr r1, [r0]                                    \n" /* The first item in the TCB is the top of the stack. */
+    "    ldr r0, [r1]                                    \n" /* The first item on the stack is the task's xSecureContext. */
+    "    cmp r0, #0                                        \n" /* Raise svc if task's xSecureContext is not NULL. */
+    "    it ne                                            \n"
+    "    svcne %0                                        \n" /* Secure context is freed in the supervisor call. */
+    "    bx lr                                            \n" /* Return. */
+    :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.h

@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h

@@ -0,0 +1,295 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+    #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+    #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+    #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR                                            char
+#define portFLOAT                                            float
+#define portDOUBLE                                            double
+#define portLONG                                            long
+#define portSHORT                                            short
+#define portSTACK_TYPE                                        uint32_t
+#define portBASE_TYPE                                        long
+
+typedef portSTACK_TYPE                                        StackType_t;
+typedef long                                                BaseType_t;
+typedef unsigned long                                        UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t )                    0xffff
+#else
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t )                    0xffffffffUL
+
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC                            1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portSTACK_GROWTH                                    ( -1 )
+#define portTICK_PERIOD_MS                                    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT                                    8
+#define portNOP()
+#define portINLINE                                            __inline
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE                                inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING                        1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );
+    extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+    extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+    extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+    #define portUSING_MPU_WRAPPERS                            1
+    #define portPRIVILEGE_BIT                                ( 0x80000000UL )
+#else
+    #define portPRIVILEGE_BIT                                ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION                            ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION                        ( 1UL )
+#define portPRIVILEGED_RAM_REGION                            ( 2UL )
+#define portUNPRIVILEGED_DEVICE_REGION                        ( 3UL )
+#define portSTACK_REGION                                    ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION                        ( 5UL )
+#define portLAST_CONFIGURABLE_REGION                        ( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS                        ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS                                ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Devices Region. */
+#define portDEVICE_REGION_START_ADDRESS                        ( 0x50000000 )
+#define portDEVICE_REGION_END_ADDRESS                        ( 0x5FFFFFFF )
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *                01 --> Device-nGnRE
+ *                10 --> Device-nGRE
+ *                11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE                        ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE                            ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE                            ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE                            ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE                    ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE            ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE                        ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE                        ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE                        ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE                ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE                            ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY                    ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY                            ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER                        ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+    uint32_t ulRBAR;    /**< RBAR for the region. */
+    uint32_t ulRLAR;    /**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+    uint32_t ulMAIR0;    /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+    MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT                        0
+#define portSVC_FREE_SECURE_CONTEXT                            1
+#define portSVC_START_SCHEDULER                                2
+#define portSVC_RAISE_PRIVILEGE                                3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()                                            vPortYield()
+#define portNVIC_INT_CTRL_REG                                ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT                                ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )                                portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()                    ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)                vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()                            __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()                                __asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()                                vPortEnterCritical()
+#define portEXIT_CRITICAL()                                    vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )        void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
+    #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
+    #define portCLEAN_UP_TCB( pxTCB )                            vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+    #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+    #define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
+    #define portIS_PRIVILEGED()                                    xIsPrivileged()
+
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
+    #define portRAISE_PRIVILEGE()                                __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
+    #define portRESET_PRIVILEGE()                                vResetPrivilege()
+#else
+    #define portIS_PRIVILEGED()
+    #define portRAISE_PRIVILEGE()
+    #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.c

@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED        0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED        0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+    uint8_t *pucCurrentStackPointer;    /**< Current value of stack pointer (PSP). */
+    uint8_t *pucStackLimit;                /**< Last location of the stack memory (PSPLIM). */
+    uint8_t *pucStackStart;                /**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* No stack for thread mode until a task's context is loaded. */
+        secureportSET_PSPLIM( securecontextNO_STACK );
+        secureportSET_PSP( securecontextNO_STACK );
+
+        #if( configENABLE_MPU == 1 )
+        {
+            /* Configure thread mode to use PSP and to be unprivileged. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+        }
+        #else /* configENABLE_MPU */
+        {
+            /* Configure thread mode to use PSP and to be privileged.. */
+            secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+        }
+        #endif /* configENABLE_MPU */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+    uint8_t *pucStackMemory = NULL;
+    uint32_t ulIPSR;
+    SecureContextHandle_t xSecureContextHandle = NULL;
+    #if( configENABLE_MPU == 1 )
+        uint32_t *pulCurrentStackPointer = NULL;
+    #endif /* configENABLE_MPU */
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Allocate the context structure. */
+        xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+        if( xSecureContextHandle != NULL )
+        {
+            /* Allocate the stack space. */
+            pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+            if( pucStackMemory != NULL )
+            {
+                /* Since stack grows down, the starting point will be the last
+                 * location. Note that this location is next to the last
+                 * allocated byte because the hardware decrements the stack
+                 * pointer before writing i.e. if stack pointer is 0x2, a push
+                 * operation will decrement the stack pointer to 0x1 and then
+                 * write at 0x1. */
+                xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+                /* The stack cannot go beyond this location. This value is
+                 * programmed in the PSPLIM register on context switch.*/
+                xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+                #if( configENABLE_MPU == 1 )
+                {
+                    /* Store the correct CONTROL value for the task on the stack.
+                     * This value is programmed in the CONTROL register on
+                     * context switch. */
+                    pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+                    pulCurrentStackPointer--;
+                    if( ulIsTaskPrivileged )
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+                    }
+                    else
+                    {
+                        *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                    }
+
+                    /* Store the current stack pointer. This value is programmed in
+                     * the PSP register on context switch. */
+                    xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                }
+                #else /* configENABLE_MPU */
+                {
+                    /* Current SP is set to the starting of the stack. This
+                     * value programmed in the PSP register on context switch. */
+                    xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+
+                }
+                #endif /* configENABLE_MPU */
+            }
+            else
+            {
+                /* Free the context to avoid memory leak and make sure to return
+                 * NULL to indicate failure. */
+                vPortFree( xSecureContextHandle );
+                xSecureContextHandle = NULL;
+            }
+        }
+    }
+
+    return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Ensure that valid parameters are passed. */
+        secureportASSERT( xSecureContextHandle != NULL );
+
+        /* Free the stack space. */
+        vPortFree( xSecureContextHandle->pucStackLimit );
+
+        /* Free the context itself. */
+        vPortFree( xSecureContextHandle );
+    }
+}
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.h

@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK    0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext*    SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if( configENABLE_MPU == 1 )
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c

@@ -0,0 +1,88 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+    /* xSecureContextHandle value is in r0. */
+    __asm volatile
+    (
+    "    .syntax unified                            \n"
+    "                                            \n"
+    "    mrs r1, ipsr                            \n" /* r1 = IPSR. */
+    "    cbz r1, load_ctx_therad_mode            \n" /* Do nothing if the processor is running in the Thread Mode. */
+    "    ldmia r0!, {r1, r2}                        \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+    #if( configENABLE_MPU == 1 )
+    "    ldmia r1!, {r3}                            \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
+    "    msr control, r3                            \n" /* CONTROL = r3. */
+    #endif /* configENABLE_MPU */
+    "    msr psplim, r2                            \n" /* PSPLIM = r2. */
+    "    msr psp, r1                                \n" /* PSP = r1. */
+    "                                            \n"
+    " load_ctx_therad_mode:                        \n"
+    "    nop                                        \n"
+    "                                            \n"
+    :::"r0", "r1", "r2"
+    );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+    /* xSecureContextHandle value is in r0. */
+    __asm volatile
+    (
+    "    .syntax unified                            \n"
+    "                                            \n"
+    "    mrs r1, ipsr                            \n" /* r1 = IPSR. */
+    "    cbz r1, save_ctx_therad_mode            \n" /* Do nothing if the processor is running in the Thread Mode. */
+    "    mrs r1, psp                                \n" /* r1 = PSP. */
+    #if( configENABLE_FPU == 1 )
+    "    vstmdb r1!, {s0}                        \n" /* Trigger the defferred stacking of FPU registers. */
+    "    vldmia r1!, {s0}                        \n" /* Nullify the effect of the pervious statement. */
+    #endif /* configENABLE_FPU */
+    #if( configENABLE_MPU == 1 )
+    "    mrs r2, control                            \n" /* r2 = CONTROL. */
+    "    stmdb r1!, {r2}                            \n" /* Store CONTROL value on the stack. */
+    #endif /* configENABLE_MPU */
+    "    str r1, [r0]                            \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+    "    movs r1, %0                                \n" /* r1 = securecontextNO_STACK. */
+    "    msr psplim, r1                            \n" /* PSPLIM = securecontextNO_STACK. */
+    "    msr psp, r1                                \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+    "                                            \n"
+    " save_ctx_therad_mode:                        \n"
+    "    nop                                        \n"
+    "                                            \n"
+    :: "i" ( securecontextNO_STACK ) : "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.c

@@ -0,0 +1,450 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE        ( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+    #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+    #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+    #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE            ( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+    /* The application writer has already defined the array used for the RTOS
+     * heap - probably so it can be placed in a special segment or address. */
+    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+    struct A_BLOCK_LINK *pxNextFreeBlock;    /**< The next free block in the list. */
+    size_t xBlockSize;                        /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t uxAddress;
+size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+    /* Ensure the heap starts on a correctly aligned boundary. */
+    uxAddress = ( size_t ) ucHeap;
+
+    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+    {
+        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+    }
+
+    pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+    /* xStart is used to hold a pointer to the first item in the list of free
+     * blocks.  The void cast is used to prevent compiler warnings. */
+    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+    xStart.xBlockSize = ( size_t ) 0;
+
+    /* pxEnd is used to mark the end of the list of free blocks and is inserted
+     * at the end of the heap space. */
+    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+    uxAddress -= xHeapStructSize;
+    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+    pxEnd = ( void * ) uxAddress;
+    pxEnd->xBlockSize = 0;
+    pxEnd->pxNextFreeBlock = NULL;
+
+    /* To start with there is a single free block that is sized to take up the
+     * entire heap space, minus the space taken by pxEnd. */
+    pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+    /* Only one block exists - and it covers the entire usable heap space. */
+    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+    /* Work out the position of the top bit in a size_t variable. */
+    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+    /* Iterate through the list until a block is found that has a higher address
+     * than the block being inserted. */
+    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+    {
+        /* Nothing to do here, just iterate to the right position. */
+    }
+
+    /* Do the block being inserted, and the block it is being inserted after
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxIterator;
+    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+    {
+        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+        pxBlockToInsert = pxIterator;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Do the block being inserted, and the block it is being inserted before
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxBlockToInsert;
+    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+    {
+        if( pxIterator->pxNextFreeBlock != pxEnd )
+        {
+            /* Form one big block from the two blocks. */
+            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+        }
+        else
+        {
+            pxBlockToInsert->pxNextFreeBlock = pxEnd;
+        }
+    }
+    else
+    {
+        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+    }
+
+    /* If the block being inserted plugged a gab, so was merged with the block
+     * before and the block after, then it's pxNextFreeBlock pointer will have
+     * already been set, and should not be set here as that would make it point
+     * to itself. */
+    if( pxIterator != pxBlockToInsert )
+    {
+        pxIterator->pxNextFreeBlock = pxBlockToInsert;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+    /* If this is the first call to malloc then the heap will require
+     * initialisation to setup the list of free blocks. */
+    if( pxEnd == NULL )
+    {
+        prvHeapInit();
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    {
+        /* The wanted size is increased so it can contain a BlockLink_t
+         * structure in addition to the requested amount of bytes. */
+        if( xWantedSize > 0 )
+        {
+            xWantedSize += xHeapStructSize;
+
+            /* Ensure that blocks are always aligned to the required number of
+             * bytes. */
+            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+            {
+                /* Byte alignment required. */
+                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+        {
+            /* Traverse the list from the start (lowest address) block until
+             * one of adequate size is found. */
+            pxPreviousBlock = &xStart;
+            pxBlock = xStart.pxNextFreeBlock;
+            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+            {
+                pxPreviousBlock = pxBlock;
+                pxBlock = pxBlock->pxNextFreeBlock;
+            }
+
+            /* If the end marker was reached then a block of adequate size was
+             * not found. */
+            if( pxBlock != pxEnd )
+            {
+                /* Return the memory space pointed to - jumping over the
+                 * BlockLink_t structure at its start. */
+                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+                /* This block is being returned for use so must be taken out
+                 * of the list of free blocks. */
+                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+                /* If the block is larger than required it can be split into
+                 * two. */
+                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+                {
+                    /* This block is to be split into two.  Create a new
+                     * block following the number of bytes requested. The void
+                     * cast is used to prevent byte alignment warnings from the
+                     * compiler. */
+                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+                    /* Calculate the sizes of two blocks split from the single
+                     * block. */
+                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+                    pxBlock->xBlockSize = xWantedSize;
+
+                    /* Insert the new block into the list of free blocks. */
+                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+                {
+                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* The block is being returned - it is allocated and owned by
+                 * the application and has no "next" block. */
+                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                pxBlock->pxNextFreeBlock = NULL;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    traceMALLOC( pvReturn, xWantedSize );
+
+    #if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+    {
+        if( pvReturn == NULL )
+        {
+            extern void vApplicationMallocFailedHook( void );
+            vApplicationMallocFailedHook();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    #endif
+
+    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+    return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+    if( pv != NULL )
+    {
+        /* The memory being freed will have an BlockLink_t structure immediately
+         * before it. */
+        puc -= xHeapStructSize;
+
+        /* This casting is to keep the compiler from issuing warnings. */
+        pxLink = ( void * ) puc;
+
+        /* Check the block is actually allocated. */
+        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        {
+            if( pxLink->pxNextFreeBlock == NULL )
+            {
+                /* The block is being returned to the heap - it is no longer
+                 * allocated. */
+                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+                secureportDISABLE_NON_SECURE_INTERRUPTS();
+                {
+                    /* Add this block to the list of free blocks. */
+                    xFreeBytesRemaining += pxLink->xBlockSize;
+                    traceFREE( pv, pxLink->xBlockSize );
+                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+                }
+                secureportENABLE_NON_SECURE_INTERRUPTS();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+    return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+    return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+    /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.h

@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void *pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void *pv );
+
+#endif /* __SECURE_HEAP_H__ */

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.c

@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR                    ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS        ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK        ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR                        ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS            ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK            ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS                ( 26UL )
+#define secureinitFPCCR_TS_MASK                ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR                        ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS            ( 10UL )
+#define secureinitNSACR_CP10_MASK            ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS            ( 11UL )
+#define secureinitNSACR_CP11_MASK            ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+    uint32_t ulIPSR;
+
+     /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        *( secureinitSCB_AIRCR ) =    ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+                                    ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+                                    ( ( 0x1UL    << secureinitSCB_AIRCR_PRIS_POS )    & secureinitSCB_AIRCR_PRIS_MASK );
+    }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+    uint32_t ulIPSR;
+
+     /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+         * permitted. CP11 should be programmed to the same value as CP10. */
+        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+         * that we can enable/disable lazy stacking in port.c file. */
+        *( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
+
+        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+         * registers (S16-S31) are also pushed to stack on exception entry and
+         * restored on exception return. */
+        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+    }
+}
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.h

@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h

@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT                    8
+#define secureportBYTE_ALIGNMENT_MASK                ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+    #define secureportNON_SECURE_CALLABLE            __cmse_nonsecure_entry
+#else
+    #define secureportNON_SECURE_CALLABLE            __attribute__((cmse_nonsecure_entry))
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+    __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+    __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+    __asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+    __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+    __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+    __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+    __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+    __asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL        0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )                        \
+    if( ( x ) == 0 )                                \
+    {                                                \
+        secureportDISABLE_SECURE_INTERRUPTS();        \
+        secureportDISABLE_NON_SECURE_INTERRUPTS();    \
+        for( ;; );                                    \
+    }
+
+#endif /* __SECURE_PORT_MACROS_H__ */

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c

@@ -0,0 +1,897 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if( configENABLE_TRUSTZONE == 1 )
+    /* Secure components includes. */
+    #include "secure_context.h"
+    #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *        configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *        configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *        configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL                ( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD                ( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SYSTICK_CURRENT_VALUE        ( ( volatile uint32_t * ) 0xe000e018 )
+#define portNVIC_INT_CTRL                    ( ( volatile uint32_t * ) 0xe000ed04 )
+#define portNVIC_SYSPRI2                    ( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK                ( 0x00000004 )
+#define portNVIC_SYSTICK_INT                ( 0x00000002 )
+#define portNVIC_SYSTICK_ENABLE                ( 0x00000001 )
+#define portNVIC_PENDSVSET                    ( 0x10000000 )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                    ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                ( portMIN_INTERRUPT_PRIORITY << 24UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( * ( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE            ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR                            ( ( volatile uint32_t * ) 0xe000ed88 )    /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE                ( 3UL )
+#define portCPACR_CP11_VALUE                portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS                    ( 20UL )
+#define portCPACR_CP11_POS                    ( 22UL )
+
+#define portFPCCR                            ( ( volatile uint32_t * ) 0xe000ef34 )    /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS                    ( 31UL )
+#define portFPCCR_ASPEN_MASK                ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS                    ( 30UL )
+#define portFPCCR_LSPEN_MASK                ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG                    ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                    ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                        ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG                    ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                    ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG                    ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                    ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG                    ( * ( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                    ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG                    ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                    ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG                    ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                    ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK            ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK            ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS                ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK                ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS                ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK                ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS                ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK                ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS                ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK                ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS                ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK                ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS                ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK                ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS                ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK                ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS                ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK                ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0            ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1            ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2            ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3            ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4            ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5            ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6            ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7            ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE        ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE                        ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE            ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR                    ( 0x01000000 )
+
+#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         FD
+     * 1111 1111  1111 1111  1111 1111  1111 1101
+     *
+     * Bit[6] - 1 --> The exception was taken from the Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 1 --> The exception was taken to the Secure state.
+     */
+    #define portINITIAL_EXC_RETURN            ( 0xfffffffd )
+#else
+    /**
+     * @brief Initial EXC_RETURN value.
+     *
+     *     FF         FF         FF         BC
+     * 1111 1111  1111 1111  1111 1111  1011 1100
+     *
+     * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+     * Bit[5] - 1 --> Do not skip stacking of additional state context.
+     * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+     * Bit[3] - 1 --> Return to the Thread mode.
+     * Bit[2] - 1 --> Restore registers from the process stack.
+     * Bit[1] - 0 --> Reserved, 0.
+     * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+     */
+    #define portINITIAL_EXC_RETURN            ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK            ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED        ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS            configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS            prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS                1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT                0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if( configENABLE_MPU == 1 )
+    /**
+     * @brief Setup the Memory Protection Unit (MPU).
+     */
+    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if( configENABLE_FPU == 1 )
+    /**
+     * @brief Setup the Floating Point Unit (FPU).
+     */
+    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if( configENABLE_TRUSTZONE == 1 )
+    /**
+     * @brief Saved as part of the task context to indicate which context the
+     * task is using on the secure side.
+     */
+    volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Stop and reset the SysTick. */
+    *( portNVIC_SYSTICK_CTRL ) = 0UL;
+    *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, then stop here so
+     * application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being
+         * defined but never called.  ulDummy is used purely to quieten other
+         * warnings about code appearing after this function is called - making
+         * ulDummy volatile makes the compiler think the function could return
+         * and therefore not output an 'unreachable code' warning for code that
+         * appears after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+    #if defined( __ARMCC_VERSION )
+        /* Declaration when these variable are defined in code instead of being
+         * exported from linker scripts. */
+        extern uint32_t * __privileged_functions_start__;
+        extern uint32_t * __privileged_functions_end__;
+        extern uint32_t * __syscalls_flash_start__;
+        extern uint32_t * __unprivileged_flash_end__;
+        extern uint32_t * __privileged_sram_start__;
+        extern uint32_t * __privileged_sram_end__;
+    #else
+        /* Declaration when these variable are exported from linker scripts. */
+        extern uint32_t __privileged_functions_start__[];
+        extern uint32_t __privileged_functions_end__[];
+        extern uint32_t __syscalls_flash_start__[];
+        extern uint32_t __unprivileged_flash_end__[];
+        extern uint32_t __privileged_sram_start__[];
+        extern uint32_t __privileged_sram_end__[];
+    #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Check that the MPU is present. */
+        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+        {
+            /* MAIR0 - Index 0. */
+            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+            /* MAIR0 - Index 1. */
+            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+            /* Setup privileged flash as Read Only so that privileged tasks can
+             * read it but not modify. */
+            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG =    ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                                ( portMPU_REGION_NON_SHAREABLE ) |
+                                ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+            portMPU_RLAR_REG =    ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                                ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged flash and system calls flash as Read Only by
+             * both privileged and unprivileged tasks. All tasks can read it but
+             * no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG =    ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                                ( portMPU_REGION_NON_SHAREABLE ) |
+                                ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG =    ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                                ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup RAM containing kernel data for privileged access only. */
+            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+            portMPU_RBAR_REG =    ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                                ( portMPU_REGION_NON_SHAREABLE ) |
+                                ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                                ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG =    ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                                ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                ( portMPU_RLAR_REGION_ENABLE );
+
+            /* By default allow everything to access the general peripherals.
+             * The system peripherals and registers are protected. */
+            portMPU_RNR_REG = portUNPRIVILEGED_DEVICE_REGION;
+            portMPU_RBAR_REG =    ( ( ( uint32_t ) portDEVICE_REGION_START_ADDRESS ) & portMPU_RBAR_ADDRESS_MASK ) |
+                                ( portMPU_REGION_NON_SHAREABLE ) |
+                                ( portMPU_REGION_READ_WRITE ) |
+                                ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG =    ( ( ( uint32_t ) portDEVICE_REGION_END_ADDRESS ) & portMPU_RLAR_ADDRESS_MASK ) |
+                                ( portMPU_RLAR_ATTR_INDEX1 ) |
+                                ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Enable mem fault. */
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
+
+            /* Enable MPU with privileged background access i.e. unmapped
+             * regions have privileged access. */
+            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_FPU == 1 )
+    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if( configENABLE_TRUSTZONE == 1 )
+        {
+            /* Enable non-secure access to the FPU. */
+            SecureInit_EnableNSFPUAccess();
+        }
+        #endif /* configENABLE_TRUSTZONE */
+
+        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+         * unprivileged code should be able to access FPU. CP11 should be
+         * programmed to the same value as CP10. */
+        *( portCPACR ) |=    (    ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+                                ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+                            );
+
+        /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+         * context on exception entry and restore on exception return.
+         * LSPEN = 1 ==> Enable lazy context save of FP state. */
+        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+    }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Set a PendSV to request a context switch. */
+    *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile( "dsb" ::: "memory" );
+    __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile( "dsb" ::: "memory" );
+    __asm volatile( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION */
+{
+#if( configENABLE_MPU == 1 )
+    #if defined( __ARMCC_VERSION )
+        /* Declaration when these variable are defined in code instead of being
+         * exported from linker scripts. */
+        extern uint32_t * __syscalls_flash_start__;
+        extern uint32_t * __syscalls_flash_end__;
+    #else
+        /* Declaration when these variable are exported from linker scripts. */
+        extern uint32_t __syscalls_flash_start__[];
+        extern uint32_t __syscalls_flash_end__[];
+    #endif /* defined( __ARMCC_VERSION ) */
+#endif /* configENABLE_MPU */
+
+uint32_t ulPC;
+
+#if( configENABLE_TRUSTZONE == 1 )
+    uint32_t ulR0;
+    #if( configENABLE_MPU == 1 )
+        uint32_t ulControl, ulIsTaskPrivileged;
+    #endif /* configENABLE_MPU */
+#endif /* configENABLE_TRUSTZONE */
+uint8_t ucSVCNumber;
+
+    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+     * R12, LR, PC, xPSR. */
+    ulPC = pulCallerStackAddress[ 6 ];
+    ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        #if( configENABLE_TRUSTZONE == 1 )
+            case portSVC_ALLOCATE_SECURE_CONTEXT:
+            {
+                /* R0 contains the stack size passed as parameter to the
+                 * vPortAllocateSecureContext function. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                #if( configENABLE_MPU == 1 )
+                {
+                    /* Read the CONTROL register value. */
+                    __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+                    /* The task that raised the SVC is privileged if Bit[0]
+                     * in the CONTROL register is 0. */
+                    ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+                    /* Allocate and load a context for the secure task. */
+                    xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+                }
+                #else
+                {
+                    /* Allocate and load a context for the secure task. */
+                    xSecureContext = SecureContext_AllocateContext( ulR0 );
+                }
+                #endif /* configENABLE_MPU */
+
+                configASSERT( xSecureContext != NULL );
+                SecureContext_LoadContext( xSecureContext );
+            }
+            break;
+
+            case portSVC_FREE_SECURE_CONTEXT:
+            {
+                /* R0 contains the secure context handle to be freed. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                /* Free the secure context. */
+                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+            }
+            break;
+        #endif /* configENABLE_TRUSTZONE */
+
+        case portSVC_START_SCHEDULER:
+        {
+            #if( configENABLE_TRUSTZONE == 1 )
+            {
+                /* De-prioritize the non-secure exceptions so that the
+                 * non-secure pendSV runs at the lowest priority. */
+                SecureInit_DePrioritizeNSExceptions();
+
+                /* Initialize the secure context management system. */
+                SecureContext_Init();
+            }
+            #endif /* configENABLE_TRUSTZONE */
+
+            #if( configENABLE_FPU == 1 )
+            {
+                /* Setup the Floating Point Unit (FPU). */
+                prvSetupFPU();
+            }
+            #endif /* configENABLE_FPU */
+
+            /* Setup the context of the first task so that the first task starts
+             * executing. */
+            vRestoreContextOfFirstTask();
+        }
+        break;
+
+        #if( configENABLE_MPU == 1 )
+            case portSVC_RAISE_PRIVILEGE:
+            {
+                /* Only raise the privilege, if the svc was raised from any of
+                 * the system calls. */
+                if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
+                    ulPC <= ( uint32_t ) __syscalls_flash_end__ )
+                {
+                    vRaisePrivilege();
+                }
+            }
+            break;
+        #endif /* configENABLE_MPU */
+
+        default:
+        {
+            /* Incorrect SVC call. */
+            configASSERT( pdFALSE );
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+    StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+    StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    #if( portPRELOAD_REGISTERS == 0 )
+    {
+        pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+        *pxTopOfStack = portINITIAL_XPSR;                            /* xPSR */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pxCode;                        /* PC */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;    /* LR */
+        pxTopOfStack -= 5;                                            /* R12, R3, R2 and R1. */
+        *pxTopOfStack = ( StackType_t ) pvParameters;                /* R0 */
+        pxTopOfStack -= 9;                                            /* R11..R4, EXC_RETURN. */
+        *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+        #if( configENABLE_MPU == 1 )
+        {
+            pxTopOfStack--;
+            if( xRunPrivileged == pdTRUE )
+            {
+                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;        /* Slot used to hold this task's CONTROL value. */
+            }
+            else
+            {
+                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;    /* Slot used to hold this task's CONTROL value. */
+            }
+        }
+        #endif /* configENABLE_MPU */
+
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pxEndOfStack;    /* Slot used to hold this task's PSPLIM value. */
+
+        #if( configENABLE_TRUSTZONE == 1 )
+        {
+            pxTopOfStack--;
+            *pxTopOfStack = portNO_SECURE_CONTEXT;        /* Slot used to hold this task's xSecureContext value. */
+        }
+        #endif /* configENABLE_TRUSTZONE */
+    }
+    #else /* portPRELOAD_REGISTERS */
+    {
+        pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+        *pxTopOfStack = portINITIAL_XPSR;                            /* xPSR */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pxCode;                        /* PC */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;    /* LR */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x12121212UL;                /* R12 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x03030303UL;                /* R3 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x02020202UL;                /* R2 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x01010101UL;                /* R1 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pvParameters;                /* R0 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x11111111UL;                /* R11 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x10101010UL;                /* R10 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x09090909UL;                /* R09 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x08080808UL;                /* R08 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x07070707UL;                /* R07 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x06060606UL;                /* R06 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x05050505UL;                /* R05 */
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) 0x04040404UL;                /* R04 */
+        pxTopOfStack--;
+        *pxTopOfStack = portINITIAL_EXC_RETURN;                        /* EXC_RETURN */
+
+        #if( configENABLE_MPU == 1 )
+        {
+            pxTopOfStack--;
+            if( xRunPrivileged == pdTRUE )
+            {
+                *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;        /* Slot used to hold this task's CONTROL value. */
+            }
+            else
+            {
+                *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;    /* Slot used to hold this task's CONTROL value. */
+            }
+        }
+        #endif /* configENABLE_MPU */
+
+        pxTopOfStack--;
+        *pxTopOfStack = ( StackType_t ) pxEndOfStack;    /* Slot used to hold this task's PSPLIM value. */
+
+        #if( configENABLE_TRUSTZONE == 1 )
+        {
+            pxTopOfStack--;
+            *pxTopOfStack = portNO_SECURE_CONTEXT;        /* Slot used to hold this task's xSecureContext value. */
+        }
+        #endif /* configENABLE_TRUSTZONE */
+    }
+    #endif /* portPRELOAD_REGISTERS */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
+    *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
+
+    #if( configENABLE_MPU == 1 )
+    {
+        /* Setup the Memory Protection Unit (MPU). */
+        prvSetupMPU();
+    }
+    #endif /* configENABLE_MPU */
+
+    /* Start the timer that generates the tick ISR. Interrupts are disabled
+     * here already. */
+    prvSetupTimerInterrupt();
+
+    /* Initialize the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    /* Start the first task. */
+    vStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing. Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. Call
+     * vTaskSwitchContext() so link time optimization does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here. */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
+    {
+    uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+    int32_t lIndex = 0;
+
+        /* Setup MAIR0. */
+        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that
+         * the stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            /* Define the region that allows access to the stack. */
+            ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+            ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+            xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =    ( ulRegionStartAddress ) |
+                                                            ( portMPU_REGION_NON_SHAREABLE ) |
+                                                            ( portMPU_REGION_READ_WRITE ) |
+                                                            ( portMPU_REGION_EXECUTE_NEVER );
+
+            xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =    ( ulRegionEndAddress ) |
+                                                            ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                                            ( portMPU_RLAR_REGION_ENABLE );
+        }
+
+        /* User supplied configurable regions. */
+        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+        {
+            /* If xRegions is NULL i.e. the task has not specified any MPU
+             * region, the else part ensures that all the configurable MPU
+             * regions are invalidated. */
+            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+            {
+                /* Translate the generic region definition contained in xRegions
+                 * into the ARMv8 specific MPU settings that are then stored in
+                 * xMPUSettings. */
+                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+                ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
+
+                /* Start address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =    ( ulRegionStartAddress ) |
+                                                                            ( portMPU_REGION_NON_SHAREABLE );
+
+                /* RO/RW. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+                }
+                else
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+                }
+
+                /* XN. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+                }
+
+                /* End Address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =    ( ulRegionEndAddress ) |
+                                                                            ( portMPU_RLAR_REGION_ENABLE );
+
+                /* Normal memory/ Device memory. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+                {
+                    /* Attr1 in MAIR0 is configured as device memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+                }
+                else
+                {
+                    /* Attr1 in MAIR0 is configured as normal memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+                }
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c

@@ -0,0 +1,285 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Portasm includes. */
+#include "portasm.h"
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    .syntax unified                                    \n"
+    "                                                    \n"
+    "    ldr  r2, pxCurrentTCBConst2                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    "    ldr  r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+    "    ldr  r0, [r1]                                    \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    adds r1, #4                                        \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+    "    ldr  r3, [r1]                                    \n" /* r3 = *r1 i.e. r3 = MAIR0. */
+    "    ldr  r2, xMAIR0Const2                            \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+    "    str  r3, [r2]                                    \n" /* Program MAIR0. */
+    "    ldr  r2, xRNRConst2                                \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+    "    movs r3, #4                                        \n" /* r3 = 4. */
+    "    str  r3, [r2]                                    \n" /* Program RNR = 4. */
+    "    adds r1, #4                                        \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+    "    ldr  r2, xRBARConst2                            \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+    "    ldmia r1!, {r4-r11}                                \n" /* Read 4 set of RBAR/RLAR registers from TCB. */
+    "    stmia r2!, {r4-r11}                                \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    ldm  r0!, {r1-r3}                                \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+    "    msr  psplim, r1                                    \n" /* Set this task's PSPLIM value. */
+    "    msr  control, r2                                \n" /* Set this task's CONTROL value. */
+    "    adds r0, #32                                    \n" /* Discard everything up to r0. */
+    "    msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+    "    isb                                                \n"
+    "    bx   r3                                            \n" /* Finally, branch to EXC_RETURN. */
+    #else /* configENABLE_MPU */
+    "    ldm  r0!, {r1-r2}                                \n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+    "    msr  psplim, r1                                    \n" /* Set this task's PSPLIM value. */
+    "    movs r1, #2                                        \n" /* r1 = 2. */
+    "    msr  CONTROL, r1                                \n" /* Switch to use PSP in the thread mode. */
+    "    adds r0, #32                                    \n" /* Discard everything up to r0. */
+    "    msr  psp, r0                                    \n" /* This is now the new top of stack to use in the task. */
+    "    isb                                                \n"
+    "    bx   r2                                            \n" /* Finally, branch to EXC_RETURN. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    "    .align 4                                        \n"
+    "pxCurrentTCBConst2: .word pxCurrentTCB                \n"
+    #if( configENABLE_MPU == 1 )
+    "xMAIR0Const2: .word 0xe000edc0                        \n"
+    "xRNRConst2: .word 0xe000ed98                        \n"
+    "xRBARConst2: .word 0xe000ed9c                        \n"
+    #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+    "    mrs r0, control                                    \n" /* r0 = CONTROL. */
+    "    tst r0, #1                                        \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+    "    ite ne                                            \n"
+    "    movne r0, #0                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+    "    moveq r0, #1                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+    "    bx lr                                            \n" /* Return. */
+    "                                                    \n"
+    "    .align 4                                        \n"
+    ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+     __asm volatile
+    (
+    "    mrs  r0, control                                \n" /* Read the CONTROL register. */
+    "    bic r0, #1                                        \n" /* Clear the bit 0. */
+    "    msr  control, r0                                \n" /* Write back the new CONTROL value. */
+    "    bx lr                                            \n" /* Return to the caller. */
+    ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+    "    mrs r0, control                                    \n" /* r0 = CONTROL. */
+    "    orr r0, #1                                        \n" /* r0 = r0 | 1. */
+    "    msr control, r0                                    \n" /* CONTROL = r0. */
+    "    bx lr                                            \n" /* Return to the caller. */
+    :::"r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    ldr r0, xVTORConst                                \n" /* Use the NVIC offset register to locate the stack. */
+    "    ldr r0, [r0]                                    \n" /* Read the VTOR register which gives the address of vector table. */
+    "    ldr r0, [r0]                                    \n" /* The first entry in vector table is stack pointer. */
+    "    msr msp, r0                                        \n" /* Set the MSP back to the start of the stack. */
+    "    cpsie i                                            \n" /* Globally enable interrupts. */
+    "    cpsie f                                            \n"
+    "    dsb                                                \n"
+    "    isb                                                \n"
+    "    svc %0                                            \n" /* System call to start the first task. */
+    "    nop                                                \n"
+    "                                                    \n"
+    "   .align 4                                        \n"
+    "xVTORConst: .word 0xe000ed08                        \n"
+    :: "i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    mrs r0, PRIMASK                                    \n"
+    "    cpsid i                                            \n"
+    "    bx lr                                            \n"
+    ::: "memory"
+    );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+    /* To avoid compiler warnings.  The return statement will never be reached,
+     * but some compilers warn if it is not included, while others won't compile
+     * if it is. */
+    return 0;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    msr PRIMASK, r0                                    \n"
+    "    bx lr                                            \n"
+    ::: "memory"
+    );
+
+#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+    /* Just to avoid compiler warning.  ulMask is used from the asm code but
+     * the compiler can't see that.  Some compilers generate warnings without
+     * the following line, while others generate warnings if the line is
+     * included. */
+    ( void ) ulMask;
+#endif
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "    .syntax unified                                    \n"
+    "                                                    \n"
+    "    mrs r0, psp                                        \n" /* Read PSP in r0. */
+    #if( configENABLE_FPU == 1 )
+    "    tst lr, #0x10                                    \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+    "    it eq                                            \n"
+    "    vstmdbeq r0!, {s16-s31}                            \n" /* Store the FPU registers which are not saved automatically. */
+    #endif /* configENABLE_FPU */
+    #if( configENABLE_MPU == 1 )
+    "    mrs r1, psplim                                    \n" /* r1 = PSPLIM. */
+    "    mrs r2, control                                    \n" /* r2 = CONTROL. */
+    "    mov r3, lr                                        \n" /* r3 = LR/EXC_RETURN. */
+    "    stmdb r0!, {r1-r11}                                \n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+    #else /* configENABLE_MPU */
+    "    mrs r2, psplim                                    \n" /* r2 = PSPLIM. */
+    "    mov r3, lr                                        \n" /* r3 = LR/EXC_RETURN. */
+    "    stmdb r0!, {r2-r11}                                \n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    "    ldr r2, pxCurrentTCBConst                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    "    ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+    "    str r0, [r1]                                    \n" /* Save the new top of stack in TCB. */
+    "                                                    \n"
+    "    cpsid i                                            \n"
+    "    bl vTaskSwitchContext                            \n"
+    "    cpsie i                                            \n"
+    "                                                    \n"
+    "    ldr r2, pxCurrentTCBConst                        \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+    "    ldr r1, [r2]                                    \n" /* Read pxCurrentTCB. */
+    "    ldr r0, [r1]                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    adds r1, #4                                        \n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+    "    ldr r3, [r1]                                    \n" /* r3 = *r1 i.e. r3 = MAIR0. */
+    "    ldr r2, xMAIR0Const                                \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
+    "    str r3, [r2]                                    \n" /* Program MAIR0. */
+    "    ldr r2, xRNRConst                                \n" /* r2 = 0xe000ed98 [Location of RNR]. */
+    "    movs r3, #4                                        \n" /* r3 = 4. */
+    "    str r3, [r2]                                    \n" /* Program RNR = 4. */
+    "    adds r1, #4                                        \n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+    "    ldr r2, xRBARConst                                \n" /* r2 = 0xe000ed9c [Location of RBAR]. */
+    "    ldmia r1!, {r4-r11}                                \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
+    "    stmia r2!, {r4-r11}                                \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    ldmia r0!, {r1-r11}                                \n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+    #else /* configENABLE_MPU */
+    "    ldmia r0!, {r2-r11}                                \n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+    #endif /* configENABLE_MPU */
+    "                                                    \n"
+    #if( configENABLE_FPU == 1 )
+    "    tst r3, #0x10                                    \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+    "    it eq                                            \n"
+    "    vldmiaeq r0!, {s16-s31}                            \n" /* Restore the FPU registers which are not restored automatically. */
+    #endif /* configENABLE_FPU */
+    "                                                    \n"
+    #if( configENABLE_MPU == 1 )
+    "    msr psplim, r1                                    \n" /* Restore the PSPLIM register value for the task. */
+    "    msr control, r2                                    \n" /* Restore the CONTROL register value for the task. */
+    #else /* configENABLE_MPU */
+    "    msr psplim, r2                                    \n" /* Restore the PSPLIM register value for the task. */
+    #endif /* configENABLE_MPU */
+    "    msr psp, r0                                        \n" /* Remember the new top of stack for the task. */
+    "    bx r3                                            \n"
+    "                                                    \n"
+    "    .align 4                                        \n"
+    "pxCurrentTCBConst: .word pxCurrentTCB                \n"
+    "xMAIR0Const: .word 0xe000edc0                        \n"
+    "xRNRConst: .word 0xe000ed98                        \n"
+    "xRBARConst: .word 0xe000ed9c                        \n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+    "     tst lr, #4                                        \n"
+    "     ite eq                                            \n"
+    "     mrseq r0, msp                                    \n"
+    "     mrsne r0, psp                                    \n"
+    "     ldr r1, svchandler_address_const                \n"
+    "     bx r1                                            \n"
+    "                                                    \n"
+    "     .align 4                                        \n"
+    "svchandler_address_const: .word vPortSVCHandler_C    \n"
+    );
+}
+/*-----------------------------------------------------------*/

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h

@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h

@@ -0,0 +1,295 @@
+/*
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+#ifndef configENABLE_FPU
+    #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+#endif /* configENABLE_FPU */
+
+#ifndef configENABLE_MPU
+    #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+#endif /* configENABLE_MPU */
+
+#ifndef configENABLE_TRUSTZONE
+    #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+#endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+#define portCHAR                                            char
+#define portFLOAT                                            float
+#define portDOUBLE                                            double
+#define portLONG                                            long
+#define portSHORT                                            short
+#define portSTACK_TYPE                                        uint32_t
+#define portBASE_TYPE                                        long
+
+typedef portSTACK_TYPE                                        StackType_t;
+typedef long                                                BaseType_t;
+typedef unsigned long                                        UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t )                    0xffff
+#else
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t )                    0xffffffffUL
+
+    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+     * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC                            1
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+#define portSTACK_GROWTH                                    ( -1 )
+#define portTICK_PERIOD_MS                                    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT                                    8
+#define portNOP()
+#define portINLINE                                            __inline
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE                                inline __attribute__(( always_inline ))
+#endif
+#define portHAS_STACK_OVERFLOW_CHECKING                        1
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+#if( configENABLE_TRUSTZONE == 1 )
+    extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );
+    extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;
+#endif /* configENABLE_TRUSTZONE */
+
+#if( configENABLE_MPU == 1 )
+    extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+    extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+#if( configENABLE_MPU == 1 )
+    #define portUSING_MPU_WRAPPERS                            1
+    #define portPRIVILEGE_BIT                                ( 0x80000000UL )
+#else
+    #define portPRIVILEGE_BIT                                ( 0x0UL )
+#endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+#define portPRIVILEGED_FLASH_REGION                            ( 0UL )
+#define portUNPRIVILEGED_FLASH_REGION                        ( 1UL )
+#define portPRIVILEGED_RAM_REGION                            ( 2UL )
+#define portUNPRIVILEGED_DEVICE_REGION                        ( 3UL )
+#define portSTACK_REGION                                    ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION                        ( 5UL )
+#define portLAST_CONFIGURABLE_REGION                        ( 7UL )
+#define portNUM_CONFIGURABLE_REGIONS                        ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+#define portTOTAL_NUM_REGIONS                                ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+/* Devices Region. */
+#define portDEVICE_REGION_START_ADDRESS                        ( 0x50000000 )
+#define portDEVICE_REGION_END_ADDRESS                        ( 0x5FFFFFFF )
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *                01 --> Device-nGnRE
+ *                10 --> Device-nGRE
+ *                11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+#define portMPU_DEVICE_MEMORY_nGnRnE                        ( 0x00 ) /* 0000 0000 */
+#define portMPU_DEVICE_MEMORY_nGnRE                            ( 0x04 ) /* 0000 0100 */
+#define portMPU_DEVICE_MEMORY_nGRE                            ( 0x08 ) /* 0000 1000 */
+#define portMPU_DEVICE_MEMORY_GRE                            ( 0x0C ) /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+#define portMPU_NORMAL_MEMORY_NON_CACHEABLE                    ( 0x44 ) /* Non-cacheable. */
+#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE            ( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+#define portMPU_REGION_NON_SHAREABLE                        ( 0UL << 3UL )
+#define portMPU_REGION_INNER_SHAREABLE                        ( 1UL << 3UL )
+#define portMPU_REGION_OUTER_SHAREABLE                        ( 2UL << 3UL )
+
+#define portMPU_REGION_PRIVILEGED_READ_WRITE                ( 0UL << 1UL )
+#define portMPU_REGION_READ_WRITE                            ( 1UL << 1UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY                    ( 2UL << 1UL )
+#define portMPU_REGION_READ_ONLY                            ( 3UL << 1UL )
+
+#define portMPU_REGION_EXECUTE_NEVER                        ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+typedef struct MPURegionSettings
+{
+    uint32_t ulRBAR;    /**< RBAR for the region. */
+    uint32_t ulRLAR;    /**< RLAR for the region. */
+} MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+typedef struct MPU_SETTINGS
+{
+    uint32_t ulMAIR0;    /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+    MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+} xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+#define portSVC_ALLOCATE_SECURE_CONTEXT                        0
+#define portSVC_FREE_SECURE_CONTEXT                            1
+#define portSVC_START_SCHEDULER                                2
+#define portSVC_RAISE_PRIVILEGE                                3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+#define portYIELD()                                            vPortYield()
+#define portNVIC_INT_CTRL_REG                                ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT                                ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )            if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )                                portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+#define portSET_INTERRUPT_MASK_FROM_ISR()                    ulSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)                vClearInterruptMaskFromISR( x )
+#define portDISABLE_INTERRUPTS()                            __asm volatile ( " cpsid i " ::: "memory" )
+#define portENABLE_INTERRUPTS()                                __asm volatile ( " cpsie i " ::: "memory" )
+#define portENTER_CRITICAL()                                vPortEnterCritical()
+#define portEXIT_CRITICAL()                                    vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )        void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_TRUSTZONE == 1 )
+    /**
+     * @brief Allocate a secure context for the task.
+     *
+     * Tasks are not created with a secure context. Any task that is going to call
+     * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+     * secure context before it calls any secure function.
+     *
+     * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+     */
+    #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+    /**
+     * @brief Called when a task is deleted to delete the task's secure context,
+     * if it has one.
+     *
+     * @param[in] pxTCB The TCB of the task being deleted.
+     */
+    #define portCLEAN_UP_TCB( pxTCB )                            vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+#else
+    #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+    #define portCLEAN_UP_TCB( pxTCB )
+#endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+#if( configENABLE_MPU == 1 )
+    /**
+     * @brief Checks whether or not the processor is privileged.
+     *
+     * @return 1 if the processor is already privileged, 0 otherwise.
+     */
+    #define portIS_PRIVILEGED()                                    xIsPrivileged()
+
+    /**
+     * @brief Raise an SVC request to raise privilege.
+     *
+     * The SVC handler checks that the SVC was raised from a system call and only
+     * then it raises the privilege. If this is called from any other place,
+     * the privilege is not raised.
+     */
+    #define portRAISE_PRIVILEGE()                                __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+    /**
+     * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+     * register.
+     */
+    #define portRESET_PRIVILEGE()                                vResetPrivilege()
+#else
+    #define portIS_PRIVILEGED()
+    #define portRAISE_PRIVILEGE()
+    #define portRESET_PRIVILEGE()
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -114,13 +114,6 @@ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
  */
 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
 
-/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
- */
-BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
-
 /*
  * Setup the timer to generate the tick interrupts.  The implementation in this
  * file is weak to allow application writers to change the timer used to
@@ -146,6 +139,35 @@ static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVIL
  */
 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
 
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
 /*-----------------------------------------------------------*/
 
 /* Each task maintains its own interrupt status in the critical nesting
@@ -585,21 +607,33 @@ uint32_t ulRegionSize, ulReturnValue = 4;
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xPortRaisePrivilege( void )
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 {
     __asm volatile
     (
-        "    mrs r0, control                        \n"
-        "    tst r0, #1                            \n" /* Is the task running privileged? */
-        "    itte ne                                \n"
-        "    movne r0, #0                        \n" /* CONTROL[0]!=0, return false. */
-        "    svcne %0                            \n" /* Switch to privileged. */
-        "    moveq r0, #1                        \n" /* CONTROL[0]==0, return true. */
-        "    bx lr                                \n"
-        :: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"
+    "    mrs r0, control                            \n" /* r0 = CONTROL. */
+    "    tst r0, #1                                \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+    "    ite ne                                    \n"
+    "    movne r0, #0                            \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+    "    moveq r0, #1                            \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+    "    bx lr                                    \n" /* Return. */
+    "                                            \n"
+    "    .align 4                                \n"
+    ::: "r0", "memory"
     );
+}
+/*-----------------------------------------------------------*/
 
-    return 0;
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+    "    mrs r0, control                            \n" /* r0 = CONTROL. */
+    "    orr r0, #1                                \n" /* r0 = r0 | 1. */
+    "    msr control, r0                            \n" /* CONTROL = r0. */
+    "    bx lr                                    \n" /* Return to the caller. */
+    :::"r0", "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -200,18 +200,28 @@ not necessary for to use this port.  They are defined so the common demo files
 #ifndef portFORCE_INLINE
     #define portFORCE_INLINE inline __attribute__(( always_inline))
 #endif
+/*-----------------------------------------------------------*/
 
-/* Set the privilege level to user mode if xRunningPrivileged is false. */
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
-    if( xRunningPrivileged != pdTRUE )
-    {
-        __asm volatile ( " mrs r0, control     \n" \
-                         " orr r0, #1         \n" \
-                         " msr control, r0    \n"    \
-                         :::"r0", "memory" );
-    }
-}
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()            xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE()        __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()        vResetPrivilege()
 /*-----------------------------------------------------------*/
 
 portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -123,13 +123,6 @@ static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
  */
 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
 
-/*
- * Checks to see if being called from the context of an unprivileged task, and
- * if so raises the privilege level and returns false - otherwise does nothing
- * other than return true.
- */
-BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
-
 /*
  * Setup the timer to generate the tick interrupts.  The implementation in this
  * file is weak to allow application writers to change the timer used to
@@ -160,6 +153,35 @@ static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline ))
  */
  static void vPortEnableVFP( void ) __attribute__ (( naked ));
 
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__ (( naked ));
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
 /*-----------------------------------------------------------*/
 
 /* Each task maintains its own interrupt status in the critical nesting
@@ -573,7 +595,7 @@ extern uint32_t __privileged_data_end__[];
                                         ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
                                         ( portMPU_REGION_ENABLE );
 
-        /* Setup the first 16K for privileged only access (even though less
+        /* Setup the first nK for privileged only access (even though less
         than 10K is actually being used).  This is where the kernel code is
         placed. */
         portMPU_REGION_BASE_ADDRESS_REG =    ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
@@ -639,21 +661,33 @@ uint32_t ulRegionSize, ulReturnValue = 4;
 }
 /*-----------------------------------------------------------*/
 
-BaseType_t xPortRaisePrivilege( void )
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
 {
     __asm volatile
     (
-        "    mrs r0, control                        \n"
-        "    tst r0, #1                            \n" /* Is the task running privileged? */
-        "    itte ne                                \n"
-        "    movne r0, #0                        \n" /* CONTROL[0]!=0, return false. */
-        "    svcne %0                            \n" /* Switch to privileged. */
-        "    moveq r0, #1                        \n" /* CONTROL[0]==0, return true. */
-        "    bx lr                                \n"
-        :: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"
+    "    mrs r0, control                            \n" /* r0 = CONTROL. */
+    "    tst r0, #1                                \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+    "    ite ne                                    \n"
+    "    movne r0, #0                            \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+    "    moveq r0, #1                            \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+    "    bx lr                                    \n" /* Return. */
+    "                                            \n"
+    "    .align 4                                \n"
+    ::: "r0", "memory"
     );
+}
+/*-----------------------------------------------------------*/
 
-    return 0;
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+    "    mrs r0, control                            \n" /* r0 = CONTROL. */
+    "    orr r0, #1                                \n" /* r0 = r0 | 1. */
+    "    msr control, r0                            \n" /* CONTROL = r0. */
+    "    bx lr                                    \n" /* Return to the caller. */
+    :::"r0", "memory"
+    );
 }
 /*-----------------------------------------------------------*/
 

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in
@@ -200,18 +200,28 @@ not necessary for to use this port.  They are defined so the common demo files
 #ifndef portFORCE_INLINE
     #define portFORCE_INLINE inline __attribute__(( always_inline))
 #endif
+/*-----------------------------------------------------------*/
 
-/* Set the privilege level to user mode if xRunningPrivileged is false. */
-portFORCE_INLINE static void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
-    if( xRunningPrivileged != pdTRUE )
-    {
-        __asm volatile ( " mrs r0, control     \n" \
-                         " orr r0, #1         \n" \
-                         " msr control, r0    \n"    \
-                         :::"r0", "memory" );
-    }
-}
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()            xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+*/
+#define portRAISE_PRIVILEGE()        __asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()        vResetPrivilege()
 /*-----------------------------------------------------------*/
 
 portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h

@@ -1,6 +1,6 @@
 ;/*
-; * FreeRTOS Kernel V10.1.1
-; * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * FreeRTOS Kernel V10.2.0
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
 ; * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s

@@ -1,6 +1,6 @@
 ;/*
-; * FreeRTOS Kernel V10.1.1
-; * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; * FreeRTOS Kernel V10.2.0
+; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
 ; *
 ; * Permission is hereby granted, free of charge, to any person obtaining a copy of
 ; * this software and associated documentation files (the "Software"), to deal in

3rd_party/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h

@@ -1,6 +1,6 @@
 /*
- * FreeRTOS Kernel V10.1.1
- * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ * FreeRTOS Kernel V10.2.0
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a copy of
  * this software and associated documentation files (the "Software"), to deal in