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@@ -1,211 +1,208 @@
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-/***************************************************************************
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- This is a library for the Adafruit MFRC630 Breakout
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-
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- Designed specifically to work with the Adafruit MFRC630 Breakout:
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- http://www.adafruit.com/products/xxx
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-
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- These boards use I2C to communicate, 2 pins are required to interface.
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-
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- Adafruit invests time and resources providing this open source code,
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- please support Adafruit andopen-source hardware by purchasing products
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- from Adafruit!
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-
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- Written by Kevin Townsend for Adafruit Industries.
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- BSD license, all text above must be included in any redistribution
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- ***************************************************************************/
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+/*!
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+ * @file Adafruit_MFRC630_regs.h
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+ */
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#ifndef __ADAFRUIT_MFRC630_REGS_H__
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#define __ADAFRUIT_MFRC630_REGS_H__
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-enum mfrc630reg
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-{
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- MFRC630_REG_COMMAND = 0x00,
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- MFRC630_REG_HOST_CTRL = 0x01,
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- MFRC630_REG_FIFO_CONTROL = 0x02,
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- MFRC630_REG_WATER_LEVEL = 0x03,
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- MFRC630_REG_FIFO_LENGTH = 0x04,
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- MFRC630_REG_FIFO_DATA = 0x05,
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- MFRC630_REG_IRQ0 = 0x06,
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- MFRC630_REG_IRQ1 = 0x07,
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- MFRC630_REG_IRQOEN = 0x08,
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- MFRC630_REG_IRQ1EN = 0x09,
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- MFRC630_REG_ERROR = 0x0A,
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- MFRC630_REG_STATUS = 0x0B,
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- MFRC630_REG_RX_BIT_CTRL = 0x0C,
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- MFRC630_REG_RX_COLL = 0x0D,
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- MFRC630_REG_T_CONTROL = 0x0E,
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- MFRC630_REG_T0_CONTROL = 0x0F,
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- MFRC630_REG_T0_RELOAD_HI = 0x10,
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- MFRC630_REG_TO_RELOAD_LO = 0x11,
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- MFRC630_REG_T0_COUNTER_VAL_HI = 0x12,
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- MFRC630_REG_T0_COUNTER_VAL_LO = 0x13,
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- MFRC630_REG_T1_CONTROL = 0x14,
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- MFRC630_REG_T1_RELOAD_HI = 0x15,
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- MFRC630_REG_T1_RELOAD_LO = 0x16,
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- MFRC630_REG_T1_COUNTER_VAL_HI = 0x17,
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- MFRC630_REG_T1_COUNTER_VAL_LO = 0x18,
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- MFRC630_REG_T2_CONTROL = 0x19,
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- MFRC630_REG_T2_RELOAD_HI = 0x1A,
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- MFRC630_REG_T2_RELOAD_LO = 0x1B,
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- MFRC630_REG_T2_COUNTER_VAL_HI = 0x1C,
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- MFRC630_REG_T2_COUNTER_VAL_LO = 0x1D,
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- MFRC630_REG_T3_CONTROL = 0x1E,
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- MFRC630_REG_T3_RELOAD_HI = 0x1F,
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- MFRC630_REG_T3_RELOAD_LO = 0x20,
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- MFRC630_REG_T3_COUNTER_VAL_HI = 0x21,
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- MFRC630_REG_T3_COUNTER_VAL_LO = 0x22,
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- MFRC630_REG_T4_CONTROL = 0x23,
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- MFRC630_REG_T4_RELOAD_HI = 0x24,
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- MFRC630_REG_T4_RELOAD_LO = 0x25,
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- MFRC630_REG_T4_COUNTER_VAL_HI = 0x26,
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- MFRC630_REG_T4_COUNTER_VAL_LO = 0x27,
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+/*!
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+ * @brief MFRC630 command set
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+ */
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+enum mfrc630reg {
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+ MFRC630_REG_COMMAND = 0x00,
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+ MFRC630_REG_HOST_CTRL = 0x01,
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+ MFRC630_REG_FIFO_CONTROL = 0x02,
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+ MFRC630_REG_WATER_LEVEL = 0x03,
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+ MFRC630_REG_FIFO_LENGTH = 0x04,
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+ MFRC630_REG_FIFO_DATA = 0x05,
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+ MFRC630_REG_IRQ0 = 0x06,
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+ MFRC630_REG_IRQ1 = 0x07,
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+ MFRC630_REG_IRQOEN = 0x08,
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+ MFRC630_REG_IRQ1EN = 0x09,
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+ MFRC630_REG_ERROR = 0x0A,
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+ MFRC630_REG_STATUS = 0x0B,
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+ MFRC630_REG_RX_BIT_CTRL = 0x0C,
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+ MFRC630_REG_RX_COLL = 0x0D,
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+ MFRC630_REG_T_CONTROL = 0x0E,
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+ MFRC630_REG_T0_CONTROL = 0x0F,
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+ MFRC630_REG_T0_RELOAD_HI = 0x10,
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+ MFRC630_REG_TO_RELOAD_LO = 0x11,
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+ MFRC630_REG_T0_COUNTER_VAL_HI = 0x12,
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+ MFRC630_REG_T0_COUNTER_VAL_LO = 0x13,
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+ MFRC630_REG_T1_CONTROL = 0x14,
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+ MFRC630_REG_T1_RELOAD_HI = 0x15,
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+ MFRC630_REG_T1_RELOAD_LO = 0x16,
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+ MFRC630_REG_T1_COUNTER_VAL_HI = 0x17,
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+ MFRC630_REG_T1_COUNTER_VAL_LO = 0x18,
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+ MFRC630_REG_T2_CONTROL = 0x19,
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+ MFRC630_REG_T2_RELOAD_HI = 0x1A,
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+ MFRC630_REG_T2_RELOAD_LO = 0x1B,
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+ MFRC630_REG_T2_COUNTER_VAL_HI = 0x1C,
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+ MFRC630_REG_T2_COUNTER_VAL_LO = 0x1D,
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+ MFRC630_REG_T3_CONTROL = 0x1E,
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+ MFRC630_REG_T3_RELOAD_HI = 0x1F,
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+ MFRC630_REG_T3_RELOAD_LO = 0x20,
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+ MFRC630_REG_T3_COUNTER_VAL_HI = 0x21,
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+ MFRC630_REG_T3_COUNTER_VAL_LO = 0x22,
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+ MFRC630_REG_T4_CONTROL = 0x23,
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+ MFRC630_REG_T4_RELOAD_HI = 0x24,
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+ MFRC630_REG_T4_RELOAD_LO = 0x25,
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+ MFRC630_REG_T4_COUNTER_VAL_HI = 0x26,
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+ MFRC630_REG_T4_COUNTER_VAL_LO = 0x27,
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/* 0x28..0x39 = Antenna Configuration */
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- MFRC630_REG_DRV_MOD = 0x28, /**< (ISO/IEC14443-A 106 = 0x8E) */
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- MFRC630_REG_TX_AMP = 0x29, /**< (ISO/IEC14443-A 106 = 0x12) */
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- MFRC630_REG_DRV_CON = 0x2A, /**< (ISO/IEC14443-A 106 = 0x39) */
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- MFRC630_REG_TXL = 0x2B, /**< (ISO/IEC14443-A 106 = 0x0A) */
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- MFRC630_REG_TX_CRC_PRESET = 0x2C, /**< (ISO/IEC14443-A 106 = 0x18) */
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- MFRC630_REG_RX_CRC_CON = 0x2D, /**< (ISO/IEC14443-A 106 = 0x18) */
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- MFRC630_REG_TX_DATA_NUM = 0x2E, /**< (ISO/IEC14443-A 106 = 0x0F) */
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- MFRC630_REG_TX_MOD_WIDTH = 0x2F, /**< (ISO/IEC14443-A 106 = 0x21) */
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- MFRC630_REG_TX_SYM_10_BURST_LEN = 0x30, /**< (ISO/IEC14443-A 106 = 0x00) */
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- MFRC630_REG_TX_WAIT_CTRL = 0x31, /**< (ISO/IEC14443-A 106 = 0xC0) */
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- MFRC630_REG_TX_WAIT_LO = 0x32, /**< (ISO/IEC14443-A 106 = 0x12) */
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- MFRC630_REG_FRAME_CON = 0x33, /**< (ISO/IEC14443-A 106 = 0xCF) */
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- MFRC630_REG_RX_SOFD = 0x34, /**< (ISO/IEC14443-A 106 = 0x00) */
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- MFRC630_REG_RX_CTRL = 0x35, /**< (ISO/IEC14443-A 106 = 0x04) */
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- MFRC630_REG_RX_WAIT = 0x36, /**< (ISO/IEC14443-A 106 = 0x90) */
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- MFRC630_REG_RX_THRESHOLD = 0x37, /**< (ISO/IEC14443-A 106 = 0x5C) */
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- MFRC630_REG_RCV = 0x38, /**< (ISO/IEC14443-A 106 = 0x12) */
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- MFRC630_REG_RX_ANA = 0x39, /**< (ISO/IEC14443-A 106 = 0x0A) */
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-
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- MFRC630_REG_RFU_LPCD = 0x3A,
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- MFRC630_REG_SERIAL_SPEED = 0x3B,
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- MFRC630_REG_LFO_TRIMM = 0x3C,
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- MFRC630_REG_PLL_CTRL = 0x3D,
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- MFRC630_REG_PLL_DIVOUT = 0x3E,
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- MFRC630_REG_LPCD_QMIN = 0x3F,
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- MFRC630_REG_LPCD_QMAX = 0x40,
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- MFRC630_REG_LPCD_IMIN = 0x41,
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- MFRC630_REG_LPCD_I_RESULT = 0x42,
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- MFRC630_REG_LPCD_Q_RESULT = 0x43,
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- MFRC630_REG_PADEN = 0x44,
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- MFRC630_REG_PADOUT = 0x45,
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- MFRC630_REG_PADIN = 0x46,
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- MFRC630_REG_SIGOUT = 0x47,
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- MFRC630_REG_VERSION = 0x7F
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+ MFRC630_REG_DRV_MOD = 0x28, /**< (ISO/IEC14443-A 106 = 0x8E) */
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+ MFRC630_REG_TX_AMP = 0x29, /**< (ISO/IEC14443-A 106 = 0x12) */
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+ MFRC630_REG_DRV_CON = 0x2A, /**< (ISO/IEC14443-A 106 = 0x39) */
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+ MFRC630_REG_TXL = 0x2B, /**< (ISO/IEC14443-A 106 = 0x0A) */
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+ MFRC630_REG_TX_CRC_PRESET = 0x2C, /**< (ISO/IEC14443-A 106 = 0x18) */
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+ MFRC630_REG_RX_CRC_CON = 0x2D, /**< (ISO/IEC14443-A 106 = 0x18) */
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+ MFRC630_REG_TX_DATA_NUM = 0x2E, /**< (ISO/IEC14443-A 106 = 0x0F) */
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+ MFRC630_REG_TX_MOD_WIDTH = 0x2F, /**< (ISO/IEC14443-A 106 = 0x21) */
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+ MFRC630_REG_TX_SYM_10_BURST_LEN = 0x30, /**< (ISO/IEC14443-A 106 = 0x00) */
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+ MFRC630_REG_TX_WAIT_CTRL = 0x31, /**< (ISO/IEC14443-A 106 = 0xC0) */
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+ MFRC630_REG_TX_WAIT_LO = 0x32, /**< (ISO/IEC14443-A 106 = 0x12) */
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+ MFRC630_REG_FRAME_CON = 0x33, /**< (ISO/IEC14443-A 106 = 0xCF) */
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+ MFRC630_REG_RX_SOFD = 0x34, /**< (ISO/IEC14443-A 106 = 0x00) */
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+ MFRC630_REG_RX_CTRL = 0x35, /**< (ISO/IEC14443-A 106 = 0x04) */
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+ MFRC630_REG_RX_WAIT = 0x36, /**< (ISO/IEC14443-A 106 = 0x90) */
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+ MFRC630_REG_RX_THRESHOLD = 0x37, /**< (ISO/IEC14443-A 106 = 0x5C) */
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+ MFRC630_REG_RCV = 0x38, /**< (ISO/IEC14443-A 106 = 0x12) */
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+ MFRC630_REG_RX_ANA = 0x39, /**< (ISO/IEC14443-A 106 = 0x0A) */
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+
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+ MFRC630_REG_RFU_LPCD = 0x3A,
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+ MFRC630_REG_SERIAL_SPEED = 0x3B,
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+ MFRC630_REG_LFO_TRIMM = 0x3C,
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+ MFRC630_REG_PLL_CTRL = 0x3D,
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+ MFRC630_REG_PLL_DIVOUT = 0x3E,
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+ MFRC630_REG_LPCD_QMIN = 0x3F,
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+ MFRC630_REG_LPCD_QMAX = 0x40,
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+ MFRC630_REG_LPCD_IMIN = 0x41,
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+ MFRC630_REG_LPCD_I_RESULT = 0x42,
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+ MFRC630_REG_LPCD_Q_RESULT = 0x43,
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+ MFRC630_REG_PADEN = 0x44,
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+ MFRC630_REG_PADOUT = 0x45,
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+ MFRC630_REG_PADIN = 0x46,
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+ MFRC630_REG_SIGOUT = 0x47,
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+ MFRC630_REG_VERSION = 0x7F
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};
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-/* See Table 7.10.2: Command Set */
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-enum mfrc630cmd
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-{
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- MFRC630_CMD_IDLE = 0x00, /**< Cancels current command */
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- MFRC630_CMD_LPCD = 0x01, /**< Low power card detection */
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- MFRC630_CMD_LOADKEY = 0x02, /**< Reads a 6 byte MIFARE key and puts it into KEY BUFFER */
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- MFRC630_CMD_MFAUTHENT = 0x03, /**< Performs Mifare Classic authentication */
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- MFRC630_CMD_RECEIVE = 0x05, /**< Activates the receive circuit */
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- MFRC630_CMD_TRANSMIT = 0x06, /**< Transmits data from the FIFO buffer */
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- MFRC630_CMD_TRANSCEIVE = 0x07, /**< Transmits data from the FIFO buffer and automatically activates the receive buffer when finished */
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- MFRC630_CMD_WRITEE2 = 0x08, /**< Gets 1 byte from FIFO and writes to EEPROM */
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- MFRC630_CMD_WRITEE2PAGE = 0x09, /**< Gets up to 64 bytes from FIFO and writes to EEPROM */
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- MFRC630_CMD_READE2 = 0x0A, /**< Reads data from EEPROM and copies it into the FIFO buffer */
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- MFRC630_CMD_LOADREG = 0x0C, /**< Reads data from the internal EEPROM and initializes the MFRC630 registers. EEPROM address needs to be within EEPROM sector 2 */
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- MFRC630_CMD_LOADPROTOCOL = 0x0D, /**< Reads data from the internal EEPROM and initializes the MFRC630 registers needed for a protocol change. */
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- MFRC630_CMD_LOADKEYE2 = 0x0E, /**< Copies a key from EEPROM into the key buffer */
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- MFRC630_CMD_STOREKEYE2 = 0x0F, /**< Stores a MIFARE key (6 bytes) into EEPROM */
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- MFRC630_CMD_READRNR = 0x1C, /**< Copies bytes from the random number generator into the FIFO buffer until the FIFO is full */
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- MFRC630_CMD_SOFTRESET = 0x1F /**< SW resets the MFRC630 */
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+/*! See Table 7.10.2: Command Set */
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+enum mfrc630cmd {
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+ MFRC630_CMD_IDLE = 0x00, /**< Cancels current command */
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+ MFRC630_CMD_LPCD = 0x01, /**< Low power card detection */
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+ MFRC630_CMD_LOADKEY =
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+ 0x02, /**< Reads a 6 byte MIFARE key and puts it into KEY BUFFER */
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+ MFRC630_CMD_MFAUTHENT = 0x03, /**< Performs Mifare Classic authentication */
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+ MFRC630_CMD_RECEIVE = 0x05, /**< Activates the receive circuit */
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+ MFRC630_CMD_TRANSMIT = 0x06, /**< Transmits data from the FIFO buffer */
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+ MFRC630_CMD_TRANSCEIVE =
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+ 0x07, /**< Transmits data from the FIFO buffer and automatically activates
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+ the receive buffer when finished */
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+ MFRC630_CMD_WRITEE2 = 0x08, /**< Gets 1 byte from FIFO and writes to EEPROM */
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+ MFRC630_CMD_WRITEE2PAGE =
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+ 0x09, /**< Gets up to 64 bytes from FIFO and writes to EEPROM */
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+ MFRC630_CMD_READE2 =
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+ 0x0A, /**< Reads data from EEPROM and copies it into the FIFO buffer */
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+ MFRC630_CMD_LOADREG =
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+ 0x0C, /**< Reads data from the internal EEPROM and initializes the MFRC630
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+ registers. EEPROM address needs to be within EEPROM sector 2 */
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+ MFRC630_CMD_LOADPROTOCOL =
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+ 0x0D, /**< Reads data from the internal EEPROM and initializes the MFRC630
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+ registers needed for a protocol change. */
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+ MFRC630_CMD_LOADKEYE2 =
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+ 0x0E, /**< Copies a key from EEPROM into the key buffer */
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+ MFRC630_CMD_STOREKEYE2 =
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+ 0x0F, /**< Stores a MIFARE key (6 bytes) into EEPROM */
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+ MFRC630_CMD_READRNR = 0x1C, /**< Copies bytes from the random number generator
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+ into the FIFO buffer until the FIFO is full */
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+ MFRC630_CMD_SOFTRESET = 0x1F /**< SW resets the MFRC630 */
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};
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-/* ISO14443 Commands (see ISO-14443-3) */
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-enum iso14443_cmd
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-{
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- ISO14443_CMD_REQA = 0x26, /**< Request command. */
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- ISO14443_CMD_WUPA = 0x52, /**< Wakeup command. */
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- ISO14443_CAS_LEVEL_1 = 0x93, /**< Anticollision cascade level 1. */
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- ISO14443_CAS_LEVEL_2 = 0x95, /**< Anticollision cascade level 2. */
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- ISO14443_CAS_LEVEL_3 = 0x97 /**< Anticollision cascade level 3. */
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+/*! ISO14443 Commands (see ISO-14443-3) */
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+enum iso14443_cmd {
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+ ISO14443_CMD_REQA = 0x26, /**< Request command. */
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+ ISO14443_CMD_WUPA = 0x52, /**< Wakeup command. */
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+ ISO14443_CAS_LEVEL_1 = 0x93, /**< Anticollision cascade level 1. */
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+ ISO14443_CAS_LEVEL_2 = 0x95, /**< Anticollision cascade level 2. */
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+ ISO14443_CAS_LEVEL_3 = 0x97 /**< Anticollision cascade level 3. */
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};
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-/* Mifare Commands */
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-enum mifare_cmd
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-{
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- MIFARE_CMD_AUTH_A = 0x60,
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- MIFARE_CMD_AUTH_B = 0x61,
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- MIFARE_CMD_READ = 0x30,
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- MIFARE_CMD_WRITE = 0xA0,
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- MIFARE_CMD_TRANSFER = 0xB0,
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- MIFARE_CMD_DECREMENT = 0xC0,
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- MIFARE_CMD_INCREMENT = 0xC1,
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- MIFARE_CMD_STORE = 0xC2,
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- MIFARE_ULTRALIGHT_CMD_WRITE = 0xA2
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+/*! Mifare Commands */
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+enum mifare_cmd {
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+ MIFARE_CMD_AUTH_A = 0x60,
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+ MIFARE_CMD_AUTH_B = 0x61,
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+ MIFARE_CMD_READ = 0x30,
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+ MIFARE_CMD_WRITE = 0xA0,
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+ MIFARE_CMD_TRANSFER = 0xB0,
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+ MIFARE_CMD_DECREMENT = 0xC0,
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+ MIFARE_CMD_INCREMENT = 0xC1,
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+ MIFARE_CMD_STORE = 0xC2,
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+ MIFARE_ULTRALIGHT_CMD_WRITE = 0xA2
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};
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-/* NTAG Commands */
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-enum ntag_cmd
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-{
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- NTAG_CMD_READ = 0x30, /**> NTAG page read. */
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- NTAG_CMD_WRITE = 0xA2, /**< NTAG-specfiic 4 byte write. */
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- NTAG_CMD_COMP_WRITE = 0xA0 /**< Mifare Classic 16-byte compat. write. */
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+/*! NTAG Commands */
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+enum ntag_cmd {
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+ NTAG_CMD_READ = 0x30, /**> NTAG page read. */
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+ NTAG_CMD_WRITE = 0xA2, /**< NTAG-specfiic 4 byte write. */
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+ NTAG_CMD_COMP_WRITE = 0xA0 /**< Mifare Classic 16-byte compat. write. */
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};
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-/* 'ComState' values for for the MFRC630_REG_STATUS register (0x0B) */
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-enum mfrc630comstat
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-{
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- MFRC630_COMSTAT_IDLE = 0b000, /**< IDLE */
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- MFRC630_COMSTAT_TXWAIT = 0b001, /**< TX Wait */
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- MFRC630_COMSTAT_TRANSMITTING = 0b011, /**< Transmitting */
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- MFRC630_COMSTAT_RXWAIT = 0b101, /**< RX Wait */
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- MFRC630_COMSTAT_WAITFORDATA = 0b110, /**< Waiting for DATA */
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- MFRC630_COMSTAT_RECEIVING = 0b111 /**< Receiving */
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+/*! 'ComState' values for for the MFRC630_REG_STATUS register (0x0B) */
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+enum mfrc630comstat {
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+ MFRC630_COMSTAT_IDLE = 0b000, /**< IDLE */
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+ MFRC630_COMSTAT_TXWAIT = 0b001, /**< TX Wait */
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+ MFRC630_COMSTAT_TRANSMITTING = 0b011, /**< Transmitting */
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+ MFRC630_COMSTAT_RXWAIT = 0b101, /**< RX Wait */
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+ MFRC630_COMSTAT_WAITFORDATA = 0b110, /**< Waiting for DATA */
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+ MFRC630_COMSTAT_RECEIVING = 0b111 /**< Receiving */
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};
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-/* Radio config modes */
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-enum mfrc630radiocfg
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-{
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- MFRC630_RADIOCFG_ISO1443A_106 = 1, /**< ISO1443A 106 Mode */
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+/*! Radio config modes */
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+enum mfrc630radiocfg {
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+ MFRC630_RADIOCFG_ISO1443A_106 = 1, /**< ISO1443A 106 Mode */
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MFRC630_LAST
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};
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-enum mfrc630errors
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-{
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- MFRC630_ERROR_EEPROM = (1 << 7), /**< EEPROM error. */
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- MFRC630_ERROR_FIFOWR = (1 << 6), /**< FIFO write error. */
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- MFRC630_ERROR_FIFOOVL = (1 << 5), /**< FIFO already full! */
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- MFRC630_ERROR_MINFRAME = (1 << 4), /**< Not enough data in frame. */
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- MFRC630_ERROR_NODATA = (1 << 3), /**< FIFO empty! */
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- MFRC630_ERROR_COLLDET = (1 << 2), /**< Collision detection, see RxColl. */
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- MFRC630_ERROR_PROT = (1 << 1), /**< Protocol error. */
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- MFRC630_ERROR_INTEG = (1 << 0) /**< Data integrity error. */
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+/*! MFRC360 errors */
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+enum mfrc630errors {
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+ MFRC630_ERROR_EEPROM = (1 << 7), /**< EEPROM error. */
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+ MFRC630_ERROR_FIFOWR = (1 << 6), /**< FIFO write error. */
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+ MFRC630_ERROR_FIFOOVL = (1 << 5), /**< FIFO already full! */
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+ MFRC630_ERROR_MINFRAME = (1 << 4), /**< Not enough data in frame. */
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+ MFRC630_ERROR_NODATA = (1 << 3), /**< FIFO empty! */
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+ MFRC630_ERROR_COLLDET = (1 << 2), /**< Collision detection, see RxColl. */
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+ MFRC630_ERROR_PROT = (1 << 1), /**< Protocol error. */
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+ MFRC630_ERROR_INTEG = (1 << 0) /**< Data integrity error. */
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};
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-enum mfrc630irq0
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-{
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- MFRC630IRQ0_SET = (1 << 7), /**< Sets/Clears interrupt. */
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- MFRC630IRQ0_HIALERTIRQ = (1 << 6), /**< FIFO has reached top level. */
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- MFRC630IRQ0_LOALERTIRQ = (1 << 5), /**< FIFO has reached bottom level. */
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- MFRC630IRQ0_IDLEIRQ = (1 << 4), /**< Command terminated by itself. */
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- MFRC630IRQ0_TXIRQ = (1 << 3), /**< Data transmission complete */
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- MFRC630IRQ0_RXIRQ = (1 << 2), /**< Receiver detected end of stream */
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- MFRC630IRQ0_ERRIRQ = (1 << 1), /**< FifoWrErr, FiFoOvl, ProtErr, NoDataErr, IntegErr. */
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- MFRC630IRQ0_RXSOF = (1 << 0) /**< RX start of frame detected. */
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+/*! MFRC630 interrupt requests 0 */
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+enum mfrc630irq0 {
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+ MFRC630IRQ0_SET = (1 << 7), /**< Sets/Clears interrupt. */
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+ MFRC630IRQ0_HIALERTIRQ = (1 << 6), /**< FIFO has reached top level. */
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+ MFRC630IRQ0_LOALERTIRQ = (1 << 5), /**< FIFO has reached bottom level. */
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+ MFRC630IRQ0_IDLEIRQ = (1 << 4), /**< Command terminated by itself. */
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+ MFRC630IRQ0_TXIRQ = (1 << 3), /**< Data transmission complete */
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+ MFRC630IRQ0_RXIRQ = (1 << 2), /**< Receiver detected end of stream */
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+ MFRC630IRQ0_ERRIRQ =
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+ (1 << 1), /**< FifoWrErr, FiFoOvl, ProtErr, NoDataErr, IntegErr. */
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+ MFRC630IRQ0_RXSOF = (1 << 0) /**< RX start of frame detected. */
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};
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-enum mfrc630irq1
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-{
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- MFRC630IRQ1_SET = (1 << 7), /**< Sets/Clears interrupt. */
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- MFRC630IRQ1_GLOBALIRQ = (1 << 6), /**< Set if an enabled IRQ occured */
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- MFRC630IRQ1_LPCDIRQ = (1 << 5), /**< Card detected in low power mode */
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- MFRC630IRQ1_TIMER4IRQ = (1 << 4), /**< Timer 4 underflow */
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- MFRC630IRQ1_TIMER3IRQ = (1 << 3), /**< Timer 3 underflow */
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- MFRC630IRQ1_TIMER2IRQ = (1 << 2), /**< Timer 2 underflow */
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- MFRC630IRQ1_TIMER1IRQ = (1 << 1), /**< Timer 1 underflow */
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- MFRC630IRQ1_TIMER0IRQ = (1 << 0), /**< Timer 0 underflow */
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+/*! MFRC630 interrupt requests 1 */
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+enum mfrc630irq1 {
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|
+ MFRC630IRQ1_SET = (1 << 7), /**< Sets/Clears interrupt. */
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+ MFRC630IRQ1_GLOBALIRQ = (1 << 6), /**< Set if an enabled IRQ occured */
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+ MFRC630IRQ1_LPCDIRQ = (1 << 5), /**< Card detected in low power mode */
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+ MFRC630IRQ1_TIMER4IRQ = (1 << 4), /**< Timer 4 underflow */
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+ MFRC630IRQ1_TIMER3IRQ = (1 << 3), /**< Timer 3 underflow */
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+ MFRC630IRQ1_TIMER2IRQ = (1 << 2), /**< Timer 2 underflow */
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+ MFRC630IRQ1_TIMER1IRQ = (1 << 1), /**< Timer 1 underflow */
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|
|
+ MFRC630IRQ1_TIMER0IRQ = (1 << 0), /**< Timer 0 underflow */
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|
|
};
|
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|
|
|
-enum mfrc630status
|
|
|
-{
|
|
|
- MFRC630STATUS_CRYPTO1ON = (1 << 5) /**< Mifare Classic Crypto engine on */
|
|
|
+/*! MFRC630 crypto engine status */
|
|
|
+enum mfrc630status {
|
|
|
+ MFRC630STATUS_CRYPTO1ON = (1 << 5) /**< Mifare Classic Crypto engine on */
|
|
|
};
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#endif
|