Fix Zifencei extension issue in RISC-V (#2807)

Refer to:
https://github.com/bytecodealliance/wasm-micro-runtime/pull/2805

core/iwasm/aot/arch/aot_reloc_riscv.c

@@ -177,7 +177,11 @@ rv_set_val(uint16 *addr, uint32 val)
     *addr = (val & 0xffff);
     *(addr + 1) = (val >> 16);
 
+#ifdef __riscv_zifencei
     __asm__ volatile("fence.i");
+#else
+    __asm__ volatile("fence");
+#endif
 }
 
 /* Add a val to given address */