invokeNative_arm.s 2.0 KB

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  1. /*
  2. * Copyright (C) 2019 Intel Corporation. All rights reserved.
  3. *
  4. * Licensed under the Apache License, Version 2.0 (the "License");
  5. * you may not use this file except in compliance with the License.
  6. * You may obtain a copy of the License at
  7. *
  8. * http://www.apache.org/licenses/LICENSE-2.0
  9. *
  10. * Unless required by applicable law or agreed to in writing, software
  11. * distributed under the License is distributed on an "AS IS" BASIS,
  12. * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13. * See the License for the specific language governing permissions and
  14. * limitations under the License.
  15. */
  16. .text
  17. .align 2
  18. .global invokeNative
  19. .type invokeNative,function
  20. /*
  21. * Arguments passed in:
  22. *
  23. * r0 argv
  24. * r1 argc
  25. * r2 function pntr
  26. */
  27. invokeNative:
  28. stmfd sp!, {r4, r5, r6, r7, lr}
  29. mov r4, r0 /* get argv */
  30. mov r5, r1 /* get argc */
  31. mov ip, r2 /* get function ptr */
  32. cmp r5, #2 /* is argc < 2 ? */
  33. blt return
  34. ldr r0, [r4], #4 /* argv[0] */
  35. ldr r1, [r4], #4 /* argv[1] */
  36. mov r6, #0
  37. cmp r5, #2
  38. beq call_func
  39. ldr r2, [r4], #4
  40. cmp r5, #3
  41. beq call_func
  42. ldr r3, [r4], #4
  43. subs r5, r5, #4 /* now we have r0 ~ r3 */
  44. /* Ensure address is 8 byte aligned */
  45. mov r6, r5, lsl#2
  46. add r6, r6, #7
  47. bic r6, r6, #7
  48. add r6, r6, #4 /* +4 because only odd(5) registers are in stack */
  49. subs sp, sp, r6 /* for stacked args */
  50. mov r7, sp
  51. loop_args:
  52. cmp r5, #0
  53. beq call_func
  54. ldr lr, [r4], #4
  55. str lr, [r7], #4
  56. subs r5, r5, #1
  57. b loop_args
  58. call_func:
  59. blx ip
  60. add sp, sp, r6 /* recover sp */
  61. return:
  62. ldmfd sp!, {r4, r5, r6, r7, lr}
  63. bx lr