update: update esc register

Signed-off-by: sakumisu <1203593632@qq.com>

include/esc_register.h

@@ -4138,31 +4138,31 @@ typedef struct {
 #define ESC_PHY_CFG1_REFCK_25M_INV_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_REFCK_25M_INV_MASK) >> ESC_PHY_CFG1_REFCK_25M_INV_SHIFT)
 
 /*
- * RMII_P2_RXCK_REFCLK_OE (RW)
+ * RMII_P2_TXCK_REFCLK_OE (RW)
  *
  */
-#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK (0x40U)
-#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT (6U)
-#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK)
-#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT)
+#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK (0x40U)
+#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT (6U)
+#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK)
+#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT)
 
 /*
- * RMII_P1_RXCK_REFCLK_OE (RW)
+ * RMII_P1_TXCK_REFCLK_OE (RW)
  *
  */
-#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK (0x20U)
-#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT (5U)
-#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK)
-#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT)
+#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK (0x20U)
+#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT (5U)
+#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK)
+#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT)
 
 /*
- * RMII_P0_RXCK_REFCLK_OE (RW)
+ * RMII_P0_TXCK_REFCLK_OE (RW)
  *
  */
-#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK (0x10U)
-#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT (4U)
-#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK)
-#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT)
+#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK (0x10U)
+#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT (4U)
+#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK)
+#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT)
 
 /*
  * REFCK_25M_OE (RW)
@@ -4174,31 +4174,31 @@ typedef struct {
 #define ESC_PHY_CFG1_REFCK_25M_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_REFCK_25M_OE_MASK) >> ESC_PHY_CFG1_REFCK_25M_OE_SHIFT)
 
 /*
- * RMII_P2_TXCK_REFCLK_OE (RW)
+ * RMII_P2_RXCK_REFCLK_OE (RW)
  *
  */
-#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK (0x4U)
-#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT (2U)
-#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK)
-#define ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P2_TXCK_REFCLK_OE_SHIFT)
+#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK (0x4U)
+#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT (2U)
+#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK)
+#define ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P2_RXCK_REFCLK_OE_SHIFT)
 
 /*
- * RMII_P1_TXCK_REFCLK_OE (RW)
+ * RMII_P1_RXCK_REFCLK_OE (RW)
  *
  */
-#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK (0x2U)
-#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT (1U)
-#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK)
-#define ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P1_TXCK_REFCLK_OE_SHIFT)
+#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK (0x2U)
+#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT (1U)
+#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK)
+#define ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P1_RXCK_REFCLK_OE_SHIFT)
 
 /*
- * RMII_P0_TXCK_REFCLK_OE (RW)
+ * RMII_P0_RXCK_REFCLK_OE (RW)
  *
  */
-#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK (0x1U)
-#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT (0U)
-#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK)
-#define ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P0_TXCK_REFCLK_OE_SHIFT)
+#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK (0x1U)
+#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT (0U)
+#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SET(x) (((uint32_t)(x) << ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT) & ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK)
+#define ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_GET(x) (((uint32_t)(x) & ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_MASK) >> ESC_PHY_CFG1_RMII_P0_RXCK_REFCLK_OE_SHIFT)
 
 /* Bitfield definition for register: GPIO_CTRL */
 /*