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@@ -218,7 +218,7 @@
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// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4)
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/* IN Endpoints Max packet Size / 4 */
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// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4)
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-// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4)
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+// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (1024 / 4)
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// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4)
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// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4)
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// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4)
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@@ -227,6 +227,8 @@
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// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4)
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// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4)
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+// #define CONFIG_USB_DWC2_DMA_ENABLE
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+
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/* ---------------- MUSB Configuration ---------------- */
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// #define CONFIG_USB_MUSB_SUNXI
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