update(port/dwc2): rename struct name to avoid duplicate definitions

port/dwc2/usb_dc_dwc2.c

@@ -95,11 +95,11 @@
 
 #define USBD_BASE (g_usbdev_bus[0].reg_base)
 
-#define USB_OTG_GLB      ((USB_OTG_GlobalTypeDef *)(USBD_BASE))
-#define USB_OTG_DEV      ((USB_OTG_DeviceTypeDef *)(USBD_BASE + USB_OTG_DEVICE_BASE))
+#define USB_OTG_GLB      ((DWC2_GlobalTypeDef *)(USBD_BASE))
+#define USB_OTG_DEV      ((DWC2_DeviceTypeDef *)(USBD_BASE + USB_OTG_DEVICE_BASE))
 #define USB_OTG_PCGCCTL  *(__IO uint32_t *)((uint32_t)USBD_BASE + USB_OTG_PCGCCTL_BASE)
-#define USB_OTG_INEP(i)  ((USB_OTG_INEndpointTypeDef *)(USBD_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE)))
-#define USB_OTG_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBD_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE)))
+#define USB_OTG_INEP(i)  ((DWC2_INEndpointTypeDef *)(USBD_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE)))
+#define USB_OTG_OUTEP(i) ((DWC2_OUTEndpointTypeDef *)(USBD_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE)))
 #define USB_OTG_FIFO(i)  *(__IO uint32_t *)(USBD_BASE + USB_OTG_FIFO_BASE + ((i)*USB_OTG_FIFO_SIZE))
 
 extern uint32_t SystemCoreClock;

port/dwc2/usb_dwc2_reg.h

@@ -39,7 +39,7 @@ typedef struct
     uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */
   __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
   __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */
-} USB_OTG_GlobalTypeDef;
+} DWC2_GlobalTypeDef;
 
 /**
   * @brief USB_OTG_device_Registers
@@ -66,7 +66,7 @@ typedef struct
   __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
   uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
   __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
-} USB_OTG_DeviceTypeDef;
+} DWC2_DeviceTypeDef;
 
 /**
   * @brief USB_OTG_IN_Endpoint-Specific_Register
@@ -81,7 +81,7 @@ typedef struct
   __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
   __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
   uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
+} DWC2_INEndpointTypeDef;
 
 /**
   * @brief USB_OTG_OUT_Endpoint-Specific_Registers
@@ -95,7 +95,7 @@ typedef struct
   __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
   __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
   uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
+} DWC2_OUTEndpointTypeDef;
 
 /**
   * @brief USB_OTG_Host_Mode_Register_Structures
@@ -112,7 +112,7 @@ typedef struct
   __IO uint32_t HFLBADDR;         /*!< Host frame list base address register 41Ch */
   uint32_t Reserved420[8];        /*!< Reserved                              420h */
   __IO uint32_t HPRT;             /*!< Host port control and status register 440h */
-} USB_OTG_HostTypeDef;
+} DWC2_HostTypeDef;
 
 /**
   * @brief USB_OTG_Host_Channel_Specific_Registers
@@ -128,7 +128,7 @@ typedef struct
   uint32_t Reserved0;             /*!< Reserved                                 518h */
   __IO uint32_t HCDMAB;           /*!< Host Channel DMA Address Buffer Register 51Ch */
   uint32_t Reserved[2];           /*!< Reserved                                      */
-} USB_OTG_HostChannelTypeDef;
+} DWC2_HostChannelTypeDef;
 
 #define USB_OTG_GLOBAL_BASE                  0x000UL
 #define USB_OTG_DEVICE_BASE                  0x800UL

port/dwc2/usb_glue_st.c

@@ -153,7 +153,7 @@ static int usb_hsphy_init(uint32_t hse_value)
 uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base)
 {
 #if __has_include("stm32h7xx.h") || __has_include("stm32f7xx.h") || __has_include("stm32l4xx.h")
-#define USB_OTG_GLB ((USB_OTG_GlobalTypeDef *)(reg_base))
+#define USB_OTG_GLB ((DWC2_GlobalTypeDef *)(reg_base))
     /* B-peripheral session valid override enable */
     USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
     USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
@@ -179,7 +179,7 @@ uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base)
 uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base)
 {
 #if __has_include("stm32h7xx.h") || __has_include("stm32f7xx.h") || __has_include("stm32l4xx.h")
-#define USB_OTG_GLB ((USB_OTG_GlobalTypeDef *)(reg_base))
+#define USB_OTG_GLB ((DWC2_GlobalTypeDef *)(reg_base))
     /* B-peripheral session valid override enable */
     USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOEN;
     USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL;

port/dwc2/usb_hc_dwc2.c

@@ -29,12 +29,11 @@
 #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE) / 4)
 #endif
 
-#define USB_OTG_GLB     ((USB_OTG_GlobalTypeDef *)(bus->hcd.reg_base))
+#define USB_OTG_GLB     ((DWC2_GlobalTypeDef *)(bus->hcd.reg_base))
 #define USB_OTG_PCGCCTL *(__IO uint32_t *)((uint32_t)bus->hcd.reg_base + USB_OTG_PCGCCTL_BASE)
 #define USB_OTG_HPRT    *(__IO uint32_t *)((uint32_t)bus->hcd.reg_base + USB_OTG_HOST_PORT_BASE)
-#define USB_OTG_HOST    ((USB_OTG_HostTypeDef *)(bus->hcd.reg_base + USB_OTG_HOST_BASE))
-#define USB_OTG_HC(i)   ((USB_OTG_HostChannelTypeDef *)(bus->hcd.reg_base + USB_OTG_HOST_CHANNEL_BASE + ((i)*USB_OTG_HOST_CHANNEL_SIZE)))
-#define USB_OTG_FIFO(i) *(__IO uint32_t *)(bus->hcd.reg_base + USB_OTG_FIFO_BASE + ((i)*USB_OTG_FIFO_SIZE))
+#define USB_OTG_HOST    ((DWC2_HostTypeDef *)(bus->hcd.reg_base + USB_OTG_HOST_BASE))
+#define USB_OTG_HC(i)   ((DWC2_HostChannelTypeDef *)(bus->hcd.reg_base + USB_OTG_HOST_CHANNEL_BASE + ((i)*USB_OTG_HOST_CHANNEL_SIZE)))
 
 struct dwc2_chan {
     uint8_t ep0_state;