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@@ -17,24 +17,27 @@
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#define USBD_IRQHandler OTG_HS_IRQHandler
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#define USBD_IRQHandler OTG_HS_IRQHandler
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#endif
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#endif
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+#ifndef USB_NUM_BIDIR_ENDPOINTS
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+#define USB_NUM_BIDIR_ENDPOINTS 6 /* define with minimum value*/
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+#endif
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+
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#ifndef USB_RAM_SIZE
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#ifndef USB_RAM_SIZE
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-#define USB_RAM_SIZE 4096
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+#define USB_RAM_SIZE 4096 /* define with minimum value*/
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#endif
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#endif
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-#define USB_INSTANCE USB_OTG_HS
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#else
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#else
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#ifndef USBD_IRQHandler
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#ifndef USBD_IRQHandler
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#define USBD_IRQHandler OTG_FS_IRQHandler
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#define USBD_IRQHandler OTG_FS_IRQHandler
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#endif
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#endif
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-#ifndef USB_RAM_SIZE
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-#define USB_RAM_SIZE 1280
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+#ifndef USB_NUM_BIDIR_ENDPOINTS
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+#define USB_NUM_BIDIR_ENDPOINTS 4 /* define with minimum value*/
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#endif
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#endif
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+#ifndef USB_RAM_SIZE
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+#define USB_RAM_SIZE 1280 /* define with minimum value*/
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#endif
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#endif
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-#ifndef USB_NUM_BIDIR_ENDPOINTS
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-#define USB_NUM_BIDIR_ENDPOINTS 6
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#endif
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#endif
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#if defined(CONFIG_USB_HS) || defined(CONFIG_USB_HS_IN_FULL)
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#if defined(CONFIG_USB_HS) || defined(CONFIG_USB_HS_IN_FULL)
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@@ -60,25 +63,16 @@
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#ifndef CONFIG_USB_TX5_FIFO_SIZE
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#ifndef CONFIG_USB_TX5_FIFO_SIZE
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#define CONFIG_USB_TX5_FIFO_SIZE (256U)
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#define CONFIG_USB_TX5_FIFO_SIZE (256U)
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#endif
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#endif
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-#ifndef CONFIG_USB_TX6_FIFO_SIZE
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-#define CONFIG_USB_TX6_FIFO_SIZE (256U)
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-#endif
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-#ifndef CONFIG_USB_TX7_FIFO_SIZE
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-#define CONFIG_USB_TX7_FIFO_SIZE (256U)
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-#endif
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-#ifndef CONFIG_USB_TX8_FIFO_SIZE
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-#define CONFIG_USB_TX8_FIFO_SIZE (192U)
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-#endif
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#else
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#else
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/*FIFO sizes in bytes (total available memory for FIFOs is 1.25kB)*/
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/*FIFO sizes in bytes (total available memory for FIFOs is 1.25kB)*/
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#ifndef CONFIG_USB_RX_FIFO_SIZE
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#ifndef CONFIG_USB_RX_FIFO_SIZE
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#define CONFIG_USB_RX_FIFO_SIZE (640U)
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#define CONFIG_USB_RX_FIFO_SIZE (640U)
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#endif
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#endif
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#ifndef CONFIG_USB_TX0_FIFO_SIZE
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#ifndef CONFIG_USB_TX0_FIFO_SIZE
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-#define CONFIG_USB_TX0_FIFO_SIZE (160U)
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+#define CONFIG_USB_TX0_FIFO_SIZE (64U)
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#endif
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#endif
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#ifndef CONFIG_USB_TX1_FIFO_SIZE
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#ifndef CONFIG_USB_TX1_FIFO_SIZE
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-#define CONFIG_USB_TX1_FIFO_SIZE (160U)
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+#define CONFIG_USB_TX1_FIFO_SIZE (256U)
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#endif
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#endif
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#ifndef CONFIG_USB_TX2_FIFO_SIZE
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#ifndef CONFIG_USB_TX2_FIFO_SIZE
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#define CONFIG_USB_TX2_FIFO_SIZE (160U)
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#define CONFIG_USB_TX2_FIFO_SIZE (160U)
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@@ -86,9 +80,6 @@
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#ifndef CONFIG_USB_TX3_FIFO_SIZE
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#ifndef CONFIG_USB_TX3_FIFO_SIZE
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#define CONFIG_USB_TX3_FIFO_SIZE (160U)
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#define CONFIG_USB_TX3_FIFO_SIZE (160U)
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#endif
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#endif
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-#ifndef CONFIG_USB_TX4_FIFO_SIZE
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-#define CONFIG_USB_TX4_FIFO_SIZE (160U)
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-#endif
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#endif
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#endif
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#ifndef CONFIG_USB_TURNAROUND_TIME
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#ifndef CONFIG_USB_TURNAROUND_TIME
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@@ -161,16 +152,9 @@ int usb_dc_init(void)
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#else
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#else
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/* Select FS Embedded PHY */
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/* Select FS Embedded PHY */
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USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
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USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
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- // if (cfg.battery_charging_enable == 0U)
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- // {
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/* Activate the USB Transceiver */
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/* Activate the USB Transceiver */
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USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
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USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
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-// }
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-// else
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-// {
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-// /* Deactivate the USB Transceiver */
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-// USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
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-// }
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+
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#endif
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#endif
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/* Reset after a PHY select and set Host mode */
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/* Reset after a PHY select and set Host mode */
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@@ -201,23 +185,18 @@ int usb_dc_init(void)
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USBx->DIEPTXF[i] = 0U;
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USBx->DIEPTXF[i] = 0U;
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}
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}
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- /* VBUS Sensing setup */
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- // if (cfg.vbus_sensing_enable == 0U)
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- // {
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+#if 1 /* To fix vbus sensing disable*/
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/* Deactivate VBUS Sensing B */
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/* Deactivate VBUS Sensing B */
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USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
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USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN;
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/* B-peripheral session valid override enable */
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/* B-peripheral session valid override enable */
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USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
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USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
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USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
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USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
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- // }
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- // else
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- // {
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- // /* Enable HW VBUS sensing */
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- // USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
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- // }
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- //
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-
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+#else
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+ USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
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+ USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN;
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+ USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN;
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+#endif
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/* Restart the Phy Clock */
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/* Restart the Phy Clock */
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USBx_PCGCCTL = 0U;
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USBx_PCGCCTL = 0U;
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@@ -226,6 +205,8 @@ int usb_dc_init(void)
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#if defined(CONFIG_USB_HS)
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#if defined(CONFIG_USB_HS)
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/* Set Core speed to High speed mode */
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/* Set Core speed to High speed mode */
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USBx_DEVICE->DCFG |= USB_OTG_SPEED_HIGH;
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USBx_DEVICE->DCFG |= USB_OTG_SPEED_HIGH;
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+#elif defined(CONFIG_USB_HS_IN_FULL)
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+ USBx_DEVICE->DCFG |= USB_OTG_SPEED_HIGH_IN_FULL;
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#else
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#else
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USBx_DEVICE->DCFG |= USB_OTG_SPEED_FULL;
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USBx_DEVICE->DCFG |= USB_OTG_SPEED_FULL;
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#endif
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#endif
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@@ -277,15 +258,27 @@ int usb_dc_init(void)
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USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM |
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USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM |
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USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_RXFLVLM |
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USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT | USB_OTG_GINTMSK_RXFLVLM |
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USB_OTG_GINTMSK_WUIM;
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USB_OTG_GINTMSK_WUIM;
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+#if 0
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+ USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
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+#endif
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+ USBx_DEVICE->DOEPMSK = USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM;
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- USBx->GRXFSIZ = (CONFIG_USB_RX_FIFO_SIZE / 4);
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+ USBx_DEVICE->DIEPMSK = USB_OTG_DIEPMSK_XFRCM;
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+ USBx->GRXFSIZ = (CONFIG_USB_RX_FIFO_SIZE / 4);
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+#if defined(CONFIG_USB_HS) || defined(CONFIG_USB_HS_IN_FULL)
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usb_set_txfifo(USBx, 0, CONFIG_USB_TX0_FIFO_SIZE / 4);
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usb_set_txfifo(USBx, 0, CONFIG_USB_TX0_FIFO_SIZE / 4);
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usb_set_txfifo(USBx, 1, CONFIG_USB_TX1_FIFO_SIZE / 4);
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usb_set_txfifo(USBx, 1, CONFIG_USB_TX1_FIFO_SIZE / 4);
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usb_set_txfifo(USBx, 2, CONFIG_USB_TX2_FIFO_SIZE / 4);
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usb_set_txfifo(USBx, 2, CONFIG_USB_TX2_FIFO_SIZE / 4);
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usb_set_txfifo(USBx, 3, CONFIG_USB_TX3_FIFO_SIZE / 4);
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usb_set_txfifo(USBx, 3, CONFIG_USB_TX3_FIFO_SIZE / 4);
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usb_set_txfifo(USBx, 4, CONFIG_USB_TX4_FIFO_SIZE / 4);
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usb_set_txfifo(USBx, 4, CONFIG_USB_TX4_FIFO_SIZE / 4);
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-
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+ usb_set_txfifo(USBx, 5, CONFIG_USB_TX5_FIFO_SIZE / 4);
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+#else
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+ usb_set_txfifo(USBx, 0, CONFIG_USB_TX0_FIFO_SIZE / 4);
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+ usb_set_txfifo(USBx, 1, CONFIG_USB_TX1_FIFO_SIZE / 4);
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+ usb_set_txfifo(USBx, 2, CONFIG_USB_TX2_FIFO_SIZE / 4);
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+ usb_set_txfifo(USBx, 3, CONFIG_USB_TX3_FIFO_SIZE / 4);
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+#endif
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USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
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USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
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USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
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USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS;
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@@ -298,6 +291,22 @@ void usb_dc_deinit(void)
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uint32_t USBx_BASE = (uint32_t)USBx;
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uint32_t USBx_BASE = (uint32_t)USBx;
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usb_dc_low_level_deinit();
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usb_dc_low_level_deinit();
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+ /* Clear Pending interrupt */
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+ for (uint8_t i = 0U; i < 15U; i++) {
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+ USBx_INEP(i)->DIEPINT = 0xFB7FU;
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+ USBx_OUTEP(i)->DOEPINT = 0xFB7FU;
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+ }
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+
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+ /* Clear interrupt masks */
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+ USBx_DEVICE->DIEPMSK = 0U;
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+ USBx_DEVICE->DOEPMSK = 0U;
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+ USBx_DEVICE->DAINTMSK = 0U;
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+
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+ /* Flush the FIFO */
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+ usb_flush_txfifo(USBx, 0x10U);
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+ usb_flush_rxfifo(USBx);
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+
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+ USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS;
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}
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}
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int usbd_set_address(const uint8_t addr)
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int usbd_set_address(const uint8_t addr)
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@@ -346,13 +355,6 @@ int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
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}
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}
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int usbd_ep_close(const uint8_t ep)
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int usbd_ep_close(const uint8_t ep)
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{
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{
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- USB_OTG_GlobalTypeDef *USBx = usb_dc_cfg.Instance;
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- uint32_t USBx_BASE = (uint32_t)USBx;
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- uint8_t ep_idx = USB_EP_GET_IDX(ep);
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-
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- if (USB_EP_DIR_IS_OUT(ep)) {
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- } else {
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- }
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return 0;
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return 0;
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}
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}
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int usbd_ep_set_stall(const uint8_t ep)
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int usbd_ep_set_stall(const uint8_t ep)
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@@ -617,12 +619,6 @@ void USBD_IRQHandler(void)
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}
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}
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USBx_DEVICE->DAINTMSK |= 0x10001U;
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USBx_DEVICE->DAINTMSK |= 0x10001U;
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- USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM |
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- USB_OTG_DOEPMSK_XFRCM;
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-
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- USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM |
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- USB_OTG_DIEPMSK_XFRCM;
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-
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USBx_OUTEP(0U)->DOEPTSIZ = 0U;
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USBx_OUTEP(0U)->DOEPTSIZ = 0U;
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USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
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USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
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USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
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USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U);
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