delete repeatable file

port/fsdev/usb_dc_fsdev.c

@@ -352,26 +352,27 @@ void USBD_IRQHandler(void)
                         USBx->DADDR = ((uint16_t)usb_dc_cfg.USB_Address | USB_DADDR_EF);
                         usb_dc_cfg.USB_Address = 0U;
                     }
-                }
-                /* DIR = 1 */
-
-                /* DIR = 1 & CTR_RX => SETUP or OUT int */
-                /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
-
-                wEPVal = PCD_GET_ENDPOINT(USBx, 0);
-
-                if ((wEPVal & USB_EP_SETUP) != 0U) {
-                    /* SETUP bit kept frozen while CTR_RX = 1 */
-                    PCD_CLEAR_RX_EP_CTR(USBx, 0);
-
-                    /* Process SETUP Packet*/
-                    usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
-                    PCD_SET_EP_RX_STATUS(USBx, 0, USB_EP_RX_VALID);
-                } else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
-                    PCD_CLEAR_RX_EP_CTR(USBx, 0);
-                    /* Process Control Data OUT Packet */
-                    usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
-                    PCD_SET_EP_RX_STATUS(USBx, 0, USB_EP_RX_VALID);
+                } else {
+                    /* DIR = 1 */
+
+                    /* DIR = 1 & CTR_RX => SETUP or OUT int */
+                    /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
+
+                    wEPVal = PCD_GET_ENDPOINT(USBx, 0);
+
+                    if ((wEPVal & USB_EP_SETUP) != 0U) {
+                        /* SETUP bit kept frozen while CTR_RX = 1 */
+                        PCD_CLEAR_RX_EP_CTR(USBx, 0);
+
+                        /* Process SETUP Packet*/
+                        usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
+                        PCD_SET_EP_RX_STATUS(USBx, 0, USB_EP_RX_VALID);
+                    } else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
+                        PCD_CLEAR_RX_EP_CTR(USBx, 0);
+                        /* Process Control Data OUT Packet */
+                        usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
+                        PCD_SET_EP_RX_STATUS(USBx, 0, USB_EP_RX_VALID);
+                    }
                 }
             } else {
                 /* Decode and service non control endpoints interrupt */

port/fsdev/usb_fsdev_reg.h

@@ -1105,1078 +1105,8 @@ typedef struct
 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
 
-#define USB_COUNT7_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) *//******************************************************************************/
-/*                                                                            */
-/*                                   USB Device FS                            */
-/*                                                                            */
-/******************************************************************************/
-
-/*!< Endpoint-specific registers */
-#define  USB_EP0R                            USB_BASE                      /*!< Endpoint 0 register address */
-#define  USB_EP1R                            (USB_BASE + 0x00000004)       /*!< Endpoint 1 register address */
-#define  USB_EP2R                            (USB_BASE + 0x00000008)       /*!< Endpoint 2 register address */
-#define  USB_EP3R                            (USB_BASE + 0x0000000C)       /*!< Endpoint 3 register address */
-#define  USB_EP4R                            (USB_BASE + 0x00000010)       /*!< Endpoint 4 register address */
-#define  USB_EP5R                            (USB_BASE + 0x00000014)       /*!< Endpoint 5 register address */
-#define  USB_EP6R                            (USB_BASE + 0x00000018)       /*!< Endpoint 6 register address */
-#define  USB_EP7R                            (USB_BASE + 0x0000001C)       /*!< Endpoint 7 register address */
-
-/* bit positions */
-#define USB_EP_CTR_RX_Pos                       (15U)
-#define USB_EP_CTR_RX_Msk                       (0x1UL << USB_EP_CTR_RX_Pos)    /*!< 0x00008000 */
-#define USB_EP_CTR_RX                           USB_EP_CTR_RX_Msk              /*!< EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX_Pos                      (14U)
-#define USB_EP_DTOG_RX_Msk                      (0x1UL << USB_EP_DTOG_RX_Pos)   /*!< 0x00004000 */
-#define USB_EP_DTOG_RX                          USB_EP_DTOG_RX_Msk             /*!< EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT_Pos                       (12U)
-#define USB_EPRX_STAT_Msk                       (0x3UL << USB_EPRX_STAT_Pos)    /*!< 0x00003000 */
-#define USB_EPRX_STAT                           USB_EPRX_STAT_Msk              /*!< EndPoint RX STATus bit field */
-#define USB_EP_SETUP_Pos                        (11U)
-#define USB_EP_SETUP_Msk                        (0x1UL << USB_EP_SETUP_Pos)     /*!< 0x00000800 */
-#define USB_EP_SETUP                            USB_EP_SETUP_Msk               /*!< EndPoint SETUP */
-#define USB_EP_T_FIELD_Pos                      (9U)
-#define USB_EP_T_FIELD_Msk                      (0x3UL << USB_EP_T_FIELD_Pos)   /*!< 0x00000600 */
-#define USB_EP_T_FIELD                          USB_EP_T_FIELD_Msk             /*!< EndPoint TYPE */
-#define USB_EP_KIND_Pos                         (8U)
-#define USB_EP_KIND_Msk                         (0x1UL << USB_EP_KIND_Pos)      /*!< 0x00000100 */
-#define USB_EP_KIND                             USB_EP_KIND_Msk                /*!< EndPoint KIND */
-#define USB_EP_CTR_TX_Pos                       (7U)
-#define USB_EP_CTR_TX_Msk                       (0x1UL << USB_EP_CTR_TX_Pos)    /*!< 0x00000080 */
-#define USB_EP_CTR_TX                           USB_EP_CTR_TX_Msk              /*!< EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX_Pos                      (6U)
-#define USB_EP_DTOG_TX_Msk                      (0x1UL << USB_EP_DTOG_TX_Pos)   /*!< 0x00000040 */
-#define USB_EP_DTOG_TX                          USB_EP_DTOG_TX_Msk             /*!< EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT_Pos                       (4U)
-#define USB_EPTX_STAT_Msk                       (0x3UL << USB_EPTX_STAT_Pos)    /*!< 0x00000030 */
-#define USB_EPTX_STAT                           USB_EPTX_STAT_Msk              /*!< EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD_Pos                    (0U)
-#define USB_EPADDR_FIELD_Msk                    (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
-#define USB_EPADDR_FIELD                        USB_EPADDR_FIELD_Msk           /*!< EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK                      (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                           /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK_Pos                    (9U)
-#define USB_EP_TYPE_MASK_Msk                    (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
-#define USB_EP_TYPE_MASK                        USB_EP_TYPE_MASK_Msk           /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                             0x00000000U                    /*!< EndPoint BULK */
-#define USB_EP_CONTROL                          0x00000200U                    /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                      0x00000400U                    /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                        0x00000600U                    /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK                          (~USB_EP_T_FIELD & USB_EPREG_MASK)
-
-#define  USB_EPKIND_MASK                        (~USB_EP_KIND & USB_EPREG_MASK)  /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                           0x00000000U                    /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                         0x00000010U                    /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                           0x00000020U                    /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                         0x00000030U                    /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                          0x00000010U                    /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                          0x00000020U                    /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                           0x00000000U                    /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                         0x00001000U                    /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                           0x00002000U                    /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                         0x00003000U                    /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                          0x00001000U                    /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                          0x00002000U                    /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define USB_EP0R_EA_Pos                         (0U)
-#define USB_EP0R_EA_Msk                         (0xFUL << USB_EP0R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP0R_EA                             USB_EP0R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP0R_STAT_TX_Pos                    (4U)
-#define USB_EP0R_STAT_TX_Msk                    (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP0R_STAT_TX                        USB_EP0R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP0R_STAT_TX_0                      (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP0R_STAT_TX_1                      (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP0R_DTOG_TX_Pos                    (6U)
-#define USB_EP0R_DTOG_TX_Msk                    (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP0R_DTOG_TX                        USB_EP0R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP0R_CTR_TX_Pos                     (7U)
-#define USB_EP0R_CTR_TX_Msk                     (0x1UL << USB_EP0R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP0R_CTR_TX                         USB_EP0R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP0R_EP_KIND_Pos                    (8U)
-#define USB_EP0R_EP_KIND_Msk                    (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP0R_EP_KIND                        USB_EP0R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP0R_EP_TYPE_Pos                    (9U)
-#define USB_EP0R_EP_TYPE_Msk                    (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP0R_EP_TYPE                        USB_EP0R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP0R_EP_TYPE_0                      (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP0R_EP_TYPE_1                      (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP0R_SETUP_Pos                      (11U)
-#define USB_EP0R_SETUP_Msk                      (0x1UL << USB_EP0R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP0R_SETUP                          USB_EP0R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP0R_STAT_RX_Pos                    (12U)
-#define USB_EP0R_STAT_RX_Msk                    (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP0R_STAT_RX                        USB_EP0R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP0R_STAT_RX_0                      (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP0R_STAT_RX_1                      (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP0R_DTOG_RX_Pos                    (14U)
-#define USB_EP0R_DTOG_RX_Msk                    (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP0R_DTOG_RX                        USB_EP0R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP0R_CTR_RX_Pos                     (15U)
-#define USB_EP0R_CTR_RX_Msk                     (0x1UL << USB_EP0R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP0R_CTR_RX                         USB_EP0R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define USB_EP1R_EA_Pos                         (0U)
-#define USB_EP1R_EA_Msk                         (0xFUL << USB_EP1R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP1R_EA                             USB_EP1R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP1R_STAT_TX_Pos                    (4U)
-#define USB_EP1R_STAT_TX_Msk                    (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP1R_STAT_TX                        USB_EP1R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP1R_STAT_TX_0                      (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP1R_STAT_TX_1                      (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP1R_DTOG_TX_Pos                    (6U)
-#define USB_EP1R_DTOG_TX_Msk                    (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP1R_DTOG_TX                        USB_EP1R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP1R_CTR_TX_Pos                     (7U)
-#define USB_EP1R_CTR_TX_Msk                     (0x1UL << USB_EP1R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP1R_CTR_TX                         USB_EP1R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP1R_EP_KIND_Pos                    (8U)
-#define USB_EP1R_EP_KIND_Msk                    (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP1R_EP_KIND                        USB_EP1R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP1R_EP_TYPE_Pos                    (9U)
-#define USB_EP1R_EP_TYPE_Msk                    (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP1R_EP_TYPE                        USB_EP1R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP1R_EP_TYPE_0                      (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP1R_EP_TYPE_1                      (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP1R_SETUP_Pos                      (11U)
-#define USB_EP1R_SETUP_Msk                      (0x1UL << USB_EP1R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP1R_SETUP                          USB_EP1R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP1R_STAT_RX_Pos                    (12U)
-#define USB_EP1R_STAT_RX_Msk                    (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP1R_STAT_RX                        USB_EP1R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP1R_STAT_RX_0                      (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP1R_STAT_RX_1                      (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP1R_DTOG_RX_Pos                    (14U)
-#define USB_EP1R_DTOG_RX_Msk                    (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP1R_DTOG_RX                        USB_EP1R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP1R_CTR_RX_Pos                     (15U)
-#define USB_EP1R_CTR_RX_Msk                     (0x1UL << USB_EP1R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP1R_CTR_RX                         USB_EP1R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define USB_EP2R_EA_Pos                         (0U)
-#define USB_EP2R_EA_Msk                         (0xFUL << USB_EP2R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP2R_EA                             USB_EP2R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP2R_STAT_TX_Pos                    (4U)
-#define USB_EP2R_STAT_TX_Msk                    (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP2R_STAT_TX                        USB_EP2R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP2R_STAT_TX_0                      (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP2R_STAT_TX_1                      (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP2R_DTOG_TX_Pos                    (6U)
-#define USB_EP2R_DTOG_TX_Msk                    (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP2R_DTOG_TX                        USB_EP2R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP2R_CTR_TX_Pos                     (7U)
-#define USB_EP2R_CTR_TX_Msk                     (0x1UL << USB_EP2R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP2R_CTR_TX                         USB_EP2R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP2R_EP_KIND_Pos                    (8U)
-#define USB_EP2R_EP_KIND_Msk                    (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP2R_EP_KIND                        USB_EP2R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP2R_EP_TYPE_Pos                    (9U)
-#define USB_EP2R_EP_TYPE_Msk                    (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP2R_EP_TYPE                        USB_EP2R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP2R_EP_TYPE_0                      (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP2R_EP_TYPE_1                      (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP2R_SETUP_Pos                      (11U)
-#define USB_EP2R_SETUP_Msk                      (0x1UL << USB_EP2R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP2R_SETUP                          USB_EP2R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP2R_STAT_RX_Pos                    (12U)
-#define USB_EP2R_STAT_RX_Msk                    (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP2R_STAT_RX                        USB_EP2R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP2R_STAT_RX_0                      (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP2R_STAT_RX_1                      (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP2R_DTOG_RX_Pos                    (14U)
-#define USB_EP2R_DTOG_RX_Msk                    (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP2R_DTOG_RX                        USB_EP2R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP2R_CTR_RX_Pos                     (15U)
-#define USB_EP2R_CTR_RX_Msk                     (0x1UL << USB_EP2R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP2R_CTR_RX                         USB_EP2R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define USB_EP3R_EA_Pos                         (0U)
-#define USB_EP3R_EA_Msk                         (0xFUL << USB_EP3R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP3R_EA                             USB_EP3R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP3R_STAT_TX_Pos                    (4U)
-#define USB_EP3R_STAT_TX_Msk                    (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP3R_STAT_TX                        USB_EP3R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP3R_STAT_TX_0                      (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP3R_STAT_TX_1                      (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP3R_DTOG_TX_Pos                    (6U)
-#define USB_EP3R_DTOG_TX_Msk                    (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP3R_DTOG_TX                        USB_EP3R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP3R_CTR_TX_Pos                     (7U)
-#define USB_EP3R_CTR_TX_Msk                     (0x1UL << USB_EP3R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP3R_CTR_TX                         USB_EP3R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP3R_EP_KIND_Pos                    (8U)
-#define USB_EP3R_EP_KIND_Msk                    (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP3R_EP_KIND                        USB_EP3R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP3R_EP_TYPE_Pos                    (9U)
-#define USB_EP3R_EP_TYPE_Msk                    (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP3R_EP_TYPE                        USB_EP3R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP3R_EP_TYPE_0                      (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP3R_EP_TYPE_1                      (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP3R_SETUP_Pos                      (11U)
-#define USB_EP3R_SETUP_Msk                      (0x1UL << USB_EP3R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP3R_SETUP                          USB_EP3R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP3R_STAT_RX_Pos                    (12U)
-#define USB_EP3R_STAT_RX_Msk                    (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP3R_STAT_RX                        USB_EP3R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP3R_STAT_RX_0                      (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP3R_STAT_RX_1                      (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP3R_DTOG_RX_Pos                    (14U)
-#define USB_EP3R_DTOG_RX_Msk                    (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP3R_DTOG_RX                        USB_EP3R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP3R_CTR_RX_Pos                     (15U)
-#define USB_EP3R_CTR_RX_Msk                     (0x1UL << USB_EP3R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP3R_CTR_RX                         USB_EP3R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define USB_EP4R_EA_Pos                         (0U)
-#define USB_EP4R_EA_Msk                         (0xFUL << USB_EP4R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP4R_EA                             USB_EP4R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP4R_STAT_TX_Pos                    (4U)
-#define USB_EP4R_STAT_TX_Msk                    (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP4R_STAT_TX                        USB_EP4R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP4R_STAT_TX_0                      (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP4R_STAT_TX_1                      (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP4R_DTOG_TX_Pos                    (6U)
-#define USB_EP4R_DTOG_TX_Msk                    (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP4R_DTOG_TX                        USB_EP4R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP4R_CTR_TX_Pos                     (7U)
-#define USB_EP4R_CTR_TX_Msk                     (0x1UL << USB_EP4R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP4R_CTR_TX                         USB_EP4R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP4R_EP_KIND_Pos                    (8U)
-#define USB_EP4R_EP_KIND_Msk                    (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP4R_EP_KIND                        USB_EP4R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP4R_EP_TYPE_Pos                    (9U)
-#define USB_EP4R_EP_TYPE_Msk                    (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP4R_EP_TYPE                        USB_EP4R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP4R_EP_TYPE_0                      (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP4R_EP_TYPE_1                      (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP4R_SETUP_Pos                      (11U)
-#define USB_EP4R_SETUP_Msk                      (0x1UL << USB_EP4R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP4R_SETUP                          USB_EP4R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP4R_STAT_RX_Pos                    (12U)
-#define USB_EP4R_STAT_RX_Msk                    (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP4R_STAT_RX                        USB_EP4R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP4R_STAT_RX_0                      (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP4R_STAT_RX_1                      (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP4R_DTOG_RX_Pos                    (14U)
-#define USB_EP4R_DTOG_RX_Msk                    (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP4R_DTOG_RX                        USB_EP4R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP4R_CTR_RX_Pos                     (15U)
-#define USB_EP4R_CTR_RX_Msk                     (0x1UL << USB_EP4R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP4R_CTR_RX                         USB_EP4R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define USB_EP5R_EA_Pos                         (0U)
-#define USB_EP5R_EA_Msk                         (0xFUL << USB_EP5R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP5R_EA                             USB_EP5R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP5R_STAT_TX_Pos                    (4U)
-#define USB_EP5R_STAT_TX_Msk                    (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP5R_STAT_TX                        USB_EP5R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP5R_STAT_TX_0                      (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP5R_STAT_TX_1                      (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP5R_DTOG_TX_Pos                    (6U)
-#define USB_EP5R_DTOG_TX_Msk                    (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP5R_DTOG_TX                        USB_EP5R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP5R_CTR_TX_Pos                     (7U)
-#define USB_EP5R_CTR_TX_Msk                     (0x1UL << USB_EP5R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP5R_CTR_TX                         USB_EP5R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP5R_EP_KIND_Pos                    (8U)
-#define USB_EP5R_EP_KIND_Msk                    (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP5R_EP_KIND                        USB_EP5R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP5R_EP_TYPE_Pos                    (9U)
-#define USB_EP5R_EP_TYPE_Msk                    (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP5R_EP_TYPE                        USB_EP5R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP5R_EP_TYPE_0                      (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP5R_EP_TYPE_1                      (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP5R_SETUP_Pos                      (11U)
-#define USB_EP5R_SETUP_Msk                      (0x1UL << USB_EP5R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP5R_SETUP                          USB_EP5R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP5R_STAT_RX_Pos                    (12U)
-#define USB_EP5R_STAT_RX_Msk                    (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP5R_STAT_RX                        USB_EP5R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP5R_STAT_RX_0                      (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP5R_STAT_RX_1                      (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP5R_DTOG_RX_Pos                    (14U)
-#define USB_EP5R_DTOG_RX_Msk                    (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP5R_DTOG_RX                        USB_EP5R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP5R_CTR_RX_Pos                     (15U)
-#define USB_EP5R_CTR_RX_Msk                     (0x1UL << USB_EP5R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP5R_CTR_RX                         USB_EP5R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define USB_EP6R_EA_Pos                         (0U)
-#define USB_EP6R_EA_Msk                         (0xFUL << USB_EP6R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP6R_EA                             USB_EP6R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP6R_STAT_TX_Pos                    (4U)
-#define USB_EP6R_STAT_TX_Msk                    (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP6R_STAT_TX                        USB_EP6R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP6R_STAT_TX_0                      (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP6R_STAT_TX_1                      (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP6R_DTOG_TX_Pos                    (6U)
-#define USB_EP6R_DTOG_TX_Msk                    (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP6R_DTOG_TX                        USB_EP6R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP6R_CTR_TX_Pos                     (7U)
-#define USB_EP6R_CTR_TX_Msk                     (0x1UL << USB_EP6R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP6R_CTR_TX                         USB_EP6R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP6R_EP_KIND_Pos                    (8U)
-#define USB_EP6R_EP_KIND_Msk                    (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP6R_EP_KIND                        USB_EP6R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP6R_EP_TYPE_Pos                    (9U)
-#define USB_EP6R_EP_TYPE_Msk                    (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP6R_EP_TYPE                        USB_EP6R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP6R_EP_TYPE_0                      (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP6R_EP_TYPE_1                      (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP6R_SETUP_Pos                      (11U)
-#define USB_EP6R_SETUP_Msk                      (0x1UL << USB_EP6R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP6R_SETUP                          USB_EP6R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP6R_STAT_RX_Pos                    (12U)
-#define USB_EP6R_STAT_RX_Msk                    (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP6R_STAT_RX                        USB_EP6R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP6R_STAT_RX_0                      (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP6R_STAT_RX_1                      (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP6R_DTOG_RX_Pos                    (14U)
-#define USB_EP6R_DTOG_RX_Msk                    (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP6R_DTOG_RX                        USB_EP6R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP6R_CTR_RX_Pos                     (15U)
-#define USB_EP6R_CTR_RX_Msk                     (0x1UL << USB_EP6R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP6R_CTR_RX                         USB_EP6R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define USB_EP7R_EA_Pos                         (0U)
-#define USB_EP7R_EA_Msk                         (0xFUL << USB_EP7R_EA_Pos)      /*!< 0x0000000F */
-#define USB_EP7R_EA                             USB_EP7R_EA_Msk                /*!< Endpoint Address */
-
-#define USB_EP7R_STAT_TX_Pos                    (4U)
-#define USB_EP7R_STAT_TX_Msk                    (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
-#define USB_EP7R_STAT_TX                        USB_EP7R_STAT_TX_Msk           /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define USB_EP7R_STAT_TX_0                      (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
-#define USB_EP7R_STAT_TX_1                      (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
-
-#define USB_EP7R_DTOG_TX_Pos                    (6U)
-#define USB_EP7R_DTOG_TX_Msk                    (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
-#define USB_EP7R_DTOG_TX                        USB_EP7R_DTOG_TX_Msk           /*!< Data Toggle, for transmission transfers */
-#define USB_EP7R_CTR_TX_Pos                     (7U)
-#define USB_EP7R_CTR_TX_Msk                     (0x1UL << USB_EP7R_CTR_TX_Pos)  /*!< 0x00000080 */
-#define USB_EP7R_CTR_TX                         USB_EP7R_CTR_TX_Msk            /*!< Correct Transfer for transmission */
-#define USB_EP7R_EP_KIND_Pos                    (8U)
-#define USB_EP7R_EP_KIND_Msk                    (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
-#define USB_EP7R_EP_KIND                        USB_EP7R_EP_KIND_Msk           /*!< Endpoint Kind */
-
-#define USB_EP7R_EP_TYPE_Pos                    (9U)
-#define USB_EP7R_EP_TYPE_Msk                    (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
-#define USB_EP7R_EP_TYPE                        USB_EP7R_EP_TYPE_Msk           /*!< EP_TYPE[1:0] bits (Endpoint type) */
-#define USB_EP7R_EP_TYPE_0                      (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
-#define USB_EP7R_EP_TYPE_1                      (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
-
-#define USB_EP7R_SETUP_Pos                      (11U)
-#define USB_EP7R_SETUP_Msk                      (0x1UL << USB_EP7R_SETUP_Pos)   /*!< 0x00000800 */
-#define USB_EP7R_SETUP                          USB_EP7R_SETUP_Msk             /*!< Setup transaction completed */
-
-#define USB_EP7R_STAT_RX_Pos                    (12U)
-#define USB_EP7R_STAT_RX_Msk                    (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
-#define USB_EP7R_STAT_RX                        USB_EP7R_STAT_RX_Msk           /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define USB_EP7R_STAT_RX_0                      (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
-#define USB_EP7R_STAT_RX_1                      (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
-
-#define USB_EP7R_DTOG_RX_Pos                    (14U)
-#define USB_EP7R_DTOG_RX_Msk                    (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
-#define USB_EP7R_DTOG_RX                        USB_EP7R_DTOG_RX_Msk           /*!< Data Toggle, for reception transfers */
-#define USB_EP7R_CTR_RX_Pos                     (15U)
-#define USB_EP7R_CTR_RX_Msk                     (0x1UL << USB_EP7R_CTR_RX_Pos)  /*!< 0x00008000 */
-#define USB_EP7R_CTR_RX                         USB_EP7R_CTR_RX_Msk            /*!< Correct Transfer for reception */
-
-/*!< Common registers */
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define USB_CNTR_FRES_Pos                       (0U)
-#define USB_CNTR_FRES_Msk                       (0x1UL << USB_CNTR_FRES_Pos)    /*!< 0x00000001 */
-#define USB_CNTR_FRES                           USB_CNTR_FRES_Msk              /*!< Force USB Reset */
-#define USB_CNTR_PDWN_Pos                       (1U)
-#define USB_CNTR_PDWN_Msk                       (0x1UL << USB_CNTR_PDWN_Pos)    /*!< 0x00000002 */
-#define USB_CNTR_PDWN                           USB_CNTR_PDWN_Msk              /*!< Power down */
-#define USB_CNTR_LP_MODE_Pos                    (2U)
-#define USB_CNTR_LP_MODE_Msk                    (0x1UL << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
-#define USB_CNTR_LP_MODE                        USB_CNTR_LP_MODE_Msk           /*!< Low-power mode */
-#define USB_CNTR_FSUSP_Pos                      (3U)
-#define USB_CNTR_FSUSP_Msk                      (0x1UL << USB_CNTR_FSUSP_Pos)   /*!< 0x00000008 */
-#define USB_CNTR_FSUSP                          USB_CNTR_FSUSP_Msk             /*!< Force suspend */
-#define USB_CNTR_RESUME_Pos                     (4U)
-#define USB_CNTR_RESUME_Msk                     (0x1UL << USB_CNTR_RESUME_Pos)  /*!< 0x00000010 */
-#define USB_CNTR_RESUME                         USB_CNTR_RESUME_Msk            /*!< Resume request */
-#define USB_CNTR_ESOFM_Pos                      (8U)
-#define USB_CNTR_ESOFM_Msk                      (0x1UL << USB_CNTR_ESOFM_Pos)   /*!< 0x00000100 */
-#define USB_CNTR_ESOFM                          USB_CNTR_ESOFM_Msk             /*!< Expected Start Of Frame Interrupt Mask */
-#define USB_CNTR_SOFM_Pos                       (9U)
-#define USB_CNTR_SOFM_Msk                       (0x1UL << USB_CNTR_SOFM_Pos)    /*!< 0x00000200 */
-#define USB_CNTR_SOFM                           USB_CNTR_SOFM_Msk              /*!< Start Of Frame Interrupt Mask */
-#define USB_CNTR_RESETM_Pos                     (10U)
-#define USB_CNTR_RESETM_Msk                     (0x1UL << USB_CNTR_RESETM_Pos)  /*!< 0x00000400 */
-#define USB_CNTR_RESETM                         USB_CNTR_RESETM_Msk            /*!< RESET Interrupt Mask */
-#define USB_CNTR_SUSPM_Pos                      (11U)
-#define USB_CNTR_SUSPM_Msk                      (0x1UL << USB_CNTR_SUSPM_Pos)   /*!< 0x00000800 */
-#define USB_CNTR_SUSPM                          USB_CNTR_SUSPM_Msk             /*!< Suspend mode Interrupt Mask */
-#define USB_CNTR_WKUPM_Pos                      (12U)
-#define USB_CNTR_WKUPM_Msk                      (0x1UL << USB_CNTR_WKUPM_Pos)   /*!< 0x00001000 */
-#define USB_CNTR_WKUPM                          USB_CNTR_WKUPM_Msk             /*!< Wakeup Interrupt Mask */
-#define USB_CNTR_ERRM_Pos                       (13U)
-#define USB_CNTR_ERRM_Msk                       (0x1UL << USB_CNTR_ERRM_Pos)    /*!< 0x00002000 */
-#define USB_CNTR_ERRM                           USB_CNTR_ERRM_Msk              /*!< Error Interrupt Mask */
-#define USB_CNTR_PMAOVRM_Pos                    (14U)
-#define USB_CNTR_PMAOVRM_Msk                    (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
-#define USB_CNTR_PMAOVRM                        USB_CNTR_PMAOVRM_Msk           /*!< Packet Memory Area Over / Underrun Interrupt Mask */
-#define USB_CNTR_CTRM_Pos                       (15U)
-#define USB_CNTR_CTRM_Msk                       (0x1UL << USB_CNTR_CTRM_Pos)    /*!< 0x00008000 */
-#define USB_CNTR_CTRM                           USB_CNTR_CTRM_Msk              /*!< Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define USB_ISTR_EP_ID_Pos                      (0U)
-#define USB_ISTR_EP_ID_Msk                      (0xFUL << USB_ISTR_EP_ID_Pos)   /*!< 0x0000000F */
-#define USB_ISTR_EP_ID                          USB_ISTR_EP_ID_Msk             /*!< Endpoint Identifier */
-#define USB_ISTR_DIR_Pos                        (4U)
-#define USB_ISTR_DIR_Msk                        (0x1UL << USB_ISTR_DIR_Pos)     /*!< 0x00000010 */
-#define USB_ISTR_DIR                            USB_ISTR_DIR_Msk               /*!< Direction of transaction */
-#define USB_ISTR_ESOF_Pos                       (8U)
-#define USB_ISTR_ESOF_Msk                       (0x1UL << USB_ISTR_ESOF_Pos)    /*!< 0x00000100 */
-#define USB_ISTR_ESOF                           USB_ISTR_ESOF_Msk              /*!< Expected Start Of Frame */
-#define USB_ISTR_SOF_Pos                        (9U)
-#define USB_ISTR_SOF_Msk                        (0x1UL << USB_ISTR_SOF_Pos)     /*!< 0x00000200 */
-#define USB_ISTR_SOF                            USB_ISTR_SOF_Msk               /*!< Start Of Frame */
-#define USB_ISTR_RESET_Pos                      (10U)
-#define USB_ISTR_RESET_Msk                      (0x1UL << USB_ISTR_RESET_Pos)   /*!< 0x00000400 */
-#define USB_ISTR_RESET                          USB_ISTR_RESET_Msk             /*!< USB RESET request */
-#define USB_ISTR_SUSP_Pos                       (11U)
-#define USB_ISTR_SUSP_Msk                       (0x1UL << USB_ISTR_SUSP_Pos)    /*!< 0x00000800 */
-#define USB_ISTR_SUSP                           USB_ISTR_SUSP_Msk              /*!< Suspend mode request */
-#define USB_ISTR_WKUP_Pos                       (12U)
-#define USB_ISTR_WKUP_Msk                       (0x1UL << USB_ISTR_WKUP_Pos)    /*!< 0x00001000 */
-#define USB_ISTR_WKUP                           USB_ISTR_WKUP_Msk              /*!< Wake up */
-#define USB_ISTR_ERR_Pos                        (13U)
-#define USB_ISTR_ERR_Msk                        (0x1UL << USB_ISTR_ERR_Pos)     /*!< 0x00002000 */
-#define USB_ISTR_ERR                            USB_ISTR_ERR_Msk               /*!< Error */
-#define USB_ISTR_PMAOVR_Pos                     (14U)
-#define USB_ISTR_PMAOVR_Msk                     (0x1UL << USB_ISTR_PMAOVR_Pos)  /*!< 0x00004000 */
-#define USB_ISTR_PMAOVR                         USB_ISTR_PMAOVR_Msk            /*!< Packet Memory Area Over / Underrun */
-#define USB_ISTR_CTR_Pos                        (15U)
-#define USB_ISTR_CTR_Msk                        (0x1UL << USB_ISTR_CTR_Pos)     /*!< 0x00008000 */
-#define USB_ISTR_CTR                            USB_ISTR_CTR_Msk               /*!< Correct Transfer */
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define USB_FNR_FN_Pos                          (0U)
-#define USB_FNR_FN_Msk                          (0x7FFUL << USB_FNR_FN_Pos)     /*!< 0x000007FF */
-#define USB_FNR_FN                              USB_FNR_FN_Msk                 /*!< Frame Number */
-#define USB_FNR_LSOF_Pos                        (11U)
-#define USB_FNR_LSOF_Msk                        (0x3UL << USB_FNR_LSOF_Pos)     /*!< 0x00001800 */
-#define USB_FNR_LSOF                            USB_FNR_LSOF_Msk               /*!< Lost SOF */
-#define USB_FNR_LCK_Pos                         (13U)
-#define USB_FNR_LCK_Msk                         (0x1UL << USB_FNR_LCK_Pos)      /*!< 0x00002000 */
-#define USB_FNR_LCK                             USB_FNR_LCK_Msk                /*!< Locked */
-#define USB_FNR_RXDM_Pos                        (14U)
-#define USB_FNR_RXDM_Msk                        (0x1UL << USB_FNR_RXDM_Pos)     /*!< 0x00004000 */
-#define USB_FNR_RXDM                            USB_FNR_RXDM_Msk               /*!< Receive Data - Line Status */
-#define USB_FNR_RXDP_Pos                        (15U)
-#define USB_FNR_RXDP_Msk                        (0x1UL << USB_FNR_RXDP_Pos)     /*!< 0x00008000 */
-#define USB_FNR_RXDP                            USB_FNR_RXDP_Msk               /*!< Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define USB_DADDR_ADD_Pos                       (0U)
-#define USB_DADDR_ADD_Msk                       (0x7FUL << USB_DADDR_ADD_Pos)   /*!< 0x0000007F */
-#define USB_DADDR_ADD                           USB_DADDR_ADD_Msk              /*!< ADD[6:0] bits (Device Address) */
-#define USB_DADDR_ADD0_Pos                      (0U)
-#define USB_DADDR_ADD0_Msk                      (0x1UL << USB_DADDR_ADD0_Pos)   /*!< 0x00000001 */
-#define USB_DADDR_ADD0                          USB_DADDR_ADD0_Msk             /*!< Bit 0 */
-#define USB_DADDR_ADD1_Pos                      (1U)
-#define USB_DADDR_ADD1_Msk                      (0x1UL << USB_DADDR_ADD1_Pos)   /*!< 0x00000002 */
-#define USB_DADDR_ADD1                          USB_DADDR_ADD1_Msk             /*!< Bit 1 */
-#define USB_DADDR_ADD2_Pos                      (2U)
-#define USB_DADDR_ADD2_Msk                      (0x1UL << USB_DADDR_ADD2_Pos)   /*!< 0x00000004 */
-#define USB_DADDR_ADD2                          USB_DADDR_ADD2_Msk             /*!< Bit 2 */
-#define USB_DADDR_ADD3_Pos                      (3U)
-#define USB_DADDR_ADD3_Msk                      (0x1UL << USB_DADDR_ADD3_Pos)   /*!< 0x00000008 */
-#define USB_DADDR_ADD3                          USB_DADDR_ADD3_Msk             /*!< Bit 3 */
-#define USB_DADDR_ADD4_Pos                      (4U)
-#define USB_DADDR_ADD4_Msk                      (0x1UL << USB_DADDR_ADD4_Pos)   /*!< 0x00000010 */
-#define USB_DADDR_ADD4                          USB_DADDR_ADD4_Msk             /*!< Bit 4 */
-#define USB_DADDR_ADD5_Pos                      (5U)
-#define USB_DADDR_ADD5_Msk                      (0x1UL << USB_DADDR_ADD5_Pos)   /*!< 0x00000020 */
-#define USB_DADDR_ADD5                          USB_DADDR_ADD5_Msk             /*!< Bit 5 */
-#define USB_DADDR_ADD6_Pos                      (6U)
-#define USB_DADDR_ADD6_Msk                      (0x1UL << USB_DADDR_ADD6_Pos)   /*!< 0x00000040 */
-#define USB_DADDR_ADD6                          USB_DADDR_ADD6_Msk             /*!< Bit 6 */
-
-#define USB_DADDR_EF_Pos                        (7U)
-#define USB_DADDR_EF_Msk                        (0x1UL << USB_DADDR_EF_Pos)     /*!< 0x00000080 */
-#define USB_DADDR_EF                            USB_DADDR_EF_Msk               /*!< Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/
-#define USB_BTABLE_BTABLE_Pos                   (3U)
-#define USB_BTABLE_BTABLE_Msk                   (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
-#define USB_BTABLE_BTABLE                       USB_BTABLE_BTABLE_Msk          /*!< Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define USB_ADDR0_TX_ADDR0_TX_Pos               (1U)
-#define USB_ADDR0_TX_ADDR0_TX_Msk               (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_TX_ADDR0_TX                   USB_ADDR0_TX_ADDR0_TX_Msk      /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define USB_ADDR1_TX_ADDR1_TX_Pos               (1U)
-#define USB_ADDR1_TX_ADDR1_TX_Msk               (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_TX_ADDR1_TX                   USB_ADDR1_TX_ADDR1_TX_Msk      /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define USB_ADDR2_TX_ADDR2_TX_Pos               (1U)
-#define USB_ADDR2_TX_ADDR2_TX_Msk               (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_TX_ADDR2_TX                   USB_ADDR2_TX_ADDR2_TX_Msk      /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define USB_ADDR3_TX_ADDR3_TX_Pos               (1U)
-#define USB_ADDR3_TX_ADDR3_TX_Msk               (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_TX_ADDR3_TX                   USB_ADDR3_TX_ADDR3_TX_Msk      /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define USB_ADDR4_TX_ADDR4_TX_Pos               (1U)
-#define USB_ADDR4_TX_ADDR4_TX_Msk               (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_TX_ADDR4_TX                   USB_ADDR4_TX_ADDR4_TX_Msk      /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define USB_ADDR5_TX_ADDR5_TX_Pos               (1U)
-#define USB_ADDR5_TX_ADDR5_TX_Msk               (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_TX_ADDR5_TX                   USB_ADDR5_TX_ADDR5_TX_Msk      /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define USB_ADDR6_TX_ADDR6_TX_Pos               (1U)
-#define USB_ADDR6_TX_ADDR6_TX_Msk               (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_TX_ADDR6_TX                   USB_ADDR6_TX_ADDR6_TX_Msk      /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define USB_ADDR7_TX_ADDR7_TX_Pos               (1U)
-#define USB_ADDR7_TX_ADDR7_TX_Msk               (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_TX_ADDR7_TX                   USB_ADDR7_TX_ADDR7_TX_Msk      /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define USB_COUNT0_TX_COUNT0_TX_Pos             (0U)
-#define USB_COUNT0_TX_COUNT0_TX_Msk             (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_TX_COUNT0_TX                 USB_COUNT0_TX_COUNT0_TX_Msk    /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define USB_COUNT1_TX_COUNT1_TX_Pos             (0U)
-#define USB_COUNT1_TX_COUNT1_TX_Msk             (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_TX_COUNT1_TX                 USB_COUNT1_TX_COUNT1_TX_Msk    /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define USB_COUNT2_TX_COUNT2_TX_Pos             (0U)
-#define USB_COUNT2_TX_COUNT2_TX_Msk             (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_TX_COUNT2_TX                 USB_COUNT2_TX_COUNT2_TX_Msk    /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define USB_COUNT3_TX_COUNT3_TX_Pos             (0U)
-#define USB_COUNT3_TX_COUNT3_TX_Msk             (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_TX_COUNT3_TX                 USB_COUNT3_TX_COUNT3_TX_Msk    /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define USB_COUNT4_TX_COUNT4_TX_Pos             (0U)
-#define USB_COUNT4_TX_COUNT4_TX_Msk             (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_TX_COUNT4_TX                 USB_COUNT4_TX_COUNT4_TX_Msk    /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define USB_COUNT5_TX_COUNT5_TX_Pos             (0U)
-#define USB_COUNT5_TX_COUNT5_TX_Msk             (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_TX_COUNT5_TX                 USB_COUNT5_TX_COUNT5_TX_Msk    /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define USB_COUNT6_TX_COUNT6_TX_Pos             (0U)
-#define USB_COUNT6_TX_COUNT6_TX_Msk             (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_TX_COUNT6_TX                 USB_COUNT6_TX_COUNT6_TX_Msk    /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define USB_COUNT7_TX_COUNT7_TX_Pos             (0U)
-#define USB_COUNT7_TX_COUNT7_TX_Msk             (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_TX_COUNT7_TX                 USB_COUNT7_TX_COUNT7_TX_Msk    /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define USB_COUNT0_TX_0_COUNT0_TX_0             0x000003FFU         /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define USB_COUNT0_TX_1_COUNT0_TX_1             0x03FF0000U         /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define USB_COUNT1_TX_0_COUNT1_TX_0             0x000003FFU         /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define USB_COUNT1_TX_1_COUNT1_TX_1             0x03FF0000U         /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define USB_COUNT2_TX_0_COUNT2_TX_0             0x000003FFU         /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define USB_COUNT2_TX_1_COUNT2_TX_1             0x03FF0000U         /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define USB_COUNT3_TX_0_COUNT3_TX_0             0x000003FFU         /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define USB_COUNT3_TX_1_COUNT3_TX_1             0x03FF0000U         /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define USB_COUNT4_TX_0_COUNT4_TX_0             0x000003FFU         /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define USB_COUNT4_TX_1_COUNT4_TX_1             0x03FF0000U         /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define USB_COUNT5_TX_0_COUNT5_TX_0             0x000003FFU         /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define USB_COUNT5_TX_1_COUNT5_TX_1             0x03FF0000U         /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define USB_COUNT6_TX_0_COUNT6_TX_0             0x000003FFU         /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define USB_COUNT6_TX_1_COUNT6_TX_1             0x03FF0000U         /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define USB_COUNT7_TX_0_COUNT7_TX_0             0x000003FFU         /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define USB_COUNT7_TX_1_COUNT7_TX_1             0x03FF0000U         /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define USB_ADDR0_RX_ADDR0_RX_Pos               (1U)
-#define USB_ADDR0_RX_ADDR0_RX_Msk               (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR0_RX_ADDR0_RX                   USB_ADDR0_RX_ADDR0_RX_Msk      /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define USB_ADDR1_RX_ADDR1_RX_Pos               (1U)
-#define USB_ADDR1_RX_ADDR1_RX_Msk               (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR1_RX_ADDR1_RX                   USB_ADDR1_RX_ADDR1_RX_Msk      /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define USB_ADDR2_RX_ADDR2_RX_Pos               (1U)
-#define USB_ADDR2_RX_ADDR2_RX_Msk               (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR2_RX_ADDR2_RX                   USB_ADDR2_RX_ADDR2_RX_Msk      /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define USB_ADDR3_RX_ADDR3_RX_Pos               (1U)
-#define USB_ADDR3_RX_ADDR3_RX_Msk               (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR3_RX_ADDR3_RX                   USB_ADDR3_RX_ADDR3_RX_Msk      /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define USB_ADDR4_RX_ADDR4_RX_Pos               (1U)
-#define USB_ADDR4_RX_ADDR4_RX_Msk               (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR4_RX_ADDR4_RX                   USB_ADDR4_RX_ADDR4_RX_Msk      /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define USB_ADDR5_RX_ADDR5_RX_Pos               (1U)
-#define USB_ADDR5_RX_ADDR5_RX_Msk               (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR5_RX_ADDR5_RX                   USB_ADDR5_RX_ADDR5_RX_Msk      /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define USB_ADDR6_RX_ADDR6_RX_Pos               (1U)
-#define USB_ADDR6_RX_ADDR6_RX_Msk               (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR6_RX_ADDR6_RX                   USB_ADDR6_RX_ADDR6_RX_Msk      /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define USB_ADDR7_RX_ADDR7_RX_Pos               (1U)
-#define USB_ADDR7_RX_ADDR7_RX_Msk               (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
-#define USB_ADDR7_RX_ADDR7_RX                   USB_ADDR7_RX_ADDR7_RX_Msk      /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define USB_COUNT0_RX_COUNT0_RX_Pos             (0U)
-#define USB_COUNT0_RX_COUNT0_RX_Msk             (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT0_RX_COUNT0_RX                 USB_COUNT0_RX_COUNT0_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT0_RX_NUM_BLOCK_Pos             (10U)
-#define USB_COUNT0_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT0_RX_NUM_BLOCK                 USB_COUNT0_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT0_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT0_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT0_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT0_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT0_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT0_RX_BLSIZE_Pos                (15U)
-#define USB_COUNT0_RX_BLSIZE_Msk                (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT0_RX_BLSIZE                    USB_COUNT0_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define USB_COUNT1_RX_COUNT1_RX_Pos             (0U)
-#define USB_COUNT1_RX_COUNT1_RX_Msk             (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT1_RX_COUNT1_RX                 USB_COUNT1_RX_COUNT1_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT1_RX_NUM_BLOCK_Pos             (10U)
-#define USB_COUNT1_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT1_RX_NUM_BLOCK                 USB_COUNT1_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT1_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT1_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT1_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT1_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT1_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT1_RX_BLSIZE_Pos                (15U)
-#define USB_COUNT1_RX_BLSIZE_Msk                (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT1_RX_BLSIZE                    USB_COUNT1_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define USB_COUNT2_RX_COUNT2_RX_Pos             (0U)
-#define USB_COUNT2_RX_COUNT2_RX_Msk             (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT2_RX_COUNT2_RX                 USB_COUNT2_RX_COUNT2_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT2_RX_NUM_BLOCK_Pos             (10U)
-#define USB_COUNT2_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT2_RX_NUM_BLOCK                 USB_COUNT2_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT2_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT2_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT2_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT2_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT2_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT2_RX_BLSIZE_Pos                (15U)
-#define USB_COUNT2_RX_BLSIZE_Msk                (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT2_RX_BLSIZE                    USB_COUNT2_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define USB_COUNT3_RX_COUNT3_RX_Pos             (0U)
-#define USB_COUNT3_RX_COUNT3_RX_Msk             (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT3_RX_COUNT3_RX                 USB_COUNT3_RX_COUNT3_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT3_RX_NUM_BLOCK_Pos             (10U)
-#define USB_COUNT3_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT3_RX_NUM_BLOCK                 USB_COUNT3_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT3_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT3_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT3_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT3_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT3_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT3_RX_BLSIZE_Pos                (15U)
-#define USB_COUNT3_RX_BLSIZE_Msk                (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT3_RX_BLSIZE                    USB_COUNT3_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define USB_COUNT4_RX_COUNT4_RX_Pos             (0U)
-#define USB_COUNT4_RX_COUNT4_RX_Msk             (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT4_RX_COUNT4_RX                 USB_COUNT4_RX_COUNT4_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT4_RX_NUM_BLOCK_Pos             (10U)
-#define USB_COUNT4_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT4_RX_NUM_BLOCK                 USB_COUNT4_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT4_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT4_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT4_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT4_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT4_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT4_RX_BLSIZE_Pos                (15U)
-#define USB_COUNT4_RX_BLSIZE_Msk                (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT4_RX_BLSIZE                    USB_COUNT4_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define USB_COUNT5_RX_COUNT5_RX_Pos             (0U)
-#define USB_COUNT5_RX_COUNT5_RX_Msk             (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT5_RX_COUNT5_RX                 USB_COUNT5_RX_COUNT5_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT5_RX_NUM_BLOCK_Pos             (10U)
-#define USB_COUNT5_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT5_RX_NUM_BLOCK                 USB_COUNT5_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT5_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT5_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT5_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT5_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT5_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT5_RX_BLSIZE_Pos                (15U)
-#define USB_COUNT5_RX_BLSIZE_Msk                (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT5_RX_BLSIZE                    USB_COUNT5_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define USB_COUNT6_RX_COUNT6_RX_Pos             (0U)
-#define USB_COUNT6_RX_COUNT6_RX_Msk             (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT6_RX_COUNT6_RX                 USB_COUNT6_RX_COUNT6_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT6_RX_NUM_BLOCK_Pos             (10U)
-#define USB_COUNT6_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT6_RX_NUM_BLOCK                 USB_COUNT6_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT6_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT6_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT6_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT6_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT6_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT6_RX_BLSIZE_Pos                (15U)
-#define USB_COUNT6_RX_BLSIZE_Msk                (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT6_RX_BLSIZE                    USB_COUNT6_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define USB_COUNT7_RX_COUNT7_RX_Pos             (0U)
-#define USB_COUNT7_RX_COUNT7_RX_Msk             (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
-#define USB_COUNT7_RX_COUNT7_RX                 USB_COUNT7_RX_COUNT7_RX_Msk    /*!< Reception Byte Count */
-
-#define USB_COUNT7_RX_NUM_BLOCK_Pos             (10U)
-#define USB_COUNT7_RX_NUM_BLOCK_Msk             (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
-#define USB_COUNT7_RX_NUM_BLOCK                 USB_COUNT7_RX_NUM_BLOCK_Msk    /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define USB_COUNT7_RX_NUM_BLOCK_0               (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
-#define USB_COUNT7_RX_NUM_BLOCK_1               (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
-#define USB_COUNT7_RX_NUM_BLOCK_2               (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
-#define USB_COUNT7_RX_NUM_BLOCK_3               (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
-#define USB_COUNT7_RX_NUM_BLOCK_4               (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
-
-#define USB_COUNT7_RX_BLSIZE_Pos                (15U)
-#define USB_COUNT7_RX_BLSIZE_Msk                (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
-#define USB_COUNT7_RX_BLSIZE                    USB_COUNT7_RX_BLSIZE_Msk       /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define USB_COUNT0_RX_0_COUNT0_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT0_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
-#define USB_COUNT0_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define USB_COUNT0_RX_1_COUNT0_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT0_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
-#define USB_COUNT0_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
-
-#define USB_COUNT0_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define USB_COUNT1_RX_0_COUNT1_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT1_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
-#define USB_COUNT1_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define USB_COUNT1_RX_1_COUNT1_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT1_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
-#define USB_COUNT1_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
-
-#define USB_COUNT1_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define USB_COUNT2_RX_0_COUNT2_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT2_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
-#define USB_COUNT2_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define USB_COUNT2_RX_1_COUNT2_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT2_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
-#define USB_COUNT2_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
-
-#define USB_COUNT2_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define USB_COUNT3_RX_0_COUNT3_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT3_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
-#define USB_COUNT3_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define USB_COUNT3_RX_1_COUNT3_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT3_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
-#define USB_COUNT3_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
-
-#define USB_COUNT3_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define USB_COUNT4_RX_0_COUNT4_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT4_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
-#define USB_COUNT4_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define USB_COUNT4_RX_1_COUNT4_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT4_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
-#define USB_COUNT4_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
-
-#define USB_COUNT4_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define USB_COUNT5_RX_0_COUNT5_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT5_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
-#define USB_COUNT5_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define USB_COUNT5_RX_1_COUNT5_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT5_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
-#define USB_COUNT5_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
-
-#define USB_COUNT5_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define USB_COUNT6_RX_0_COUNT6_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT6_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
-#define USB_COUNT6_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
-
-#define USB_COUNT6_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define USB_COUNT6_RX_1_COUNT6_RX_1             0x03FF0000U                   /*!< Reception Byte Count (high) */
-
-#define USB_COUNT6_RX_1_NUM_BLOCK_1             0x7C000000U                   /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_0           0x04000000U                   /*!< Bit 0 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_1           0x08000000U                   /*!< Bit 1 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_2           0x10000000U                   /*!< Bit 2 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_3           0x20000000U                   /*!< Bit 3 */
-#define USB_COUNT6_RX_1_NUM_BLOCK_1_4           0x40000000U                   /*!< Bit 4 */
-
-#define USB_COUNT6_RX_1_BLSIZE_1                0x80000000U                   /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define USB_COUNT7_RX_0_COUNT7_RX_0             0x000003FFU                    /*!< Reception Byte Count (low) */
-
-#define USB_COUNT7_RX_0_NUM_BLOCK_0             0x00007C00U                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_0           0x00000400U                    /*!< Bit 0 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_1           0x00000800U                    /*!< Bit 1 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_2           0x00001000U                    /*!< Bit 2 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_3           0x00002000U                    /*!< Bit 3 */
-#define USB_COUNT7_RX_0_NUM_BLOCK_0_4           0x00004000U                    /*!< Bit 4 */
-
-#define USB_COUNT7_RX_0_BLSIZE_0                0x00008000U                    /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define USB_COUNT7_RX_1_COUNT7_RX_1             0x03FF0000U                    /*!< Reception Byte Count (high) */
-
-#define USB_COUNT7_RX_1_NUM_BLOCK_1             0x7C000000U                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_0           0x04000000U                    /*!< Bit 0 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_1           0x08000000U                    /*!< Bit 1 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_2           0x10000000U                    /*!< Bit 2 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_3           0x20000000U                    /*!< Bit 3 */
-#define USB_COUNT7_RX_1_NUM_BLOCK_1_4           0x40000000U                    /*!< Bit 4 */
-
 #define USB_COUNT7_RX_1_BLSIZE_1                0x80000000U                    /*!< BLock SIZE (high) */
 
-
 /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
   * @{
   */

port/stm32/README.md

@@ -1,10 +0,0 @@
-# 基本工程生成
-
-- 首先使用 stm32cubemx 使能系统时钟、USB时钟、USB引脚，勾选 USB外设、使能 USB 中断，然后产生基本工程。
-- 如果使用的是 usb_dc_nohal.c，需要注释掉 MX_USB_PCD_Init 函数，USB 中断中调用 USBD_IRQHandler 替代 HAL_PCD_IRQHandler 函数，HAL_PCD_MspInit 函数保留
-- 如果使用的是 usb_dc_hal.c 则上条不需要
-- 推荐使用 nohal 版本，极简代码
-
-
-## 该目录下porting可以不再使用，选择 fsdev 或者 synopsys下的porting接口
-

port/stm32/usb_dc_hal.c

@@ -1,441 +0,0 @@
-#include "usbd_core.h"
-#include "usbd_config.h"
-
-#ifndef USB_NUM_BIDIR_ENDPOINTS
-#define USB_NUM_BIDIR_ENDPOINTS 6
-#endif
-
-#ifdef USB
-#ifndef USB_RAM_SIZE
-#define USB_RAM_SIZE 512
-#endif
-extern PCD_HandleTypeDef hpcd_USB_FS;
-#define PCD_HANDLE &hpcd_USB_FS
-#else
-
-#ifdef CONFIG_USB_HS
-
-#ifndef USB_RAM_SIZE
-#define USB_RAM_SIZE 4096
-#endif
-extern PCD_HandleTypeDef hpcd_USB_OTG_HS;
-#define PCD_HANDLE &hpcd_USB_OTG_HS
-
-#else
-
-#ifndef USB_RAM_SIZE
-#define USB_RAM_SIZE 1280
-#endif
-//extern PCD_HandleTypeDef hpcd_USB_OTG_HS;
-//#define PCD_HANDLE &hpcd_USB_OTG_HS
-extern PCD_HandleTypeDef hpcd_USB_OTG_FS;
-#define PCD_HANDLE &hpcd_USB_OTG_FS
-#endif
-#endif
-
-#ifdef USB
-
-#define EP0_MPS 64U
-#define EP_MPS  64U
-
-/*
- * USB BTABLE is stored in the PMA. The size of BTABLE is 4 bytes
- * per endpoint.
- *
- */
-#define USB_BTABLE_SIZE (8 * USB_NUM_BIDIR_ENDPOINTS)
-
-#else /* USB_OTG_FS */
-#define EP0_MPS USB_OTG_MAX_EP0_SIZE
-
-#ifdef CONFIG_USB_HS
-#define EP_MPS USB_OTG_HS_MAX_PACKET_SIZE
-#else
-#define EP_MPS USB_OTG_FS_MAX_PACKET_SIZE
-#endif
-
-#define CONTROL_EP_NUM   1
-/*this should user make config*/
-#define OUT_EP_NUM       2
-#define OUT_EP_MPS       1024
-#define EP_RX_FIFO_WORDS ((4 * CONTROL_EP_NUM + 6) + ((OUT_EP_MPS / 4) + 1) + 2 * OUT_EP_NUM + 1)
-#define EP_TX_FIFO_WORDS 0x40
-
-#endif /* USB */
-
-/* Endpoint state */
-struct usb_dc_ep_state {
-    uint16_t ep_mps; /** Endpoint max packet size */
-#ifdef USB
-    uint16_t ep_pma_buf_len; /** Previously allocated buffer size */
-#endif
-    uint8_t ep_type;      /** Endpoint type (STM32 HAL enum) */
-    uint8_t ep_stalled;   /** Endpoint stall flag */
-    uint32_t read_count;  /** Number of bytes in read buffer  */
-    uint32_t read_offset; /** Current offset in read buffer */
-};
-
-/* Driver state */
-struct usb_dc_pcd_state {
-    struct usb_dc_ep_state out_ep_state[USB_NUM_BIDIR_ENDPOINTS];
-    struct usb_dc_ep_state in_ep_state[USB_NUM_BIDIR_ENDPOINTS];
-    uint8_t ep_buf[USB_NUM_BIDIR_ENDPOINTS][EP_MPS];
-
-#ifdef USB
-    uint32_t pma_offset;
-#endif /* USB */
-};
-
-static struct usb_dc_pcd_state usb_dc_pcd_state;
-
-/* Internal functions */
-
-static struct usb_dc_ep_state *usb_dc_stm32_get_ep_state(uint8_t ep)
-{
-    struct usb_dc_ep_state *ep_state_base;
-
-    if (USB_EP_GET_IDX(ep) >= USB_NUM_BIDIR_ENDPOINTS) {
-        return NULL;
-    }
-
-    if (USB_EP_DIR_IS_OUT(ep)) {
-        ep_state_base = usb_dc_pcd_state.out_ep_state;
-    } else {
-        ep_state_base = usb_dc_pcd_state.in_ep_state;
-    }
-
-    return ep_state_base + USB_EP_GET_IDX(ep);
-}
-
-int usb_dc_init(void)
-{
-    HAL_StatusTypeDef status;
-    unsigned int i;
-
-    /*pcd has init*/
-    status = HAL_PCD_Start(PCD_HANDLE);
-    if (status != HAL_OK) {
-        return -2;
-    }
-
-    usb_dc_pcd_state.out_ep_state[0].ep_mps = EP0_MPS;
-    usb_dc_pcd_state.out_ep_state[0].ep_type = EP_TYPE_CTRL;
-    usb_dc_pcd_state.in_ep_state[0].ep_mps = EP0_MPS;
-    usb_dc_pcd_state.in_ep_state[0].ep_type = EP_TYPE_CTRL;
-
-#ifdef USB
-    /* Start PMA configuration for the endpoints after the BTABLE. */
-    usb_dc_pcd_state.pma_offset = USB_BTABLE_SIZE;
-#else /* USB_OTG_FS */
-    /* TODO: make this dynamic (depending usage) */
-    HAL_PCDEx_SetRxFiFo(PCD_HANDLE, EP_RX_FIFO_WORDS);
-    for (i = 0U; i < USB_NUM_BIDIR_ENDPOINTS; i++) {
-        HAL_PCDEx_SetTxFiFo(PCD_HANDLE, i,
-                            EP_TX_FIFO_WORDS);
-    }
-#endif /* USB */
-    return 0;
-}
-
-void usb_dc_deinit(void)
-{
-}
-
-int usbd_set_address(const uint8_t addr)
-{
-    HAL_StatusTypeDef status;
-
-    status = HAL_PCD_SetAddress(PCD_HANDLE, addr);
-    if (status != HAL_OK) {
-        return -2;
-    }
-
-    return 0;
-}
-
-int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
-{
-    HAL_StatusTypeDef status;
-    uint8_t ep = ep_cfg->ep_addr;
-    struct usb_dc_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
-
-    if (!ep_state) {
-        return -1;
-    }
-
-#ifdef USB
-    if (ep_cfg->ep_mps > ep_state->ep_pma_buf_len) {
-        if (USB_RAM_SIZE <=
-            (usb_dc_pcd_state.pma_offset + ep_cfg->ep_mps)) {
-            return -1;
-        }
-        HAL_PCDEx_PMAConfig(&hpcd_USB_FS, ep, PCD_SNG_BUF,
-                            usb_dc_pcd_state.pma_offset);
-        ep_state->ep_pma_buf_len = ep_cfg->ep_mps;
-        usb_dc_pcd_state.pma_offset += ep_cfg->ep_mps;
-    }
-#endif
-    ep_state->ep_mps = ep_cfg->ep_mps;
-
-    switch (ep_cfg->ep_type) {
-        case USBD_EP_TYPE_CTRL:
-            ep_state->ep_type = EP_TYPE_CTRL;
-            break;
-        case USBD_EP_TYPE_ISOC:
-            ep_state->ep_type = EP_TYPE_ISOC;
-            break;
-        case USBD_EP_TYPE_BULK:
-            ep_state->ep_type = EP_TYPE_BULK;
-            break;
-        case USBD_EP_TYPE_INTR:
-            ep_state->ep_type = EP_TYPE_INTR;
-            break;
-        default:
-            return -1;
-    }
-
-    status = HAL_PCD_EP_Open(PCD_HANDLE, ep,
-                             ep_state->ep_mps, ep_state->ep_type);
-    if (status != HAL_OK) {
-        return -1;
-    }
-
-    if (USB_EP_DIR_IS_OUT(ep) && ep != USB_CONTROL_OUT_EP0) {
-        return HAL_PCD_EP_Receive(PCD_HANDLE, ep,
-                                  usb_dc_pcd_state.ep_buf[USB_EP_GET_IDX(ep)],
-                                  EP_MPS);
-    }
-    return 0;
-}
-int usbd_ep_close(const uint8_t ep)
-{
-    struct usb_dc_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
-    HAL_StatusTypeDef status;
-
-    if (!ep_state) {
-        return -1;
-    }
-
-    status = HAL_PCD_EP_Close(PCD_HANDLE, ep);
-    if (status != HAL_OK) {
-        return -2;
-    }
-
-    return 0;
-}
-int usbd_ep_set_stall(const uint8_t ep)
-{
-    struct usb_dc_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
-    HAL_StatusTypeDef status;
-
-    if (!ep_state) {
-        return -1;
-    }
-
-    status = HAL_PCD_EP_SetStall(PCD_HANDLE, ep);
-    if (status != HAL_OK) {
-        return -2;
-    }
-
-    ep_state->ep_stalled = 1U;
-
-    return 0;
-}
-int usbd_ep_clear_stall(const uint8_t ep)
-{
-    struct usb_dc_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
-    HAL_StatusTypeDef status;
-
-    if (!ep_state) {
-        return -1;
-    }
-
-    status = HAL_PCD_EP_ClrStall(PCD_HANDLE, ep);
-    if (status != HAL_OK) {
-        return -2;
-    }
-
-    ep_state->ep_stalled = 0U;
-    ep_state->read_count = 0U;
-
-    return 0;
-}
-int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
-{
-    struct usb_dc_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
-
-    if (!ep_state || !stalled) {
-        return -1;
-    }
-
-    *stalled = ep_state->ep_stalled;
-
-    return 0;
-}
-
-int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes)
-{
-    struct usb_dc_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
-    HAL_StatusTypeDef status;
-    int ret = 0;
-
-    if (!ep_state || !USB_EP_DIR_IS_IN(ep)) {
-        return -1;
-    }
-
-    if (ep == USB_CONTROL_IN_EP0 && data_len > 64) {
-        data_len = 64;
-    }
-
-    status = HAL_PCD_EP_Transmit(PCD_HANDLE, ep,
-                                 (void *)data, data_len);
-    if (status != HAL_OK) {
-        ret = -2;
-    }
-
-    if (!ret && ep == USB_CONTROL_IN_EP0 && data_len > 0) {
-        /* Wait for an empty package as from the host.
-		 * This also flushes the TX FIFO to the host.
-		 */
-        status = HAL_PCD_EP_Receive(PCD_HANDLE, ep,
-                                    usb_dc_pcd_state.ep_buf[USB_EP_GET_IDX(ep)],
-                                    0);
-        if (status != HAL_OK) {
-            return -2;
-        }
-    }
-
-    if (!ret && ret_bytes) {
-        *ret_bytes = data_len;
-    }
-
-    return ret;
-}
-
-int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_t *read_bytes)
-{
-    struct usb_dc_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
-    uint32_t read_count;
-    HAL_StatusTypeDef status;
-
-    if (!ep_state) {
-        return -1;
-    }
-    if (!USB_EP_DIR_IS_OUT(ep)) { /* check if OUT ep */
-
-        return -1;
-    }
-    if (!data && max_data_len) {
-        return -1;
-    }
-
-    if (max_data_len == 0) {
-        /* If no more data in the buffer, start a new read transaction.
-        * DataOutStageCallback will called on transaction complete.
-        */
-        if (!ep_state->read_count) {
-            status = HAL_PCD_EP_Receive(PCD_HANDLE, ep,
-                                        usb_dc_pcd_state.ep_buf[USB_EP_GET_IDX(ep)],
-                                        EP_MPS);
-            if (status != HAL_OK) {
-                return -2;
-            }
-        }
-        return 0;
-    }
-
-    ep_state->read_count = HAL_PCD_EP_GetRxCount(PCD_HANDLE, ep);
-    ep_state->read_offset = 0U;
-    read_count = ep_state->read_count;
-
-    /* When both buffer and max data to read are zero, just ingore reading
-	 * and return available data in buffer. Otherwise, return data
-	 * previously stored in the buffer.
-	 */
-    if (data) {
-        read_count = MIN(read_count, max_data_len);
-        memcpy(data, usb_dc_pcd_state.ep_buf[USB_EP_GET_IDX(ep)] + ep_state->read_offset, read_count);
-        ep_state->read_count -= read_count;
-        ep_state->read_offset += read_count;
-    }
-
-    /* If no more data in the buffer, start a new read transaction.
-	 * DataOutStageCallback will called on transaction complete.
-	 */
-#if 0
-    if (!ep_state->read_count) {
-        status = HAL_PCD_EP_Receive(PCD_HANDLE, ep,
-                                    usb_dc_pcd_state.ep_buf[USB_EP_GET_IDX(ep)],
-                                    EP_MPS);
-        if (status != HAL_OK) {
-            return -2;
-        }
-    }
-#endif
-    if (read_bytes) {
-        *read_bytes = read_count;
-    }
-
-    return 0;
-}
-
-/* Callbacks from the STM32 Cube HAL code */
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
-{
-}
-
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
-{
-    usbd_event_notify_handler(USBD_EVENT_RESET, NULL);
-}
-
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
-{
-}
-
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
-{
-}
-
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
-{
-}
-
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
-{
-}
-
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
-{
-    struct usb_setup_packet *setup = (void *)hpcd->Setup;
-
-    memcpy(&usb_dc_pcd_state.ep_buf[0],
-           hpcd->Setup, 8);
-
-    usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
-    if (!(setup->wLength == 0U) &&
-        !(REQTYPE_GET_DIR(setup->bmRequestType) ==
-          USB_REQUEST_DIR_IN)) {
-        HAL_PCD_EP_Receive(PCD_HANDLE, 0x00,
-                           usb_dc_pcd_state.ep_buf[0],
-                           setup->wLength);
-    }
-}
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-    if (epnum == 0) {
-        usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
-    } else {
-        usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(epnum | USB_EP_DIR_OUT));
-    }
-}
-
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-    if (epnum == 0) {
-        usbd_event_notify_handler(USBD_EVENT_EP0_IN_NOTIFY, NULL);
-    } else {
-        usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(epnum | USB_EP_DIR_IN));
-    }
-}

port/stm32/usb_dc_nohal.c

@@ -1,773 +0,0 @@
-#include "usbd_core.h"
-#include "usbd_config.h"
-
-#ifndef USB_NUM_BIDIR_ENDPOINTS
-#define USB_NUM_BIDIR_ENDPOINTS 8
-#endif
-
-#ifdef USB
-#ifndef USB_RAM_SIZE
-#define USB_RAM_SIZE 512
-#endif
-#define USB_BTABLE_SIZE (8 * USB_NUM_BIDIR_ENDPOINTS)
-#else
-
-#ifdef CONFIG_USB_HS
-
-#ifndef USB_RAM_SIZE
-#define USB_RAM_SIZE 4096
-#endif
-#else
-
-#ifndef USB_RAM_SIZE
-#define USB_RAM_SIZE 1280
-#endif
-
-#endif
-
-#endif
-/* Endpoint state */
-struct usb_dc_ep_state {
-    /** Endpoint max packet size */
-    uint16_t ep_mps;
-    /** Endpoint Transfer Type.
-     * May be Bulk, Interrupt, Control or Isochronous
-     */
-    uint8_t ep_type;
-    uint8_t ep_stalled; /** Endpoint stall flag */
-#ifdef USB
-    uint16_t ep_pma_buf_len; /** Previously allocated buffer size */
-    uint16_t ep_pma_addr;    /**ep pmd allocated addr*/
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-#endif
-};
-
-/* Driver state */
-struct usb_dc_config_priv {
-    PCD_TypeDef *Instance;                                  /*!< Register base address */
-    PCD_InitTypeDef Init;                                   /*!< PCD required parameters */
-    __IO uint8_t USB_Address;                               /*!< USB Address */
-    struct usb_dc_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS];  /*!< IN endpoint parameters*/
-    struct usb_dc_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
-#ifdef USB
-    uint32_t pma_offset;
-#endif
-} usb_dc_cfg;
-
-int usb_dc_init(void)
-{
-    memset(&usb_dc_cfg, 0, sizeof(struct usb_dc_config_priv));
-#ifdef USB
-    usb_dc_cfg.Instance = USB;
-    usb_dc_cfg.pma_offset = USB_BTABLE_SIZE;
-    usb_dc_cfg.Init.speed = PCD_SPEED_FULL;
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-#ifdef CONFIG_USB_HS
-    usb_dc_cfg.Instance = USB_OTG_HS;
-    usb_dc_cfg.Init.speed = PCD_SPEED_FULL;
-    usb_dc_cfg.Init.dma_enable = DISABLE;
-    usb_dc_cfg.Init.phy_itface = USB_OTG_ULPI_PHY;
-    usb_dc_cfg.Init.vbus_sensing_enable = DISABLE;
-    usb_dc_cfg.Init.use_dedicated_ep1 = DISABLE;
-    usb_dc_cfg.Init.use_external_vbus = DISABLE;
-#else
-    //usb_dc_cfg.Instance = USB_OTG_HS;  //run in full speed
-    usb_dc_cfg.Instance = USB_OTG_FS;
-    usb_dc_cfg.Init.speed = PCD_SPEED_FULL;
-    usb_dc_cfg.Init.dma_enable = DISABLE;
-    usb_dc_cfg.Init.phy_itface = USB_OTG_EMBEDDED_PHY;
-    usb_dc_cfg.Init.vbus_sensing_enable = DISABLE;
-    usb_dc_cfg.Init.use_dedicated_ep1 = DISABLE;
-    usb_dc_cfg.Init.use_external_vbus = DISABLE;
-#endif
-#endif
-    PCD_TypeDef *USBx = usb_dc_cfg.Instance;
-
-    usb_dc_cfg.Init.dev_endpoints = USB_NUM_BIDIR_ENDPOINTS;
-    usb_dc_cfg.Init.Sof_enable = DISABLE;
-    usb_dc_cfg.Init.low_power_enable = DISABLE;
-    usb_dc_cfg.Init.lpm_enable = DISABLE;
-
-    HAL_PCD_MspInit((PCD_HandleTypeDef *)&usb_dc_cfg);
-
-#ifdef USB
-    USB_DisableGlobalInt(USBx);
-    USB_DevInit(USBx, usb_dc_cfg.Init);
-    USB_EnableGlobalInt(USBx);
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-    /* Disable DMA mode for FS instance */
-#ifndef CONFIG_USB_HS
-    if ((USBx->CID & (0x1U << 8)) == 0U) {
-        usb_dc_cfg.Init.dma_enable = 0U;
-    }
-#endif
-    /* Disable the Interrupts */
-    USB_DisableGlobalInt(USBx);
-
-    /*Init the Core (common init.) */
-    if (USB_CoreInit(usb_dc_cfg.Instance, usb_dc_cfg.Init) != HAL_OK) {
-        return -1;
-    }
-
-    /* Force Device Mode*/
-    (void)USB_SetCurrentMode(USBx, USB_DEVICE_MODE);
-
-    /* Init Device */
-    if (USB_DevInit(USBx, usb_dc_cfg.Init) != HAL_OK) {
-        return -1;
-    }
-
-    USB_DevDisconnect(USBx);
-
-    if ((usb_dc_cfg.Init.battery_charging_enable == 1U) &&
-        (usb_dc_cfg.Init.phy_itface != USB_OTG_ULPI_PHY)) {
-        /* Enable USB Transceiver */
-        USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN;
-    }
-    (void)USB_DevConnect(USBx);
-    /* Enable the Interrupts */
-    USB_EnableGlobalInt(USBx);
-#endif
-    return 0;
-}
-
-void usb_dc_deinit(void)
-{
-    PCD_TypeDef *USBx = usb_dc_cfg.Instance;
-    USB_StopDevice(USBx);
-    HAL_PCD_MspDeInit((PCD_HandleTypeDef *)&usb_dc_cfg);
-}
-
-int usbd_set_address(const uint8_t addr)
-{
-    PCD_TypeDef *USBx = usb_dc_cfg.Instance;
-
-    USB_SetDevAddress(USBx, addr);
-    usb_dc_cfg.USB_Address = addr;
-    return 0;
-}
-
-int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
-{
-    PCD_TypeDef *USBx = usb_dc_cfg.Instance;
-    uint8_t ep_idx = USB_EP_GET_IDX(ep_cfg->ep_addr);
-#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
-    uint32_t USBx_BASE = (uint32_t)USBx;
-#endif
-    if (!ep_cfg) {
-        return -1;
-    }
-
-#ifdef USB
-    uint16_t wEpRegVal;
-
-    wEpRegVal = PCD_GET_ENDPOINT(USBx, ep_idx) & USB_EP_T_MASK;
-    /* initialize Endpoint */
-    switch (ep_cfg->ep_type) {
-        case EP_TYPE_CTRL:
-            wEpRegVal |= USB_EP_CONTROL;
-            break;
-
-        case EP_TYPE_BULK:
-            wEpRegVal |= USB_EP_BULK;
-            break;
-
-        case EP_TYPE_INTR:
-            wEpRegVal |= USB_EP_INTERRUPT;
-            break;
-
-        case EP_TYPE_ISOC:
-            wEpRegVal |= USB_EP_ISOCHRONOUS;
-            break;
-
-        default:
-            break;
-    }
-    PCD_SET_ENDPOINT(USBx, ep_idx, (wEpRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX));
-
-    PCD_SET_EP_ADDRESS(USBx, ep_idx, ep_idx);
-    if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) {
-        usb_dc_cfg.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
-        usb_dc_cfg.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
-        if (usb_dc_cfg.out_ep[ep_idx].ep_mps > usb_dc_cfg.out_ep[ep_idx].ep_pma_buf_len) {
-            if (usb_dc_cfg.pma_offset + usb_dc_cfg.out_ep[ep_idx].ep_mps >= 512) {
-                return -1;
-            }
-            usb_dc_cfg.out_ep[ep_idx].ep_pma_buf_len = ep_cfg->ep_mps;
-            usb_dc_cfg.out_ep[ep_idx].ep_pma_addr = usb_dc_cfg.pma_offset;
-            /*Set the endpoint Receive buffer address */
-            PCD_SET_EP_RX_ADDRESS(USBx, ep_idx, usb_dc_cfg.pma_offset);
-            usb_dc_cfg.pma_offset += ep_cfg->ep_mps;
-        }
-        /*Set the endpoint Receive buffer counter*/
-        PCD_SET_EP_RX_CNT(USBx, ep_idx, ep_cfg->ep_mps);
-        PCD_CLEAR_RX_DTOG(USBx, ep_idx);
-
-        /* Configure VALID status for the Endpoint*/
-        PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_VALID);
-    } else {
-        usb_dc_cfg.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
-        usb_dc_cfg.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
-        if (usb_dc_cfg.in_ep[ep_idx].ep_mps > usb_dc_cfg.in_ep[ep_idx].ep_pma_buf_len) {
-            if (usb_dc_cfg.pma_offset + usb_dc_cfg.in_ep[ep_idx].ep_mps >= USB_RAM_SIZE) {
-                return -1;
-            }
-            usb_dc_cfg.in_ep[ep_idx].ep_pma_buf_len = ep_cfg->ep_mps;
-            usb_dc_cfg.in_ep[ep_idx].ep_pma_addr = usb_dc_cfg.pma_offset;
-            /*Set the endpoint Transmit buffer address */
-            PCD_SET_EP_TX_ADDRESS(USBx, ep_idx, usb_dc_cfg.pma_offset);
-            usb_dc_cfg.pma_offset += ep_cfg->ep_mps;
-        }
-
-        PCD_CLEAR_TX_DTOG(USBx, ep_idx);
-        if (ep_cfg->ep_type != EP_TYPE_ISOC) {
-            /* Configure NAK status for the Endpoint */
-            PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_NAK);
-        } else {
-            /* Configure TX Endpoint to disabled state */
-            PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_DIS);
-        }
-    }
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-    if (USB_EP_DIR_IS_OUT(ep_cfg->ep_addr)) {
-        usb_dc_cfg.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
-        usb_dc_cfg.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
-        USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep_idx & EP_ADDR_MSK)) << 16);
-
-        if (((USBx_OUTEP(ep_idx)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) {
-            USBx_OUTEP(ep_idx)->DOEPCTL |= (ep_cfg->ep_mps & USB_OTG_DOEPCTL_MPSIZ) |
-                                           ((uint32_t)ep_cfg->ep_type << 18) |
-                                           USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
-                                           USB_OTG_DOEPCTL_USBAEP;
-        }
-
-    } else {
-        usb_dc_cfg.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
-        usb_dc_cfg.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
-        USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep_idx & EP_ADDR_MSK));
-
-        if ((USBx_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) {
-            USBx_INEP(ep_idx)->DIEPCTL |= (ep_cfg->ep_mps & USB_OTG_DIEPCTL_MPSIZ) |
-                                          ((uint32_t)ep_cfg->ep_type << 18) | (ep_idx << 22) |
-                                          USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
-                                          USB_OTG_DIEPCTL_USBAEP;
-        }
-    }
-
-#endif
-
-    return 0;
-}
-int usbd_ep_close(const uint8_t ep)
-{
-    PCD_TypeDef *USBx = usb_dc_cfg.Instance;
-    uint8_t ep_idx = USB_EP_GET_IDX(ep);
-#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
-    uint32_t USBx_BASE = (uint32_t)USBx;
-#endif
-    if (USB_EP_DIR_IS_OUT(ep)) {
-#ifdef USB
-        PCD_CLEAR_RX_DTOG(USBx, ep_idx);
-
-        /* Configure DISABLE status for the Endpoint*/
-        PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_DIS);
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-        if (((USBx_OUTEP(ep_idx)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) {
-            USBx_OUTEP(ep_idx)->DOEPCTL |= (usb_dc_cfg.out_ep[ep_idx].ep_mps & USB_OTG_DOEPCTL_MPSIZ) |
-                                           ((uint32_t)usb_dc_cfg.out_ep[ep_idx].ep_type << 18) | (ep_idx << 22) |
-                                           USB_OTG_DOEPCTL_USBAEP;
-        }
-
-        USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep_idx & EP_ADDR_MSK)) << 16);
-#endif
-    } else {
-#ifdef USB
-        PCD_CLEAR_TX_DTOG(USBx, ep_idx);
-
-        /* Configure DISABLE status for the Endpoint*/
-        PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_DIS);
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-        if (((USBx_INEP(ep_idx)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) {
-            USBx_INEP(ep_idx)->DIEPCTL |= (usb_dc_cfg.in_ep[ep_idx].ep_mps & USB_OTG_DIEPCTL_MPSIZ) |
-                                          ((uint32_t)usb_dc_cfg.in_ep[ep_idx].ep_type << 18) | (ep_idx << 22) |
-                                          USB_OTG_DIEPCTL_SD0PID_SEVNFRM |
-                                          USB_OTG_DIEPCTL_USBAEP;
-        }
-
-        USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep_idx & EP_ADDR_MSK));
-#endif
-    }
-    return 0;
-}
-int usbd_ep_set_stall(const uint8_t ep)
-{
-    PCD_TypeDef *USBx = usb_dc_cfg.Instance;
-    uint8_t ep_idx = USB_EP_GET_IDX(ep);
-#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
-    uint32_t USBx_BASE = (uint32_t)USBx;
-#endif
-    if (USB_EP_DIR_IS_OUT(ep)) {
-#ifdef USB
-        PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_STALL);
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-        if (((USBx_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (ep_idx != 0U)) {
-            USBx_OUTEP(ep_idx)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
-        }
-        USBx_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
-#endif
-    } else {
-#ifdef USB
-        PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_STALL);
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-        if (((USBx_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (ep_idx != 0U)) {
-            USBx_INEP(ep_idx)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
-        }
-        USBx_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
-#endif
-    }
-    return 0;
-}
-int usbd_ep_clear_stall(const uint8_t ep)
-{
-    PCD_TypeDef *USBx = usb_dc_cfg.Instance;
-    uint8_t ep_idx = USB_EP_GET_IDX(ep);
-#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
-    uint32_t USBx_BASE = (uint32_t)USBx;
-#endif
-    if (USB_EP_DIR_IS_OUT(ep)) {
-#ifdef USB
-        PCD_CLEAR_TX_DTOG(USBx, ep_idx);
-
-        if (usb_dc_cfg.in_ep[ep_idx].ep_type != EP_TYPE_ISOC) {
-            /* Configure NAK status for the Endpoint */
-            PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_NAK);
-        }
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-        USBx_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
-        if ((usb_dc_cfg.out_ep[ep_idx].ep_type == EP_TYPE_INTR) || (usb_dc_cfg.out_ep[ep_idx].ep_type == EP_TYPE_BULK)) {
-            USBx_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
-        }
-#endif
-    } else {
-#ifdef USB
-        PCD_CLEAR_RX_DTOG(USBx, ep_idx);
-        /* Configure VALID status for the Endpoint */
-        PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_VALID);
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-        USBx_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
-        if ((usb_dc_cfg.in_ep[ep_idx].ep_type == EP_TYPE_INTR) || (usb_dc_cfg.in_ep[ep_idx].ep_type == EP_TYPE_BULK)) {
-            USBx_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
-        }
-#endif
-    }
-    return 0;
-}
-int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
-{
-    PCD_TypeDef *USBx = usb_dc_cfg.Instance;
-    uint8_t ep_idx = USB_EP_GET_IDX(ep);
-#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
-    uint32_t USBx_BASE = (uint32_t)USBx;
-#endif
-    if (USB_EP_DIR_IS_OUT(ep)) {
-    } else {
-    }
-    return 0;
-}
-
-int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes)
-{
-    PCD_TypeDef *USBx = usb_dc_cfg.Instance;
-    uint8_t ep_idx = USB_EP_GET_IDX(ep);
-#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
-    uint32_t USBx_BASE = (uint32_t)USBx;
-#endif
-
-    if (!data && data_len) {
-        return -1;
-    }
-
-    if (!data_len) {
-#ifdef USB
-        PCD_SET_EP_TX_CNT(USBx, ep_idx, (uint16_t)0);
-        PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_VALID);
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-        USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
-        USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
-        USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-
-        /* EP enable, IN data in FIFO */
-        USBx_INEP(ep_idx)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-
-#endif
-        return 0;
-    }
-
-    if (data_len > usb_dc_cfg.in_ep[ep_idx].ep_mps) {
-        data_len = usb_dc_cfg.in_ep[ep_idx].ep_mps;
-    }
-#ifdef USB
-    USB_WritePMA(USBx, (uint8_t *)data, usb_dc_cfg.in_ep[ep_idx].ep_pma_addr, (uint16_t)data_len);
-    PCD_SET_EP_TX_CNT(USBx, ep_idx, (uint16_t)data_len);
-    PCD_SET_EP_TX_STATUS(USBx, ep_idx, USB_EP_TX_VALID);
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-
-    if (ep_idx == 0x00) {
-        /* Program the transfer size and packet count
-      * as follows: xfersize = N * maxpacket +
-      * short_packet pktcnt = N + (short_packet
-      * exist ? 1 : 0)
-      */
-        USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-        USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
-        USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19));
-        USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & data_len);
-
-        /* EP enable, IN data in FIFO */
-        USBx_INEP(ep_idx)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-
-        /* Enable the Tx FIFO Empty Interrupt for this EP */
-        USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep_idx & EP_ADDR_MSK);
-
-    } else {
-        /* Program the transfer size and packet count
-      * as follows: xfersize = N * maxpacket +
-      * short_packet pktcnt = N + (short_packet
-      * exist ? 1 : 0)
-      */
-        uint32_t len32b = (data_len + 3) / 4;
-        while ((USBx_INEP(ep_idx)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) {
-        }
-
-        USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
-        USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
-        USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((data_len + usb_dc_cfg.in_ep[ep_idx].ep_mps - 1U) / usb_dc_cfg.in_ep[ep_idx].ep_mps) << 19));
-        USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & data_len);
-
-        if (usb_dc_cfg.in_ep[ep_idx].ep_type == EP_TYPE_ISOC) {
-            USBx_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
-            USBx_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29));
-        }
-
-        (void)USB_WritePacket(USBx, (uint8_t *)data, ep_idx, (uint16_t)data_len, 0);
-
-        /* EP enable, IN data in FIFO */
-        USBx_INEP(ep_idx)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-
-        if (usb_dc_cfg.in_ep[ep_idx].ep_type != EP_TYPE_ISOC) {
-            /* Enable the Tx FIFO Empty Interrupt for this EP */
-            //USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep_idx & EP_ADDR_MSK);
-        } else {
-            if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) {
-                USBx_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
-            } else {
-                USBx_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
-            }
-        }
-    }
-
-#endif
-    if (ret_bytes) {
-        *ret_bytes = data_len;
-    }
-
-    return 0;
-}
-
-int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_t *read_bytes)
-{
-    PCD_TypeDef *USBx = usb_dc_cfg.Instance;
-    uint8_t ep_idx = USB_EP_GET_IDX(ep);
-#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
-    uint32_t USBx_BASE = (uint32_t)USBx;
-#endif
-
-    uint32_t read_count;
-    if (!data && max_data_len) {
-        return -1;
-    }
-
-    if (!max_data_len) {
-#ifdef USB
-        if (ep_idx != 0x00)
-            PCD_SET_EP_RX_STATUS(USBx, ep_idx, USB_EP_RX_VALID);
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-        /* Program the transfer size and packet count as follows:
-    * pktcnt = N
-    * xfersize = N * maxpacket
-    */
-        USBx_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
-        USBx_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
-        USBx_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
-        USBx_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (usb_dc_cfg.out_ep[ep_idx].ep_mps));
-
-        if (usb_dc_cfg.out_ep[ep_idx].ep_type == EP_TYPE_ISOC) {
-            if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) {
-                USBx_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
-            } else {
-                USBx_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
-            }
-        }
-        /* EP enable */
-        USBx_OUTEP(ep_idx)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
-
-#endif
-        return 0;
-    }
-#ifdef USB
-    read_count = PCD_GET_EP_RX_CNT(USBx, ep_idx);
-    read_count = MIN(read_count, max_data_len);
-    USB_ReadPMA(USBx, (uint8_t *)data,
-                usb_dc_cfg.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-
-    read_count = (USBx->GRXSTSP & USB_OTG_GRXSTSP_BCNT) >> 4;
-    read_count = MIN(read_count, max_data_len);
-    (void)USB_ReadPacket(USBx, data, read_count);
-
-    USBx_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
-    USBx_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
-    USBx_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19));
-    USBx_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (usb_dc_cfg.out_ep[ep_idx].ep_mps));
-
-    if (usb_dc_cfg.out_ep[ep_idx].ep_type == EP_TYPE_ISOC) {
-        if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) {
-            USBx_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
-        } else {
-            USBx_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
-        }
-    }
-    /* EP enable */
-    USBx_OUTEP(ep_idx)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
-
-#endif
-    if (read_bytes) {
-        *read_bytes = read_count;
-    }
-
-    return 0;
-}
-
-/**
-  * @brief  This function handles PCD interrupt request.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-void USBD_IRQHandler(void)
-{
-    PCD_TypeDef *USBx = usb_dc_cfg.Instance;
-#ifdef USB
-    uint16_t wIstr, wEPVal;
-    uint8_t epindex;
-    wIstr = USBx->ISTR;
-
-    uint16_t store_ep[8];
-    if (wIstr & USB_ISTR_CTR) {
-        while ((USBx->ISTR & USB_ISTR_CTR) != 0U) {
-            wIstr = USBx->ISTR;
-
-            /* extract highest priority endpoint number */
-            epindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
-
-            if (epindex == 0U) {
-                /* Decode and service control endpoint interrupt */
-
-                /* DIR bit = origin of the interrupt */
-                if ((wIstr & USB_ISTR_DIR) == 0U) {
-                    /* DIR = 0 */
-
-                    /* DIR = 0 => IN  int */
-                    /* DIR = 0 implies that (EP_CTR_TX = 1) always */
-                    PCD_CLEAR_TX_EP_CTR(USBx, PCD_ENDP0);
-                    usbd_event_notify_handler(USBD_EVENT_EP0_IN_NOTIFY, NULL);
-                    if ((usb_dc_cfg.USB_Address > 0U) && (PCD_GET_EP_TX_CNT(USBx, PCD_ENDP0) == 0U)) {
-                        USBx->DADDR = ((uint16_t)usb_dc_cfg.USB_Address | USB_DADDR_EF);
-                        usb_dc_cfg.USB_Address = 0U;
-                    }
-                }
-                /* DIR = 1 */
-
-                /* DIR = 1 & CTR_RX => SETUP or OUT int */
-                /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
-
-                wEPVal = PCD_GET_ENDPOINT(USBx, PCD_ENDP0);
-
-                if ((wEPVal & USB_EP_SETUP) != 0U) {
-                    /* SETUP bit kept frozen while CTR_RX = 1 */
-                    PCD_CLEAR_RX_EP_CTR(USBx, PCD_ENDP0);
-
-                    /* Process SETUP Packet*/
-                    usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
-                    PCD_SET_EP_RX_STATUS(USBx, 0, USB_EP_RX_VALID);
-                } else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
-                    PCD_CLEAR_RX_EP_CTR(USBx, PCD_ENDP0);
-                    /* Process Control Data OUT Packet */
-                    usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
-                    PCD_SET_EP_RX_STATUS(USBx, 0, USB_EP_RX_VALID);
-                }
-            } else {
-                /* Decode and service non control endpoints interrupt */
-                /* process related endpoint register */
-                wEPVal = PCD_GET_ENDPOINT(USBx, epindex);
-
-                if ((wEPVal & USB_EP_CTR_RX) != 0U) {
-                    /* clear int flag */
-                    PCD_CLEAR_RX_EP_CTR(USBx, epindex);
-                    usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(epindex & 0x7f));
-                }
-
-                if ((wEPVal & USB_EP_CTR_TX) != 0U) {
-                    /* clear int flag */
-                    PCD_CLEAR_TX_EP_CTR(USBx, epindex);
-                    usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(epindex | 0x80));
-                }
-            }
-        }
-    }
-    if (wIstr & USB_ISTR_RESET) {
-        usbd_event_notify_handler(USBD_EVENT_RESET, NULL);
-
-        USBx->ISTR &= (uint16_t)(~USB_ISTR_RESET);
-    }
-    if (wIstr & USB_ISTR_PMAOVR) {
-        USBx->ISTR &= (uint16_t)(~USB_ISTR_PMAOVR);
-    }
-    if (wIstr & USB_ISTR_ERR) {
-        USBx->ISTR &= (uint16_t)(~USB_ISTR_ERR);
-    }
-    if (wIstr & USB_ISTR_WKUP) {
-        USBx->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
-        USBx->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
-
-        USBx->ISTR &= (uint16_t)(~USB_ISTR_WKUP);
-    }
-    if (wIstr & USB_ISTR_SUSP) {
-        /* WA: To Clear Wakeup flag if raised with suspend signal */
-
-        /* Store Endpoint register */
-        for (uint8_t i = 0U; i < 8U; i++) {
-            store_ep[i] = PCD_GET_ENDPOINT(USBx, i);
-        }
-
-        /* FORCE RESET */
-        USBx->CNTR |= (uint16_t)(USB_CNTR_FRES);
-
-        /* CLEAR RESET */
-        USBx->CNTR &= (uint16_t)(~USB_CNTR_FRES);
-
-        /* wait for reset flag in ISTR */
-        while ((USBx->ISTR & USB_ISTR_RESET) == 0U) {
-        }
-
-        /* Clear Reset Flag */
-        USBx->ISTR &= (uint16_t)(~USB_ISTR_RESET);
-        /* Restore Registre */
-        for (uint8_t i = 0U; i < 8U; i++) {
-            PCD_SET_ENDPOINT(USBx, i, store_ep[i]);
-        }
-
-        /* Force low-power mode in the macrocell */
-        USBx->CNTR |= (uint16_t)USB_CNTR_FSUSP;
-
-        /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
-        USBx->ISTR &= (uint16_t)(~USB_ISTR_SUSP);
-
-        USBx->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
-    }
-    if (wIstr & USB_ISTR_SOF) {
-        USBx->ISTR &= (uint16_t)(~USB_ISTR_SOF);
-    }
-    if (wIstr & USB_ISTR_ESOF) {
-        USBx->ISTR &= (uint16_t)(~USB_ISTR_ESOF);
-    }
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-    uint32_t USBx_BASE = (uint32_t)USBx;
-    uint32_t int_status;
-    uint32_t temp, epindex, ep_intr, ep_int_status;
-    /* ensure that we are in device mode */
-    if (USB_GetMode(USBx) == USB_OTG_MODE_DEVICE) {
-        while (int_status == USB_ReadInterrupts(USBx)) {
-            if (int_status & USB_OTG_GINTSTS_USBRST) {
-                usbd_event_notify_handler(USBD_EVENT_RESET, NULL);
-                USBx->GINTSTS &= USB_OTG_GINTSTS_USBRST;
-            }
-            if (int_status & USB_OTG_GINTSTS_ENUMDNE) {
-                USBx->GINTSTS &= USB_OTG_GINTSTS_ENUMDNE;
-            }
-            if (int_status & USB_OTG_GINTSTS_RXFLVL) {
-                USB_MASK_INTERRUPT(USBx, USB_OTG_GINTSTS_RXFLVL);
-                temp = USBx->GRXSTSP;
-                epindex = temp & USB_OTG_GRXSTSP_EPNUM;
-                if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) {
-                    if (epindex == 0)
-                        usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
-                    else {
-                        usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(epindex & 0x7f));
-                    }
-                } else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) {
-                    usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
-                } else {
-                    /* ... */
-                }
-                USB_UNMASK_INTERRUPT(USBx, USB_OTG_GINTSTS_RXFLVL);
-            }
-            if (int_status & USB_OTG_GINTSTS_IEPINT) {
-                epindex = 0U;
-                /* Read in the device interrupt bits */
-                ep_intr = USB_ReadDevAllInEpInterrupt(USBx);
-
-                while (ep_intr != 0U) {
-                    if ((ep_intr & 0x1U) != 0U) {
-                        /* Read IN EP interrupt status */
-                        ep_int_status = USB_ReadDevInEPInterrupt(USBx, (uint8_t)epindex);
-                        /* Clear IN EP interrupts */
-                        CLEAR_IN_EP_INTR(epindex, ep_int_status);
-                        if (ep_int_status & USB_OTG_DIEPINT_XFRC) {
-                            usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(epindex | 0x80));
-                        }
-                    }
-                    epindex++;
-                    ep_intr >>= 1U;
-                }
-            }
-            if (int_status & USB_OTG_GINTSTS_OEPINT) {
-                epindex = 0;
-                /* Read in the device interrupt bits */
-                ep_intr = USB_ReadDevAllOutEpInterrupt(USBx);
-
-                while (ep_intr != 0U) {
-                    if ((ep_intr & 0x1U) != 0U) {
-                        /* Read OUT EP interrupt status */
-                        ep_int_status = USB_ReadDevOutEPInterrupt(USBx, (uint8_t)epindex);
-                        /* Clear OUT EP interrupts */
-                        CLEAR_OUT_EP_INTR(epindex, ep_int_status);
-                    }
-                    epindex++;
-                    ep_intr >>= 1U;
-                }
-            }
-            if (int_status & USB_OTG_GINTSTS_MMIS) {
-                USBx->GINTSTS &= USB_OTG_GINTSTS_MMIS;
-            }
-            if (int_status & USB_OTG_GINTSTS_WKUINT) {
-                USBx->GINTSTS &= USB_OTG_GINTSTS_WKUINT;
-            }
-            if (int_status & USB_OTG_GINTSTS_USBSUSP) {
-                USBx->GINTSTS &= USB_OTG_GINTSTS_USBSUSP;
-            }
-            //            if (int_status & USB_OTG_GINTSTS_LPMINT) {
-            //                USBx->GINTSTS &= USB_OTG_GINTSTS_LPMINT;
-            //            }
-            if (int_status & USB_OTG_GINTSTS_SOF) {
-                USBx->GINTSTS &= USB_OTG_GINTSTS_SOF;
-            }
-            if (int_status & USB_OTG_GINTSTS_SRQINT) {
-                USBx->GINTSTS &= USB_OTG_GINTSTS_SRQINT;
-            }
-            if (int_status & USB_OTG_GINTSTS_OTGINT) {
-                USBx->GINTSTS &= USB_OTG_GINTSTS_OTGINT;
-            }
-        }
-    }
-#endif
-}

port/stm32/usbd_config.h

@@ -1,29 +0,0 @@
-#ifndef __USBD_CONFIG_H__
-#define __USBD_CONFIG_H__
-
-#if defined(STM32F0)
-#include "stm32f0xx.h"
-#elif defined(STM32F1)
-#include "stm32f1xx.h"
-#elif STM32F3
-#include "stm32f3xx.h"
-#elif defined(STM32F4)
-#include "stm32f4xx.h"
-#elif defined(STM32H7)
-#include "stm32h7xx.h"
-#endif
-
-/*other do not process，users need to modify byself*/
-#if defined(STM32F0)
-#define USBD_IRQHandler USB_IRQHandler
-#elif defined(STM32F1) || defined(STM32F3)
-#define USBD_IRQHandler USB_LP_CAN1_RX0_IRQHandler
-#else
-#ifdef CONFIG_USB_HS
-#define USBD_IRQHandler OTG_HS_IRQHandler
-#else
-#define USBD_IRQHandler OTG_FS_IRQHandler
-#endif
-#endif
-
-#endif