add ch32 dcd porting and ch32v307 cdc demo

.gitignore

@@ -10,4 +10,5 @@ demo/mm32/**/obj/**
 demo/mm32/**/RET/**
 demo/mm32/**/*.map
 demo/mm32/**/*.lst
-demo/mm32/**/*.uvguix.*
+demo/mm32/**/*.uvguix.*
+demo/ch32/**/**/**/**/**/obj/**

demo/ch32/ch32v307/SRC/Core/core_riscv.c

@@ -0,0 +1,539 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : core_riscv.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : RISC-V Core Peripheral Access Layer Source File
+*******************************************************************************/
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/*********************************************************************
+ * @fn      __get_FFLAGS
+ *
+ * @brief   Return the Floating-Point Accrued Exceptions
+ *
+ * @return  fflags value
+ */
+uint32_t __get_FFLAGS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "fflags" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_FFLAGS
+ *
+ * @brief   Set the Floating-Point Accrued Exceptions
+ *
+ * @param   value  - set FFLAGS value
+ *
+ * @return  none
+ */
+void __set_FFLAGS(uint32_t value)
+{
+  __ASM volatile ("csrw fflags, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_FRM
+ *
+ * @brief   Return the Floating-Point Dynamic Rounding Mode
+ *
+ * @return  frm value
+ */
+uint32_t __get_FRM(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "frm" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_FRM
+ *
+ * @brief   Set the Floating-Point Dynamic Rounding Mode
+ *
+ * @param   value  - set frm value
+ *
+ * @return  none
+ */
+void __set_FRM(uint32_t value)
+{
+  __ASM volatile ("csrw frm, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_FCSR
+ *
+ * @brief   Return the Floating-Point Control and Status Register
+ *
+ * @return  fcsr value
+ */
+uint32_t __get_FCSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "fcsr" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_FCSR
+ *
+ * @brief   Set the Floating-Point Dynamic Rounding Mode
+ *
+ * @param   value  - set fcsr value
+ *
+ * @return  none
+ */
+void __set_FCSR(uint32_t value)
+{
+  __ASM volatile ("csrw fcsr, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MSTATUS
+ *
+ * @brief   Return the Machine Status Register
+ *
+ * @return  mstatus value
+ */
+uint32_t __get_MSTATUS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MSTATUS
+ *
+ * @brief   Set the Machine Status Register
+ *
+ * @param   value  - set mstatus value
+ *
+ * @return  none
+ */
+void __set_MSTATUS(uint32_t value)
+{
+  __ASM volatile ("csrw mstatus, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MISA
+ *
+ * @brief   Return the Machine ISA Register
+ *
+ * @return  misa value
+ */
+uint32_t __get_MISA(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "misa" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MISA
+ *
+ * @brief   Set the Machine ISA Register
+ *
+ * @param   value  - set misa value
+ *
+ * @return  none
+ */
+void __set_MISA(uint32_t value)
+{
+  __ASM volatile ("csrw misa, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MIE
+ *
+ * @brief   Return the Machine Interrupt Enable Register
+ *
+ * @return  mie value
+ */
+uint32_t __get_MIE(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mie" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MISA
+ *
+ * @brief   Set the Machine ISA Register
+ *
+ * @param   value  - set mie value
+ *
+ * @return  none
+ */
+void __set_MIE(uint32_t value)
+{
+  __ASM volatile ("csrw mie, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MTVEC
+ *
+ * @brief   Return the Machine Trap-Vector Base-Address Register
+ *
+ * @return  mtvec value
+ */
+uint32_t __get_MTVEC(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MTVEC
+ *
+ * @brief   Set the Machine Trap-Vector Base-Address Register
+ *
+ * @param   value  - set mtvec value
+ *
+ * @return  none
+ */
+void __set_MTVEC(uint32_t value)
+{
+  __ASM volatile ("csrw mtvec, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MTVEC
+ *
+ * @brief   Return the Machine Seratch Register
+ *
+ * @return  mscratch value
+ */
+uint32_t __get_MSCRATCH(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MTVEC
+ *
+ * @brief   Set the Machine Seratch Register
+ *
+ * @param   value  - set mscratch value
+ *
+ * @return  none
+ */
+void __set_MSCRATCH(uint32_t value)
+{
+  __ASM volatile ("csrw mscratch, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MEPC
+ *
+ * @brief   Return the Machine Exception Program Register
+ *
+ * @return  mepc value
+ */
+uint32_t __get_MEPC(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mepc" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MEPC
+ *
+ * @brief   Set the Machine Exception Program Register
+ *
+ * @return  mepc value
+ */
+void __set_MEPC(uint32_t value)
+{
+  __ASM volatile ("csrw mepc, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MCAUSE
+ *
+ * @brief   Return the Machine Cause Register
+ *
+ * @return  mcause value
+ */
+uint32_t __get_MCAUSE(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mcause" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MEPC
+ *
+ * @brief   Set the Machine Cause Register
+ *
+ * @return  mcause value
+ */
+void __set_MCAUSE(uint32_t value)
+{
+  __ASM volatile ("csrw mcause, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MTVAL
+ *
+ * @brief   Return the Machine Trap Value Register
+ *
+ * @return  mtval value
+ */
+uint32_t __get_MTVAL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mtval" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MTVAL
+ *
+ * @brief   Set the Machine Trap Value Register
+ *
+ * @return  mtval value
+ */
+void __set_MTVAL(uint32_t value)
+{
+  __ASM volatile ("csrw mtval, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MIP
+ *
+ * @brief   Return the Machine Interrupt Pending Register
+ *
+ * @return  mip value
+ */
+uint32_t __get_MIP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mip" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MIP
+ *
+ * @brief   Set the Machine Interrupt Pending Register
+ *
+ * @return  mip value
+ */
+void __set_MIP(uint32_t value)
+{
+  __ASM volatile ("csrw mip, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MCYCLE
+ *
+ * @brief   Return Lower 32 bits of Cycle counter
+ *
+ * @return  mcycle value
+ */
+uint32_t __get_MCYCLE(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mcycle" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MCYCLE
+ *
+ * @brief   Set Lower 32 bits of Cycle counter
+ *
+ * @return  mcycle value
+ */
+void __set_MCYCLE(uint32_t value)
+{
+  __ASM volatile ("csrw mcycle, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MCYCLEH
+ *
+ * @brief   Return Upper 32 bits of Cycle counter
+ *
+ * @return  mcycleh value
+ */
+uint32_t __get_MCYCLEH(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mcycleh" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MCYCLEH
+ *
+ * @brief   Set Upper 32 bits of Cycle counter
+ *
+ * @return  mcycleh value
+ */
+void __set_MCYCLEH(uint32_t value)
+{
+  __ASM volatile ("csrw mcycleh, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MINSTRET
+ *
+ * @brief   Return Lower 32 bits of Instructions-retired counter
+ *
+ * @return  mcause value
+ */
+uint32_t __get_MINSTRET(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "minstret" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MINSTRET
+ *
+ * @brief   Set Lower 32 bits of Instructions-retired counter
+ *
+ * @return  minstret value
+ */
+void __set_MINSTRET(uint32_t value)
+{
+  __ASM volatile ("csrw minstret, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MINSTRETH
+ *
+ * @brief   Return Upper 32 bits of Instructions-retired counter
+ *
+ * @return  minstreth value
+ */
+uint32_t __get_MINSTRETH(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "minstreth" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MINSTRETH
+ *
+ * @brief   Set Upper 32 bits of Instructions-retired counter
+ *
+ * @return  minstreth value
+ */
+void __set_MINSTRETH(uint32_t value)
+{
+  __ASM volatile ("csrw minstreth, %0" : : "r" (value) );
+}
+
+/*********************************************************************
+ * @fn      __get_MVENDORID
+ *
+ * @brief   Return Vendor ID Register
+ *
+ * @return  mvendorid value
+ */
+uint32_t __get_MVENDORID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MARCHID
+ *
+ * @brief   Return Machine Architecture ID Register
+ *
+ * @return  marchid value
+ */
+uint32_t __get_MARCHID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "marchid" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MIMPID
+ *
+ * @brief   Return Machine Implementation ID Register
+ *
+ * @return  mimpid value
+ */
+uint32_t __get_MIMPID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) );
+  return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MHARTID
+ *
+ * @brief   Return Hart ID Register
+ *
+ * @return  mhartid value
+ */
+uint32_t __get_MHARTID(void)
+{
+  uint32_t result;
+
+  __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) );
+  return (result);
+}
+
+
+

demo/ch32/ch32v307/SRC/Core/core_riscv.h

@@ -0,0 +1,381 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : core_riscv.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : RISC-V Core Peripheral Access Layer Header File for CH32V30x
+*******************************************************************************/
+#ifndef __CORE_RISCV_H__
+#define __CORE_RISCV_H__
+
+/* IO definitions */
+#ifdef __cplusplus
+  #define     __I     volatile                /* defines 'read only' permissions */
+#else
+  #define     __I     volatile const          /* defines 'read only' permissions */
+#endif
+#define     __O     volatile                  /* defines 'write only' permissions */
+#define     __IO    volatile                  /* defines 'read / write' permissions */
+
+/* Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef __I uint64_t vuc64;  /* Read Only */
+typedef __I uint32_t vuc32;  /* Read Only */
+typedef __I uint16_t vuc16;  /* Read Only */
+typedef __I uint8_t vuc8;   /* Read Only */
+
+typedef const uint64_t uc64;  /* Read Only */
+typedef const uint32_t uc32;  /* Read Only */
+typedef const uint16_t uc16;  /* Read Only */
+typedef const uint8_t uc8;   /* Read Only */
+
+typedef __I int64_t vsc64;  /* Read Only */
+typedef __I int32_t vsc32;  /* Read Only */
+typedef __I int16_t vsc16;  /* Read Only */
+typedef __I int8_t vsc8;   /* Read Only */
+
+typedef const int64_t sc64;  /* Read Only */
+typedef const int32_t sc32;  /* Read Only */
+typedef const int16_t sc16;  /* Read Only */
+typedef const int8_t sc8;   /* Read Only */
+
+typedef __IO uint64_t  vu64;
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef uint64_t  u64;
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef __IO int64_t  vs64;
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef int64_t  s64;
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+#define   RV_STATIC_INLINE  static  inline
+
+/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
+typedef struct{
+  __I  uint32_t ISR[8];
+  __I  uint32_t IPR[8];
+  __IO uint32_t ITHRESDR;
+  __IO uint32_t RESERVED;
+  __IO uint32_t CFGR;
+  __I  uint32_t GISR;
+  uint8_t VTFIDR[4];
+  uint8_t RESERVED0[12];
+  __IO uint32_t VTFADDR[4];
+  uint8_t RESERVED1[0x90];
+  __O  uint32_t IENR[8];
+  uint8_t RESERVED2[0x60];
+  __O  uint32_t IRER[8];
+  uint8_t RESERVED3[0x60];
+  __O  uint32_t IPSR[8];
+  uint8_t RESERVED4[0x60];
+  __O  uint32_t IPRR[8];
+  uint8_t RESERVED5[0x60];
+  __IO uint32_t IACTR[8];
+  uint8_t RESERVED6[0xE0];
+  __IO uint8_t IPRIOR[256];
+  uint8_t RESERVED7[0x810];
+  __IO uint32_t SCTLR;
+}PFIC_Type;
+
+/* memory mapped structure for SysTick */
+typedef struct
+{
+    __IO u32 CTLR;
+    __IO u32 SR;
+    __IO u64 CNT;
+    __IO u64 CMP;
+}SysTick_Type;
+
+
+#define PFIC            ((PFIC_Type *) 0xE000E000 )
+#define NVIC            PFIC
+#define NVIC_KEY1       ((uint32_t)0xFA050000)
+#define	NVIC_KEY2				((uint32_t)0xBCAF0000)
+#define	NVIC_KEY3				((uint32_t)0xBEEF0000)
+
+#define SysTick         ((SysTick_Type *) 0xE000F000)
+
+/*********************************************************************
+ * @fn      __enable_irq
+ *
+ * @brief   Enable Global Interrupt
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void __enable_irq()
+{
+  __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) );
+}
+
+/*********************************************************************
+ * @fn      __disable_irq
+ *
+ * @brief   Disable Global Interrupt
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void __disable_irq()
+{
+  __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) );
+}
+
+/*********************************************************************
+ * @fn      __NOP
+ *
+ * @brief   nop
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void __NOP()
+{
+  __asm volatile ("nop");
+}
+
+/*********************************************************************
+ * @fn      NVIC_EnableIRQ
+ *
+ * @brief   Enable Interrupt
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_DisableIRQ
+ *
+ * @brief   Disable Interrupt
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetStatusIRQ
+ *
+ * @brief   Get Interrupt Enable State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Enable
+ *          0 - Interrupt Disable
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetPendingIRQ
+ *
+ * @brief   Get Interrupt Pending State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Pending Enable
+ *          0 - Interrupt Pending Disable
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_SetPendingIRQ
+ *
+ * @brief   Set Interrupt Pending
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_ClearPendingIRQ
+ *
+ * @brief   Clear Interrupt Pending
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetActive
+ *
+ * @brief   Get Interrupt Active State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Active
+ *          0 - Interrupt No Active
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_SetPriority
+ *
+ * @brief   Set Interrupt Priority
+ *
+ * @param   IRQn - Interrupt Numbers
+ *          priority -
+ *              bit7 - pre-emption priority
+ *              bit6~bit4 - subpriority
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
+{
+  NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
+}
+
+/*********************************************************************
+ * @fn      __WFI
+ *
+ * @brief   Wait for Interrupt
+ *
+ * @return  None
+ */
+__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
+{
+  NVIC->SCTLR &= ~(1<<3);	// wfi
+  asm volatile ("wfi");
+}
+
+/*********************************************************************
+ * @fn      __WFE
+ *
+ * @brief   Wait for Events
+ *
+ * @return  None
+ */
+__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
+{
+  uint32_t t;
+
+  t = NVIC->SCTLR;
+  NVIC->SCTLR |= (1<<3)|(1<<5);		// (wfi->wfe)+(__sev)
+  NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
+  asm volatile ("wfi");
+  asm volatile ("wfi");
+}
+
+/*********************************************************************
+ * @fn      SetVTFIRQ
+ *
+ * @brief   Set VTF Interrupt
+ *
+ * @param   add - VTF interrupt service function base address.
+ *          IRQn -Interrupt Numbers
+ *          num - VTF Interrupt Numbers
+ *          NewState - DISABLE or ENABLE
+ * @return  None
+ */
+RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
+  if(num > 3)  return ;
+
+  if (NewState != DISABLE)
+  {
+      NVIC->VTFIDR[num] = IRQn;
+      NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
+  }
+  else{
+      NVIC->VTFIDR[num] = IRQn;
+      NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
+  }
+}
+
+/*********************************************************************
+ * @fn      NVIC_SystemReset
+ *
+ * @brief   Initiate a system reset request
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SystemReset(void)
+{
+  NVIC->CFGR = NVIC_KEY3|(1<<7);
+}
+
+
+/* Core_Exported_Functions */  
+extern uint32_t __get_FFLAGS(void);
+extern void __set_FFLAGS(uint32_t value);
+extern uint32_t __get_FRM(void);
+extern void __set_FRM(uint32_t value);
+extern uint32_t __get_FCSR(void);
+extern void __set_FCSR(uint32_t value);
+extern uint32_t __get_MSTATUS(void);
+extern void __set_MSTATUS(uint32_t value);
+extern uint32_t __get_MISA(void);
+extern void __set_MISA(uint32_t value);
+extern uint32_t __get_MIE(void);
+extern void __set_MIE(uint32_t value);
+extern uint32_t __get_MTVEC(void);
+extern void __set_MTVEC(uint32_t value);
+extern uint32_t __get_MSCRATCH(void);
+extern void __set_MSCRATCH(uint32_t value);
+extern uint32_t __get_MEPC(void);
+extern void __set_MEPC(uint32_t value);
+extern uint32_t __get_MCAUSE(void);
+extern void __set_MCAUSE(uint32_t value);
+extern uint32_t __get_MTVAL(void);
+extern void __set_MTVAL(uint32_t value);
+extern uint32_t __get_MIP(void);
+extern void __set_MIP(uint32_t value);
+extern uint32_t __get_MCYCLE(void);
+extern void __set_MCYCLE(uint32_t value);
+extern uint32_t __get_MCYCLEH(void);
+extern void __set_MCYCLEH(uint32_t value);
+extern uint32_t __get_MINSTRET(void);
+extern void __set_MINSTRET(uint32_t value);
+extern uint32_t __get_MINSTRETH(void);
+extern void __set_MINSTRETH(uint32_t value);
+extern uint32_t __get_MVENDORID(void);
+extern uint32_t __get_MARCHID(void);
+extern uint32_t __get_MIMPID(void);
+extern uint32_t __get_MHARTID(void);
+
+
+
+#endif
+
+
+
+
+

demo/ch32/ch32v307/SRC/Debug/debug.c

@@ -0,0 +1,170 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : debug.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for UART
+*                      Printf , Delay functions.
+*******************************************************************************/
+#include "debug.h"
+
+static uint8_t  p_us=0;
+static uint16_t p_ms=0;
+
+/*********************************************************************
+ * @fn      Delay_Init
+ *
+ * @brief   Initializes Delay Funcation.
+ *
+ * @return  none
+ */
+void Delay_Init(void)
+{
+	p_us=SystemCoreClock/8000000;
+	p_ms=(uint16_t)p_us*1000;
+}
+
+/*********************************************************************
+ * @fn      Delay_Us
+ *
+ * @brief   Microsecond Delay Time.
+ *
+ * @param   n - Microsecond number.
+ *
+ * @return  None
+ */
+void Delay_Us(uint32_t n)
+{
+    uint32_t i;
+
+    SysTick->CTLR = (1<<4);
+    i = (uint32_t)n*p_us;
+
+    SysTick->CMP = i;
+    SysTick->CTLR |= (1<<5)|(1<<0);
+
+    while((SysTick->SR & (1<<0)) != (1<<0));
+    SysTick->SR &= ~(1<<0);
+}
+
+/*********************************************************************
+ * @fn      Delay_Ms
+ *
+ * @brief   Millisecond Delay Time.
+ *
+ * @param   n - Millisecond number.
+ *
+ * @return  None
+ */
+void Delay_Ms(uint32_t n)
+{
+    uint32_t i;
+
+    SysTick->CTLR = (1<<4);
+    i = (uint32_t)n*p_ms;
+
+    SysTick->CMP = i;
+    SysTick->CTLR |= (1<<5)|(1<<0);
+
+    while((SysTick->SR & (1<<0)) != (1<<0));
+    SysTick->SR &= ~(1<<0);
+}
+
+/*********************************************************************
+ * @fn      USART_Printf_Init
+ *
+ * @brief   Initializes the USARTx peripheral.
+ *
+ * @param   baudrate - USART communication baud rate.
+ *
+ * @return  None
+ */
+void USART_Printf_Init(uint32_t baudrate)
+{
+  GPIO_InitTypeDef GPIO_InitStructure;
+  USART_InitTypeDef USART_InitStructure;
+
+#if (DEBUG == DEBUG_UART1)
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1|RCC_APB2Periph_GPIOA, ENABLE);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+#elif (DEBUG == DEBUG_UART2)
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+#elif (DEBUG == DEBUG_UART3)
+  RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
+  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
+
+  GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+  GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+  GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+  GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+#endif
+
+  USART_InitStructure.USART_BaudRate = baudrate;
+  USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+  USART_InitStructure.USART_StopBits = USART_StopBits_1;
+  USART_InitStructure.USART_Parity = USART_Parity_No;
+  USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+  USART_InitStructure.USART_Mode = USART_Mode_Tx;
+
+#if (DEBUG == DEBUG_UART1)
+  USART_Init(USART1, &USART_InitStructure);
+  USART_Cmd(USART1, ENABLE);
+
+#elif (DEBUG == DEBUG_UART2)
+  USART_Init(USART2, &USART_InitStructure);
+  USART_Cmd(USART2, ENABLE);
+
+#elif (DEBUG == DEBUG_UART3)
+  USART_Init(USART3, &USART_InitStructure);
+  USART_Cmd(USART3, ENABLE);
+
+#endif
+}
+
+/*********************************************************************
+ * @fn      _write
+ *
+ * @brief   Support Printf Function
+ *
+ * @param   *buf - UART send Data.
+ *          size - Data length
+ *
+ * @return  size: Data length
+ */
+int _write(int fd, char *buf, int size)
+{
+  int i;
+
+  for(i=0; i<size; i++)
+  {
+#if (DEBUG == DEBUG_UART1)
+    while (USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
+    USART_SendData(USART1, *buf++);
+#elif (DEBUG == DEBUG_UART2)
+    while (USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET);
+    USART_SendData(USART2, *buf++);
+#elif (DEBUG == DEBUG_UART3)
+    while (USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET);
+    USART_SendData(USART3, *buf++);
+#endif
+  }
+
+  return size;
+}
+
+
+
+

demo/ch32/ch32v307/SRC/Debug/debug.h

@@ -0,0 +1,34 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : debug.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for UART
+*                      Printf , Delay functions.
+*******************************************************************************/
+#ifndef __DEBUG_H
+#define __DEBUG_H
+
+#include "stdio.h"
+#include "ch32v30x.h"
+
+/* UART Printf Definition */
+#define DEBUG_UART1    1
+#define DEBUG_UART2    2
+#define DEBUG_UART3    3
+
+/* DEBUG UATR Definition */
+#define DEBUG   DEBUG_UART1
+//#define DEBUG   DEBUG_UART2
+//#define DEBUG   DEBUG_UART3
+
+
+void Delay_Init(void);
+void Delay_Us (uint32_t n);
+void Delay_Ms (uint32_t n);
+void USART_Printf_Init(uint32_t baudrate);
+
+#endif 
+
+
+

demo/ch32/ch32v307/SRC/Peripheral/inc/ch32v30x.h

@@ -0,0 +1,5202 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x Device Peripheral Access Layer Header File.
+*******************************************************************************/   
+#ifndef __CH32V30x_H
+#define __CH32V30x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+  
+#define __MPU_PRESENT             0 /* Other CH32 devices does not provide an MPU */
+#define __Vendor_SysTickConfig    0 /* Set to 1 if different SysTick Config is used */	 
+	 
+#define HSE_VALUE    ((uint32_t)8000000) /* Value of the External oscillator in Hz */
+
+/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */
+#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x500) /* Time out for HSE start up */
+
+#define HSI_VALUE    ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */
+
+/* Interrupt Number Definition, according to the selected device */	 
+typedef enum IRQn
+{
+ /******  RISC-V Processor Exceptions Numbers *******************************************************/
+  NonMaskableInt_IRQn         = 2,       /* 2 Non Maskable Interrupt                             */
+  EXC_IRQn                    = 3,       /* 3 Exception Interrupt                                */
+  Ecall_M_Mode_IRQn           = 5,       /* 5 Ecall M Mode Interrupt                             */
+  Ecall_U_Mode_IRQn           = 8,       /* 8 Ecall U Mode Interrupt                             */
+  Break_Point_IRQn            = 9,       /* 9 Break Point Interrupt                              */
+  SysTicK_IRQn                = 12,      /* 12 System timer Interrupt                            */
+  Software_IRQn               = 14,      /* 14 software Interrupt                                */
+
+ /******  RISC-V specific Interrupt Numbers *********************************************************/
+  WWDG_IRQn                   = 16,      /* Window WatchDog Interrupt                            */
+  PVD_IRQn                    = 17,      /* PVD through EXTI Line detection Interrupt            */
+  TAMPER_IRQn                 = 18,      /* Tamper Interrupt                                     */
+  RTC_IRQn                    = 19,      /* RTC global Interrupt                                 */
+  FLASH_IRQn                  = 20,      /* FLASH global Interrupt                               */
+  RCC_IRQn                    = 21,      /* RCC global Interrupt                                 */
+  EXTI0_IRQn                  = 22,      /* EXTI Line0 Interrupt                                 */
+  EXTI1_IRQn                  = 23,      /* EXTI Line1 Interrupt                                 */
+  EXTI2_IRQn                  = 24,      /* EXTI Line2 Interrupt                                 */
+  EXTI3_IRQn                  = 25,      /* EXTI Line3 Interrupt                                 */
+  EXTI4_IRQn                  = 26,      /* EXTI Line4 Interrupt                                 */
+  DMA1_Channel1_IRQn          = 27,      /* DMA1 Channel 1 global Interrupt                      */
+  DMA1_Channel2_IRQn          = 28,      /* DMA1 Channel 2 global Interrupt                      */
+  DMA1_Channel3_IRQn          = 29,      /* DMA1 Channel 3 global Interrupt                      */
+  DMA1_Channel4_IRQn          = 30,      /* DMA1 Channel 4 global Interrupt                      */
+  DMA1_Channel5_IRQn          = 31,      /* DMA1 Channel 5 global Interrupt                      */
+  DMA1_Channel6_IRQn          = 32,      /* DMA1 Channel 6 global Interrupt                      */
+  DMA1_Channel7_IRQn          = 33,      /* DMA1 Channel 7 global Interrupt                      */
+  ADC_IRQn                    = 34,      /* ADC1 and ADC2 global Interrupt                       */
+  USB_HP_CAN1_TX_IRQn         = 35,      /* USB Device High Priority or CAN1 TX Interrupts       */
+  USB_LP_CAN1_RX0_IRQn        = 36,      /* USB Device Low Priority or CAN1 RX0 Interrupts       */
+  CAN1_RX1_IRQn               = 37,      /* CAN1 RX1 Interrupt                                   */
+  CAN1_SCE_IRQn               = 38,      /* CAN1 SCE Interrupt                                   */
+  EXTI9_5_IRQn                = 39,      /* External Line[9:5] Interrupts                        */
+  TIM1_BRK_IRQn               = 40,      /* TIM1 Break Interrupt                                 */
+  TIM1_UP_IRQn                = 41,      /* TIM1 Update Interrupt                                */
+  TIM1_TRG_COM_IRQn           = 42,      /* TIM1 Trigger and Commutation Interrupt               */
+  TIM1_CC_IRQn                = 43,      /* TIM1 Capture Compare Interrupt                       */
+  TIM2_IRQn                   = 44,      /* TIM2 global Interrupt                                */
+  TIM3_IRQn                   = 45,      /* TIM3 global Interrupt                                */
+  TIM4_IRQn                   = 46,      /* TIM4 global Interrupt                                */
+  I2C1_EV_IRQn                = 47,      /* I2C1 Event Interrupt                                 */
+  I2C1_ER_IRQn                = 48,      /* I2C1 Error Interrupt                                 */
+  I2C2_EV_IRQn                = 49,      /* I2C2 Event Interrupt                                 */
+  I2C2_ER_IRQn                = 50,      /* I2C2 Error Interrupt                                 */
+  SPI1_IRQn                   = 51,      /* SPI1 global Interrupt                                */
+  SPI2_IRQn                   = 52,      /* SPI2 global Interrupt                                */
+  USART1_IRQn                 = 53,      /* USART1 global Interrupt                              */
+  USART2_IRQn                 = 54,      /* USART2 global Interrupt                              */
+  USART3_IRQn                 = 55,      /* USART3 global Interrupt                              */
+  EXTI15_10_IRQn              = 56,      /* External Line[15:10] Interrupts                      */
+  RTCAlarm_IRQn               = 57,      /* RTC Alarm through EXTI Line Interrupt                */
+  USBWakeUp_IRQn              = 58,      /* USB Device WakeUp from suspend through EXTI Line Interrupt */
+  TIM8_BRK_IRQn               = 59,      /* TIM8 Break Interrupt                                 */
+  TIM8_UP_IRQn                = 60,      /* TIM8 Update Interrupt                                */
+  TIM8_TRG_COM_IRQn           = 61,      /* TIM8 Trigger and Commutation Interrupt               */
+  TIM8_CC_IRQn                = 62,      /* TIM8 Capture Compare Interrupt                       */
+  RNG_IRQn                    = 63,      /* RNG global Interrupt                                 */
+  FSMC_IRQn                   = 64,      /* FSMC global Interrupt                                */
+  SDIO_IRQn                   = 65,      /* SDIO global Interrupt                                */
+  TIM5_IRQn                   = 66,      /* TIM5 global Interrupt                                */
+  SPI3_IRQn                   = 67,      /* SPI3 global Interrupt                                */
+  UART4_IRQn                  = 68,      /* UART4 global Interrupt                               */
+  UART5_IRQn                  = 69,      /* UART5 global Interrupt                               */
+  TIM6_IRQn                   = 70,      /* TIM6 global Interrupt                                */
+  TIM7_IRQn                   = 71,      /* TIM7 global Interrupt                                */
+  DMA2_Channel1_IRQn          = 72,      /* DMA2 Channel 1 global Interrupt                      */
+  DMA2_Channel2_IRQn          = 73,      /* DMA2 Channel 2 global Interrupt                      */
+  DMA2_Channel3_IRQn          = 74,      /* DMA2 Channel 3 global Interrupt                      */
+  DMA2_Channel4_IRQn          = 75,      /* DMA2 Channel 4 global Interrupt                      */
+  DMA2_Channel5_IRQn          = 76,      /* DMA2 Channel 5 global Interrupt                      */
+  ETH_IRQn                    = 77,      /* ETH global Interrupt                                 */
+  ETH_WKUP_IRQn               = 78,      /* ETH WakeUp Interrupt                                 */
+  CAN2_TX_IRQn                = 79,      /* CAN2 TX Interrupts                                   */
+  CAN2_RX0_IRQn               = 80,      /* CAN2 RX0 Interrupts                                  */
+  CAN2_RX1_IRQn               = 81,      /* CAN2 RX1 Interrupt                                   */
+  CAN2_SCE_IRQn               = 82,      /* CAN2 SCE Interrupt                                   */
+  OTG_FS_IRQn                 = 83,      /* OTGFS global Interrupt                               */
+  USBHSWakeup_IRQn            = 84,      /* USBHS WakeUp Interrupt                               */
+  USBHS_IRQn                  = 85,      /* USBHS global Interrupt                               */
+  DVP_IRQn                    = 86,      /* DVP global Interrupt                                 */
+  UART6_IRQn                  = 87,      /* UART6 global Interrupt                               */
+  UART7_IRQn                  = 88,      /* UART7 global Interrupt                               */
+  UART8_IRQn                  = 89,      /* UART8 global Interrupt                               */
+  TIM9_BRK_IRQn               = 90,      /* TIM9 Break Interrupt                                 */
+  TIM9_UP_IRQn                = 91,      /* TIM9 Update Interrupt                                */
+  TIM9_TRG_COM_IRQn           = 92,      /* TIM9 Trigger and Commutation Interrupt               */
+  TIM9_CC_IRQn                = 93,      /* TIM9 Capture Compare Interrupt                       */
+  TIM10_BRK_IRQn              = 94,      /* TIM10 Break Interrupt                                */
+  TIM10_UP_IRQn               = 95,      /* TIM10 Update Interrupt                               */
+  TIM10_TRG_COM_IRQn          = 96,      /* TIM10 Trigger and Commutation Interrupt              */
+  TIM10_CC_IRQn               = 97,      /* TIM10 Capture Compare Interrupt                      */
+  DMA2_Channel6_IRQn          = 98,      /* DMA2 Channel 6 global Interrupt                      */
+  DMA2_Channel7_IRQn          = 99,      /* DMA2 Channel 7 global Interrupt                      */
+  DMA2_Channel8_IRQn          = 100,     /* DMA2 Channel 8 global Interrupt                      */
+  DMA2_Channel9_IRQn          = 101,     /* DMA2 Channel 9 global Interrupt                      */
+  DMA2_Channel10_IRQn         = 102,     /* DMA2 Channel 10 global Interrupt                     */
+  DMA2_Channel11_IRQn         = 103,     /* DMA2 Channel 11 global Interrupt                     */
+} IRQn_Type;
+
+#define HardFault_IRQn   EXC_IRQn
+#define ADC1_2_IRQn      ADC_IRQn
+
+
+#include <stdint.h>
+#include "core_riscv.h"
+#include "system_ch32v30x.h"
+
+
+/* Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSI_Value            HSI_VALUE 
+#define HSE_Value            HSE_VALUE
+#define HSEStartUp_TimeOut   HSE_STARTUP_TIMEOUT
+
+/* Analog to Digital Converter */
+typedef struct
+{
+  __IO uint32_t STATR;
+  __IO uint32_t CTLR1;
+  __IO uint32_t CTLR2;
+  __IO uint32_t SAMPTR1;
+  __IO uint32_t SAMPTR2;
+  __IO uint32_t IOFR1;
+  __IO uint32_t IOFR2;
+  __IO uint32_t IOFR3;
+  __IO uint32_t IOFR4;
+  __IO uint32_t WDHTR;
+  __IO uint32_t WDLTR;
+  __IO uint32_t RSQR1;
+  __IO uint32_t RSQR2;
+  __IO uint32_t RSQR3;
+  __IO uint32_t ISQR;
+  __IO uint32_t IDATAR1;
+  __IO uint32_t IDATAR2;
+  __IO uint32_t IDATAR3;
+  __IO uint32_t IDATAR4;
+  __IO uint32_t RDATAR;
+} ADC_TypeDef;
+
+/* Backup Registers */
+typedef struct
+{
+  uint32_t  RESERVED0;
+  __IO uint16_t DATAR1;
+  uint16_t  RESERVED1;
+  __IO uint16_t DATAR2;
+  uint16_t  RESERVED2;
+  __IO uint16_t DATAR3;
+  uint16_t  RESERVED3;
+  __IO uint16_t DATAR4;
+  uint16_t  RESERVED4;
+  __IO uint16_t DATAR5;
+  uint16_t  RESERVED5;
+  __IO uint16_t DATAR6;
+  uint16_t  RESERVED6;
+  __IO uint16_t DATAR7;
+  uint16_t  RESERVED7;
+  __IO uint16_t DATAR8;
+  uint16_t  RESERVED8;
+  __IO uint16_t DATAR9;
+  uint16_t  RESERVED9;
+  __IO uint16_t DATAR10;
+  uint16_t  RESERVED10; 
+  __IO uint16_t OCTLR;
+  uint16_t  RESERVED11;
+  __IO uint16_t TPCTLR;
+  uint16_t  RESERVED12;
+  __IO uint16_t TPCSR;
+  uint16_t  RESERVED13[5];
+  __IO uint16_t DATAR11;
+  uint16_t  RESERVED14;
+  __IO uint16_t DATAR12;
+  uint16_t  RESERVED15;
+  __IO uint16_t DATAR13;
+  uint16_t  RESERVED16;
+  __IO uint16_t DATAR14;
+  uint16_t  RESERVED17;
+  __IO uint16_t DATAR15;
+  uint16_t  RESERVED18;
+  __IO uint16_t DATAR16;
+  uint16_t  RESERVED19;
+  __IO uint16_t DATAR17;
+  uint16_t  RESERVED20;
+  __IO uint16_t DATAR18;
+  uint16_t  RESERVED21;
+  __IO uint16_t DATAR19;
+  uint16_t  RESERVED22;
+  __IO uint16_t DATAR20;
+  uint16_t  RESERVED23;
+  __IO uint16_t DATAR21;
+  uint16_t  RESERVED24;
+  __IO uint16_t DATAR22;
+  uint16_t  RESERVED25;
+  __IO uint16_t DATAR23;
+  uint16_t  RESERVED26;
+  __IO uint16_t DATAR24;
+  uint16_t  RESERVED27;
+  __IO uint16_t DATAR25;
+  uint16_t  RESERVED28;
+  __IO uint16_t DATAR26;
+  uint16_t  RESERVED29;
+  __IO uint16_t DATAR27;
+  uint16_t  RESERVED30;
+  __IO uint16_t DATAR28;
+  uint16_t  RESERVED31;
+  __IO uint16_t DATAR29;
+  uint16_t  RESERVED32;
+  __IO uint16_t DATAR30;
+  uint16_t  RESERVED33; 
+  __IO uint16_t DATAR31;
+  uint16_t  RESERVED34;
+  __IO uint16_t DATAR32;
+  uint16_t  RESERVED35;
+  __IO uint16_t DATAR33;
+  uint16_t  RESERVED36;
+  __IO uint16_t DATAR34;
+  uint16_t  RESERVED37;
+  __IO uint16_t DATAR35;
+  uint16_t  RESERVED38;
+  __IO uint16_t DATAR36;
+  uint16_t  RESERVED39;
+  __IO uint16_t DATAR37;
+  uint16_t  RESERVED40;
+  __IO uint16_t DATAR38;
+  uint16_t  RESERVED41;
+  __IO uint16_t DATAR39;
+  uint16_t  RESERVED42;
+  __IO uint16_t DATAR40;
+  uint16_t  RESERVED43;
+  __IO uint16_t DATAR41;
+  uint16_t  RESERVED44;
+  __IO uint16_t DATAR42;
+  uint16_t  RESERVED45;    
+} BKP_TypeDef;
+
+/* Controller Area Network TxMailBox */
+typedef struct
+{
+  __IO uint32_t TXMIR;
+  __IO uint32_t TXMDTR;
+  __IO uint32_t TXMDLR;
+  __IO uint32_t TXMDHR;
+} CAN_TxMailBox_TypeDef;
+
+/* Controller Area Network FIFOMailBox */ 
+typedef struct
+{
+  __IO uint32_t RXMIR;
+  __IO uint32_t RXMDTR;
+  __IO uint32_t RXMDLR;
+  __IO uint32_t RXMDHR;
+} CAN_FIFOMailBox_TypeDef;
+
+/* Controller Area Network FilterRegister */  
+typedef struct
+{
+  __IO uint32_t FR1;
+  __IO uint32_t FR2;
+} CAN_FilterRegister_TypeDef;
+
+/* Controller Area Network */  
+typedef struct
+{
+  __IO uint32_t CTLR;
+  __IO uint32_t STATR;
+  __IO uint32_t TSTATR;
+  __IO uint32_t RFIFO0;
+  __IO uint32_t RFIFO1;
+  __IO uint32_t INTENR;
+  __IO uint32_t ERRSR;
+  __IO uint32_t BTIMR;
+  uint32_t  RESERVED0[88];
+  CAN_TxMailBox_TypeDef sTxMailBox[3];
+  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
+  uint32_t  RESERVED1[12];
+  __IO uint32_t FCTLR;
+  __IO uint32_t FMCFGR;
+  uint32_t  RESERVED2;
+  __IO uint32_t FSCFGR;
+  uint32_t  RESERVED3;
+  __IO uint32_t FAFIFOR;
+  uint32_t  RESERVED4;
+  __IO uint32_t FWR;
+  uint32_t  RESERVED5[8];
+  CAN_FilterRegister_TypeDef sFilterRegister[28];
+} CAN_TypeDef;
+
+/* CRC Calculation Unit */
+typedef struct
+{
+  __IO uint32_t DATAR;
+  __IO uint8_t  IDATAR;
+  uint8_t   RESERVED0;
+  uint16_t  RESERVED1;
+  __IO uint32_t CTLR;
+} CRC_TypeDef;
+
+/* Digital to Analog Converter */
+typedef struct
+{
+  __IO uint32_t CTLR;
+  __IO uint32_t SWTR;
+  __IO uint32_t R12BDHR1;
+  __IO uint32_t L12BDHR1;
+  __IO uint32_t R8BDHR1;
+  __IO uint32_t R12BDHR2;
+  __IO uint32_t L12BDHR2;
+  __IO uint32_t R8BDHR2;
+  __IO uint32_t RD12BDHR;
+  __IO uint32_t LD12BDHR;
+  __IO uint32_t RD8BDHR;
+  __IO uint32_t DOR1;
+  __IO uint32_t DOR2;
+} DAC_TypeDef;
+
+/* Debug MCU */
+typedef struct
+{
+  __IO uint32_t CFGR0;
+  __IO uint32_t CFGR1;
+}DBGMCU_TypeDef;
+
+/* DMA Channel Controller */
+typedef struct
+{
+  __IO uint32_t CFGR;
+  __IO uint32_t CNTR;
+  __IO uint32_t PADDR;
+  __IO uint32_t MADDR;
+} DMA_Channel_TypeDef;
+
+/* DMA Controller */
+typedef struct
+{
+  __IO uint32_t INTFR;
+  __IO uint32_t INTFCR;
+} DMA_TypeDef;
+
+/* External Interrupt/Event Controller */
+typedef struct
+{
+  __IO uint32_t INTENR; 
+  __IO uint32_t EVENR;   
+  __IO uint32_t RTENR;   
+  __IO uint32_t FTENR;   
+  __IO uint32_t SWIEVR;  
+  __IO uint32_t INTFR;   
+} EXTI_TypeDef;
+
+/* FLASH Registers */
+typedef struct
+{
+  __IO uint32_t ACTLR;
+  __IO uint32_t KEYR;
+  __IO uint32_t OBKEYR;
+  __IO uint32_t STATR;
+  __IO uint32_t CTLR;
+  __IO uint32_t ADDR;
+  __IO uint32_t RESERVED;
+  __IO uint32_t OBR;
+  __IO uint32_t WPR;
+  __IO uint32_t MODEKEYR;
+} FLASH_TypeDef;
+
+/* Option Bytes Registers */  
+typedef struct
+{
+  __IO uint16_t RDPR;
+  __IO uint16_t USER;
+  __IO uint16_t Data0;
+  __IO uint16_t Data1;
+  __IO uint16_t WRPR0;
+  __IO uint16_t WRPR1;
+  __IO uint16_t WRPR2;
+  __IO uint16_t WRPR3;
+} OB_TypeDef;
+
+/* FSMC Bank1 Registers */ 
+typedef struct
+{
+  __IO uint32_t BTCR[8];
+} FSMC_Bank1_TypeDef;
+
+/* FSMC Bank1E Registers */ 
+typedef struct
+{
+  __IO uint32_t BWTR[7];
+} FSMC_Bank1E_TypeDef;
+
+/* FSMC Bank2 Registers */ 
+typedef struct
+{
+  __IO uint32_t PCR2;
+  __IO uint32_t SR2;
+  __IO uint32_t PMEM2;
+  __IO uint32_t PATT2;
+  uint32_t  RESERVED0;
+  __IO uint32_t ECCR2;
+} FSMC_Bank2_TypeDef;
+
+/* General Purpose I/O */
+typedef struct
+{
+  __IO uint32_t CFGLR;
+  __IO uint32_t CFGHR;
+  __IO uint32_t INDR;
+  __IO uint32_t OUTDR;
+  __IO uint32_t BSHR;
+  __IO uint32_t BCR;
+  __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/* Alternate Function I/O */
+typedef struct
+{
+  __IO uint32_t ECR;
+  __IO uint32_t PCFR1;
+  __IO uint32_t EXTICR[4];
+  uint32_t RESERVED0;
+  __IO uint32_t PCFR2;  
+} AFIO_TypeDef;
+
+/* Inter Integrated Circuit Interface */
+typedef struct
+{
+  __IO uint16_t CTLR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CTLR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t OADDR1;
+  uint16_t  RESERVED2;
+  __IO uint16_t OADDR2;
+  uint16_t  RESERVED3;
+  __IO uint16_t DATAR;
+  uint16_t  RESERVED4;
+  __IO uint16_t STAR1;
+  uint16_t  RESERVED5;
+  __IO uint16_t STAR2;
+  uint16_t  RESERVED6;
+  __IO uint16_t CKCFGR;
+  uint16_t  RESERVED7;
+  __IO uint16_t RTR;
+  uint16_t  RESERVED8;
+} I2C_TypeDef;
+
+/* Independent WatchDog */
+typedef struct
+{
+  __IO uint32_t CTLR;
+  __IO uint32_t PSCR;
+  __IO uint32_t RLDR;
+  __IO uint32_t STATR;
+} IWDG_TypeDef;
+
+/* Power Control */
+typedef struct
+{
+  __IO uint32_t CTLR;
+  __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/* Reset and Clock Control */
+typedef struct
+{
+  __IO uint32_t CTLR;
+  __IO uint32_t CFGR0;
+  __IO uint32_t INTR;
+  __IO uint32_t APB2PRSTR;
+  __IO uint32_t APB1PRSTR;
+  __IO uint32_t AHBPCENR;
+  __IO uint32_t APB2PCENR;
+  __IO uint32_t APB1PCENR;
+  __IO uint32_t BDCTLR;
+  __IO uint32_t RSTSCKR;
+
+  __IO uint32_t AHBRSTR;
+  __IO uint32_t CFGR2;
+} RCC_TypeDef;
+
+/* Real-Time Clock */
+typedef struct
+{
+  __IO uint16_t CTLRH;
+  uint16_t  RESERVED0;
+  __IO uint16_t CTLRL;
+  uint16_t  RESERVED1;
+  __IO uint16_t PSCRH;
+  uint16_t  RESERVED2;
+  __IO uint16_t PSCRL;
+  uint16_t  RESERVED3;
+  __IO uint16_t DIVH;
+  uint16_t  RESERVED4;
+  __IO uint16_t DIVL;
+  uint16_t  RESERVED5;
+  __IO uint16_t CNTH;
+  uint16_t  RESERVED6;
+  __IO uint16_t CNTL;
+  uint16_t  RESERVED7;
+  __IO uint16_t ALRMH;
+  uint16_t  RESERVED8;
+  __IO uint16_t ALRML;
+  uint16_t  RESERVED9;
+} RTC_TypeDef;
+
+/* SDIO Registers */ 
+typedef struct
+{
+  __IO uint32_t POWER;
+  __IO uint32_t CLKCR;
+  __IO uint32_t ARG;
+  __IO uint32_t CMD;
+  __I uint32_t RESPCMD;
+  __I uint32_t RESP1;
+  __I uint32_t RESP2;
+  __I uint32_t RESP3;
+  __I uint32_t RESP4;
+  __IO uint32_t DTIMER;
+  __IO uint32_t DLEN;
+  __IO uint32_t DCTRL;
+  __I uint32_t DCOUNT;
+  __I uint32_t STA;
+  __IO uint32_t ICR;
+  __IO uint32_t MASK;
+  uint32_t  RESERVED0[2];
+  __I uint32_t FIFOCNT;
+  uint32_t  RESERVED1[13];
+  __IO uint32_t FIFO;
+} SDIO_TypeDef;
+
+/* Serial Peripheral Interface */
+typedef struct
+{
+  __IO uint16_t CTLR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CTLR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t STATR;
+  uint16_t  RESERVED2;
+  __IO uint16_t DATAR;
+  uint16_t  RESERVED3;
+  __IO uint16_t CRCR;
+  uint16_t  RESERVED4;
+  __IO uint16_t RCRCR;
+  uint16_t  RESERVED5;
+  __IO uint16_t TCRCR;
+  uint16_t  RESERVED6;
+  __IO uint16_t I2SCFGR;
+  uint16_t  RESERVED7;
+  __IO uint16_t I2SPR;
+  uint16_t  RESERVED8;  
+} SPI_TypeDef;
+
+/* TIM */
+typedef struct
+{
+  __IO uint16_t CTLR1;
+  uint16_t  RESERVED0;
+  __IO uint16_t CTLR2;
+  uint16_t  RESERVED1;
+  __IO uint16_t SMCFGR;
+  uint16_t  RESERVED2;
+  __IO uint16_t DMAINTENR;
+  uint16_t  RESERVED3;
+  __IO uint16_t INTFR;
+  uint16_t  RESERVED4;
+  __IO uint16_t SWEVGR;
+  uint16_t  RESERVED5;
+  __IO uint16_t CHCTLR1;
+  uint16_t  RESERVED6;
+  __IO uint16_t CHCTLR2;
+  uint16_t  RESERVED7;
+  __IO uint16_t CCER;
+  uint16_t  RESERVED8;
+  __IO uint16_t CNT;
+  uint16_t  RESERVED9;
+  __IO uint16_t PSC;
+  uint16_t  RESERVED10;
+  __IO uint16_t ATRLR;
+  uint16_t  RESERVED11;
+  __IO uint16_t RPTCR;
+  uint16_t  RESERVED12;
+  __IO uint16_t CH1CVR;
+  uint16_t  RESERVED13;
+  __IO uint16_t CH2CVR;
+  uint16_t  RESERVED14;
+  __IO uint16_t CH3CVR;
+  uint16_t  RESERVED15;
+  __IO uint16_t CH4CVR;
+  uint16_t  RESERVED16;
+  __IO uint16_t BDTR;
+  uint16_t  RESERVED17;
+  __IO uint16_t DMACFGR;
+  uint16_t  RESERVED18;
+  __IO uint16_t DMAADR;
+  uint16_t  RESERVED19;
+} TIM_TypeDef;
+
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+typedef struct
+{
+  __IO uint16_t STATR;
+  uint16_t  RESERVED0;
+  __IO uint16_t DATAR;
+  uint16_t  RESERVED1;
+  __IO uint16_t BRR;
+  uint16_t  RESERVED2;
+  __IO uint16_t CTLR1;
+  uint16_t  RESERVED3;
+  __IO uint16_t CTLR2;
+  uint16_t  RESERVED4;
+  __IO uint16_t CTLR3;
+  uint16_t  RESERVED5;
+  __IO uint16_t GPR;
+  uint16_t  RESERVED6;
+} USART_TypeDef;
+
+/* Window WatchDog */
+typedef struct
+{
+  __IO uint32_t CTLR;
+  __IO uint32_t CFGR;
+  __IO uint32_t STATR;
+} WWDG_TypeDef;
+
+/* Enhanced Registers */
+typedef struct
+{
+  __IO uint32_t EXTEN_CTR;
+} EXTEN_TypeDef;
+
+/* OPA Registers */
+typedef struct
+{
+  __IO uint32_t CR;
+} OPA_TypeDef;
+
+/* RNG Registers */
+typedef struct
+{
+  __IO uint32_t CR;
+  __IO uint32_t SR;
+  __IO uint32_t DR;
+} RNG_TypeDef;
+
+/* DVP Registers */
+typedef struct
+{
+  __IO uint8_t CR0;
+  __IO uint8_t CR1;
+  __IO uint8_t IER;
+  __IO uint8_t Reserved0;        
+  __IO uint16_t ROW_NUM;
+  __IO uint16_t COL_NUM;
+  __IO uint32_t DMA_BUF0;
+  __IO uint32_t DMA_BUF1;
+  __IO uint8_t IFR;
+  __IO uint8_t STATUS;
+  __IO uint16_t Reserved1;            
+  __IO uint16_t ROW_CNT;
+  __IO uint16_t Reserved2;           
+  __IO uint16_t HOFFCNT;
+  __IO uint16_t VST;
+  __IO uint16_t CAPCNT;
+  __IO uint16_t VLINE;
+  __IO uint32_t DR;
+} DVP_TypeDef;
+
+/* USBHS Registers */
+typedef struct
+{
+  __IO uint8_t  CONTROL;
+  __IO uint8_t  HOST_CTRL;
+  __IO uint8_t  INT_EN;
+  __IO uint8_t  DEV_AD;
+  __IO uint16_t FRAME_NO;
+  __IO uint8_t  SUSPEND;
+  __IO uint8_t  RESERVED0;
+  __IO uint8_t  SPEED_TYPE;
+  __IO uint8_t  MIS_ST;
+  __IO uint8_t  INT_FG;
+  __IO uint8_t  INT_ST;
+  __IO uint16_t RX_LEN;
+  __IO uint16_t RESERVED1;
+  __IO uint32_t ENDP_CONFIG;
+  __IO uint32_t ENDP_TYPE;
+  __IO uint32_t BUF_MODE;
+  __IO uint32_t UEP0_DMA;               
+  __IO uint32_t UEP1_RX_DMA;       
+  __IO uint32_t UEP2_RX_DMA;       
+  __IO uint32_t UEP3_RX_DMA;       
+  __IO uint32_t UEP4_RX_DMA;       
+  __IO uint32_t UEP5_RX_DMA;       
+  __IO uint32_t UEP6_RX_DMA;       
+  __IO uint32_t UEP7_RX_DMA;       
+  __IO uint32_t UEP8_RX_DMA;      
+  __IO uint32_t UEP9_RX_DMA;       
+  __IO uint32_t UEP10_RX_DMA;      
+  __IO uint32_t UEP11_RX_DMA;      
+  __IO uint32_t UEP12_RX_DMA;      
+  __IO uint32_t UEP13_RX_DMA;      
+  __IO uint32_t UEP14_RX_DMA;      
+  __IO uint32_t UEP15_RX_DMA;      
+  __IO uint32_t UEP1_TX_DMA;       
+  __IO uint32_t UEP2_TX_DMA;       
+  __IO uint32_t UEP3_TX_DMA;       
+  __IO uint32_t UEP4_TX_DMA;       
+  __IO uint32_t UEP5_TX_DMA;      
+  __IO uint32_t UEP6_TX_DMA;      
+  __IO uint32_t UEP7_TX_DMA;       
+  __IO uint32_t UEP8_TX_DMA;      
+  __IO uint32_t UEP9_TX_DMA;       
+  __IO uint32_t UEP10_TX_DMA;      
+  __IO uint32_t UEP11_TX_DMA;      
+  __IO uint32_t UEP12_TX_DMA;    
+  __IO uint32_t UEP13_TX_DMA;      
+  __IO uint32_t UEP14_TX_DMA;     
+  __IO uint32_t UEP15_TX_DMA;      
+  __IO uint16_t UEP0_MAX_LEN;
+  __IO uint16_t RESERVED2;
+  __IO uint16_t UEP1_MAX_LEN;
+  __IO uint16_t RESERVED3;
+  __IO uint16_t UEP2_MAX_LEN;
+  __IO uint16_t RESERVED4;
+  __IO uint16_t UEP3_MAX_LEN;
+  __IO uint16_t RESERVED5;
+  __IO uint16_t UEP4_MAX_LEN;
+  __IO uint16_t RESERVED6;
+  __IO uint16_t UEP5_MAX_LEN;
+  __IO uint16_t RESERVED7;
+  __IO uint16_t UEP6_MAX_LEN;
+  __IO uint16_t RESERVED8;
+  __IO uint16_t UEP7_MAX_LEN;
+  __IO uint16_t RESERVED9;
+  __IO uint16_t UEP8_MAX_LEN;
+  __IO uint16_t RESERVED10;
+  __IO uint16_t UEP9_MAX_LEN;
+  __IO uint16_t RESERVED11;
+  __IO uint16_t UEP10_MAX_LEN;
+  __IO uint16_t RESERVED12;
+  __IO uint16_t UEP11_MAX_LEN;
+  __IO uint16_t RESERVED13;
+  __IO uint16_t UEP12_MAX_LEN;
+  __IO uint16_t RESERVED14;
+  __IO uint16_t UEP13_MAX_LEN;
+  __IO uint16_t RESERVED15;
+  __IO uint16_t UEP14_MAX_LEN;
+  __IO uint16_t RESERVED16;
+  __IO uint16_t UEP15_MAX_LEN;
+  __IO uint16_t RESERVED17;
+  __IO uint16_t UEP0_TX_LEN;
+  __IO uint8_t  UEP0_TX_CTRL;
+  __IO uint8_t  UEP0_RX_CTRL;
+  __IO uint16_t UEP1_TX_LEN;
+  __IO uint8_t  UEP1_TX_CTRL;
+  __IO uint8_t  UEP1_RX_CTRL;
+  __IO uint16_t UEP2_TX_LEN;
+  __IO uint8_t  UEP2_TX_CTRL;
+  __IO uint8_t  UEP2_RX_CTRL;
+  __IO uint16_t UEP3_TX_LEN;
+  __IO uint8_t  UEP3_TX_CTRL;
+  __IO uint8_t  UEP3_RX_CTRL;
+  __IO uint16_t UEP4_TX_LEN;
+  __IO uint8_t  UEP4_TX_CTRL;
+  __IO uint8_t  UEP4_RX_CTRL;
+  __IO uint16_t UEP5_TX_LEN;
+  __IO uint8_t  UEP5_TX_CTRL;
+  __IO uint8_t  UEP5_RX_CTRL;
+  __IO uint16_t UEP6_TX_LEN;
+  __IO uint8_t  UEP6_TX_CTRL;
+  __IO uint8_t  UEP6_RX_CTRL;
+  __IO uint16_t UEP7_TX_LEN;
+  __IO uint8_t  UEP7_TX_CTRL;
+  __IO uint8_t  UEP7_RX_CTRL;
+  __IO uint16_t UEP8_TX_LEN;
+  __IO uint8_t  UEP8_TX_CTRL;
+  __IO uint8_t  UEP8_RX_CTRL;
+  __IO uint16_t UEP9_TX_LEN;
+  __IO uint8_t  UEP9_TX_CTRL;
+  __IO uint8_t  UEP9_RX_CTRL;
+  __IO uint16_t UEP10_TX_LEN;
+  __IO uint8_t  UEP10_TX_CTRL;
+  __IO uint8_t  UEP10_RX_CTRL;
+  __IO uint16_t UEP11_TX_LEN;
+  __IO uint8_t  UEP11_TX_CTRL;
+  __IO uint8_t  UEP11_RX_CTRL;
+  __IO uint16_t UEP12_TX_LEN;
+  __IO uint8_t  UEP12_TX_CTRL;
+  __IO uint8_t  UEP12_RX_CTRL;
+  __IO uint16_t UEP13_TX_LEN;
+  __IO uint8_t  UEP13_TX_CTRL;
+  __IO uint8_t  UEP13_RX_CTRL;
+  __IO uint16_t UEP14_TX_LEN;
+  __IO uint8_t  UEP14_TX_CTRL;
+  __IO uint8_t  UEP14_RX_CTRL;
+  __IO uint16_t UEP15_TX_LEN;
+  __IO uint8_t  UEP15_TX_CTRL;
+  __IO uint8_t  UEP15_RX_CTRL;
+} USBHSD_TypeDef;
+
+typedef struct  __attribute__((packed))
+{
+    __IO uint8_t  CONTROL;
+    __IO uint8_t  HOST_CTRL;
+    __IO uint8_t  INT_EN;
+    __IO uint8_t  DEV_AD;
+    __IO uint16_t FRAME_NO;
+    __IO uint8_t  SUSPEND;
+    __IO uint8_t  RESERVED0;
+    __IO uint8_t  SPEED_TYPE;
+    __IO uint8_t  MIS_ST;
+    __IO uint8_t  INT_FG;
+    __IO uint8_t  INT_ST;
+    __IO uint16_t RX_LEN;
+    __IO uint16_t RESERVED1;
+    __IO uint32_t HOST_EP_CONFIG;
+    __IO uint32_t HOST_EP_TYPE;
+    __IO uint32_t RESERVED2;
+    __IO uint32_t RESERVED3;
+    __IO uint32_t RESERVED4;
+    __IO uint32_t HOST_RX_DMA;
+    __IO uint32_t RESERVED5;
+    __IO uint32_t RESERVED6;
+    __IO uint32_t RESERVED7;
+    __IO uint32_t RESERVED8;
+    __IO uint32_t RESERVED9;
+    __IO uint32_t RESERVED10;
+    __IO uint32_t RESERVED11;
+    __IO uint32_t RESERVED12;
+    __IO uint32_t RESERVED13;
+    __IO uint32_t RESERVED14;
+    __IO uint32_t RESERVED15;
+    __IO uint32_t RESERVED16;
+    __IO uint32_t RESERVED17;
+    __IO uint32_t RESERVED18;
+    __IO uint32_t RESERVED19;
+    __IO uint32_t HOST_TX_DMA;
+    __IO uint32_t RESERVED20;
+    __IO uint32_t RESERVED21;
+    __IO uint32_t RESERVED22;
+    __IO uint32_t RESERVED23;
+    __IO uint32_t RESERVED24;
+    __IO uint32_t RESERVED25;
+    __IO uint32_t RESERVED26;
+    __IO uint32_t RESERVED27;
+    __IO uint32_t RESERVED28;
+    __IO uint32_t RESERVED29;
+    __IO uint32_t RESERVED30;
+    __IO uint32_t RESERVED31;
+    __IO uint32_t RESERVED32;
+    __IO uint32_t RESERVED33;
+    __IO uint16_t HOST_RX_MAX_LEN;
+    __IO uint16_t RESERVED34;
+    __IO uint32_t RESERVED35;
+    __IO uint32_t RESERVED36;
+    __IO uint32_t RESERVED37;
+    __IO uint32_t RESERVED38;
+    __IO uint32_t RESERVED39;
+    __IO uint32_t RESERVED40;
+    __IO uint32_t RESERVED41;
+    __IO uint32_t RESERVED42;
+    __IO uint32_t RESERVED43;
+    __IO uint32_t RESERVED44;
+    __IO uint32_t RESERVED45;
+    __IO uint32_t RESERVED46;
+    __IO uint32_t RESERVED47;
+    __IO uint32_t RESERVED48;
+    __IO uint32_t RESERVED49;
+    __IO uint8_t  HOST_EP_PID;
+    __IO uint8_t  RESERVED50;
+    __IO uint8_t  RESERVED51;
+    __IO uint8_t  HOST_RX_CTRL;
+    __IO uint16_t HOST_TX_LEN;
+    __IO uint8_t  HOST_TX_CTRL;
+    __IO uint8_t  RESERVED52;
+    __IO uint16_t HOST_SPLIT_DATA;
+} USBHSH_TypeDef;
+
+
+/* USBOTG_FS Registers */
+typedef struct
+{
+   __IO uint8_t  BASE_CTRL;
+   __IO uint8_t  UDEV_CTRL;
+   __IO uint8_t  INT_EN;
+   __IO uint8_t  DEV_ADDR;
+   __IO uint8_t  Reserve0;
+   __IO uint8_t  MIS_ST;
+   __IO uint8_t  INT_FG;
+   __IO uint8_t  INT_ST;
+   __IO uint16_t RX_LEN;
+   __IO uint16_t Reserve1;
+   __IO uint8_t  UEP4_1_MOD;
+   __IO uint8_t  UEP2_3_MOD;
+   __IO uint8_t  UEP5_6_MOD;
+   __IO uint8_t  UEP7_MOD;
+   __IO uint32_t UEP0_DMA;
+   __IO uint32_t UEP1_DMA;
+   __IO uint32_t UEP2_DMA;
+   __IO uint32_t UEP3_DMA;
+   __IO uint32_t UEP4_DMA;
+   __IO uint32_t UEP5_DMA;
+   __IO uint32_t UEP6_DMA;
+   __IO uint32_t UEP7_DMA;
+   __IO uint16_t UEP0_TX_LEN;
+   __IO uint8_t  UEP0_TX_CTRL;
+   __IO uint8_t  UEP0_RX_CTRL;
+   __IO uint16_t UEP1_TX_LEN;
+   __IO uint8_t  UEP1_TX_CTRL;
+   __IO uint8_t  UEP1_RX_CTRL;
+   __IO uint16_t UEP2_TX_LEN;
+   __IO uint8_t  UEP2_TX_CTRL;
+   __IO uint8_t  UEP2_RX_CTRL;
+   __IO uint16_t UEP3_TX_LEN;
+   __IO uint8_t  UEP3_TX_CTRL;
+   __IO uint8_t  UEP3_RX_CTRL;
+   __IO uint16_t UEP4_TX_LEN;
+   __IO uint8_t  UEP4_TX_CTRL;
+   __IO uint8_t  UEP4_RX_CTRL;
+   __IO uint16_t UEP5_TX_LEN;
+   __IO uint8_t  UEP5_TX_CTRL;
+   __IO uint8_t  UEP5_RX_CTRL;
+   __IO uint16_t UEP6_TX_LEN;
+   __IO uint8_t  UEP6_TX_CTRL;
+   __IO uint8_t  UEP6_RX_CTRL;
+   __IO uint16_t UEP7_TX_LEN;
+   __IO uint8_t  UEP7_TX_CTRL;
+   __IO uint8_t  UEP7_RX_CTRL;
+   __IO uint32_t Reserve2;
+   __IO uint32_t OTG_CR;
+   __IO uint32_t OTG_SR;
+}USBOTG_FS_TypeDef;
+
+typedef struct  __attribute__((packed))
+{
+   __IO uint8_t   BASE_CTRL;
+   __IO uint8_t   HOST_CTRL;
+   __IO uint8_t   INT_EN;
+   __IO uint8_t   DEV_ADDR;
+   __IO uint8_t   Reserve0;
+   __IO uint8_t   MIS_ST;
+   __IO uint8_t   INT_FG;
+   __IO uint8_t   INT_ST;
+   __IO uint16_t  RX_LEN;
+   __IO uint16_t  Reserve1;
+   __IO uint8_t   Reserve2;
+   __IO uint8_t   HOST_EP_MOD;
+   __IO uint16_t  Reserve3;
+   __IO uint32_t  Reserve4;
+   __IO uint32_t  Reserve5;
+   __IO uint32_t  HOST_RX_DMA;
+   __IO uint32_t  HOST_TX_DMA;
+   __IO uint32_t  Reserve6;
+   __IO uint32_t  Reserve7;
+   __IO uint32_t  Reserve8;
+   __IO uint32_t  Reserve9;
+   __IO uint32_t  Reserve10;
+   __IO uint16_t  Reserve11;
+   __IO uint16_t  HOST_SETUP;
+   __IO uint8_t   HOST_EP_PID;
+   __IO uint8_t   Reserve12;
+   __IO uint8_t   Reserve13;
+   __IO uint8_t   HOST_RX_CTRL;
+   __IO uint16_t  HOST_TX_LEN;
+   __IO uint8_t   HOST_TX_CTRL;
+   __IO uint8_t   Reserve14;
+   __IO uint32_t  Reserve15;
+   __IO uint32_t  Reserve16;
+   __IO uint32_t  Reserve17;
+   __IO uint32_t  Reserve18;
+   __IO uint32_t  Reserve19;
+   __IO uint32_t  OTG_CR;
+   __IO uint32_t  OTG_SR;
+}USBOTGH_FS_TypeDef;
+
+/* Ethernet MAC */
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;
+       uint32_t RESERVED0[2];
+  __IO uint32_t MACRWUFFR;
+  __IO uint32_t MACPMTCSR;
+       uint32_t RESERVED1[2];
+  __IO uint32_t MACSR;
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;
+       uint32_t RESERVED2[40];
+  __IO uint32_t MMCCR;
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;
+       uint32_t RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;
+  __IO uint32_t MMCTGFMSCCR;
+       uint32_t RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+       uint32_t RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+       uint32_t RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+       uint32_t RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+       uint32_t RESERVED8[567];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+       uint32_t RESERVED9[9];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+
+
+/* Peripheral memory map */
+#define FLASH_BASE            ((uint32_t)0x08000000) /* FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /* SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /* Peripheral base address in the alias region */
+
+#define FSMC_R_BASE           ((uint32_t)0xA0000000) /* FSMC registers base address */
+
+
+#define APB1PERIPH_BASE       (PERIPH_BASE)
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
+#define UART6_BASE            (APB1PERIPH_BASE + 0x1800)
+#define UART7_BASE            (APB1PERIPH_BASE + 0x1C00)
+#define UART8_BASE            (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
+#define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+
+#define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE            (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE            (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4C00)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x5000)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x5400)
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x8000)
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE    (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE    (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE    (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE    (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE    (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE    (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE    (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE             (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE    (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE    (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE    (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE    (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE    (AHBPERIPH_BASE + 0x0458)
+#define DMA2_Channel6_BASE    (AHBPERIPH_BASE + 0x046C)
+#define DMA2_Channel7_BASE    (AHBPERIPH_BASE + 0x0480)
+#define DMA2_Channel8_BASE    (AHBPERIPH_BASE + 0x0490)
+#define DMA2_Channel9_BASE    (AHBPERIPH_BASE + 0x04A0)
+#define DMA2_Channel10_BASE   (AHBPERIPH_BASE + 0x04B0)
+#define DMA2_Channel11_BASE   (AHBPERIPH_BASE + 0x04C0)
+#define DMA2_EXTEN_BASE       (AHBPERIPH_BASE + 0x04D0)
+#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000)
+#define CRC_BASE              (AHBPERIPH_BASE + 0x3000)
+#define USBHS_BASE            (AHBPERIPH_BASE + 0x3400)
+#define EXTEN_BASE            (AHBPERIPH_BASE + 0x3800)
+#define OPA_BASE              (AHBPERIPH_BASE + 0x3804)
+#define RNG_BASE              (AHBPERIPH_BASE + 0x3C00)
+
+#define ETH_BASE              (AHBPERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
+
+#define USBFS_BASE            ((uint32_t)0x50000000)
+#define DVP_BASE              ((uint32_t)0x50050000)
+
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000) 
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104) 
+#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060) 
+
+#define DBGMCU_BASE           ((uint32_t)0xE000D000)
+
+#define OB_BASE               ((uint32_t)0x1FFFF800)
+
+/* Peripheral declaration */
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define UART6               ((USART_TypeDef *) UART6_BASE)
+#define UART7               ((USART_TypeDef *) UART7_BASE)
+#define UART8               ((USART_TypeDef *) UART8_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define BKP                 ((BKP_TypeDef *) BKP_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+
+#define AFIO                ((AFIO_TypeDef *) AFIO_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define TKey1               ((ADC_TypeDef *) ADC1_BASE)
+#define TKey2               ((ADC_TypeDef *) ADC2_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)
+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_EXTEN          ((DMA_TypeDef *) DMA2_EXTEN_BASE)
+#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define DMA2_Channel6       ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
+#define DMA2_Channel7       ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
+#define DMA2_Channel8       ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
+#define DMA2_Channel9       ((DMA_Channel_TypeDef *) DMA2_Channel9_BASE)
+#define DMA2_Channel10      ((DMA_Channel_TypeDef *) DMA2_Channel10_BASE)
+#define DMA2_Channel11      ((DMA_Channel_TypeDef *) DMA2_Channel11_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define USBHSD              ((USBHSD_TypeDef *) USBHS_BASE)
+#define USBHSH              ((USBHSH_TypeDef *) USBHS_BASE)
+#define USBOTG_FS           ((USBOTG_FS_TypeDef *)USBFS_BASE)
+#define USBOTG_H_FS         ((USBOTGH_FS_TypeDef *)USBFS_BASE)
+#define EXTEN               ((EXTEN_TypeDef *) EXTEN_BASE)
+#define OPA                 ((OPA_TypeDef *) OPA_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)
+
+#define DVP                 ((DVP_TypeDef *) DVP_BASE)
+
+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+#define OB                  ((OB_TypeDef *) OB_BASE)
+
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                        Analog to Digital Converter                         */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_STATR register  ********************/
+#define  ADC_AWD                        ((uint8_t)0x01)               /* Analog watchdog flag */
+#define  ADC_EOC                        ((uint8_t)0x02)               /* End of conversion */
+#define  ADC_JEOC                       ((uint8_t)0x04)               /* Injected channel end of conversion */
+#define  ADC_JSTRT                      ((uint8_t)0x08)               /* Injected channel Start flag */
+#define  ADC_STRT                       ((uint8_t)0x10)               /* Regular channel Start flag */
+
+/*******************  Bit definition for ADC_CTLR1 register  ********************/
+#define  ADC_AWDCH                      ((uint32_t)0x0000001F)        /* AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define  ADC_AWDCH_0                    ((uint32_t)0x00000001)        /* Bit 0 */
+#define  ADC_AWDCH_1                    ((uint32_t)0x00000002)        /* Bit 1 */
+#define  ADC_AWDCH_2                    ((uint32_t)0x00000004)        /* Bit 2 */
+#define  ADC_AWDCH_3                    ((uint32_t)0x00000008)        /* Bit 3 */
+#define  ADC_AWDCH_4                    ((uint32_t)0x00000010)        /* Bit 4 */
+
+#define  ADC_EOCIE                      ((uint32_t)0x00000020)        /* Interrupt enable for EOC */
+#define  ADC_AWDIE                      ((uint32_t)0x00000040)        /* Analog Watchdog interrupt enable */
+#define  ADC_JEOCIE                     ((uint32_t)0x00000080)        /* Interrupt enable for injected channels */
+#define  ADC_SCAN                       ((uint32_t)0x00000100)        /* Scan mode */
+#define  ADC_AWDSGL                     ((uint32_t)0x00000200)        /* Enable the watchdog on a single channel in scan mode */
+#define  ADC_JAUTO                      ((uint32_t)0x00000400)        /* Automatic injected group conversion */
+#define  ADC_DISCEN                     ((uint32_t)0x00000800)        /* Discontinuous mode on regular channels */
+#define  ADC_JDISCEN                    ((uint32_t)0x00001000)        /* Discontinuous mode on injected channels */
+
+#define  ADC_DISCNUM                    ((uint32_t)0x0000E000)        /* DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define  ADC_DISCNUM_0                  ((uint32_t)0x00002000)        /* Bit 0 */
+#define  ADC_DISCNUM_1                  ((uint32_t)0x00004000)        /* Bit 1 */
+#define  ADC_DISCNUM_2                  ((uint32_t)0x00008000)        /* Bit 2 */
+
+#define  ADC_DUALMOD                    ((uint32_t)0x000F0000)        /* DUALMOD[3:0] bits (Dual mode selection) */
+#define  ADC_DUALMOD_0                  ((uint32_t)0x00010000)        /* Bit 0 */
+#define  ADC_DUALMOD_1                  ((uint32_t)0x00020000)        /* Bit 1 */
+#define  ADC_DUALMOD_2                  ((uint32_t)0x00040000)        /* Bit 2 */
+#define  ADC_DUALMOD_3                  ((uint32_t)0x00080000)        /* Bit 3 */
+
+#define  ADC_JAWDEN                     ((uint32_t)0x00400000)        /* Analog watchdog enable on injected channels */
+#define  ADC_AWDEN                      ((uint32_t)0x00800000)        /* Analog watchdog enable on regular channels */
+
+/*******************  Bit definition for ADC_CTLR2 register  ********************/
+#define  ADC_ADON                       ((uint32_t)0x00000001)        /* A/D Converter ON / OFF */
+#define  ADC_CONT                       ((uint32_t)0x00000002)        /* Continuous Conversion */
+#define  ADC_CAL                        ((uint32_t)0x00000004)        /* A/D Calibration */
+#define  ADC_RSTCAL                     ((uint32_t)0x00000008)        /* Reset Calibration */
+#define  ADC_DMA                        ((uint32_t)0x00000100)        /* Direct Memory access mode */
+#define  ADC_ALIGN                      ((uint32_t)0x00000800)        /* Data Alignment */
+
+#define  ADC_JEXTSEL                    ((uint32_t)0x00007000)        /* JEXTSEL[2:0] bits (External event select for injected group) */
+#define  ADC_JEXTSEL_0                  ((uint32_t)0x00001000)        /* Bit 0 */
+#define  ADC_JEXTSEL_1                  ((uint32_t)0x00002000)        /* Bit 1 */
+#define  ADC_JEXTSEL_2                  ((uint32_t)0x00004000)        /* Bit 2 */
+
+#define  ADC_JEXTTRIG                   ((uint32_t)0x00008000)        /* External Trigger Conversion mode for injected channels */
+
+#define  ADC_EXTSEL                     ((uint32_t)0x000E0000)        /* EXTSEL[2:0] bits (External Event Select for regular group) */
+#define  ADC_EXTSEL_0                   ((uint32_t)0x00020000)        /* Bit 0 */
+#define  ADC_EXTSEL_1                   ((uint32_t)0x00040000)        /* Bit 1 */
+#define  ADC_EXTSEL_2                   ((uint32_t)0x00080000)        /* Bit 2 */
+
+#define  ADC_EXTTRIG                    ((uint32_t)0x00100000)        /* External Trigger Conversion mode for regular channels */
+#define  ADC_JSWSTART                   ((uint32_t)0x00200000)        /* Start Conversion of injected channels */
+#define  ADC_SWSTART                    ((uint32_t)0x00400000)        /* Start Conversion of regular channels */
+#define  ADC_TSVREFE                    ((uint32_t)0x00800000)        /* Temperature Sensor and VREFINT Enable */
+
+/******************  Bit definition for ADC_SAMPTR1 register  *******************/
+#define  ADC_SMP10                      ((uint32_t)0x00000007)        /* SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define  ADC_SMP10_0                    ((uint32_t)0x00000001)        /* Bit 0 */
+#define  ADC_SMP10_1                    ((uint32_t)0x00000002)        /* Bit 1 */
+#define  ADC_SMP10_2                    ((uint32_t)0x00000004)        /* Bit 2 */
+
+#define  ADC_SMP11                      ((uint32_t)0x00000038)        /* SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define  ADC_SMP11_0                    ((uint32_t)0x00000008)        /* Bit 0 */
+#define  ADC_SMP11_1                    ((uint32_t)0x00000010)        /* Bit 1 */
+#define  ADC_SMP11_2                    ((uint32_t)0x00000020)        /* Bit 2 */
+
+#define  ADC_SMP12                      ((uint32_t)0x000001C0)        /* SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define  ADC_SMP12_0                    ((uint32_t)0x00000040)        /* Bit 0 */
+#define  ADC_SMP12_1                    ((uint32_t)0x00000080)        /* Bit 1 */
+#define  ADC_SMP12_2                    ((uint32_t)0x00000100)        /* Bit 2 */
+
+#define  ADC_SMP13                      ((uint32_t)0x00000E00)        /* SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define  ADC_SMP13_0                    ((uint32_t)0x00000200)        /* Bit 0 */
+#define  ADC_SMP13_1                    ((uint32_t)0x00000400)        /* Bit 1 */
+#define  ADC_SMP13_2                    ((uint32_t)0x00000800)        /* Bit 2 */
+
+#define  ADC_SMP14                      ((uint32_t)0x00007000)        /* SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define  ADC_SMP14_0                    ((uint32_t)0x00001000)        /* Bit 0 */
+#define  ADC_SMP14_1                    ((uint32_t)0x00002000)        /* Bit 1 */
+#define  ADC_SMP14_2                    ((uint32_t)0x00004000)        /* Bit 2 */
+
+#define  ADC_SMP15                      ((uint32_t)0x00038000)        /* SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define  ADC_SMP15_0                    ((uint32_t)0x00008000)        /* Bit 0 */
+#define  ADC_SMP15_1                    ((uint32_t)0x00010000)        /* Bit 1 */
+#define  ADC_SMP15_2                    ((uint32_t)0x00020000)        /* Bit 2 */
+
+#define  ADC_SMP16                      ((uint32_t)0x001C0000)        /* SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define  ADC_SMP16_0                    ((uint32_t)0x00040000)        /* Bit 0 */
+#define  ADC_SMP16_1                    ((uint32_t)0x00080000)        /* Bit 1 */
+#define  ADC_SMP16_2                    ((uint32_t)0x00100000)        /* Bit 2 */
+
+#define  ADC_SMP17                      ((uint32_t)0x00E00000)        /* SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define  ADC_SMP17_0                    ((uint32_t)0x00200000)        /* Bit 0 */
+#define  ADC_SMP17_1                    ((uint32_t)0x00400000)        /* Bit 1 */
+#define  ADC_SMP17_2                    ((uint32_t)0x00800000)        /* Bit 2 */
+
+/******************  Bit definition for ADC_SAMPTR2 register  *******************/
+#define  ADC_SMP0                       ((uint32_t)0x00000007)        /* SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define  ADC_SMP0_0                     ((uint32_t)0x00000001)        /* Bit 0 */
+#define  ADC_SMP0_1                     ((uint32_t)0x00000002)        /* Bit 1 */
+#define  ADC_SMP0_2                     ((uint32_t)0x00000004)        /* Bit 2 */
+
+#define  ADC_SMP1                       ((uint32_t)0x00000038)        /* SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define  ADC_SMP1_0                     ((uint32_t)0x00000008)        /* Bit 0 */
+#define  ADC_SMP1_1                     ((uint32_t)0x00000010)        /* Bit 1 */
+#define  ADC_SMP1_2                     ((uint32_t)0x00000020)        /* Bit 2 */
+
+#define  ADC_SMP2                       ((uint32_t)0x000001C0)        /* SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define  ADC_SMP2_0                     ((uint32_t)0x00000040)        /* Bit 0 */
+#define  ADC_SMP2_1                     ((uint32_t)0x00000080)        /* Bit 1 */
+#define  ADC_SMP2_2                     ((uint32_t)0x00000100)        /* Bit 2 */
+
+#define  ADC_SMP3                       ((uint32_t)0x00000E00)        /* SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define  ADC_SMP3_0                     ((uint32_t)0x00000200)        /* Bit 0 */
+#define  ADC_SMP3_1                     ((uint32_t)0x00000400)        /* Bit 1 */
+#define  ADC_SMP3_2                     ((uint32_t)0x00000800)        /* Bit 2 */
+
+#define  ADC_SMP4                       ((uint32_t)0x00007000)        /* SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define  ADC_SMP4_0                     ((uint32_t)0x00001000)        /* Bit 0 */
+#define  ADC_SMP4_1                     ((uint32_t)0x00002000)        /* Bit 1 */
+#define  ADC_SMP4_2                     ((uint32_t)0x00004000)        /* Bit 2 */
+
+#define  ADC_SMP5                       ((uint32_t)0x00038000)        /* SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define  ADC_SMP5_0                     ((uint32_t)0x00008000)        /* Bit 0 */
+#define  ADC_SMP5_1                     ((uint32_t)0x00010000)        /* Bit 1 */
+#define  ADC_SMP5_2                     ((uint32_t)0x00020000)        /* Bit 2 */
+
+#define  ADC_SMP6                       ((uint32_t)0x001C0000)        /* SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define  ADC_SMP6_0                     ((uint32_t)0x00040000)        /* Bit 0 */
+#define  ADC_SMP6_1                     ((uint32_t)0x00080000)        /* Bit 1 */
+#define  ADC_SMP6_2                     ((uint32_t)0x00100000)        /* Bit 2 */
+
+#define  ADC_SMP7                       ((uint32_t)0x00E00000)        /* SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define  ADC_SMP7_0                     ((uint32_t)0x00200000)        /* Bit 0 */
+#define  ADC_SMP7_1                     ((uint32_t)0x00400000)        /* Bit 1 */
+#define  ADC_SMP7_2                     ((uint32_t)0x00800000)        /* Bit 2 */
+
+#define  ADC_SMP8                       ((uint32_t)0x07000000)        /* SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define  ADC_SMP8_0                     ((uint32_t)0x01000000)        /* Bit 0 */
+#define  ADC_SMP8_1                     ((uint32_t)0x02000000)        /* Bit 1 */
+#define  ADC_SMP8_2                     ((uint32_t)0x04000000)        /* Bit 2 */
+
+#define  ADC_SMP9                       ((uint32_t)0x38000000)        /* SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define  ADC_SMP9_0                     ((uint32_t)0x08000000)        /* Bit 0 */
+#define  ADC_SMP9_1                     ((uint32_t)0x10000000)        /* Bit 1 */
+#define  ADC_SMP9_2                     ((uint32_t)0x20000000)        /* Bit 2 */
+
+/******************  Bit definition for ADC_IOFR1 register  *******************/
+#define  ADC_JOFFSET1                   ((uint16_t)0x0FFF)            /* Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_IOFR2 register  *******************/
+#define  ADC_JOFFSET2                   ((uint16_t)0x0FFF)            /* Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_IOFR3 register  *******************/
+#define  ADC_JOFFSET3                   ((uint16_t)0x0FFF)            /* Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_IOFR4 register  *******************/
+#define  ADC_JOFFSET4                   ((uint16_t)0x0FFF)            /* Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_WDHTR register  ********************/
+#define  ADC_HT                         ((uint16_t)0x0FFF)            /* Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_WDLTR register  ********************/
+#define  ADC_LT                         ((uint16_t)0x0FFF)            /* Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_RSQR1 register  *******************/
+#define  ADC_SQ13                       ((uint32_t)0x0000001F)        /* SQ13[4:0] bits (13th conversion in regular sequence) */
+#define  ADC_SQ13_0                     ((uint32_t)0x00000001)        /* Bit 0 */
+#define  ADC_SQ13_1                     ((uint32_t)0x00000002)        /* Bit 1 */
+#define  ADC_SQ13_2                     ((uint32_t)0x00000004)        /* Bit 2 */
+#define  ADC_SQ13_3                     ((uint32_t)0x00000008)        /* Bit 3 */
+#define  ADC_SQ13_4                     ((uint32_t)0x00000010)        /* Bit 4 */
+
+#define  ADC_SQ14                       ((uint32_t)0x000003E0)        /* SQ14[4:0] bits (14th conversion in regular sequence) */
+#define  ADC_SQ14_0                     ((uint32_t)0x00000020)        /* Bit 0 */
+#define  ADC_SQ14_1                     ((uint32_t)0x00000040)        /* Bit 1 */
+#define  ADC_SQ14_2                     ((uint32_t)0x00000080)        /* Bit 2 */
+#define  ADC_SQ14_3                     ((uint32_t)0x00000100)        /* Bit 3 */
+#define  ADC_SQ14_4                     ((uint32_t)0x00000200)        /* Bit 4 */
+
+#define  ADC_SQ15                       ((uint32_t)0x00007C00)        /* SQ15[4:0] bits (15th conversion in regular sequence) */
+#define  ADC_SQ15_0                     ((uint32_t)0x00000400)        /* Bit 0 */
+#define  ADC_SQ15_1                     ((uint32_t)0x00000800)        /* Bit 1 */
+#define  ADC_SQ15_2                     ((uint32_t)0x00001000)        /* Bit 2 */
+#define  ADC_SQ15_3                     ((uint32_t)0x00002000)        /* Bit 3 */
+#define  ADC_SQ15_4                     ((uint32_t)0x00004000)        /* Bit 4 */
+
+#define  ADC_SQ16                       ((uint32_t)0x000F8000)        /* SQ16[4:0] bits (16th conversion in regular sequence) */
+#define  ADC_SQ16_0                     ((uint32_t)0x00008000)        /* Bit 0 */
+#define  ADC_SQ16_1                     ((uint32_t)0x00010000)        /* Bit 1 */
+#define  ADC_SQ16_2                     ((uint32_t)0x00020000)        /* Bit 2 */
+#define  ADC_SQ16_3                     ((uint32_t)0x00040000)        /* Bit 3 */
+#define  ADC_SQ16_4                     ((uint32_t)0x00080000)        /* Bit 4 */
+
+#define  ADC_L                          ((uint32_t)0x00F00000)        /* L[3:0] bits (Regular channel sequence length) */
+#define  ADC_L_0                        ((uint32_t)0x00100000)        /* Bit 0 */
+#define  ADC_L_1                        ((uint32_t)0x00200000)        /* Bit 1 */
+#define  ADC_L_2                        ((uint32_t)0x00400000)        /* Bit 2 */
+#define  ADC_L_3                        ((uint32_t)0x00800000)        /* Bit 3 */
+
+/*******************  Bit definition for ADC_RSQR2 register  *******************/
+#define  ADC_SQ7                        ((uint32_t)0x0000001F)        /* SQ7[4:0] bits (7th conversion in regular sequence) */
+#define  ADC_SQ7_0                      ((uint32_t)0x00000001)        /* Bit 0 */
+#define  ADC_SQ7_1                      ((uint32_t)0x00000002)        /* Bit 1 */
+#define  ADC_SQ7_2                      ((uint32_t)0x00000004)        /* Bit 2 */
+#define  ADC_SQ7_3                      ((uint32_t)0x00000008)        /* Bit 3 */
+#define  ADC_SQ7_4                      ((uint32_t)0x00000010)        /* Bit 4 */
+
+#define  ADC_SQ8                        ((uint32_t)0x000003E0)        /* SQ8[4:0] bits (8th conversion in regular sequence) */
+#define  ADC_SQ8_0                      ((uint32_t)0x00000020)        /* Bit 0 */
+#define  ADC_SQ8_1                      ((uint32_t)0x00000040)        /* Bit 1 */
+#define  ADC_SQ8_2                      ((uint32_t)0x00000080)        /* Bit 2 */
+#define  ADC_SQ8_3                      ((uint32_t)0x00000100)        /* Bit 3 */
+#define  ADC_SQ8_4                      ((uint32_t)0x00000200)        /* Bit 4 */
+
+#define  ADC_SQ9                        ((uint32_t)0x00007C00)        /* SQ9[4:0] bits (9th conversion in regular sequence) */
+#define  ADC_SQ9_0                      ((uint32_t)0x00000400)        /* Bit 0 */
+#define  ADC_SQ9_1                      ((uint32_t)0x00000800)        /* Bit 1 */
+#define  ADC_SQ9_2                      ((uint32_t)0x00001000)        /* Bit 2 */
+#define  ADC_SQ9_3                      ((uint32_t)0x00002000)        /* Bit 3 */
+#define  ADC_SQ9_4                      ((uint32_t)0x00004000)        /* Bit 4 */
+
+#define  ADC_SQ10                       ((uint32_t)0x000F8000)        /* SQ10[4:0] bits (10th conversion in regular sequence) */
+#define  ADC_SQ10_0                     ((uint32_t)0x00008000)        /* Bit 0 */
+#define  ADC_SQ10_1                     ((uint32_t)0x00010000)        /* Bit 1 */
+#define  ADC_SQ10_2                     ((uint32_t)0x00020000)        /* Bit 2 */
+#define  ADC_SQ10_3                     ((uint32_t)0x00040000)        /* Bit 3 */
+#define  ADC_SQ10_4                     ((uint32_t)0x00080000)        /* Bit 4 */
+
+#define  ADC_SQ11                       ((uint32_t)0x01F00000)        /* SQ11[4:0] bits (11th conversion in regular sequence) */
+#define  ADC_SQ11_0                     ((uint32_t)0x00100000)        /* Bit 0 */
+#define  ADC_SQ11_1                     ((uint32_t)0x00200000)        /* Bit 1 */
+#define  ADC_SQ11_2                     ((uint32_t)0x00400000)        /* Bit 2 */
+#define  ADC_SQ11_3                     ((uint32_t)0x00800000)        /* Bit 3 */
+#define  ADC_SQ11_4                     ((uint32_t)0x01000000)        /* Bit 4 */
+
+#define  ADC_SQ12                       ((uint32_t)0x3E000000)        /* SQ12[4:0] bits (12th conversion in regular sequence) */
+#define  ADC_SQ12_0                     ((uint32_t)0x02000000)        /* Bit 0 */
+#define  ADC_SQ12_1                     ((uint32_t)0x04000000)        /* Bit 1 */
+#define  ADC_SQ12_2                     ((uint32_t)0x08000000)        /* Bit 2 */
+#define  ADC_SQ12_3                     ((uint32_t)0x10000000)        /* Bit 3 */
+#define  ADC_SQ12_4                     ((uint32_t)0x20000000)        /* Bit 4 */
+
+/*******************  Bit definition for ADC_RSQR3 register  *******************/
+#define  ADC_SQ1                        ((uint32_t)0x0000001F)        /* SQ1[4:0] bits (1st conversion in regular sequence) */
+#define  ADC_SQ1_0                      ((uint32_t)0x00000001)        /* Bit 0 */
+#define  ADC_SQ1_1                      ((uint32_t)0x00000002)        /* Bit 1 */
+#define  ADC_SQ1_2                      ((uint32_t)0x00000004)        /* Bit 2 */
+#define  ADC_SQ1_3                      ((uint32_t)0x00000008)        /* Bit 3 */
+#define  ADC_SQ1_4                      ((uint32_t)0x00000010)        /* Bit 4 */
+
+#define  ADC_SQ2                        ((uint32_t)0x000003E0)        /* SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define  ADC_SQ2_0                      ((uint32_t)0x00000020)        /* Bit 0 */
+#define  ADC_SQ2_1                      ((uint32_t)0x00000040)        /* Bit 1 */
+#define  ADC_SQ2_2                      ((uint32_t)0x00000080)        /* Bit 2 */
+#define  ADC_SQ2_3                      ((uint32_t)0x00000100)        /* Bit 3 */
+#define  ADC_SQ2_4                      ((uint32_t)0x00000200)        /* Bit 4 */
+
+#define  ADC_SQ3                        ((uint32_t)0x00007C00)        /* SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define  ADC_SQ3_0                      ((uint32_t)0x00000400)        /* Bit 0 */
+#define  ADC_SQ3_1                      ((uint32_t)0x00000800)        /* Bit 1 */
+#define  ADC_SQ3_2                      ((uint32_t)0x00001000)        /* Bit 2 */
+#define  ADC_SQ3_3                      ((uint32_t)0x00002000)        /* Bit 3 */
+#define  ADC_SQ3_4                      ((uint32_t)0x00004000)        /* Bit 4 */
+
+#define  ADC_SQ4                        ((uint32_t)0x000F8000)        /* SQ4[4:0] bits (4th conversion in regular sequence) */
+#define  ADC_SQ4_0                      ((uint32_t)0x00008000)        /* Bit 0 */
+#define  ADC_SQ4_1                      ((uint32_t)0x00010000)        /* Bit 1 */
+#define  ADC_SQ4_2                      ((uint32_t)0x00020000)        /* Bit 2 */
+#define  ADC_SQ4_3                      ((uint32_t)0x00040000)        /* Bit 3 */
+#define  ADC_SQ4_4                      ((uint32_t)0x00080000)        /* Bit 4 */
+
+#define  ADC_SQ5                        ((uint32_t)0x01F00000)        /* SQ5[4:0] bits (5th conversion in regular sequence) */
+#define  ADC_SQ5_0                      ((uint32_t)0x00100000)        /* Bit 0 */
+#define  ADC_SQ5_1                      ((uint32_t)0x00200000)        /* Bit 1 */
+#define  ADC_SQ5_2                      ((uint32_t)0x00400000)        /* Bit 2 */
+#define  ADC_SQ5_3                      ((uint32_t)0x00800000)        /* Bit 3 */
+#define  ADC_SQ5_4                      ((uint32_t)0x01000000)        /* Bit 4 */
+
+#define  ADC_SQ6                        ((uint32_t)0x3E000000)        /* SQ6[4:0] bits (6th conversion in regular sequence) */
+#define  ADC_SQ6_0                      ((uint32_t)0x02000000)        /* Bit 0 */
+#define  ADC_SQ6_1                      ((uint32_t)0x04000000)        /* Bit 1 */
+#define  ADC_SQ6_2                      ((uint32_t)0x08000000)        /* Bit 2 */
+#define  ADC_SQ6_3                      ((uint32_t)0x10000000)        /* Bit 3 */
+#define  ADC_SQ6_4                      ((uint32_t)0x20000000)        /* Bit 4 */
+
+/*******************  Bit definition for ADC_ISQR register  *******************/
+#define  ADC_JSQ1                       ((uint32_t)0x0000001F)        /* JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define  ADC_JSQ1_0                     ((uint32_t)0x00000001)        /* Bit 0 */
+#define  ADC_JSQ1_1                     ((uint32_t)0x00000002)        /* Bit 1 */
+#define  ADC_JSQ1_2                     ((uint32_t)0x00000004)        /* Bit 2 */
+#define  ADC_JSQ1_3                     ((uint32_t)0x00000008)        /* Bit 3 */
+#define  ADC_JSQ1_4                     ((uint32_t)0x00000010)        /* Bit 4 */
+
+#define  ADC_JSQ2                       ((uint32_t)0x000003E0)        /* JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define  ADC_JSQ2_0                     ((uint32_t)0x00000020)        /* Bit 0 */
+#define  ADC_JSQ2_1                     ((uint32_t)0x00000040)        /* Bit 1 */
+#define  ADC_JSQ2_2                     ((uint32_t)0x00000080)        /* Bit 2 */
+#define  ADC_JSQ2_3                     ((uint32_t)0x00000100)        /* Bit 3 */
+#define  ADC_JSQ2_4                     ((uint32_t)0x00000200)        /* Bit 4 */
+
+#define  ADC_JSQ3                       ((uint32_t)0x00007C00)        /* JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define  ADC_JSQ3_0                     ((uint32_t)0x00000400)        /* Bit 0 */
+#define  ADC_JSQ3_1                     ((uint32_t)0x00000800)        /* Bit 1 */
+#define  ADC_JSQ3_2                     ((uint32_t)0x00001000)        /* Bit 2 */
+#define  ADC_JSQ3_3                     ((uint32_t)0x00002000)        /* Bit 3 */
+#define  ADC_JSQ3_4                     ((uint32_t)0x00004000)        /* Bit 4 */
+
+#define  ADC_JSQ4                       ((uint32_t)0x000F8000)        /* JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define  ADC_JSQ4_0                     ((uint32_t)0x00008000)        /* Bit 0 */
+#define  ADC_JSQ4_1                     ((uint32_t)0x00010000)        /* Bit 1 */
+#define  ADC_JSQ4_2                     ((uint32_t)0x00020000)        /* Bit 2 */
+#define  ADC_JSQ4_3                     ((uint32_t)0x00040000)        /* Bit 3 */
+#define  ADC_JSQ4_4                     ((uint32_t)0x00080000)        /* Bit 4 */
+
+#define  ADC_JL                         ((uint32_t)0x00300000)        /* JL[1:0] bits (Injected Sequence length) */
+#define  ADC_JL_0                       ((uint32_t)0x00100000)        /* Bit 0 */
+#define  ADC_JL_1                       ((uint32_t)0x00200000)        /* Bit 1 */
+
+/*******************  Bit definition for ADC_IDATAR1 register  *******************/
+#define  ADC_IDATAR1_JDATA              ((uint16_t)0xFFFF)            /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR2 register  *******************/
+#define  ADC_IDATAR2_JDATA              ((uint16_t)0xFFFF)            /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR3 register  *******************/
+#define  ADC_IDATAR3_JDATA              ((uint16_t)0xFFFF)            /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR4 register  *******************/
+#define  ADC_IDATAR4_JDATA              ((uint16_t)0xFFFF)            /* Injected data */
+
+/********************  Bit definition for ADC_RDATAR register  ********************/
+#define  ADC_RDATAR_DATA                ((uint32_t)0x0000FFFF)        /* Regular data */
+#define  ADC_RDATAR_ADC2DATA            ((uint32_t)0xFFFF0000)        /* ADC2 data */
+
+/******************************************************************************/
+/*                            Backup registers                                */
+/******************************************************************************/
+
+/*******************  Bit definition for BKP_DATAR1 register  ********************/
+#define  BKP_DATAR1_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR2 register  ********************/
+#define  BKP_DATAR2_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR3 register  ********************/
+#define  BKP_DATAR3_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR4 register  ********************/
+#define  BKP_DATAR4_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR5 register  ********************/
+#define  BKP_DATAR5_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR6 register  ********************/
+#define  BKP_DATAR6_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR7 register  ********************/
+#define  BKP_DATAR7_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR8 register  ********************/
+#define  BKP_DATAR8_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR9 register  ********************/
+#define  BKP_DATAR9_D                           ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR10 register  *******************/
+#define  BKP_DATAR10_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR11 register  *******************/
+#define  BKP_DATAR11_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR12 register  *******************/
+#define  BKP_DATAR12_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR13 register  *******************/
+#define  BKP_DATAR13_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR14 register  *******************/
+#define  BKP_DATAR14_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR15 register  *******************/
+#define  BKP_DATAR15_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR16 register  *******************/
+#define  BKP_DATAR16_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR17 register  *******************/
+#define  BKP_DATAR17_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/******************  Bit definition for BKP_DATAR18 register  ********************/
+#define  BKP_DATAR18_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR19 register  *******************/
+#define  BKP_DATAR19_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR20 register  *******************/
+#define  BKP_DATAR20_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR21 register  *******************/
+#define  BKP_DATAR21_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR22 register  *******************/
+#define  BKP_DATAR22_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR23 register  *******************/
+#define  BKP_DATAR23_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR24 register  *******************/
+#define  BKP_DATAR24_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR25 register  *******************/
+#define  BKP_DATAR25_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR26 register  *******************/
+#define  BKP_DATAR26_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR27 register  *******************/
+#define  BKP_DATAR27_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR28 register  *******************/
+#define  BKP_DATAR28_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR29 register  *******************/
+#define  BKP_DATAR29_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR30 register  *******************/
+#define  BKP_DATAR30_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR31 register  *******************/
+#define  BKP_DATAR31_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR32 register  *******************/
+#define  BKP_DATAR32_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR33 register  *******************/
+#define  BKP_DATAR33_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR34 register  *******************/
+#define  BKP_DATAR34_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR35 register  *******************/
+#define  BKP_DATAR35_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR36 register  *******************/
+#define  BKP_DATAR36_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR37 register  *******************/
+#define  BKP_DATAR37_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR38 register  *******************/
+#define  BKP_DATAR38_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR39 register  *******************/
+#define  BKP_DATAR39_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR40 register  *******************/
+#define  BKP_DATAR40_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR41 register  *******************/
+#define  BKP_DATAR41_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR42 register  *******************/
+#define  BKP_DATAR42_D                          ((uint16_t)0xFFFF)     /* Backup data */
+
+/******************  Bit definition for BKP_OCTLR register  *******************/
+#define  BKP_CAL                                ((uint16_t)0x007F)     /* Calibration value */
+#define  BKP_CCO                                ((uint16_t)0x0080)     /* Calibration Clock Output */
+#define  BKP_ASOE                               ((uint16_t)0x0100)     /* Alarm or Second Output Enable */
+#define  BKP_ASOS                               ((uint16_t)0x0200)     /* Alarm or Second Output Selection */
+
+/********************  Bit definition for BKP_TPCTLR register  ********************/
+#define  BKP_TPE                                ((uint8_t)0x01)        /* TAMPER pin enable */
+#define  BKP_TPAL                               ((uint8_t)0x02)        /* TAMPER pin active level */
+
+/*******************  Bit definition for BKP_TPCSR register  ********************/
+#define  BKP_CTE                                ((uint16_t)0x0001)     /* Clear Tamper event */
+#define  BKP_CTI                                ((uint16_t)0x0002)     /* Clear Tamper Interrupt */
+#define  BKP_TPIE                               ((uint16_t)0x0004)     /* TAMPER Pin interrupt enable */
+#define  BKP_TEF                                ((uint16_t)0x0100)     /* Tamper Event Flag */
+#define  BKP_TIF                                ((uint16_t)0x0200)     /* Tamper Interrupt Flag */
+
+/******************************************************************************/
+/*                         Controller Area Network                            */
+/******************************************************************************/
+
+/*******************  Bit definition for CAN_CTLR register  ********************/
+#define  CAN_CTLR_INRQ                       ((uint16_t)0x0001)            /* Initialization Request */
+#define  CAN_CTLR_SLEEP                      ((uint16_t)0x0002)            /* Sleep Mode Request */
+#define  CAN_CTLR_TXFP                       ((uint16_t)0x0004)            /* Transmit FIFO Priority */
+#define  CAN_CTLR_RFLM                       ((uint16_t)0x0008)            /* Receive FIFO Locked Mode */
+#define  CAN_CTLR_NART                       ((uint16_t)0x0010)            /* No Automatic Retransmission */
+#define  CAN_CTLR_AWUM                       ((uint16_t)0x0020)            /* Automatic Wakeup Mode */
+#define  CAN_CTLR_ABOM                       ((uint16_t)0x0040)            /* Automatic Bus-Off Management */
+#define  CAN_CTLR_TTCM                       ((uint16_t)0x0080)            /* Time Triggered Communication Mode */
+#define  CAN_CTLR_RESET                      ((uint16_t)0x8000)            /* CAN software master reset */
+
+/*******************  Bit definition for CAN_STATR register  ********************/
+#define  CAN_STATR_INAK                      ((uint16_t)0x0001)            /* Initialization Acknowledge */
+#define  CAN_STATR_SLAK                      ((uint16_t)0x0002)            /* Sleep Acknowledge */
+#define  CAN_STATR_ERRI                      ((uint16_t)0x0004)            /* Error Interrupt */
+#define  CAN_STATR_WKUI                      ((uint16_t)0x0008)            /* Wakeup Interrupt */
+#define  CAN_STATR_SLAKI                     ((uint16_t)0x0010)            /* Sleep Acknowledge Interrupt */
+#define  CAN_STATR_TXM                       ((uint16_t)0x0100)            /* Transmit Mode */
+#define  CAN_STATR_RXM                       ((uint16_t)0x0200)            /* Receive Mode */
+#define  CAN_STATR_SAMP                      ((uint16_t)0x0400)            /* Last Sample Point */
+#define  CAN_STATR_RX                        ((uint16_t)0x0800)            /* CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSTATR register  ********************/
+#define  CAN_TSTATR_RQCP0                    ((uint32_t)0x00000001)        /* Request Completed Mailbox0 */
+#define  CAN_TSTATR_TXOK0                    ((uint32_t)0x00000002)        /* Transmission OK of Mailbox0 */
+#define  CAN_TSTATR_ALST0                    ((uint32_t)0x00000004)        /* Arbitration Lost for Mailbox0 */
+#define  CAN_TSTATR_TERR0                    ((uint32_t)0x00000008)        /* Transmission Error of Mailbox0 */
+#define  CAN_TSTATR_ABRQ0                    ((uint32_t)0x00000080)        /* Abort Request for Mailbox0 */
+#define  CAN_TSTATR_RQCP1                    ((uint32_t)0x00000100)        /* Request Completed Mailbox1 */
+#define  CAN_TSTATR_TXOK1                    ((uint32_t)0x00000200)        /* Transmission OK of Mailbox1 */
+#define  CAN_TSTATR_ALST1                    ((uint32_t)0x00000400)        /* Arbitration Lost for Mailbox1 */
+#define  CAN_TSTATR_TERR1                    ((uint32_t)0x00000800)        /* Transmission Error of Mailbox1 */
+#define  CAN_TSTATR_ABRQ1                    ((uint32_t)0x00008000)        /* Abort Request for Mailbox 1 */
+#define  CAN_TSTATR_RQCP2                    ((uint32_t)0x00010000)        /* Request Completed Mailbox2 */
+#define  CAN_TSTATR_TXOK2                    ((uint32_t)0x00020000)        /* Transmission OK of Mailbox 2 */
+#define  CAN_TSTATR_ALST2                    ((uint32_t)0x00040000)        /* Arbitration Lost for mailbox 2 */
+#define  CAN_TSTATR_TERR2                    ((uint32_t)0x00080000)        /* Transmission Error of Mailbox 2 */
+#define  CAN_TSTATR_ABRQ2                    ((uint32_t)0x00800000)        /* Abort Request for Mailbox 2 */
+#define  CAN_TSTATR_CODE                     ((uint32_t)0x03000000)        /* Mailbox Code */
+
+#define  CAN_TSTATR_TME                      ((uint32_t)0x1C000000)        /* TME[2:0] bits */
+#define  CAN_TSTATR_TME0                     ((uint32_t)0x04000000)        /* Transmit Mailbox 0 Empty */
+#define  CAN_TSTATR_TME1                     ((uint32_t)0x08000000)        /* Transmit Mailbox 1 Empty */
+#define  CAN_TSTATR_TME2                     ((uint32_t)0x10000000)        /* Transmit Mailbox 2 Empty */
+
+#define  CAN_TSTATR_LOW                      ((uint32_t)0xE0000000)        /* LOW[2:0] bits */
+#define  CAN_TSTATR_LOW0                     ((uint32_t)0x20000000)        /* Lowest Priority Flag for Mailbox 0 */
+#define  CAN_TSTATR_LOW1                     ((uint32_t)0x40000000)        /* Lowest Priority Flag for Mailbox 1 */
+#define  CAN_TSTATR_LOW2                     ((uint32_t)0x80000000)        /* Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RFIFO0 register  *******************/
+#define  CAN_RFIFO0_FMP0                     ((uint8_t)0x03)               /* FIFO 0 Message Pending */
+#define  CAN_RFIFO0_FULL0                    ((uint8_t)0x08)               /* FIFO 0 Full */
+#define  CAN_RFIFO0_FOVR0                    ((uint8_t)0x10)               /* FIFO 0 Overrun */
+#define  CAN_RFIFO0_RFOM0                    ((uint8_t)0x20)               /* Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RFIFO1 register  *******************/
+#define  CAN_RFIFO1_FMP1                     ((uint8_t)0x03)               /* FIFO 1 Message Pending */
+#define  CAN_RFIFO1_FULL1                    ((uint8_t)0x08)               /* FIFO 1 Full */
+#define  CAN_RFIFO1_FOVR1                    ((uint8_t)0x10)               /* FIFO 1 Overrun */
+#define  CAN_RFIFO1_RFOM1                    ((uint8_t)0x20)               /* Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_INTENR register  *******************/
+#define  CAN_INTENR_TMEIE                    ((uint32_t)0x00000001)        /* Transmit Mailbox Empty Interrupt Enable */
+#define  CAN_INTENR_FMPIE0                   ((uint32_t)0x00000002)        /* FIFO Message Pending Interrupt Enable */
+#define  CAN_INTENR_FFIE0                    ((uint32_t)0x00000004)        /* FIFO Full Interrupt Enable */
+#define  CAN_INTENR_FOVIE0                   ((uint32_t)0x00000008)        /* FIFO Overrun Interrupt Enable */
+#define  CAN_INTENR_FMPIE1                   ((uint32_t)0x00000010)        /* FIFO Message Pending Interrupt Enable */
+#define  CAN_INTENR_FFIE1                    ((uint32_t)0x00000020)        /* FIFO Full Interrupt Enable */
+#define  CAN_INTENR_FOVIE1                   ((uint32_t)0x00000040)        /* FIFO Overrun Interrupt Enable */
+#define  CAN_INTENR_EWGIE                    ((uint32_t)0x00000100)        /* Error Warning Interrupt Enable */
+#define  CAN_INTENR_EPVIE                    ((uint32_t)0x00000200)        /* Error Passive Interrupt Enable */
+#define  CAN_INTENR_BOFIE                    ((uint32_t)0x00000400)        /* Bus-Off Interrupt Enable */
+#define  CAN_INTENR_LECIE                    ((uint32_t)0x00000800)        /* Last Error Code Interrupt Enable */
+#define  CAN_INTENR_ERRIE                    ((uint32_t)0x00008000)        /* Error Interrupt Enable */
+#define  CAN_INTENR_WKUIE                    ((uint32_t)0x00010000)        /* Wakeup Interrupt Enable */
+#define  CAN_INTENR_SLKIE                    ((uint32_t)0x00020000)        /* Sleep Interrupt Enable */
+
+/********************  Bit definition for CAN_ERRSR register  *******************/
+#define  CAN_ERRSR_EWGF                      ((uint32_t)0x00000001)        /* Error Warning Flag */
+#define  CAN_ERRSR_EPVF                      ((uint32_t)0x00000002)        /* Error Passive Flag */
+#define  CAN_ERRSR_BOFF                      ((uint32_t)0x00000004)        /* Bus-Off Flag */
+
+#define  CAN_ERRSR_LEC                       ((uint32_t)0x00000070)        /* LEC[2:0] bits (Last Error Code) */
+#define  CAN_ERRSR_LEC_0                     ((uint32_t)0x00000010)        /* Bit 0 */
+#define  CAN_ERRSR_LEC_1                     ((uint32_t)0x00000020)        /* Bit 1 */
+#define  CAN_ERRSR_LEC_2                     ((uint32_t)0x00000040)        /* Bit 2 */
+
+#define  CAN_ERRSR_TEC                       ((uint32_t)0x00FF0000)        /* Least significant byte of the 9-bit Transmit Error Counter */
+#define  CAN_ERRSR_REC                       ((uint32_t)0xFF000000)        /* Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTIMR register  ********************/
+#define  CAN_BTIMR_BRP                       ((uint32_t)0x000003FF)        /* Baud Rate Prescaler */
+#define  CAN_BTIMR_TS1                       ((uint32_t)0x000F0000)        /* Time Segment 1 */
+#define  CAN_BTIMR_TS2                       ((uint32_t)0x00700000)        /* Time Segment 2 */
+#define  CAN_BTIMR_SJW                       ((uint32_t)0x03000000)        /* Resynchronization Jump Width */
+#define  CAN_BTIMR_LBKM                      ((uint32_t)0x40000000)        /* Loop Back Mode (Debug) */
+#define  CAN_BTIMR_SILM                      ((uint32_t)0x80000000)        /* Silent Mode */
+
+/******************  Bit definition for CAN_TXMI0R register  ********************/
+#define  CAN_TXMI0R_TXRQ                     ((uint32_t)0x00000001)        /* Transmit Mailbox Request */
+#define  CAN_TXMI0R_RTR                      ((uint32_t)0x00000002)        /* Remote Transmission Request */
+#define  CAN_TXMI0R_IDE                      ((uint32_t)0x00000004)        /* Identifier Extension */
+#define  CAN_TXMI0R_EXID                     ((uint32_t)0x001FFFF8)        /* Extended Identifier */
+#define  CAN_TXMI0R_STID                     ((uint32_t)0xFFE00000)        /* Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TXMDT0R register  *******************/
+#define  CAN_TXMDT0R_DLC                     ((uint32_t)0x0000000F)        /* Data Length Code */
+#define  CAN_TXMDT0R_TGT                     ((uint32_t)0x00000100)        /* Transmit Global Time */
+#define  CAN_TXMDT0R_TIME                    ((uint32_t)0xFFFF0000)        /* Message Time Stamp */
+
+/******************  Bit definition for CAN_TXMDL0R register  *******************/
+#define  CAN_TXMDL0R_DATA0                   ((uint32_t)0x000000FF)        /* Data byte 0 */
+#define  CAN_TXMDL0R_DATA1                   ((uint32_t)0x0000FF00)        /* Data byte 1 */
+#define  CAN_TXMDL0R_DATA2                   ((uint32_t)0x00FF0000)        /* Data byte 2 */
+#define  CAN_TXMDL0R_DATA3                   ((uint32_t)0xFF000000)        /* Data byte 3 */
+
+/******************  Bit definition for CAN_TXMDH0R register  *******************/
+#define  CAN_TXMDH0R_DATA4                   ((uint32_t)0x000000FF)        /* Data byte 4 */
+#define  CAN_TXMDH0R_DATA5                   ((uint32_t)0x0000FF00)        /* Data byte 5 */
+#define  CAN_TXMDH0R_DATA6                   ((uint32_t)0x00FF0000)        /* Data byte 6 */
+#define  CAN_TXMDH0R_DATA7                   ((uint32_t)0xFF000000)        /* Data byte 7 */
+
+/*******************  Bit definition for CAN_TXMI1R register  *******************/
+#define  CAN_TXMI1R_TXRQ                     ((uint32_t)0x00000001)        /* Transmit Mailbox Request */
+#define  CAN_TXMI1R_RTR                      ((uint32_t)0x00000002)        /* Remote Transmission Request */
+#define  CAN_TXMI1R_IDE                      ((uint32_t)0x00000004)        /* Identifier Extension */
+#define  CAN_TXMI1R_EXID                     ((uint32_t)0x001FFFF8)        /* Extended Identifier */
+#define  CAN_TXMI1R_STID                     ((uint32_t)0xFFE00000)        /* Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TXMDT1R register  ******************/
+#define  CAN_TXMDT1R_DLC                     ((uint32_t)0x0000000F)        /* Data Length Code */
+#define  CAN_TXMDT1R_TGT                     ((uint32_t)0x00000100)        /* Transmit Global Time */
+#define  CAN_TXMDT1R_TIME                    ((uint32_t)0xFFFF0000)        /* Message Time Stamp */
+
+/*******************  Bit definition for CAN_TXMDL1R register  ******************/
+#define  CAN_TXMDL1R_DATA0                   ((uint32_t)0x000000FF)        /* Data byte 0 */
+#define  CAN_TXMDL1R_DATA1                   ((uint32_t)0x0000FF00)        /* Data byte 1 */
+#define  CAN_TXMDL1R_DATA2                   ((uint32_t)0x00FF0000)        /* Data byte 2 */
+#define  CAN_TXMDL1R_DATA3                   ((uint32_t)0xFF000000)        /* Data byte 3 */
+
+/*******************  Bit definition for CAN_TXMDH1R register  ******************/
+#define  CAN_TXMDH1R_DATA4                   ((uint32_t)0x000000FF)        /* Data byte 4 */
+#define  CAN_TXMDH1R_DATA5                   ((uint32_t)0x0000FF00)        /* Data byte 5 */
+#define  CAN_TXMDH1R_DATA6                   ((uint32_t)0x00FF0000)        /* Data byte 6 */
+#define  CAN_TXMDH1R_DATA7                   ((uint32_t)0xFF000000)        /* Data byte 7 */
+
+/*******************  Bit definition for CAN_TXMI2R register  *******************/
+#define  CAN_TXMI2R_TXRQ                     ((uint32_t)0x00000001)        /* Transmit Mailbox Request */
+#define  CAN_TXMI2R_RTR                      ((uint32_t)0x00000002)        /* Remote Transmission Request */
+#define  CAN_TXMI2R_IDE                      ((uint32_t)0x00000004)        /* Identifier Extension */
+#define  CAN_TXMI2R_EXID                     ((uint32_t)0x001FFFF8)        /* Extended identifier */
+#define  CAN_TXMI2R_STID                     ((uint32_t)0xFFE00000)        /* Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TXMDT2R register  ******************/  
+#define  CAN_TXMDT2R_DLC                     ((uint32_t)0x0000000F)        /* Data Length Code */
+#define  CAN_TXMDT2R_TGT                     ((uint32_t)0x00000100)        /* Transmit Global Time */
+#define  CAN_TXMDT2R_TIME                    ((uint32_t)0xFFFF0000)        /* Message Time Stamp */
+
+/*******************  Bit definition for CAN_TXMDL2R register  ******************/
+#define  CAN_TXMDL2R_DATA0                   ((uint32_t)0x000000FF)        /* Data byte 0 */
+#define  CAN_TXMDL2R_DATA1                   ((uint32_t)0x0000FF00)        /* Data byte 1 */
+#define  CAN_TXMDL2R_DATA2                   ((uint32_t)0x00FF0000)        /* Data byte 2 */
+#define  CAN_TXMDL2R_DATA3                   ((uint32_t)0xFF000000)        /* Data byte 3 */
+
+/*******************  Bit definition for CAN_TXMDH2R register  ******************/
+#define  CAN_TXMDH2R_DATA4                   ((uint32_t)0x000000FF)        /* Data byte 4 */
+#define  CAN_TXMDH2R_DATA5                   ((uint32_t)0x0000FF00)        /* Data byte 5 */
+#define  CAN_TXMDH2R_DATA6                   ((uint32_t)0x00FF0000)        /* Data byte 6 */
+#define  CAN_TXMDH2R_DATA7                   ((uint32_t)0xFF000000)        /* Data byte 7 */
+
+/*******************  Bit definition for CAN_RXMI0R register  *******************/
+#define  CAN_RXMI0R_RTR                      ((uint32_t)0x00000002)        /* Remote Transmission Request */
+#define  CAN_RXMI0R_IDE                      ((uint32_t)0x00000004)        /* Identifier Extension */
+#define  CAN_RXMI0R_EXID                     ((uint32_t)0x001FFFF8)        /* Extended Identifier */
+#define  CAN_RXMI0R_STID                     ((uint32_t)0xFFE00000)        /* Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RXMDT0R register  ******************/
+#define  CAN_RXMDT0R_DLC                     ((uint32_t)0x0000000F)        /* Data Length Code */
+#define  CAN_RXMDT0R_FMI                     ((uint32_t)0x0000FF00)        /* Filter Match Index */
+#define  CAN_RXMDT0R_TIME                    ((uint32_t)0xFFFF0000)        /* Message Time Stamp */
+
+/*******************  Bit definition for CAN_RXMDL0R register  ******************/
+#define  CAN_RXMDL0R_DATA0                   ((uint32_t)0x000000FF)        /* Data byte 0 */
+#define  CAN_RXMDL0R_DATA1                   ((uint32_t)0x0000FF00)        /* Data byte 1 */
+#define  CAN_RXMDL0R_DATA2                   ((uint32_t)0x00FF0000)        /* Data byte 2 */
+#define  CAN_RXMDL0R_DATA3                   ((uint32_t)0xFF000000)        /* Data byte 3 */
+
+/*******************  Bit definition for CAN_RXMDH0R register  ******************/
+#define  CAN_RXMDH0R_DATA4                   ((uint32_t)0x000000FF)        /* Data byte 4 */
+#define  CAN_RXMDH0R_DATA5                   ((uint32_t)0x0000FF00)        /* Data byte 5 */
+#define  CAN_RXMDH0R_DATA6                   ((uint32_t)0x00FF0000)        /* Data byte 6 */
+#define  CAN_RXMDH0R_DATA7                   ((uint32_t)0xFF000000)        /* Data byte 7 */
+
+/*******************  Bit definition for CAN_RXMI1R register  *******************/
+#define  CAN_RXMI1R_RTR                      ((uint32_t)0x00000002)        /* Remote Transmission Request */
+#define  CAN_RXMI1R_IDE                      ((uint32_t)0x00000004)        /* Identifier Extension */
+#define  CAN_RXMI1R_EXID                     ((uint32_t)0x001FFFF8)        /* Extended identifier */
+#define  CAN_RXMI1R_STID                     ((uint32_t)0xFFE00000)        /* Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RXMDT1R register  ******************/
+#define  CAN_RXMDT1R_DLC                     ((uint32_t)0x0000000F)        /* Data Length Code */
+#define  CAN_RXMDT1R_FMI                     ((uint32_t)0x0000FF00)        /* Filter Match Index */
+#define  CAN_RXMDT1R_TIME                    ((uint32_t)0xFFFF0000)        /* Message Time Stamp */
+
+/*******************  Bit definition for CAN_RXMDL1R register  ******************/
+#define  CAN_RXMDL1R_DATA0                   ((uint32_t)0x000000FF)        /* Data byte 0 */
+#define  CAN_RXMDL1R_DATA1                   ((uint32_t)0x0000FF00)        /* Data byte 1 */
+#define  CAN_RXMDL1R_DATA2                   ((uint32_t)0x00FF0000)        /* Data byte 2 */
+#define  CAN_RXMDL1R_DATA3                   ((uint32_t)0xFF000000)        /* Data byte 3 */
+
+/*******************  Bit definition for CAN_RXMDH1R register  ******************/
+#define  CAN_RXMDH1R_DATA4                   ((uint32_t)0x000000FF)        /* Data byte 4 */
+#define  CAN_RXMDH1R_DATA5                   ((uint32_t)0x0000FF00)        /* Data byte 5 */
+#define  CAN_RXMDH1R_DATA6                   ((uint32_t)0x00FF0000)        /* Data byte 6 */
+#define  CAN_RXMDH1R_DATA7                   ((uint32_t)0xFF000000)        /* Data byte 7 */
+
+/*******************  Bit definition for CAN_FCTLR register  ********************/
+#define  CAN_FCTLR_FINIT                     ((uint8_t)0x01)               /* Filter Init Mode */
+
+/*******************  Bit definition for CAN_FMCFGR register  *******************/
+#define  CAN_FMCFGR_FBM                      ((uint16_t)0x3FFF)            /* Filter Mode */
+#define  CAN_FMCFGR_FBM0                     ((uint16_t)0x0001)            /* Filter Init Mode bit 0 */
+#define  CAN_FMCFGR_FBM1                     ((uint16_t)0x0002)            /* Filter Init Mode bit 1 */
+#define  CAN_FMCFGR_FBM2                     ((uint16_t)0x0004)            /* Filter Init Mode bit 2 */
+#define  CAN_FMCFGR_FBM3                     ((uint16_t)0x0008)            /* Filter Init Mode bit 3 */
+#define  CAN_FMCFGR_FBM4                     ((uint16_t)0x0010)            /* Filter Init Mode bit 4 */
+#define  CAN_FMCFGR_FBM5                     ((uint16_t)0x0020)            /* Filter Init Mode bit 5 */
+#define  CAN_FMCFGR_FBM6                     ((uint16_t)0x0040)            /* Filter Init Mode bit 6 */
+#define  CAN_FMCFGR_FBM7                     ((uint16_t)0x0080)            /* Filter Init Mode bit 7 */
+#define  CAN_FMCFGR_FBM8                     ((uint16_t)0x0100)            /* Filter Init Mode bit 8 */
+#define  CAN_FMCFGR_FBM9                     ((uint16_t)0x0200)            /* Filter Init Mode bit 9 */
+#define  CAN_FMCFGR_FBM10                    ((uint16_t)0x0400)            /* Filter Init Mode bit 10 */
+#define  CAN_FMCFGR_FBM11                    ((uint16_t)0x0800)            /* Filter Init Mode bit 11 */
+#define  CAN_FMCFGR_FBM12                    ((uint16_t)0x1000)            /* Filter Init Mode bit 12 */
+#define  CAN_FMCFGR_FBM13                    ((uint16_t)0x2000)            /* Filter Init Mode bit 13 */
+
+/*******************  Bit definition for CAN_FSCFGR register  *******************/
+#define  CAN_FSCFGR_FSC                      ((uint16_t)0x3FFF)            /* Filter Scale Configuration */
+#define  CAN_FSCFGR_FSC0                     ((uint16_t)0x0001)            /* Filter Scale Configuration bit 0 */
+#define  CAN_FSCFGR_FSC1                     ((uint16_t)0x0002)            /* Filter Scale Configuration bit 1 */
+#define  CAN_FSCFGR_FSC2                     ((uint16_t)0x0004)            /* Filter Scale Configuration bit 2 */
+#define  CAN_FSCFGR_FSC3                     ((uint16_t)0x0008)            /* Filter Scale Configuration bit 3 */
+#define  CAN_FSCFGR_FSC4                     ((uint16_t)0x0010)            /* Filter Scale Configuration bit 4 */
+#define  CAN_FSCFGR_FSC5                     ((uint16_t)0x0020)            /* Filter Scale Configuration bit 5 */
+#define  CAN_FSCFGR_FSC6                     ((uint16_t)0x0040)            /* Filter Scale Configuration bit 6 */
+#define  CAN_FSCFGR_FSC7                     ((uint16_t)0x0080)            /* Filter Scale Configuration bit 7 */
+#define  CAN_FSCFGR_FSC8                     ((uint16_t)0x0100)            /* Filter Scale Configuration bit 8 */
+#define  CAN_FSCFGR_FSC9                     ((uint16_t)0x0200)            /* Filter Scale Configuration bit 9 */
+#define  CAN_FSCFGR_FSC10                    ((uint16_t)0x0400)            /* Filter Scale Configuration bit 10 */
+#define  CAN_FSCFGR_FSC11                    ((uint16_t)0x0800)            /* Filter Scale Configuration bit 11 */
+#define  CAN_FSCFGR_FSC12                    ((uint16_t)0x1000)            /* Filter Scale Configuration bit 12 */
+#define  CAN_FSCFGR_FSC13                    ((uint16_t)0x2000)            /* Filter Scale Configuration bit 13 */
+
+/******************  Bit definition for CAN_FAFIFOR register  *******************/
+#define  CAN_FAFIFOR_FFA                     ((uint16_t)0x3FFF)            /* Filter FIFO Assignment */
+#define  CAN_FAFIFOR_FFA0                    ((uint16_t)0x0001)            /* Filter FIFO Assignment for Filter 0 */
+#define  CAN_FAFIFOR_FFA1                    ((uint16_t)0x0002)            /* Filter FIFO Assignment for Filter 1 */
+#define  CAN_FAFIFOR_FFA2                    ((uint16_t)0x0004)            /* Filter FIFO Assignment for Filter 2 */
+#define  CAN_FAFIFOR_FFA3                    ((uint16_t)0x0008)            /* Filter FIFO Assignment for Filter 3 */
+#define  CAN_FAFIFOR_FFA4                    ((uint16_t)0x0010)            /* Filter FIFO Assignment for Filter 4 */
+#define  CAN_FAFIFOR_FFA5                    ((uint16_t)0x0020)            /* Filter FIFO Assignment for Filter 5 */
+#define  CAN_FAFIFOR_FFA6                    ((uint16_t)0x0040)            /* Filter FIFO Assignment for Filter 6 */
+#define  CAN_FAFIFOR_FFA7                    ((uint16_t)0x0080)            /* Filter FIFO Assignment for Filter 7 */
+#define  CAN_FAFIFOR_FFA8                    ((uint16_t)0x0100)            /* Filter FIFO Assignment for Filter 8 */
+#define  CAN_FAFIFOR_FFA9                    ((uint16_t)0x0200)            /* Filter FIFO Assignment for Filter 9 */
+#define  CAN_FAFIFOR_FFA10                   ((uint16_t)0x0400)            /* Filter FIFO Assignment for Filter 10 */
+#define  CAN_FAFIFOR_FFA11                   ((uint16_t)0x0800)            /* Filter FIFO Assignment for Filter 11 */
+#define  CAN_FAFIFOR_FFA12                   ((uint16_t)0x1000)            /* Filter FIFO Assignment for Filter 12 */
+#define  CAN_FAFIFOR_FFA13                   ((uint16_t)0x2000)            /* Filter FIFO Assignment for Filter 13 */
+
+/*******************  Bit definition for CAN_FWR register  *******************/
+#define  CAN_FWR_FACT                        ((uint16_t)0x3FFF)            /* Filter Active */
+#define  CAN_FWR_FACT0                       ((uint16_t)0x0001)            /* Filter 0 Active */
+#define  CAN_FWR_FACT1                       ((uint16_t)0x0002)            /* Filter 1 Active */
+#define  CAN_FWR_FACT2                       ((uint16_t)0x0004)            /* Filter 2 Active */
+#define  CAN_FWR_FACT3                       ((uint16_t)0x0008)            /* Filter 3 Active */
+#define  CAN_FWR_FACT4                       ((uint16_t)0x0010)            /* Filter 4 Active */
+#define  CAN_FWR_FACT5                       ((uint16_t)0x0020)            /* Filter 5 Active */
+#define  CAN_FWR_FACT6                       ((uint16_t)0x0040)            /* Filter 6 Active */
+#define  CAN_FWR_FACT7                       ((uint16_t)0x0080)            /* Filter 7 Active */
+#define  CAN_FWR_FACT8                       ((uint16_t)0x0100)            /* Filter 8 Active */
+#define  CAN_FWR_FACT9                       ((uint16_t)0x0200)            /* Filter 9 Active */
+#define  CAN_FWR_FACT10                      ((uint16_t)0x0400)            /* Filter 10 Active */
+#define  CAN_FWR_FACT11                      ((uint16_t)0x0800)            /* Filter 11 Active */
+#define  CAN_FWR_FACT12                      ((uint16_t)0x1000)            /* Filter 12 Active */
+#define  CAN_FWR_FACT13                      ((uint16_t)0x2000)            /* Filter 13 Active */
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /* Filter bit 0 */
+#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /* Filter bit 1 */
+#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /* Filter bit 2 */
+#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /* Filter bit 3 */
+#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /* Filter bit 4 */
+#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /* Filter bit 5 */
+#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /* Filter bit 6 */
+#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /* Filter bit 7 */
+#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /* Filter bit 8 */
+#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /* Filter bit 9 */
+#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /* Filter bit 10 */
+#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /* Filter bit 11 */
+#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /* Filter bit 12 */
+#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /* Filter bit 13 */
+#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /* Filter bit 14 */
+#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /* Filter bit 15 */
+#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /* Filter bit 16 */
+#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /* Filter bit 17 */
+#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /* Filter bit 18 */
+#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /* Filter bit 19 */
+#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /* Filter bit 20 */
+#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /* Filter bit 21 */
+#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /* Filter bit 22 */
+#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /* Filter bit 23 */
+#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /* Filter bit 24 */
+#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /* Filter bit 25 */
+#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /* Filter bit 26 */
+#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /* Filter bit 27 */
+#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /* Filter bit 28 */
+#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /* Filter bit 29 */
+#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /* Filter bit 30 */
+#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /* Filter bit 31 */
+
+
+
+/******************************************************************************/
+/*                          CRC Calculation Unit                              */
+/******************************************************************************/
+
+/*******************  Bit definition for CRC_DATAR register  *********************/
+#define  CRC_DATAR_DR                           ((uint32_t)0xFFFFFFFF) /* Data register bits */
+
+
+/*******************  Bit definition for CRC_IDATAR register  ********************/
+#define  CRC_IDR_IDATAR                         ((uint8_t)0xFF)        /* General-purpose 8-bit data register bits */
+
+
+/********************  Bit definition for CRC_CTLR register  ********************/
+#define  CRC_CTLR_RESET                         ((uint8_t)0x01)        /* RESET bit */
+
+/******************************************************************************/
+/*                      Digital to Analog Converter                           */
+/******************************************************************************/
+
+/********************  Bit definition for DAC_CTLR register  ********************/
+#define  DAC_EN1                          ((uint32_t)0x00000001)        /* DAC channel1 enable */
+#define  DAC_BOFF1                        ((uint32_t)0x00000002)        /* DAC channel1 output buffer disable */
+#define  DAC_TEN1                         ((uint32_t)0x00000004)        /* DAC channel1 Trigger enable */
+
+#define  DAC_TSEL1                        ((uint32_t)0x00000038)        /* TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define  DAC_TSEL1_0                      ((uint32_t)0x00000008)        /* Bit 0 */
+#define  DAC_TSEL1_1                      ((uint32_t)0x00000010)        /* Bit 1 */
+#define  DAC_TSEL1_2                      ((uint32_t)0x00000020)        /* Bit 2 */
+
+#define  DAC_WAVE1                        ((uint32_t)0x000000C0)        /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define  DAC_WAVE1_0                      ((uint32_t)0x00000040)        /* Bit 0 */
+#define  DAC_WAVE1_1                      ((uint32_t)0x00000080)        /* Bit 1 */
+
+#define  DAC_MAMP1                        ((uint32_t)0x00000F00)        /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define  DAC_MAMP1_0                      ((uint32_t)0x00000100)        /* Bit 0 */
+#define  DAC_MAMP1_1                      ((uint32_t)0x00000200)        /* Bit 1 */
+#define  DAC_MAMP1_2                      ((uint32_t)0x00000400)        /* Bit 2 */
+#define  DAC_MAMP1_3                      ((uint32_t)0x00000800)        /* Bit 3 */
+
+#define  DAC_DMAEN1                       ((uint32_t)0x00001000)        /* DAC channel1 DMA enable */
+#define  DAC_EN2                          ((uint32_t)0x00010000)        /* DAC channel2 enable */
+#define  DAC_BOFF2                        ((uint32_t)0x00020000)        /* DAC channel2 output buffer disable */
+#define  DAC_TEN2                         ((uint32_t)0x00040000)        /* DAC channel2 Trigger enable */
+
+#define  DAC_TSEL2                        ((uint32_t)0x00380000)        /* TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define  DAC_TSEL2_0                      ((uint32_t)0x00080000)        /* Bit 0 */
+#define  DAC_TSEL2_1                      ((uint32_t)0x00100000)        /* Bit 1 */
+#define  DAC_TSEL2_2                      ((uint32_t)0x00200000)        /* Bit 2 */
+
+#define  DAC_WAVE2                        ((uint32_t)0x00C00000)        /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define  DAC_WAVE2_0                      ((uint32_t)0x00400000)        /* Bit 0 */
+#define  DAC_WAVE2_1                      ((uint32_t)0x00800000)        /* Bit 1 */
+
+#define  DAC_MAMP2                        ((uint32_t)0x0F000000)        /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define  DAC_MAMP2_0                      ((uint32_t)0x01000000)        /* Bit 0 */
+#define  DAC_MAMP2_1                      ((uint32_t)0x02000000)        /* Bit 1 */
+#define  DAC_MAMP2_2                      ((uint32_t)0x04000000)        /* Bit 2 */
+#define  DAC_MAMP2_3                      ((uint32_t)0x08000000)        /* Bit 3 */
+
+#define  DAC_DMAEN2                       ((uint32_t)0x10000000)        /* DAC channel2 DMA enabled */
+
+/*****************  Bit definition for DAC_SWTR register  ******************/
+#define  DAC_SWTRIG1                      ((uint8_t)0x01)               /* DAC channel1 software trigger */
+#define  DAC_SWTRIG2                      ((uint8_t)0x02)               /* DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_R12BDHR1 register  ******************/
+#define  DAC_DHR12R1                      ((uint16_t)0x0FFF)            /* DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_L12BDHR1 register  ******************/
+#define  DAC_DHR12L1                      ((uint16_t)0xFFF0)            /* DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_R8BDHR1 register  ******************/
+#define  DAC_DHR8R1                       ((uint8_t)0xFF)               /* DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_R12BDHR2 register  ******************/
+#define  DAC_DHR12R2                      ((uint16_t)0x0FFF)            /* DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_L12BDHR2 register  ******************/
+#define  DAC_DHR12L2                      ((uint16_t)0xFFF0)            /* DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_R8BDHR2 register  ******************/
+#define  DAC_DHR8R2                       ((uint8_t)0xFF)               /* DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_RD12BDHR register  ******************/
+#define  DAC_RD12BDHR_DACC1DHR            ((uint32_t)0x00000FFF)        /* DAC channel1 12-bit Right aligned data */
+#define  DAC_RD12BDHR_DACC2DHR            ((uint32_t)0x0FFF0000)        /* DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_LD12BDHR register  ******************/
+#define  DAC_LD12BDHR_DACC1DHR            ((uint32_t)0x0000FFF0)        /* DAC channel1 12-bit Left aligned data */
+#define  DAC_LD12BDHR_DACC2DHR            ((uint32_t)0xFFF00000)        /* DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_RD8BDHR register  ******************/
+#define  DAC_RD8BDHR_DACC1DHR             ((uint16_t)0x00FF)            /* DAC channel1 8-bit Right aligned data */
+#define  DAC_RD8BDHR_DACC2DHR             ((uint16_t)0xFF00)            /* DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define  DAC_DACC1DOR                     ((uint16_t)0x0FFF)            /* DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define  DAC_DACC2DOR                     ((uint16_t)0x0FFF)            /* DAC channel2 data output */
+
+/******************************************************************************/
+/*                             DMA Controller                                 */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_INTFR register  ********************/
+#define  DMA_GIF1                           ((uint32_t)0x00000001)        /* Channel 1 Global interrupt flag */
+#define  DMA_TCIF1                          ((uint32_t)0x00000002)        /* Channel 1 Transfer Complete flag */
+#define  DMA_HTIF1                          ((uint32_t)0x00000004)        /* Channel 1 Half Transfer flag */
+#define  DMA_TEIF1                          ((uint32_t)0x00000008)        /* Channel 1 Transfer Error flag */
+#define  DMA_GIF2                           ((uint32_t)0x00000010)        /* Channel 2 Global interrupt flag */
+#define  DMA_TCIF2                          ((uint32_t)0x00000020)        /* Channel 2 Transfer Complete flag */
+#define  DMA_HTIF2                          ((uint32_t)0x00000040)        /* Channel 2 Half Transfer flag */
+#define  DMA_TEIF2                          ((uint32_t)0x00000080)        /* Channel 2 Transfer Error flag */
+#define  DMA_GIF3                           ((uint32_t)0x00000100)        /* Channel 3 Global interrupt flag */
+#define  DMA_TCIF3                          ((uint32_t)0x00000200)        /* Channel 3 Transfer Complete flag */
+#define  DMA_HTIF3                          ((uint32_t)0x00000400)        /* Channel 3 Half Transfer flag */
+#define  DMA_TEIF3                          ((uint32_t)0x00000800)        /* Channel 3 Transfer Error flag */
+#define  DMA_GIF4                           ((uint32_t)0x00001000)        /* Channel 4 Global interrupt flag */
+#define  DMA_TCIF4                          ((uint32_t)0x00002000)        /* Channel 4 Transfer Complete flag */
+#define  DMA_HTIF4                          ((uint32_t)0x00004000)        /* Channel 4 Half Transfer flag */
+#define  DMA_TEIF4                          ((uint32_t)0x00008000)        /* Channel 4 Transfer Error flag */
+#define  DMA_GIF5                           ((uint32_t)0x00010000)        /* Channel 5 Global interrupt flag */
+#define  DMA_TCIF5                          ((uint32_t)0x00020000)        /* Channel 5 Transfer Complete flag */
+#define  DMA_HTIF5                          ((uint32_t)0x00040000)        /* Channel 5 Half Transfer flag */
+#define  DMA_TEIF5                          ((uint32_t)0x00080000)        /* Channel 5 Transfer Error flag */
+#define  DMA_GIF6                           ((uint32_t)0x00100000)        /* Channel 6 Global interrupt flag */
+#define  DMA_TCIF6                          ((uint32_t)0x00200000)        /* Channel 6 Transfer Complete flag */
+#define  DMA_HTIF6                          ((uint32_t)0x00400000)        /* Channel 6 Half Transfer flag */
+#define  DMA_TEIF6                          ((uint32_t)0x00800000)        /* Channel 6 Transfer Error flag */
+#define  DMA_GIF7                           ((uint32_t)0x01000000)        /* Channel 7 Global interrupt flag */
+#define  DMA_TCIF7                          ((uint32_t)0x02000000)        /* Channel 7 Transfer Complete flag */
+#define  DMA_HTIF7                          ((uint32_t)0x04000000)        /* Channel 7 Half Transfer flag */
+#define  DMA_TEIF7                          ((uint32_t)0x08000000)        /* Channel 7 Transfer Error flag */
+
+#define  DMA_GIF8                           ((uint32_t)0x00000001)        /* Channel 8 Global interrupt flag */
+#define  DMA_TCIF8                          ((uint32_t)0x00000002)        /* Channel 8 Transfer Complete flag */
+#define  DMA_HTIF8                          ((uint32_t)0x00000004)        /* Channel 8 Half Transfer flag */
+#define  DMA_TEIF8                          ((uint32_t)0x00000008)        /* Channel 8 Transfer Error flag */
+#define  DMA_GIF9                           ((uint32_t)0x00000010)        /* Channel 9 Global interrupt flag */
+#define  DMA_TCIF9                          ((uint32_t)0x00000020)        /* Channel 9 Transfer Complete flag */
+#define  DMA_HTIF9                          ((uint32_t)0x00000040)        /* Channel 9 Half Transfer flag */
+#define  DMA_TEIF9                          ((uint32_t)0x00000080)        /* Channel 9 Transfer Error flag */
+#define  DMA_GIF10                          ((uint32_t)0x00000100)        /* Channel 10 Global interrupt flag */
+#define  DMA_TCIF10                         ((uint32_t)0x00000200)        /* Channel 10 Transfer Complete flag */
+#define  DMA_HTIF10                         ((uint32_t)0x00000400)        /* Channel 10 Half Transfer flag */
+#define  DMA_TEIF10                         ((uint32_t)0x00000800)        /* Channel 10 Transfer Error flag */
+#define  DMA_GIF11                          ((uint32_t)0x00001000)        /* Channel 11 Global interrupt flag */
+#define  DMA_TCIF11                         ((uint32_t)0x00002000)        /* Channel 11 Transfer Complete flag */
+#define  DMA_HTIF11                         ((uint32_t)0x00004000)        /* Channel 11 Half Transfer flag */
+#define  DMA_TEIF11                         ((uint32_t)0x00008000)        /* Channel 11 Transfer Error flag */
+
+/*******************  Bit definition for DMA_INTFCR register  *******************/
+#define  DMA_CGIF1                          ((uint32_t)0x00000001)        /* Channel 1 Global interrupt clear */
+#define  DMA_CTCIF1                         ((uint32_t)0x00000002)        /* Channel 1 Transfer Complete clear */
+#define  DMA_CHTIF1                         ((uint32_t)0x00000004)        /* Channel 1 Half Transfer clear */
+#define  DMA_CTEIF1                         ((uint32_t)0x00000008)        /* Channel 1 Transfer Error clear */
+#define  DMA_CGIF2                          ((uint32_t)0x00000010)        /* Channel 2 Global interrupt clear */
+#define  DMA_CTCIF2                         ((uint32_t)0x00000020)        /* Channel 2 Transfer Complete clear */
+#define  DMA_CHTIF2                         ((uint32_t)0x00000040)        /* Channel 2 Half Transfer clear */
+#define  DMA_CTEIF2                         ((uint32_t)0x00000080)        /* Channel 2 Transfer Error clear */
+#define  DMA_CGIF3                          ((uint32_t)0x00000100)        /* Channel 3 Global interrupt clear */
+#define  DMA_CTCIF3                         ((uint32_t)0x00000200)        /* Channel 3 Transfer Complete clear */
+#define  DMA_CHTIF3                         ((uint32_t)0x00000400)        /* Channel 3 Half Transfer clear */
+#define  DMA_CTEIF3                         ((uint32_t)0x00000800)        /* Channel 3 Transfer Error clear */
+#define  DMA_CGIF4                          ((uint32_t)0x00001000)        /* Channel 4 Global interrupt clear */
+#define  DMA_CTCIF4                         ((uint32_t)0x00002000)        /* Channel 4 Transfer Complete clear */
+#define  DMA_CHTIF4                         ((uint32_t)0x00004000)        /* Channel 4 Half Transfer clear */
+#define  DMA_CTEIF4                         ((uint32_t)0x00008000)        /* Channel 4 Transfer Error clear */
+#define  DMA_CGIF5                          ((uint32_t)0x00010000)        /* Channel 5 Global interrupt clear */
+#define  DMA_CTCIF5                         ((uint32_t)0x00020000)        /* Channel 5 Transfer Complete clear */
+#define  DMA_CHTIF5                         ((uint32_t)0x00040000)        /* Channel 5 Half Transfer clear */
+#define  DMA_CTEIF5                         ((uint32_t)0x00080000)        /* Channel 5 Transfer Error clear */
+#define  DMA_CGIF6                          ((uint32_t)0x00100000)        /* Channel 6 Global interrupt clear */
+#define  DMA_CTCIF6                         ((uint32_t)0x00200000)        /* Channel 6 Transfer Complete clear */
+#define  DMA_CHTIF6                         ((uint32_t)0x00400000)        /* Channel 6 Half Transfer clear */
+#define  DMA_CTEIF6                         ((uint32_t)0x00800000)        /* Channel 6 Transfer Error clear */
+#define  DMA_CGIF7                          ((uint32_t)0x01000000)        /* Channel 7 Global interrupt clear */
+#define  DMA_CTCIF7                         ((uint32_t)0x02000000)        /* Channel 7 Transfer Complete clear */
+#define  DMA_CHTIF7                         ((uint32_t)0x04000000)        /* Channel 7 Half Transfer clear */
+#define  DMA_CTEIF7                         ((uint32_t)0x08000000)        /* Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CFGR1 register  *******************/
+#define  DMA_CFGR1_EN                       ((uint16_t)0x0001)            /* Channel enable*/
+#define  DMA_CFGR1_TCIE                     ((uint16_t)0x0002)            /* Transfer complete interrupt enable */
+#define  DMA_CFGR1_HTIE                     ((uint16_t)0x0004)            /* Half Transfer interrupt enable */
+#define  DMA_CFGR1_TEIE                     ((uint16_t)0x0008)            /* Transfer error interrupt enable */
+#define  DMA_CFGR1_DIR                      ((uint16_t)0x0010)            /* Data transfer direction */
+#define  DMA_CFGR1_CIRC                     ((uint16_t)0x0020)            /* Circular mode */
+#define  DMA_CFGR1_PINC                     ((uint16_t)0x0040)            /* Peripheral increment mode */
+#define  DMA_CFGR1_MINC                     ((uint16_t)0x0080)            /* Memory increment mode */
+
+#define  DMA_CFGR1_PSIZE                    ((uint16_t)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CFGR1_PSIZE_0                  ((uint16_t)0x0100)            /* Bit 0 */
+#define  DMA_CFGR1_PSIZE_1                  ((uint16_t)0x0200)            /* Bit 1 */
+
+#define  DMA_CFGR1_MSIZE                    ((uint16_t)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
+#define  DMA_CFGR1_MSIZE_0                  ((uint16_t)0x0400)            /* Bit 0 */
+#define  DMA_CFGR1_MSIZE_1                  ((uint16_t)0x0800)            /* Bit 1 */
+
+#define  DMA_CFGR1_PL                       ((uint16_t)0x3000)            /* PL[1:0] bits(Channel Priority level) */
+#define  DMA_CFGR1_PL_0                     ((uint16_t)0x1000)            /* Bit 0 */
+#define  DMA_CFGR1_PL_1                     ((uint16_t)0x2000)            /* Bit 1 */
+
+#define  DMA_CFGR1_MEM2MEM                  ((uint16_t)0x4000)            /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFGR2 register  *******************/
+#define  DMA_CFGR2_EN                       ((uint16_t)0x0001)            /* Channel enable */
+#define  DMA_CFGR2_TCIE                     ((uint16_t)0x0002)            /* Transfer complete interrupt enable */
+#define  DMA_CFGR2_HTIE                     ((uint16_t)0x0004)            /* Half Transfer interrupt enable */
+#define  DMA_CFGR2_TEIE                     ((uint16_t)0x0008)            /* Transfer error interrupt enable */
+#define  DMA_CFGR2_DIR                      ((uint16_t)0x0010)            /* Data transfer direction */
+#define  DMA_CFGR2_CIRC                     ((uint16_t)0x0020)            /* Circular mode */
+#define  DMA_CFGR2_PINC                     ((uint16_t)0x0040)            /* Peripheral increment mode */
+#define  DMA_CFGR2_MINC                     ((uint16_t)0x0080)            /* Memory increment mode */
+
+#define  DMA_CFGR2_PSIZE                    ((uint16_t)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CFGR2_PSIZE_0                  ((uint16_t)0x0100)            /* Bit 0 */
+#define  DMA_CFGR2_PSIZE_1                  ((uint16_t)0x0200)            /* Bit 1 */
+
+#define  DMA_CFGR2_MSIZE                    ((uint16_t)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
+#define  DMA_CFGR2_MSIZE_0                  ((uint16_t)0x0400)            /* Bit 0 */
+#define  DMA_CFGR2_MSIZE_1                  ((uint16_t)0x0800)            /* Bit 1 */
+
+#define  DMA_CFGR2_PL                       ((uint16_t)0x3000)            /* PL[1:0] bits (Channel Priority level) */
+#define  DMA_CFGR2_PL_0                     ((uint16_t)0x1000)            /* Bit 0 */
+#define  DMA_CFGR2_PL_1                     ((uint16_t)0x2000)            /* Bit 1 */
+
+#define  DMA_CFGR2_MEM2MEM                  ((uint16_t)0x4000)            /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFGR3 register  *******************/
+#define  DMA_CFGR3_EN                       ((uint16_t)0x0001)            /* Channel enable */
+#define  DMA_CFGR3_TCIE                     ((uint16_t)0x0002)            /* Transfer complete interrupt enable */
+#define  DMA_CFGR3_HTIE                     ((uint16_t)0x0004)            /* Half Transfer interrupt enable */
+#define  DMA_CFGR3_TEIE                     ((uint16_t)0x0008)            /* Transfer error interrupt enable */
+#define  DMA_CFGR3_DIR                      ((uint16_t)0x0010)            /* Data transfer direction */
+#define  DMA_CFGR3_CIRC                     ((uint16_t)0x0020)            /* Circular mode */
+#define  DMA_CFGR3_PINC                     ((uint16_t)0x0040)            /* Peripheral increment mode */
+#define  DMA_CFGR3_MINC                     ((uint16_t)0x0080)            /* Memory increment mode */
+
+#define  DMA_CFGR3_PSIZE                    ((uint16_t)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CFGR3_PSIZE_0                  ((uint16_t)0x0100)            /* Bit 0 */
+#define  DMA_CFGR3_PSIZE_1                  ((uint16_t)0x0200)            /* Bit 1 */
+
+#define  DMA_CFGR3_MSIZE                    ((uint16_t)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
+#define  DMA_CFGR3_MSIZE_0                  ((uint16_t)0x0400)            /* Bit 0 */
+#define  DMA_CFGR3_MSIZE_1                  ((uint16_t)0x0800)            /* Bit 1 */
+
+#define  DMA_CFGR3_PL                       ((uint16_t)0x3000)            /* PL[1:0] bits (Channel Priority level) */
+#define  DMA_CFGR3_PL_0                     ((uint16_t)0x1000)            /* Bit 0 */
+#define  DMA_CFGR3_PL_1                     ((uint16_t)0x2000)            /* Bit 1 */
+
+#define  DMA_CFGR3_MEM2MEM                  ((uint16_t)0x4000)            /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFG4 register  *******************/
+#define  DMA_CFG4_EN                        ((uint16_t)0x0001)            /* Channel enable */
+#define  DMA_CFG4_TCIE                      ((uint16_t)0x0002)            /* Transfer complete interrupt enable */
+#define  DMA_CFG4_HTIE                      ((uint16_t)0x0004)            /* Half Transfer interrupt enable */
+#define  DMA_CFG4_TEIE                      ((uint16_t)0x0008)            /* Transfer error interrupt enable */
+#define  DMA_CFG4_DIR                       ((uint16_t)0x0010)            /* Data transfer direction */
+#define  DMA_CFG4_CIRC                      ((uint16_t)0x0020)            /* Circular mode */
+#define  DMA_CFG4_PINC                      ((uint16_t)0x0040)            /* Peripheral increment mode */
+#define  DMA_CFG4_MINC                      ((uint16_t)0x0080)            /* Memory increment mode */
+
+#define  DMA_CFG4_PSIZE                     ((uint16_t)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CFG4_PSIZE_0                   ((uint16_t)0x0100)            /* Bit 0 */
+#define  DMA_CFG4_PSIZE_1                   ((uint16_t)0x0200)            /* Bit 1 */
+             
+#define  DMA_CFG4_MSIZE                     ((uint16_t)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
+#define  DMA_CFG4_MSIZE_0                   ((uint16_t)0x0400)            /* Bit 0 */
+#define  DMA_CFG4_MSIZE_1                   ((uint16_t)0x0800)            /* Bit 1 */
+             
+#define  DMA_CFG4_PL                        ((uint16_t)0x3000)            /* PL[1:0] bits (Channel Priority level) */
+#define  DMA_CFG4_PL_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  DMA_CFG4_PL_1                      ((uint16_t)0x2000)            /* Bit 1 */
+             
+#define  DMA_CFG4_MEM2MEM                   ((uint16_t)0x4000)            /* Memory to memory mode */
+
+/******************  Bit definition for DMA_CFG5 register  *******************/
+#define  DMA_CFG5_EN                        ((uint16_t)0x0001)            /* Channel enable */
+#define  DMA_CFG5_TCIE                      ((uint16_t)0x0002)            /* Transfer complete interrupt enable */
+#define  DMA_CFG5_HTIE                      ((uint16_t)0x0004)            /* Half Transfer interrupt enable */
+#define  DMA_CFG5_TEIE                      ((uint16_t)0x0008)            /* Transfer error interrupt enable */
+#define  DMA_CFG5_DIR                       ((uint16_t)0x0010)            /* Data transfer direction */
+#define  DMA_CFG5_CIRC                      ((uint16_t)0x0020)            /* Circular mode */
+#define  DMA_CFG5_PINC                      ((uint16_t)0x0040)            /* Peripheral increment mode */
+#define  DMA_CFG5_MINC                      ((uint16_t)0x0080)            /* Memory increment mode */
+             
+#define  DMA_CFG5_PSIZE                     ((uint16_t)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CFG5_PSIZE_0                   ((uint16_t)0x0100)            /* Bit 0 */
+#define  DMA_CFG5_PSIZE_1                   ((uint16_t)0x0200)            /* Bit 1 */
+             
+#define  DMA_CFG5_MSIZE                     ((uint16_t)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
+#define  DMA_CFG5_MSIZE_0                   ((uint16_t)0x0400)            /* Bit 0 */
+#define  DMA_CFG5_MSIZE_1                   ((uint16_t)0x0800)            /* Bit 1 */
+             
+#define  DMA_CFG5_PL                        ((uint16_t)0x3000)            /* PL[1:0] bits (Channel Priority level) */
+#define  DMA_CFG5_PL_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  DMA_CFG5_PL_1                      ((uint16_t)0x2000)            /* Bit 1 */
+             
+#define  DMA_CFG5_MEM2MEM                   ((uint16_t)0x4000)            /* Memory to memory mode enable */
+
+/*******************  Bit definition for DMA_CFG6 register  *******************/
+#define  DMA_CFG6_EN                        ((uint16_t)0x0001)            /* Channel enable */
+#define  DMA_CFG6_TCIE                      ((uint16_t)0x0002)            /* Transfer complete interrupt enable */
+#define  DMA_CFG6_HTIE                      ((uint16_t)0x0004)            /* Half Transfer interrupt enable */
+#define  DMA_CFG6_TEIE                      ((uint16_t)0x0008)            /* Transfer error interrupt enable */
+#define  DMA_CFG6_DIR                       ((uint16_t)0x0010)            /* Data transfer direction */
+#define  DMA_CFG6_CIRC                      ((uint16_t)0x0020)            /* Circular mode */
+#define  DMA_CFG6_PINC                      ((uint16_t)0x0040)            /* Peripheral increment mode */
+#define  DMA_CFG6_MINC                      ((uint16_t)0x0080)            /* Memory increment mode */
+             
+#define  DMA_CFG6_PSIZE                     ((uint16_t)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CFG6_PSIZE_0                   ((uint16_t)0x0100)            /* Bit 0 */
+#define  DMA_CFG6_PSIZE_1                   ((uint16_t)0x0200)            /* Bit 1 */
+             
+#define  DMA_CFG6_MSIZE                     ((uint16_t)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
+#define  DMA_CFG6_MSIZE_0                   ((uint16_t)0x0400)            /* Bit 0 */
+#define  DMA_CFG6_MSIZE_1                   ((uint16_t)0x0800)            /* Bit 1 */
+             
+#define  DMA_CFG6_PL                        ((uint16_t)0x3000)            /* PL[1:0] bits (Channel Priority level) */
+#define  DMA_CFG6_PL_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  DMA_CFG6_PL_1                      ((uint16_t)0x2000)            /* Bit 1 */
+             
+#define  DMA_CFG6_MEM2MEM                   ((uint16_t)0x4000)            /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFG7 register  *******************/
+#define  DMA_CFG7_EN                        ((uint16_t)0x0001)            /* Channel enable */
+#define  DMA_CFG7_TCIE                      ((uint16_t)0x0002)            /* Transfer complete interrupt enable */
+#define  DMA_CFG7_HTIE                      ((uint16_t)0x0004)            /* Half Transfer interrupt enable */
+#define  DMA_CFG7_TEIE                      ((uint16_t)0x0008)            /* Transfer error interrupt enable */
+#define  DMA_CFG7_DIR                       ((uint16_t)0x0010)            /* Data transfer direction */
+#define  DMA_CFG7_CIRC                      ((uint16_t)0x0020)            /* Circular mode */
+#define  DMA_CFG7_PINC                      ((uint16_t)0x0040)            /* Peripheral increment mode */
+#define  DMA_CFG7_MINC                      ((uint16_t)0x0080)            /* Memory increment mode */
+             
+#define  DMA_CFG7_PSIZE                     ((uint16_t)0x0300)            /* PSIZE[1:0] bits (Peripheral size) */
+#define  DMA_CFG7_PSIZE_0                   ((uint16_t)0x0100)            /* Bit 0 */
+#define  DMA_CFG7_PSIZE_1                   ((uint16_t)0x0200)            /* Bit 1 */
+             
+#define  DMA_CFG7_MSIZE                     ((uint16_t)0x0C00)            /* MSIZE[1:0] bits (Memory size) */
+#define  DMA_CFG7_MSIZE_0                   ((uint16_t)0x0400)            /* Bit 0 */
+#define  DMA_CFG7_MSIZE_1                   ((uint16_t)0x0800)            /* Bit 1 */
+             
+#define  DMA_CFG7_PL                        ((uint16_t)0x3000)            /* PL[1:0] bits (Channel Priority level) */
+#define  DMA_CFG7_PL_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  DMA_CFG7_PL_1                      ((uint16_t)0x2000)            /* Bit 1 */
+             
+#define  DMA_CFG7_MEM2MEM                   ((uint16_t)0x4000)            /* Memory to memory mode enable */
+
+/******************  Bit definition for DMA_CNTR1 register  ******************/
+#define  DMA_CNTR1_NDT                      ((uint16_t)0xFFFF)            /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR2 register  ******************/
+#define  DMA_CNTR2_NDT                      ((uint16_t)0xFFFF)            /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR3 register  ******************/
+#define  DMA_CNTR3_NDT                      ((uint16_t)0xFFFF)            /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR4 register  ******************/
+#define  DMA_CNTR4_NDT                      ((uint16_t)0xFFFF)            /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR5 register  ******************/
+#define  DMA_CNTR5_NDT                      ((uint16_t)0xFFFF)            /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR6 register  ******************/
+#define  DMA_CNTR6_NDT                      ((uint16_t)0xFFFF)            /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR7 register  ******************/
+#define  DMA_CNTR7_NDT                      ((uint16_t)0xFFFF)            /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_PADDR1 register  *******************/
+#define  DMA_PADDR1_PA                      ((uint32_t)0xFFFFFFFF)        /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR2 register  *******************/
+#define  DMA_PADDR2_PA                      ((uint32_t)0xFFFFFFFF)        /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR3 register  *******************/
+#define  DMA_PADDR3_PA                      ((uint32_t)0xFFFFFFFF)        /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR4 register  *******************/
+#define  DMA_PADDR4_PA                      ((uint32_t)0xFFFFFFFF)        /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR5 register  *******************/
+#define  DMA_PADDR5_PA                      ((uint32_t)0xFFFFFFFF)        /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR6 register  *******************/
+#define  DMA_PADDR6_PA                      ((uint32_t)0xFFFFFFFF)        /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR7 register  *******************/
+#define  DMA_PADDR7_PA                      ((uint32_t)0xFFFFFFFF)        /* Peripheral Address */
+
+/******************  Bit definition for DMA_MADDR1 register  *******************/
+#define  DMA_MADDR1_MA                      ((uint32_t)0xFFFFFFFF)        /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR2 register  *******************/
+#define  DMA_MADDR2_MA                      ((uint32_t)0xFFFFFFFF)        /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR3 register  *******************/
+#define  DMA_MADDR3_MA                      ((uint32_t)0xFFFFFFFF)        /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR4 register  *******************/
+#define  DMA_MADDR4_MA                      ((uint32_t)0xFFFFFFFF)        /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR5 register  *******************/
+#define  DMA_MADDR5_MA                      ((uint32_t)0xFFFFFFFF)        /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR6 register  *******************/
+#define  DMA_MADDR6_MA                      ((uint32_t)0xFFFFFFFF)        /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR7 register  *******************/
+#define  DMA_MADDR7_MA                      ((uint32_t)0xFFFFFFFF)        /* Memory Address */
+
+
+/******************************************************************************/
+/*                    External Interrupt/Event Controller                     */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_INTENR register  *******************/
+#define  EXTI_INTENR_MR0                        ((uint32_t)0x00000001)        /* Interrupt Mask on line 0 */
+#define  EXTI_INTENR_MR1                        ((uint32_t)0x00000002)        /* Interrupt Mask on line 1 */
+#define  EXTI_INTENR_MR2                        ((uint32_t)0x00000004)        /* Interrupt Mask on line 2 */
+#define  EXTI_INTENR_MR3                        ((uint32_t)0x00000008)        /* Interrupt Mask on line 3 */
+#define  EXTI_INTENR_MR4                        ((uint32_t)0x00000010)        /* Interrupt Mask on line 4 */
+#define  EXTI_INTENR_MR5                        ((uint32_t)0x00000020)        /* Interrupt Mask on line 5 */
+#define  EXTI_INTENR_MR6                        ((uint32_t)0x00000040)        /* Interrupt Mask on line 6 */
+#define  EXTI_INTENR_MR7                        ((uint32_t)0x00000080)        /* Interrupt Mask on line 7 */
+#define  EXTI_INTENR_MR8                        ((uint32_t)0x00000100)        /* Interrupt Mask on line 8 */
+#define  EXTI_INTENR_MR9                        ((uint32_t)0x00000200)        /* Interrupt Mask on line 9 */
+#define  EXTI_INTENR_MR10                       ((uint32_t)0x00000400)        /* Interrupt Mask on line 10 */
+#define  EXTI_INTENR_MR11                       ((uint32_t)0x00000800)        /* Interrupt Mask on line 11 */
+#define  EXTI_INTENR_MR12                       ((uint32_t)0x00001000)        /* Interrupt Mask on line 12 */
+#define  EXTI_INTENR_MR13                       ((uint32_t)0x00002000)        /* Interrupt Mask on line 13 */
+#define  EXTI_INTENR_MR14                       ((uint32_t)0x00004000)        /* Interrupt Mask on line 14 */
+#define  EXTI_INTENR_MR15                       ((uint32_t)0x00008000)        /* Interrupt Mask on line 15 */
+#define  EXTI_INTENR_MR16                       ((uint32_t)0x00010000)        /* Interrupt Mask on line 16 */
+#define  EXTI_INTENR_MR17                       ((uint32_t)0x00020000)        /* Interrupt Mask on line 17 */
+#define  EXTI_INTENR_MR18                       ((uint32_t)0x00040000)        /* Interrupt Mask on line 18 */
+#define  EXTI_INTENR_MR19                       ((uint32_t)0x00080000)        /* Interrupt Mask on line 19 */
+
+/*******************  Bit definition for EXTI_EVENR register  *******************/
+#define  EXTI_EVENR_MR0                         ((uint32_t)0x00000001)        /* Event Mask on line 0 */
+#define  EXTI_EVENR_MR1                         ((uint32_t)0x00000002)        /* Event Mask on line 1 */
+#define  EXTI_EVENR_MR2                         ((uint32_t)0x00000004)        /* Event Mask on line 2 */
+#define  EXTI_EVENR_MR3                         ((uint32_t)0x00000008)        /* Event Mask on line 3 */
+#define  EXTI_EVENR_MR4                         ((uint32_t)0x00000010)        /* Event Mask on line 4 */
+#define  EXTI_EVENR_MR5                         ((uint32_t)0x00000020)        /* Event Mask on line 5 */
+#define  EXTI_EVENR_MR6                         ((uint32_t)0x00000040)        /* Event Mask on line 6 */
+#define  EXTI_EVENR_MR7                         ((uint32_t)0x00000080)        /* Event Mask on line 7 */
+#define  EXTI_EVENR_MR8                         ((uint32_t)0x00000100)        /* Event Mask on line 8 */
+#define  EXTI_EVENR_MR9                         ((uint32_t)0x00000200)        /* Event Mask on line 9 */
+#define  EXTI_EVENR_MR10                        ((uint32_t)0x00000400)        /* Event Mask on line 10 */
+#define  EXTI_EVENR_MR11                        ((uint32_t)0x00000800)        /* Event Mask on line 11 */
+#define  EXTI_EVENR_MR12                        ((uint32_t)0x00001000)        /* Event Mask on line 12 */
+#define  EXTI_EVENR_MR13                        ((uint32_t)0x00002000)        /* Event Mask on line 13 */
+#define  EXTI_EVENR_MR14                        ((uint32_t)0x00004000)        /* Event Mask on line 14 */
+#define  EXTI_EVENR_MR15                        ((uint32_t)0x00008000)        /* Event Mask on line 15 */
+#define  EXTI_EVENR_MR16                        ((uint32_t)0x00010000)        /* Event Mask on line 16 */
+#define  EXTI_EVENR_MR17                        ((uint32_t)0x00020000)        /* Event Mask on line 17 */
+#define  EXTI_EVENR_MR18                        ((uint32_t)0x00040000)        /* Event Mask on line 18 */
+#define  EXTI_EVENR_MR19                        ((uint32_t)0x00080000)        /* Event Mask on line 19 */
+
+/******************  Bit definition for EXTI_RTENR register  *******************/
+#define  EXTI_RTENR_TR0                         ((uint32_t)0x00000001)        /* Rising trigger event configuration bit of line 0 */
+#define  EXTI_RTENR_TR1                         ((uint32_t)0x00000002)        /* Rising trigger event configuration bit of line 1 */
+#define  EXTI_RTENR_TR2                         ((uint32_t)0x00000004)        /* Rising trigger event configuration bit of line 2 */
+#define  EXTI_RTENR_TR3                         ((uint32_t)0x00000008)        /* Rising trigger event configuration bit of line 3 */
+#define  EXTI_RTENR_TR4                         ((uint32_t)0x00000010)        /* Rising trigger event configuration bit of line 4 */
+#define  EXTI_RTENR_TR5                         ((uint32_t)0x00000020)        /* Rising trigger event configuration bit of line 5 */
+#define  EXTI_RTENR_TR6                         ((uint32_t)0x00000040)        /* Rising trigger event configuration bit of line 6 */
+#define  EXTI_RTENR_TR7                         ((uint32_t)0x00000080)        /* Rising trigger event configuration bit of line 7 */
+#define  EXTI_RTENR_TR8                         ((uint32_t)0x00000100)        /* Rising trigger event configuration bit of line 8 */
+#define  EXTI_RTENR_TR9                         ((uint32_t)0x00000200)        /* Rising trigger event configuration bit of line 9 */
+#define  EXTI_RTENR_TR10                        ((uint32_t)0x00000400)        /* Rising trigger event configuration bit of line 10 */
+#define  EXTI_RTENR_TR11                        ((uint32_t)0x00000800)        /* Rising trigger event configuration bit of line 11 */
+#define  EXTI_RTENR_TR12                        ((uint32_t)0x00001000)        /* Rising trigger event configuration bit of line 12 */
+#define  EXTI_RTENR_TR13                        ((uint32_t)0x00002000)        /* Rising trigger event configuration bit of line 13 */
+#define  EXTI_RTENR_TR14                        ((uint32_t)0x00004000)        /* Rising trigger event configuration bit of line 14 */
+#define  EXTI_RTENR_TR15                        ((uint32_t)0x00008000)        /* Rising trigger event configuration bit of line 15 */
+#define  EXTI_RTENR_TR16                        ((uint32_t)0x00010000)        /* Rising trigger event configuration bit of line 16 */
+#define  EXTI_RTENR_TR17                        ((uint32_t)0x00020000)        /* Rising trigger event configuration bit of line 17 */
+#define  EXTI_RTENR_TR18                        ((uint32_t)0x00040000)        /* Rising trigger event configuration bit of line 18 */
+#define  EXTI_RTENR_TR19                        ((uint32_t)0x00080000)        /* Rising trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_FTENR register  *******************/
+#define  EXTI_FTENR_TR0                         ((uint32_t)0x00000001)        /* Falling trigger event configuration bit of line 0 */
+#define  EXTI_FTENR_TR1                         ((uint32_t)0x00000002)        /* Falling trigger event configuration bit of line 1 */
+#define  EXTI_FTENR_TR2                         ((uint32_t)0x00000004)        /* Falling trigger event configuration bit of line 2 */
+#define  EXTI_FTENR_TR3                         ((uint32_t)0x00000008)        /* Falling trigger event configuration bit of line 3 */
+#define  EXTI_FTENR_TR4                         ((uint32_t)0x00000010)        /* Falling trigger event configuration bit of line 4 */
+#define  EXTI_FTENR_TR5                         ((uint32_t)0x00000020)        /* Falling trigger event configuration bit of line 5 */
+#define  EXTI_FTENR_TR6                         ((uint32_t)0x00000040)        /* Falling trigger event configuration bit of line 6 */
+#define  EXTI_FTENR_TR7                         ((uint32_t)0x00000080)        /* Falling trigger event configuration bit of line 7 */
+#define  EXTI_FTENR_TR8                         ((uint32_t)0x00000100)        /* Falling trigger event configuration bit of line 8 */
+#define  EXTI_FTENR_TR9                         ((uint32_t)0x00000200)        /* Falling trigger event configuration bit of line 9 */
+#define  EXTI_FTENR_TR10                        ((uint32_t)0x00000400)        /* Falling trigger event configuration bit of line 10 */
+#define  EXTI_FTENR_TR11                        ((uint32_t)0x00000800)        /* Falling trigger event configuration bit of line 11 */
+#define  EXTI_FTENR_TR12                        ((uint32_t)0x00001000)        /* Falling trigger event configuration bit of line 12 */
+#define  EXTI_FTENR_TR13                        ((uint32_t)0x00002000)        /* Falling trigger event configuration bit of line 13 */
+#define  EXTI_FTENR_TR14                        ((uint32_t)0x00004000)        /* Falling trigger event configuration bit of line 14 */
+#define  EXTI_FTENR_TR15                        ((uint32_t)0x00008000)        /* Falling trigger event configuration bit of line 15 */
+#define  EXTI_FTENR_TR16                        ((uint32_t)0x00010000)        /* Falling trigger event configuration bit of line 16 */
+#define  EXTI_FTENR_TR17                        ((uint32_t)0x00020000)        /* Falling trigger event configuration bit of line 17 */
+#define  EXTI_FTENR_TR18                        ((uint32_t)0x00040000)        /* Falling trigger event configuration bit of line 18 */
+#define  EXTI_FTENR_TR19                        ((uint32_t)0x00080000)        /* Falling trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_SWIEVR register  ******************/
+#define  EXTI_SWIEVR_SWIEVR0                    ((uint32_t)0x00000001)        /* Software Interrupt on line 0 */
+#define  EXTI_SWIEVR_SWIEVR1                    ((uint32_t)0x00000002)        /* Software Interrupt on line 1 */
+#define  EXTI_SWIEVR_SWIEVR2                    ((uint32_t)0x00000004)        /* Software Interrupt on line 2 */
+#define  EXTI_SWIEVR_SWIEVR3                    ((uint32_t)0x00000008)        /* Software Interrupt on line 3 */
+#define  EXTI_SWIEVR_SWIEVR4                    ((uint32_t)0x00000010)        /* Software Interrupt on line 4 */
+#define  EXTI_SWIEVR_SWIEVR5                    ((uint32_t)0x00000020)        /* Software Interrupt on line 5 */
+#define  EXTI_SWIEVR_SWIEVR6                    ((uint32_t)0x00000040)        /* Software Interrupt on line 6 */
+#define  EXTI_SWIEVR_SWIEVR7                    ((uint32_t)0x00000080)        /* Software Interrupt on line 7 */
+#define  EXTI_SWIEVR_SWIEVR8                    ((uint32_t)0x00000100)        /* Software Interrupt on line 8 */
+#define  EXTI_SWIEVR_SWIEVR9                    ((uint32_t)0x00000200)        /* Software Interrupt on line 9 */
+#define  EXTI_SWIEVR_SWIEVR10                   ((uint32_t)0x00000400)        /* Software Interrupt on line 10 */
+#define  EXTI_SWIEVR_SWIEVR11                   ((uint32_t)0x00000800)        /* Software Interrupt on line 11 */
+#define  EXTI_SWIEVR_SWIEVR12                   ((uint32_t)0x00001000)        /* Software Interrupt on line 12 */
+#define  EXTI_SWIEVR_SWIEVR13                   ((uint32_t)0x00002000)        /* Software Interrupt on line 13 */
+#define  EXTI_SWIEVR_SWIEVR14                   ((uint32_t)0x00004000)        /* Software Interrupt on line 14 */
+#define  EXTI_SWIEVR_SWIEVR15                   ((uint32_t)0x00008000)        /* Software Interrupt on line 15 */
+#define  EXTI_SWIEVR_SWIEVR16                   ((uint32_t)0x00010000)        /* Software Interrupt on line 16 */
+#define  EXTI_SWIEVR_SWIEVR17                   ((uint32_t)0x00020000)        /* Software Interrupt on line 17 */
+#define  EXTI_SWIEVR_SWIEVR18                   ((uint32_t)0x00040000)        /* Software Interrupt on line 18 */
+#define  EXTI_SWIEVR_SWIEVR19                   ((uint32_t)0x00080000)        /* Software Interrupt on line 19 */
+
+/*******************  Bit definition for EXTI_INTFR register  ********************/
+#define  EXTI_INTF_INTF0                        ((uint32_t)0x00000001)        /* Pending bit for line 0 */
+#define  EXTI_INTF_INTF1                        ((uint32_t)0x00000002)        /* Pending bit for line 1 */
+#define  EXTI_INTF_INTF2                        ((uint32_t)0x00000004)        /* Pending bit for line 2 */
+#define  EXTI_INTF_INTF3                        ((uint32_t)0x00000008)        /* Pending bit for line 3 */
+#define  EXTI_INTF_INTF4                        ((uint32_t)0x00000010)        /* Pending bit for line 4 */
+#define  EXTI_INTF_INTF5                        ((uint32_t)0x00000020)        /* Pending bit for line 5 */
+#define  EXTI_INTF_INTF6                        ((uint32_t)0x00000040)        /* Pending bit for line 6 */
+#define  EXTI_INTF_INTF7                        ((uint32_t)0x00000080)        /* Pending bit for line 7 */
+#define  EXTI_INTF_INTF8                        ((uint32_t)0x00000100)        /* Pending bit for line 8 */
+#define  EXTI_INTF_INTF9                        ((uint32_t)0x00000200)        /* Pending bit for line 9 */
+#define  EXTI_INTF_INTF10                       ((uint32_t)0x00000400)        /* Pending bit for line 10 */
+#define  EXTI_INTF_INTF11                       ((uint32_t)0x00000800)        /* Pending bit for line 11 */
+#define  EXTI_INTF_INTF12                       ((uint32_t)0x00001000)        /* Pending bit for line 12 */
+#define  EXTI_INTF_INTF13                       ((uint32_t)0x00002000)        /* Pending bit for line 13 */
+#define  EXTI_INTF_INTF14                       ((uint32_t)0x00004000)        /* Pending bit for line 14 */
+#define  EXTI_INTF_INTF15                       ((uint32_t)0x00008000)        /* Pending bit for line 15 */
+#define  EXTI_INTF_INTF16                       ((uint32_t)0x00010000)        /* Pending bit for line 16 */
+#define  EXTI_INTF_INTF17                       ((uint32_t)0x00020000)        /* Pending bit for line 17 */
+#define  EXTI_INTF_INTF18                       ((uint32_t)0x00040000)        /* Pending bit for line 18 */
+#define  EXTI_INTF_INTF19                       ((uint32_t)0x00080000)        /* Pending bit for line 19 */
+
+/******************************************************************************/
+/*                      FLASH and Option Bytes Registers                      */
+/******************************************************************************/
+
+
+/*******************  Bit definition for FLASH_ACTLR register  ******************/
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define  FLASH_KEYR_FKEYR                      ((uint32_t)0xFFFFFFFF)        /* FPEC Key */
+
+/*****************  Bit definition for FLASH_OBKEYR register  ****************/
+#define  FLASH_OBKEYR_OBKEYR                   ((uint32_t)0xFFFFFFFF)        /* Option Byte Key */
+
+/******************  Bit definition for FLASH_STATR register  *******************/
+#define  FLASH_STATR_BSY                       ((uint8_t)0x01)               /* Busy */
+#define  FLASH_STATR_PGERR                     ((uint8_t)0x04)               /* Programming Error */
+#define  FLASH_STATR_WRPRTERR                  ((uint8_t)0x10)               /* Write Protection Error */
+#define  FLASH_STATR_EOP                       ((uint8_t)0x20)               /* End of operation */
+
+/*******************  Bit definition for FLASH_CTLR register  *******************/
+#define  FLASH_CTLR_PG                         ((uint32_t)0x00000001)        /* Programming */
+#define  FLASH_CTLR_PER                        ((uint32_t)0x00000002)        /* Sector Erase 4K */
+#define  FLASH_CTLR_MER                        ((uint32_t)0x00000004)        /* Mass Erase */
+#define  FLASH_CTLR_OPTPG                      ((uint32_t)0x00000010)        /* Option Byte Programming */
+#define  FLASH_CTLR_OPTER                      ((uint32_t)0x00000020)        /* Option Byte Erase */
+#define  FLASH_CTLR_STRT                       ((uint32_t)0x00000040)        /* Start */
+#define  FLASH_CTLR_LOCK                       ((uint32_t)0x00000080)        /* Lock */
+#define  FLASH_CTLR_OPTWRE                     ((uint32_t)0x00000200)        /* Option Bytes Write Enable */
+#define  FLASH_CTLR_ERRIE                      ((uint32_t)0x00000400)        /* Error Interrupt Enable */
+#define  FLASH_CTLR_EOPIE                      ((uint32_t)0x00001000)        /* End of operation interrupt enable */
+#define  FLASH_CTLR_FAST_LOCK                  ((uint32_t)0x00008000)        /* Fast Lock */
+#define  FLASH_CTLR_PAGE_PG                    ((uint32_t)0x00010000)        /* Page Programming 256Byte */
+#define  FLASH_CTLR_PAGE_ER                    ((uint32_t)0x00020000)        /* Page Erase 256Byte */
+#define  FLASH_CTLR_PAGE_BER32                 ((uint32_t)0x00040000)        /* Block Erase 32K */
+#define  FLASH_CTLR_PAGE_BER64                 ((uint32_t)0x00080000)        /* Block Erase 64K */
+#define  FLASH_CTLR_PG_STRT                    ((uint32_t)0x00200000)        /* Page Programming Start */
+
+/*******************  Bit definition for FLASH_ADDR register  *******************/
+#define  FLASH_ADDR_FAR                        ((uint32_t)0xFFFFFFFF)        /* Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define  FLASH_OBR_OPTERR                      ((uint16_t)0x0001)            /* Option Byte Error */
+#define  FLASH_OBR_RDPRT                       ((uint16_t)0x0002)            /* Read protection */
+
+#define  FLASH_OBR_USER                        ((uint16_t)0x03FC)            /* User Option Bytes */
+#define  FLASH_OBR_WDG_SW                      ((uint16_t)0x0004)            /* WDG_SW */
+#define  FLASH_OBR_nRST_STOP                   ((uint16_t)0x0008)            /* nRST_STOP */
+#define  FLASH_OBR_nRST_STDBY                  ((uint16_t)0x0010)            /* nRST_STDBY */
+#define  FLASH_OBR_BFB2                        ((uint16_t)0x0020)            /* BFB2 */
+
+/******************  Bit definition for FLASH_WPR register  ******************/
+#define  FLASH_WPR_WRP                         ((uint32_t)0xFFFFFFFF)        /* Write Protect */
+
+/******************  Bit definition for FLASH_RDPR register  *******************/
+#define  FLASH_RDPR_RDPR                       ((uint32_t)0x000000FF)        /* Read protection option byte */
+#define  FLASH_RDPR_nRDPR                      ((uint32_t)0x0000FF00)        /* Read protection complemented option byte */
+
+/******************  Bit definition for FLASH_USER register  ******************/
+#define  FLASH_USER_USER                       ((uint32_t)0x00FF0000)        /* User option byte */
+#define  FLASH_USER_nUSER                      ((uint32_t)0xFF000000)        /* User complemented option byte */
+
+/******************  Bit definition for FLASH_Data0 register  *****************/
+#define  FLASH_Data0_Data0                     ((uint32_t)0x000000FF)        /* User data storage option byte */
+#define  FLASH_Data0_nData0                    ((uint32_t)0x0000FF00)        /* User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_Data1 register  *****************/
+#define  FLASH_Data1_Data1                     ((uint32_t)0x00FF0000)        /* User data storage option byte */
+#define  FLASH_Data1_nData1                    ((uint32_t)0xFF000000)        /* User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_WRPR0 register  ******************/
+#define  FLASH_WRPR0_WRPR0                     ((uint32_t)0x000000FF)        /* Flash memory write protection option bytes */
+#define  FLASH_WRPR0_nWRPR0                    ((uint32_t)0x0000FF00)        /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR1 register  ******************/
+#define  FLASH_WRPR1_WRPR1                     ((uint32_t)0x00FF0000)        /* Flash memory write protection option bytes */
+#define  FLASH_WRPR1_nWRPR1                    ((uint32_t)0xFF000000)        /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR2 register  ******************/
+#define  FLASH_WRPR2_WRPR2                     ((uint32_t)0x000000FF)        /* Flash memory write protection option bytes */
+#define  FLASH_WRPR2_nWRPR2                    ((uint32_t)0x0000FF00)        /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR3 register  ******************/
+#define  FLASH_WRPR3_WRPR3                     ((uint32_t)0x00FF0000)        /* Flash memory write protection option bytes */
+#define  FLASH_WRPR3_nWRPR3                    ((uint32_t)0xFF000000)        /* Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/*                General Purpose and Alternate Function I/O                  */
+/******************************************************************************/
+
+/*******************  Bit definition for GPIO_CFGLR register  *******************/
+#define  GPIO_CFGLR_MODE                       ((uint32_t)0x33333333)        /* Port x mode bits */
+
+#define  GPIO_CFGLR_MODE0                      ((uint32_t)0x00000003)        /* MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define  GPIO_CFGLR_MODE0_0                    ((uint32_t)0x00000001)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE0_1                    ((uint32_t)0x00000002)        /* Bit 1 */
+
+#define  GPIO_CFGLR_MODE1                      ((uint32_t)0x00000030)        /* MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define  GPIO_CFGLR_MODE1_0                    ((uint32_t)0x00000010)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE1_1                    ((uint32_t)0x00000020)        /* Bit 1 */
+
+#define  GPIO_CFGLR_MODE2                      ((uint32_t)0x00000300)        /* MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define  GPIO_CFGLR_MODE2_0                    ((uint32_t)0x00000100)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE2_1                    ((uint32_t)0x00000200)        /* Bit 1 */
+
+#define  GPIO_CFGLR_MODE3                      ((uint32_t)0x00003000)        /* MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define  GPIO_CFGLR_MODE3_0                    ((uint32_t)0x00001000)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE3_1                    ((uint32_t)0x00002000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_MODE4                      ((uint32_t)0x00030000)        /* MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define  GPIO_CFGLR_MODE4_0                    ((uint32_t)0x00010000)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE4_1                    ((uint32_t)0x00020000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_MODE5                      ((uint32_t)0x00300000)        /* MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define  GPIO_CFGLR_MODE5_0                    ((uint32_t)0x00100000)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE5_1                    ((uint32_t)0x00200000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_MODE6                      ((uint32_t)0x03000000)        /* MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define  GPIO_CFGLR_MODE6_0                    ((uint32_t)0x01000000)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE6_1                    ((uint32_t)0x02000000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_MODE7                      ((uint32_t)0x30000000)        /* MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define  GPIO_CFGLR_MODE7_0                    ((uint32_t)0x10000000)        /* Bit 0 */
+#define  GPIO_CFGLR_MODE7_1                    ((uint32_t)0x20000000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF                        ((uint32_t)0xCCCCCCCC)        /* Port x configuration bits */
+
+#define  GPIO_CFGLR_CNF0                       ((uint32_t)0x0000000C)        /* CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define  GPIO_CFGLR_CNF0_0                     ((uint32_t)0x00000004)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF0_1                     ((uint32_t)0x00000008)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF1                       ((uint32_t)0x000000C0)        /* CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define  GPIO_CFGLR_CNF1_0                     ((uint32_t)0x00000040)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF1_1                     ((uint32_t)0x00000080)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF2                       ((uint32_t)0x00000C00)        /* CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define  GPIO_CFGLR_CNF2_0                     ((uint32_t)0x00000400)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF2_1                     ((uint32_t)0x00000800)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF3                       ((uint32_t)0x0000C000)        /* CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define  GPIO_CFGLR_CNF3_0                     ((uint32_t)0x00004000)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF3_1                     ((uint32_t)0x00008000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF4                       ((uint32_t)0x000C0000)        /* CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define  GPIO_CFGLR_CNF4_0                     ((uint32_t)0x00040000)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF4_1                     ((uint32_t)0x00080000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF5                       ((uint32_t)0x00C00000)        /* CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define  GPIO_CFGLR_CNF5_0                     ((uint32_t)0x00400000)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF5_1                     ((uint32_t)0x00800000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF6                       ((uint32_t)0x0C000000)        /* CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define  GPIO_CFGLR_CNF6_0                     ((uint32_t)0x04000000)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF6_1                     ((uint32_t)0x08000000)        /* Bit 1 */
+
+#define  GPIO_CFGLR_CNF7                       ((uint32_t)0xC0000000)        /* CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define  GPIO_CFGLR_CNF7_0                     ((uint32_t)0x40000000)        /* Bit 0 */
+#define  GPIO_CFGLR_CNF7_1                     ((uint32_t)0x80000000)        /* Bit 1 */
+
+/*******************  Bit definition for GPIO_CFGHR register  *******************/
+#define  GPIO_CFGHR_MODE                       ((uint32_t)0x33333333)        /* Port x mode bits */
+
+#define  GPIO_CFGHR_MODE8                      ((uint32_t)0x00000003)        /* MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define  GPIO_CFGHR_MODE8_0                    ((uint32_t)0x00000001)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE8_1                    ((uint32_t)0x00000002)        /* Bit 1 */
+
+#define  GPIO_CFGHR_MODE9                      ((uint32_t)0x00000030)        /* MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define  GPIO_CFGHR_MODE9_0                    ((uint32_t)0x00000010)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE9_1                    ((uint32_t)0x00000020)        /* Bit 1 */
+
+#define  GPIO_CFGHR_MODE10                     ((uint32_t)0x00000300)        /* MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define  GPIO_CFGHR_MODE10_0                   ((uint32_t)0x00000100)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE10_1                   ((uint32_t)0x00000200)        /* Bit 1 */
+
+#define  GPIO_CFGHR_MODE11                     ((uint32_t)0x00003000)        /* MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define  GPIO_CFGHR_MODE11_0                   ((uint32_t)0x00001000)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE11_1                   ((uint32_t)0x00002000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_MODE12                     ((uint32_t)0x00030000)        /* MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define  GPIO_CFGHR_MODE12_0                   ((uint32_t)0x00010000)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE12_1                   ((uint32_t)0x00020000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_MODE13                     ((uint32_t)0x00300000)        /* MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define  GPIO_CFGHR_MODE13_0                   ((uint32_t)0x00100000)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE13_1                   ((uint32_t)0x00200000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_MODE14                     ((uint32_t)0x03000000)        /* MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define  GPIO_CFGHR_MODE14_0                   ((uint32_t)0x01000000)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE14_1                   ((uint32_t)0x02000000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_MODE15                     ((uint32_t)0x30000000)        /* MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define  GPIO_CFGHR_MODE15_0                   ((uint32_t)0x10000000)        /* Bit 0 */
+#define  GPIO_CFGHR_MODE15_1                   ((uint32_t)0x20000000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF                        ((uint32_t)0xCCCCCCCC)        /* Port x configuration bits */
+
+#define  GPIO_CFGHR_CNF8                       ((uint32_t)0x0000000C)        /* CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define  GPIO_CFGHR_CNF8_0                     ((uint32_t)0x00000004)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF8_1                     ((uint32_t)0x00000008)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF9                       ((uint32_t)0x000000C0)        /* CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define  GPIO_CFGHR_CNF9_0                     ((uint32_t)0x00000040)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF9_1                     ((uint32_t)0x00000080)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF10                      ((uint32_t)0x00000C00)        /* CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define  GPIO_CFGHR_CNF10_0                    ((uint32_t)0x00000400)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF10_1                    ((uint32_t)0x00000800)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF11                      ((uint32_t)0x0000C000)        /* CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define  GPIO_CFGHR_CNF11_0                    ((uint32_t)0x00004000)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF11_1                    ((uint32_t)0x00008000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF12                      ((uint32_t)0x000C0000)        /* CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define  GPIO_CFGHR_CNF12_0                    ((uint32_t)0x00040000)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF12_1                    ((uint32_t)0x00080000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF13                      ((uint32_t)0x00C00000)        /* CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define  GPIO_CFGHR_CNF13_0                    ((uint32_t)0x00400000)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF13_1                    ((uint32_t)0x00800000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF14                      ((uint32_t)0x0C000000)        /* CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define  GPIO_CFGHR_CNF14_0                    ((uint32_t)0x04000000)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF14_1                    ((uint32_t)0x08000000)        /* Bit 1 */
+
+#define  GPIO_CFGHR_CNF15                      ((uint32_t)0xC0000000)        /* CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define  GPIO_CFGHR_CNF15_0                    ((uint32_t)0x40000000)        /* Bit 0 */
+#define  GPIO_CFGHR_CNF15_1                    ((uint32_t)0x80000000)        /* Bit 1 */
+
+/*******************  Bit definition for GPIO_INDR register  *******************/
+#define GPIO_INDR_IDR0                         ((uint16_t)0x0001)            /* Port input data, bit 0 */
+#define GPIO_INDR_IDR1                         ((uint16_t)0x0002)            /* Port input data, bit 1 */
+#define GPIO_INDR_IDR2                         ((uint16_t)0x0004)            /* Port input data, bit 2 */
+#define GPIO_INDR_IDR3                         ((uint16_t)0x0008)            /* Port input data, bit 3 */
+#define GPIO_INDR_IDR4                         ((uint16_t)0x0010)            /* Port input data, bit 4 */
+#define GPIO_INDR_IDR5                         ((uint16_t)0x0020)            /* Port input data, bit 5 */
+#define GPIO_INDR_IDR6                         ((uint16_t)0x0040)            /* Port input data, bit 6 */
+#define GPIO_INDR_IDR7                         ((uint16_t)0x0080)            /* Port input data, bit 7 */
+#define GPIO_INDR_IDR8                         ((uint16_t)0x0100)            /* Port input data, bit 8 */
+#define GPIO_INDR_IDR9                         ((uint16_t)0x0200)            /* Port input data, bit 9 */
+#define GPIO_INDR_IDR10                        ((uint16_t)0x0400)            /* Port input data, bit 10 */
+#define GPIO_INDR_IDR11                        ((uint16_t)0x0800)            /* Port input data, bit 11 */
+#define GPIO_INDR_IDR12                        ((uint16_t)0x1000)            /* Port input data, bit 12 */
+#define GPIO_INDR_IDR13                        ((uint16_t)0x2000)            /* Port input data, bit 13 */
+#define GPIO_INDR_IDR14                        ((uint16_t)0x4000)            /* Port input data, bit 14 */
+#define GPIO_INDR_IDR15                        ((uint16_t)0x8000)            /* Port input data, bit 15 */
+
+/*******************  Bit definition for GPIO_OUTDR register  *******************/
+#define GPIO_OUTDR_ODR0                        ((uint16_t)0x0001)            /* Port output data, bit 0 */
+#define GPIO_OUTDR_ODR1                        ((uint16_t)0x0002)            /* Port output data, bit 1 */
+#define GPIO_OUTDR_ODR2                        ((uint16_t)0x0004)            /* Port output data, bit 2 */
+#define GPIO_OUTDR_ODR3                        ((uint16_t)0x0008)            /* Port output data, bit 3 */
+#define GPIO_OUTDR_ODR4                        ((uint16_t)0x0010)            /* Port output data, bit 4 */
+#define GPIO_OUTDR_ODR5                        ((uint16_t)0x0020)            /* Port output data, bit 5 */
+#define GPIO_OUTDR_ODR6                        ((uint16_t)0x0040)            /* Port output data, bit 6 */
+#define GPIO_OUTDR_ODR7                        ((uint16_t)0x0080)            /* Port output data, bit 7 */
+#define GPIO_OUTDR_ODR8                        ((uint16_t)0x0100)            /* Port output data, bit 8 */
+#define GPIO_OUTDR_ODR9                        ((uint16_t)0x0200)            /* Port output data, bit 9 */
+#define GPIO_OUTDR_ODR10                       ((uint16_t)0x0400)            /* Port output data, bit 10 */
+#define GPIO_OUTDR_ODR11                       ((uint16_t)0x0800)            /* Port output data, bit 11 */
+#define GPIO_OUTDR_ODR12                       ((uint16_t)0x1000)            /* Port output data, bit 12 */
+#define GPIO_OUTDR_ODR13                       ((uint16_t)0x2000)            /* Port output data, bit 13 */
+#define GPIO_OUTDR_ODR14                       ((uint16_t)0x4000)            /* Port output data, bit 14 */
+#define GPIO_OUTDR_ODR15                       ((uint16_t)0x8000)            /* Port output data, bit 15 */
+
+/******************  Bit definition for GPIO_BSHR register  *******************/
+#define GPIO_BSHR_BS0                          ((uint32_t)0x00000001)        /* Port x Set bit 0 */
+#define GPIO_BSHR_BS1                          ((uint32_t)0x00000002)        /* Port x Set bit 1 */
+#define GPIO_BSHR_BS2                          ((uint32_t)0x00000004)        /* Port x Set bit 2 */
+#define GPIO_BSHR_BS3                          ((uint32_t)0x00000008)        /* Port x Set bit 3 */
+#define GPIO_BSHR_BS4                          ((uint32_t)0x00000010)        /* Port x Set bit 4 */
+#define GPIO_BSHR_BS5                          ((uint32_t)0x00000020)        /* Port x Set bit 5 */
+#define GPIO_BSHR_BS6                          ((uint32_t)0x00000040)        /* Port x Set bit 6 */
+#define GPIO_BSHR_BS7                          ((uint32_t)0x00000080)        /* Port x Set bit 7 */
+#define GPIO_BSHR_BS8                          ((uint32_t)0x00000100)        /* Port x Set bit 8 */
+#define GPIO_BSHR_BS9                          ((uint32_t)0x00000200)        /* Port x Set bit 9 */
+#define GPIO_BSHR_BS10                         ((uint32_t)0x00000400)        /* Port x Set bit 10 */
+#define GPIO_BSHR_BS11                         ((uint32_t)0x00000800)        /* Port x Set bit 11 */
+#define GPIO_BSHR_BS12                         ((uint32_t)0x00001000)        /* Port x Set bit 12 */
+#define GPIO_BSHR_BS13                         ((uint32_t)0x00002000)        /* Port x Set bit 13 */
+#define GPIO_BSHR_BS14                         ((uint32_t)0x00004000)        /* Port x Set bit 14 */
+#define GPIO_BSHR_BS15                         ((uint32_t)0x00008000)        /* Port x Set bit 15 */
+
+#define GPIO_BSHR_BR0                          ((uint32_t)0x00010000)        /* Port x Reset bit 0 */
+#define GPIO_BSHR_BR1                          ((uint32_t)0x00020000)        /* Port x Reset bit 1 */
+#define GPIO_BSHR_BR2                          ((uint32_t)0x00040000)        /* Port x Reset bit 2 */
+#define GPIO_BSHR_BR3                          ((uint32_t)0x00080000)        /* Port x Reset bit 3 */
+#define GPIO_BSHR_BR4                          ((uint32_t)0x00100000)        /* Port x Reset bit 4 */
+#define GPIO_BSHR_BR5                          ((uint32_t)0x00200000)        /* Port x Reset bit 5 */
+#define GPIO_BSHR_BR6                          ((uint32_t)0x00400000)        /* Port x Reset bit 6 */
+#define GPIO_BSHR_BR7                          ((uint32_t)0x00800000)        /* Port x Reset bit 7 */
+#define GPIO_BSHR_BR8                          ((uint32_t)0x01000000)        /* Port x Reset bit 8 */
+#define GPIO_BSHR_BR9                          ((uint32_t)0x02000000)        /* Port x Reset bit 9 */
+#define GPIO_BSHR_BR10                         ((uint32_t)0x04000000)        /* Port x Reset bit 10 */
+#define GPIO_BSHR_BR11                         ((uint32_t)0x08000000)        /* Port x Reset bit 11 */
+#define GPIO_BSHR_BR12                         ((uint32_t)0x10000000)        /* Port x Reset bit 12 */
+#define GPIO_BSHR_BR13                         ((uint32_t)0x20000000)        /* Port x Reset bit 13 */
+#define GPIO_BSHR_BR14                         ((uint32_t)0x40000000)        /* Port x Reset bit 14 */
+#define GPIO_BSHR_BR15                         ((uint32_t)0x80000000)        /* Port x Reset bit 15 */
+
+/*******************  Bit definition for GPIO_BCR register  *******************/
+#define GPIO_BCR_BR0                           ((uint16_t)0x0001)            /* Port x Reset bit 0 */
+#define GPIO_BCR_BR1                           ((uint16_t)0x0002)            /* Port x Reset bit 1 */
+#define GPIO_BCR_BR2                           ((uint16_t)0x0004)            /* Port x Reset bit 2 */
+#define GPIO_BCR_BR3                           ((uint16_t)0x0008)            /* Port x Reset bit 3 */
+#define GPIO_BCR_BR4                           ((uint16_t)0x0010)            /* Port x Reset bit 4 */
+#define GPIO_BCR_BR5                           ((uint16_t)0x0020)            /* Port x Reset bit 5 */
+#define GPIO_BCR_BR6                           ((uint16_t)0x0040)            /* Port x Reset bit 6 */
+#define GPIO_BCR_BR7                           ((uint16_t)0x0080)            /* Port x Reset bit 7 */
+#define GPIO_BCR_BR8                           ((uint16_t)0x0100)            /* Port x Reset bit 8 */
+#define GPIO_BCR_BR9                           ((uint16_t)0x0200)            /* Port x Reset bit 9 */
+#define GPIO_BCR_BR10                          ((uint16_t)0x0400)            /* Port x Reset bit 10 */
+#define GPIO_BCR_BR11                          ((uint16_t)0x0800)            /* Port x Reset bit 11 */
+#define GPIO_BCR_BR12                          ((uint16_t)0x1000)            /* Port x Reset bit 12 */
+#define GPIO_BCR_BR13                          ((uint16_t)0x2000)            /* Port x Reset bit 13 */
+#define GPIO_BCR_BR14                          ((uint16_t)0x4000)            /* Port x Reset bit 14 */
+#define GPIO_BCR_BR15                          ((uint16_t)0x8000)            /* Port x Reset bit 15 */
+
+/******************  Bit definition for GPIO_LCKR register  *******************/
+#define GPIO_LCK0                              ((uint32_t)0x00000001)        /* Port x Lock bit 0 */
+#define GPIO_LCK1                              ((uint32_t)0x00000002)        /* Port x Lock bit 1 */
+#define GPIO_LCK2                              ((uint32_t)0x00000004)        /* Port x Lock bit 2 */
+#define GPIO_LCK3                              ((uint32_t)0x00000008)        /* Port x Lock bit 3 */
+#define GPIO_LCK4                              ((uint32_t)0x00000010)        /* Port x Lock bit 4 */
+#define GPIO_LCK5                              ((uint32_t)0x00000020)        /* Port x Lock bit 5 */
+#define GPIO_LCK6                              ((uint32_t)0x00000040)        /* Port x Lock bit 6 */
+#define GPIO_LCK7                              ((uint32_t)0x00000080)        /* Port x Lock bit 7 */
+#define GPIO_LCK8                              ((uint32_t)0x00000100)        /* Port x Lock bit 8 */
+#define GPIO_LCK9                              ((uint32_t)0x00000200)        /* Port x Lock bit 9 */
+#define GPIO_LCK10                             ((uint32_t)0x00000400)        /* Port x Lock bit 10 */
+#define GPIO_LCK11                             ((uint32_t)0x00000800)        /* Port x Lock bit 11 */
+#define GPIO_LCK12                             ((uint32_t)0x00001000)        /* Port x Lock bit 12 */
+#define GPIO_LCK13                             ((uint32_t)0x00002000)        /* Port x Lock bit 13 */
+#define GPIO_LCK14                             ((uint32_t)0x00004000)        /* Port x Lock bit 14 */
+#define GPIO_LCK15                             ((uint32_t)0x00008000)        /* Port x Lock bit 15 */
+#define GPIO_LCKK                              ((uint32_t)0x00010000)        /* Lock key */
+
+
+/******************  Bit definition for AFIO_ECR register  *******************/
+#define AFIO_ECR_PIN                           ((uint8_t)0x0F)               /* PIN[3:0] bits (Pin selection) */
+#define AFIO_ECR_PIN_0                         ((uint8_t)0x01)               /* Bit 0 */
+#define AFIO_ECR_PIN_1                         ((uint8_t)0x02)               /* Bit 1 */
+#define AFIO_ECR_PIN_2                         ((uint8_t)0x04)               /* Bit 2 */
+#define AFIO_ECR_PIN_3                         ((uint8_t)0x08)               /* Bit 3 */
+
+#define AFIO_ECR_PIN_PX0                       ((uint8_t)0x00)               /* Pin 0 selected */
+#define AFIO_ECR_PIN_PX1                       ((uint8_t)0x01)               /* Pin 1 selected */
+#define AFIO_ECR_PIN_PX2                       ((uint8_t)0x02)               /* Pin 2 selected */
+#define AFIO_ECR_PIN_PX3                       ((uint8_t)0x03)               /* Pin 3 selected */
+#define AFIO_ECR_PIN_PX4                       ((uint8_t)0x04)               /* Pin 4 selected */
+#define AFIO_ECR_PIN_PX5                       ((uint8_t)0x05)               /* Pin 5 selected */
+#define AFIO_ECR_PIN_PX6                       ((uint8_t)0x06)               /* Pin 6 selected */
+#define AFIO_ECR_PIN_PX7                       ((uint8_t)0x07)               /* Pin 7 selected */
+#define AFIO_ECR_PIN_PX8                       ((uint8_t)0x08)               /* Pin 8 selected */
+#define AFIO_ECR_PIN_PX9                       ((uint8_t)0x09)               /* Pin 9 selected */
+#define AFIO_ECR_PIN_PX10                      ((uint8_t)0x0A)               /* Pin 10 selected */
+#define AFIO_ECR_PIN_PX11                      ((uint8_t)0x0B)               /* Pin 11 selected */
+#define AFIO_ECR_PIN_PX12                      ((uint8_t)0x0C)               /* Pin 12 selected */
+#define AFIO_ECR_PIN_PX13                      ((uint8_t)0x0D)               /* Pin 13 selected */
+#define AFIO_ECR_PIN_PX14                      ((uint8_t)0x0E)               /* Pin 14 selected */
+#define AFIO_ECR_PIN_PX15                      ((uint8_t)0x0F)               /* Pin 15 selected */
+
+#define AFIO_ECR_PORT                          ((uint8_t)0x70)               /* PORT[2:0] bits (Port selection) */
+#define AFIO_ECR_PORT_0                        ((uint8_t)0x10)               /* Bit 0 */
+#define AFIO_ECR_PORT_1                        ((uint8_t)0x20)               /* Bit 1 */
+#define AFIO_ECR_PORT_2                        ((uint8_t)0x40)               /* Bit 2 */
+
+#define AFIO_ECR_PORT_PA                       ((uint8_t)0x00)               /* Port A selected */
+#define AFIO_ECR_PORT_PB                       ((uint8_t)0x10)               /* Port B selected */
+#define AFIO_ECR_PORT_PC                       ((uint8_t)0x20)               /* Port C selected */
+#define AFIO_ECR_PORT_PD                       ((uint8_t)0x30)               /* Port D selected */
+#define AFIO_ECR_PORT_PE                       ((uint8_t)0x40)               /* Port E selected */
+
+#define AFIO_ECR_EVOE                          ((uint8_t)0x80)               /* Event Output Enable */
+
+/******************  Bit definition for AFIO_PCFR1register  *******************/
+#define AFIO_PCFR1_SPI1_REMAP                  ((uint32_t)0x00000001)        /* SPI1 remapping */
+#define AFIO_PCFR1_I2C1_REMAP                  ((uint32_t)0x00000002)        /* I2C1 remapping */
+#define AFIO_PCFR1_USART1_REMAP                ((uint32_t)0x00000004)        /* USART1 remapping */
+#define AFIO_PCFR1_USART2_REMAP                ((uint32_t)0x00000008)        /* USART2 remapping */
+
+#define AFIO_PCFR1_USART3_REMAP                ((uint32_t)0x00000030)        /* USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_PCFR1_USART3_REMAP_0              ((uint32_t)0x00000010)        /* Bit 0 */
+#define AFIO_PCFR1_USART3_REMAP_1              ((uint32_t)0x00000020)        /* Bit 1 */
+
+#define AFIO_PCFR1_USART3_REMAP_NOREMAP        ((uint32_t)0x00000000)        /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP   ((uint32_t)0x00000010)        /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_PCFR1_USART3_REMAP_FULLREMAP      ((uint32_t)0x00000030)        /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_PCFR1_TIM1_REMAP                  ((uint32_t)0x000000C0)        /* TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_PCFR1_TIM1_REMAP_0                ((uint32_t)0x00000040)        /* Bit 0 */
+#define AFIO_PCFR1_TIM1_REMAP_1                ((uint32_t)0x00000080)        /* Bit 1 */
+
+#define AFIO_PCFR1_TIM1_REMAP_NOREMAP          ((uint32_t)0x00000000)        /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP     ((uint32_t)0x00000040)        /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP        ((uint32_t)0x000000C0)        /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_PCFR1_TIM2_REMAP                  ((uint32_t)0x00000300)        /* TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_PCFR1_TIM2_REMAP_0                ((uint32_t)0x00000100)        /* Bit 0 */
+#define AFIO_PCFR1_TIM2_REMAP_1                ((uint32_t)0x00000200)        /* Bit 1 */
+
+#define AFIO_PCFR1_TIM2_REMAP_NOREMAP          ((uint32_t)0x00000000)        /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1    ((uint32_t)0x00000100)        /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2    ((uint32_t)0x00000200)        /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP        ((uint32_t)0x00000300)        /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_PCFR1_TIM3_REMAP                  ((uint32_t)0x00000C00)        /* TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_PCFR1_TIM3_REMAP_0                ((uint32_t)0x00000400)        /* Bit 0 */
+#define AFIO_PCFR1_TIM3_REMAP_1                ((uint32_t)0x00000800)        /* Bit 1 */
+
+#define AFIO_PCFR1_TIM3_REMAP_NOREMAP          ((uint32_t)0x00000000)        /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP     ((uint32_t)0x00000800)        /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP        ((uint32_t)0x00000C00)        /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_PCFR1_TIM4_REMAP                  ((uint32_t)0x00001000)        /* TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_PCFR1_CAN_REMAP                   ((uint32_t)0x00006000)        /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_PCFR1_CAN_REMAP_0                 ((uint32_t)0x00002000)        /* Bit 0 */
+#define AFIO_PCFR1_CAN_REMAP_1                 ((uint32_t)0x00004000)        /* Bit 1 */
+
+#define AFIO_PCFR1_CAN_REMAP_REMAP1            ((uint32_t)0x00000000)        /* CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_PCFR1_CAN_REMAP_REMAP2            ((uint32_t)0x00004000)        /* CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_PCFR1_CAN_REMAP_REMAP3            ((uint32_t)0x00006000)        /* CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_PCFR1_PD01_REMAP                  ((uint32_t)0x00008000)        /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_PCFR1_TIM5CH4_IREMAP              ((uint32_t)0x00010000)        /* TIM5 Channel4 Internal Remap */
+#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP          ((uint32_t)0x00020000)        /* ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_PCFR1_ADC1_ETRGREG_REMAP          ((uint32_t)0x00040000)        /* ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP          ((uint32_t)0x00080000)        /* ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_PCFR1_ADC2_ETRGREG_REMAP          ((uint32_t)0x00100000)        /* ADC 2 External Trigger Regular Conversion remapping */
+
+#define AFIO_PCFR1_SWJ_CFG                     ((uint32_t)0x07000000)        /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_PCFR1_SWJ_CFG_0                   ((uint32_t)0x01000000)        /* Bit 0 */
+#define AFIO_PCFR1_SWJ_CFG_1                   ((uint32_t)0x02000000)        /* Bit 1 */
+#define AFIO_PCFR1_SWJ_CFG_2                   ((uint32_t)0x04000000)        /* Bit 2 */
+
+#define AFIO_PCFR1_SWJ_CFG_RESET               ((uint32_t)0x00000000)        /* Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_PCFR1_SWJ_CFG_NOJNTRST            ((uint32_t)0x01000000)        /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE         ((uint32_t)0x02000000)        /* JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_PCFR1_SWJ_CFG_DISABLE             ((uint32_t)0x04000000)        /* JTAG-DP Disabled and SW-DP Disabled */
+
+/*****************  Bit definition for AFIO_EXTICR1 register  *****************/
+#define AFIO_EXTICR1_EXTI0                     ((uint16_t)0x000F)            /* EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1                     ((uint16_t)0x00F0)            /* EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2                     ((uint16_t)0x0F00)            /* EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3                     ((uint16_t)0xF000)            /* EXTI 3 configuration */
+
+#define AFIO_EXTICR1_EXTI0_PA                  ((uint16_t)0x0000)            /* PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB                  ((uint16_t)0x0001)            /* PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC                  ((uint16_t)0x0002)            /* PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD                  ((uint16_t)0x0003)            /* PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE                  ((uint16_t)0x0004)            /* PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF                  ((uint16_t)0x0005)            /* PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG                  ((uint16_t)0x0006)            /* PG[0] pin */
+
+#define AFIO_EXTICR1_EXTI1_PA                  ((uint16_t)0x0000)            /* PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB                  ((uint16_t)0x0010)            /* PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC                  ((uint16_t)0x0020)            /* PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD                  ((uint16_t)0x0030)            /* PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE                  ((uint16_t)0x0040)            /* PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF                  ((uint16_t)0x0050)            /* PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG                  ((uint16_t)0x0060)            /* PG[1] pin */
+ 
+#define AFIO_EXTICR1_EXTI2_PA                  ((uint16_t)0x0000)            /* PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB                  ((uint16_t)0x0100)            /* PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC                  ((uint16_t)0x0200)            /* PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD                  ((uint16_t)0x0300)            /* PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE                  ((uint16_t)0x0400)            /* PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF                  ((uint16_t)0x0500)            /* PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG                  ((uint16_t)0x0600)            /* PG[2] pin */
+
+#define AFIO_EXTICR1_EXTI3_PA                  ((uint16_t)0x0000)            /* PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB                  ((uint16_t)0x1000)            /* PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC                  ((uint16_t)0x2000)            /* PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD                  ((uint16_t)0x3000)            /* PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE                  ((uint16_t)0x4000)            /* PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF                  ((uint16_t)0x5000)            /* PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG                  ((uint16_t)0x6000)            /* PG[3] pin */
+
+/*****************  Bit definition for AFIO_EXTICR2 register  *****************/
+#define AFIO_EXTICR2_EXTI4                     ((uint16_t)0x000F)            /* EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5                     ((uint16_t)0x00F0)            /* EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6                     ((uint16_t)0x0F00)            /* EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7                     ((uint16_t)0xF000)            /* EXTI 7 configuration */
+
+#define AFIO_EXTICR2_EXTI4_PA                  ((uint16_t)0x0000)            /* PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB                  ((uint16_t)0x0001)            /* PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC                  ((uint16_t)0x0002)            /* PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD                  ((uint16_t)0x0003)            /* PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE                  ((uint16_t)0x0004)            /* PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF                  ((uint16_t)0x0005)            /* PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG                  ((uint16_t)0x0006)            /* PG[4] pin */
+
+#define AFIO_EXTICR2_EXTI5_PA                  ((uint16_t)0x0000)            /* PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB                  ((uint16_t)0x0010)            /* PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC                  ((uint16_t)0x0020)            /* PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD                  ((uint16_t)0x0030)            /* PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE                  ((uint16_t)0x0040)            /* PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF                  ((uint16_t)0x0050)            /* PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG                  ((uint16_t)0x0060)            /* PG[5] pin */
+
+#define AFIO_EXTICR2_EXTI6_PA                  ((uint16_t)0x0000)            /* PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB                  ((uint16_t)0x0100)            /* PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC                  ((uint16_t)0x0200)            /* PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD                  ((uint16_t)0x0300)            /* PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE                  ((uint16_t)0x0400)            /* PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF                  ((uint16_t)0x0500)            /* PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG                  ((uint16_t)0x0600)            /* PG[6] pin */
+
+#define AFIO_EXTICR2_EXTI7_PA                  ((uint16_t)0x0000)            /* PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB                  ((uint16_t)0x1000)            /* PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC                  ((uint16_t)0x2000)            /* PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD                  ((uint16_t)0x3000)            /* PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE                  ((uint16_t)0x4000)            /* PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF                  ((uint16_t)0x5000)            /* PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG                  ((uint16_t)0x6000)            /* PG[7] pin */
+
+/*****************  Bit definition for AFIO_EXTICR3 register  *****************/
+#define AFIO_EXTICR3_EXTI8                     ((uint16_t)0x000F)            /* EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9                     ((uint16_t)0x00F0)            /* EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10                    ((uint16_t)0x0F00)            /* EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11                    ((uint16_t)0xF000)            /* EXTI 11 configuration */
+
+#define AFIO_EXTICR3_EXTI8_PA                  ((uint16_t)0x0000)            /* PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB                  ((uint16_t)0x0001)            /* PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC                  ((uint16_t)0x0002)            /* PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD                  ((uint16_t)0x0003)            /* PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE                  ((uint16_t)0x0004)            /* PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF                  ((uint16_t)0x0005)            /* PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG                  ((uint16_t)0x0006)            /* PG[8] pin */
+
+#define AFIO_EXTICR3_EXTI9_PA                  ((uint16_t)0x0000)            /* PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB                  ((uint16_t)0x0010)            /* PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC                  ((uint16_t)0x0020)            /* PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD                  ((uint16_t)0x0030)            /* PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE                  ((uint16_t)0x0040)            /* PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF                  ((uint16_t)0x0050)            /* PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG                  ((uint16_t)0x0060)            /* PG[9] pin */
+ 
+#define AFIO_EXTICR3_EXTI10_PA                 ((uint16_t)0x0000)            /* PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB                 ((uint16_t)0x0100)            /* PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC                 ((uint16_t)0x0200)            /* PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD                 ((uint16_t)0x0300)            /* PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE                 ((uint16_t)0x0400)            /* PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF                 ((uint16_t)0x0500)            /* PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG                 ((uint16_t)0x0600)            /* PG[10] pin */
+
+#define AFIO_EXTICR3_EXTI11_PA                 ((uint16_t)0x0000)            /* PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB                 ((uint16_t)0x1000)            /* PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC                 ((uint16_t)0x2000)            /* PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD                 ((uint16_t)0x3000)            /* PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE                 ((uint16_t)0x4000)            /* PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF                 ((uint16_t)0x5000)            /* PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG                 ((uint16_t)0x6000)            /* PG[11] pin */
+
+/*****************  Bit definition for AFIO_EXTICR4 register  *****************/
+#define AFIO_EXTICR4_EXTI12                    ((uint16_t)0x000F)            /* EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13                    ((uint16_t)0x00F0)            /* EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14                    ((uint16_t)0x0F00)            /* EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15                    ((uint16_t)0xF000)            /* EXTI 15 configuration */
+
+#define AFIO_EXTICR4_EXTI12_PA                 ((uint16_t)0x0000)            /* PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB                 ((uint16_t)0x0001)            /* PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC                 ((uint16_t)0x0002)            /* PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD                 ((uint16_t)0x0003)            /* PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE                 ((uint16_t)0x0004)            /* PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF                 ((uint16_t)0x0005)            /* PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG                 ((uint16_t)0x0006)            /* PG[12] pin */
+
+#define AFIO_EXTICR4_EXTI13_PA                 ((uint16_t)0x0000)            /* PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB                 ((uint16_t)0x0010)            /* PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC                 ((uint16_t)0x0020)            /* PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD                 ((uint16_t)0x0030)            /* PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE                 ((uint16_t)0x0040)            /* PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF                 ((uint16_t)0x0050)            /* PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG                 ((uint16_t)0x0060)            /* PG[13] pin */
+
+#define AFIO_EXTICR4_EXTI14_PA                 ((uint16_t)0x0000)            /* PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB                 ((uint16_t)0x0100)            /* PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC                 ((uint16_t)0x0200)            /* PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD                 ((uint16_t)0x0300)            /* PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE                 ((uint16_t)0x0400)            /* PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF                 ((uint16_t)0x0500)            /* PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG                 ((uint16_t)0x0600)            /* PG[14] pin */
+
+#define AFIO_EXTICR4_EXTI15_PA                 ((uint16_t)0x0000)            /* PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB                 ((uint16_t)0x1000)            /* PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC                 ((uint16_t)0x2000)            /* PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD                 ((uint16_t)0x3000)            /* PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE                 ((uint16_t)0x4000)            /* PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF                 ((uint16_t)0x5000)            /* PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG                 ((uint16_t)0x6000)            /* PG[15] pin */
+
+/******************************************************************************/
+/*                           Independent WATCHDOG                             */
+/******************************************************************************/
+
+/*******************  Bit definition for IWDG_CTLR register  ********************/
+#define  IWDG_KEY                              ((uint16_t)0xFFFF)            /* Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PSCR register  ********************/
+#define  IWDG_PR                               ((uint8_t)0x07)               /* PR[2:0] (Prescaler divider) */
+#define  IWDG_PR_0                             ((uint8_t)0x01)               /* Bit 0 */
+#define  IWDG_PR_1                             ((uint8_t)0x02)               /* Bit 1 */
+#define  IWDG_PR_2                             ((uint8_t)0x04)               /* Bit 2 */
+
+/*******************  Bit definition for IWDG_RLDR register  *******************/
+#define  IWDG_RL                               ((uint16_t)0x0FFF)            /* Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_STATR register  ********************/
+#define  IWDG_PVU                              ((uint8_t)0x01)               /* Watchdog prescaler value update */
+#define  IWDG_RVU                              ((uint8_t)0x02)               /* Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                      Inter-integrated Circuit Interface                    */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CTLR1 register  ********************/
+#define  I2C_CTLR1_PE                          ((uint16_t)0x0001)            /* Peripheral Enable */
+#define  I2C_CTLR1_SMBUS                       ((uint16_t)0x0002)            /* SMBus Mode */
+#define  I2C_CTLR1_SMBTYPE                     ((uint16_t)0x0008)            /* SMBus Type */
+#define  I2C_CTLR1_ENARP                       ((uint16_t)0x0010)            /* ARP Enable */
+#define  I2C_CTLR1_ENPEC                       ((uint16_t)0x0020)            /* PEC Enable */
+#define  I2C_CTLR1_ENGC                        ((uint16_t)0x0040)            /* General Call Enable */
+#define  I2C_CTLR1_NOSTRETCH                   ((uint16_t)0x0080)            /* Clock Stretching Disable (Slave mode) */
+#define  I2C_CTLR1_START                       ((uint16_t)0x0100)            /* Start Generation */
+#define  I2C_CTLR1_STOP                        ((uint16_t)0x0200)            /* Stop Generation */
+#define  I2C_CTLR1_ACK                         ((uint16_t)0x0400)            /* Acknowledge Enable */
+#define  I2C_CTLR1_POS                         ((uint16_t)0x0800)            /* Acknowledge/PEC Position (for data reception) */
+#define  I2C_CTLR1_PEC                         ((uint16_t)0x1000)            /* Packet Error Checking */
+#define  I2C_CTLR1_ALERT                       ((uint16_t)0x2000)            /* SMBus Alert */
+#define  I2C_CTLR1_SWRST                       ((uint16_t)0x8000)            /* Software Reset */
+
+/*******************  Bit definition for I2C_CTLR2 register  ********************/
+#define  I2C_CTLR2_FREQ                        ((uint16_t)0x003F)            /* FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define  I2C_CTLR2_FREQ_0                      ((uint16_t)0x0001)            /* Bit 0 */
+#define  I2C_CTLR2_FREQ_1                      ((uint16_t)0x0002)            /* Bit 1 */
+#define  I2C_CTLR2_FREQ_2                      ((uint16_t)0x0004)            /* Bit 2 */
+#define  I2C_CTLR2_FREQ_3                      ((uint16_t)0x0008)            /* Bit 3 */
+#define  I2C_CTLR2_FREQ_4                      ((uint16_t)0x0010)            /* Bit 4 */
+#define  I2C_CTLR2_FREQ_5                      ((uint16_t)0x0020)            /* Bit 5 */
+
+#define  I2C_CTLR2_ITERREN                     ((uint16_t)0x0100)            /* Error Interrupt Enable */
+#define  I2C_CTLR2_ITEVTEN                     ((uint16_t)0x0200)            /* Event Interrupt Enable */
+#define  I2C_CTLR2_ITBUFEN                     ((uint16_t)0x0400)            /* Buffer Interrupt Enable */
+#define  I2C_CTLR2_DMAEN                       ((uint16_t)0x0800)            /* DMA Requests Enable */
+#define  I2C_CTLR2_LAST                        ((uint16_t)0x1000)            /* DMA Last Transfer */
+
+/*******************  Bit definition for I2C_OADDR1 register  *******************/
+#define  I2C_OADDR1_ADD1_7                     ((uint16_t)0x00FE)            /* Interface Address */
+#define  I2C_OADDR1_ADD8_9                     ((uint16_t)0x0300)            /* Interface Address */
+
+#define  I2C_OADDR1_ADD0                       ((uint16_t)0x0001)            /* Bit 0 */
+#define  I2C_OADDR1_ADD1                       ((uint16_t)0x0002)            /* Bit 1 */
+#define  I2C_OADDR1_ADD2                       ((uint16_t)0x0004)            /* Bit 2 */
+#define  I2C_OADDR1_ADD3                       ((uint16_t)0x0008)            /* Bit 3 */
+#define  I2C_OADDR1_ADD4                       ((uint16_t)0x0010)            /* Bit 4 */
+#define  I2C_OADDR1_ADD5                       ((uint16_t)0x0020)            /* Bit 5 */
+#define  I2C_OADDR1_ADD6                       ((uint16_t)0x0040)            /* Bit 6 */
+#define  I2C_OADDR1_ADD7                       ((uint16_t)0x0080)            /* Bit 7 */
+#define  I2C_OADDR1_ADD8                       ((uint16_t)0x0100)            /* Bit 8 */
+#define  I2C_OADDR1_ADD9                       ((uint16_t)0x0200)            /* Bit 9 */
+
+#define  I2C_OADDR1_ADDMODE                    ((uint16_t)0x8000)            /* Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OADDR2 register  *******************/
+#define  I2C_OADDR2_ENDUAL                     ((uint8_t)0x01)               /* Dual addressing mode enable */
+#define  I2C_OADDR2_ADD2                       ((uint8_t)0xFE)               /* Interface address */
+
+/********************  Bit definition for I2C_DATAR register  ********************/
+#define  I2C_DR_DATAR                          ((uint8_t)0xFF)               /* 8-bit Data Register */
+
+/*******************  Bit definition for I2C_STAR1 register  ********************/
+#define  I2C_STAR1_SB                          ((uint16_t)0x0001)            /* Start Bit (Master mode) */
+#define  I2C_STAR1_ADDR                        ((uint16_t)0x0002)            /* Address sent (master mode)/matched (slave mode) */
+#define  I2C_STAR1_BTF                         ((uint16_t)0x0004)            /* Byte Transfer Finished */
+#define  I2C_STAR1_ADD10                       ((uint16_t)0x0008)            /* 10-bit header sent (Master mode) */
+#define  I2C_STAR1_STOPF                       ((uint16_t)0x0010)            /* Stop detection (Slave mode) */
+#define  I2C_STAR1_RXNE                        ((uint16_t)0x0040)            /* Data Register not Empty (receivers) */
+#define  I2C_STAR1_TXE                         ((uint16_t)0x0080)            /* Data Register Empty (transmitters) */
+#define  I2C_STAR1_BERR                        ((uint16_t)0x0100)            /* Bus Error */
+#define  I2C_STAR1_ARLO                        ((uint16_t)0x0200)            /* Arbitration Lost (master mode) */
+#define  I2C_STAR1_AF                          ((uint16_t)0x0400)            /* Acknowledge Failure */
+#define  I2C_STAR1_OVR                         ((uint16_t)0x0800)            /* Overrun/Underrun */
+#define  I2C_STAR1_PECERR                      ((uint16_t)0x1000)            /* PEC Error in reception */
+#define  I2C_STAR1_TIMEOUT                     ((uint16_t)0x4000)            /* Timeout or Tlow Error */
+#define  I2C_STAR1_SMBALERT                    ((uint16_t)0x8000)            /* SMBus Alert */
+
+/*******************  Bit definition for I2C_STAR2 register  ********************/
+#define  I2C_STAR2_MSL                         ((uint16_t)0x0001)            /* Master/Slave */
+#define  I2C_STAR2_BUSY                        ((uint16_t)0x0002)            /* Bus Busy */
+#define  I2C_STAR2_TRA                         ((uint16_t)0x0004)            /* Transmitter/Receiver */
+#define  I2C_STAR2_GENCALL                     ((uint16_t)0x0010)            /* General Call Address (Slave mode) */
+#define  I2C_STAR2_SMBDEFAULT                  ((uint16_t)0x0020)            /* SMBus Device Default Address (Slave mode) */
+#define  I2C_STAR2_SMBHOST                     ((uint16_t)0x0040)            /* SMBus Host Header (Slave mode) */
+#define  I2C_STAR2_DUALF                       ((uint16_t)0x0080)            /* Dual Flag (Slave mode) */
+#define  I2C_STAR2_PEC                         ((uint16_t)0xFF00)            /* Packet Error Checking Register */
+
+/*******************  Bit definition for I2C_CKCFGR register  ********************/
+#define  I2C_CKCFGR_CCR                        ((uint16_t)0x0FFF)            /* Clock Control Register in Fast/Standard mode (Master mode) */
+#define  I2C_CKCFGR_DUTY                       ((uint16_t)0x4000)            /* Fast Mode Duty Cycle */
+#define  I2C_CKCFGR_FS                         ((uint16_t)0x8000)            /* I2C Master Mode Selection */
+
+/******************  Bit definition for I2C_RTR register  *******************/
+#define  I2C_RTR_TRISE                         ((uint8_t)0x3F)               /* Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+
+/******************************************************************************/
+/*                             Power Control                                  */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CTLR register  ********************/
+#define  PWR_CTLR_LPDS                         ((uint16_t)0x0001)     /* Low-Power Deepsleep */
+#define  PWR_CTLR_PDDS                         ((uint16_t)0x0002)     /* Power Down Deepsleep */
+#define  PWR_CTLR_CWUF                         ((uint16_t)0x0004)     /* Clear Wakeup Flag */
+#define  PWR_CTLR_CSBF                         ((uint16_t)0x0008)     /* Clear Standby Flag */
+#define  PWR_CTLR_PVDE                         ((uint16_t)0x0010)     /* Power Voltage Detector Enable */
+
+#define  PWR_CTLR_PLS                          ((uint16_t)0x00E0)     /* PLS[2:0] bits (PVD Level Selection) */
+#define  PWR_CTLR_PLS_0                        ((uint16_t)0x0020)     /* Bit 0 */
+#define  PWR_CTLR_PLS_1                        ((uint16_t)0x0040)     /* Bit 1 */
+#define  PWR_CTLR_PLS_2                        ((uint16_t)0x0080)     /* Bit 2 */
+
+#define  PWR_CTLR_PLS_2V2                      ((uint16_t)0x0000)     /* PVD level 2.2V */
+#define  PWR_CTLR_PLS_2V3                      ((uint16_t)0x0020)     /* PVD level 2.3V */
+#define  PWR_CTLR_PLS_2V4                      ((uint16_t)0x0040)     /* PVD level 2.4V */
+#define  PWR_CTLR_PLS_2V5                      ((uint16_t)0x0060)     /* PVD level 2.5V */
+#define  PWR_CTLR_PLS_2V6                      ((uint16_t)0x0080)     /* PVD level 2.6V */
+#define  PWR_CTLR_PLS_2V7                      ((uint16_t)0x00A0)     /* PVD level 2.7V */
+#define  PWR_CTLR_PLS_2V8                      ((uint16_t)0x00C0)     /* PVD level 2.8V */
+#define  PWR_CTLR_PLS_2V9                      ((uint16_t)0x00E0)     /* PVD level 2.9V */
+
+#define  PWR_CTLR_DBP                          ((uint16_t)0x0100)     /* Disable Backup Domain write protection */
+
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define  PWR_CSR_WUF                           ((uint16_t)0x0001)     /* Wakeup Flag */
+#define  PWR_CSR_SBF                           ((uint16_t)0x0002)     /* Standby Flag */
+#define  PWR_CSR_PVDO                          ((uint16_t)0x0004)     /* PVD Output */
+#define  PWR_CSR_EWUP                          ((uint16_t)0x0100)     /* Enable WKUP pin */
+
+
+
+/******************************************************************************/
+/*                         Reset and Clock Control                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CTLR register  ********************/
+#define  RCC_HSION                       ((uint32_t)0x00000001)        /* Internal High Speed clock enable */
+#define  RCC_HSIRDY                      ((uint32_t)0x00000002)        /* Internal High Speed clock ready flag */
+#define  RCC_HSITRIM                     ((uint32_t)0x000000F8)        /* Internal High Speed clock trimming */
+#define  RCC_HSICAL                      ((uint32_t)0x0000FF00)        /* Internal High Speed clock Calibration */
+#define  RCC_HSEON                       ((uint32_t)0x00010000)        /* External High Speed clock enable */
+#define  RCC_HSERDY                      ((uint32_t)0x00020000)        /* External High Speed clock ready flag */
+#define  RCC_HSEBYP                      ((uint32_t)0x00040000)        /* External High Speed clock Bypass */
+#define  RCC_CSSON                       ((uint32_t)0x00080000)        /* Clock Security System enable */
+#define  RCC_PLLON                       ((uint32_t)0x01000000)        /* PLL enable */
+#define  RCC_PLLRDY                      ((uint32_t)0x02000000)        /* PLL clock ready flag */
+
+
+/*******************  Bit definition for RCC_CFGR0 register  *******************/
+#define  RCC_SW                          ((uint32_t)0x00000003)        /* SW[1:0] bits (System clock Switch) */
+#define  RCC_SW_0                        ((uint32_t)0x00000001)        /* Bit 0 */
+#define  RCC_SW_1                        ((uint32_t)0x00000002)        /* Bit 1 */
+
+#define  RCC_SW_HSI                      ((uint32_t)0x00000000)        /* HSI selected as system clock */
+#define  RCC_SW_HSE                      ((uint32_t)0x00000001)        /* HSE selected as system clock */
+#define  RCC_SW_PLL                      ((uint32_t)0x00000002)        /* PLL selected as system clock */
+
+#define  RCC_SWS                         ((uint32_t)0x0000000C)        /* SWS[1:0] bits (System Clock Switch Status) */
+#define  RCC_SWS_0                       ((uint32_t)0x00000004)        /* Bit 0 */
+#define  RCC_SWS_1                       ((uint32_t)0x00000008)        /* Bit 1 */
+
+#define  RCC_SWS_HSI                     ((uint32_t)0x00000000)        /* HSI oscillator used as system clock */
+#define  RCC_SWS_HSE                     ((uint32_t)0x00000004)        /* HSE oscillator used as system clock */
+#define  RCC_SWS_PLL                     ((uint32_t)0x00000008)        /* PLL used as system clock */
+
+#define  RCC_HPRE                        ((uint32_t)0x000000F0)        /* HPRE[3:0] bits (AHB prescaler) */
+#define  RCC_HPRE_0                      ((uint32_t)0x00000010)        /* Bit 0 */
+#define  RCC_HPRE_1                      ((uint32_t)0x00000020)        /* Bit 1 */
+#define  RCC_HPRE_2                      ((uint32_t)0x00000040)        /* Bit 2 */
+#define  RCC_HPRE_3                      ((uint32_t)0x00000080)        /* Bit 3 */
+
+#define  RCC_HPRE_DIV1                   ((uint32_t)0x00000000)        /* SYSCLK not divided */
+#define  RCC_HPRE_DIV2                   ((uint32_t)0x00000080)        /* SYSCLK divided by 2 */
+#define  RCC_HPRE_DIV4                   ((uint32_t)0x00000090)        /* SYSCLK divided by 4 */
+#define  RCC_HPRE_DIV8                   ((uint32_t)0x000000A0)        /* SYSCLK divided by 8 */
+#define  RCC_HPRE_DIV16                  ((uint32_t)0x000000B0)        /* SYSCLK divided by 16 */
+#define  RCC_HPRE_DIV64                  ((uint32_t)0x000000C0)        /* SYSCLK divided by 64 */
+#define  RCC_HPRE_DIV128                 ((uint32_t)0x000000D0)        /* SYSCLK divided by 128 */
+#define  RCC_HPRE_DIV256                 ((uint32_t)0x000000E0)        /* SYSCLK divided by 256 */
+#define  RCC_HPRE_DIV512                 ((uint32_t)0x000000F0)        /* SYSCLK divided by 512 */
+
+#define  RCC_PPRE1                       ((uint32_t)0x00000700)        /* PRE1[2:0] bits (APB1 prescaler) */
+#define  RCC_PPRE1_0                     ((uint32_t)0x00000100)        /* Bit 0 */
+#define  RCC_PPRE1_1                     ((uint32_t)0x00000200)        /* Bit 1 */
+#define  RCC_PPRE1_2                     ((uint32_t)0x00000400)        /* Bit 2 */
+
+#define  RCC_PPRE1_DIV1                  ((uint32_t)0x00000000)        /* HCLK not divided */
+#define  RCC_PPRE1_DIV2                  ((uint32_t)0x00000400)        /* HCLK divided by 2 */
+#define  RCC_PPRE1_DIV4                  ((uint32_t)0x00000500)        /* HCLK divided by 4 */
+#define  RCC_PPRE1_DIV8                  ((uint32_t)0x00000600)        /* HCLK divided by 8 */
+#define  RCC_PPRE1_DIV16                 ((uint32_t)0x00000700)        /* HCLK divided by 16 */
+
+#define  RCC_PPRE2                       ((uint32_t)0x00003800)        /* PRE2[2:0] bits (APB2 prescaler) */
+#define  RCC_PPRE2_0                     ((uint32_t)0x00000800)        /* Bit 0 */
+#define  RCC_PPRE2_1                     ((uint32_t)0x00001000)        /* Bit 1 */
+#define  RCC_PPRE2_2                     ((uint32_t)0x00002000)        /* Bit 2 */
+
+#define  RCC_PPRE2_DIV1                  ((uint32_t)0x00000000)        /* HCLK not divided */
+#define  RCC_PPRE2_DIV2                  ((uint32_t)0x00002000)        /* HCLK divided by 2 */
+#define  RCC_PPRE2_DIV4                  ((uint32_t)0x00002800)        /* HCLK divided by 4 */
+#define  RCC_PPRE2_DIV8                  ((uint32_t)0x00003000)        /* HCLK divided by 8 */
+#define  RCC_PPRE2_DIV16                 ((uint32_t)0x00003800)        /* HCLK divided by 16 */
+
+#define  RCC_ADCPRE                      ((uint32_t)0x0000C000)        /* ADCPRE[1:0] bits (ADC prescaler) */
+#define  RCC_ADCPRE_0                    ((uint32_t)0x00004000)        /* Bit 0 */
+#define  RCC_ADCPRE_1                    ((uint32_t)0x00008000)        /* Bit 1 */
+
+#define  RCC_ADCPRE_DIV2                 ((uint32_t)0x00000000)        /* PCLK2 divided by 2 */
+#define  RCC_ADCPRE_DIV4                 ((uint32_t)0x00004000)        /* PCLK2 divided by 4 */
+#define  RCC_ADCPRE_DIV6                 ((uint32_t)0x00008000)        /* PCLK2 divided by 6 */
+#define  RCC_ADCPRE_DIV8                 ((uint32_t)0x0000C000)        /* PCLK2 divided by 8 */
+
+#define  RCC_PLLSRC                      ((uint32_t)0x00010000)        /* PLL entry clock source */
+
+#define  RCC_PLLXTPRE                    ((uint32_t)0x00020000)        /* HSE divider for PLL entry */
+
+#define  RCC_PLLMULL                     ((uint32_t)0x003C0000)        /* PLLMUL[3:0] bits (PLL multiplication factor) */
+#define  RCC_PLLMULL_0                   ((uint32_t)0x00040000)        /* Bit 0 */
+#define  RCC_PLLMULL_1                   ((uint32_t)0x00080000)        /* Bit 1 */
+#define  RCC_PLLMULL_2                   ((uint32_t)0x00100000)        /* Bit 2 */
+#define  RCC_PLLMULL_3                   ((uint32_t)0x00200000)        /* Bit 3 */
+ 
+#define  RCC_PLLSRC_HSI_Div2             ((uint32_t)0x00000000)        /* HSI clock divided by 2 selected as PLL entry clock source */
+#define  RCC_PLLSRC_HSE                  ((uint32_t)0x00010000)        /* HSE clock selected as PLL entry clock source */
+ 
+#define  RCC_PLLXTPRE_HSE                ((uint32_t)0x00000000)        /* HSE clock not divided for PLL entry */
+#define  RCC_PLLXTPRE_HSE_Div2           ((uint32_t)0x00020000)        /* HSE clock divided by 2 for PLL entry */
+
+/* for other CH32V30x */
+#define  RCC_PLLMULL2                    ((uint32_t)0x00000000)        /* PLL input clock*2 */
+#define  RCC_PLLMULL3                    ((uint32_t)0x00040000)        /* PLL input clock*3 */
+#define  RCC_PLLMULL4                    ((uint32_t)0x00080000)        /* PLL input clock*4 */
+#define  RCC_PLLMULL5                    ((uint32_t)0x000C0000)        /* PLL input clock*5 */
+#define  RCC_PLLMULL6                    ((uint32_t)0x00100000)        /* PLL input clock*6 */
+#define  RCC_PLLMULL7                    ((uint32_t)0x00140000)        /* PLL input clock*7 */
+#define  RCC_PLLMULL8                    ((uint32_t)0x00180000)        /* PLL input clock*8 */
+#define  RCC_PLLMULL9                    ((uint32_t)0x001C0000)        /* PLL input clock*9 */
+#define  RCC_PLLMULL10                   ((uint32_t)0x00200000)        /* PLL input clock10 */
+#define  RCC_PLLMULL11                   ((uint32_t)0x00240000)        /* PLL input clock*11 */
+#define  RCC_PLLMULL12                   ((uint32_t)0x00280000)        /* PLL input clock*12 */
+#define  RCC_PLLMULL13                   ((uint32_t)0x002C0000)        /* PLL input clock*13 */
+#define  RCC_PLLMULL14                   ((uint32_t)0x00300000)        /* PLL input clock*14 */
+#define  RCC_PLLMULL15                   ((uint32_t)0x00340000)        /* PLL input clock*15 */
+#define  RCC_PLLMULL16                   ((uint32_t)0x00380000)        /* PLL input clock*16 */
+#define  RCC_PLLMULL18                   ((uint32_t)0x003C0000)        /* PLL input clock*18 */
+/* for CH32V307 */
+#define  RCC_PLLMULL18_EXTEN             ((uint32_t)0x00000000)        /* PLL input clock*18 */
+#define  RCC_PLLMULL3_EXTEN              ((uint32_t)0x00040000)        /* PLL input clock*3 */
+#define  RCC_PLLMULL4_EXTEN              ((uint32_t)0x00080000)        /* PLL input clock*4 */
+#define  RCC_PLLMULL5_EXTEN              ((uint32_t)0x000C0000)        /* PLL input clock*5 */
+#define  RCC_PLLMULL6_EXTEN              ((uint32_t)0x00100000)        /* PLL input clock*6 */
+#define  RCC_PLLMULL7_EXTEN              ((uint32_t)0x00140000)        /* PLL input clock*7 */
+#define  RCC_PLLMULL8_EXTEN              ((uint32_t)0x00180000)        /* PLL input clock*8 */
+#define  RCC_PLLMULL9_EXTEN              ((uint32_t)0x001C0000)        /* PLL input clock*9 */
+#define  RCC_PLLMULL10_EXTEN             ((uint32_t)0x00200000)        /* PLL input clock10 */
+#define  RCC_PLLMULL11_EXTEN             ((uint32_t)0x00240000)        /* PLL input clock*11 */
+#define  RCC_PLLMULL12_EXTEN             ((uint32_t)0x00280000)        /* PLL input clock*12 */
+#define  RCC_PLLMULL13_EXTEN             ((uint32_t)0x002C0000)        /* PLL input clock*13 */
+#define  RCC_PLLMULL14_EXTEN             ((uint32_t)0x00300000)        /* PLL input clock*14 */
+#define  RCC_PLLMULL6_5_EXTEN            ((uint32_t)0x00340000)        /* PLL input clock*6.5 */
+#define  RCC_PLLMULL15_EXTEN             ((uint32_t)0x00380000)        /* PLL input clock*15 */
+#define  RCC_PLLMULL16_EXTEN             ((uint32_t)0x003C0000)        /* PLL input clock*16 */
+
+#define  RCC_USBPRE                      ((uint32_t)0x00400000)        /* USB Device prescaler */
+
+#define  RCC_CFGR0_MCO                   ((uint32_t)0x07000000)        /* MCO[2:0] bits (Microcontroller Clock Output) */
+#define  RCC_MCO_0                       ((uint32_t)0x01000000)        /* Bit 0 */
+#define  RCC_MCO_1                       ((uint32_t)0x02000000)        /* Bit 1 */
+#define  RCC_MCO_2                       ((uint32_t)0x04000000)        /* Bit 2 */
+
+#define  RCC_MCO_NOCLOCK                 ((uint32_t)0x00000000)        /* No clock */
+#define  RCC_CFGR0_MCO_SYSCLK            ((uint32_t)0x04000000)        /* System clock selected as MCO source */
+#define  RCC_CFGR0_MCO_HSI               ((uint32_t)0x05000000)        /* HSI clock selected as MCO source */
+#define  RCC_CFGR0_MCO_HSE               ((uint32_t)0x06000000)        /* HSE clock selected as MCO source  */
+#define  RCC_CFGR0_MCO_PLL               ((uint32_t)0x07000000)        /* PLL clock divided by 2 selected as MCO source */
+
+/*******************  Bit definition for RCC_INTR register  ********************/
+#define  RCC_LSIRDYF                     ((uint32_t)0x00000001)        /* LSI Ready Interrupt flag */
+#define  RCC_LSERDYF                     ((uint32_t)0x00000002)        /* LSE Ready Interrupt flag */
+#define  RCC_HSIRDYF                     ((uint32_t)0x00000004)        /* HSI Ready Interrupt flag */
+#define  RCC_HSERDYF                     ((uint32_t)0x00000008)        /* HSE Ready Interrupt flag */
+#define  RCC_PLLRDYF                     ((uint32_t)0x00000010)        /* PLL Ready Interrupt flag */
+#define  RCC_CSSF                        ((uint32_t)0x00000080)        /* Clock Security System Interrupt flag */
+#define  RCC_LSIRDYIE                    ((uint32_t)0x00000100)        /* LSI Ready Interrupt Enable */
+#define  RCC_LSERDYIE                    ((uint32_t)0x00000200)        /* LSE Ready Interrupt Enable */
+#define  RCC_HSIRDYIE                    ((uint32_t)0x00000400)        /* HSI Ready Interrupt Enable */
+#define  RCC_HSERDYIE                    ((uint32_t)0x00000800)        /* HSE Ready Interrupt Enable */
+#define  RCC_PLLRDYIE                    ((uint32_t)0x00001000)        /* PLL Ready Interrupt Enable */
+#define  RCC_LSIRDYC                     ((uint32_t)0x00010000)        /* LSI Ready Interrupt Clear */
+#define  RCC_LSERDYC                     ((uint32_t)0x00020000)        /* LSE Ready Interrupt Clear */
+#define  RCC_HSIRDYC                     ((uint32_t)0x00040000)        /* HSI Ready Interrupt Clear */
+#define  RCC_HSERDYC                     ((uint32_t)0x00080000)        /* HSE Ready Interrupt Clear */
+#define  RCC_PLLRDYC                     ((uint32_t)0x00100000)        /* PLL Ready Interrupt Clear */
+#define  RCC_CSSC                        ((uint32_t)0x00800000)        /* Clock Security System Interrupt Clear */
+
+
+/*****************  Bit definition for RCC_APB2PRSTR register  *****************/
+#define  RCC_AFIORST                     ((uint32_t)0x00000001)        /* Alternate Function I/O reset */
+#define  RCC_IOPARST                     ((uint32_t)0x00000004)        /* I/O port A reset */
+#define  RCC_IOPBRST                     ((uint32_t)0x00000008)        /* I/O port B reset */
+#define  RCC_IOPCRST                     ((uint32_t)0x00000010)        /* I/O port C reset */
+#define  RCC_IOPDRST                     ((uint32_t)0x00000020)        /* I/O port D reset */
+#define  RCC_ADC1RST                     ((uint32_t)0x00000200)        /* ADC 1 interface reset */
+
+
+#define  RCC_ADC2RST                     ((uint32_t)0x00000400)        /* ADC 2 interface reset */
+
+
+#define  RCC_TIM1RST                     ((uint32_t)0x00000800)        /* TIM1 Timer reset */
+#define  RCC_SPI1RST                     ((uint32_t)0x00001000)        /* SPI 1 reset */
+#define  RCC_USART1RST                   ((uint32_t)0x00004000)        /* USART1 reset */
+
+#define  RCC_IOPERST                     ((uint32_t)0x00000040)        /* I/O port E reset */
+
+/*****************  Bit definition for RCC_APB1PRSTR register  *****************/
+#define  RCC_TIM2RST                     ((uint32_t)0x00000001)        /* Timer 2 reset */
+#define  RCC_TIM3RST                     ((uint32_t)0x00000002)        /* Timer 3 reset */
+#define  RCC_WWDGRST                     ((uint32_t)0x00000800)        /* Window Watchdog reset */
+#define  RCC_USART2RST                   ((uint32_t)0x00020000)        /* USART 2 reset */
+#define  RCC_I2C1RST                     ((uint32_t)0x00200000)        /* I2C 1 reset */
+  
+#define  RCC_CAN1RST                     ((uint32_t)0x02000000)        /* CAN1 reset */
+
+
+#define  RCC_BKPRST                      ((uint32_t)0x08000000)        /* Backup interface reset */
+#define  RCC_PWRRST                      ((uint32_t)0x10000000)        /* Power interface reset */
+
+
+#define  RCC_TIM4RST                     ((uint32_t)0x00000004)        /* Timer 4 reset */
+#define  RCC_SPI2RST                     ((uint32_t)0x00004000)        /* SPI 2 reset */
+#define  RCC_USART3RST                   ((uint32_t)0x00040000)        /* USART 3 reset */
+#define  RCC_I2C2RST                     ((uint32_t)0x00400000)        /* I2C 2 reset */
+
+#define  RCC_USBRST                      ((uint32_t)0x00800000)        /* USB Device reset */
+
+/******************  Bit definition for RCC_AHBPCENR register  ******************/
+#define  RCC_DMA1EN                      ((uint16_t)0x0001)            /* DMA1 clock enable */
+#define  RCC_SRAMEN                      ((uint16_t)0x0004)            /* SRAM interface clock enable */
+#define  RCC_FLITFEN                     ((uint16_t)0x0010)            /* FLITF clock enable */
+#define  RCC_CRCEN                       ((uint16_t)0x0040)            /* CRC clock enable */
+#define  RCC_USBHD                       ((uint16_t)0x1000)
+
+/******************  Bit definition for RCC_APB2PCENR register  *****************/
+#define  RCC_AFIOEN                      ((uint32_t)0x00000001)         /* Alternate Function I/O clock enable */
+#define  RCC_IOPAEN                      ((uint32_t)0x00000004)         /* I/O port A clock enable */
+#define  RCC_IOPBEN                      ((uint32_t)0x00000008)         /* I/O port B clock enable */
+#define  RCC_IOPCEN                      ((uint32_t)0x00000010)         /* I/O port C clock enable */
+#define  RCC_IOPDEN                      ((uint32_t)0x00000020)         /* I/O port D clock enable */
+#define  RCC_ADC1EN                      ((uint32_t)0x00000200)         /* ADC 1 interface clock enable */
+
+#define  RCC_ADC2EN                      ((uint32_t)0x00000400)         /* ADC 2 interface clock enable */
+
+
+#define  RCC_TIM1EN                      ((uint32_t)0x00000800)         /* TIM1 Timer clock enable */
+#define  RCC_SPI1EN                      ((uint32_t)0x00001000)         /* SPI 1 clock enable */
+#define  RCC_USART1EN                    ((uint32_t)0x00004000)         /* USART1 clock enable */
+
+/*****************  Bit definition for RCC_APB1PCENR register  ******************/
+#define  RCC_TIM2EN                      ((uint32_t)0x00000001)        /* Timer 2 clock enabled*/
+#define  RCC_TIM3EN                      ((uint32_t)0x00000002)        /* Timer 3 clock enable */
+#define  RCC_WWDGEN                      ((uint32_t)0x00000800)        /* Window Watchdog clock enable */
+#define  RCC_USART2EN                    ((uint32_t)0x00020000)        /* USART 2 clock enable */
+#define  RCC_I2C1EN                      ((uint32_t)0x00200000)        /* I2C 1 clock enable */
+
+#define  RCC_BKPEN                       ((uint32_t)0x08000000)        /* Backup interface clock enable */
+#define  RCC_PWREN                       ((uint32_t)0x10000000)        /* Power interface clock enable */
+
+
+#define  RCC_USBEN                       ((uint32_t)0x00800000)        /* USB Device clock enable */
+
+/*******************  Bit definition for RCC_BDCTLR register  *******************/
+#define  RCC_LSEON                       ((uint32_t)0x00000001)        /* External Low Speed oscillator enable */
+#define  RCC_LSERDY                      ((uint32_t)0x00000002)        /* External Low Speed oscillator Ready */
+#define  RCC_LSEBYP                      ((uint32_t)0x00000004)        /* External Low Speed oscillator Bypass */
+
+#define  RCC_RTCSEL                      ((uint32_t)0x00000300)        /* RTCSEL[1:0] bits (RTC clock source selection) */
+#define  RCC_RTCSEL_0                    ((uint32_t)0x00000100)        /* Bit 0 */
+#define  RCC_RTCSEL_1                    ((uint32_t)0x00000200)        /* Bit 1 */
+
+#define  RCC_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)        /* No clock */
+#define  RCC_RTCSEL_LSE                  ((uint32_t)0x00000100)        /* LSE oscillator clock used as RTC clock */
+#define  RCC_RTCSEL_LSI                  ((uint32_t)0x00000200)        /* LSI oscillator clock used as RTC clock */
+#define  RCC_RTCSEL_HSE                  ((uint32_t)0x00000300)        /* HSE oscillator clock divided by 128 used as RTC clock */
+
+#define  RCC_RTCEN                       ((uint32_t)0x00008000)        /* RTC clock enable */
+#define  RCC_BDRST                       ((uint32_t)0x00010000)        /* Backup domain software reset  */
+
+/*******************  Bit definition for RCC_RSTSCKR register  ********************/  
+#define  RCC_LSION                       ((uint32_t)0x00000001)        /* Internal Low Speed oscillator enable */
+#define  RCC_LSIRDY                      ((uint32_t)0x00000002)        /* Internal Low Speed oscillator Ready */
+#define  RCC_RMVF                        ((uint32_t)0x01000000)        /* Remove reset flag */
+#define  RCC_PINRSTF                     ((uint32_t)0x04000000)        /* PIN reset flag */
+#define  RCC_PORRSTF                     ((uint32_t)0x08000000)        /* POR/PDR reset flag */
+#define  RCC_SFTRSTF                     ((uint32_t)0x10000000)        /* Software Reset flag */
+#define  RCC_IWDGRSTF                    ((uint32_t)0x20000000)        /* Independent Watchdog reset flag */
+#define  RCC_WWDGRSTF                    ((uint32_t)0x40000000)        /* Window watchdog reset flag */
+#define  RCC_LPWRRSTF                    ((uint32_t)0x80000000)        /* Low-Power reset flag */
+
+/******************************************************************************/
+/*                                    RNG                                     */
+/******************************************************************************/
+/********************  Bit definition for RNG_CR register  *******************/
+#define  RNG_CR_RNGEN                         ((uint32_t)0x00000004)
+#define  RNG_CR_IE                            ((uint32_t)0x00000008)
+
+/********************  Bit definition for RNG_SR register  *******************/
+#define  RNG_SR_DRDY                          ((uint32_t)0x00000001)
+#define  RNG_SR_CECS                          ((uint32_t)0x00000002)
+#define  RNG_SR_SECS                          ((uint32_t)0x00000004)
+#define  RNG_SR_CEIS                          ((uint32_t)0x00000020)
+#define  RNG_SR_SEIS                          ((uint32_t)0x00000040)
+
+/******************************************************************************/
+/*                             Real-Time Clock                                */
+/******************************************************************************/
+
+/*******************  Bit definition for RTC_CTLRH register  ********************/
+#define  RTC_CTLRH_SECIE                     ((uint8_t)0x01)               /* Second Interrupt Enable */
+#define  RTC_CTLRH_ALRIE                     ((uint8_t)0x02)               /* Alarm Interrupt Enable */
+#define  RTC_CTLRH_OWIE                      ((uint8_t)0x04)               /* OverfloW Interrupt Enable */
+
+/*******************  Bit definition for RTC_CTLRL register  ********************/
+#define  RTC_CTLRL_SECF                      ((uint8_t)0x01)               /* Second Flag */
+#define  RTC_CTLRL_ALRF                      ((uint8_t)0x02)               /* Alarm Flag */
+#define  RTC_CTLRL_OWF                       ((uint8_t)0x04)               /* OverfloW Flag */
+#define  RTC_CTLRL_RSF                       ((uint8_t)0x08)               /* Registers Synchronized Flag */
+#define  RTC_CTLRL_CNF                       ((uint8_t)0x10)               /* Configuration Flag */
+#define  RTC_CTLRL_RTOFF                     ((uint8_t)0x20)               /* RTC operation OFF */
+
+/*******************  Bit definition for RTC_PSCH register  *******************/
+#define  RTC_PSCH_PRL                        ((uint16_t)0x000F)            /* RTC Prescaler Reload Value High */
+
+/*******************  Bit definition for RTC_PRLL register  *******************/
+#define  RTC_PSCL_PRL                        ((uint16_t)0xFFFF)            /* RTC Prescaler Reload Value Low */
+
+/*******************  Bit definition for RTC_DIVH register  *******************/
+#define  RTC_DIVH_RTC_DIV                    ((uint16_t)0x000F)            /* RTC Clock Divider High */
+
+/*******************  Bit definition for RTC_DIVL register  *******************/
+#define  RTC_DIVL_RTC_DIV                    ((uint16_t)0xFFFF)            /* RTC Clock Divider Low */
+
+/*******************  Bit definition for RTC_CNTH register  *******************/
+#define  RTC_CNTH_RTC_CNT                    ((uint16_t)0xFFFF)            /* RTC Counter High */
+
+/*******************  Bit definition for RTC_CNTL register  *******************/
+#define  RTC_CNTL_RTC_CNT                    ((uint16_t)0xFFFF)            /* RTC Counter Low */
+
+/*******************  Bit definition for RTC_ALRMH register  *******************/
+#define  RTC_ALRMH_RTC_ALRM                  ((uint16_t)0xFFFF)            /* RTC Alarm High */
+
+/*******************  Bit definition for RTC_ALRML register  *******************/
+#define  RTC_ALRML_RTC_ALRM                  ((uint16_t)0xFFFF)            /* RTC Alarm Low */
+
+/******************************************************************************/
+/*                        Serial Peripheral Interface                         */
+/******************************************************************************/
+
+/*******************  Bit definition for SPI_CTLR1 register  ********************/
+#define  SPI_CTLR1_CPHA                      ((uint16_t)0x0001)            /* Clock Phase */
+#define  SPI_CTLR1_CPOL                      ((uint16_t)0x0002)            /* Clock Polarity */
+#define  SPI_CTLR1_MSTR                      ((uint16_t)0x0004)            /* Master Selection */
+
+#define  SPI_CTLR1_BR                        ((uint16_t)0x0038)            /* BR[2:0] bits (Baud Rate Control) */
+#define  SPI_CTLR1_BR_0                      ((uint16_t)0x0008)            /* Bit 0 */
+#define  SPI_CTLR1_BR_1                      ((uint16_t)0x0010)            /* Bit 1 */
+#define  SPI_CTLR1_BR_2                      ((uint16_t)0x0020)            /* Bit 2 */
+
+#define  SPI_CTLR1_SPE                       ((uint16_t)0x0040)            /* SPI Enable */
+#define  SPI_CTLR1_LSBFIRST                  ((uint16_t)0x0080)            /* Frame Format */
+#define  SPI_CTLR1_SSI                       ((uint16_t)0x0100)            /* Internal slave select */
+#define  SPI_CTLR1_SSM                       ((uint16_t)0x0200)            /* Software slave management */
+#define  SPI_CTLR1_RXONLY                    ((uint16_t)0x0400)            /* Receive only */
+#define  SPI_CTLR1_DFF                       ((uint16_t)0x0800)            /* Data Frame Format */
+#define  SPI_CTLR1_CRCNEXT                   ((uint16_t)0x1000)            /* Transmit CRC next */
+#define  SPI_CTLR1_CRCEN                     ((uint16_t)0x2000)            /* Hardware CRC calculation enable */
+#define  SPI_CTLR1_BIDIOE                    ((uint16_t)0x4000)            /* Output enable in bidirectional mode */
+#define  SPI_CTLR1_BIDIMODE                  ((uint16_t)0x8000)            /* Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CTLR2 register  ********************/
+#define  SPI_CTLR2_RXDMAEN                   ((uint8_t)0x01)               /* Rx Buffer DMA Enable */
+#define  SPI_CTLR2_TXDMAEN                   ((uint8_t)0x02)               /* Tx Buffer DMA Enable */
+#define  SPI_CTLR2_SSOE                      ((uint8_t)0x04)               /* SS Output Enable */
+#define  SPI_CTLR2_ERRIE                     ((uint8_t)0x20)               /* Error Interrupt Enable */
+#define  SPI_CTLR2_RXNEIE                    ((uint8_t)0x40)               /* RX buffer Not Empty Interrupt Enable */
+#define  SPI_CTLR2_TXEIE                     ((uint8_t)0x80)               /* Tx buffer Empty Interrupt Enable */
+
+/********************  Bit definition for SPI_STATR register  ********************/
+#define  SPI_STATR_RXNE                      ((uint8_t)0x01)               /* Receive buffer Not Empty */
+#define  SPI_STATR_TXE                       ((uint8_t)0x02)               /* Transmit buffer Empty */
+#define  SPI_STATR_CHSIDE                    ((uint8_t)0x04)               /* Channel side */
+#define  SPI_STATR_UDR                       ((uint8_t)0x08)               /* Underrun flag */
+#define  SPI_STATR_CRCERR                    ((uint8_t)0x10)               /* CRC Error flag */
+#define  SPI_STATR_MODF                      ((uint8_t)0x20)               /* Mode fault */
+#define  SPI_STATR_OVR                       ((uint8_t)0x40)               /* Overrun flag */
+#define  SPI_STATR_BSY                       ((uint8_t)0x80)               /* Busy flag */
+
+/********************  Bit definition for SPI_DATAR register  ********************/
+#define  SPI_DATAR_DR                        ((uint16_t)0xFFFF)            /* Data Register */
+
+/*******************  Bit definition for SPI_CRCR register  ******************/
+#define  SPI_CRCR_CRCPOLY                    ((uint16_t)0xFFFF)            /* CRC polynomial register */
+
+/******************  Bit definition for SPI_RCRCR register  ******************/
+#define  SPI_RCRCR_RXCRC                     ((uint16_t)0xFFFF)            /* Rx CRC Register */
+
+/******************  Bit definition for SPI_TCRCR register  ******************/
+#define  SPI_TCRCR_TXCRC                     ((uint16_t)0xFFFF)            /* Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /* Channel length (number of bits per audio channel) */
+
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /* DATLEN[1:0] bits (Data length to be transferred) */
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /* Bit 0 */
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /* Bit 1 */
+
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /* steady state clock polarity */
+
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /* I2SSTD[1:0] bits (I2S standard selection) */
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /* Bit 0 */
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /* Bit 1 */
+
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /* PCM frame synchronization */
+
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /* I2SCFG[1:0] bits (I2S configuration mode) */
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /* Bit 0 */
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /* Bit 1 */
+
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /* I2S Enable */
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /* I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /* I2S Linear prescaler */
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /* Odd factor for the prescaler */
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /* Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                    TIM                                     */
+/******************************************************************************/
+
+/*******************  Bit definition for TIM_CTLR1 register  ********************/
+#define  TIM_CEN                         ((uint16_t)0x0001)            /* Counter enable */
+#define  TIM_UDIS                        ((uint16_t)0x0002)            /* Update disable */
+#define  TIM_URS                         ((uint16_t)0x0004)            /* Update request source */
+#define  TIM_OPM                         ((uint16_t)0x0008)            /* One pulse mode */
+#define  TIM_DIR                         ((uint16_t)0x0010)            /* Direction */
+
+#define  TIM_CMS                         ((uint16_t)0x0060)            /* CMS[1:0] bits (Center-aligned mode selection) */
+#define  TIM_CMS_0                       ((uint16_t)0x0020)            /* Bit 0 */
+#define  TIM_CMS_1                       ((uint16_t)0x0040)            /* Bit 1 */
+
+#define  TIM_ARPE                        ((uint16_t)0x0080)            /* Auto-reload preload enable */
+
+#define  TIM_CTLR1_CKD                   ((uint16_t)0x0300)            /* CKD[1:0] bits (clock division) */
+#define  TIM_CKD_0                       ((uint16_t)0x0100)            /* Bit 0 */
+#define  TIM_CKD_1                       ((uint16_t)0x0200)            /* Bit 1 */
+
+/*******************  Bit definition for TIM_CTLR2 register  ********************/
+#define  TIM_CCPC                        ((uint16_t)0x0001)            /* Capture/Compare Preloaded Control */
+#define  TIM_CCUS                        ((uint16_t)0x0004)            /* Capture/Compare Control Update Selection */
+#define  TIM_CCDS                        ((uint16_t)0x0008)            /* Capture/Compare DMA Selection */
+
+#define  TIM_MMS                         ((uint16_t)0x0070)            /* MMS[2:0] bits (Master Mode Selection) */
+#define  TIM_MMS_0                       ((uint16_t)0x0010)            /* Bit 0 */
+#define  TIM_MMS_1                       ((uint16_t)0x0020)            /* Bit 1 */
+#define  TIM_MMS_2                       ((uint16_t)0x0040)            /* Bit 2 */
+
+#define  TIM_TI1S                        ((uint16_t)0x0080)            /* TI1 Selection */
+#define  TIM_OIS1                        ((uint16_t)0x0100)            /* Output Idle state 1 (OC1 output) */
+#define  TIM_OIS1N                       ((uint16_t)0x0200)            /* Output Idle state 1 (OC1N output) */
+#define  TIM_OIS2                        ((uint16_t)0x0400)            /* Output Idle state 2 (OC2 output) */
+#define  TIM_OIS2N                       ((uint16_t)0x0800)            /* Output Idle state 2 (OC2N output) */
+#define  TIM_OIS3                        ((uint16_t)0x1000)            /* Output Idle state 3 (OC3 output) */
+#define  TIM_OIS3N                       ((uint16_t)0x2000)            /* Output Idle state 3 (OC3N output) */
+#define  TIM_OIS4                        ((uint16_t)0x4000)            /* Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCFGR register  *******************/
+#define  TIM_SMS                         ((uint16_t)0x0007)            /* SMS[2:0] bits (Slave mode selection) */
+#define  TIM_SMS_0                       ((uint16_t)0x0001)            /* Bit 0 */
+#define  TIM_SMS_1                       ((uint16_t)0x0002)            /* Bit 1 */
+#define  TIM_SMS_2                       ((uint16_t)0x0004)            /* Bit 2 */
+
+#define  TIM_TS                          ((uint16_t)0x0070)            /* TS[2:0] bits (Trigger selection) */
+#define  TIM_TS_0                        ((uint16_t)0x0010)            /* Bit 0 */
+#define  TIM_TS_1                        ((uint16_t)0x0020)            /* Bit 1 */
+#define  TIM_TS_2                        ((uint16_t)0x0040)            /* Bit 2 */
+
+#define  TIM_MSM                         ((uint16_t)0x0080)            /* Master/slave mode */
+ 
+#define  TIM_ETF                         ((uint16_t)0x0F00)            /* ETF[3:0] bits (External trigger filter) */
+#define  TIM_ETF_0                       ((uint16_t)0x0100)            /* Bit 0 */
+#define  TIM_ETF_1                       ((uint16_t)0x0200)            /* Bit 1 */
+#define  TIM_ETF_2                       ((uint16_t)0x0400)            /* Bit 2 */
+#define  TIM_ETF_3                       ((uint16_t)0x0800)            /* Bit 3 */
+
+#define  TIM_ETPS                        ((uint16_t)0x3000)            /* ETPS[1:0] bits (External trigger prescaler) */
+#define  TIM_ETPS_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  TIM_ETPS_1                      ((uint16_t)0x2000)            /* Bit 1 */
+ 
+#define  TIM_ECE                         ((uint16_t)0x4000)            /* External clock enable */
+#define  TIM_ETP                         ((uint16_t)0x8000)            /* External trigger polarity */
+
+/*******************  Bit definition for TIM_DMAINTENR register  *******************/
+#define  TIM_UIE                         ((uint16_t)0x0001)            /* Update interrupt enable */
+#define  TIM_CC1IE                       ((uint16_t)0x0002)            /* Capture/Compare 1 interrupt enable */
+#define  TIM_CC2IE                       ((uint16_t)0x0004)            /* Capture/Compare 2 interrupt enable */
+#define  TIM_CC3IE                       ((uint16_t)0x0008)            /* Capture/Compare 3 interrupt enable */
+#define  TIM_CC4IE                       ((uint16_t)0x0010)            /* Capture/Compare 4 interrupt enable */
+#define  TIM_COMIE                       ((uint16_t)0x0020)            /* COM interrupt enable */
+#define  TIM_TIE                         ((uint16_t)0x0040)            /* Trigger interrupt enable */
+#define  TIM_BIE                         ((uint16_t)0x0080)            /* Break interrupt enable */
+#define  TIM_UDE                         ((uint16_t)0x0100)            /* Update DMA request enable */
+#define  TIM_CC1DE                       ((uint16_t)0x0200)            /* Capture/Compare 1 DMA request enable */
+#define  TIM_CC2DE                       ((uint16_t)0x0400)            /* Capture/Compare 2 DMA request enable */
+#define  TIM_CC3DE                       ((uint16_t)0x0800)            /* Capture/Compare 3 DMA request enable */
+#define  TIM_CC4DE                       ((uint16_t)0x1000)            /* Capture/Compare 4 DMA request enable */
+#define  TIM_COMDE                       ((uint16_t)0x2000)            /* COM DMA request enable */
+#define  TIM_TDE                         ((uint16_t)0x4000)            /* Trigger DMA request enable */
+
+/********************  Bit definition for TIM_INTFR register  ********************/
+#define  TIM_UIF                         ((uint16_t)0x0001)            /* Update interrupt Flag */
+#define  TIM_CC1IF                       ((uint16_t)0x0002)            /* Capture/Compare 1 interrupt Flag */
+#define  TIM_CC2IF                       ((uint16_t)0x0004)            /* Capture/Compare 2 interrupt Flag */
+#define  TIM_CC3IF                       ((uint16_t)0x0008)            /* Capture/Compare 3 interrupt Flag */
+#define  TIM_CC4IF                       ((uint16_t)0x0010)            /* Capture/Compare 4 interrupt Flag */
+#define  TIM_COMIF                       ((uint16_t)0x0020)            /* COM interrupt Flag */
+#define  TIM_TIF                         ((uint16_t)0x0040)            /* Trigger interrupt Flag */
+#define  TIM_BIF                         ((uint16_t)0x0080)            /* Break interrupt Flag */
+#define  TIM_CC1OF                       ((uint16_t)0x0200)            /* Capture/Compare 1 Overcapture Flag */
+#define  TIM_CC2OF                       ((uint16_t)0x0400)            /* Capture/Compare 2 Overcapture Flag */
+#define  TIM_CC3OF                       ((uint16_t)0x0800)            /* Capture/Compare 3 Overcapture Flag */
+#define  TIM_CC4OF                       ((uint16_t)0x1000)            /* Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_SWEVGR register  ********************/
+#define  TIM_UG                          ((uint8_t)0x01)               /* Update Generation */
+#define  TIM_CC1G                        ((uint8_t)0x02)               /* Capture/Compare 1 Generation */
+#define  TIM_CC2G                        ((uint8_t)0x04)               /* Capture/Compare 2 Generation */
+#define  TIM_CC3G                        ((uint8_t)0x08)               /* Capture/Compare 3 Generation */
+#define  TIM_CC4G                        ((uint8_t)0x10)               /* Capture/Compare 4 Generation */
+#define  TIM_COMG                        ((uint8_t)0x20)               /* Capture/Compare Control Update Generation */
+#define  TIM_TG                          ((uint8_t)0x40)               /* Trigger Generation */
+#define  TIM_BG                          ((uint8_t)0x80)               /* Break Generation */
+
+/******************  Bit definition for TIM_CHCTLR1 register  *******************/
+#define  TIM_CC1S                        ((uint16_t)0x0003)            /* CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define  TIM_CC1S_0                      ((uint16_t)0x0001)            /* Bit 0 */
+#define  TIM_CC1S_1                      ((uint16_t)0x0002)            /* Bit 1 */
+
+#define  TIM_OC1FE                       ((uint16_t)0x0004)            /* Output Compare 1 Fast enable */
+#define  TIM_OC1PE                       ((uint16_t)0x0008)            /* Output Compare 1 Preload enable */
+
+#define  TIM_OC1M                        ((uint16_t)0x0070)            /* OC1M[2:0] bits (Output Compare 1 Mode) */
+#define  TIM_OC1M_0                      ((uint16_t)0x0010)            /* Bit 0 */
+#define  TIM_OC1M_1                      ((uint16_t)0x0020)            /* Bit 1 */
+#define  TIM_OC1M_2                      ((uint16_t)0x0040)            /* Bit 2 */
+
+#define  TIM_OC1CE                       ((uint16_t)0x0080)            /* Output Compare 1Clear Enable */
+
+#define  TIM_CC2S                        ((uint16_t)0x0300)            /* CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define  TIM_CC2S_0                      ((uint16_t)0x0100)            /* Bit 0 */
+#define  TIM_CC2S_1                      ((uint16_t)0x0200)            /* Bit 1 */
+
+#define  TIM_OC2FE                       ((uint16_t)0x0400)            /* Output Compare 2 Fast enable */
+#define  TIM_OC2PE                       ((uint16_t)0x0800)            /* Output Compare 2 Preload enable */
+
+#define  TIM_OC2M                        ((uint16_t)0x7000)            /* OC2M[2:0] bits (Output Compare 2 Mode) */
+#define  TIM_OC2M_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  TIM_OC2M_1                      ((uint16_t)0x2000)            /* Bit 1 */
+#define  TIM_OC2M_2                      ((uint16_t)0x4000)            /* Bit 2 */
+
+#define  TIM_OC2CE                       ((uint16_t)0x8000)            /* Output Compare 2 Clear Enable */
+
+
+#define  TIM_IC1PSC                      ((uint16_t)0x000C)            /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define  TIM_IC1PSC_0                    ((uint16_t)0x0004)            /* Bit 0 */
+#define  TIM_IC1PSC_1                    ((uint16_t)0x0008)            /* Bit 1 */
+
+#define  TIM_IC1F                        ((uint16_t)0x00F0)            /* IC1F[3:0] bits (Input Capture 1 Filter) */
+#define  TIM_IC1F_0                      ((uint16_t)0x0010)            /* Bit 0 */
+#define  TIM_IC1F_1                      ((uint16_t)0x0020)            /* Bit 1 */
+#define  TIM_IC1F_2                      ((uint16_t)0x0040)            /* Bit 2 */
+#define  TIM_IC1F_3                      ((uint16_t)0x0080)            /* Bit 3 */
+
+#define  TIM_IC2PSC                      ((uint16_t)0x0C00)            /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define  TIM_IC2PSC_0                    ((uint16_t)0x0400)            /* Bit 0 */
+#define  TIM_IC2PSC_1                    ((uint16_t)0x0800)            /* Bit 1 */
+
+#define  TIM_IC2F                        ((uint16_t)0xF000)            /* IC2F[3:0] bits (Input Capture 2 Filter) */
+#define  TIM_IC2F_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  TIM_IC2F_1                      ((uint16_t)0x2000)            /* Bit 1 */
+#define  TIM_IC2F_2                      ((uint16_t)0x4000)            /* Bit 2 */
+#define  TIM_IC2F_3                      ((uint16_t)0x8000)            /* Bit 3 */
+
+/******************  Bit definition for TIM_CHCTLR2 register  *******************/
+#define  TIM_CC3S                        ((uint16_t)0x0003)            /* CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define  TIM_CC3S_0                      ((uint16_t)0x0001)            /* Bit 0 */
+#define  TIM_CC3S_1                      ((uint16_t)0x0002)            /* Bit 1 */
+
+#define  TIM_OC3FE                       ((uint16_t)0x0004)            /* Output Compare 3 Fast enable */
+#define  TIM_OC3PE                       ((uint16_t)0x0008)            /* Output Compare 3 Preload enable */
+
+#define  TIM_OC3M                        ((uint16_t)0x0070)            /* OC3M[2:0] bits (Output Compare 3 Mode) */
+#define  TIM_OC3M_0                      ((uint16_t)0x0010)            /* Bit 0 */
+#define  TIM_OC3M_1                      ((uint16_t)0x0020)            /* Bit 1 */
+#define  TIM_OC3M_2                      ((uint16_t)0x0040)            /* Bit 2 */
+
+#define  TIM_OC3CE                       ((uint16_t)0x0080)            /* Output Compare 3 Clear Enable */
+
+#define  TIM_CC4S                        ((uint16_t)0x0300)            /* CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define  TIM_CC4S_0                      ((uint16_t)0x0100)            /* Bit 0 */
+#define  TIM_CC4S_1                      ((uint16_t)0x0200)            /* Bit 1 */
+
+#define  TIM_OC4FE                       ((uint16_t)0x0400)            /* Output Compare 4 Fast enable */
+#define  TIM_OC4PE                       ((uint16_t)0x0800)            /* Output Compare 4 Preload enable */
+
+#define  TIM_OC4M                        ((uint16_t)0x7000)            /* OC4M[2:0] bits (Output Compare 4 Mode) */
+#define  TIM_OC4M_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  TIM_OC4M_1                      ((uint16_t)0x2000)            /* Bit 1 */
+#define  TIM_OC4M_2                      ((uint16_t)0x4000)            /* Bit 2 */
+
+#define  TIM_OC4CE                       ((uint16_t)0x8000)            /* Output Compare 4 Clear Enable */
+
+
+#define  TIM_IC3PSC                      ((uint16_t)0x000C)            /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define  TIM_IC3PSC_0                    ((uint16_t)0x0004)            /* Bit 0 */
+#define  TIM_IC3PSC_1                    ((uint16_t)0x0008)            /* Bit 1 */
+
+#define  TIM_IC3F                        ((uint16_t)0x00F0)            /* IC3F[3:0] bits (Input Capture 3 Filter) */
+#define  TIM_IC3F_0                      ((uint16_t)0x0010)            /* Bit 0 */
+#define  TIM_IC3F_1                      ((uint16_t)0x0020)            /* Bit 1 */
+#define  TIM_IC3F_2                      ((uint16_t)0x0040)            /* Bit 2 */
+#define  TIM_IC3F_3                      ((uint16_t)0x0080)            /* Bit 3 */
+
+#define  TIM_IC4PSC                      ((uint16_t)0x0C00)            /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define  TIM_IC4PSC_0                    ((uint16_t)0x0400)            /* Bit 0 */
+#define  TIM_IC4PSC_1                    ((uint16_t)0x0800)            /* Bit 1 */
+
+#define  TIM_IC4F                        ((uint16_t)0xF000)            /* IC4F[3:0] bits (Input Capture 4 Filter) */
+#define  TIM_IC4F_0                      ((uint16_t)0x1000)            /* Bit 0 */
+#define  TIM_IC4F_1                      ((uint16_t)0x2000)            /* Bit 1 */
+#define  TIM_IC4F_2                      ((uint16_t)0x4000)            /* Bit 2 */
+#define  TIM_IC4F_3                      ((uint16_t)0x8000)            /* Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define  TIM_CC1E                        ((uint16_t)0x0001)            /* Capture/Compare 1 output enable */
+#define  TIM_CC1P                        ((uint16_t)0x0002)            /* Capture/Compare 1 output Polarity */
+#define  TIM_CC1NE                       ((uint16_t)0x0004)            /* Capture/Compare 1 Complementary output enable */
+#define  TIM_CC1NP                       ((uint16_t)0x0008)            /* Capture/Compare 1 Complementary output Polarity */
+#define  TIM_CC2E                        ((uint16_t)0x0010)            /* Capture/Compare 2 output enable */
+#define  TIM_CC2P                        ((uint16_t)0x0020)            /* Capture/Compare 2 output Polarity */
+#define  TIM_CC2NE                       ((uint16_t)0x0040)            /* Capture/Compare 2 Complementary output enable */
+#define  TIM_CC2NP                       ((uint16_t)0x0080)            /* Capture/Compare 2 Complementary output Polarity */
+#define  TIM_CC3E                        ((uint16_t)0x0100)            /* Capture/Compare 3 output enable */
+#define  TIM_CC3P                        ((uint16_t)0x0200)            /* Capture/Compare 3 output Polarity */
+#define  TIM_CC3NE                       ((uint16_t)0x0400)            /* Capture/Compare 3 Complementary output enable */
+#define  TIM_CC3NP                       ((uint16_t)0x0800)            /* Capture/Compare 3 Complementary output Polarity */
+#define  TIM_CC4E                        ((uint16_t)0x1000)            /* Capture/Compare 4 output enable */
+#define  TIM_CC4P                        ((uint16_t)0x2000)            /* Capture/Compare 4 output Polarity */
+#define  TIM_CC4NP                       ((uint16_t)0x8000)            /* Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define  TIM_CNT                         ((uint16_t)0xFFFF)            /* Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define  TIM_PSC                         ((uint16_t)0xFFFF)            /* Prescaler Value */
+
+/*******************  Bit definition for TIM_ATRLR register  ********************/
+#define  TIM_ARR                         ((uint16_t)0xFFFF)            /* actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RPTCR register  ********************/
+#define  TIM_REP                         ((uint8_t)0xFF)               /* Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CH1CVR register  *******************/
+#define  TIM_CCR1                        ((uint16_t)0xFFFF)            /* Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CH2CVR register  *******************/
+#define  TIM_CCR2                        ((uint16_t)0xFFFF)            /* Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CH3CVR register  *******************/
+#define  TIM_CCR3                        ((uint16_t)0xFFFF)            /* Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CH4CVR register  *******************/
+#define  TIM_CCR4                        ((uint16_t)0xFFFF)            /* Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define  TIM_DTG                         ((uint16_t)0x00FF)            /* DTG[0:7] bits (Dead-Time Generator set-up) */
+#define  TIM_DTG_0                       ((uint16_t)0x0001)            /* Bit 0 */
+#define  TIM_DTG_1                       ((uint16_t)0x0002)            /* Bit 1 */
+#define  TIM_DTG_2                       ((uint16_t)0x0004)            /* Bit 2 */
+#define  TIM_DTG_3                       ((uint16_t)0x0008)            /* Bit 3 */
+#define  TIM_DTG_4                       ((uint16_t)0x0010)            /* Bit 4 */
+#define  TIM_DTG_5                       ((uint16_t)0x0020)            /* Bit 5 */
+#define  TIM_DTG_6                       ((uint16_t)0x0040)            /* Bit 6 */
+#define  TIM_DTG_7                       ((uint16_t)0x0080)            /* Bit 7 */
+
+#define  TIM_LOCK                        ((uint16_t)0x0300)            /* LOCK[1:0] bits (Lock Configuration) */
+#define  TIM_LOCK_0                      ((uint16_t)0x0100)            /* Bit 0 */
+#define  TIM_LOCK_1                      ((uint16_t)0x0200)            /* Bit 1 */
+ 
+#define  TIM_OSSI                        ((uint16_t)0x0400)            /* Off-State Selection for Idle mode */
+#define  TIM_OSSR                        ((uint16_t)0x0800)            /* Off-State Selection for Run mode */
+#define  TIM_BKE                         ((uint16_t)0x1000)            /* Break enable */
+#define  TIM_BKP                         ((uint16_t)0x2000)            /* Break Polarity */
+#define  TIM_AOE                         ((uint16_t)0x4000)            /* Automatic Output enable */
+#define  TIM_MOE                         ((uint16_t)0x8000)            /* Main Output enable */
+
+/*******************  Bit definition for TIM_DMACFGR register  ********************/
+#define  TIM_DBA                         ((uint16_t)0x001F)            /* DBA[4:0] bits (DMA Base Address) */
+#define  TIM_DBA_0                       ((uint16_t)0x0001)            /* Bit 0 */
+#define  TIM_DBA_1                       ((uint16_t)0x0002)            /* Bit 1 */
+#define  TIM_DBA_2                       ((uint16_t)0x0004)            /* Bit 2 */
+#define  TIM_DBA_3                       ((uint16_t)0x0008)            /* Bit 3 */
+#define  TIM_DBA_4                       ((uint16_t)0x0010)            /* Bit 4 */
+
+#define  TIM_DBL                         ((uint16_t)0x1F00)            /* DBL[4:0] bits (DMA Burst Length) */
+#define  TIM_DBL_0                       ((uint16_t)0x0100)            /* Bit 0 */
+#define  TIM_DBL_1                       ((uint16_t)0x0200)            /* Bit 1 */
+#define  TIM_DBL_2                       ((uint16_t)0x0400)            /* Bit 2 */
+#define  TIM_DBL_3                       ((uint16_t)0x0800)            /* Bit 3 */
+#define  TIM_DBL_4                       ((uint16_t)0x1000)            /* Bit 4 */
+
+/*******************  Bit definition for TIM_DMAADR register  *******************/
+#define  TIM_DMAR_DMAB                   ((uint16_t)0xFFFF)            /* DMA register for burst accesses */
+
+/******************************************************************************/
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/******************************************************************************/
+
+/*******************  Bit definition for USART_STATR register  *******************/
+#define  USART_STATR_PE                        ((uint16_t)0x0001)            /* Parity Error */
+#define  USART_STATR_FE                        ((uint16_t)0x0002)            /* Framing Error */
+#define  USART_STATR_NE                        ((uint16_t)0x0004)            /* Noise Error Flag */
+#define  USART_STATR_ORE                       ((uint16_t)0x0008)            /* OverRun Error */
+#define  USART_STATR_IDLE                      ((uint16_t)0x0010)            /* IDLE line detected */
+#define  USART_STATR_RXNE                      ((uint16_t)0x0020)            /* Read Data Register Not Empty */
+#define  USART_STATR_TC                        ((uint16_t)0x0040)            /* Transmission Complete */
+#define  USART_STATR_TXE                       ((uint16_t)0x0080)            /* Transmit Data Register Empty */
+#define  USART_STATR_LBD                       ((uint16_t)0x0100)            /* LIN Break Detection Flag */
+#define  USART_STATR_CTS                       ((uint16_t)0x0200)            /* CTS Flag */
+
+/*******************  Bit definition for USART_DATAR register  *******************/
+#define  USART_DATAR_DR                        ((uint16_t)0x01FF)            /* Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define  USART_BRR_DIV_Fraction                ((uint16_t)0x000F)            /* Fraction of USARTDIV */
+#define  USART_BRR_DIV_Mantissa                ((uint16_t)0xFFF0)            /* Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CTLR1 register  *******************/
+#define  USART_CTLR1_SBK                       ((uint16_t)0x0001)            /* Send Break */
+#define  USART_CTLR1_RWU                       ((uint16_t)0x0002)            /* Receiver wakeup */
+#define  USART_CTLR1_RE                        ((uint16_t)0x0004)            /* Receiver Enable */
+#define  USART_CTLR1_TE                        ((uint16_t)0x0008)            /* Transmitter Enable */
+#define  USART_CTLR1_IDLEIE                    ((uint16_t)0x0010)            /* IDLE Interrupt Enable */
+#define  USART_CTLR1_RXNEIE                    ((uint16_t)0x0020)            /* RXNE Interrupt Enable */
+#define  USART_CTLR1_TCIE                      ((uint16_t)0x0040)            /* Transmission Complete Interrupt Enable */
+#define  USART_CTLR1_TXEIE                     ((uint16_t)0x0080)            /* PE Interrupt Enable */
+#define  USART_CTLR1_PEIE                      ((uint16_t)0x0100)            /* PE Interrupt Enable */
+#define  USART_CTLR1_PS                        ((uint16_t)0x0200)            /* Parity Selection */
+#define  USART_CTLR1_PCE                       ((uint16_t)0x0400)            /* Parity Control Enable */
+#define  USART_CTLR1_WAKE                      ((uint16_t)0x0800)            /* Wakeup method */
+#define  USART_CTLR1_M                         ((uint16_t)0x1000)            /* Word length */
+#define  USART_CTLR1_UE                        ((uint16_t)0x2000)            /* USART Enable */
+#define  USART_CTLR1_OVER8                     ((uint16_t)0x8000)            /* USART Oversmapling 8-bits */
+
+/******************  Bit definition for USART_CTLR2 register  *******************/
+#define  USART_CTLR2_ADD                       ((uint16_t)0x000F)            /* Address of the USART node */
+#define  USART_CTLR2_LBDL                      ((uint16_t)0x0020)            /* LIN Break Detection Length */
+#define  USART_CTLR2_LBDIE                     ((uint16_t)0x0040)            /* LIN Break Detection Interrupt Enable */
+#define  USART_CTLR2_LBCL                      ((uint16_t)0x0100)            /* Last Bit Clock pulse */
+#define  USART_CTLR2_CPHA                      ((uint16_t)0x0200)            /* Clock Phase */
+#define  USART_CTLR2_CPOL                      ((uint16_t)0x0400)            /* Clock Polarity */
+#define  USART_CTLR2_CLKEN                     ((uint16_t)0x0800)            /* Clock Enable */
+
+#define  USART_CTLR2_STOP                      ((uint16_t)0x3000)            /* STOP[1:0] bits (STOP bits) */
+#define  USART_CTLR2_STOP_0                    ((uint16_t)0x1000)            /* Bit 0 */
+#define  USART_CTLR2_STOP_1                    ((uint16_t)0x2000)            /* Bit 1 */
+
+#define  USART_CTLR2_LINEN                     ((uint16_t)0x4000)            /* LIN mode enable */
+
+/******************  Bit definition for USART_CTLR3 register  *******************/
+#define  USART_CTLR3_EIE                       ((uint16_t)0x0001)            /* Error Interrupt Enable */
+#define  USART_CTLR3_IREN                      ((uint16_t)0x0002)            /* IrDA mode Enable */
+#define  USART_CTLR3_IRLP                      ((uint16_t)0x0004)            /* IrDA Low-Power */
+#define  USART_CTLR3_HDSEL                     ((uint16_t)0x0008)            /* Half-Duplex Selection */
+#define  USART_CTLR3_NACK                      ((uint16_t)0x0010)            /* Smartcard NACK enable */
+#define  USART_CTLR3_SCEN                      ((uint16_t)0x0020)            /* Smartcard mode enable */
+#define  USART_CTLR3_DMAR                      ((uint16_t)0x0040)            /* DMA Enable Receiver */
+#define  USART_CTLR3_DMAT                      ((uint16_t)0x0080)            /* DMA Enable Transmitter */
+#define  USART_CTLR3_RTSE                      ((uint16_t)0x0100)            /* RTS Enable */
+#define  USART_CTLR3_CTSE                      ((uint16_t)0x0200)            /* CTS Enable */
+#define  USART_CTLR3_CTSIE                     ((uint16_t)0x0400)            /* CTS Interrupt Enable */
+#define  USART_CTLR3_ONEBIT                    ((uint16_t)0x0800)            /* One Bit method */
+
+/******************  Bit definition for USART_GPR register  ******************/
+#define  USART_GPR_PSC                         ((uint16_t)0x00FF)            /* PSC[7:0] bits (Prescaler value) */
+#define  USART_GPR_PSC_0                       ((uint16_t)0x0001)            /* Bit 0 */
+#define  USART_GPR_PSC_1                       ((uint16_t)0x0002)            /* Bit 1 */
+#define  USART_GPR_PSC_2                       ((uint16_t)0x0004)            /* Bit 2 */
+#define  USART_GPR_PSC_3                       ((uint16_t)0x0008)            /* Bit 3 */
+#define  USART_GPR_PSC_4                       ((uint16_t)0x0010)            /* Bit 4 */
+#define  USART_GPR_PSC_5                       ((uint16_t)0x0020)            /* Bit 5 */
+#define  USART_GPR_PSC_6                       ((uint16_t)0x0040)            /* Bit 6 */
+#define  USART_GPR_PSC_7                       ((uint16_t)0x0080)            /* Bit 7 */
+
+#define  USART_GPR_GT                          ((uint16_t)0xFF00)            /* Guard time value */
+
+/******************************************************************************/
+/*                            Window WATCHDOG                                 */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CTLR register  ********************/
+#define  WWDG_CTLR_T                           ((uint8_t)0x7F)               /* T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define  WWDG_CTLR_T0                          ((uint8_t)0x01)               /* Bit 0 */
+#define  WWDG_CTLR_T1                          ((uint8_t)0x02)               /* Bit 1 */
+#define  WWDG_CTLR_T2                          ((uint8_t)0x04)               /* Bit 2 */
+#define  WWDG_CTLR_T3                          ((uint8_t)0x08)               /* Bit 3 */
+#define  WWDG_CTLR_T4                          ((uint8_t)0x10)               /* Bit 4 */
+#define  WWDG_CTLR_T5                          ((uint8_t)0x20)               /* Bit 5 */
+#define  WWDG_CTLR_T6                          ((uint8_t)0x40)               /* Bit 6 */
+
+#define  WWDG_CTLR_WDGA                        ((uint8_t)0x80)               /* Activation bit */
+
+/*******************  Bit definition for WWDG_CFGR register  *******************/
+#define  WWDG_CFGR_W                           ((uint16_t)0x007F)            /* W[6:0] bits (7-bit window value) */
+#define  WWDG_CFGR_W0                          ((uint16_t)0x0001)            /* Bit 0 */
+#define  WWDG_CFGR_W1                          ((uint16_t)0x0002)            /* Bit 1 */
+#define  WWDG_CFGR_W2                          ((uint16_t)0x0004)            /* Bit 2 */
+#define  WWDG_CFGR_W3                          ((uint16_t)0x0008)            /* Bit 3 */
+#define  WWDG_CFGR_W4                          ((uint16_t)0x0010)            /* Bit 4 */
+#define  WWDG_CFGR_W5                          ((uint16_t)0x0020)            /* Bit 5 */
+#define  WWDG_CFGR_W6                          ((uint16_t)0x0040)            /* Bit 6 */
+
+#define  WWDG_CFGR_WDGTB                       ((uint16_t)0x0180)            /* WDGTB[1:0] bits (Timer Base) */
+#define  WWDG_CFGR_WDGTB0                      ((uint16_t)0x0080)            /* Bit 0 */
+#define  WWDG_CFGR_WDGTB1                      ((uint16_t)0x0100)            /* Bit 1 */
+
+#define  WWDG_CFGR_EWI                         ((uint16_t)0x0200)            /* Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_STATR register  ********************/
+#define  WWDG_STATR_EWIF                       ((uint8_t)0x01)               /* Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                          ENHANCED FUNNCTION                                */
+/******************************************************************************/
+
+/****************************  Enhanced register  *****************************/
+#define  EXTEN_USBD_LS                         ((uint32_t)0x00000001)         /* Bit 0 */
+#define  EXTEN_USBD_PU_EN                      ((uint32_t)0x00000002)         /* Bit 1 */
+#define  EXTEN_ETH_10M_EN                      ((uint32_t)0x00000004)         /* Bit 2 */
+#define  EXTEN_ETH_RGMII_SEL                   ((uint32_t)0x00000008)         /* Bit 3 */
+#define  EXTEN_PLL_HSI_PRE                     ((uint32_t)0x00000010)         /* Bit 4 */
+#define  EXTEN_LOCKUP_EN                       ((uint32_t)0x00000040)         /* Bit 5 */
+#define  EXTEN_LOCKUP_RSTF                     ((uint32_t)0x00000080)         /* Bit 7 */
+
+#define  EXTEN_ULLDO_TRIM                      ((uint32_t)0x00000300)         /* ULLDO_TRIM[1:0] bits */
+#define  EXTEN_ULLDO_TRIM0                     ((uint32_t)0x00000100)         /* Bit 0 */
+#define  EXTEN_ULLDO_TRIM1                     ((uint32_t)0x00000200)         /* Bit 1 */
+
+#define  EXTEN_LDO_TRIM                        ((uint32_t)0x00000C00)         /* LDO_TRIM[1:0] bits */
+#define  EXTEN_LDO_TRIM0                       ((uint32_t)0x00000400)         /* Bit 0 */
+#define  EXTEN_LDO_TRIM1                       ((uint32_t)0x00000800)         /* Bit 1 */
+
+
+/******************************************************************************/
+/*                                  DVP                                       */
+/******************************************************************************/
+
+/*******************  Bit definition for DVP_CR0 register  ********************/
+#define RB_DVP_ENABLE			0x01					// RW, DVP enable
+#define RB_DVP_V_POLAR			0x02					// RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert
+#define	RB_DVP_H_POLAR			0x04					// RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert
+#define	RB_DVP_P_POLAR			0x08					// RW, DVP PCLK polarity control: 1 = invert, 0 = not invert
+#define RB_DVP_MSK_DAT_MOD		0x30					
+#define 	RB_DVP_D8_MOD			0x00				// RW, DVP 8bits data mode
+#define		RB_DVP_D10_MOD			0x10				// RW, DVP 10bits data mode
+#define		RB_DVP_D12_MOD			0x20				// RW, DVP 12bits data mode
+#define	RB_DVP_JPEG				0x40					// RW, DVP JPEG mode
+
+/*******************  Bit definition for DVP_CR1 register  ********************/
+#define RB_DVP_DMA_EN			0x01					// RW, DVP dma enable
+#define RB_DVP_ALL_CLR			0x02					// RW, DVP all clear, high action
+#define	RB_DVP_RCV_CLR			0x04					// RW, DVP receive logic clear, high action
+#define RB_DVP_BUF_TOG			0x08					// RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0
+#define RB_DVP_CM				0x10					// RW, DVP capture mode
+#define	RB_DVP_CROP				0x20					// RW, DVP Crop feature enable
+#define RB_DVP_FCRC				0xC0					// RW, DVP frame capture rate control: 
+#define		DVP_RATE_100P		0x00					//00 = every frame captured (100%) 
+#define		DVP_RATE_50P		0x40					//01 = every alternate frame captured (50%)
+#define		DVP_RATE_25P		0x80					//10 = one frame in four frame captured (25%)
+
+/*******************  Bit definition for DVP_IER register  ********************/
+#define	RB_DVP_IE_STR_FRM		0x01					// RW, DVP frame start interrupt enable
+#define	RB_DVP_IE_ROW_DONE		0x02					// RW, DVP row received done interrupt enable
+#define RB_DVP_IE_FRM_DONE		0x04					// RW, DVP frame received done interrupt enable
+#define	RB_DVP_IE_FIFO_OV		0x08					// RW, DVP receive fifo overflow interrupt enable	
+#define RB_DVP_IE_STP_FRM		0x10					// RW, DVP frame stop interrupt enable				
+
+/*******************  Bit definition for DVP_IFR register  ********************/
+#define RB_DVP_IF_STR_FRM	    0x01				    // RW1, interrupt flag for DVP frame start
+#define RB_DVP_IF_ROW_DONE		0x02				    // RW1, interrupt flag for DVP row receive done
+#define RB_DVP_IF_FRM_DONE		0x04				    // RW1, interrupt flag for DVP frame receive done
+#define RB_DVP_IF_FIFO_OV		0x08				    // RW1, interrupt flag for DVP receive fifo overflow
+#define RB_DVP_IF_STP_FRM		0x10				    // RW1, interrupt flag for DVP frame stop
+
+/*******************  Bit definition for DVP_STATUS register  ********************/
+#define RB_DVP_FIFO_RDY			0x01					// RO, DVP receive fifo ready
+#define RB_DVP_FIFO_FULL		0x02					// RO, DVP receive fifo full
+#define RB_DVP_FIFO_OV			0x04					// RO, DVP receive fifo overflow
+#define RB_DVP_MSK_FIFO_CNT		0x70					// RO, DVP receive fifo count
+
+
+
+#include "ch32v30x_conf.h"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+

demo/ch32/ch32v307/SRC/Peripheral/inc/ch32v30x_gpio.h

@@ -0,0 +1,195 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_gpio.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      GPIO firmware library.
+*******************************************************************************/ 
+#ifndef __CH32V30x_GPIO_H
+#define __CH32V30x_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+                                 
+/* Output Maximum frequency selection */
+typedef enum
+{ 
+  GPIO_Speed_10MHz = 1,
+  GPIO_Speed_2MHz, 
+  GPIO_Speed_50MHz
+}GPIOSpeed_TypeDef;
+
+/* Configuration Mode enumeration */
+typedef enum
+{ GPIO_Mode_AIN = 0x0,
+  GPIO_Mode_IN_FLOATING = 0x04,
+  GPIO_Mode_IPD = 0x28,
+  GPIO_Mode_IPU = 0x48,
+  GPIO_Mode_Out_OD = 0x14,
+  GPIO_Mode_Out_PP = 0x10,
+  GPIO_Mode_AF_OD = 0x1C,
+  GPIO_Mode_AF_PP = 0x18
+}GPIOMode_TypeDef;
+
+/* GPIO Init structure definition */
+typedef struct
+{
+  uint16_t GPIO_Pin;             /* Specifies the GPIO pins to be configured.
+                                    This parameter can be any value of @ref GPIO_pins_define */
+
+  GPIOSpeed_TypeDef GPIO_Speed;  /* Specifies the speed for the selected pins.
+                                    This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+  GPIOMode_TypeDef GPIO_Mode;    /* Specifies the operating mode for the selected pins.
+                                    This parameter can be a value of @ref GPIOMode_TypeDef */
+}GPIO_InitTypeDef;
+
+/* Bit_SET and Bit_RESET enumeration */
+typedef enum
+{
+	Bit_RESET = 0,
+  Bit_SET
+}BitAction;
+
+/* GPIO_pins_define */
+#define GPIO_Pin_0                  ((uint16_t)0x0001)  /* Pin 0 selected */
+#define GPIO_Pin_1                  ((uint16_t)0x0002)  /* Pin 1 selected */
+#define GPIO_Pin_2                  ((uint16_t)0x0004)  /* Pin 2 selected */
+#define GPIO_Pin_3                  ((uint16_t)0x0008)  /* Pin 3 selected */
+#define GPIO_Pin_4                  ((uint16_t)0x0010)  /* Pin 4 selected */
+#define GPIO_Pin_5                  ((uint16_t)0x0020)  /* Pin 5 selected */
+#define GPIO_Pin_6                  ((uint16_t)0x0040)  /* Pin 6 selected */
+#define GPIO_Pin_7                  ((uint16_t)0x0080)  /* Pin 7 selected */
+#define GPIO_Pin_8                  ((uint16_t)0x0100)  /* Pin 8 selected */
+#define GPIO_Pin_9                  ((uint16_t)0x0200)  /* Pin 9 selected */
+#define GPIO_Pin_10                 ((uint16_t)0x0400)  /* Pin 10 selected */
+#define GPIO_Pin_11                 ((uint16_t)0x0800)  /* Pin 11 selected */
+#define GPIO_Pin_12                 ((uint16_t)0x1000)  /* Pin 12 selected */
+#define GPIO_Pin_13                 ((uint16_t)0x2000)  /* Pin 13 selected */
+#define GPIO_Pin_14                 ((uint16_t)0x4000)  /* Pin 14 selected */
+#define GPIO_Pin_15                 ((uint16_t)0x8000)  /* Pin 15 selected */
+#define GPIO_Pin_All                ((uint16_t)0xFFFF)  /* All pins selected */
+
+/* GPIO_Remap_define */
+/* PCFR1 */
+#define GPIO_Remap_SPI1             ((uint32_t)0x00000001)  /* SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1             ((uint32_t)0x00000002)  /* I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1           ((uint32_t)0x00000004)  /* USART1 Alternate Function mapping low bit */
+#define GPIO_Remap_USART2           ((uint32_t)0x00000008)  /* USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3    ((uint32_t)0x00140010)  /* USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3       ((uint32_t)0x00140030)  /* USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1      ((uint32_t)0x00160040)  /* TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1         ((uint32_t)0x001600C0)  /* TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2     ((uint32_t)0x00180100)  /* TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2     ((uint32_t)0x00180200)  /* TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2         ((uint32_t)0x00180300)  /* TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3      ((uint32_t)0x001A0800)  /* TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3         ((uint32_t)0x001A0C00)  /* TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4             ((uint32_t)0x00001000)  /* TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN1            ((uint32_t)0x001D4000)  /* CAN1 Alternate Function mapping */
+#define GPIO_Remap2_CAN1            ((uint32_t)0x001D6000)  /* CAN1 Alternate Function mapping */
+#define GPIO_Remap_PD01             ((uint32_t)0x00008000)  /* PD01 Alternate Function mapping */
+#define GPIO_Remap_TIM5CH4_LSI      ((uint32_t)0x00200001)  /* LSI connected to TIM5 Channel4 input capture for calibration */
+#define GPIO_Remap_ADC1_ETRGINJ     ((uint32_t)0x00200002)  /* ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG     ((uint32_t)0x00200004)  /* ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGINJ     ((uint32_t)0x00200008)  /* ADC2 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC2_ETRGREG     ((uint32_t)0x00200010)  /* ADC2 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_ETH              ((uint32_t)0x00200020)  /* Ethernet remapping (only for Connectivity line devices) */
+#define GPIO_Remap_CAN2             ((uint32_t)0x00200040)  /* CAN2 remapping (only for Connectivity line devices) */
+#define GPIO_Remap_MII_RMII_SEL     ((uint32_t)0x00200080)  /* MII or RMII selection */
+#define GPIO_Remap_SWJ_NoJTRST      ((uint32_t)0x00300100)  /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable  ((uint32_t)0x00300200)  /* JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable      ((uint32_t)0x00300400)  /* Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define GPIO_Remap_SPI3             ((uint32_t)0x00201000)  /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
+#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000)  /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+                                                               to TIM2 Internal Trigger 1 for calibration
+                                                               (only for Connectivity line devices) */
+#define GPIO_Remap_PTP_PPS          ((uint32_t)0x00204000)  /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
+
+/* PCFR2 */
+#define GPIO_Remap_TIM8             ((uint32_t)0x80000004)  /* TIM8 Alternate Function mapping */
+#define GPIO_PartialRemap_TIM9      ((uint32_t)0x80130008)  /* TIM9 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM9         ((uint32_t)0x80130010)  /* TIM9 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM10     ((uint32_t)0x80150020)  /* TIM10 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM10        ((uint32_t)0x80150040)  /* TIM10 Full Alternate Function mapping */
+#define GPIO_Remap_FSMC_NADV        ((uint32_t)0x80000400)  /* FSMC_NADV Alternate Function mapping */
+#define GPIO_PartialRemap_USART4    ((uint32_t)0x80300001)  /* USART4 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART4       ((uint32_t)0x80300002)  /* USART4 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART5    ((uint32_t)0x80320004)  /* USART5 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART5       ((uint32_t)0x80320008)  /* USART5 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART6    ((uint32_t)0x80340010)  /* USART6 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART6       ((uint32_t)0x80340020)  /* USART6 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART7    ((uint32_t)0x80360040)  /* USART7 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART7       ((uint32_t)0x80360080)  /* USART7 Full Alternate Function mapping */
+#define GPIO_PartialRemap_USART8    ((uint32_t)0x80380100)  /* USART8 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART8       ((uint32_t)0x80380200)  /* USART8 Full Alternate Function mapping */
+#define GPIO_Remap_USART1_HighBit   ((uint32_t)0x80200400)  /* USART1 Alternate Function mapping high bit */
+
+
+/* GPIO_Port_Sources */
+#define GPIO_PortSourceGPIOA        ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB        ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC        ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD        ((uint8_t)0x03)
+#define GPIO_PortSourceGPIOE        ((uint8_t)0x04)
+#define GPIO_PortSourceGPIOF        ((uint8_t)0x05)
+#define GPIO_PortSourceGPIOG        ((uint8_t)0x06)
+
+/* GPIO_Pin_sources */
+#define GPIO_PinSource0             ((uint8_t)0x00)
+#define GPIO_PinSource1             ((uint8_t)0x01)
+#define GPIO_PinSource2             ((uint8_t)0x02)
+#define GPIO_PinSource3             ((uint8_t)0x03)
+#define GPIO_PinSource4             ((uint8_t)0x04)
+#define GPIO_PinSource5             ((uint8_t)0x05)
+#define GPIO_PinSource6             ((uint8_t)0x06)
+#define GPIO_PinSource7             ((uint8_t)0x07)
+#define GPIO_PinSource8             ((uint8_t)0x08)
+#define GPIO_PinSource9             ((uint8_t)0x09)
+#define GPIO_PinSource10            ((uint8_t)0x0A)
+#define GPIO_PinSource11            ((uint8_t)0x0B)
+#define GPIO_PinSource12            ((uint8_t)0x0C)
+#define GPIO_PinSource13            ((uint8_t)0x0D)
+#define GPIO_PinSource14            ((uint8_t)0x0E)
+#define GPIO_PinSource15            ((uint8_t)0x0F)
+
+/* Ethernet_Media_Interface */
+#define GPIO_ETH_MediaInterface_MII    ((u32)0x00000000)
+#define GPIO_ETH_MediaInterface_RMII   ((u32)0x00000001)
+
+
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+void GPIO_AFIODeInit(void);
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_EventOutputCmd(FunctionalState NewState);
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+

demo/ch32/ch32v307/SRC/Peripheral/inc/ch32v30x_misc.h

@@ -0,0 +1,44 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_misc.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      miscellaneous firmware library functions.
+*******************************************************************************/   
+#ifndef __CH32V30X_MISC_H
+#define __CH32V30X_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* NVIC Init Structure definition */	 
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;
+  uint8_t NVIC_IRQChannelPreemptionPriority;
+  uint8_t NVIC_IRQChannelSubPriority;
+  FunctionalState NVIC_IRQChannelCmd;
+} NVIC_InitTypeDef;
+ 
+
+/* Preemption_Priority_Group */
+#define NVIC_PriorityGroup_0           ((uint32_t)0x00)
+#define NVIC_PriorityGroup_1           ((uint32_t)0x01)
+#define NVIC_PriorityGroup_2           ((uint32_t)0x02)
+#define NVIC_PriorityGroup_3           ((uint32_t)0x03)
+#define NVIC_PriorityGroup_4           ((uint32_t)0x04)
+
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+

demo/ch32/ch32v307/SRC/Peripheral/inc/ch32v30x_rcc.h

@@ -0,0 +1,393 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_rcc.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the RCC firmware functions.
+*******************************************************************************/ 
+#ifndef __CH32V30x_RCC_H
+#define __CH32V30x_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+
+/* RCC_Exported_Types */
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;  /* returns SYSCLK clock frequency expressed in Hz */
+  uint32_t HCLK_Frequency;    /* returns HCLK clock frequency expressed in Hz */
+  uint32_t PCLK1_Frequency;   /* returns PCLK1 clock frequency expressed in Hz */
+  uint32_t PCLK2_Frequency;   /* returns PCLK2 clock frequency expressed in Hz */
+  uint32_t ADCCLK_Frequency;  /* returns ADCCLK clock frequency expressed in Hz */
+}RCC_ClocksTypeDef;
+
+/* HSE_configuration */
+#define RCC_HSE_OFF                      ((uint32_t)0x00000000)
+#define RCC_HSE_ON                       ((uint32_t)0x00010000)
+#define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
+
+/* PLL_entry_clock_source */
+#define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)
+#define RCC_PLLSource_PREDIV1            ((uint32_t)0x00010000)
+
+/* PLL_multiplication_factor for other CH32V30x  */
+#define RCC_PLLMul_2                     ((uint32_t)0x00000000)
+#define RCC_PLLMul_3                     ((uint32_t)0x00040000)
+#define RCC_PLLMul_4                     ((uint32_t)0x00080000)
+#define RCC_PLLMul_5                     ((uint32_t)0x000C0000)
+#define RCC_PLLMul_6                     ((uint32_t)0x00100000)
+#define RCC_PLLMul_7                     ((uint32_t)0x00140000)
+#define RCC_PLLMul_8                     ((uint32_t)0x00180000)
+#define RCC_PLLMul_9                     ((uint32_t)0x001C0000)
+#define RCC_PLLMul_10                    ((uint32_t)0x00200000)
+#define RCC_PLLMul_11                    ((uint32_t)0x00240000)
+#define RCC_PLLMul_12                    ((uint32_t)0x00280000)
+#define RCC_PLLMul_13                    ((uint32_t)0x002C0000)
+#define RCC_PLLMul_14                    ((uint32_t)0x00300000)
+#define RCC_PLLMul_15                    ((uint32_t)0x00340000)
+#define RCC_PLLMul_16                    ((uint32_t)0x00380000)
+#define RCC_PLLMul_18                    ((uint32_t)0x003C0000)
+
+/* PLL_multiplication_factor for CH32V307 */
+#define RCC_PLLMul_18_EXTEN              ((uint32_t)0x00000000)
+#define RCC_PLLMul_3_EXTEN               ((uint32_t)0x00040000)
+#define RCC_PLLMul_4_EXTEN               ((uint32_t)0x00080000)
+#define RCC_PLLMul_5_EXTEN               ((uint32_t)0x000C0000)
+#define RCC_PLLMul_6_EXTEN               ((uint32_t)0x00100000)
+#define RCC_PLLMul_7_EXTEN               ((uint32_t)0x00140000)
+#define RCC_PLLMul_8_EXTEN               ((uint32_t)0x00180000)
+#define RCC_PLLMul_9_EXTEN               ((uint32_t)0x001C0000)
+#define RCC_PLLMul_10_EXTEN              ((uint32_t)0x00200000)
+#define RCC_PLLMul_11_EXTEN              ((uint32_t)0x00240000)
+#define RCC_PLLMul_12_EXTEN              ((uint32_t)0x00280000)
+#define RCC_PLLMul_13_EXTEN              ((uint32_t)0x002C0000)
+#define RCC_PLLMul_14_EXTEN              ((uint32_t)0x00300000)
+#define RCC_PLLMul_6_5_EXTEN             ((uint32_t)0x00340000)
+#define RCC_PLLMul_15_EXTEN              ((uint32_t)0x00380000)
+#define RCC_PLLMul_16_EXTEN              ((uint32_t)0x003C0000)
+
+/* PREDIV1_division_factor */
+#define RCC_PREDIV1_Div1                 ((uint32_t)0x00000000)
+#define RCC_PREDIV1_Div2                 ((uint32_t)0x00000001)
+#define RCC_PREDIV1_Div3                 ((uint32_t)0x00000002)
+#define RCC_PREDIV1_Div4                 ((uint32_t)0x00000003)
+#define RCC_PREDIV1_Div5                 ((uint32_t)0x00000004)
+#define RCC_PREDIV1_Div6                 ((uint32_t)0x00000005)
+#define RCC_PREDIV1_Div7                 ((uint32_t)0x00000006)
+#define RCC_PREDIV1_Div8                 ((uint32_t)0x00000007)
+#define RCC_PREDIV1_Div9                 ((uint32_t)0x00000008)
+#define RCC_PREDIV1_Div10                ((uint32_t)0x00000009)
+#define RCC_PREDIV1_Div11                ((uint32_t)0x0000000A)
+#define RCC_PREDIV1_Div12                ((uint32_t)0x0000000B)
+#define RCC_PREDIV1_Div13                ((uint32_t)0x0000000C)
+#define RCC_PREDIV1_Div14                ((uint32_t)0x0000000D)
+#define RCC_PREDIV1_Div15                ((uint32_t)0x0000000E)
+#define RCC_PREDIV1_Div16                ((uint32_t)0x0000000F)
+
+/* PREDIV1_clock_source */
+#define RCC_PREDIV1_Source_HSE           ((uint32_t)0x00000000)
+#define RCC_PREDIV1_Source_PLL2          ((uint32_t)0x00010000)
+
+/* PREDIV2_division_factor */
+#define RCC_PREDIV2_Div1                 ((uint32_t)0x00000000)
+#define RCC_PREDIV2_Div2                 ((uint32_t)0x00000010)
+#define RCC_PREDIV2_Div3                 ((uint32_t)0x00000020)
+#define RCC_PREDIV2_Div4                 ((uint32_t)0x00000030)
+#define RCC_PREDIV2_Div5                 ((uint32_t)0x00000040)
+#define RCC_PREDIV2_Div6                 ((uint32_t)0x00000050)
+#define RCC_PREDIV2_Div7                 ((uint32_t)0x00000060)
+#define RCC_PREDIV2_Div8                 ((uint32_t)0x00000070)
+#define RCC_PREDIV2_Div9                 ((uint32_t)0x00000080)
+#define RCC_PREDIV2_Div10                ((uint32_t)0x00000090)
+#define RCC_PREDIV2_Div11                ((uint32_t)0x000000A0)
+#define RCC_PREDIV2_Div12                ((uint32_t)0x000000B0)
+#define RCC_PREDIV2_Div13                ((uint32_t)0x000000C0)
+#define RCC_PREDIV2_Div14                ((uint32_t)0x000000D0)
+#define RCC_PREDIV2_Div15                ((uint32_t)0x000000E0)
+#define RCC_PREDIV2_Div16                ((uint32_t)0x000000F0)
+
+/* PLL2_multiplication_factor */
+#define RCC_PLL2Mul_2_5                  ((uint32_t)0x00000000)
+#define RCC_PLL2Mul_12_5                 ((uint32_t)0x00000100)
+#define RCC_PLL2Mul_4                    ((uint32_t)0x00000200)
+#define RCC_PLL2Mul_5                    ((uint32_t)0x00000300)
+#define RCC_PLL2Mul_6                    ((uint32_t)0x00000400)
+#define RCC_PLL2Mul_7                    ((uint32_t)0x00000500)
+#define RCC_PLL2Mul_8                    ((uint32_t)0x00000600)
+#define RCC_PLL2Mul_9                    ((uint32_t)0x00000700)
+#define RCC_PLL2Mul_10                   ((uint32_t)0x00000800)
+#define RCC_PLL2Mul_11                   ((uint32_t)0x00000900)
+#define RCC_PLL2Mul_12                   ((uint32_t)0x00000A00)
+#define RCC_PLL2Mul_13                   ((uint32_t)0x00000B00)
+#define RCC_PLL2Mul_14                   ((uint32_t)0x00000C00)
+#define RCC_PLL2Mul_15                   ((uint32_t)0x00000D00)
+#define RCC_PLL2Mul_16                   ((uint32_t)0x00000E00)
+#define RCC_PLL2Mul_20                   ((uint32_t)0x00000F00)
+
+/* PLL3_multiplication_factor */
+#define RCC_PLL3Mul_2_5                  ((uint32_t)0x00000000)
+#define RCC_PLL3Mul_12_5                 ((uint32_t)0x00001000)
+#define RCC_PLL3Mul_4                    ((uint32_t)0x00002000)
+#define RCC_PLL3Mul_5                    ((uint32_t)0x00003000)
+#define RCC_PLL3Mul_6                    ((uint32_t)0x00004000)
+#define RCC_PLL3Mul_7                    ((uint32_t)0x00005000)
+#define RCC_PLL3Mul_8                    ((uint32_t)0x00006000)
+#define RCC_PLL3Mul_9                    ((uint32_t)0x00007000)
+#define RCC_PLL3Mul_10                   ((uint32_t)0x00008000)
+#define RCC_PLL3Mul_11                   ((uint32_t)0x00009000)
+#define RCC_PLL3Mul_12                   ((uint32_t)0x0000A000)
+#define RCC_PLL3Mul_13                   ((uint32_t)0x0000B000)
+#define RCC_PLL3Mul_14                   ((uint32_t)0x0000C000)
+#define RCC_PLL3Mul_15                   ((uint32_t)0x0000D000)
+#define RCC_PLL3Mul_16                   ((uint32_t)0x0000E000)
+#define RCC_PLL3Mul_20                   ((uint32_t)0x0000F000)
+
+/* System_clock_source */
+#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
+
+/* AHB_clock_source */
+#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
+
+/* APB1_APB2_clock_source */
+#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
+
+/* RCC_Interrupt_source */
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_PLL2RDY                   ((uint8_t)0x20)
+#define RCC_IT_PLL3RDY                   ((uint8_t)0x40)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+
+/* USB_OTG_FS_clock_source */
+#define RCC_OTGFSCLKSource_PLLCLK_Div1   ((uint8_t)0x00)
+#define RCC_OTGFSCLKSource_PLLCLK_Div2   ((uint8_t)0x01)
+#define RCC_OTGFSCLKSource_PLLCLK_Div3   ((uint8_t)0x02)
+
+/* I2S2_clock_source */
+#define RCC_I2S2CLKSource_SYSCLK         ((uint8_t)0x00)
+#define RCC_I2S2CLKSource_PLL3_VCO       ((uint8_t)0x01)
+
+/* I2S3_clock_source */
+#define RCC_I2S3CLKSource_SYSCLK         ((uint8_t)0x00)
+#define RCC_I2S3CLKSource_PLL3_VCO       ((uint8_t)0x01)
+
+/* ADC_clock_source */
+#define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
+
+/* LSE_configuration */
+#define RCC_LSE_OFF                      ((uint8_t)0x00)
+#define RCC_LSE_ON                       ((uint8_t)0x01)
+#define RCC_LSE_Bypass                   ((uint8_t)0x04)
+
+/* RTC_clock_source */
+#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
+
+/* AHB_peripheral */
+#define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
+#define RCC_AHBPeriph_FSMC               ((uint32_t)0x00000100)
+#define RCC_AHBPeriph_RNG                ((uint32_t)0x00000200)
+#define RCC_AHBPeriph_SDIO               ((uint32_t)0x00000400)
+#define RCC_AHBPeriph_USBHS              ((uint32_t)0x00000800)
+#define RCC_AHBPeriph_OTG_FS             ((uint32_t)0x00001000)
+#define RCC_AHBPeriph_DVP                ((uint32_t)0x00002000)
+#define RCC_AHBPeriph_ETH_MAC            ((uint32_t)0x00004000)
+#define RCC_AHBPeriph_ETH_MAC_Tx         ((uint32_t)0x00008000)
+#define RCC_AHBPeriph_ETH_MAC_Rx         ((uint32_t)0x00010000)
+
+/* APB2_peripheral */
+#define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
+#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)
+#define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)
+#define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)
+
+/* APB1_peripheral */
+#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
+#define RCC_APB1Periph_UART6             ((uint32_t)0x00000040)
+#define RCC_APB1Periph_UART7             ((uint32_t)0x00000080)
+#define RCC_APB1Periph_UART8             ((uint32_t)0x00000100)
+#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
+#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
+#define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
+
+/* Clock_source_to_output_on_MCO_pin */
+#define RCC_MCO_NoClock                  ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
+#define RCC_MCO_HSI                      ((uint8_t)0x05)
+#define RCC_MCO_HSE                      ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
+#define RCC_MCO_PLL2CLK                  ((uint8_t)0x08)
+#define RCC_MCO_PLL3CLK_Div2             ((uint8_t)0x09)
+#define RCC_MCO_XT1                      ((uint8_t)0x0A)
+#define RCC_MCO_PLL3CLK                  ((uint8_t)0x0B)
+
+/* RCC_Flag */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+#define RCC_FLAG_PLL2RDY                 ((uint8_t)0x3B)
+#define RCC_FLAG_PLL3RDY                 ((uint8_t)0x3D)
+
+/* SysTick_clock_source */
+#define SysTick_CLKSource_HCLK_Div8      ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK           ((uint32_t)0x00000004)
+
+/* RNG_clock_source */
+#define RCC_RNGCLKSource_SYSCLK          ((uint32_t)0x00)
+#define RCC_RNGCLKSource_PLL3_VCO        ((uint32_t)0x01)
+
+/* ETH1G_clock_source */
+#define RCC_ETH1GCLKSource_PLL2_VCO      ((uint32_t)0x00)
+#define RCC_ETH1GCLKSource_PLL3_VCO      ((uint32_t)0x01)
+#define RCC_ETH1GCLKSource_PB1_IN        ((uint32_t)0x02)
+
+/* USBFS_clock_source */
+#define RCC_USBPLL_Div1                  ((uint32_t)0x00)
+#define RCC_USBPLL_Div2                  ((uint32_t)0x01)
+#define RCC_USBPLL_Div3                  ((uint32_t)0x02)
+#define RCC_USBPLL_Div4                  ((uint32_t)0x03)
+#define RCC_USBPLL_Div5                  ((uint32_t)0x04)
+#define RCC_USBPLL_Div6                  ((uint32_t)0x05)
+#define RCC_USBPLL_Div7                  ((uint32_t)0x06)
+#define RCC_USBPLL_Div8                  ((uint32_t)0x07)
+
+/* USBHSPLL_clock_source */
+#define RCC_HSBHSPLLCLKSource_HSE        ((uint32_t)0x00)
+#define RCC_HSBHSPLLCLKSource_HSI        ((uint32_t)0x01)
+
+/* USBHSPLLCKREF_clock_select */
+#define RCC_USBHSPLLCKREFCLK_3M          ((uint32_t)0x00)
+#define RCC_USBHSPLLCKREFCLK_4M          ((uint32_t)0x01)
+#define RCC_USBHSPLLCKREFCLK_8M          ((uint32_t)0x02)
+#define RCC_USBHSPLLCKREFCLK_5M          ((uint32_t)0x03)
+
+/* USBCLK48M_clock_source */
+#define RCC_USBCLK48MCLKSource_PLLCLK    ((uint32_t)0x00)
+#define RCC_USBCLK48MCLKSource_USBPHY    ((uint32_t)0x01)
+
+
+void RCC_DeInit(void);
+void RCC_HSEConfig(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCOConfig(uint8_t RCC_MCO);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
+void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
+void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
+void RCC_PLL2Cmd(FunctionalState NewState);
+void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
+void RCC_PLL3Cmd(FunctionalState NewState);
+void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource);
+void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
+void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+
+void RCC_ADCCLKADJcmd(FunctionalState NewState);
+void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource);
+void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource);
+void RCC_ETH1G_125Mcmd(FunctionalState NewState);
+void RCC_USBHSConfig(uint32_t RCC_USBHS);
+void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource);
+void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource);
+void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState);
+void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+

demo/ch32/ch32v307/SRC/Peripheral/inc/ch32v30x_usart.h

@@ -0,0 +1,193 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_usart.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains all the functions prototypes for the 
+*                      USART firmware library.
+*******************************************************************************/ 
+#ifndef __CH32V30x_USART_H
+#define __CH32V30x_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v30x.h"
+ 
+
+/* USART Init Structure definition */  
+typedef struct
+{
+  uint32_t USART_BaudRate;            /* This member configures the USART communication baud rate.
+                                         The baud rate is computed using the following formula:
+                                          - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+                                          - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+  uint16_t USART_WordLength;          /* Specifies the number of data bits transmitted or received in a frame.
+                                         This parameter can be a value of @ref USART_Word_Length */
+
+  uint16_t USART_StopBits;            /* Specifies the number of stop bits transmitted.
+                                         This parameter can be a value of @ref USART_Stop_Bits */
+
+  uint16_t USART_Parity;              /* Specifies the parity mode.
+                                         This parameter can be a value of @ref USART_Parity
+                                         @note When parity is enabled, the computed parity is inserted
+                                               at the MSB position of the transmitted data (9th bit when
+                                               the word length is set to 9 data bits; 8th bit when the
+                                               word length is set to 8 data bits). */
+ 
+  uint16_t USART_Mode;                /* Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                         This parameter can be a value of @ref USART_Mode */
+
+  uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
+                                         or disabled.
+                                         This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/* USART Clock Init Structure definition */  
+typedef struct
+{
+
+  uint16_t USART_Clock;   /* Specifies whether the USART clock is enabled or disabled.
+                             This parameter can be a value of @ref USART_Clock */
+
+  uint16_t USART_CPOL;    /* Specifies the steady state value of the serial clock.
+                             This parameter can be a value of @ref USART_Clock_Polarity */
+
+  uint16_t USART_CPHA;    /* Specifies the clock transition on which the bit capture is made.
+                             This parameter can be a value of @ref USART_Clock_Phase */
+
+  uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
+                             data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                             This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* USART_Word_Length */ 
+#define USART_WordLength_8b                  ((uint16_t)0x0000)
+#define USART_WordLength_9b                  ((uint16_t)0x1000)
+                                    
+/* USART_Stop_Bits */  
+#define USART_StopBits_1                     ((uint16_t)0x0000)
+#define USART_StopBits_0_5                   ((uint16_t)0x1000)
+#define USART_StopBits_2                     ((uint16_t)0x2000)
+#define USART_StopBits_1_5                   ((uint16_t)0x3000)
+
+/* USART_Parity */  
+#define USART_Parity_No                      ((uint16_t)0x0000)
+#define USART_Parity_Even                    ((uint16_t)0x0400)
+#define USART_Parity_Odd                     ((uint16_t)0x0600) 
+
+/* USART_Mode */ 
+#define USART_Mode_Rx                        ((uint16_t)0x0004)
+#define USART_Mode_Tx                        ((uint16_t)0x0008)
+
+/* USART_Hardware_Flow_Control */
+#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
+
+/* USART_Clock */
+#define USART_Clock_Disable                  ((uint16_t)0x0000)
+#define USART_Clock_Enable                   ((uint16_t)0x0800)
+
+/* USART_Clock_Polarity */  
+#define USART_CPOL_Low                       ((uint16_t)0x0000)
+#define USART_CPOL_High                      ((uint16_t)0x0400)
+
+/* USART_Clock_Phase */
+#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
+#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
+
+/* USART_Last_Bit */
+#define USART_LastBit_Disable                ((uint16_t)0x0000)
+#define USART_LastBit_Enable                 ((uint16_t)0x0100)
+
+/* USART_Interrupt_definition */  
+#define USART_IT_PE                          ((uint16_t)0x0028)
+#define USART_IT_TXE                         ((uint16_t)0x0727)
+#define USART_IT_TC                          ((uint16_t)0x0626)
+#define USART_IT_RXNE                        ((uint16_t)0x0525)
+#define USART_IT_ORE_RX                      ((uint16_t)0x0325)
+#define USART_IT_IDLE                        ((uint16_t)0x0424)
+#define USART_IT_LBD                         ((uint16_t)0x0846)
+#define USART_IT_CTS                         ((uint16_t)0x096A)
+#define USART_IT_ERR                         ((uint16_t)0x0060)
+#define USART_IT_ORE_ER                      ((uint16_t)0x0360)
+#define USART_IT_NE                          ((uint16_t)0x0260)
+#define USART_IT_FE                          ((uint16_t)0x0160)
+
+#define USART_IT_ORE                          USART_IT_ORE_ER
+
+/* USART_DMA_Requests */
+#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
+#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
+
+/* USART_WakeUp_methods */
+#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
+
+/* USART_LIN_Break_Detection_Length */
+#define USART_LINBreakDetectLength_10b       ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b       ((uint16_t)0x0020)
+
+/* USART_IrDA_Low_Power */
+#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
+
+/* USART_Flags */
+#define USART_FLAG_CTS                       ((uint16_t)0x0200)
+#define USART_FLAG_LBD                       ((uint16_t)0x0100)
+#define USART_FLAG_TXE                       ((uint16_t)0x0080)
+#define USART_FLAG_TC                        ((uint16_t)0x0040)
+#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
+#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
+#define USART_FLAG_ORE                       ((uint16_t)0x0008)
+#define USART_FLAG_NE                        ((uint16_t)0x0004)
+#define USART_FLAG_FE                        ((uint16_t)0x0002)
+#define USART_FLAG_PE                        ((uint16_t)0x0001)
+
+
+void USART_DeInit(USART_TypeDef* USARTx);
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+void USART_SendBreak(USART_TypeDef* USARTx);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif 
+
+
+
+
+
+
+

demo/ch32/ch32v307/SRC/Peripheral/src/ch32v30x_gpio.c

@@ -0,0 +1,568 @@
+/********************************** (C) COPYRIGHT  *******************************
+* File Name          : ch32v30x_gpio.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the GPIO firmware functions. 
+*******************************************************************************/
+#include "ch32v30x_gpio.h"
+#include "ch32v30x_rcc.h"
+
+/* MASK */
+#define ECR_PORTPINCONFIG_MASK      ((uint16_t)0xFF80)
+#define LSB_MASK                    ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK        ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCFG_MASK          ((uint32_t)0xF0FFFFFF)
+#define DBGAFR_LOCATION_MASK        ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK         ((uint32_t)0x00100000)
+
+
+/*********************************************************************
+ * @fn      GPIO_DeInit
+ *
+ * @brief   Deinitializes the GPIOx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  none
+ */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+  if (GPIOx == GPIOA)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
+  }
+  else if (GPIOx == GPIOD)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
+  }    
+  else if (GPIOx == GPIOE)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
+  } 
+}
+
+/*********************************************************************
+ * @fn      GPIO_AFIODeInit
+ *
+ * @brief   Deinitializes the Alternate Functions (remap, event control
+ *        and EXTI configuration) registers to their default reset values.
+ *
+ * @return  none
+ */
+void GPIO_AFIODeInit(void)
+{
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
+}
+
+/*********************************************************************
+ * @fn      GPIO_Init
+ *
+ * @brief   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @param   GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that
+ *        contains the configuration information for the specified GPIO peripheral.
+ *
+ * @return  none
+ */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+  uint32_t tmpreg = 0x00, pinmask = 0x00;
+
+  currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+	
+  if ((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
+  { 
+    currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
+  }
+
+  if (((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
+  {
+    tmpreg = GPIOx->CFGLR;
+		
+    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+    {
+      pos = ((uint32_t)0x01) << pinpos;
+      currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+			
+      if (currentpin == pos)
+      {
+        pos = pinpos << 2;
+        pinmask = ((uint32_t)0x0F) << pos;
+        tmpreg &= ~pinmask;
+        tmpreg |= (currentmode << pos);
+
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+        {
+          GPIOx->BCR = (((uint32_t)0x01) << pinpos);
+        }
+        else
+        {
+          if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+          {
+            GPIOx->BSHR = (((uint32_t)0x01) << pinpos);
+          }
+        }
+      }
+    }
+    GPIOx->CFGLR = tmpreg;
+  }
+
+  if (GPIO_InitStruct->GPIO_Pin > 0x00FF)
+  {
+    tmpreg = GPIOx->CFGHR;
+		
+    for (pinpos = 0x00; pinpos < 0x08; pinpos++)
+    {
+      pos = (((uint32_t)0x01) << (pinpos + 0x08));
+      currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
+			
+      if (currentpin == pos)
+      {
+        pos = pinpos << 2;
+        pinmask = ((uint32_t)0x0F) << pos;
+        tmpreg &= ~pinmask;
+        tmpreg |= (currentmode << pos);
+
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+        {
+          GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08));
+        }
+
+        if (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+        {
+          GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08));
+        }
+      }
+    }
+    GPIOx->CFGHR = tmpreg;
+  }
+}
+
+/*********************************************************************
+ * @fn      GPIO_StructInit
+ *
+ * @brief   Fills each GPIO_InitStruct member with its default
+ *
+ * @param   GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure
+ *      which will be initialized.
+ *
+ * @return  none
+ */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadInputDataBit
+ *
+ * @brief   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @param    GPIO_Pin - specifies the port bit to read.
+ *             This parameter can be GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+  
+  if ((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+	
+  return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadInputData
+ *
+ * @brief   Reads the specified GPIO input data port.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  The output port pin value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+  return ((uint16_t)GPIOx->INDR);
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadOutputDataBit
+ *
+ * @brief   Reads the specified output data port bit.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bit to read.
+ *            This parameter can be GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+ 
+  if ((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+	
+  return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadOutputData
+ *
+ * @brief   Reads the specified GPIO output data port.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  GPIO output port pin value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{ 
+  return ((uint16_t)GPIOx->OUTDR);
+}
+
+/*********************************************************************
+ * @fn      GPIO_SetBits
+ *
+ * @brief   Sets the selected data port bits.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bits to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  GPIOx->BSHR = GPIO_Pin;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ResetBits
+ *
+ * @brief   Clears the selected data port bits.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bits to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  GPIOx->BCR = GPIO_Pin;
+}
+
+/*********************************************************************
+ * @fn      GPIO_WriteBit
+ *
+ * @brief   Sets or clears the selected data port bit.
+ *
+ * @param   GPIO_Pin - specifies the port bit to be written.
+ *            This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ *          BitVal - specifies the value to be written to the selected bit.
+ *            Bit_SetL - to clear the port pin.
+ *            Bit_SetH - to set the port pin.
+ *
+ * @return  none
+ */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+  if (BitVal != Bit_RESET)
+  {
+    GPIOx->BSHR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BCR = GPIO_Pin;
+  }
+}
+
+/*********************************************************************
+ * @fn      GPIO_Write
+ *
+ * @brief   Writes data to the specified GPIO data port.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          PortVal - specifies the value to be written to the port output data register.
+ *
+ * @return  none
+ */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+  GPIOx->OUTDR = PortVal;
+}
+
+/*********************************************************************
+ * @fn      GPIO_PinLockConfig
+ *
+ * @brief   Locks GPIO Pins configuration registers.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bit to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint32_t tmp = 0x00010000;
+  
+  tmp |= GPIO_Pin;
+  GPIOx->LCKR = tmp;
+  GPIOx->LCKR =  GPIO_Pin;
+  GPIOx->LCKR = tmp;
+  tmp = GPIOx->LCKR;
+  tmp = GPIOx->LCKR;
+}
+
+/*********************************************************************
+ * @fn      GPIO_EventOutputConfig
+ *
+ * @brief   Selects the GPIO pin used as Event output.
+ *
+ * @param   GPIO_PortSource - selects the GPIO port to be used as source
+ *        for Event output.
+ *            This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
+ *          GPIO_PinSource - specifies the pin for the Event output.
+ *            This parameter can be GPIO_PinSourcex where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+  uint32_t tmpreg = 0x00;
+  
+  tmpreg = AFIO->ECR;
+  tmpreg &= ECR_PORTPINCONFIG_MASK;
+  tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
+  tmpreg |= GPIO_PinSource;
+  AFIO->ECR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      GPIO_EventOutputCmd
+ *
+ * @brief   Enables or disables the Event Output.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void GPIO_EventOutputCmd(FunctionalState NewState)
+{
+	if(NewState)
+	{
+		AFIO->ECR |= (1<<7);
+	}
+	else
+	{
+		AFIO->ECR &= ~(1<<7);		
+	}
+}
+
+/*********************************************************************
+ * @fn      GPIO_PinRemapConfig
+ *
+ * @brief   Changes the mapping of the specified pin.
+ *
+ * @param   GPIO_Remap - selects the pin to remap.
+ *            GPIO_Remap_SPI1 - SPI1 Alternate Function mapping
+ *            GPIO_Remap_I2C1 - I2C1 Alternate Function mapping
+ *            GPIO_Remap_USART1 - USART1 Alternate Function mapping
+ *            GPIO_Remap_USART2 - USART2 Alternate Function mapping
+ *            GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping
+ *            GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping
+ *            GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping
+ *            GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping
+ *            GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping
+ *            GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping
+ *            GPIO_Remap_TIM4 - TIM4 Alternate Function mapping
+ *            GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping
+ *            GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping
+ *            GPIO_Remap_PD01 - PD01 Alternate Function mapping
+ *            GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping
+ *            GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping
+ *            GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping
+ *            GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping
+ *            GPIO_Remap_ETH - Ethernet remapping
+ *            GPIO_Remap_CAN2 - CAN2 remapping
+ *            GPIO_Remap_MII_RMII_SEL - MII or RMII selection
+ *            GPIO_Remap_SWJ_NoJTRST - Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
+ *            GPIO_Remap_SWJ_JTAGDisable - JTAG-DP Disabled and SW-DP Enabled
+ *            GPIO_Remap_SWJ_Disable - Full SWJ Disabled (JTAG-DP + SW-DP)
+ *            GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+ *        to TIM2 Internal Trigger 1 for calibration
+ *            GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame)
+ *            GPIO_Remap_TIM8 - TIM8 Alternate Function mapping
+ *            GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping
+ *            GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping
+ *            GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping
+ *            GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping
+ *            GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
+{
+  uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+
+  if((GPIO_Remap & 0x80000000) == 0x80000000)
+  {
+    tmpreg = AFIO->PCFR2;
+  }
+  else
+  {
+    tmpreg = AFIO->PCFR1;
+  }
+
+  tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
+  tmp = GPIO_Remap & LSB_MASK;
+
+  /* Clear bit */
+  if((GPIO_Remap & 0x80000000) == 0x80000000){ /* PCFR2 */
+      if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */
+      {
+          tmp1 = ((uint32_t)0x03) << (tmpmask+0x10);
+          tmpreg &= ~tmp1;
+      }
+      else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)  /* [15:0] 2bit */
+      {
+        tmp1 = ((uint32_t)0x03) << tmpmask;
+        tmpreg &= ~tmp1;
+      }
+      else /* [31:0] 1bit */
+      {
+        tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
+      }
+
+  }
+  else{ /* PCFR1 */
+      if ((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */
+      {
+        tmpreg &= DBGAFR_SWJCFG_MASK;
+        AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK;
+      }
+      else if ((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
+      {
+        tmp1 = ((uint32_t)0x03) << tmpmask;
+        tmpreg &= ~tmp1;
+        tmpreg |= ~DBGAFR_SWJCFG_MASK;
+      }
+      else /* [31:0] 1bit */
+      {
+        tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15)*0x10));
+        tmpreg |= ~DBGAFR_SWJCFG_MASK;
+      }
+  }
+
+  /* Set bit */
+  if (NewState != DISABLE)
+  {
+    tmpreg |= (tmp << ((GPIO_Remap >> 0x15)*0x10));
+  }
+
+  if((GPIO_Remap & 0x80000000) == 0x80000000)
+  {
+    AFIO->PCFR2 = tmpreg;
+  }
+  else
+  {
+    AFIO->PCFR1 = tmpreg;
+  }  
+}
+
+/*********************************************************************
+ * @fn      GPIO_EXTILineConfig
+ *
+ * @brief   Selects the GPIO pin used as EXTI Line.
+ *
+ * @param   GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines.
+ *            This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
+ *          GPIO_PinSource - specifies the EXTI line to be configured.
+ *            This parameter can be GPIO_PinSourcex where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+  uint32_t tmp = 0x00;
+
+  tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
+  AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
+  AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
+}
+
+/*********************************************************************
+ * @fn      GPIO_ETH_MediaInterfaceConfig
+ *
+ * @brief   Selects the Ethernet media interface.
+ *
+ * @param   GPIO_ETH_MediaInterface - specifies the Media Interface mode.
+ *            GPIO_ETH_MediaInterface_MII - MII mode
+ *            GPIO_ETH_MediaInterface_RMII - RMII mode
+ *
+ * @return  none
+ */
+void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
+{
+    if(GPIO_ETH_MediaInterface)
+    {
+        AFIO->PCFR1 |= (1<<23);
+    }
+    else
+    {
+        AFIO->PCFR1 &= ~(1<<23);
+    }
+}
+
+
+
+

demo/ch32/ch32v307/SRC/Peripheral/src/ch32v30x_misc.c

@@ -0,0 +1,109 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_misc.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the miscellaneous firmware functions .
+*********************************************************************************/
+#include "ch32v30x_misc.h"
+
+__IO uint32_t NVIC_Priority_Group = 0;
+
+
+/*********************************************************************
+ * @fn      NVIC_PriorityGroupConfig
+ *
+ * @brief   Configures the priority grouping - pre-emption priority and subpriority.
+ *
+ * @param   NVIC_PriorityGroup - specifies the priority grouping bits length.
+ *            NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
+ *                                   4 bits for subpriority
+ *            NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
+ *                                   3 bits for subpriority
+ *            NVIC_PriorityGroup_2 - 2 bits for pre-emption priority
+ *                                   2 bits for subpriority
+ *            NVIC_PriorityGroup_3 - 3 bits for pre-emption priority
+ *                                   1 bits for subpriority
+ *            NVIC_PriorityGroup_4 - 4 bits for pre-emption priority
+ *                                   0 bits for subpriority
+ *
+ * @return  none
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+	NVIC_Priority_Group = NVIC_PriorityGroup;
+}
+
+/*********************************************************************
+ * @fn      NVIC_Init
+ *
+ * @brief   Initializes the NVIC peripheral according to the specified parameters in
+ *        the NVIC_InitStruct.
+ *
+ * @param   NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
+ *        configuration information for the specified NVIC peripheral.
+ *
+ * @return  none
+ */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+	uint8_t tmppre = 0;
+
+	if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
+	{
+		NVIC_SetPriority( NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority<<4);
+	}
+	else if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
+	{
+    if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1)
+    {
+    	NVIC_SetPriority( NVIC_InitStruct->NVIC_IRQChannel, (1<<7)|(NVIC_InitStruct->NVIC_IRQChannelSubPriority<<4));
+    }
+    else
+    {
+    	NVIC_SetPriority( NVIC_InitStruct->NVIC_IRQChannel, (0<<7)|(NVIC_InitStruct->NVIC_IRQChannelSubPriority<<4));
+    }
+	}
+	else if(NVIC_Priority_Group == NVIC_PriorityGroup_2)
+	{
+    if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1)
+    {
+      tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4*NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
+    	NVIC_SetPriority( NVIC_InitStruct->NVIC_IRQChannel, (0<<7)|(tmppre<<4));
+    }
+    else
+    {
+      tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4*(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority-2));
+    	NVIC_SetPriority( NVIC_InitStruct->NVIC_IRQChannel, (1<<7)|(tmppre<<4));
+    }
+	}
+	else if(NVIC_Priority_Group == NVIC_PriorityGroup_3)
+	{
+    if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3)
+    {
+      tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2*NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
+    	NVIC_SetPriority( NVIC_InitStruct->NVIC_IRQChannel, (0<<7)|(tmppre<<4));
+    }
+    else
+    {
+      tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2*(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority-4));
+    	NVIC_SetPriority( NVIC_InitStruct->NVIC_IRQChannel, (1<<7)|(tmppre<<4));
+    }
+	}
+	else if(NVIC_Priority_Group == NVIC_PriorityGroup_4)
+	{
+		NVIC_SetPriority( NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority<<4);
+	}
+
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+  {
+  	NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+  }
+  else
+  {
+  	NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+  }
+}
+
+
+

demo/ch32/ch32v307/SRC/Peripheral/src/ch32v30x_rcc.c

@@ -0,0 +1,1391 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_rcc.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the RCC firmware functions.
+*******************************************************************************/ 
+#include "ch32v30x_rcc.h"
+
+/* RCC registers bit address in the alias region */
+#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
+
+/* BDCTLR Register */
+#define BDCTLR_OFFSET             (RCC_OFFSET + 0x20)
+
+/* RCC registers bit mask */
+
+/* CTLR register bit mask */
+#define CTLR_HSEBYP_Reset           ((uint32_t)0xFFFBFFFF)
+#define CTLR_HSEBYP_Set             ((uint32_t)0x00040000)
+#define CTLR_HSEON_Reset            ((uint32_t)0xFFFEFFFF)
+#define CTLR_HSEON_Set              ((uint32_t)0x00010000)
+#define CTLR_HSITRIM_Mask           ((uint32_t)0xFFFFFF07)
+
+#define CFGR0_PLL_Mask              ((uint32_t)0xFFC0FFFF)  /* 103 */
+#define CFGR0_PLL_Mask_1            ((uint32_t)0xFFC2FFFF)  /* 107 */
+
+#define CFGR0_PLLMull_Mask          ((uint32_t)0x003C0000)
+#define CFGR0_PLLSRC_Mask           ((uint32_t)0x00010000)
+#define CFGR0_PLLXTPRE_Mask         ((uint32_t)0x00020000)
+#define CFGR0_SWS_Mask              ((uint32_t)0x0000000C)
+#define CFGR0_SW_Mask               ((uint32_t)0xFFFFFFFC)
+#define CFGR0_HPRE_Reset_Mask       ((uint32_t)0xFFFFFF0F)
+#define CFGR0_HPRE_Set_Mask         ((uint32_t)0x000000F0)
+#define CFGR0_PPRE1_Reset_Mask      ((uint32_t)0xFFFFF8FF)
+#define CFGR0_PPRE1_Set_Mask        ((uint32_t)0x00000700)
+#define CFGR0_PPRE2_Reset_Mask      ((uint32_t)0xFFFFC7FF)
+#define CFGR0_PPRE2_Set_Mask        ((uint32_t)0x00003800)
+#define CFGR0_ADCPRE_Reset_Mask     ((uint32_t)0xFFFF3FFF)
+#define CFGR0_ADCPRE_Set_Mask       ((uint32_t)0x0000C000)
+
+/* RSTSCKR register bit mask */
+#define RSTSCKR_RMVF_Set            ((uint32_t)0x01000000)
+
+/* CFGR2 register bit mask */
+#define CFGR2_PREDIV1SRC            ((uint32_t)0x00010000)
+#define CFGR2_PREDIV1               ((uint32_t)0x0000000F)
+#define CFGR2_PREDIV2               ((uint32_t)0x000000F0)
+#define CFGR2_PLL2MUL               ((uint32_t)0x00000F00)
+#define CFGR2_PLL3MUL               ((uint32_t)0x0000F000)
+
+/* RCC Flag Mask */
+#define FLAG_Mask                   ((uint8_t)0x1F)
+
+/* INTR register byte 2 (Bits[15:8]) base address */
+#define INTR_BYTE2_ADDRESS          ((uint32_t)0x40021009)
+
+/* INTR register byte 3 (Bits[23:16]) base address */
+#define INTR_BYTE3_ADDRESS          ((uint32_t)0x4002100A)
+
+/* CFGR0 register byte 4 (Bits[31:24]) base address */
+#define CFGR0_BYTE4_ADDRESS         ((uint32_t)0x40021007)
+
+/* BDCTLR register base address */
+#define BDCTLR_ADDRESS              (PERIPH_BASE + BDCTLR_OFFSET)
+
+
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
+
+/*********************************************************************
+ * @fn      RCC_DeInit
+ *
+ * @brief   Resets the RCC clock configuration to the default reset state.
+ *
+ * @return  none
+ */
+void RCC_DeInit(void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;  
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+  RCC->INTR = 0x009F0000;
+}
+
+/*********************************************************************
+ * @fn      RCC_HSEConfig
+ *
+ * @brief   Configures the External High Speed oscillator (HSE).
+ *
+ * @param   RCC_HSE -
+ *            RCC_HSE_OFF - HSE oscillator OFF.
+ *            RCC_HSE_ON - HSE oscillator ON.
+ *            RCC_HSE_Bypass - HSE oscillator bypassed with external clock.
+ *
+ * @return  none
+ */
+void RCC_HSEConfig(uint32_t RCC_HSE)
+{
+  RCC->CTLR &= CTLR_HSEON_Reset;
+  RCC->CTLR &= CTLR_HSEBYP_Reset;
+
+  switch(RCC_HSE)
+  {
+    case RCC_HSE_ON:
+      RCC->CTLR |= CTLR_HSEON_Set;
+      break;
+      
+    case RCC_HSE_Bypass:
+      RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set;
+      break;
+      
+    default:
+      break;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_WaitForHSEStartUp
+ *
+ * @brief   Waits for HSE start-up.
+ *
+ * @return  SUCCESS - HSE oscillator is stable and ready to use.
+ *                  ERROR - HSE oscillator not yet ready.
+ */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+  __IO uint32_t StartUpCounter = 0;
+	
+  ErrorStatus status = ERROR;
+  FlagStatus HSEStatus = RESET;
+  
+  do
+  {
+    HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+    StartUpCounter++;  
+  } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+  
+  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+  {
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }  
+	
+  return (status);
+}
+
+/*********************************************************************
+ * @fn      RCC_AdjustHSICalibrationValue
+ *
+ * @brief   Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ *
+ * @param   HSICalibrationValue - specifies the calibration trimming value.
+ *                    This parameter must be a number between 0 and 0x1F.
+ *
+ * @return  none
+ */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CTLR;
+  tmpreg &= CTLR_HSITRIM_Mask;
+  tmpreg |= (uint32_t)HSICalibrationValue << 3;
+  RCC->CTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_HSICmd
+ *
+ * @brief   Enables or disables the Internal High Speed oscillator (HSI).
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_HSICmd(FunctionalState NewState)
+{
+	if(NewState)
+	{
+		RCC->CTLR |= (1<<0);
+	}
+	else{
+		RCC->CTLR &= ~(1<<0);		
+	}
+}
+
+/*********************************************************************
+ * @fn      RCC_PLLConfig
+ *
+ * @brief   Configures the PLL clock source and multiplication factor.
+ *
+ * @param   RCC_PLLSource - specifies the PLL entry clock source.
+ *            RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2
+ *        selected as PLL clock entry.
+ *            RCC_PLLSource_PREDIV1 - PREDIV1 clock selected as PLL clock
+ *        entry.
+ *          RCC_PLLMul - specifies the PLL multiplication factor.
+ *            This parameter can be RCC_PLLMul_x where x:[2,16].
+ *            For CH32V307 -
+ *              RCC_PLLMul_18_EXTEN
+ *              RCC_PLLMul_3_EXTEN
+ *              RCC_PLLMul_4_EXTEN
+ *              RCC_PLLMul_5_EXTEN
+ *              RCC_PLLMul_6_EXTEN
+ *              RCC_PLLMul_7_EXTEN
+ *              RCC_PLLMul_8_EXTEN
+ *              RCC_PLLMul_9_EXTEN
+ *              RCC_PLLMul_10_EXTEN
+ *              RCC_PLLMul_11_EXTEN
+ *              RCC_PLLMul_12_EXTEN
+ *              RCC_PLLMul_13_EXTEN
+ *              RCC_PLLMul_14_EXTEN
+ *              RCC_PLLMul_6_5_EXTEN
+ *              RCC_PLLMul_15_EXTEN
+ *              RCC_PLLMul_16_EXTEN
+ *            For other CH32V30x -
+ *              RCC_PLLMul_2
+ *              RCC_PLLMul_3
+ *              RCC_PLLMul_4
+ *              RCC_PLLMul_5
+ *              RCC_PLLMul_6
+ *              RCC_PLLMul_7
+ *              RCC_PLLMul_8
+ *              RCC_PLLMul_9
+ *              RCC_PLLMul_10
+ *              RCC_PLLMul_11
+ *              RCC_PLLMul_12
+ *              RCC_PLLMul_13
+ *              RCC_PLLMul_14
+ *              RCC_PLLMul_15
+ *              RCC_PLLMul_16
+ *              RCC_PLLMul_18
+ *
+ * @return  none
+ */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR0;
+
+  if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){ /* for other CH32V30x */
+      tmpreg &= CFGR0_PLL_Mask;
+  }
+  else{ /* for CH32V307 */
+      tmpreg &= CFGR0_PLL_Mask_1;
+  }
+
+  tmpreg |= RCC_PLLSource | RCC_PLLMul;
+  RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PLLCmd
+ *
+ * @brief   Enables or disables the PLL.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+	if(NewState)
+	{
+		RCC->CTLR |= (1<<24);
+	}
+	else{
+		RCC->CTLR &= ~(1<<24);		
+	}
+}
+
+/*********************************************************************
+ * @fn      RCC_SYSCLKConfig
+ *
+ * @brief   Configures the system clock (SYSCLK).
+ *
+ * @param   RCC_SYSCLKSource - specifies the clock source used as system clock.
+ *            RCC_SYSCLKSource_HSI - HSI selected as system clock.
+ *            RCC_SYSCLKSource_HSE - HSE selected as system clock.
+ *            RCC_SYSCLKSource_PLLCLK - PLL selected as system clock.
+ *
+ * @return  none
+ */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR0;
+  tmpreg &= CFGR0_SW_Mask;
+  tmpreg |= RCC_SYSCLKSource;
+  RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetSYSCLKSource
+ *
+ * @brief   Returns the clock source used as system clock.
+ *
+ * @return  0x00 - HSI used as system clock.
+ *          0x04 - HSE used as system clock.
+ *          0x08 - PLL used as system clock.
+ */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+  return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask));
+}
+
+/*********************************************************************
+ * @fn      RCC_HCLKConfig
+ *
+ * @brief   Configures the AHB clock (HCLK).
+ *
+ * @param   RCC_SYSCLK - defines the AHB clock divider. This clock is derived from
+ *        the system clock (SYSCLK).
+ *            RCC_SYSCLK_Div1 - AHB clock = SYSCLK.
+ *            RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2.
+ *            RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4.
+ *            RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8.
+ *            RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16.
+ *            RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64.
+ *            RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128.
+ *            RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256.
+ *            RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512.
+ *
+ * @return  none
+ */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR0;
+  tmpreg &= CFGR0_HPRE_Reset_Mask;
+  tmpreg |= RCC_SYSCLK;
+  RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PCLK1Config
+ *
+ * @brief   Configures the Low Speed APB clock (PCLK1).
+ *
+ * @param   RCC_HCLK - defines the APB1 clock divider. This clock is derived from
+ *        the AHB clock (HCLK).
+ *            RCC_HCLK_Div1 - APB1 clock = HCLK.
+ *            RCC_HCLK_Div2 - APB1 clock = HCLK/2.
+ *            RCC_HCLK_Div4 - APB1 clock = HCLK/4.
+ *            RCC_HCLK_Div8 - APB1 clock = HCLK/8.
+ *            RCC_HCLK_Div16 - APB1 clock = HCLK/16.
+ *
+ * @return  none
+ */
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR0;
+  tmpreg &= CFGR0_PPRE1_Reset_Mask;
+  tmpreg |= RCC_HCLK;
+  RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PCLK2Config
+ *
+ * @brief   Configures the High Speed APB clock (PCLK2).
+ *
+ * @param   RCC_HCLK - defines the APB2 clock divider. This clock is derived from
+ *        the AHB clock (HCLK).
+ *            RCC_HCLK_Div1 - APB1 clock = HCLK.
+ *            RCC_HCLK_Div2 - APB1 clock = HCLK/2.
+ *            RCC_HCLK_Div4 - APB1 clock = HCLK/4.
+ *            RCC_HCLK_Div8 - APB1 clock = HCLK/8.
+ *            RCC_HCLK_Div16 - APB1 clock = HCLK/16.
+ *
+ * @return  none
+ */
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR0;
+  tmpreg &= CFGR0_PPRE2_Reset_Mask;
+  tmpreg |= RCC_HCLK << 3;
+  RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_ITConfig
+ *
+ * @brief   Enables or disables the specified RCC interrupts.
+ *
+ * @param   RCC_IT - specifies the RCC interrupt sources to be enabled or disabled.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    *(__IO uint8_t *) INTR_BYTE2_ADDRESS |= RCC_IT;
+  }
+  else
+  {
+    *(__IO uint8_t *) INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_ADCCLKConfig
+ *
+ * @brief   Configures the ADC clock (ADCCLK).
+ *
+ * @param   RCC_PCLK2 - defines the ADC clock divider. This clock is derived from
+ *        the APB2 clock (PCLK2).
+ *          RCC_PCLK2_Div2 - ADC clock = PCLK2/2.
+ *          RCC_PCLK2_Div4 - ADC clock = PCLK2/4.
+ *          RCC_PCLK2_Div6 - ADC clock = PCLK2/6.
+ *          RCC_PCLK2_Div8 - ADC clock = PCLK2/8.
+ *
+ * @return  none
+ */
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR0;
+  tmpreg &= CFGR0_ADCPRE_Reset_Mask;
+  tmpreg |= RCC_PCLK2;
+  RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_LSEConfig
+ *
+ * @brief   Configures the External Low Speed oscillator (LSE).
+ *
+ * @param   RCC_LSE - specifies the new state of the LSE.
+ *            RCC_LSE_OFF - LSE oscillator OFF.
+ *            RCC_LSE_ON - LSE oscillator ON.
+ *            RCC_LSE_Bypass - LSE oscillator bypassed with external clock.
+ *
+ * @return  none
+ */
+void RCC_LSEConfig(uint8_t RCC_LSE)
+{
+  *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF;
+  *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_OFF;
+	
+  switch(RCC_LSE)
+  {
+    case RCC_LSE_ON:
+      *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_ON;
+      break;
+      
+    case RCC_LSE_Bypass:
+      *(__IO uint8_t *) BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
+      break;            
+      
+    default:
+      break;      
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_LSICmd
+ *
+ * @brief   Enables or disables the Internal Low Speed oscillator (LSI).
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_LSICmd(FunctionalState NewState)
+{
+	if(NewState)
+	{
+		RCC->RSTSCKR |= (1<<0);
+	}
+	else{
+		RCC->RSTSCKR &= ~(1<<0);		
+	}	
+}
+
+/*********************************************************************
+ * @fn      RCC_RTCCLKConfig
+ *
+ * @brief   Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
+ *
+ * @param   RCC_RTCCLKSource - specifies the RTC clock source.
+ *            RCC_RTCCLKSource_LSE - LSE selected as RTC clock.
+ *            RCC_RTCCLKSource_LSI - LSI selected as RTC clock.
+ *            RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock.
+ *
+ * @return  none
+ */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+  RCC->BDCTLR |= RCC_RTCCLKSource;
+}
+
+/*********************************************************************
+ * @fn      RCC_RTCCLKCmd
+ *
+ * @brief   This function must be used only after the RTC clock was selected
+ *        using the RCC_RTCCLKConfig function.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+	if(NewState)
+	{
+		RCC->BDCTLR |= (1<<15);
+	}
+	else{
+		RCC->BDCTLR &= ~(1<<15);		
+	}	
+}
+
+/*********************************************************************
+ * @fn      RCC_GetClocksFreq
+ *
+ * @brief   The result of this function could be not correct when using
+ *        fractional value for HSE crystal.
+ *
+ * @param   RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold
+ *        the clocks frequencies.
+ *
+ * @return  none
+ */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+    uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0, Pll_6_5 = 0;
+
+    tmp = RCC->CFGR0 & CFGR0_SWS_Mask;
+
+    switch (tmp)
+    {
+      case 0x00:
+        RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+        break;
+
+      case 0x04:
+        RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+        break;
+
+      case 0x08:
+        pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask;
+        pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask;
+
+        pllmull = ( pllmull >> 18) + 2;
+
+        if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){ /* for other CH32V30x */
+            if(pllmull == 17) pllmull = 18;
+        }
+        else{  /* for CH32V307 */
+            if(pllmull == 2) pllmull = 18;
+            if(pllmull == 15){
+                pllmull = 13;  /* *6.5 */
+                Pll_6_5 = 1;
+            }
+            if(pllmull == 16) pllmull = 15;
+            if(pllmull == 17) pllmull = 16;
+        }
+
+
+        if (pllsource == 0x00)
+        {
+                  if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
+                   RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE) * pllmull;
+                  }
+                  else{
+                   RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >>1) * pllmull;
+                  }
+        }
+        else
+        {
+          if ((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET)
+          {
+            RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
+          }
+          else
+          {
+            RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
+          }
+        }
+
+        if(Pll_6_5 == 1) RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency / 2);
+
+        break;
+
+      default:
+        RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+        break;
+    }
+
+    tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask;
+    tmp = tmp >> 4;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask;
+    tmp = tmp >> 8;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask;
+    tmp = tmp >> 11;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask;
+    tmp = tmp >> 14;
+    presc = ADCPrescTable[tmp];
+    RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
+}
+
+/*********************************************************************
+ * @fn      RCC_AHBPeriphClockCmd
+ *
+ * @brief   Enables or disables the AHB peripheral clock.
+ *
+ * @param   RCC_AHBPeriph - specifies the AHB peripheral to gates its clock.
+ *            RCC_AHBPeriph_DMA1.
+ *            RCC_AHBPeriph_DMA2.
+ *            RCC_AHBPeriph_SRAM.
+ *            RCC_AHBPeriph_CRC.
+ *            RCC_AHBPeriph_FSMC
+ *            RCC_AHBPeriph_RNG
+ *            RCC_AHBPeriph_SDIO
+ *            RCC_AHBPeriph_USBHS
+ *            RCC_AHBPeriph_OTG_FS
+ *            RCC_AHBPeriph_DVP
+ *            RCC_AHBPeriph_ETH_MAC
+ *            RCC_AHBPeriph_ETH_MAC_Tx
+ *            RCC_AHBPeriph_ETH_MAC_Rx
+ *          NewState: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->AHBPCENR |= RCC_AHBPeriph;
+  }
+  else
+  {
+    RCC->AHBPCENR &= ~RCC_AHBPeriph;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB2PeriphClockCmd
+ *
+ * @brief   Enables or disables the High Speed APB (APB2) peripheral clock.
+ *
+ * @param   RCC_APB2Periph - specifies the APB2 peripheral to gates its clock.
+ *            RCC_APB2Periph_AFIO.
+ *            RCC_APB2Periph_GPIOA.
+ *            RCC_APB2Periph_GPIOB.
+ *            RCC_APB2Periph_GPIOC.
+ *            RCC_APB2Periph_GPIOD.
+ *            RCC_APB2Periph_GPIOE
+ *            RCC_APB2Periph_ADC1.
+ *            RCC_APB2Periph_ADC2
+ *            RCC_APB2Periph_TIM1.
+ *            RCC_APB2Periph_SPI1.
+ *            RCC_APB2Periph_TIM8
+ *            RCC_APB2Periph_USART1.
+ *            RCC_APB2Periph_TIM9
+ *            RCC_APB2Periph_TIM10
+ *          NewState - ENABLE or DISABLE
+ *
+ * @return  none
+ */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->APB2PCENR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2PCENR &= ~RCC_APB2Periph;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB1PeriphClockCmd
+ *
+ * @brief   Enables or disables the Low Speed APB (APB1) peripheral clock.
+ *
+ * @param   RCC_APB1Periph - specifies the APB1 peripheral to gates its clock.
+ *            RCC_APB1Periph_TIM2.
+ *            RCC_APB1Periph_TIM3.
+ *            RCC_APB1Periph_TIM4.
+ *            RCC_APB1Periph_TIM5
+ *            RCC_APB1Periph_TIM6
+ *            RCC_APB1Periph_TIM7
+ *            RCC_APB1Periph_UART6
+ *            RCC_APB1Periph_UART7
+ *            RCC_APB1Periph_UART8
+ *            RCC_APB1Periph_WWDG.
+ *            RCC_APB1Periph_SPI2.
+ *            RCC_APB1Periph_SPI3.
+ *            RCC_APB1Periph_USART2.
+ *            RCC_APB1Periph_USART3.
+ *            RCC_APB1Periph_UART4
+ *            RCC_APB1Periph_UART5
+ *            RCC_APB1Periph_I2C1.
+ *            RCC_APB1Periph_I2C2.
+ *            RCC_APB1Periph_USB.
+ *            RCC_APB1Periph_CAN1.
+ *            RCC_APB1Periph_BKP.
+ *            RCC_APB1Periph_PWR.
+ *            RCC_APB1Periph_DAC.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->APB1PCENR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1PCENR &= ~RCC_APB1Periph;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB2PeriphResetCmd
+ *
+ * @brief   Forces or releases High Speed APB (APB2) peripheral reset.
+ *
+ * @param   RCC_APB2Periph - specifies the APB2 peripheral to reset.
+ *            RCC_APB2Periph_AFIO.
+ *            RCC_APB2Periph_GPIOA.
+ *            RCC_APB2Periph_GPIOB.
+ *            RCC_APB2Periph_GPIOC.
+ *            RCC_APB2Periph_GPIOD.
+ *            RCC_APB2Periph_GPIOE
+ *            RCC_APB2Periph_ADC1.
+ *            RCC_APB2Periph_ADC2
+ *            RCC_APB2Periph_TIM1.
+ *            RCC_APB2Periph_SPI1.
+ *            RCC_APB2Periph_TIM8
+ *            RCC_APB2Periph_USART1.
+ *            RCC_APB2Periph_TIM9
+ *            RCC_APB2Periph_TIM10
+ *          NewState - ENABLE or DISABLE
+ *
+ * @return  none
+ */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->APB2PRSTR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2PRSTR &= ~RCC_APB2Periph;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB1PeriphResetCmd
+ *
+ * @brief   Forces or releases Low Speed APB (APB1) peripheral reset.
+ *
+ * @param   RCC_APB1Periph - specifies the APB1 peripheral to reset.
+ *            RCC_APB1Periph_TIM2.
+ *            RCC_APB1Periph_TIM3.
+ *            RCC_APB1Periph_TIM4.
+ *            RCC_APB1Periph_TIM5
+ *            RCC_APB1Periph_TIM6
+ *            RCC_APB1Periph_TIM7
+ *            RCC_APB1Periph_UART6
+ *            RCC_APB1Periph_UART7
+ *            RCC_APB1Periph_UART8
+ *            RCC_APB1Periph_WWDG.
+ *            RCC_APB1Periph_SPI2.
+ *            RCC_APB1Periph_SPI3.
+ *            RCC_APB1Periph_USART2.
+ *            RCC_APB1Periph_USART3.
+ *            RCC_APB1Periph_UART4
+ *            RCC_APB1Periph_UART5
+ *            RCC_APB1Periph_I2C1.
+ *            RCC_APB1Periph_I2C2.
+ *            RCC_APB1Periph_USB.
+ *            RCC_APB1Periph_CAN1.
+ *            RCC_APB1Periph_BKP.
+ *            RCC_APB1Periph_PWR.
+ *            RCC_APB1Periph_DAC.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->APB1PRSTR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1PRSTR &= ~RCC_APB1Periph;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_BackupResetCmd
+ *
+ * @brief   Forces or releases the Backup domain reset.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+	if(NewState)
+	{
+		RCC->BDCTLR |= (1<<16);
+	}
+	else{
+		RCC->BDCTLR &= ~(1<<16);		
+	}		
+}
+
+/*********************************************************************
+ * @fn      RCC_ClockSecuritySystemCmd
+ *
+ * @brief   Enables or disables the Clock Security System.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+	if(NewState)
+	{
+		RCC->CTLR |= (1<<19);
+	}
+	else{
+		RCC->CTLR &= ~(1<<19);		
+	}		
+}
+
+/*********************************************************************
+ * @fn      RCC_MCOConfig
+ *
+ * @brief   Selects the clock source to output on MCO pin.
+ *
+ * @param   RCC_MCO - specifies the clock source to output.
+ *            RCC_MCO_NoClock - No clock selected.
+ *            RCC_MCO_SYSCLK - System clock selected.
+ *            RCC_MCO_HSI - HSI oscillator clock selected.
+ *            RCC_MCO_HSE - HSE oscillator clock selected.
+ *            RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected.
+ *            RCC_MCO_PLL2CLK - PLL2 clock selected
+ *            RCC_MCO_PLL3CLK_Div2 - PLL3 clock divided by 2 selected
+ *            RCC_MCO_XT1 - External 3-25 MHz oscillator clock selected
+ *            RCC_MCO_PLL3CLK - PLL3 clock selected
+ *
+ * @return  none
+ */
+void RCC_MCOConfig(uint8_t RCC_MCO)
+{
+  *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetFlagStatus
+ *
+ * @brief   Checks whether the specified RCC flag is set or not.
+ *
+ * @param   RCC_FLAG - specifies the flag to check.
+ *            RCC_FLAG_HSIRDY - HSI oscillator clock ready.
+ *            RCC_FLAG_HSERDY - HSE oscillator clock ready.
+ *            RCC_FLAG_PLLRDY - PLL clock ready.
+ *            RCC_FLAG_PLL2RDY - PLL2 clock ready.
+ *            RCC_FLAG_PLL3RDY - PLL3 clock ready.
+ *            RCC_FLAG_LSERDY - LSE oscillator clock ready.
+ *            RCC_FLAG_LSIRDY - LSI oscillator clock ready.
+ *            RCC_FLAG_PINRST - Pin reset.
+ *            RCC_FLAG_PORRST - POR/PDR reset.
+ *            RCC_FLAG_SFTRST - Software reset.
+ *            RCC_FLAG_IWDGRST - Independent Watchdog reset.
+ *            RCC_FLAG_WWDGRST - Window Watchdog reset.
+ *            RCC_FLAG_LPWRRST - Low Power reset.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+  uint32_t tmp = 0;
+  uint32_t statusreg = 0;
+	
+  FlagStatus bitstatus = RESET;
+  tmp = RCC_FLAG >> 5;
+	
+  if (tmp == 1)            
+  {
+    statusreg = RCC->CTLR;
+  }
+  else if (tmp == 2)       
+  {
+    statusreg = RCC->BDCTLR;
+  }
+  else                    
+  {
+    statusreg = RCC->RSTSCKR;
+  }
+
+  tmp = RCC_FLAG & FLAG_Mask;
+	
+  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RCC_ClearFlag
+ *
+ * @brief   Clears the RCC reset flags.
+ *
+ * @return  none
+ */
+void RCC_ClearFlag(void)
+{
+  RCC->RSTSCKR |= RSTSCKR_RMVF_Set;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetITStatus
+ *
+ * @brief   Checks whether the specified RCC interrupt has occurred or not.
+ *
+ * @param   RCC_IT - specifies the RCC interrupt source to check.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *            RCC_IT_PLL2RDY - PLL2 ready interrupt.
+ *            RCC_IT_PLL3RDY - PLL3 ready interrupt.
+ *            RCC_IT_CSS - Clock Security System interrupt.
+ *
+ * @return  ITStatus - SET or RESET.
+ */
+
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  if ((RCC->INTR & RCC_IT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+
+  return  bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RCC_ClearITPendingBit
+ *
+ * @brief   Clears the RCC's interrupt pending bits.
+ *
+ * @param   RCC_IT - specifies the interrupt pending bit to clear.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *            RCC_IT_PLL2RDY - PLL2 ready interrupt.
+ *            RCC_IT_PLL3RDY - PLL3 ready interrupt.
+ *            RCC_IT_CSS - Clock Security System interrupt.
+ *
+ * @return  none
+ */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+  *(__IO uint8_t *) INTR_BYTE3_ADDRESS = RCC_IT;
+}
+
+/*********************************************************************
+ * @fn      RCC_PREDIV1Config
+ *
+ * @brief   Configures the PREDIV1 division factor.
+ *
+ * @param   RCC_PREDIV1_Source - specifies the PREDIV1 clock source.
+ *            RCC_PREDIV1_Source_HSE - HSE selected as PREDIV1 clock
+ *            RCC_PREDIV1_Source_PLL2 - PLL2 selected as PREDIV1 clock
+ *          RCC_PREDIV1_Div - specifies the PREDIV1 clock division factor.
+ *            This parameter can be RCC_PREDIV1_Divx where x[1,16]
+ *
+ * @return  none
+ */
+void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR2;
+  tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
+  tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
+  RCC->CFGR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PREDIV2Config
+ *
+ * @brief   Configures the PREDIV2 division factor.
+ *
+ * @param   RCC_PREDIV2_Div - specifies the PREDIV2 clock division factor.
+ *            This parameter can be RCC_PREDIV2_Divx where x:[1,16]
+ *
+ * @return  none
+ */
+void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR2;
+  tmpreg &= ~CFGR2_PREDIV2;
+  tmpreg |= RCC_PREDIV2_Div;
+  RCC->CFGR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PLL2Config
+ *
+ * @brief   Configures the PLL2 multiplication factor.
+ *
+ * @param   RCC_PLL2Mul - specifies the PLL2 multiplication factor.
+ *            This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
+ *
+ * @return  none
+ */
+void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR2;
+  tmpreg &= ~CFGR2_PLL2MUL;
+  tmpreg |= RCC_PLL2Mul;
+  RCC->CFGR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PLL2Cmd
+ *
+ * @brief   Enables or disables the PLL2.
+ *
+ * @param   NewState - new state of the PLL2. This parameter can be
+ *        ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_PLL2Cmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->CTLR |= (1<<26);
+    }
+    else{
+        RCC->CTLR &= ~(1<<26);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_PLL3Config
+ *
+ * @brief   Configures the PLL3 multiplication factor.
+ *
+ * @param   RCC_PLL3Mul - specifies the PLL2 multiplication factor.
+ *            This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
+ *
+ * @return  none
+ */
+void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
+{
+  uint32_t tmpreg = 0;
+
+  tmpreg = RCC->CFGR2;
+  tmpreg &= ~CFGR2_PLL3MUL;
+  tmpreg |= RCC_PLL3Mul;
+  RCC->CFGR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PLL3Cmd
+ *
+ * @brief   Enables or disables the PLL3.
+ *
+ * @param   NewState - new state of the PLL2. This parameter can be
+ *        ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_PLL3Cmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->CTLR |= (1<<28);
+    }
+    else{
+        RCC->CTLR &= ~(1<<28);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_OTGFSCLKConfig
+ *
+ * @brief   Configures the USB OTG FS clock (OTGFSCLK).
+ *
+ * @param   RCC_OTGFSCLKSource - specifies the USB OTG FS clock source.
+ *            RCC_OTGFSCLKSource_PLLCLK_Div1 - PLL clock divided by 1
+ *        selected as USB OTG FS clock source
+ *            RCC_OTGFSCLKSource_PLLCLK_Div2 - PLL clock divided by 2
+ *        selected as USB OTG FS clock source
+ *            RCC_OTGFSCLKSource_PLLCLK_Div3 - PLL clock divided by 3
+ *        selected as USB OTG FS clock source
+ *
+ * @return  none
+ */
+void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
+{
+    RCC->CFGR0 &= ~(3<<22);
+    RCC->CFGR0 |= RCC_OTGFSCLKSource<<22;
+}
+
+/*********************************************************************
+ * @fn      RCC_I2S2CLKConfig
+ *
+ * @brief   Configures the I2S2 clock source(I2S2CLK).
+ *
+ * @param   RCC_I2S2CLKSource - specifies the I2S2 clock source.
+ *          RCC_I2S2CLKSource_SYSCLK - system clock selected as I2S2 clock entry
+ *          RCC_I2S2CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S2 clock entry
+ *
+ * @return  none
+ */
+void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
+{
+    RCC->CFGR2 &= ~(1<<17);
+    RCC->CFGR2 |= RCC_I2S2CLKSource<<17;
+}
+
+/*********************************************************************
+ * @fn      RCC_I2S3CLKConfig
+ *
+ * @brief   Configures the I2S3 clock source(I2S2CLK).
+ *
+ * @param   RCC_I2S3CLKSource - specifies the I2S3 clock source.
+ *            RCC_I2S3CLKSource_SYSCLK - system clock selected as I2S3 clock entry
+ *            RCC_I2S3CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S3 clock entry
+ *
+ * @return  none
+ */
+void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
+{
+    RCC->CFGR2 &= ~(1<<18);
+    RCC->CFGR2 |= RCC_I2S3CLKSource<<18;
+}
+
+/*********************************************************************
+ * @fn      RCC_AHBPeriphResetCmd
+ *
+ * @brief   Forces or releases AHB peripheral reset.
+ *
+ * @param   RCC_AHBPeriph - specifies the AHB peripheral to reset.
+ *            RCC_AHBPeriph_OTG_FS
+ *            RCC_AHBPeriph_ETH_MAC
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->AHBRSTR |= RCC_AHBPeriph;
+  }
+  else
+  {
+    RCC->AHBRSTR &= ~RCC_AHBPeriph;
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_ADCCLKADJcmd
+ *
+ * @brief   Enable ADC clock duty cycle adjustment.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_ADCCLKADJcmd(FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->CFGR0 |= (1<<31);
+  }
+  else
+  {
+    RCC->CFGR0 &= ~(1<<31);
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_RNGCLKConfig
+ *
+ * @brief   Configures the RNG clock source.
+ *
+ * @param   RCC_RNGCLKSource - specifies the RNG clock source.
+ *            RCC_RNGCLKSource_SYSCLK - system clock selected as RNG clock entry
+ *            RCC_RNGCLKSource_PLL3_VCO - PLL3 VCO clock selected as RNG clock entry
+ *
+ * @return  none
+ */
+void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource)
+{
+    RCC->CFGR2 &= ~(1<<19);
+    RCC->CFGR2 |= RCC_RNGCLKSource<<19;
+}
+
+/*********************************************************************
+ * @fn      RCC_ETH1GCLKConfig
+ *
+ * @brief   Configures the ETH1G clock source.
+ *
+ * @param   RCC_RNGCLKSource - specifies the ETH1G clock source.
+ *            RCC_ETH1GCLKSource_PLL2_VCO - system clock selected as ETH1G clock entry
+ *            RCC_ETH1GCLKSource_PLL3_VCO - PLL3 VCO clock selected as ETH1G clock entry
+ *            RCC_ETH1GCLKSource_PB1_IN -  GPIO PB1 input clock selected as ETH1G clock entry
+ *
+ * @return  none
+ */
+void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource)
+{
+    RCC->CFGR2 &= ~(3<<20);
+    RCC->CFGR2 |= RCC_ETH1GCLKSource<<20;
+}
+
+/*********************************************************************
+ * @fn      RCC_ETH1G_125Mcmd
+ *
+ * @brief   Enable ETH1G 125M.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_ETH1G_125Mcmd(FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->CFGR2 |= (1<<22);
+  }
+  else
+  {
+    RCC->CFGR2 &= ~(1<<22);
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_USBHSConfig
+ *
+ * @brief   Configures the USBHS clock.
+ *
+ * @param   RCC_USBHS - defines the USBHS clock divider.
+ *            RCC_USBPLL_Div1 - USBHS clock = USBPLL.
+ *            RCC_USBPLL_Div2 - USBHS clock = USBPLL/2.
+ *            RCC_USBPLL_Div3 - USBHS clock = USBPLL/3.
+ *            RCC_USBPLL_Div4 - USBHS clock = USBPLL/4.
+ *            RCC_USBPLL_Div5 - USBHS clock = USBPLL/5.
+ *            RCC_USBPLL_Div6 - USBHS clock = USBPLL/6.
+ *            RCC_USBPLL_Div7 - USBHS clock = USBPLL/7.
+ *            RCC_USBPLL_Div8 - USBHS clock = USBPLL/8.
+ *
+ * @return  none
+ */
+void RCC_USBHSConfig(uint32_t RCC_USBHS)
+{
+    RCC->CFGR2 &= ~(7<<24);
+    RCC->CFGR2 |= RCC_USBHS<<24;
+}
+
+/*********************************************************************
+ * @fn      RCC_USBHSPLLCLKConfig
+ *
+ * @brief   Configures the USBHSPLL clock source.
+ *
+ * @param   RCC_HSBHSPLLCLKSource - specifies the USBHSPLL clock source.
+ *            RCC_HSBHSPLLCLKSource_HSE - HSE clock selected as USBHSPLL clock entry
+ *            RCC_HSBHSPLLCLKSource_HSI - HSI clock selected as USBHSPLL clock entry
+ *
+ * @return  none
+ */
+void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource)
+{
+    RCC->CFGR2 &= ~(1<<27);
+    RCC->CFGR2 |= RCC_USBHSPLLCLKSource<<27;
+}
+
+/*********************************************************************
+ * @fn      RCC_USBHSPLLCKREFCLKConfig
+ *
+ * @brief   Configures the USBHSPLL reference clock.
+ *
+ * @param   RCC_USBHSPLLCKREFCLKSource - Select reference clock.
+ *            RCC_USBHSPLLCKREFCLK_3M - reference clock 3Mhz.
+ *            RCC_USBHSPLLCKREFCLK_4M - reference clock 4Mhz.
+ *            RCC_USBHSPLLCKREFCLK_8M - reference clock 8Mhz.
+ *            RCC_USBHSPLLCKREFCLK_5M - reference clock 5Mhz.
+ *
+ * @return  none
+ */
+void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource)
+{
+    RCC->CFGR2 &= ~(3<<28);
+    RCC->CFGR2 |= RCC_USBHSPLLCKREFCLKSource<<28;
+}
+
+/*********************************************************************
+ * @fn      RCC_USBHSPHYPLLALIVEcmd
+ *
+ * @brief   Enable USBHS PHY control.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    RCC->CFGR2 |= (1<<30);
+  }
+  else
+  {
+    RCC->CFGR2 &= ~(1<<30);
+  }
+}
+
+/*********************************************************************
+ * @fn      RCC_USBCLK48MConfig
+ *
+ * @brief   Configures the USB clock 48MHz source.
+ *
+ * @param   RCC_USBCLK48MSource - specifies the USB clock 48MHz source.
+ *            RCC_USBCLK48MCLKSource_PLLCLK - PLLCLK clock selected as USB clock 48MHz clock entry
+ *            RCC_USBCLK48MCLKSource_USBPHY - USBPHY clock selected as USB clock 48MHz clock entry
+ *
+ * @return  none
+ */
+void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource)
+{
+    RCC->CFGR2 &= ~(1<<31);
+    RCC->CFGR2 |= RCC_USBCLK48MSource<<31;
+}

demo/ch32/ch32v307/SRC/Peripheral/src/ch32v30x_usart.c

@@ -0,0 +1,821 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_usart.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file provides all the USART firmware functions.
+*******************************************************************************/ 
+#include "ch32v30x_usart.h"
+#include "ch32v30x_rcc.h"
+
+/* USART_Private_Defines */
+#define CTLR1_UE_Set                ((uint16_t)0x2000)  /* USART Enable Mask */
+#define CTLR1_UE_Reset              ((uint16_t)0xDFFF)  /* USART Disable Mask */
+
+#define CTLR1_WAKE_Mask             ((uint16_t)0xF7FF)  /* USART WakeUp Method Mask */
+
+#define CTLR1_RWU_Set               ((uint16_t)0x0002)  /* USART mute mode Enable Mask */
+#define CTLR1_RWU_Reset             ((uint16_t)0xFFFD)  /* USART mute mode Enable Mask */
+#define CTLR1_SBK_Set               ((uint16_t)0x0001)  /* USART Break Character send Mask */
+#define CTLR1_CLEAR_Mask            ((uint16_t)0xE9F3)  /* USART CR1 Mask */
+#define CTLR2_Address_Mask          ((uint16_t)0xFFF0)  /* USART address Mask */
+
+#define CTLR2_LINEN_Set             ((uint16_t)0x4000)  /* USART LIN Enable Mask */
+#define CTLR2_LINEN_Reset           ((uint16_t)0xBFFF)  /* USART LIN Disable Mask */
+
+#define CTLR2_LBDL_Mask             ((uint16_t)0xFFDF)  /* USART LIN Break detection Mask */
+#define CTLR2_STOP_CLEAR_Mask       ((uint16_t)0xCFFF)  /* USART CR2 STOP Bits Mask */
+#define CTLR2_CLOCK_CLEAR_Mask      ((uint16_t)0xF0FF)  /* USART CR2 Clock Mask */
+
+#define CTLR3_SCEN_Set              ((uint16_t)0x0020)  /* USART SC Enable Mask */
+#define CTLR3_SCEN_Reset            ((uint16_t)0xFFDF)  /* USART SC Disable Mask */
+
+#define CTLR3_NACK_Set              ((uint16_t)0x0010)  /* USART SC NACK Enable Mask */
+#define CTLR3_NACK_Reset            ((uint16_t)0xFFEF)  /* USART SC NACK Disable Mask */
+
+#define CTLR3_HDSEL_Set             ((uint16_t)0x0008)  /* USART Half-Duplex Enable Mask */
+#define CTLR3_HDSEL_Reset           ((uint16_t)0xFFF7)  /* USART Half-Duplex Disable Mask */
+
+#define CTLR3_IRLP_Mask             ((uint16_t)0xFFFB)  /* USART IrDA LowPower mode Mask */
+#define CTLR3_CLEAR_Mask            ((uint16_t)0xFCFF)  /* USART CR3 Mask */
+
+#define CTLR3_IREN_Set              ((uint16_t)0x0002)  /* USART IrDA Enable Mask */
+#define CTLR3_IREN_Reset            ((uint16_t)0xFFFD)  /* USART IrDA Disable Mask */
+#define GPR_LSB_Mask                ((uint16_t)0x00FF)  /* Guard Time Register LSB Mask */
+#define GPR_MSB_Mask                ((uint16_t)0xFF00)  /* Guard Time Register MSB Mask */
+#define IT_Mask                     ((uint16_t)0x001F)  /* USART Interrupt Mask */
+
+/* USART OverSampling-8 Mask */
+#define CTLR1_OVER8_Set             ((uint16_t)0x8000)  /* USART OVER8 mode Enable Mask */
+#define CTLR1_OVER8_Reset           ((uint16_t)0x7FFF)  /* USART OVER8 mode Disable Mask */
+
+/* USART One Bit Sampling Mask */
+#define CTLR3_ONEBITE_Set           ((uint16_t)0x0800)  /* USART ONEBITE mode Enable Mask */
+#define CTLR3_ONEBITE_Reset         ((uint16_t)0xF7FF)  /* USART ONEBITE mode Disable Mask */
+
+
+/*********************************************************************
+ * @fn      USART_DeInit
+ *
+ * @brief   Deinitializes the USARTx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
+ *
+ * @return  none
+ */
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+  if (USARTx == USART1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+  }
+  else if (USARTx == USART2)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+  }
+  else if (USARTx == USART3)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+  }    
+  else if (USARTx == UART4)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
+  }    
+  else
+  {
+    if (USARTx == UART5)
+    { 
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
+    }
+  }
+}
+
+/*********************************************************************
+ * @fn      USART_Init
+ *
+ * @brief   Initializes the USARTx peripheral according to the specified
+ *        parameters in the USART_InitStruct.
+ *
+ * @param   USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
+ *          USART_InitStruct - pointer to a USART_InitTypeDef structure
+ *        that contains the configuration information for the specified
+ *        USART peripheral.
+ *
+ * @return  none
+ */
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+  uint32_t tmpreg = 0x00, apbclock = 0x00;
+  uint32_t integerdivider = 0x00;
+  uint32_t fractionaldivider = 0x00;
+  uint32_t usartxbase = 0;
+  RCC_ClocksTypeDef RCC_ClocksStatus;
+
+  if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
+  {
+  }
+
+  usartxbase = (uint32_t)USARTx;
+  tmpreg = USARTx->CTLR2;
+  tmpreg &= CTLR2_STOP_CLEAR_Mask;
+  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;  
+	
+  USARTx->CTLR2 = (uint16_t)tmpreg;
+  tmpreg = USARTx->CTLR1;
+  tmpreg &= CTLR1_CLEAR_Mask;
+  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+            USART_InitStruct->USART_Mode;
+  USARTx->CTLR1 = (uint16_t)tmpreg;
+ 
+  tmpreg = USARTx->CTLR3;
+  tmpreg &= CTLR3_CLEAR_Mask;
+  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+  USARTx->CTLR3 = (uint16_t)tmpreg;
+
+  RCC_GetClocksFreq(&RCC_ClocksStatus);
+	
+  if (usartxbase == USART1_BASE)
+  {
+    apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+  }
+  else
+  {
+    apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+  }
+  
+  if ((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0)
+  {
+    integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));    
+  }
+  else 
+  {
+    integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));    
+  }
+  tmpreg = (integerdivider / 100) << 4;
+
+  fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
+
+  if ((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0)
+  {
+    tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
+  }
+  else 
+  {
+    tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+  }
+  
+  USARTx->BRR = (uint16_t)tmpreg;
+}
+
+/*********************************************************************
+ * @fn      USART_StructInit
+ *
+ * @brief   Fills each USART_InitStruct member with its default value.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  none
+ */
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+  USART_InitStruct->USART_BaudRate = 9600;
+  USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+  USART_InitStruct->USART_StopBits = USART_StopBits_1;
+  USART_InitStruct->USART_Parity = USART_Parity_No ;
+  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;  
+}
+
+/*********************************************************************
+ * @fn      USART_ClockInit
+ *
+ * @brief   Initializes the USARTx peripheral Clock according to the
+ *        specified parameters in the USART_ClockInitStruct .
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
+ *        structure that contains the configuration information for the specified
+ *        USART peripheral.
+ *
+ * @return  none
+ */
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  uint32_t tmpreg = 0x00;
+	
+  tmpreg = USARTx->CTLR2;
+  tmpreg &= CTLR2_CLOCK_CLEAR_Mask;
+  tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 
+                 USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
+  USARTx->CTLR2 = (uint16_t)tmpreg;
+}
+
+/*********************************************************************
+ * @fn      USART_ClockStructInit
+ *
+ * @brief   Fills each USART_ClockStructInit member with its default value.
+ *
+ * @param   USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
+ *        structure which will be initialized.
+ *
+ * @return  none
+ */
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+  USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+  USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+  USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/*********************************************************************
+ * @fn      USART_Cmd
+ *
+ * @brief   Enables or disables the specified USART peripheral.
+ *        reset values (Affects also the I2Ss).
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    USARTx->CTLR1 |= CTLR1_UE_Set;
+  }
+  else
+  {
+    USARTx->CTLR1 &= CTLR1_UE_Reset;
+  }
+}
+
+/*********************************************************************
+ * @fn      USART_ITConfig
+ *
+ * @brief   Enables or disables the specified USART interrupts.
+ *        reset values (Affects also the I2Ss).
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the USART interrupt sources to be enabled or disabled.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TXE - Transmit Data Register empty interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *            USART_IT_IDLE - Idle line detection interrupt.
+ *            USART_IT_PE - Parity Error interrupt.
+ *            USART_IT_ERR - Error interrupt.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
+{
+  uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+  uint32_t usartxbase = 0x00;
+
+  if (USART_IT == USART_IT_CTS)
+  {
+  }   
+  
+  usartxbase = (uint32_t)USARTx;
+  usartreg = (((uint8_t)USART_IT) >> 0x05);
+  itpos = USART_IT & IT_Mask;
+  itmask = (((uint32_t)0x01) << itpos);
+    
+  if (usartreg == 0x01) 
+  {
+    usartxbase += 0x0C;
+  }
+  else if (usartreg == 0x02) 
+  {
+    usartxbase += 0x10;
+  }
+  else 
+  {
+    usartxbase += 0x14; 
+  }
+	
+  if (NewState != DISABLE)
+  {
+    *(__IO uint32_t*)usartxbase  |= itmask;
+  }
+  else
+  {
+    *(__IO uint32_t*)usartxbase &= ~itmask;
+  }
+}
+
+/*********************************************************************
+ * @fn      USART_DMACmd
+ *
+ * @brief   Enables or disables the USART DMA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_DMAReq - specifies the DMA request.
+ *            USART_DMAReq_Tx - USART DMA transmit request.
+ *            USART_DMAReq_Rx - USART DMA receive request.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    USARTx->CTLR3 |= USART_DMAReq;
+  }
+  else
+  {
+    USARTx->CTLR3 &= (uint16_t)~USART_DMAReq;
+  }
+}
+
+/*********************************************************************
+ * @fn      USART_SetAddress
+ *
+ * @brief   Sets the address of the USART node.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_Address - Indicates the address of the USART node.
+ *
+ * @return  none
+ */
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
+{
+  USARTx->CTLR2 &= CTLR2_Address_Mask;
+  USARTx->CTLR2 |= USART_Address;
+}
+
+/*********************************************************************
+ * @fn      USART_WakeUpConfig
+ *
+ * @brief   Selects the USART WakeUp method.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_WakeUp - specifies the USART wakeup method.
+ *            USART_WakeUp_IdleLine - WakeUp by an idle line detection.
+ *            USART_WakeUp_AddressMark - WakeUp by an address mark.
+ *
+ * @return  none
+ */
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
+{
+  USARTx->CTLR1 &= CTLR1_WAKE_Mask;
+  USARTx->CTLR1 |= USART_WakeUp;
+}
+
+/*********************************************************************
+ * @fn      USART_ReceiverWakeUpCmd
+ *
+ * @brief   Determines if the USART is in mute mode or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    USARTx->CTLR1 |= CTLR1_RWU_Set;
+  }
+  else
+  {
+    USARTx->CTLR1 &= CTLR1_RWU_Reset;
+  }
+}
+
+/*********************************************************************
+ * @fn      USART_LINBreakDetectLengthConfig
+ *
+ * @brief   Sets the USART LIN Break detection length.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_LINBreakDetectLength - specifies the LIN break detection length.
+ *            USART_LINBreakDetectLength_10b - 10-bit break detection.
+ *            USART_LINBreakDetectLength_11b - 11-bit break detection.
+ *
+ * @return  none
+ */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+  USARTx->CTLR2 &= CTLR2_LBDL_Mask;
+  USARTx->CTLR2 |= USART_LINBreakDetectLength;  
+}
+
+/*********************************************************************
+ * @fn      USART_LINCmd
+ *
+ * @brief   Enables or disables the USART LIN mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    USARTx->CTLR2 |= CTLR2_LINEN_Set;
+  }
+  else
+  {
+    USARTx->CTLR2 &= CTLR2_LINEN_Reset;
+  }
+}
+
+/*********************************************************************
+ * @fn      USART_SendData
+ *
+ * @brief   Transmits single data through the USARTx peripheral.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          Data - the data to transmit.
+ *
+ * @return  none
+ */
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
+{
+  USARTx->DATAR = (Data & (uint16_t)0x01FF);
+}
+
+/*********************************************************************
+ * @fn      USART_ReceiveData
+ *
+ * @brief   Returns the most recent received data by the USARTx peripheral.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *
+ * @return  The received data.
+ */
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
+{
+  return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF);
+}
+
+/*********************************************************************
+ * @fn      USART_SendBreak
+ *
+ * @brief   Transmits break characters.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *
+ * @return  none
+ */
+void USART_SendBreak(USART_TypeDef* USARTx)
+{
+  USARTx->CTLR1 |= CTLR1_SBK_Set;
+}
+
+/*********************************************************************
+ * @fn      USART_SetGuardTime
+ *
+ * @brief   Sets the specified USART guard time.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_GuardTime - specifies the guard time.
+ *
+ * @return  none
+ */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
+{    
+  USARTx->GPR &= GPR_LSB_Mask;
+  USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/*********************************************************************
+ * @fn      USART_SetPrescaler
+ *
+ * @brief   Sets the system clock prescaler.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_Prescaler - specifies the prescaler clock.
+ *
+ * @return  none
+ */
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
+{ 
+  USARTx->GPR &= GPR_MSB_Mask;
+  USARTx->GPR |= USART_Prescaler;
+}
+
+/*********************************************************************
+ * @fn      USART_SmartCardCmd
+ *
+ * @brief   Enables or disables the USART Smart Card mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    USARTx->CTLR3 |= CTLR3_SCEN_Set;
+  }
+  else
+  {
+    USARTx->CTLR3 &= CTLR3_SCEN_Reset;
+  }
+}
+
+/*********************************************************************
+ * @fn      USART_SmartCardNACKCmd
+ *
+ * @brief   Enables or disables NACK transmission.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    USARTx->CTLR3 |= CTLR3_NACK_Set;
+  }
+  else
+  {
+    USARTx->CTLR3 &= CTLR3_NACK_Reset;
+  }
+}
+
+/*********************************************************************
+ * @fn      USART_HalfDuplexCmd
+ *
+ * @brief   Enables or disables the USART Half Duplex communication.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *                  NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    USARTx->CTLR3 |= CTLR3_HDSEL_Set;
+  }
+  else
+  {
+    USARTx->CTLR3 &= CTLR3_HDSEL_Reset;
+  }
+}
+
+/*********************************************************************
+ * @fn      USART_OverSampling8Cmd
+ *
+ * @brief   Enables or disables the USART's 8x oversampling mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    USARTx->CTLR1 |= CTLR1_OVER8_Set;
+  }
+  else
+  {
+    USARTx->CTLR1 &= CTLR1_OVER8_Reset;
+  }
+}
+
+/*********************************************************************
+ * @fn      USART_OneBitMethodCmd
+ *
+ * @brief   Enables or disables the USART's one bit sampling method.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+    USARTx->CTLR3 |= CTLR3_ONEBITE_Set;
+  }
+  else
+  {
+    USARTx->CTLR3 &= CTLR3_ONEBITE_Reset;
+  }
+}
+
+/*********************************************************************
+ * @fn      USART_IrDAConfig
+ *
+ * @brief   Configures the USART's IrDA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IrDAMode - specifies the IrDA mode.
+ *            USART_IrDAMode_LowPower.
+ *            USART_IrDAMode_Normal.
+ *
+ * @return  none
+ */
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
+{ 
+  USARTx->CTLR3 &= CTLR3_IRLP_Mask;
+  USARTx->CTLR3 |= USART_IrDAMode;
+}
+
+/*********************************************************************
+ * @fn      USART_IrDACmd
+ *
+ * @brief   Enables or disables the USART's IrDA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{ 
+  if (NewState != DISABLE)
+  {
+    USARTx->CTLR3 |= CTLR3_IREN_Set;
+  }
+  else
+  {
+    USARTx->CTLR3 &= CTLR3_IREN_Reset;
+  }
+}
+
+/*********************************************************************
+ * @fn      USART_GetFlagStatus
+ *
+ * @brief   Checks whether the specified USART flag is set or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_FLAG - specifies the flag to check.
+ *            USART_FLAG_CTS - CTS Change flag.
+ *            USART_FLAG_LBD - LIN Break detection flag.
+ *            USART_FLAG_TXE - Transmit data register empty flag.
+ *            USART_FLAG_TC - Transmission Complete flag.
+ *            USART_FLAG_RXNE - Receive data register not empty flag.
+ *            USART_FLAG_IDLE - Idle Line detection flag.
+ *            USART_FLAG_ORE - OverRun Error flag.
+ *            USART_FLAG_NE - Noise Error flag.
+ *            USART_FLAG_FE - Framing Error flag.
+ *            USART_FLAG_PE - Parity Error flag.
+ *
+ * @return  none
+ */
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+
+  if (USART_FLAG == USART_FLAG_CTS)
+  {
+  }  
+  
+  if ((USARTx->STATR & USART_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      USART_ClearFlag
+ *
+ * @brief   Clears the USARTx's pending flags.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_FLAG - specifies the flag to clear.
+ *            USART_FLAG_CTS - CTS Change flag.
+ *            USART_FLAG_LBD - LIN Break detection flag.
+ *            USART_FLAG_TC - Transmission Complete flag.
+ *            USART_FLAG_RXNE - Receive data register not empty flag.
+ *
+ * @return  none
+ */
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+  if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
+  {
+  } 
+   
+  USARTx->STATR = (uint16_t)~USART_FLAG;
+}
+
+/*********************************************************************
+ * @fn      USART_GetITStatus
+ *
+ * @brief   Checks whether the specified USART interrupt has occurred or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the USART interrupt source to check.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TXE - Tansmit Data Register empty interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *            USART_IT_IDLE - Idle line detection interrupt.
+ *            USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set.
+ *            USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set.
+ *            USART_IT_NE - Noise Error interrupt.
+ *            USART_IT_FE - Framing Error interrupt.
+ *            USART_IT_PE - Parity Error interrupt.
+ *
+ * @return  none
+ */
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+  uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+  ITStatus bitstatus = RESET;
+
+  if (USART_IT == USART_IT_CTS)
+  {
+  }   
+  
+  usartreg = (((uint8_t)USART_IT) >> 0x05);
+  itmask = USART_IT & IT_Mask;
+  itmask = (uint32_t)0x01 << itmask;
+  
+  if (usartreg == 0x01) 
+  {
+    itmask &= USARTx->CTLR1;
+  }
+  else if (usartreg == 0x02) 
+  {
+    itmask &= USARTx->CTLR2;
+  }
+  else 
+  {
+    itmask &= USARTx->CTLR3;
+  }
+  
+  bitpos = USART_IT >> 0x08;
+  bitpos = (uint32_t)0x01 << bitpos;
+  bitpos &= USARTx->STATR;
+	
+  if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  
+  return bitstatus;  
+}
+
+/*********************************************************************
+ * @fn      USART_ClearITPendingBit
+ *
+ * @brief   Clears the USARTx's interrupt pending bits.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the interrupt pending bit to clear.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *
+ * @return  none
+ */
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+  uint16_t bitpos = 0x00, itmask = 0x00;
+
+  if (USART_IT == USART_IT_CTS)
+  {
+  }   
+  
+  bitpos = USART_IT >> 0x08;
+  itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+  USARTx->STATR = (uint16_t)~itmask;
+}
+
+
+
+
+
+
+
+

demo/ch32/ch32v307/SRC/Startup/startup_ch32v30x.S

@@ -0,0 +1,385 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : startup_ch32v30x.s
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x vector table for eclipse toolchain.
+*******************************************************************************/
+
+	.section	.init,"ax",@progbits
+	.global	_start
+	.align	1
+_start:
+	j	handle_reset
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00100073
+    .section    .vector,"ax",@progbits
+    .align  1
+_vector_base:
+    .option norvc;
+    .word   _start
+    .word   0
+    .word   NMI_Handler                /* NMI */
+    .word   HardFault_Handler          /* Hard Fault */
+    .word   0
+    .word   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .word   0
+    .word   0
+    .word   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .word   Break_Point_Handler        /* Break Point */
+    .word   0
+    .word   0
+    .word   SysTick_Handler            /* SysTick */
+    .word   0
+    .word   SW_handler                 /* SW */
+    .word   0
+    /* External Interrupts */
+    .word   WWDG_IRQHandler            /* Window Watchdog */
+    .word   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .word   TAMPER_IRQHandler          /* TAMPER */
+    .word   RTC_IRQHandler             /* RTC */
+    .word   FLASH_IRQHandler           /* Flash */
+    .word   RCC_IRQHandler             /* RCC */
+    .word   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .word   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .word   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .word   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .word   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .word   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .word   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .word   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .word   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .word   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .word   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .word   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .word   ADC1_2_IRQHandler          /* ADC1_2 */
+    .word   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .word   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .word   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .word   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .word   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .word   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .word   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .word   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .word   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .word   TIM2_IRQHandler            /* TIM2 */
+    .word   TIM3_IRQHandler            /* TIM3 */
+    .word   TIM4_IRQHandler            /* TIM4 */
+    .word   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .word   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .word   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .word   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .word   SPI1_IRQHandler            /* SPI1 */
+    .word   SPI2_IRQHandler            /* SPI2 */
+    .word   USART1_IRQHandler          /* USART1 */
+    .word   USART2_IRQHandler          /* USART2 */
+    .word   USART3_IRQHandler          /* USART3 */
+    .word   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .word   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .word   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .word   TIM8_BRK_IRQHandler        /* TIM8 Break */
+    .word   TIM8_UP_IRQHandler         /* TIM8 Update */
+    .word   TIM8_TRG_COM_IRQHandler    /* TIM8 Trigger and Commutation */
+    .word   TIM8_CC_IRQHandler         /* TIM8 Capture Compare */
+    .word   RNG_IRQHandler             /* RNG */
+    .word   FSMC_IRQHandler            /* FSMC */
+    .word   SDIO_IRQHandler            /* SDIO */
+    .word   TIM5_IRQHandler            /* TIM5 */
+    .word   SPI3_IRQHandler            /* SPI3 */
+    .word   UART4_IRQHandler           /* UART4 */
+    .word   UART5_IRQHandler           /* UART5 */
+    .word   TIM6_IRQHandler            /* TIM6 */
+    .word   TIM7_IRQHandler            /* TIM7 */
+    .word   DMA2_Channel1_IRQHandler   /* DMA2 Channel 1 */
+    .word   DMA2_Channel2_IRQHandler   /* DMA2 Channel 2 */
+    .word   DMA2_Channel3_IRQHandler   /* DMA2 Channel 3 */
+    .word   DMA2_Channel4_IRQHandler   /* DMA2 Channel 4 */
+    .word   DMA2_Channel5_IRQHandler   /* DMA2 Channel 5 */
+    .word   ETH_IRQHandler             /* ETH */
+    .word   ETH_WKUP_IRQHandler        /* ETH WakeUp */
+    .word   CAN2_TX_IRQHandler         /* CAN2 TX */
+    .word   CAN2_RX0_IRQHandler        /* CAN2 RX0 */
+    .word   CAN2_RX1_IRQHandler        /* CAN2 RX1 */
+    .word   CAN2_SCE_IRQHandler        /* CAN2 SCE */
+    .word   OTG_FS_IRQHandler          /* OTGFS */
+    .word   USBHSWakeup_IRQHandler     /* USBHS Wakeup */
+    .word   USBHS_IRQHandler           /* USBHS */
+    .word   DVP_IRQHandler             /* DVP */
+    .word   UART6_IRQHandler           /* UART6 */
+    .word   UART7_IRQHandler           /* UART7 */
+    .word   UART8_IRQHandler           /* UART8 */
+    .word   TIM9_BRK_IRQHandler        /* TIM9 Break */
+    .word   TIM9_UP_IRQHandler         /* TIM9 Update */
+    .word   TIM9_TRG_COM_IRQHandler    /* TIM9 Trigger and Commutation */
+    .word   TIM9_CC_IRQHandler         /* TIM9 Capture Compare */
+    .word   TIM10_BRK_IRQHandler       /* TIM10 Break */
+    .word   TIM10_UP_IRQHandler        /* TIM10 Update */
+    .word   TIM10_TRG_COM_IRQHandler   /* TIM10 Trigger and Commutation */
+    .word   TIM10_CC_IRQHandler        /* TIM10 Capture Compare */
+    .word   DMA2_Channel6_IRQHandler   /* DMA2 Channel 6 */
+    .word   DMA2_Channel7_IRQHandler   /* DMA2 Channel 7 */
+    .word   DMA2_Channel8_IRQHandler   /* DMA2 Channel 8 */
+    .word   DMA2_Channel9_IRQHandler   /* DMA2 Channel 9 */
+    .word   DMA2_Channel10_IRQHandler  /* DMA2 Channel 10 */
+    .word   DMA2_Channel11_IRQHandler  /* DMA2 Channel 11 */
+
+    .option rvc;
+
+    .section    .text.vector_handler, "ax", @progbits
+    .weak   NMI_Handler                /* NMI */
+    .weak   HardFault_Handler          /* Hard Fault */
+    .weak   Ecall_M_Mode_Handler       /* Ecall M Mode */
+    .weak   Ecall_U_Mode_Handler       /* Ecall U Mode */
+    .weak   Break_Point_Handler        /* Break Point */
+    .weak   SysTick_Handler            /* SysTick */
+    .weak   SW_handler                 /* SW */
+    .weak   WWDG_IRQHandler            /* Window Watchdog */
+    .weak   PVD_IRQHandler             /* PVD through EXTI Line detect */
+    .weak   TAMPER_IRQHandler          /* TAMPER */
+    .weak   RTC_IRQHandler             /* RTC */
+    .weak   FLASH_IRQHandler           /* Flash */
+    .weak   RCC_IRQHandler             /* RCC */
+    .weak   EXTI0_IRQHandler           /* EXTI Line 0 */
+    .weak   EXTI1_IRQHandler           /* EXTI Line 1 */
+    .weak   EXTI2_IRQHandler           /* EXTI Line 2 */
+    .weak   EXTI3_IRQHandler           /* EXTI Line 3 */
+    .weak   EXTI4_IRQHandler           /* EXTI Line 4 */
+    .weak   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+    .weak   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+    .weak   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+    .weak   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+    .weak   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+    .weak   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+    .weak   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+    .weak   ADC1_2_IRQHandler          /* ADC1_2 */
+    .weak   USB_HP_CAN1_TX_IRQHandler  /* USB HP and CAN1 TX */
+    .weak   USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
+    .weak   CAN1_RX1_IRQHandler        /* CAN1 RX1 */
+    .weak   CAN1_SCE_IRQHandler        /* CAN1 SCE */
+    .weak   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+    .weak   TIM1_BRK_IRQHandler        /* TIM1 Break */
+    .weak   TIM1_UP_IRQHandler         /* TIM1 Update */
+    .weak   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+    .weak   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+    .weak   TIM2_IRQHandler            /* TIM2 */
+    .weak   TIM3_IRQHandler            /* TIM3 */
+    .weak   TIM4_IRQHandler            /* TIM4 */
+    .weak   I2C1_EV_IRQHandler         /* I2C1 Event */
+    .weak   I2C1_ER_IRQHandler         /* I2C1 Error */
+    .weak   I2C2_EV_IRQHandler         /* I2C2 Event */
+    .weak   I2C2_ER_IRQHandler         /* I2C2 Error */
+    .weak   SPI1_IRQHandler            /* SPI1 */
+    .weak   SPI2_IRQHandler            /* SPI2 */
+    .weak   USART1_IRQHandler          /* USART1 */
+    .weak   USART2_IRQHandler          /* USART2 */
+    .weak   USART3_IRQHandler          /* USART3 */
+    .weak   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+    .weak   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+    .weak   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+    .weak   TIM8_BRK_IRQHandler        /* TIM8 Break */
+    .weak   TIM8_UP_IRQHandler         /* TIM8 Update */
+    .weak   TIM8_TRG_COM_IRQHandler    /* TIM8 Trigger and Commutation */
+    .weak   TIM8_CC_IRQHandler         /* TIM8 Capture Compare */
+    .weak   RNG_IRQHandler             /* RNG */
+    .weak   FSMC_IRQHandler            /* FSMC */
+    .weak   SDIO_IRQHandler            /* SDIO */
+    .weak   TIM5_IRQHandler            /* TIM5 */
+    .weak   SPI3_IRQHandler            /* SPI3 */
+    .weak   UART4_IRQHandler           /* UART4 */
+    .weak   UART5_IRQHandler           /* UART5 */
+    .weak   TIM6_IRQHandler            /* TIM6 */
+    .weak   TIM7_IRQHandler            /* TIM7 */
+    .weak   DMA2_Channel1_IRQHandler   /* DMA2 Channel 1 */
+    .weak   DMA2_Channel2_IRQHandler   /* DMA2 Channel 2 */
+    .weak   DMA2_Channel3_IRQHandler   /* DMA2 Channel 3 */
+    .weak   DMA2_Channel4_IRQHandler   /* DMA2 Channel 4 */
+    .weak   DMA2_Channel5_IRQHandler   /* DMA2 Channel 5 */
+    .weak   ETH_IRQHandler             /* ETH */
+    .weak   ETH_WKUP_IRQHandler        /* ETH WakeUp */
+    .weak   CAN2_TX_IRQHandler         /* CAN2 TX */
+    .weak   CAN2_RX0_IRQHandler        /* CAN2 RX0 */
+    .weak   CAN2_RX1_IRQHandler        /* CAN2 RX1 */
+    .weak   CAN2_SCE_IRQHandler        /* CAN2 SCE */
+    .weak   OTG_FS_IRQHandler          /* OTGFS */
+    .weak   USBHSWakeup_IRQHandler     /* USBHS Wakeup */
+    .weak   USBHS_IRQHandler           /* USBHS */
+    .weak   DVP_IRQHandler             /* DVP */
+    .weak   UART6_IRQHandler           /* UART6 */
+    .weak   UART7_IRQHandler           /* UART7 */
+    .weak   UART8_IRQHandler           /* UART8 */
+    .weak   TIM9_BRK_IRQHandler        /* TIM9 Break */
+    .weak   TIM9_UP_IRQHandler         /* TIM9 Update */
+    .weak   TIM9_TRG_COM_IRQHandler    /* TIM9 Trigger and Commutation */
+    .weak   TIM9_CC_IRQHandler         /* TIM9 Capture Compare */
+    .weak   TIM10_BRK_IRQHandler       /* TIM10 Break */
+    .weak   TIM10_UP_IRQHandler        /* TIM10 Update */
+    .weak   TIM10_TRG_COM_IRQHandler   /* TIM10 Trigger and Commutation */
+    .weak   TIM10_CC_IRQHandler        /* TIM10 Capture Compare */
+    .weak   DMA2_Channel6_IRQHandler   /* DMA2 Channel 6 */
+    .weak   DMA2_Channel7_IRQHandler   /* DMA2 Channel 7 */
+    .weak   DMA2_Channel8_IRQHandler   /* DMA2 Channel 8 */
+    .weak   DMA2_Channel9_IRQHandler   /* DMA2 Channel 9 */
+    .weak   DMA2_Channel10_IRQHandler  /* DMA2 Channel 10 */
+    .weak   DMA2_Channel11_IRQHandler  /* DMA2 Channel 11 */
+
+NMI_Handler:  1:  j 1b
+HardFault_Handler:  1:  j 1b
+Ecall_M_Mode_Handler:  1:  j 1b
+Ecall_U_Mode_Handler:  1:  j 1b
+Break_Point_Handler:  1:  j 1b
+SysTick_Handler:  1:  j 1b
+SW_handler:  1:  j 1b
+WWDG_IRQHandler:  1:  j 1b
+PVD_IRQHandler:  1:  j 1b
+TAMPER_IRQHandler:  1:  j 1b
+RTC_IRQHandler:  1:  j 1b
+FLASH_IRQHandler:  1:  j 1b
+RCC_IRQHandler:  1:  j 1b
+EXTI0_IRQHandler:  1:  j 1b
+EXTI1_IRQHandler:  1:  j 1b
+EXTI2_IRQHandler:  1:  j 1b
+EXTI3_IRQHandler:  1:  j 1b
+EXTI4_IRQHandler:  1:  j 1b
+DMA1_Channel1_IRQHandler:  1:  j 1b
+DMA1_Channel2_IRQHandler:  1:  j 1b
+DMA1_Channel3_IRQHandler:  1:  j 1b
+DMA1_Channel4_IRQHandler:  1:  j 1b
+DMA1_Channel5_IRQHandler:  1:  j 1b
+DMA1_Channel6_IRQHandler:  1:  j 1b
+DMA1_Channel7_IRQHandler:  1:  j 1b
+ADC1_2_IRQHandler:  1:  j 1b
+USB_HP_CAN1_TX_IRQHandler:  1:  j 1b
+USB_LP_CAN1_RX0_IRQHandler:  1:  j 1b
+CAN1_RX1_IRQHandler:  1:  j 1b
+CAN1_SCE_IRQHandler:  1:  j 1b
+EXTI9_5_IRQHandler:  1:  j 1b
+TIM1_BRK_IRQHandler:  1:  j 1b
+TIM1_UP_IRQHandler:  1:  j 1b
+TIM1_TRG_COM_IRQHandler:  1:  j 1b
+TIM1_CC_IRQHandler:  1:  j 1b
+TIM2_IRQHandler:  1:  j 1b
+TIM3_IRQHandler:  1:  j 1b
+TIM4_IRQHandler:  1:  j 1b
+I2C1_EV_IRQHandler:  1:  j 1b
+I2C1_ER_IRQHandler:  1:  j 1b
+I2C2_EV_IRQHandler:  1:  j 1b
+I2C2_ER_IRQHandler:  1:  j 1b
+SPI1_IRQHandler:  1:  j 1b
+SPI2_IRQHandler:  1:  j 1b
+USART1_IRQHandler:  1:  j 1b
+USART2_IRQHandler:  1:  j 1b
+USART3_IRQHandler:  1:  j 1b
+EXTI15_10_IRQHandler:  1:  j 1b
+RTCAlarm_IRQHandler:  1:  j 1b
+USBWakeUp_IRQHandler:  1:  j 1b
+TIM8_BRK_IRQHandler:  1:  j 1b
+TIM8_UP_IRQHandler:  1:  j 1b
+TIM8_TRG_COM_IRQHandler:  1:  j 1b
+TIM8_CC_IRQHandler:  1:  j 1b
+RNG_IRQHandler:  1:  j 1b
+FSMC_IRQHandler:  1:  j 1b
+SDIO_IRQHandler:  1:  j 1b
+TIM5_IRQHandler:  1:  j 1b
+SPI3_IRQHandler:  1:  j 1b
+UART4_IRQHandler:  1:  j 1b
+UART5_IRQHandler:  1:  j 1b
+TIM6_IRQHandler:  1:  j 1b
+TIM7_IRQHandler:  1:  j 1b
+DMA2_Channel1_IRQHandler:  1:  j 1b
+DMA2_Channel2_IRQHandler:  1:  j 1b
+DMA2_Channel3_IRQHandler:  1:  j 1b
+DMA2_Channel4_IRQHandler:  1:  j 1b
+DMA2_Channel5_IRQHandler:  1:  j 1b
+ETH_IRQHandler:  1:  j 1b
+ETH_WKUP_IRQHandler:  1:  j 1b
+CAN2_TX_IRQHandler:  1:  j 1b
+CAN2_RX0_IRQHandler:  1:  j 1b
+CAN2_RX1_IRQHandler:  1:  j 1b
+CAN2_SCE_IRQHandler:  1:  j 1b
+OTG_FS_IRQHandler:  1:  j 1b
+USBHSWakeup_IRQHandler:  1:  j 1b
+USBHS_IRQHandler:  1:  j 1b
+DVP_IRQHandler:  1:  j 1b
+UART6_IRQHandler:  1:  j 1b
+UART7_IRQHandler:  1:  j 1b
+UART8_IRQHandler:  1:  j 1b
+TIM9_BRK_IRQHandler:  1:  j 1b
+TIM9_UP_IRQHandler:  1:  j 1b
+TIM9_TRG_COM_IRQHandler:  1:  j 1b
+TIM9_CC_IRQHandler:  1:  j 1b
+TIM10_BRK_IRQHandler:  1:  j 1b
+TIM10_UP_IRQHandler:  1:  j 1b
+TIM10_TRG_COM_IRQHandler:  1:  j 1b
+TIM10_CC_IRQHandler:  1:  j 1b
+DMA2_Channel6_IRQHandler:  1:  j 1b
+DMA2_Channel7_IRQHandler:  1:  j 1b
+DMA2_Channel8_IRQHandler:  1:  j 1b
+DMA2_Channel9_IRQHandler:  1:  j 1b
+DMA2_Channel10_IRQHandler:  1:  j 1b
+DMA2_Channel11_IRQHandler:  1:  j 1b
+
+
+	.section	.text.handle_reset,"ax",@progbits
+	.weak	handle_reset
+	.align	1
+handle_reset:
+.option push 
+.option	norelax 
+	la gp, __global_pointer$
+.option	pop 
+1:
+	la sp, _eusrstack 
+2:
+	/* Load data section from flash to RAM */
+	la a0, _data_lma
+	la a1, _data_vma
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+	/* Clear bss section */
+	la a0, _sbss
+	la a1, _ebss
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+    li t0, 0x1f
+    csrw 0xbc0, t0
+
+    /* Enable nested and hardware stack */
+	li t0, 0x1f
+	csrw 0x804, t0
+
+    /* Enable floating point and interrupt */
+   	li t0, 0x6088           
+   	csrs mstatus, t0
+
+ 	la t0, _vector_base
+    ori t0, t0, 3           
+	csrw mtvec, t0
+
+    jal  SystemInit
+	la t0, main
+	csrw mepc, t0
+	mret
+
+

demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/.cproject

@@ -0,0 +1,155 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" moduleId="org.eclipse.cdt.core.settings" name="obj">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="${cross_rm} -rf" description="" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release">
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+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Startup}&quot;"/>
+								</option>
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+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Peripheral/inc}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/usb_stack/core}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/usb_stack/common}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/usb_stack/class/cdc}&quot;"/>
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+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections.1689063433" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections" value="true" valueType="boolean"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.paths.1029177148" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.paths" valueType="libPaths">
+									<listOptionValue builtIn="false" value="&quot;../LD&quot;"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.scriptfile.1751226764" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.scriptfile" valueType="stringList">
+									<listOptionValue builtIn="false" value="Link.ld"/>
+								</option>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart.642896175" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostart" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnano.1540675679" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.usenewlibnano" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver.1292785366" name="GNU RISC-V Cross Archiver" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.archiver"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.1801165667" name="GNU RISC-V Cross Create Flash Image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash"/>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting.1356766765" name="GNU RISC-V Cross Create Listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source.2052761852" name="Display source (--source|-S)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders.439659821" name="Display all headers (--all-headers|-x)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle.67111865" name="Demangle names (--demangle|-C)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers.1549373929" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide.1298918921" name="Wide lines (--wide|-w)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.wide" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.disassemble.1859590835" name="Disassemble (--disassemble|-d)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.disassemble" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+							</tool>
+							<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.712424314" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize">
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1404031980" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format" useByScannerDiscovery="false"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+					<sourceEntries>
+						<entry excluding="usb_stack/LICENSE|usb_stack/README_zh.md|usb_stack/README.md|usb_stack/SConscript|usb_stack/class/hub|usb_stack/demo|usb_stack/docs|usb_stack/packet capture|usb_stack/port/fsdev|usb_stack/port/mm32|usb_stack/port/stm32|usb_stack/port/synopsys|usb_stack/port/template|usb_stack/port/bouffalolab|Startup|Peripheral|Ld|Debug|Core" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Core"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Debug"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Ld"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Peripheral"/>
+						<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Startup"/>
+					</sourceEntries>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+			<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="999.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.275846018" name="Executable file" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+	<storageModule moduleId="refreshScope" versionNumber="2">
+		<configuration configurationName="obj">
+			<resource resourceType="PROJECT" workspacePath="/ADC_DMA"/>
+		</configuration>
+		<configuration configurationName="Debug">
+			<resource resourceType="PROJECT" workspacePath="/000"/>
+		</configuration>
+		<configuration configurationName="Release">
+			<resource resourceType="PROJECT" workspacePath="/000"/>
+		</configuration>
+	</storageModule>
+</cproject>

demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/.project

@@ -0,0 +1,79 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>usb_stack_cdc_acm</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Core</name>
+			<type>2</type>
+			<locationURI>PARENT-4-PROJECT_LOC/SRC/Core</locationURI>
+		</link>
+		<link>
+			<name>Debug</name>
+			<type>2</type>
+			<locationURI>PARENT-4-PROJECT_LOC/SRC/Debug</locationURI>
+		</link>
+		<link>
+			<name>Ld</name>
+			<type>2</type>
+			<locationURI>PARENT-4-PROJECT_LOC/SRC/Ld</locationURI>
+		</link>
+		<link>
+			<name>Peripheral</name>
+			<type>2</type>
+			<locationURI>PARENT-4-PROJECT_LOC/SRC/Peripheral</locationURI>
+		</link>
+		<link>
+			<name>Startup</name>
+			<type>2</type>
+			<locationURI>PARENT-4-PROJECT_LOC/SRC/Startup</locationURI>
+		</link>
+		<link>
+			<name>USB_Stack</name>
+			<type>2</type>
+			<locationURI>PARENT-7-PROJECT_LOC</locationURI>
+		</link>
+		<link>
+			<name>User</name>
+			<type>2</type>
+			<locationURI>PROJECT_LOC/User</locationURI>
+		</link>
+		<link>
+			<name>usb_stack</name>
+			<type>2</type>
+			<location>C:/Users/lvjiazhen/Desktop/usb_stack</location>
+		</link>
+	</linkedResources>
+	<filteredResources>
+		<filter>
+			<id>1595986042669</id>
+			<name></name>
+			<type>22</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-*.wvproj</arguments>
+			</matcher>
+		</filter>
+	</filteredResources>
+</projectDescription>

demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/.settings/language.settings.xml

@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<project>
+	<configuration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj">
+		<extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
+			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
+			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
+			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
+			<provider class="org.eclipse.cdt.managedbuilder.language.settings.providers.GCCBuiltinSpecsDetector" console="false" env-hash="-47956671669104902" id="ilg.gnumcueclipse.managedbuild.cross.riscv.GCCBuiltinSpecsDetector" keep-relative-paths="false" name="CDT RISC-V Cross GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} ${cross_toolchain_flags} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+				<language-scope id="org.eclipse.cdt.core.gcc"/>
+				<language-scope id="org.eclipse.cdt.core.g++"/>
+			</provider>
+		</extension>
+	</configuration>
+</project>

demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/.settings/org.eclipse.core.resources.prefs

@@ -0,0 +1,2 @@
+eclipse.preferences.version=1
+encoding//usb_stack/port/ch32/usb_dc.c=UTF-8

demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/.template

@@ -0,0 +1,13 @@
+
+Vendor=WCH
+Link=WCH-Link
+Toolchain=
+Series=
+Description=
+Mcu Type=CH32V30x
+Address=0x08000000
+Erase All=true
+Program=true
+Verify=true
+Reset=true
+Target Path=obj/usb_stack_cdc_acm.hex

demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/USB_Stack_CDC_ACM.wvproj

@@ -0,0 +1,2 @@
+�i“CZ	?"Ç�¸rŸ�
F<Fy8E9Y‡½„%Pa³D¶La†%Ã'y€¡]Ç;’¶ŸS)1†1+R4><‚.„ÇÅ¿º°?/£XO©Ä¿ChQN$*¢”»E
ÅBk‹!
2tŒ+buh†nUb]xl‹l|
++"Ÿ<“¯AH42}z8p;m€u1Ž-¦eh»Od¼Âwµª7x{5�CqEx©=;¦¢e¢º»2£Š	‚«*BPMš"

demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/User/ch32v30x_conf.h

@@ -0,0 +1,23 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_conf.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : Library configuration file.
+*******************************************************************************/ 
+#ifndef __CH32V30x_CONF_H
+#define __CH32V30x_CONF_H
+
+#include "ch32v30x_gpio.h"
+#include "ch32v30x_rcc.h"
+#include "ch32v30x_usart.h"
+#include "ch32v30x_it.h"
+#include "ch32v30x_misc.h"
+
+
+#endif /* __CH32V30x_CONF_H */
+
+
+	
+	
+	

demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/User/ch32v30x_it.c

@@ -0,0 +1,38 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_it.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : Main Interrupt Service Routines.
+*******************************************************************************/
+#include "ch32v30x_it.h"
+
+void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
+
+/*********************************************************************
+ * @fn      NMI_Handler
+ *
+ * @brief   This function handles NMI exception.
+ *
+ * @return  none
+ */
+void NMI_Handler(void)
+{
+}
+
+/*********************************************************************
+ * @fn      HardFault_Handler
+ *
+ * @brief   This function handles Hard Fault exception.
+ *
+ * @return  none
+ */
+void HardFault_Handler(void)
+{
+  while (1)
+  {
+  }
+}
+
+

demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/User/ch32v30x_it.h

@@ -0,0 +1,16 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : ch32v30x_it.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : This file contains the headers of the interrupt handlers.
+*******************************************************************************/
+#ifndef __CH32V30x_IT_H
+#define __CH32V30x_IT_H
+
+#include "debug.h"
+
+
+#endif /* __CH32V30x_IT_H */
+
+

demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/User/main.c

@@ -0,0 +1,203 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : main.c
+* Author             : sakumisu
+* Version            : V1.0.0
+* Date               : 2022/01/02
+* Description        : cdc acm test.
+*******************************************************************************/
+
+/*
+ *@Note
+*/
+#include "debug.h"
+#include "usbd_core.h"
+#include "usbd_cdc.h"
+
+/*!< endpoint address */
+#define CDC_IN_EP  0x81
+#define CDC_OUT_EP 0x02
+#define CDC_INT_EP 0x83
+
+#define USBD_VID           0xFFFF
+#define USBD_PID           0xFFFF
+#define USBD_MAX_POWER     100
+#define USBD_LANGID_STRING 1033
+
+/*!< config descriptor size */
+#define USB_CONFIG_SIZE (9 + CDC_ACM_DESCRIPTOR_LEN)
+
+/*!< global descriptor */
+static const uint8_t cdc_descriptor[] = {
+    USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x02, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01),
+    USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER),
+    CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, 0x02),
+    ///////////////////////////////////////
+    /// string0 descriptor
+    ///////////////////////////////////////
+    USB_LANGID_INIT(USBD_LANGID_STRING),
+    ///////////////////////////////////////
+    /// string1 descriptor
+    ///////////////////////////////////////
+    0x12,                       /* bLength */
+    USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */
+    'B', 0x00,                  /* wcChar0 */
+    'o', 0x00,                  /* wcChar1 */
+    'u', 0x00,                  /* wcChar2 */
+    'f', 0x00,                  /* wcChar3 */
+    'f', 0x00,                  /* wcChar4 */
+    'a', 0x00,                  /* wcChar5 */
+    'l', 0x00,                  /* wcChar6 */
+    'o', 0x00,                  /* wcChar7 */
+    ///////////////////////////////////////
+    /// string2 descriptor
+    ///////////////////////////////////////
+    0x24,                       /* bLength */
+    USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */
+    'B', 0x00,                  /* wcChar0 */
+    'o', 0x00,                  /* wcChar1 */
+    'u', 0x00,                  /* wcChar2 */
+    'f', 0x00,                  /* wcChar3 */
+    'f', 0x00,                  /* wcChar4 */
+    'a', 0x00,                  /* wcChar5 */
+    'l', 0x00,                  /* wcChar6 */
+    'o', 0x00,                  /* wcChar7 */
+    ' ', 0x00,                  /* wcChar8 */
+    'C', 0x00,                  /* wcChar9 */
+    'D', 0x00,                  /* wcChar10 */
+    'C', 0x00,                  /* wcChar11 */
+    ' ', 0x00,                  /* wcChar13 */
+    'D', 0x00,                  /* wcChar14 */
+    'E', 0x00,                  /* wcChar15 */
+    'M', 0x00,                  /* wcChar16 */
+    'O', 0x00,                  /* wcChar17 */
+    ///////////////////////////////////////
+    /// string3 descriptor
+    ///////////////////////////////////////
+    0x16,                       /* bLength */
+    USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */
+    '2', 0x00,                  /* wcChar0 */
+    '0', 0x00,                  /* wcChar1 */
+    '2', 0x00,                  /* wcChar2 */
+    '1', 0x00,                  /* wcChar3 */
+    '0', 0x00,                  /* wcChar4 */
+    '3', 0x00,                  /* wcChar5 */
+    '1', 0x00,                  /* wcChar6 */
+    '0', 0x00,                  /* wcChar7 */
+    '0', 0x00,                  /* wcChar8 */
+    '0', 0x00,                  /* wcChar9 */
+#ifdef CONFIG_USB_HS
+    ///////////////////////////////////////
+    /// device qualifier descriptor
+    ///////////////////////////////////////
+    0x0a,
+    USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER,
+    0x00,
+    0x02,
+    0x02,
+    0x02,
+    0x01,
+    0x40,
+    0x01,
+    0x00,
+#endif
+    0x00
+};
+/*!< class */
+usbd_class_t cdc_class;
+/*!< interface one */
+usbd_interface_t cdc_cmd_intf;
+/*!< interface two */
+usbd_interface_t cdc_data_intf;
+
+/* function ------------------------------------------------------------------*/
+void usbd_cdc_acm_out(uint8_t ep)
+{
+    uint8_t data[64];
+    uint32_t read_byte;
+    usbd_ep_read(ep, data, 64, &read_byte);
+
+    printf("read len:%d\r\n", read_byte);
+    usbd_ep_read(ep, NULL, 0, NULL);
+}
+
+void usbd_cdc_acm_in(uint8_t ep)
+{
+    printf("in\r\n");
+}
+
+/*!< endpoint call back */
+usbd_endpoint_t cdc_out_ep = {
+    .ep_addr = CDC_OUT_EP,
+    .ep_cb = usbd_cdc_acm_out
+};
+
+usbd_endpoint_t cdc_in_ep = {
+    .ep_addr = CDC_IN_EP,
+    .ep_cb = usbd_cdc_acm_in
+};
+
+/* function ------------------------------------------------------------------*/
+void cdc_init(void)
+{
+    usbd_desc_register(cdc_descriptor);
+    /*!< add interface */
+    usbd_cdc_add_acm_interface(&cdc_class, &cdc_cmd_intf);
+    usbd_cdc_add_acm_interface(&cdc_class, &cdc_data_intf);
+    /*!< interface add endpoint */
+    usbd_interface_add_endpoint(&cdc_data_intf, &cdc_out_ep);
+    usbd_interface_add_endpoint(&cdc_data_intf, &cdc_in_ep);
+}
+
+void usb_dc_low_level_init(void)
+{
+    RCC_USBCLK48MConfig(RCC_USBCLK48MCLKSource_USBPHY);
+    RCC_USBHSPLLCLKConfig(RCC_HSBHSPLLCLKSource_HSE);
+    RCC_USBHSConfig(RCC_USBPLL_Div2);
+    RCC_USBHSPLLCKREFCLKConfig(RCC_USBHSPLLCKREFCLK_4M);
+    RCC_USBHSPHYPLLALIVEcmd(ENABLE);
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHS, ENABLE);
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_OTG_FS, ENABLE);
+
+    Delay_Us(100);
+
+    EXTEN->EXTEN_CTR |= EXTEN_USBD_PU_EN;
+
+    GPIO_InitTypeDef GPIO_InitTypdefStruct = { 0 };
+
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
+    GPIO_InitTypdefStruct.GPIO_Pin = GPIO_Pin_15;
+    GPIO_InitTypdefStruct.GPIO_Mode = GPIO_Mode_IPU;
+    GPIO_InitTypdefStruct.GPIO_Speed = GPIO_Speed_50MHz;
+
+    GPIO_Init(GPIOB, &GPIO_InitTypdefStruct);
+
+    NVIC_EnableIRQ(OTG_FS_IRQn);
+}
+
+/*********************************************************************
+ * @fn      main
+ *
+ * @brief   Main program.
+ *
+ * @return  none
+ */
+int main(void)
+{
+    Delay_Init();
+    USART_Printf_Init(115200);
+    printf("SystemClk:%d\r\n", SystemCoreClock);
+
+    Delay_Ms(10);
+
+    cdc_init();
+    extern int usb_dc_init(void);
+    usb_dc_init();
+
+    while (!usb_device_is_configured()) {
+    }
+    while (1) {
+        uint8_t data_buffer[10] = { 0x31, 0x32, 0x33, 0x34, 0x35, 0x31, 0x32, 0x33, 0x34, 0x35 };
+        usbd_ep_write(0x81, data_buffer, 10, NULL);
+        Delay_Ms(500);
+    }
+}

demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/User/system_ch32v30x.c

@@ -0,0 +1,769 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32v30x.c
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x Device Peripheral Access Layer System Source File.
+*                      For HSE = 8Mhz
+*********************************************************************************/
+#include "ch32v30x.h" 
+
+/* 
+* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after 
+* reset the HSI is used as SYSCLK source).
+* If none of the define below is enabled, the HSI is used as System clock source. 
+*/
+// #define SYSCLK_FREQ_HSE    HSE_VALUE
+/* #define SYSCLK_FREQ_24MHz  24000000  */ 
+//#define SYSCLK_FREQ_48MHz  48000000
+/* #define SYSCLK_FREQ_56MHz  56000000  */  
+#define SYSCLK_FREQ_72MHz  72000000
+//#define SYSCLK_FREQ_96MHz  96000000
+//#define SYSCLK_FREQ_120MHz  120000000
+//#define SYSCLK_FREQ_144MHz  144000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_HSE;          /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_24MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_48MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_56MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_72MHz;        /* System Clock Frequency (Core Clock) */
+
+#elif defined SYSCLK_FREQ_96MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_96MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_120MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_120MHz;        /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_144MHz
+  uint32_t SystemCoreClock         = SYSCLK_FREQ_144MHz;        /* System Clock Frequency (Core Clock) */
+
+#else /* HSI Selected as System Clock source */
+  uint32_t SystemCoreClock         = HSI_VALUE;                /* System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+
+/* system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+  static void SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+  static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_48MHz
+  static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+  static void SetSysClockTo56(void);  
+#elif defined SYSCLK_FREQ_72MHz
+  static void SetSysClockTo72(void);
+
+#elif defined SYSCLK_FREQ_96MHz
+  static void SetSysClockTo96(void);
+#elif defined SYSCLK_FREQ_120MHz
+  static void SetSysClockTo120(void);
+#elif defined SYSCLK_FREQ_144MHz
+  static void SetSysClockTo144(void);
+
+#endif
+
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit (void)
+{
+  RCC->CTLR |= (uint32_t)0x00000001;
+  RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+  RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+  RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+  RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+  RCC->INTR = 0x009F0000;    
+  SetSysClock();
+}
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate (void)
+{
+  uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
+
+  tmp = RCC->CFGR0 & RCC_SWS;
+  
+  switch (tmp)
+  {
+    case 0x00:
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08: 
+      pllmull = RCC->CFGR0 & RCC_PLLMULL;
+      pllsource = RCC->CFGR0 & RCC_PLLSRC; 
+      pllmull = ( pllmull >> 18) + 2;
+
+      if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){ /* for other CH32V30x */
+          if(pllmull == 17) pllmull = 18;
+      }
+      else{  /* for CH32V307 */
+          if(pllmull == 2) pllmull = 18;
+          if(pllmull == 15){
+              pllmull = 13;  /* *6.5 */
+              Pll_6_5 = 1;
+          }
+          if(pllmull == 16) pllmull = 15;
+          if(pllmull == 17) pllmull = 16;
+      }
+
+      if (pllsource == 0x00)
+      {
+        SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+      }
+      else
+      {    
+        if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+        {
+          SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+        }
+        else
+        {
+          SystemCoreClock = HSE_VALUE * pllmull;
+        }
+      }
+
+      if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
+
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+ 
+  tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+  SystemCoreClock >>= tmp;  
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+  SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+  SetSysClockTo24();
+#elif defined SYSCLK_FREQ_48MHz
+  SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+  SetSysClockTo56();  
+#elif defined SYSCLK_FREQ_72MHz
+  SetSysClockTo72();
+#elif defined SYSCLK_FREQ_96MHz
+  SetSysClockTo96();
+#elif defined SYSCLK_FREQ_120MHz
+  SetSysClockTo120();
+#elif defined SYSCLK_FREQ_144MHz
+  SetSysClockTo144();
+
+#endif
+ 
+ /* If none of the define above is enabled, the HSI is used as System clock
+  * source (default after reset) 
+    */
+}
+
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;      
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+    
+    /* Select HSE as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;    
+
+    /* Wait till HSE is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+    {
+    }
+  }
+  else
+  { 
+        /* If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  }  
+}
+
+#elif defined SYSCLK_FREQ_24MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo24
+ *
+ * @brief   Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo24(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+    if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3);
+    }
+    else{
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3_EXTEN);
+    }
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+        /* If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_48MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo48
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+   
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;    
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;  
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+    if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
+    }
+    else{
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN);
+    }
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo56
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;   
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+  
+    /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+
+    if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
+    }
+    else{
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN);
+    }
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  } 
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo72
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+     
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;  
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }  
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; 
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; 
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+ 
+    /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
+    }
+    else{
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN);
+    }
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }    
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;    
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { 
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error 
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_96MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo96
+ *
+ * @brief   Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo96(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 12 = 96 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
+    }
+    else{
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN);
+    }
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_120MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo120
+ *
+ * @brief   Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo120(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 15 = 120 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
+    }
+    else{
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN);
+    }
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#elif defined SYSCLK_FREQ_144MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo144
+ *
+ * @brief   Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo144(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CTLR & RCC_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CTLR & RCC_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+    /* PCLK2 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+    /* PCLK1 = HCLK */
+    RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 18 = 144 MHz */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                        RCC_PLLMULL));
+
+    if(((*(uint32_t*)0x1FFFF70C) & (1<<14)) != (1<<14)){
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
+    }
+    else{
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN);
+    }
+
+    /* Enable PLL */
+    RCC->CTLR |= RCC_PLLON;
+    /* Wait till PLL is ready */
+    while((RCC->CTLR & RCC_PLLRDY) == 0)
+    {
+    }
+    /* Select PLL as system clock source */
+    RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+    RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+     * configuration. User can add here some code to deal with this error
+         */
+  }
+}
+
+
+#endif

demo/ch32/ch32v307/USB/USBFS/DEVICE/cdc_acm/User/system_ch32v30x.h

@@ -0,0 +1,28 @@
+/********************************** (C) COPYRIGHT *******************************
+* File Name          : system_ch32v30x.h
+* Author             : WCH
+* Version            : V1.0.0
+* Date               : 2021/06/06
+* Description        : CH32V30x Device Peripheral Access Layer System Header File.
+*******************************************************************************/
+#ifndef __SYSTEM_CH32V30x_H 
+#define __SYSTEM_CH32V30x_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+extern uint32_t SystemCoreClock;          /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V30x_SYSTEM_H */
+
+
+

port/ch32/README.md

@@ -2,7 +2,7 @@
 
 ## Support Chip List
 
-- CH32F10x、CH32V10x
+- all of CH chips with usb HD ip are supported, like CH57x、CH58x、CH32Vxxx、CH32Fxxx
 
 ## Before Use
 

port/ch32/usb_ch32_regs.h

@@ -0,0 +1,520 @@
+#ifndef _USB_CH32_REGS_H
+#define _USB_CH32_REGS_H
+
+#define     __IO    volatile                  /* defines 'read / write' permissions */
+
+/* USBHS Registers */
+typedef struct
+{
+  __IO uint8_t  CONTROL;
+  __IO uint8_t  HOST_CTRL;
+  __IO uint8_t  INT_EN;
+  __IO uint8_t  DEV_AD;
+  __IO uint16_t FRAME_NO;
+  __IO uint8_t  SUSPEND;
+  __IO uint8_t  RESERVED0;
+  __IO uint8_t  SPEED_TYPE;
+  __IO uint8_t  MIS_ST;
+  __IO uint8_t  INT_FG;
+  __IO uint8_t  INT_ST;
+  __IO uint16_t RX_LEN;
+  __IO uint16_t RESERVED1;
+  __IO uint32_t ENDP_CONFIG;
+  __IO uint32_t ENDP_TYPE;
+  __IO uint32_t BUF_MODE;
+  __IO uint32_t UEP0_DMA;
+  __IO uint32_t UEP1_RX_DMA;
+  __IO uint32_t UEP2_RX_DMA;
+  __IO uint32_t UEP3_RX_DMA;
+  __IO uint32_t UEP4_RX_DMA;
+  __IO uint32_t UEP5_RX_DMA;
+  __IO uint32_t UEP6_RX_DMA;
+  __IO uint32_t UEP7_RX_DMA;
+  __IO uint32_t UEP8_RX_DMA;
+  __IO uint32_t UEP9_RX_DMA;
+  __IO uint32_t UEP10_RX_DMA;
+  __IO uint32_t UEP11_RX_DMA;
+  __IO uint32_t UEP12_RX_DMA;
+  __IO uint32_t UEP13_RX_DMA;
+  __IO uint32_t UEP14_RX_DMA;
+  __IO uint32_t UEP15_RX_DMA;
+  __IO uint32_t UEP1_TX_DMA;
+  __IO uint32_t UEP2_TX_DMA;
+  __IO uint32_t UEP3_TX_DMA;
+  __IO uint32_t UEP4_TX_DMA;
+  __IO uint32_t UEP5_TX_DMA;
+  __IO uint32_t UEP6_TX_DMA;
+  __IO uint32_t UEP7_TX_DMA;
+  __IO uint32_t UEP8_TX_DMA;
+  __IO uint32_t UEP9_TX_DMA;
+  __IO uint32_t UEP10_TX_DMA;
+  __IO uint32_t UEP11_TX_DMA;
+  __IO uint32_t UEP12_TX_DMA;
+  __IO uint32_t UEP13_TX_DMA;
+  __IO uint32_t UEP14_TX_DMA;
+  __IO uint32_t UEP15_TX_DMA;
+  __IO uint16_t UEP0_MAX_LEN;
+  __IO uint16_t RESERVED2;
+  __IO uint16_t UEP1_MAX_LEN;
+  __IO uint16_t RESERVED3;
+  __IO uint16_t UEP2_MAX_LEN;
+  __IO uint16_t RESERVED4;
+  __IO uint16_t UEP3_MAX_LEN;
+  __IO uint16_t RESERVED5;
+  __IO uint16_t UEP4_MAX_LEN;
+  __IO uint16_t RESERVED6;
+  __IO uint16_t UEP5_MAX_LEN;
+  __IO uint16_t RESERVED7;
+  __IO uint16_t UEP6_MAX_LEN;
+  __IO uint16_t RESERVED8;
+  __IO uint16_t UEP7_MAX_LEN;
+  __IO uint16_t RESERVED9;
+  __IO uint16_t UEP8_MAX_LEN;
+  __IO uint16_t RESERVED10;
+  __IO uint16_t UEP9_MAX_LEN;
+  __IO uint16_t RESERVED11;
+  __IO uint16_t UEP10_MAX_LEN;
+  __IO uint16_t RESERVED12;
+  __IO uint16_t UEP11_MAX_LEN;
+  __IO uint16_t RESERVED13;
+  __IO uint16_t UEP12_MAX_LEN;
+  __IO uint16_t RESERVED14;
+  __IO uint16_t UEP13_MAX_LEN;
+  __IO uint16_t RESERVED15;
+  __IO uint16_t UEP14_MAX_LEN;
+  __IO uint16_t RESERVED16;
+  __IO uint16_t UEP15_MAX_LEN;
+  __IO uint16_t RESERVED17;
+  __IO uint16_t UEP0_TX_LEN;
+  __IO uint8_t  UEP0_TX_CTRL;
+  __IO uint8_t  UEP0_RX_CTRL;
+  __IO uint16_t UEP1_TX_LEN;
+  __IO uint8_t  UEP1_TX_CTRL;
+  __IO uint8_t  UEP1_RX_CTRL;
+  __IO uint16_t UEP2_TX_LEN;
+  __IO uint8_t  UEP2_TX_CTRL;
+  __IO uint8_t  UEP2_RX_CTRL;
+  __IO uint16_t UEP3_TX_LEN;
+  __IO uint8_t  UEP3_TX_CTRL;
+  __IO uint8_t  UEP3_RX_CTRL;
+  __IO uint16_t UEP4_TX_LEN;
+  __IO uint8_t  UEP4_TX_CTRL;
+  __IO uint8_t  UEP4_RX_CTRL;
+  __IO uint16_t UEP5_TX_LEN;
+  __IO uint8_t  UEP5_TX_CTRL;
+  __IO uint8_t  UEP5_RX_CTRL;
+  __IO uint16_t UEP6_TX_LEN;
+  __IO uint8_t  UEP6_TX_CTRL;
+  __IO uint8_t  UEP6_RX_CTRL;
+  __IO uint16_t UEP7_TX_LEN;
+  __IO uint8_t  UEP7_TX_CTRL;
+  __IO uint8_t  UEP7_RX_CTRL;
+  __IO uint16_t UEP8_TX_LEN;
+  __IO uint8_t  UEP8_TX_CTRL;
+  __IO uint8_t  UEP8_RX_CTRL;
+  __IO uint16_t UEP9_TX_LEN;
+  __IO uint8_t  UEP9_TX_CTRL;
+  __IO uint8_t  UEP9_RX_CTRL;
+  __IO uint16_t UEP10_TX_LEN;
+  __IO uint8_t  UEP10_TX_CTRL;
+  __IO uint8_t  UEP10_RX_CTRL;
+  __IO uint16_t UEP11_TX_LEN;
+  __IO uint8_t  UEP11_TX_CTRL;
+  __IO uint8_t  UEP11_RX_CTRL;
+  __IO uint16_t UEP12_TX_LEN;
+  __IO uint8_t  UEP12_TX_CTRL;
+  __IO uint8_t  UEP12_RX_CTRL;
+  __IO uint16_t UEP13_TX_LEN;
+  __IO uint8_t  UEP13_TX_CTRL;
+  __IO uint8_t  UEP13_RX_CTRL;
+  __IO uint16_t UEP14_TX_LEN;
+  __IO uint8_t  UEP14_TX_CTRL;
+  __IO uint8_t  UEP14_RX_CTRL;
+  __IO uint16_t UEP15_TX_LEN;
+  __IO uint8_t  UEP15_TX_CTRL;
+  __IO uint8_t  UEP15_RX_CTRL;
+} USBHSD_TypeDef;
+
+typedef struct  __attribute__((packed))
+{
+    __IO uint8_t  CONTROL;
+    __IO uint8_t  HOST_CTRL;
+    __IO uint8_t  INT_EN;
+    __IO uint8_t  DEV_AD;
+    __IO uint16_t FRAME_NO;
+    __IO uint8_t  SUSPEND;
+    __IO uint8_t  RESERVED0;
+    __IO uint8_t  SPEED_TYPE;
+    __IO uint8_t  MIS_ST;
+    __IO uint8_t  INT_FG;
+    __IO uint8_t  INT_ST;
+    __IO uint16_t RX_LEN;
+    __IO uint16_t RESERVED1;
+    __IO uint32_t HOST_EP_CONFIG;
+    __IO uint32_t HOST_EP_TYPE;
+    __IO uint32_t RESERVED2;
+    __IO uint32_t RESERVED3;
+    __IO uint32_t RESERVED4;
+    __IO uint32_t HOST_RX_DMA;
+    __IO uint32_t RESERVED5;
+    __IO uint32_t RESERVED6;
+    __IO uint32_t RESERVED7;
+    __IO uint32_t RESERVED8;
+    __IO uint32_t RESERVED9;
+    __IO uint32_t RESERVED10;
+    __IO uint32_t RESERVED11;
+    __IO uint32_t RESERVED12;
+    __IO uint32_t RESERVED13;
+    __IO uint32_t RESERVED14;
+    __IO uint32_t RESERVED15;
+    __IO uint32_t RESERVED16;
+    __IO uint32_t RESERVED17;
+    __IO uint32_t RESERVED18;
+    __IO uint32_t RESERVED19;
+    __IO uint32_t HOST_TX_DMA;
+    __IO uint32_t RESERVED20;
+    __IO uint32_t RESERVED21;
+    __IO uint32_t RESERVED22;
+    __IO uint32_t RESERVED23;
+    __IO uint32_t RESERVED24;
+    __IO uint32_t RESERVED25;
+    __IO uint32_t RESERVED26;
+    __IO uint32_t RESERVED27;
+    __IO uint32_t RESERVED28;
+    __IO uint32_t RESERVED29;
+    __IO uint32_t RESERVED30;
+    __IO uint32_t RESERVED31;
+    __IO uint32_t RESERVED32;
+    __IO uint32_t RESERVED33;
+    __IO uint16_t HOST_RX_MAX_LEN;
+    __IO uint16_t RESERVED34;
+    __IO uint32_t RESERVED35;
+    __IO uint32_t RESERVED36;
+    __IO uint32_t RESERVED37;
+    __IO uint32_t RESERVED38;
+    __IO uint32_t RESERVED39;
+    __IO uint32_t RESERVED40;
+    __IO uint32_t RESERVED41;
+    __IO uint32_t RESERVED42;
+    __IO uint32_t RESERVED43;
+    __IO uint32_t RESERVED44;
+    __IO uint32_t RESERVED45;
+    __IO uint32_t RESERVED46;
+    __IO uint32_t RESERVED47;
+    __IO uint32_t RESERVED48;
+    __IO uint32_t RESERVED49;
+    __IO uint8_t  HOST_EP_PID;
+    __IO uint8_t  RESERVED50;
+    __IO uint8_t  RESERVED51;
+    __IO uint8_t  HOST_RX_CTRL;
+    __IO uint16_t HOST_TX_LEN;
+    __IO uint8_t  HOST_TX_CTRL;
+    __IO uint8_t  RESERVED52;
+    __IO uint16_t HOST_SPLIT_DATA;
+} USBHSH_TypeDef;
+
+
+/* USBOTG_FS Registers */
+typedef struct
+{
+   __IO uint8_t  BASE_CTRL;
+   __IO uint8_t  UDEV_CTRL;
+   __IO uint8_t  INT_EN;
+   __IO uint8_t  DEV_ADDR;
+   __IO uint8_t  Reserve0;
+   __IO uint8_t  MIS_ST;
+   __IO uint8_t  INT_FG;
+   __IO uint8_t  INT_ST;
+   __IO uint16_t RX_LEN;
+   __IO uint16_t Reserve1;
+   __IO uint8_t  UEP4_1_MOD;
+   __IO uint8_t  UEP2_3_MOD;
+   __IO uint8_t  UEP5_6_MOD;
+   __IO uint8_t  UEP7_MOD;
+   __IO uint32_t UEP0_DMA;
+   __IO uint32_t UEP1_DMA;
+   __IO uint32_t UEP2_DMA;
+   __IO uint32_t UEP3_DMA;
+   __IO uint32_t UEP4_DMA;
+   __IO uint32_t UEP5_DMA;
+   __IO uint32_t UEP6_DMA;
+   __IO uint32_t UEP7_DMA;
+   __IO uint16_t UEP0_TX_LEN;
+   __IO uint8_t  UEP0_TX_CTRL;
+   __IO uint8_t  UEP0_RX_CTRL;
+   __IO uint16_t UEP1_TX_LEN;
+   __IO uint8_t  UEP1_TX_CTRL;
+   __IO uint8_t  UEP1_RX_CTRL;
+   __IO uint16_t UEP2_TX_LEN;
+   __IO uint8_t  UEP2_TX_CTRL;
+   __IO uint8_t  UEP2_RX_CTRL;
+   __IO uint16_t UEP3_TX_LEN;
+   __IO uint8_t  UEP3_TX_CTRL;
+   __IO uint8_t  UEP3_RX_CTRL;
+   __IO uint16_t UEP4_TX_LEN;
+   __IO uint8_t  UEP4_TX_CTRL;
+   __IO uint8_t  UEP4_RX_CTRL;
+   __IO uint16_t UEP5_TX_LEN;
+   __IO uint8_t  UEP5_TX_CTRL;
+   __IO uint8_t  UEP5_RX_CTRL;
+   __IO uint16_t UEP6_TX_LEN;
+   __IO uint8_t  UEP6_TX_CTRL;
+   __IO uint8_t  UEP6_RX_CTRL;
+   __IO uint16_t UEP7_TX_LEN;
+   __IO uint8_t  UEP7_TX_CTRL;
+   __IO uint8_t  UEP7_RX_CTRL;
+   __IO uint32_t Reserve2;
+   __IO uint32_t OTG_CR;
+   __IO uint32_t OTG_SR;
+}USBOTG_FS_TypeDef;
+
+typedef struct  __attribute__((packed))
+{
+   __IO uint8_t   BASE_CTRL;
+   __IO uint8_t   HOST_CTRL;
+   __IO uint8_t   INT_EN;
+   __IO uint8_t   DEV_ADDR;
+   __IO uint8_t   Reserve0;
+   __IO uint8_t   MIS_ST;
+   __IO uint8_t   INT_FG;
+   __IO uint8_t   INT_ST;
+   __IO uint16_t  RX_LEN;
+   __IO uint16_t  Reserve1;
+   __IO uint8_t   Reserve2;
+   __IO uint8_t   HOST_EP_MOD;
+   __IO uint16_t  Reserve3;
+   __IO uint32_t  Reserve4;
+   __IO uint32_t  Reserve5;
+   __IO uint32_t  HOST_RX_DMA;
+   __IO uint32_t  HOST_TX_DMA;
+   __IO uint32_t  Reserve6;
+   __IO uint32_t  Reserve7;
+   __IO uint32_t  Reserve8;
+   __IO uint32_t  Reserve9;
+   __IO uint32_t  Reserve10;
+   __IO uint16_t  Reserve11;
+   __IO uint16_t  HOST_SETUP;
+   __IO uint8_t   HOST_EP_PID;
+   __IO uint8_t   Reserve12;
+   __IO uint8_t   Reserve13;
+   __IO uint8_t   HOST_RX_CTRL;
+   __IO uint16_t  HOST_TX_LEN;
+   __IO uint8_t   HOST_TX_CTRL;
+   __IO uint8_t   Reserve14;
+   __IO uint32_t  Reserve15;
+   __IO uint32_t  Reserve16;
+   __IO uint32_t  Reserve17;
+   __IO uint32_t  Reserve18;
+   __IO uint32_t  Reserve19;
+   __IO uint32_t  OTG_CR;
+   __IO uint32_t  OTG_SR;
+}USBOTGH_FS_TypeDef;
+
+#define USBFS_BASE            ((uint32_t)0x50000000)
+#define USBHS_BASE            (((uint32_t))(0x40000000+0x23400))
+
+#define USBHSD              ((USBHSD_TypeDef *) USBHS_BASE)
+#define USBHSH              ((USBHSH_TypeDef *) USBHS_BASE)
+#define USBOTG_FS           ((USBOTG_FS_TypeDef *)USBFS_BASE)
+#define USBOTG_H_FS         ((USBOTGH_FS_TypeDef *)USBFS_BASE)
+
+/******************************************************************************/
+/* USBOTG_FS DEVICE USB_CONTROL */
+/* BASE USB_CTRL */
+#define   USBHD_BASE_CTRL       (USBOTG_FS->BASE_CTRL)  // USB base control
+#define     USBHD_UC_HOST_MODE     0x80      // enable USB host mode: 0=device mode, 1=host mode
+#define     USBHD_UC_LOW_SPEED     0x40      // enable USB low speed: 0=12Mbps, 1=1.5Mbps
+#define     USBHD_UC_DEV_PU_EN     0x20      // USB device enable and internal pullup resistance enable
+#define     USBHD_UC_SYS_CTRL1     0x20      // USB system control high bit
+#define     USBHD_UC_SYS_CTRL0     0x10      // USB system control low bit
+#define     USBHD_UC_SYS_CTRL_MASK 0x30      // bit mask of USB system control
+// UC_HOST_MODE & UC_SYS_CTRL1 & UC_SYS_CTRL0: USB system control
+//   0 00: disable USB device and disable internal pullup resistance
+//   0 01: enable USB device and disable internal pullup resistance, need external pullup resistance
+//   0 1x: enable USB device and enable internal pullup resistance
+//   1 00: enable USB host and normal status
+//   1 01: enable USB host and force UDP/UDM output SE0 state
+//   1 10: enable USB host and force UDP/UDM output J state
+//   1 11: enable USB host and force UDP/UDM output resume or K state
+#define     USBHD_UC_INT_BUSY      0x08      // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid
+#define     USBHD_UC_RESET_SIE     0x04      // force reset USB SIE, need software clear
+#define     USBHD_UC_CLR_ALL       0x02      // force clear FIFO and count of USB
+#define     USBHD_UC_DMA_EN        0x01      // DMA enable and DMA interrupt enable for USB
+/* DEVICE USB_CTRL */
+#define   USBHD_UDEV_CTRL        (USBOTG_FS->UDEV_CTRL)  // USB device physical prot control
+#define     USBHD_UD_PD_DIS        0x80      // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
+#define     USBHD_UD_DP_PIN        0x20      // ReadOnly: indicate current UDP pin level
+#define     USBHD_UD_DM_PIN        0x10      // ReadOnly: indicate current UDM pin level
+#define     USBHD_UD_LOW_SPEED     0x04      // enable USB physical port low speed: 0=full speed, 1=low speed
+#define     USBHD_UD_GP_BIT        0x02      // general purpose bit
+#define     USBHD_UD_PORT_EN       0x01      // enable USB physical port I/O: 0=disable, 1=enable
+/* USB INT EN */
+#define   USBHD_INT_EN           (USBOTG_FS->INT_EN)    // USB interrupt enable
+#define     USBHD_UIE_DEV_SOF      0x80      // enable interrupt for SOF received for USB device mode
+#define     USBHD_UIE_DEV_NAK      0x40      // enable interrupt for NAK responded for USB device mode
+#define     USBHD_UIE_FIFO_OV      0x10      // enable interrupt for FIFO overflow
+#define     USBHD_UIE_HST_SOF      0x08      // enable interrupt for host SOF timer action for USB host mode
+#define     USBHD_UIE_SUSPEND      0x04      // enable interrupt for USB suspend or resume event
+#define     USBHD_UIE_TRANSFER     0x02      // enable interrupt for USB transfer completion
+#define     USBHD_UIE_DETECT       0x01      // enable interrupt for USB device detected event for USB host mode
+#define     USBHD_UIE_BUS_RST      0x01      // enable interrupt for USB bus reset event for USB device mode
+/* USB_DEV_ADDR */
+#define   USBHD_DEV_ADDR         (USBOTG_FS->DEV_ADDR)   // USB device address
+#define     USBHD_UDA_GP_BIT       0x80      // general purpose bit
+#define     USBHD_USB_ADDR_MASK    0x7F      // bit mask for USB device address
+/* USBOTG_FS DEVICE USB_STATUS */
+/* USB_MIS_ST */
+#define   USBHD_MIS_ST           (USBOTG_FS->MIS_ST)     // USB miscellaneous status
+#define     USBHD_UMS_SOF_PRES     0x80      // RO, indicate host SOF timer presage status
+#define     USBHD_UMS_SOF_ACT      0x40      // RO, indicate host SOF timer action status for USB host
+#define     USBHD_UMS_SIE_FREE     0x20      // RO, indicate USB SIE free status
+#define     USBHD_UMS_R_FIFO_RDY   0x10      // RO, indicate USB receiving FIFO ready status (not empty)
+#define     USBHD_UMS_BUS_RESET    0x08      // RO, indicate USB bus reset status
+#define     USBHD_UMS_SUSPEND      0x04      // RO, indicate USB suspend status
+#define     USBHD_UMS_DM_LEVEL     0x02      // RO, indicate UDM level saved at device attached to USB host
+#define     USBHD_UMS_DEV_ATTACH   0x01      // RO, indicate device attached status on USB host
+/* USB_INT_FG */
+#define   USBHD_INT_FG           (USBOTG_FS->INT_FG)    // USB interrupt flag
+#define     USBHD_U_IS_NAK         0x80    // RO, indicate current USB transfer is NAK received
+#define     USBHD_U_TOG_OK         0x40    // RO, indicate current USB transfer toggle is OK
+#define     USBHD_U_SIE_FREE       0x20    // RO, indicate USB SIE free status
+#define     USBHD_UIF_FIFO_OV      0x10    // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
+#define     USBHD_UIF_HST_SOF      0x08    // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
+#define     USBHD_UIF_SUSPEND      0x04    // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
+#define     USBHD_UIF_TRANSFER     0x02    // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
+#define     USBHD_UIF_DETECT       0x01    // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
+#define     USBHD_UIF_BUS_RST      0x01    // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
+/* USB_INT_ST */
+#define   USBHD_INT_ST           (USBOTG_FS->INT_ST)    // USB interrupt flag
+#define     USBHD_UIS_IS_SETUP     0x80      // RO, indicate current USB transfer is setup received for USB device mode
+#define     USBHD_UIS_IS_NAK       0x80      // RO, indicate current USB transfer is NAK received for USB device mode
+#define     USBHD_UIS_TOG_OK       0x40      // RO, indicate current USB transfer toggle is OK
+#define     USBHD_UIS_TOKEN1       0x20      // RO, current token PID code bit 1 received for USB device mode
+#define     USBHD_UIS_TOKEN0       0x10      // RO, current token PID code bit 0 received for USB device mode
+#define     USBHD_UIS_TOKEN_MASK   0x30      // RO, bit mask of current token PID code received for USB device mode
+#define     USBHD_UIS_TOKEN_OUT    0x00
+#define     USBHD_UIS_TOKEN_SOF    0x10
+#define     USBHD_UIS_TOKEN_IN     0x20
+#define     USBHD_UIS_TOKEN_SETUP  0x30
+// UIS_TOKEN1 & UIS_TOKEN0: current token PID code received for USB device mode
+//   00: OUT token PID received
+//   01: SOF token PID received
+//   10: IN token PID received
+//   11: SETUP token PID received
+#define     USBHD_UIS_ENDP_MASK    0x0F      // RO, bit mask of current transfer endpoint number for USB device mode
+/* USB_RX_LEN */
+#define   USBHD_RX_LEN        (USBOTG_FS->Rx_Len)      // USB receiving length
+/* USB_BUF_MOD */
+#define   USBHD_UEP4_1_MOD    (USBOTG_FS->UEP4_1_MOD)  // endpoint 4/1 mode
+#define     USBHD_UEP1_RX_EN       0x80      // enable USB endpoint 1 receiving (OUT)
+#define     USBHD_UEP1_TX_EN       0x40      // enable USB endpoint 1 transmittal (IN)
+#define     USBHD_UEP1_BUF_MOD     0x10      // buffer mode of USB endpoint 1
+// UEPn_RX_EN & UEPn_TX_EN & UEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
+//   0 0 x:  disable endpoint and disable buffer
+//   1 0 0:  64 bytes buffer for receiving (OUT endpoint)
+//   1 0 1:  dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
+//   0 1 0:  64 bytes buffer for transmittal (IN endpoint)
+//   0 1 1:  dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
+//   1 1 0:  64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
+//   1 1 1:  dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
+#define     USBHD_UEP4_RX_EN       0x08      // enable USB endpoint 4 receiving (OUT)
+#define     USBHD_UEP4_TX_EN       0x04      // enable USB endpoint 4 transmittal (IN)
+// UEP4_RX_EN & UEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
+//   0 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
+//   1 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
+//   0 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
+//   1 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
+//           + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
+
+#define  USBHD_UEP2_3_MOD     (USBOTG_FS->UEP2_3_MOD)  // endpoint 2/3 mode
+#define     USBHD_UEP3_RX_EN       0x80      // enable USB endpoint 3 receiving (OUT)
+#define     USBHD_UEP3_TX_EN       0x40      // enable USB endpoint 3 transmittal (IN)
+#define     USBHD_UEP3_BUF_MOD     0x10      // buffer mode of USB endpoint 3
+#define     USBHD_UEP2_RX_EN       0x08      // enable USB endpoint 2 receiving (OUT)
+#define     USBHD_UEP2_TX_EN       0x04      // enable USB endpoint 2 transmittal (IN)
+#define     USBHD_UEP2_BUF_MOD     0x01      // buffer mode of USB endpoint 2
+
+#define  USBHD_UEP5_6_MOD     (USBOTG_FS->UEP5_6_MOD)  // endpoint 5/6 mode
+#define     USBHD_UEP6_RX_EN       0x80      // enable USB endpoint 6 receiving (OUT)
+#define     USBHD_UEP6_TX_EN       0x40      // enable USB endpoint 6 transmittal (IN)
+#define     USBHD_UEP6_BUF_MOD     0x10      // buffer mode of USB endpoint 6
+#define     USBHD_UEP5_RX_EN       0x08      // enable USB endpoint 5 receiving (OUT)
+#define     USBHD_UEP5_TX_EN       0x04      // enable USB endpoint 5 transmittal (IN)
+#define     USBHD_UEP5_BUF_MOD     0x01      // buffer mode of USB endpoint 5
+
+#define  USBHD_UEP7_MOD       (USBOTG_FS->UEP7_MOD)  // endpoint 7 mode
+#define     USBHD_UEP7_RX_EN       0x08      // enable USB endpoint 7 receiving (OUT)
+#define     USBHD_UEP7_TX_EN       0x04      // enable USB endpoint 7 transmittal (IN)
+#define     USBHD_UEP7_BUF_MOD     0x01      // buffer mode of USB endpoint 7
+/* USB_DMA */
+#define  USBHD_UEP0_DMA       (USBOTG_FS->UEP0_DMA) // endpoint 0 DMA buffer address
+#define  USBHD_UEP1_DMA       (USBOTG_FS->UEP1_DMA) // endpoint 1 DMA buffer address
+#define  USBHD_UEP2_DMA       (USBOTG_FS->UEP2_DMA) // endpoint 2 DMA buffer address
+#define  USBHD_UEP3_DMA       (USBOTG_FS->UEP3_DMA) // endpoint 3 DMA buffer address
+#define  USBHD_UEP4_DMA       (USBOTG_FS->UEP4_DMA) // endpoint 4 DMA buffer address
+#define  USBHD_UEP5_DMA       (USBOTG_FS->UEP5_DMA) // endpoint 5 DMA buffer address
+#define  USBHD_UEP6_DMA       (USBOTG_FS->UEP6_DMA) // endpoint 6 DMA buffer address
+#define  USBHD_UEP7_DMA       (USBOTG_FS->UEP7_DMA) // endpoint 7 DMA buffer address
+/* USB_EP_CTRL */
+#define  USBHD_UEP0_T_LEN     (USBOTG_FS->UEP0_TX_LEN)   // endpoint 0 transmittal length
+#define  USBHD_UEP0_TX_CTRL   (USBOTG_FS->UEP0_TX_CTRL)  // endpoint 0 control
+#define  USBHD_UEP0_RX_CTRL   (USBOTG_FS->UEP0_RX_CTRL)  // endpoint 0 control
+
+#define  USBHD_UEP1_T_LEN     (USBOTG_FS->UEP1_TX_LEN)   // endpoint 1 transmittal length
+#define  USBHD_UEP1_TX_CTRL   (USBOTG_FS->UEP1_TX_CTRL)  // endpoint 1 control
+#define  USBHD_UEP1_RX_CTRL   (USBOTG_FS->UEP1_RX_CTRL)  // endpoint 1 control
+
+#define  USBHD_UEP2_T_LEN     (USBOTG_FS->UEP2_TX_LEN)   // endpoint 2 transmittal length
+#define  USBHD_UEP2_TX_CTRL   (USBOTG_FS->UEP2_TX_CTRL)  // endpoint 2 control
+#define  USBHD_UEP2_RX_CTRL   (USBOTG_FS->UEP2_RX_CTRL)  // endpoint 2 control
+
+#define  USBHD_UEP3_T_LEN     (USBOTG_FS->UEP3_TX_LEN)   // endpoint 3 transmittal length
+#define  USBHD_UEP3_TX_CTRL   (USBOTG_FS->UEP3_TX_CTRL)  // endpoint 3 control
+#define  USBHD_UEP3_RX_CTRL   (USBOTG_FS->UEP3_RX_CTRL)  // endpoint 3 control
+
+#define  USBHD_UEP4_T_LEN     (USBOTG_FS->UEP4_TX_LEN)   // endpoint 4 transmittal length
+#define  USBHD_UEP4_TX_CTRL   (USBOTG_FS->UEP4_TX_CTRL)  // endpoint 4 control
+#define  USBHD_UEP4_RX_CTRL   (USBOTG_FS->UEP4_RX_CTRL)  // endpoint 4 control
+
+#define  USBHD_UEP5_T_LEN     (USBOTG_FS->UEP5_TX_LEN)   // endpoint 5 transmittal length
+#define  USBHD_UEP5_TX_CTRL   (USBOTG_FS->UEP5_TX_CTRL)  // endpoint 5 control
+#define  USBHD_UEP5_RX_CTRL   (USBOTG_FS->UEP5_RX_CTRL)  // endpoint 5 control
+
+#define  USBHD_UEP6_T_LEN     (USBOTG_FS->UEP6_TX_LEN)   // endpoint 6 transmittal length
+#define  USBHD_UEP6_TX_CTRL   (USBOTG_FS->UEP6_TX_CTRL)  // endpoint 6 control
+#define  USBHD_UEP6_RX_CTRL   (USBOTG_FS->UEP6_RX_CTRL)  // endpoint 6 control
+
+#define  USBHD_UEP7_T_LEN     (USBOTG_FS->UEP7_TX_LEN)   // endpoint 7 transmittal length
+#define  USBHD_UEP7_TX_CTRL   (USBOTG_FS->UEP7_TX_CTRL)  // endpoint 7 control
+#define  USBHD_UEP7_RX_CTRL   (USBOTG_FS->UEP7_RX_CTRL)  // endpoint 7 control
+
+#define     USBHD_UEP_AUTO_TOG     0x08      // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
+#define     USBHD_UEP_R_TOG        0x04      // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
+#define     USBHD_UEP_T_TOG        0x04      // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
+
+#define     USBHD_UEP_R_RES1       0x02      // handshake response type high bit for USB endpoint X receiving (OUT)
+#define     USBHD_UEP_R_RES0       0x01      // handshake response type low bit for USB endpoint X receiving (OUT)
+#define     USBHD_UEP_R_RES_MASK   0x03      // bit mask of handshake response type for USB endpoint X receiving (OUT)
+#define     USBHD_UEP_R_RES_ACK    0x00
+#define     USBHD_UEP_R_RES_TOUT   0x01
+#define     USBHD_UEP_R_RES_NAK    0x02
+#define     USBHD_UEP_R_RES_STALL  0x03
+// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
+//   00: ACK (ready)
+//   01: no response, time out to host, for non-zero endpoint isochronous transactions
+//   10: NAK (busy)
+//   11: STALL (error)
+#define     USBHD_UEP_T_RES1       0x02      // handshake response type high bit for USB endpoint X transmittal (IN)
+#define     USBHD_UEP_T_RES0       0x01      // handshake response type low bit for USB endpoint X transmittal (IN)
+#define     USBHD_UEP_T_RES_MASK   0x03      // bit mask of handshake response type for USB endpoint X transmittal (IN)
+#define     USBHD_UEP_T_RES_ACK    0x00
+#define     USBHD_UEP_T_RES_TOUT   0x01
+#define     USBHD_UEP_T_RES_NAK    0x02
+#define     USBHD_UEP_T_RES_STALL  0x03
+// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
+//   00: DATA0 or DATA1 then expecting ACK (ready)
+//   01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
+//   10: NAK (busy)
+//   11: TALL (error)
+
+#endif

port/ch32/usb_dc.c

@@ -1,8 +1,8 @@
 #include "usbd_core.h"
-#include "ch32f10x.h"
+#include "usb_ch32_regs.h"
 
 #ifndef USB_NUM_BIDIR_ENDPOINTS
-#define USB_NUM_BIDIR_ENDPOINTS 5
+#define USB_NUM_BIDIR_ENDPOINTS 8
 #endif
 
 /* Endpoint state */
@@ -23,37 +23,84 @@ struct usb_dc_config_priv {
     struct usb_dc_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */
 } usb_dc_cfg;
 
-/* Endpoint Buffer */
 // clang-format off
-__ALIGNED(4) uint8_t EP0_Databuf[64+64+64];	//ep0(64)+ep4_out(64)+ep4_in(64)
-__ALIGNED(4) uint8_t EP1_Databuf[64+64];	//ep1_out(64)+ep1_in(64)
-__ALIGNED(4) uint8_t EP2_Databuf[64+64];	//ep2_out(64)+ep2_in(64)
-__ALIGNED(4) uint8_t EP3_Databuf[64+64];	//ep3_out(64)+ep3_in(64)
+/* Endpoint Buffer */
+__attribute__ ((aligned(4))) uint8_t EP0_DatabufHD[64]; //ep0(64)
+__attribute__ ((aligned(4))) uint8_t EP1_DatabufHD[64+64];  //ep1_out(64)+ep1_in(64)
+__attribute__ ((aligned(4))) uint8_t EP2_DatabufHD[64+64];  //ep2_out(64)+ep2_in(64)
+__attribute__ ((aligned(4))) uint8_t EP3_DatabufHD[64+64];  //ep3_out(64)+ep3_in(64)
+__attribute__ ((aligned(4))) uint8_t EP4_DatabufHD[64+64];  //ep4_out(64)+ep4_in(64)
+__attribute__ ((aligned(4))) uint8_t EP5_DatabufHD[64+64];  //ep5_out(64)+ep5_in(64)
+__attribute__ ((aligned(4))) uint8_t EP6_DatabufHD[64+64];  //ep6_out(64)+ep6_in(64)
+__attribute__ ((aligned(4))) uint8_t EP7_DatabufHD[64+64];  //ep7_out(64)+ep7_in(64)
 // clang-format on
 
-int usb_dc_init(void)
-{
-    memset(&usb_dc_cfg, 0, sizeof(struct usb_dc_config_priv));
-
-    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
-    EXTEN->EXTEN_CTR |= EXTEN_USBHD_IO_EN;
-    RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_1Div5); //USBclk=PLLclk/1.5=48Mhz
-    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHD, ENABLE);
+void OTG_FS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
 
-    R8_USB_CTRL = 0x00;
+volatile uint8_t mps_over_flag = 0;
 
-    R8_UEP4_1_MOD = RB_UEP4_RX_EN | RB_UEP4_TX_EN | RB_UEP1_RX_EN | RB_UEP1_TX_EN;
-    R8_UEP2_3_MOD = RB_UEP2_RX_EN | RB_UEP2_TX_EN | RB_UEP3_RX_EN | RB_UEP3_TX_EN;
+__WEAK void usb_dc_low_level_init(void)
+{
+}
 
-    R8_USB_INT_FG = 0xFF;
-    R8_USB_INT_EN = RB_UIE_SUSPEND | RB_UIE_BUS_RST | RB_UIE_TRANSFER;
+__WEAK void usb_dc_low_level_deinit(void)
+{
+}
 
-    R8_USB_DEV_AD = 0x00;
-    usb_dc_cfg.dev_addr = 0;
-    R8_USB_CTRL = RB_UC_DEV_PU_EN | RB_UC_INT_BUSY | RB_UC_DMA_EN;
-    R8_UDEV_CTRL = RB_UD_PD_DIS | RB_UD_PORT_EN;
+int usb_dc_init(void)
+{
+    memset(&usb_dc_cfg, 0, sizeof(struct usb_dc_config_priv));
 
-    NVIC_EnableIRQ(USBHD_IRQn);
+    usb_dc_low_level_init();
+
+    USBOTG_FS->BASE_CTRL = 0x00;
+
+    USBOTG_FS->UEP4_1_MOD = USBHD_UEP4_RX_EN | USBHD_UEP4_TX_EN | USBHD_UEP1_RX_EN | USBHD_UEP1_TX_EN;
+    USBOTG_FS->UEP2_3_MOD = USBHD_UEP2_RX_EN | USBHD_UEP2_TX_EN | USBHD_UEP3_RX_EN | USBHD_UEP3_TX_EN;
+    USBOTG_FS->UEP5_6_MOD = USBHD_UEP5_RX_EN | USBHD_UEP5_TX_EN | USBHD_UEP6_RX_EN | USBHD_UEP6_TX_EN;
+    USBOTG_FS->UEP7_MOD = USBHD_UEP7_RX_EN | USBHD_UEP7_TX_EN;
+
+    USBOTG_FS->UEP0_DMA = (uint32_t)EP0_DatabufHD;
+    USBOTG_FS->UEP1_DMA = (uint32_t)EP1_DatabufHD;
+    USBOTG_FS->UEP2_DMA = (uint32_t)EP2_DatabufHD;
+    USBOTG_FS->UEP3_DMA = (uint32_t)EP3_DatabufHD;
+    USBOTG_FS->UEP4_DMA = (uint32_t)EP4_DatabufHD;
+    USBOTG_FS->UEP5_DMA = (uint32_t)EP5_DatabufHD;
+    USBOTG_FS->UEP6_DMA = (uint32_t)EP6_DatabufHD;
+    USBOTG_FS->UEP7_DMA = (uint32_t)EP7_DatabufHD;
+
+    USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK;
+    USBOTG_FS->UEP1_RX_CTRL = USBHD_UEP_R_RES_ACK;
+    USBOTG_FS->UEP2_RX_CTRL = USBHD_UEP_R_RES_ACK;
+    USBOTG_FS->UEP3_RX_CTRL = USBHD_UEP_R_RES_ACK;
+    USBOTG_FS->UEP4_RX_CTRL = USBHD_UEP_R_RES_ACK;
+    USBOTG_FS->UEP5_RX_CTRL = USBHD_UEP_R_RES_ACK;
+    USBOTG_FS->UEP6_RX_CTRL = USBHD_UEP_R_RES_ACK;
+    USBOTG_FS->UEP7_RX_CTRL = USBHD_UEP_R_RES_ACK;
+
+    USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK;
+    USBOTG_FS->UEP1_TX_LEN = 0;
+    USBOTG_FS->UEP2_TX_LEN = 0;
+    USBOTG_FS->UEP3_TX_LEN = 0;
+    USBOTG_FS->UEP4_TX_LEN = 0;
+    USBOTG_FS->UEP5_TX_LEN = 0;
+    USBOTG_FS->UEP6_TX_LEN = 0;
+    USBOTG_FS->UEP7_TX_LEN = 0;
+
+    USBOTG_FS->UEP1_TX_CTRL = USBHD_UEP_T_RES_NAK | USBHD_UEP_AUTO_TOG;
+    USBOTG_FS->UEP2_TX_CTRL = USBHD_UEP_T_RES_NAK | USBHD_UEP_AUTO_TOG;
+    USBOTG_FS->UEP3_TX_CTRL = USBHD_UEP_T_RES_NAK | USBHD_UEP_AUTO_TOG;
+    USBOTG_FS->UEP4_TX_CTRL = USBHD_UEP_T_RES_NAK | USBHD_UEP_AUTO_TOG;
+    USBOTG_FS->UEP5_TX_CTRL = USBHD_UEP_T_RES_NAK | USBHD_UEP_AUTO_TOG;
+    USBOTG_FS->UEP6_TX_CTRL = USBHD_UEP_T_RES_NAK | USBHD_UEP_AUTO_TOG;
+    USBOTG_FS->UEP7_TX_CTRL = USBHD_UEP_T_RES_NAK | USBHD_UEP_AUTO_TOG;
+
+    USBOTG_FS->INT_FG = 0xFF;
+    USBOTG_FS->INT_EN = USBHD_UIE_SUSPEND | USBHD_UIE_BUS_RST | USBHD_UIE_TRANSFER;
+    USBOTG_FS->DEV_ADDR = 0x00;
+
+    USBOTG_FS->BASE_CTRL = USBHD_UC_DEV_PU_EN | USBHD_UC_INT_BUSY | USBHD_UC_DMA_EN;
+    USBOTG_FS->UDEV_CTRL = USBHD_UD_PD_DIS | USBHD_UD_PORT_EN;
     return 0;
 }
 
@@ -64,7 +111,7 @@ void usb_dc_deinit(void)
 int usbd_set_address(const uint8_t addr)
 {
     if (addr == 0) {
-        R8_USB_DEV_AD = 0x00;
+        USBOTG_FS->DEV_ADDR = (USBOTG_FS->DEV_ADDR & USBHD_UDA_GP_BIT) | 0;
     }
     usb_dc_cfg.dev_addr = addr;
     return 0;
@@ -81,28 +128,6 @@ int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
         usb_dc_cfg.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
         usb_dc_cfg.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
     }
-
-    switch (ep_idx) {
-        case 0:
-            R16_UEP0_DMA = (UINT16)(UINT32)EP0_Databuf;
-            R8_UEP0_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
-            break;
-        case 1:
-            R16_UEP1_DMA = (UINT16)(UINT32)EP1_Databuf;
-            R8_UEP1_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
-            break;
-        case 2:
-            R16_UEP2_DMA = (UINT16)(UINT32)EP2_Databuf;
-            R8_UEP2_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
-            break;
-        case 3:
-            R16_UEP3_DMA = (UINT16)(UINT32)EP3_Databuf;
-            R8_UEP3_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
-            break;
-        default:
-            break;
-    }
-
     return 0;
 }
 int usbd_ep_close(const uint8_t ep)
@@ -111,10 +136,136 @@ int usbd_ep_close(const uint8_t ep)
 }
 int usbd_ep_set_stall(const uint8_t ep)
 {
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (USB_EP_DIR_IS_OUT(ep)) {
+        switch (ep_idx) {
+            case 0:
+                USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_TOG | USBHD_UEP_R_RES_STALL;
+                break;
+            case 1:
+                USBOTG_FS->UEP1_RX_CTRL = (USBOTG_FS->UEP1_RX_CTRL &= ~USBHD_UEP_R_RES_MASK) | USBHD_UEP_R_RES_STALL;
+                break;
+            case 2:
+                USBOTG_FS->UEP2_RX_CTRL = (USBOTG_FS->UEP2_RX_CTRL &= ~USBHD_UEP_R_RES_MASK) | USBHD_UEP_R_RES_STALL;
+                break;
+            case 3:
+                USBOTG_FS->UEP3_RX_CTRL = (USBOTG_FS->UEP3_RX_CTRL &= ~USBHD_UEP_R_RES_MASK) | USBHD_UEP_R_RES_STALL;
+                break;
+            case 4:
+                USBOTG_FS->UEP4_RX_CTRL = (USBOTG_FS->UEP4_RX_CTRL &= ~USBHD_UEP_R_RES_MASK) | USBHD_UEP_R_RES_STALL;
+                break;
+            case 5:
+                USBOTG_FS->UEP5_RX_CTRL = (USBOTG_FS->UEP5_RX_CTRL &= ~USBHD_UEP_R_RES_MASK) | USBHD_UEP_R_RES_STALL;
+                break;
+            case 6:
+                USBOTG_FS->UEP6_RX_CTRL = (USBOTG_FS->UEP6_RX_CTRL &= ~USBHD_UEP_R_RES_MASK) | USBHD_UEP_R_RES_STALL;
+                break;
+            case 7:
+                USBOTG_FS->UEP7_RX_CTRL = (USBOTG_FS->UEP7_RX_CTRL &= ~USBHD_UEP_R_RES_MASK) | USBHD_UEP_R_RES_STALL;
+                break;
+            default:
+                break;
+        }
+
+    } else {
+        switch (ep_idx) {
+            case 0:
+                USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_TOG | USBHD_UEP_T_RES_STALL;
+                break;
+            case 1:
+                USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL &= ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_STALL;
+                break;
+            case 2:
+                USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL &= ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_STALL;
+                break;
+            case 3:
+                USBOTG_FS->UEP3_TX_CTRL = (USBOTG_FS->UEP3_TX_CTRL &= ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_STALL;
+                break;
+            case 4:
+                USBOTG_FS->UEP4_TX_CTRL = (USBOTG_FS->UEP4_TX_CTRL &= ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_STALL;
+                break;
+            case 5:
+                USBOTG_FS->UEP5_TX_CTRL = (USBOTG_FS->UEP5_TX_CTRL &= ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_STALL;
+                break;
+            case 6:
+                USBOTG_FS->UEP6_TX_CTRL = (USBOTG_FS->UEP6_TX_CTRL &= ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_STALL;
+                break;
+            case 7:
+                USBOTG_FS->UEP7_TX_CTRL = (USBOTG_FS->UEP7_TX_CTRL &= ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_STALL;
+                break;
+            default:
+                break;
+        }
+    }
+
     return 0;
 }
+
 int usbd_ep_clear_stall(const uint8_t ep)
 {
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (USB_EP_DIR_IS_OUT(ep)) {
+        switch (ep_idx) {
+            case 0:
+
+                break;
+            case 1:
+                USBOTG_FS->UEP1_RX_CTRL = (USBOTG_FS->UEP1_RX_CTRL & ~(USBHD_UEP_R_TOG | USBHD_UEP_R_RES_MASK)) | USBHD_UEP_R_RES_ACK;
+                break;
+            case 2:
+                USBOTG_FS->UEP2_RX_CTRL = (USBOTG_FS->UEP2_RX_CTRL & ~(USBHD_UEP_R_TOG | USBHD_UEP_R_RES_MASK)) | USBHD_UEP_R_RES_ACK;
+                break;
+            case 3:
+                USBOTG_FS->UEP3_RX_CTRL = (USBOTG_FS->UEP3_RX_CTRL & ~(USBHD_UEP_R_TOG | USBHD_UEP_R_RES_MASK)) | USBHD_UEP_R_RES_ACK;
+                break;
+            case 4:
+                USBOTG_FS->UEP4_RX_CTRL = (USBOTG_FS->UEP4_RX_CTRL & ~(USBHD_UEP_R_TOG | USBHD_UEP_R_RES_MASK)) | USBHD_UEP_R_RES_ACK;
+                break;
+            case 5:
+                USBOTG_FS->UEP5_RX_CTRL = (USBOTG_FS->UEP5_RX_CTRL & ~(USBHD_UEP_R_TOG | USBHD_UEP_R_RES_MASK)) | USBHD_UEP_R_RES_ACK;
+                break;
+            case 6:
+                USBOTG_FS->UEP6_RX_CTRL = (USBOTG_FS->UEP6_RX_CTRL & ~(USBHD_UEP_R_TOG | USBHD_UEP_R_RES_MASK)) | USBHD_UEP_R_RES_ACK;
+                break;
+            case 7:
+                USBOTG_FS->UEP7_RX_CTRL = (USBOTG_FS->UEP7_RX_CTRL & ~(USBHD_UEP_R_TOG | USBHD_UEP_R_RES_MASK)) | USBHD_UEP_R_RES_ACK;
+                break;
+            default:
+                break;
+        }
+
+    } else {
+        switch (ep_idx) {
+            case 0:
+
+                break;
+            case 1:
+                USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL & ~(USBHD_UEP_T_TOG | USBHD_UEP_T_RES_MASK)) | USBHD_UEP_T_RES_NAK;
+                break;
+            case 2:
+                USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL & ~(USBHD_UEP_T_TOG | USBHD_UEP_T_RES_MASK)) | USBHD_UEP_T_RES_NAK;
+                break;
+            case 3:
+                USBOTG_FS->UEP3_TX_CTRL = (USBOTG_FS->UEP3_TX_CTRL & ~(USBHD_UEP_T_TOG | USBHD_UEP_T_RES_MASK)) | USBHD_UEP_T_RES_NAK;
+                break;
+            case 4:
+                USBOTG_FS->UEP4_TX_CTRL = (USBOTG_FS->UEP4_TX_CTRL & ~(USBHD_UEP_T_TOG | USBHD_UEP_T_RES_MASK)) | USBHD_UEP_T_RES_NAK;
+                break;
+            case 5:
+                USBOTG_FS->UEP5_TX_CTRL = (USBOTG_FS->UEP5_TX_CTRL & ~(USBHD_UEP_T_TOG | USBHD_UEP_T_RES_MASK)) | USBHD_UEP_T_RES_NAK;
+                break;
+            case 6:
+                USBOTG_FS->UEP6_TX_CTRL = (USBOTG_FS->UEP6_TX_CTRL & ~(USBHD_UEP_T_TOG | USBHD_UEP_T_RES_MASK)) | USBHD_UEP_T_RES_NAK;
+                break;
+            case 7:
+                USBOTG_FS->UEP7_TX_CTRL = (USBOTG_FS->UEP7_TX_CTRL & ~(USBHD_UEP_T_TOG | USBHD_UEP_T_RES_MASK)) | USBHD_UEP_T_RES_NAK;
+                break;
+            default:
+                break;
+        }
+    }
     return 0;
 }
 int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
@@ -131,31 +282,95 @@ int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint
     }
 
     if (!data_len) {
+        switch (ep_idx) {
+            case 0:
+                USBOTG_FS->UEP0_TX_LEN = 0;
+                break;
+            case 1:
+                USBOTG_FS->UEP1_TX_LEN = 0;
+                USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
+                break;
+            case 2:
+                USBOTG_FS->UEP2_TX_LEN = 0;
+                USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
+                break;
+            case 3:
+                USBOTG_FS->UEP3_TX_LEN = 0;
+                USBOTG_FS->UEP3_TX_CTRL = (USBOTG_FS->UEP3_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
+                break;
+            case 4:
+                USBOTG_FS->UEP4_TX_LEN = 0;
+                USBOTG_FS->UEP4_TX_CTRL = (USBOTG_FS->UEP4_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
+                break;
+            case 5:
+                USBOTG_FS->UEP5_TX_LEN = 0;
+                USBOTG_FS->UEP5_TX_CTRL = (USBOTG_FS->UEP5_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
+                break;
+            case 6:
+                USBOTG_FS->UEP6_TX_LEN = 0;
+                USBOTG_FS->UEP6_TX_CTRL = (USBOTG_FS->UEP6_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
+                break;
+            case 7:
+                USBOTG_FS->UEP7_TX_LEN = 0;
+                USBOTG_FS->UEP7_TX_CTRL = (USBOTG_FS->UEP7_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
+                break;
+            default:
+                break;
+        }
+
         return 0;
     }
 
     if (data_len > usb_dc_cfg.in_ep[ep_idx].ep_mps) {
         data_len = usb_dc_cfg.in_ep[ep_idx].ep_mps;
+
+        if (ep_idx == 0) {
+            mps_over_flag = 1;
+        }
     }
 
-    if (ep_idx == 0) {
-        memcpy(&EP0_Databuf[0], data, data_len);
-    } else if (ep_idx == 1) {
-        memcpy(&EP1_Databuf[64], data, data_len);
-        R8_UEP1_T_LEN = data_len;
-        R8_UEP1_CTRL = (R8_UEP1_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
-    } else if (ep_idx == 2) {
-        memcpy(&EP2_Databuf[64], data, data_len);
-        R8_UEP2_T_LEN = data_len;
-        R8_UEP2_CTRL = (R8_UEP2_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
-    } else if (ep_idx == 3) {
-        memcpy(&EP3_Databuf[64], data, data_len);
-        R8_UEP3_T_LEN = data_len;
-        R8_UEP3_CTRL = (R8_UEP3_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
-    } else if (ep_idx == 4) {
-        memcpy(&EP0_Databuf[128], data, data_len);
-        R8_UEP4_T_LEN = data_len;
-        R8_UEP4_CTRL = (R8_UEP4_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
+    switch (ep_idx) {
+        case 0:
+            memcpy(&EP0_DatabufHD[0], data, data_len);
+            USBOTG_FS->UEP0_TX_LEN = data_len;
+            break;
+        case 1:
+            memcpy(&EP1_DatabufHD[64], data, data_len);
+            USBOTG_FS->UEP1_TX_LEN = data_len;
+            USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
+            break;
+        case 2:
+            memcpy(&EP2_DatabufHD[64], data, data_len);
+            USBOTG_FS->UEP2_TX_LEN = data_len;
+            USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
+            break;
+        case 3:
+            memcpy(&EP3_DatabufHD[64], data, data_len);
+            USBOTG_FS->UEP3_TX_LEN = data_len;
+            USBOTG_FS->UEP3_TX_CTRL = (USBOTG_FS->UEP3_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
+            break;
+        case 4:
+            memcpy(&EP4_DatabufHD[64], data, data_len);
+            USBOTG_FS->UEP4_TX_LEN = data_len;
+            USBOTG_FS->UEP4_TX_CTRL = (USBOTG_FS->UEP4_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
+            break;
+        case 5:
+            memcpy(&EP5_DatabufHD[64], data, data_len);
+            USBOTG_FS->UEP5_TX_LEN = data_len;
+            USBOTG_FS->UEP5_TX_CTRL = (USBOTG_FS->UEP5_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
+            break;
+        case 6:
+            memcpy(&EP6_DatabufHD[64], data, data_len);
+            USBOTG_FS->UEP6_TX_LEN = data_len;
+            USBOTG_FS->UEP6_TX_CTRL = (USBOTG_FS->UEP6_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
+            break;
+        case 7:
+            memcpy(&EP7_DatabufHD[64], data, data_len);
+            USBOTG_FS->UEP7_TX_LEN = data_len;
+            USBOTG_FS->UEP7_TX_CTRL = (USBOTG_FS->UEP7_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_ACK;
+            break;
+        default:
+            break;
     }
 
     if (ret_bytes) {
@@ -178,19 +393,43 @@ int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_
         return 0;
     }
 
-    read_count = R8_USB_RX_LEN;
+    read_count = USBOTG_FS->RX_LEN;
     read_count = MIN(read_count, max_data_len);
-    if (ep_idx == 0) {
-        memcpy(data, &EP0_Databuf[0], read_count);
-    } else if (ep_idx == 1) {
-        memcpy(data, &EP1_Databuf[0], read_count);
-    } else if (ep_idx == 2) {
-        memcpy(data, &EP2_Databuf[0], read_count);
-    } else if (ep_idx == 3) {
-        memcpy(data, &EP3_Databuf[0], read_count);
-    } else if (ep_idx == 4) {
-        memcpy(data, &EP0_Databuf[64], read_count);
+
+    switch (ep_idx) {
+        case 0:
+            if ((max_data_len == 8) && !read_bytes) {
+                read_count = 8;
+                memcpy(data, &EP0_DatabufHD[0], 8);
+            } else {
+                memcpy(data, &EP0_DatabufHD[0], read_count);
+            }
+            break;
+        case 1:
+            memcpy(data, &EP1_DatabufHD[0], read_count);
+            break;
+        case 2:
+            memcpy(data, &EP2_DatabufHD[0], read_count);
+            break;
+        case 3:
+            memcpy(data, &EP3_DatabufHD[0], read_count);
+            break;
+        case 4:
+            memcpy(data, &EP4_DatabufHD[0], read_count);
+            break;
+        case 5:
+            memcpy(data, &EP5_DatabufHD[0], read_count);
+            break;
+        case 6:
+            memcpy(data, &EP6_DatabufHD[0], read_count);
+            break;
+        case 7:
+            memcpy(data, &EP7_DatabufHD[0], read_count);
+            break;
+        default:
+            break;
     }
+
     if (read_bytes) {
         *read_bytes = read_count;
     }
@@ -198,58 +437,90 @@ int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t max_data_len, uint32_
     return 0;
 }
 
-/**
-  * @brief  This function handles PCD interrupt request.
-  * @param  hpcd PCD handle
-  * @retval HAL status
-  */
-void USBD_IRQHandler(void)
+/*********************************************************************
+ * @fn      OTG_FS_IRQHandler
+ *
+ * @brief   This function handles OTG_FS exception.
+ *
+ * @return  none
+ */
+void OTG_FS_IRQHandler(void)
 {
-    UINT8 len, chtype;
-    UINT8 intflag, errflag = 0;
+    uint8_t intflag = 0;
+
+    intflag = USBOTG_FS->INT_FG;
 
-    intflag = R8_USB_INT_FG;
+    if (intflag & USBHD_UIF_TRANSFER) {
+        switch (USBOTG_FS->INT_ST & USBHD_UIS_TOKEN_MASK) {
+            case USBHD_UIS_TOKEN_SETUP:
+                USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_TOG | USBHD_UEP_T_RES_NAK;
+                USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_TOG | USBHD_UEP_R_RES_ACK;
 
-    if (intflag & RB_UIF_TRANSFER) {
-        switch (R8_USB_INT_ST & MASK_UIS_TOKEN) {
-            case UIS_TOKEN_SETUP:
                 usbd_event_notify_handler(USBD_EVENT_SETUP_NOTIFY, NULL);
-                R8_UEP0_CTRL = RB_UEP_R_TOG | RB_UEP_T_TOG | UEP_R_RES_ACK | UEP_T_RES_NAK;
+
+                USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_TOG | USBHD_UEP_T_RES_ACK;
+                USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_TOG | USBHD_UEP_R_RES_ACK;
                 break;
 
-            case UIS_TOKEN_IN:
-                switch (R8_USB_INT_ST & (MASK_UIS_TOKEN | MASK_UIS_ENDP)) {
-                    case UIS_TOKEN_IN:
+            case USBHD_UIS_TOKEN_IN:
+                switch (USBOTG_FS->INT_ST & (USBHD_UIS_TOKEN_MASK | USBHD_UIS_ENDP_MASK)) {
+                    case USBHD_UIS_TOKEN_IN:
+
                         usbd_event_notify_handler(USBD_EVENT_EP0_IN_NOTIFY, NULL);
                         if (usb_dc_cfg.dev_addr > 0) {
-                            R8_USB_DEV_AD = (R8_USB_DEV_AD & RB_UDA_GP_BIT) | usb_dc_cfg.dev_addr;
+                            USBOTG_FS->DEV_ADDR = (USBOTG_FS->DEV_ADDR & USBHD_UDA_GP_BIT) | usb_dc_cfg.dev_addr;
                             usb_dc_cfg.dev_addr = 0;
                         }
-                        R8_UEP0_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+
+                        if (mps_over_flag) {
+                            mps_over_flag = 0;
+                            USBOTG_FS->UEP0_TX_CTRL ^= USBHD_UEP_T_TOG;
+                        } else {
+                            USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK;
+                            USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK;
+                        }
                         break;
 
-                    case UIS_TOKEN_IN | 1:
+                    case USBHD_UIS_TOKEN_IN | 1:
+                        USBOTG_FS->UEP1_TX_CTRL = (USBOTG_FS->UEP1_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK;
+                        USBOTG_FS->UEP1_TX_CTRL ^= USBHD_UEP_T_TOG;
                         usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(1 | 0x80));
-                        R8_UEP1_CTRL ^= RB_UEP_T_TOG;
-                        R8_UEP1_CTRL = (R8_UEP1_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_NAK;
                         break;
 
-                    case UIS_TOKEN_IN | 2:
+                    case USBHD_UIS_TOKEN_IN | 2:
+                        USBOTG_FS->UEP2_TX_CTRL = (USBOTG_FS->UEP2_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK;
+                        USBOTG_FS->UEP2_TX_CTRL ^= USBHD_UEP_T_TOG;
                         usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(2 | 0x80));
-                        R8_UEP2_CTRL ^= RB_UEP_T_TOG;
-                        R8_UEP2_CTRL = (R8_UEP2_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_NAK;
                         break;
 
-                    case UIS_TOKEN_IN | 3:
+                    case USBHD_UIS_TOKEN_IN | 3:
+                        USBOTG_FS->UEP3_TX_CTRL = (USBOTG_FS->UEP3_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK;
+                        USBOTG_FS->UEP3_TX_CTRL ^= USBHD_UEP_T_TOG;
                         usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(3 | 0x80));
-                        R8_UEP3_CTRL ^= RB_UEP_T_TOG;
-                        R8_UEP3_CTRL = (R8_UEP3_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_NAK;
                         break;
 
-                    case UIS_TOKEN_IN | 4:
+                    case USBHD_UIS_TOKEN_IN | 4:
+                        USBOTG_FS->UEP4_TX_CTRL = (USBOTG_FS->UEP4_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK;
+                        USBOTG_FS->UEP4_TX_CTRL ^= USBHD_UEP_T_TOG;
                         usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(4 | 0x80));
-                        R8_UEP4_CTRL ^= RB_UEP_T_TOG;
-                        R8_UEP4_CTRL = (R8_UEP4_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_NAK;
+                        break;
+
+                    case USBHD_UIS_TOKEN_IN | 5:
+                        USBOTG_FS->UEP5_TX_CTRL = (USBOTG_FS->UEP5_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK;
+                        USBOTG_FS->UEP5_TX_CTRL ^= USBHD_UEP_T_TOG;
+                        usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(5 | 0x80));
+                        break;
+
+                    case USBHD_UIS_TOKEN_IN | 6:
+                        USBOTG_FS->UEP6_TX_CTRL = (USBOTG_FS->UEP6_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK;
+                        USBOTG_FS->UEP6_TX_CTRL ^= USBHD_UEP_T_TOG;
+                        usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(6 | 0x80));
+                        break;
+
+                    case USBHD_UIS_TOKEN_IN | 7:
+                        USBOTG_FS->UEP7_TX_CTRL = (USBOTG_FS->UEP7_TX_CTRL & ~USBHD_UEP_T_RES_MASK) | USBHD_UEP_T_RES_NAK;
+                        USBOTG_FS->UEP7_TX_CTRL ^= USBHD_UEP_T_TOG;
+                        usbd_event_notify_handler(USBD_EVENT_EP_IN_NOTIFY, (void *)(7 | 0x80));
                         break;
 
                     default:
@@ -257,58 +528,105 @@ void USBD_IRQHandler(void)
                 }
                 break;
 
-            case UIS_TOKEN_OUT:
-                switch (R8_USB_INT_ST & (MASK_UIS_TOKEN | MASK_UIS_ENDP)) {
-                    case UIS_TOKEN_OUT:
+            case USBHD_UIS_TOKEN_OUT:
+                switch (USBOTG_FS->INT_ST & (USBHD_UIS_TOKEN_MASK | USBHD_UIS_ENDP_MASK)) {
+                    case USBHD_UIS_TOKEN_OUT:
                         usbd_event_notify_handler(USBD_EVENT_EP0_OUT_NOTIFY, NULL);
                         break;
 
-                    case UIS_TOKEN_OUT | 1:
-                        if (R8_USB_INT_ST & RB_UIS_TOG_OK) {
+                    case USBHD_UIS_TOKEN_OUT | 1:
+                        if (USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK) {
+                            USBOTG_FS->UEP1_RX_CTRL ^= USBHD_UEP_R_TOG;
                             usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(1 & 0x7f));
-                            R8_UEP1_CTRL ^= RB_UEP_R_TOG;
                         }
                         break;
 
-                    case UIS_TOKEN_OUT | 2:
-                        if (R8_USB_INT_ST & RB_UIS_TOG_OK) {
+                    case USBHD_UIS_TOKEN_OUT | 2:
+                        if (USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK) {
+                            USBOTG_FS->UEP2_RX_CTRL ^= USBHD_UEP_R_TOG;
                             usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(2 & 0x7f));
-                            R8_UEP2_CTRL ^= RB_UEP_R_TOG;
                         }
                         break;
 
-                    case UIS_TOKEN_OUT | 3:
-                        if (R8_USB_INT_ST & RB_UIS_TOG_OK) {
+                    case USBHD_UIS_TOKEN_OUT | 3:
+                        if (USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK) {
+                            USBOTG_FS->UEP3_RX_CTRL ^= USBHD_UEP_R_TOG;
                             usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(3 & 0x7f));
-                            R8_UEP3_CTRL ^= RB_UEP_R_TOG;
                         }
                         break;
 
-                    case UIS_TOKEN_OUT | 4:
-                        if (R8_USB_INT_ST & RB_UIS_TOG_OK) {
+                    case USBHD_UIS_TOKEN_OUT | 4:
+                        if (USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK) {
+                            USBOTG_FS->UEP4_RX_CTRL ^= USBHD_UEP_R_TOG;
                             usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(4 & 0x7f));
-                            R8_UEP4_CTRL ^= RB_UEP_R_TOG;
+                        }
+                        break;
+
+                    case USBHD_UIS_TOKEN_OUT | 5:
+                        if (USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK) {
+                            USBOTG_FS->UEP5_RX_CTRL ^= USBHD_UEP_R_TOG;
+                            usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(5 & 0x7f));
+                        }
+                        break;
+
+                    case USBHD_UIS_TOKEN_OUT | 6:
+                        if (USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK) {
+                            USBOTG_FS->UEP6_RX_CTRL ^= USBHD_UEP_R_TOG;
+                            usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(6 & 0x7f));
+                        }
+                        break;
+
+                    case USBHD_UIS_TOKEN_OUT | 7:
+                        if (USBOTG_FS->INT_ST & USBHD_UIS_TOG_OK) {
+                            USBOTG_FS->UEP7_RX_CTRL ^= USBHD_UEP_R_TOG;
+                            usbd_event_notify_handler(USBD_EVENT_EP_OUT_NOTIFY, (void *)(7 & 0x7f));
                         }
                         break;
                 }
 
                 break;
 
-            case UIS_TOKEN_SOF:
+            case USBHD_UIS_TOKEN_SOF:
 
                 break;
 
             default:
                 break;
         }
-        R8_USB_INT_FG = RB_UIF_TRANSFER;
-    } else if (intflag & RB_UIF_BUS_RST) {
-        R8_USB_DEV_AD = 0;
+
+        USBOTG_FS->INT_FG = USBHD_UIF_TRANSFER;
+    } else if (intflag & USBHD_UIF_BUS_RST) {
+        USBOTG_FS->DEV_ADDR = 0;
+
+        USBOTG_FS->UEP0_RX_CTRL = USBHD_UEP_R_RES_ACK;
+        USBOTG_FS->UEP1_RX_CTRL = USBHD_UEP_R_RES_ACK;
+        USBOTG_FS->UEP2_RX_CTRL = USBHD_UEP_R_RES_ACK;
+        USBOTG_FS->UEP3_RX_CTRL = USBHD_UEP_R_RES_ACK;
+        USBOTG_FS->UEP4_RX_CTRL = USBHD_UEP_R_RES_ACK;
+        USBOTG_FS->UEP5_RX_CTRL = USBHD_UEP_R_RES_ACK;
+        USBOTG_FS->UEP6_RX_CTRL = USBHD_UEP_R_RES_ACK;
+        USBOTG_FS->UEP7_RX_CTRL = USBHD_UEP_R_RES_ACK;
+
+        USBOTG_FS->UEP0_TX_CTRL = USBHD_UEP_T_RES_NAK;
+        USBOTG_FS->UEP1_TX_CTRL = USBHD_UEP_T_RES_NAK;
+        USBOTG_FS->UEP2_TX_CTRL = USBHD_UEP_T_RES_NAK;
+        USBOTG_FS->UEP3_TX_CTRL = USBHD_UEP_T_RES_NAK;
+        USBOTG_FS->UEP4_TX_CTRL = USBHD_UEP_T_RES_NAK;
+        USBOTG_FS->UEP5_TX_CTRL = USBHD_UEP_T_RES_NAK;
+        USBOTG_FS->UEP6_TX_CTRL = USBHD_UEP_T_RES_NAK;
+        USBOTG_FS->UEP7_TX_CTRL = USBHD_UEP_T_RES_NAK;
+
         usbd_event_notify_handler(USBD_EVENT_RESET, NULL);
-        R8_USB_INT_FG |= RB_UIF_BUS_RST;
-    } else if (intflag & RB_UIF_SUSPEND) {
-        R8_USB_INT_FG = RB_UIF_SUSPEND;
+
+        USBOTG_FS->INT_FG |= USBHD_UIF_BUS_RST;
+    } else if (intflag & USBHD_UIF_SUSPEND) {
+        if (USBOTG_FS->MIS_ST & USBHD_UMS_SUSPEND) {
+            ;
+        } else {
+            ;
+        }
+        USBOTG_FS->INT_FG = USBHD_UIF_SUSPEND;
     } else {
-        R8_USB_INT_FG = intflag;
+        USBOTG_FS->INT_FG = intflag;
     }
 }