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@@ -0,0 +1,431 @@
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+/*
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+ * Copyright (c) 2024 ~ 2025, sakumisu
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ */
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+#include "usbd_core.h"
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+#include "usbh_core.h"
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+#include "fsl_common.h"
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+#include "usb_chipidea_reg.h"
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+
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+__WEAK void USBD_IRQHandler(uint8_t busid)
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+{
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+}
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+
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+__WEAK void USBH_IRQHandler(uint8_t busid)
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+{
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+}
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+
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+#if !defined(CONFIG_USB_EHCI_NXP)
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+#error "mcx ehci must config CONFIG_USB_EHCI_NXP"
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+#endif
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+
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+#if !defined(CONFIG_USB_EHCI_HCCR_OFFSET) || CONFIG_USB_EHCI_HCCR_OFFSET != 0x100
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+#error "mcx ehci must config CONFIG_USB_EHCI_HCCR_OFFSET to 0x100"
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+#endif
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+
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+#define USB_DEVICE_CONFIG_EHCI 1
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+
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+/*! @brief USB controller ID */
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+typedef enum _usb_controller_index {
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+ kUSB_ControllerKhci0 = 0U, /*!< KHCI 0U */
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+ kUSB_ControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs, this is reserved
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+ to be used in the future. */
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+ kUSB_ControllerEhci0 = 2U, /*!< EHCI 0U */
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+ kUSB_ControllerEhci1 = 3U, /*!< EHCI 1U, Currently, there are no platforms which have two EHCI IPs, this is reserved
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+ to be used in the future. */
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+
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+ kUSB_ControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */
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+ kUSB_ControllerLpcIp3511Fs1 = 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which have two IP3511
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+ IPs, this is reserved to be used in the future. */
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+
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+ kUSB_ControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */
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+ kUSB_ControllerLpcIp3511Hs1 = 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which have two IP3511
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+ IPs, this is reserved to be used in the future. */
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+
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+ kUSB_ControllerOhci0 = 8U, /*!< OHCI 0U */
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+ kUSB_ControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs, this is reserved
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+ to be used in the future. */
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+
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+ kUSB_ControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */
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+ kUSB_ControllerIp3516Hs1 = 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two IP3516HS IPs,
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+ this is reserved to be used in the future. */
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+ kUSB_ControllerDwc30 = 12U, /*!< DWC3 0U */
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+ kUSB_ControllerDwc31 = 13U, /*!< DWC3 1U Currently, there are no platforms which have two Dwc IPs, this is reserved
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+ to be used in the future.*/
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+} usb_controller_index_t;
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+
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+/* USB PHY condfiguration */
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+#define BOARD_USB_PHY_D_CAL (0x04U)
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+#define BOARD_USB_PHY_TXCAL45DP (0x07U)
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+#define BOARD_USB_PHY_TXCAL45DM (0x07U)
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+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
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+
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+typedef struct _usb_phy_config_struct {
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+ uint8_t D_CAL; /* Decode to trim the nominal 17.78mA current source */
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+ uint8_t TXCAL45DP; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DP output pin */
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+ uint8_t TXCAL45DM; /* Decode to trim the nominal 45-Ohm series termination resistance to the USB_DM output pin */
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+} usb_phy_config_struct_t;
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+
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+void *USB_EhciPhyGetBase(uint8_t controllerId)
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+{
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+ void *usbPhyBase = NULL;
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+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
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+#if defined(USBPHY_STACK_BASE_ADDRS)
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+ uint32_t usbphy_base[] = USBPHY_STACK_BASE_ADDRS;
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+#else
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+ uint32_t usbphy_base[] = USBPHY_BASE_ADDRS;
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+#endif
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+ uint32_t *temp;
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+ if (controllerId < (uint8_t)kUSB_ControllerEhci0) {
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+ return NULL;
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+ }
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+
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+ if ((controllerId == (uint8_t)kUSB_ControllerEhci0) || (controllerId == (uint8_t)kUSB_ControllerEhci1)) {
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+ controllerId = controllerId - (uint8_t)kUSB_ControllerEhci0;
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+ } else if ((controllerId == (uint8_t)kUSB_ControllerLpcIp3511Hs0) ||
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+ (controllerId == (uint8_t)kUSB_ControllerLpcIp3511Hs1)) {
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+ controllerId = controllerId - (uint8_t)kUSB_ControllerLpcIp3511Hs0;
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+ } else if ((controllerId == (uint8_t)kUSB_ControllerIp3516Hs0) || (controllerId == (uint8_t)kUSB_ControllerIp3516Hs1)) {
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+ controllerId = controllerId - (uint8_t)kUSB_ControllerIp3516Hs0;
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+ } else {
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+ return NULL;
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+ }
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+
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+ if (controllerId < (sizeof(usbphy_base) / sizeof(usbphy_base[0]))) {
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+ temp = (uint32_t *)usbphy_base[controllerId];
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+ usbPhyBase = (void *)temp;
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+ } else {
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+ return NULL;
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+ }
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+#endif
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+ return usbPhyBase;
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+}
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+
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+/*!
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+ * @brief ehci phy initialization.
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+ *
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+ * This function initialize ehci phy IP.
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+ *
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+ * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
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+ * @param[in] freq the external input clock.
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+ * for example: if the external input clock is 16M, the parameter freq should be 16000000.
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+ *
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+ * @retval 0 cancel successfully.
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+ * @retval -1 the freq value is incorrect.
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+ */
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+uint32_t USB_EhciPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig)
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+{
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+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
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+ USBPHY_Type *usbPhyBase;
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+
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+ usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
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+ if (NULL == usbPhyBase) {
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+ return (uint8_t)-1;
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+ }
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+
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+#if ((defined FSL_FEATURE_SOC_ANATOP_COUNT) && (FSL_FEATURE_SOC_ANATOP_COUNT > 0U))
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+ ANATOP->HW_ANADIG_REG_3P0.RW =
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+ (ANATOP->HW_ANADIG_REG_3P0.RW &
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+ (~(ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x1F) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_ILIMIT_MASK))) |
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+ ANATOP_HW_ANADIG_REG_3P0_OUTPUT_TRG(0x17) | ANATOP_HW_ANADIG_REG_3P0_ENABLE_LINREG_MASK;
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+ ANATOP->HW_ANADIG_USB2_CHRG_DETECT.SET =
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+ ANATOP_HW_ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B_MASK | ANATOP_HW_ANADIG_USB2_CHRG_DETECT_EN_B_MASK;
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+#endif
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+
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+#if (defined USB_ANALOG)
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+ USB_ANALOG->INSTANCE[controllerId - (uint8_t)kUSB_ControllerEhci0].CHRG_DETECT_SET =
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+ USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(1) | USB_ANALOG_CHRG_DETECT_EN_B(1);
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+#endif
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+
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+#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
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+
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+ usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
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+#endif
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+ usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */
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+ usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */
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+ /* PWD register provides overall control of the PHY power state */
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+ usbPhyBase->PWD = 0U;
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+ if (((uint8_t)kUSB_ControllerIp3516Hs0 == controllerId) || ((uint8_t)kUSB_ControllerIp3516Hs1 == controllerId) ||
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+ ((uint8_t)kUSB_ControllerLpcIp3511Hs0 == controllerId) ||
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+ ((uint8_t)kUSB_ControllerLpcIp3511Hs1 == controllerId)) {
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+ usbPhyBase->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK;
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+ usbPhyBase->CTRL_SET = USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK;
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+ }
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+ if (NULL != phyConfig) {
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+ /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */
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+ usbPhyBase->TX =
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+ ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) |
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+ (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) |
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+ USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM)));
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+ }
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+#endif
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+
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+ return (uint8_t)0;
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+}
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+
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+/*!
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+ * @brief ehci phy initialization for suspend and resume.
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+ *
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+ * This function initialize ehci phy IP for suspend and resume.
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+ *
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+ * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
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+ * @param[in] freq the external input clock.
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+ * for example: if the external input clock is 16M, the parameter freq should be 16000000.
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+ *
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+ * @retval 0 cancel successfully.
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+ * @retval -1 the freq value is incorrect.
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+ */
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+uint32_t USB_EhciLowPowerPhyInit(uint8_t controllerId, uint32_t freq, usb_phy_config_struct_t *phyConfig)
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+{
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+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
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+ USBPHY_Type *usbPhyBase;
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+
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+ usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
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+ if (NULL == usbPhyBase) {
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+ return (uint8_t)-1;
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+ }
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+
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+#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
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+ usbPhyBase->TRIM_OVERRIDE_EN = 0x001fU; /* override IFR value */
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+#endif
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+
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+#if ((defined USBPHY_CTRL_AUTORESUME_EN_MASK) && (USBPHY_CTRL_AUTORESUME_EN_MASK > 0U))
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+ usbPhyBase->CTRL_CLR |= USBPHY_CTRL_AUTORESUME_EN_MASK;
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+#else
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+ usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTO_PWRON_PLL_MASK;
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+#endif
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+ usbPhyBase->CTRL |= USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK | USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK;
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+ usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL2_MASK; /* support LS device. */
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+ usbPhyBase->CTRL |= USBPHY_CTRL_SET_ENUTMILEVEL3_MASK; /* support external FS Hub with LS device connected. */
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+ /* PWD register provides overall control of the PHY power state */
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+ usbPhyBase->PWD = 0U;
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+#if (defined USBPHY_ANACTRL_PFD_CLKGATE_MASK)
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+ /* now the 480MHz USB clock is up, then configure fractional divider after PLL with PFD
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+ * pfd clock = 480MHz*18/N, where N=18~35
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+ * Please note that USB1PFDCLK has to be less than 180MHz for RUN or HSRUN mode
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+ */
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+ usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_FRAC(24); /* N=24 */
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+ usbPhyBase->ANACTRL |= USBPHY_ANACTRL_PFD_CLK_SEL(1); /* div by 4 */
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+
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+ usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_DEV_PULLDOWN_MASK;
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+ usbPhyBase->ANACTRL &= ~USBPHY_ANACTRL_PFD_CLKGATE_MASK;
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+ while (0U == (usbPhyBase->ANACTRL & USBPHY_ANACTRL_PFD_STABLE_MASK)) {
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+ }
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+#endif
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+ if (NULL != phyConfig) {
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+ /* Decode to trim the nominal 17.78mA current source for the High Speed TX drivers on USB_DP and USB_DM. */
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+ usbPhyBase->TX =
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+ ((usbPhyBase->TX & (~(USBPHY_TX_D_CAL_MASK | USBPHY_TX_TXCAL45DM_MASK | USBPHY_TX_TXCAL45DP_MASK))) |
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+ (USBPHY_TX_D_CAL(phyConfig->D_CAL) | USBPHY_TX_TXCAL45DP(phyConfig->TXCAL45DP) |
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+ USBPHY_TX_TXCAL45DM(phyConfig->TXCAL45DM)));
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+ }
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+#endif
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+
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+ return (uint8_t)0;
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+}
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+
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+/*!
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+ * @brief ehci phy de-initialization.
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+ *
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+ * This function de-initialize ehci phy IP.
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+ *
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+ * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
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+ */
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+void USB_EhciPhyDeinit(uint8_t controllerId)
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+{
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+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
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+ USBPHY_Type *usbPhyBase;
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+
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+ usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
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+ if (NULL == usbPhyBase) {
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+ return;
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+ }
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+#if ((!(defined FSL_FEATURE_SOC_CCM_ANALOG_COUNT)) && (!(defined FSL_FEATURE_SOC_ANATOP_COUNT)))
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+ usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_POWER_MASK; /* power down PLL */
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+ usbPhyBase->PLL_SIC &= ~USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK; /* disable USB clock output from USB PHY PLL */
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+#endif
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+ usbPhyBase->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* set to 1U to gate clocks */
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+#endif
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+}
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+
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+/*!
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+ * @brief ehci phy disconnect detection enable or disable.
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+ *
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+ * This function enable/disable host ehci disconnect detection.
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+ *
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+ * @param[in] controllerId ehci controller id, please reference to #usb_controller_index_t.
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+ * @param[in] enable
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+ * 1U - enable;
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+ * 0U - disable;
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+ */
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+void USB_EhcihostPhyDisconnectDetectCmd(uint8_t controllerId, uint8_t enable)
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+{
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+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
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+ USBPHY_Type *usbPhyBase;
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+
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+ usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
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+ if (NULL == usbPhyBase) {
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+ return;
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+ }
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+
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+ if (0U != enable) {
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+ usbPhyBase->CTRL |= USBPHY_CTRL_ENHOSTDISCONDETECT_MASK;
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+ } else {
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+ usbPhyBase->CTRL &= (~USBPHY_CTRL_ENHOSTDISCONDETECT_MASK);
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+ }
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+#endif
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+}
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+
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+#if ((defined FSL_FEATURE_SOC_USBPHY_COUNT) && (FSL_FEATURE_SOC_USBPHY_COUNT > 0U))
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+#if ((defined FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE) && (FSL_FEATURE_USBHSD_HAS_EXIT_HS_ISSUE > 0U))
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+void USB_PhyDeviceForceEnterFSMode(uint8_t controllerId, uint8_t enable)
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+{
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+ USBPHY_Type *usbPhyBase;
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+
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+ usbPhyBase = (USBPHY_Type *)USB_EhciPhyGetBase(controllerId);
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+ if (NULL == usbPhyBase) {
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+ return;
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+ }
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+
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+ if (0U != enable) {
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+ uint32_t delay = 1000000;
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+ usbPhyBase->DEBUG0_CLR = USBPHY_DEBUG0_CLKGATE_MASK;
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+ while ((0U != (usbPhyBase->USB1_VBUS_DET_STAT & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)) && (0U != delay)) {
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+ delay--;
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+ }
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+ usbPhyBase->USB1_LOOPBACK_SET = USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK;
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+ } else {
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+ usbPhyBase->DEBUG0_CLR = USBPHY_DEBUG0_CLKGATE_MASK;
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+ usbPhyBase->USB1_LOOPBACK_CLR = USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK;
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+ }
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+}
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+#endif
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+#endif
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+
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+void USB_ClockInit(void)
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+{
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+ usb_phy_config_struct_t phyConfig = {
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+ BOARD_USB_PHY_D_CAL,
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+ BOARD_USB_PHY_TXCAL45DP,
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+ BOARD_USB_PHY_TXCAL45DM,
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+ };
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+
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+ SPC0->ACTIVE_VDELAY = 0x0500;
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+ /* Change the power DCDC to 1.8v (By deafult, DCDC is 1.8V), CORELDO to 1.1v (By deafult, CORELDO is 1.0V) */
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+ SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK;
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+ SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) |
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+ SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u);
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|
+ /* Wait until it is done */
|
|
|
+ while (SPC0->SC & SPC_SC_BUSY_MASK)
|
|
|
+ ;
|
|
|
+ if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) {
|
|
|
+ SCG0->TRIM_LOCK = 0x5a5a0001U;
|
|
|
+ SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
|
|
|
+ /* wait LDO ready */
|
|
|
+ while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK))
|
|
|
+ ;
|
|
|
+ }
|
|
|
+ SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK | SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
|
|
|
+ SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
|
|
|
+ /* xtal = 20 ~ 30MHz */
|
|
|
+ SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
|
|
|
+ SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
|
|
|
+ while (1) {
|
|
|
+ if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) {
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK | SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
|
|
|
+ CLOCK_EnableClock(kCLOCK_UsbHs);
|
|
|
+ CLOCK_EnableClock(kCLOCK_UsbHsPhy);
|
|
|
+ CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, 24000000U);
|
|
|
+ CLOCK_EnableUsbhsClock();
|
|
|
+ USB_EhciPhyInit(kUSB_ControllerEhci0, BOARD_XTAL0_CLK_HZ, &phyConfig);
|
|
|
+}
|
|
|
+
|
|
|
+void (*g_usb_nxp_irq)(uint8_t busid);
|
|
|
+
|
|
|
+void usb_dc_low_level_init(uint8_t busid)
|
|
|
+{
|
|
|
+ USB_ClockInit();
|
|
|
+
|
|
|
+ g_usb_nxp_irq = USBD_IRQHandler;
|
|
|
+
|
|
|
+ /* Install isr, set priority, and enable IRQ. */
|
|
|
+ NVIC_SetPriority((IRQn_Type)USB1_HS_IRQn, 3);
|
|
|
+ EnableIRQ((IRQn_Type)USB1_HS_IRQn);
|
|
|
+}
|
|
|
+
|
|
|
+void usb_dc_low_level_deinit(uint8_t busid)
|
|
|
+{
|
|
|
+ DisableIRQ((IRQn_Type)USB1_HS_IRQn);
|
|
|
+}
|
|
|
+
|
|
|
+static void usb_host_mode_init(CHIPIDEA_TypeDef *ptr)
|
|
|
+{
|
|
|
+ /* Set mode to host, must be set immediately after reset */
|
|
|
+ ptr->USBMODE &= ~USB_USBMODE_CM_MASK;
|
|
|
+ ptr->USBMODE |= USB_USBMODE_CM_SET(3);
|
|
|
+
|
|
|
+ /* Set the endian */
|
|
|
+ ptr->USBMODE &= ~USB_USBMODE_ES_MASK;
|
|
|
+
|
|
|
+ /* Set parallel interface signal */
|
|
|
+ ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK;
|
|
|
+
|
|
|
+ /* Set parallel transceiver width */
|
|
|
+ ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK;
|
|
|
+
|
|
|
+ /* Not use interrupt threshold. */
|
|
|
+ ptr->USBCMD &= ~USB_USBCMD_ITC_MASK;
|
|
|
+}
|
|
|
+
|
|
|
+void usb_hc_low_level_init(struct usbh_bus *bus)
|
|
|
+{
|
|
|
+ USB_ClockInit();
|
|
|
+
|
|
|
+ g_usb_nxp_irq = USBH_IRQHandler;
|
|
|
+
|
|
|
+ /* Install isr, set priority, and enable IRQ. */
|
|
|
+ NVIC_SetPriority((IRQn_Type)USB1_HS_IRQn, 3);
|
|
|
+ EnableIRQ((IRQn_Type)USB1_HS_IRQn);
|
|
|
+}
|
|
|
+
|
|
|
+void usb_hc_low_level2_init(struct usbh_bus *bus)
|
|
|
+{
|
|
|
+ usb_host_mode_init((CHIPIDEA_TypeDef *)(bus->hcd.reg_base));
|
|
|
+}
|
|
|
+
|
|
|
+void usb_hc_low_level_deinit(struct usbh_bus *bus)
|
|
|
+{
|
|
|
+ DisableIRQ((IRQn_Type)USB1_HS_IRQn);
|
|
|
+}
|
|
|
+
|
|
|
+uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port)
|
|
|
+{
|
|
|
+ (void)port;
|
|
|
+ uint8_t speed;
|
|
|
+
|
|
|
+ CHIPIDEA_TypeDef *ptr = (CHIPIDEA_TypeDef *)bus->hcd.reg_base;
|
|
|
+
|
|
|
+ speed = USB_PORTSC1_PSPD_GET(ptr->PORTSC1);
|
|
|
+
|
|
|
+ if (speed == 0x00) {
|
|
|
+ return USB_SPEED_FULL;
|
|
|
+ }
|
|
|
+ if (speed == 0x01) {
|
|
|
+ return USB_SPEED_LOW;
|
|
|
+ }
|
|
|
+ if (speed == 0x02) {
|
|
|
+ USB_EhcihostPhyDisconnectDetectCmd(kUSB_ControllerEhci0, 1);
|
|
|
+ return USB_SPEED_HIGH;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+void USB1_HS_IRQHandler(void)
|
|
|
+{
|
|
|
+ g_usb_nxp_irq(0);
|
|
|
+}
|
sakumisu