usb_dc_fsdev.c 18 KB

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  1. /*
  2. * Copyright (c) 2022, sakumisu
  3. *
  4. * SPDX-License-Identifier: Apache-2.0
  5. */
  6. #include "usbd_core.h"
  7. #ifndef CONFIG_USBDEV_FSDEV_PMA_ACCESS
  8. #error "please define CONFIG_USBDEV_FSDEV_PMA_ACCESS in usb_config.h"
  9. #endif
  10. #define PMA_ACCESS CONFIG_USBDEV_FSDEV_PMA_ACCESS
  11. #include "usb_fsdev_reg.h"
  12. #ifndef CONFIG_USB_FSDEV_RAM_SIZE
  13. #define CONFIG_USB_FSDEV_RAM_SIZE 512
  14. #endif
  15. #ifndef CONFIG_USBDEV_EP_NUM
  16. #define CONFIG_USBDEV_EP_NUM 8
  17. #endif
  18. #define USB ((USB_TypeDef *)g_usbdev_bus[0].reg_base)
  19. #define USB_BTABLE_SIZE (8 * CONFIG_USBDEV_EP_NUM)
  20. static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
  21. static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
  22. /* Endpoint state */
  23. struct fsdev_ep_state {
  24. uint16_t ep_mps; /* Endpoint max packet size */
  25. uint8_t ep_type; /* Endpoint type */
  26. uint8_t ep_stalled; /* Endpoint stall flag */
  27. uint8_t ep_enable; /* Endpoint enable */
  28. uint16_t ep_pma_buf_len; /* Previously allocated buffer size */
  29. uint16_t ep_pma_addr; /* ep pmd allocated addr */
  30. uint8_t *xfer_buf;
  31. uint32_t xfer_len;
  32. uint32_t actual_xfer_len;
  33. };
  34. /* Driver state */
  35. struct fsdev_udc {
  36. struct usb_setup_packet setup;
  37. volatile uint8_t dev_addr; /*!< USB Address */
  38. volatile uint32_t pma_offset; /*!< pma offset */
  39. struct fsdev_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/
  40. struct fsdev_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */
  41. } g_fsdev_udc;
  42. __WEAK void usb_dc_low_level_init(void)
  43. {
  44. }
  45. __WEAK void usb_dc_low_level_deinit(void)
  46. {
  47. }
  48. int usb_dc_init(uint8_t busid)
  49. {
  50. usb_dc_low_level_init();
  51. /* Init Device */
  52. /* CNTR_FRES = 1 */
  53. USB->CNTR = (uint16_t)USB_CNTR_FRES;
  54. /* CNTR_FRES = 0 */
  55. USB->CNTR = 0U;
  56. /* Clear pending interrupts */
  57. USB->ISTR = 0U;
  58. /*Set Btable Address*/
  59. USB->BTABLE = BTABLE_ADDRESS;
  60. uint32_t winterruptmask;
  61. /* Set winterruptmask variable */
  62. winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM |
  63. USB_CNTR_SUSPM | USB_CNTR_ERRM |
  64. USB_CNTR_ESOFM | USB_CNTR_RESETM;
  65. #ifdef CONFIG_USBDEV_SOF_ENABLE
  66. winterruptmask |= USB_CNTR_SOFM;
  67. #endif
  68. /* Set interrupt mask */
  69. USB->CNTR = (uint16_t)winterruptmask;
  70. /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */
  71. USB->BCDR |= (uint16_t)USB_BCDR_DPPU;
  72. return 0;
  73. }
  74. int usb_dc_deinit(uint8_t busid)
  75. {
  76. /* disable all interrupts and force USB reset */
  77. USB->CNTR = (uint16_t)USB_CNTR_FRES;
  78. /* clear interrupt status register */
  79. USB->ISTR = 0U;
  80. /* switch-off device */
  81. USB->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN);
  82. usb_dc_low_level_deinit();
  83. return 0;
  84. }
  85. int usbd_set_address(uint8_t busid, const uint8_t addr)
  86. {
  87. if (addr == 0U) {
  88. /* set device address and enable function */
  89. USB->DADDR = (uint16_t)USB_DADDR_EF;
  90. }
  91. g_fsdev_udc.dev_addr = addr;
  92. return 0;
  93. }
  94. int usbd_set_remote_wakeup(uint8_t busid)
  95. {
  96. return -1;
  97. }
  98. uint8_t usbd_get_port_speed(uint8_t busid)
  99. {
  100. return USB_SPEED_FULL;
  101. }
  102. int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep)
  103. {
  104. uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress);
  105. USB_ASSERT_MSG(ep_idx < CONFIG_USBDEV_EP_NUM, "Ep addr %02x overflow", ep->bEndpointAddress);
  106. USB_ASSERT_MSG(USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS, "iso endpoint not support in fsdev");
  107. uint16_t wEpRegVal;
  108. /* initialize Endpoint */
  109. switch (USB_GET_ENDPOINT_TYPE(ep->bmAttributes)) {
  110. case USB_ENDPOINT_TYPE_CONTROL:
  111. wEpRegVal = USB_EP_CONTROL;
  112. break;
  113. case USB_ENDPOINT_TYPE_BULK:
  114. wEpRegVal = USB_EP_BULK;
  115. break;
  116. case USB_ENDPOINT_TYPE_INTERRUPT:
  117. wEpRegVal = USB_EP_INTERRUPT;
  118. break;
  119. case USB_ENDPOINT_TYPE_ISOCHRONOUS:
  120. wEpRegVal = USB_EP_ISOCHRONOUS;
  121. break;
  122. default:
  123. return -1;
  124. }
  125. PCD_SET_EPTYPE(USB, ep_idx, wEpRegVal);
  126. PCD_SET_EP_ADDRESS(USB, ep_idx, ep_idx);
  127. if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) {
  128. g_fsdev_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  129. g_fsdev_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
  130. g_fsdev_udc.out_ep[ep_idx].ep_enable = true;
  131. if (g_fsdev_udc.out_ep[ep_idx].ep_mps > g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len) {
  132. USB_ASSERT_MSG((g_fsdev_udc.pma_offset + g_fsdev_udc.out_ep[ep_idx].ep_mps) <= CONFIG_USB_FSDEV_RAM_SIZE,
  133. "Ep pma %02x overflow", ep->bEndpointAddress);
  134. g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  135. g_fsdev_udc.out_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset;
  136. /*Set the endpoint Receive buffer address */
  137. PCD_SET_EP_RX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset);
  138. g_fsdev_udc.pma_offset += USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  139. }
  140. /*Set the endpoint Receive buffer counter*/
  141. PCD_SET_EP_RX_CNT(USB, ep_idx, USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize));
  142. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  143. } else {
  144. g_fsdev_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  145. g_fsdev_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes);
  146. g_fsdev_udc.in_ep[ep_idx].ep_enable = true;
  147. if (g_fsdev_udc.in_ep[ep_idx].ep_mps > g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len) {
  148. USB_ASSERT_MSG((g_fsdev_udc.pma_offset + g_fsdev_udc.in_ep[ep_idx].ep_mps) <= CONFIG_USB_FSDEV_RAM_SIZE,
  149. "Ep pma %02x overflow", ep->bEndpointAddress);
  150. g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  151. g_fsdev_udc.in_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset;
  152. /*Set the endpoint Transmit buffer address */
  153. PCD_SET_EP_TX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset);
  154. g_fsdev_udc.pma_offset += USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize);
  155. }
  156. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  157. if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
  158. /* Configure NAK status for the Endpoint */
  159. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK);
  160. } else {
  161. /* Configure TX Endpoint to disabled state */
  162. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS);
  163. }
  164. }
  165. return 0;
  166. }
  167. int usbd_ep_close(uint8_t busid, const uint8_t ep)
  168. {
  169. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  170. if (USB_EP_DIR_IS_OUT(ep)) {
  171. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  172. /* Configure DISABLE status for the Endpoint*/
  173. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_DIS);
  174. } else {
  175. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  176. /* Configure DISABLE status for the Endpoint*/
  177. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS);
  178. }
  179. return 0;
  180. }
  181. int usbd_ep_set_stall(uint8_t busid, const uint8_t ep)
  182. {
  183. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  184. if (USB_EP_DIR_IS_OUT(ep)) {
  185. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_STALL);
  186. } else {
  187. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_STALL);
  188. }
  189. return 0;
  190. }
  191. int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep)
  192. {
  193. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  194. if (USB_EP_DIR_IS_OUT(ep)) {
  195. PCD_CLEAR_RX_DTOG(USB, ep_idx);
  196. /* Configure VALID status for the Endpoint */
  197. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  198. } else {
  199. PCD_CLEAR_TX_DTOG(USB, ep_idx);
  200. if (g_fsdev_udc.in_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) {
  201. /* Configure NAK status for the Endpoint */
  202. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK);
  203. }
  204. }
  205. return 0;
  206. }
  207. int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled)
  208. {
  209. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  210. if (USB_EP_DIR_IS_OUT(ep)) {
  211. if (PCD_GET_EP_RX_STATUS(USB, ep_idx) & USB_EP_RX_STALL) {
  212. *stalled = 1;
  213. } else {
  214. *stalled = 0;
  215. }
  216. } else {
  217. if (PCD_GET_EP_TX_STATUS(USB, ep_idx) & USB_EP_TX_STALL) {
  218. *stalled = 1;
  219. } else {
  220. *stalled = 0;
  221. }
  222. }
  223. return 0;
  224. }
  225. int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len)
  226. {
  227. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  228. if (!data && data_len) {
  229. return -1;
  230. }
  231. if (!g_fsdev_udc.in_ep[ep_idx].ep_enable) {
  232. return -2;
  233. }
  234. g_fsdev_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data;
  235. g_fsdev_udc.in_ep[ep_idx].xfer_len = data_len;
  236. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len = 0;
  237. data_len = MIN(data_len, g_fsdev_udc.in_ep[ep_idx].ep_mps);
  238. fsdev_write_pma(USB, (uint8_t *)data, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)data_len);
  239. PCD_SET_EP_TX_CNT(USB, ep_idx, (uint16_t)data_len);
  240. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID);
  241. return 0;
  242. }
  243. int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len)
  244. {
  245. uint8_t ep_idx = USB_EP_GET_IDX(ep);
  246. if (!data && data_len) {
  247. return -1;
  248. }
  249. if (!g_fsdev_udc.out_ep[ep_idx].ep_enable) {
  250. return -2;
  251. }
  252. g_fsdev_udc.out_ep[ep_idx].xfer_buf = data;
  253. g_fsdev_udc.out_ep[ep_idx].xfer_len = data_len;
  254. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len = 0;
  255. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  256. return 0;
  257. }
  258. void USBD_IRQHandler(uint8_t busid)
  259. {
  260. uint16_t wIstr, wEPVal;
  261. uint8_t ep_idx;
  262. uint8_t read_count;
  263. uint16_t write_count;
  264. uint16_t store_ep[8];
  265. wIstr = USB->ISTR;
  266. if (wIstr & USB_ISTR_CTR) {
  267. while ((USB->ISTR & USB_ISTR_CTR) != 0U) {
  268. wIstr = USB->ISTR;
  269. /* extract highest priority endpoint number */
  270. ep_idx = (uint8_t)(wIstr & USB_ISTR_EP_ID);
  271. if (ep_idx == 0U) {
  272. if ((wIstr & USB_ISTR_DIR) == 0U) {
  273. PCD_CLEAR_TX_EP_CTR(USB, ep_idx);
  274. write_count = PCD_GET_EP_TX_CNT(USB, ep_idx);
  275. g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count;
  276. g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count;
  277. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count;
  278. usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len);
  279. if (g_fsdev_udc.setup.wLength == 0) {
  280. /* In status, start reading setup */
  281. usbd_ep_start_read(0, 0x00, NULL, 0);
  282. } else if (g_fsdev_udc.setup.wLength && ((g_fsdev_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) {
  283. /* In status, start reading setup */
  284. usbd_ep_start_read(0, 0x00, NULL, 0);
  285. }
  286. if ((g_fsdev_udc.dev_addr > 0U) && (write_count == 0U)) {
  287. USB->DADDR = ((uint16_t)g_fsdev_udc.dev_addr | USB_DADDR_EF);
  288. g_fsdev_udc.dev_addr = 0U;
  289. }
  290. } else {
  291. wEPVal = PCD_GET_ENDPOINT(USB, ep_idx);
  292. if ((wEPVal & USB_EP_SETUP) != 0U) {
  293. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  294. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  295. fsdev_read_pma(USB, (uint8_t *)&g_fsdev_udc.setup, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  296. usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_fsdev_udc.setup);
  297. } else if ((wEPVal & USB_EP_CTR_RX) != 0U) {
  298. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  299. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  300. fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  301. g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count;
  302. g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count;
  303. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count;
  304. usbd_event_ep_out_complete_handler(0, ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len);
  305. if (read_count == 0) {
  306. /* Out status, start reading setup */
  307. usbd_ep_start_read(0, 0x00, NULL, 0);
  308. }
  309. }
  310. }
  311. } else {
  312. wEPVal = PCD_GET_ENDPOINT(USB, ep_idx);
  313. if ((wEPVal & USB_EP_CTR_RX) != 0U) {
  314. PCD_CLEAR_RX_EP_CTR(USB, ep_idx);
  315. read_count = PCD_GET_EP_RX_CNT(USB, ep_idx);
  316. fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count);
  317. g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count;
  318. g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count;
  319. g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count;
  320. if ((read_count < g_fsdev_udc.out_ep[ep_idx].ep_mps) ||
  321. (g_fsdev_udc.out_ep[ep_idx].xfer_len == 0)) {
  322. usbd_event_ep_out_complete_handler(0, ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len);
  323. } else {
  324. PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID);
  325. }
  326. }
  327. if ((wEPVal & USB_EP_CTR_TX) != 0U) {
  328. PCD_CLEAR_TX_EP_CTR(USB, ep_idx);
  329. write_count = PCD_GET_EP_TX_CNT(USB, ep_idx);
  330. g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count;
  331. g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count;
  332. g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count;
  333. if (g_fsdev_udc.in_ep[ep_idx].xfer_len == 0) {
  334. usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len);
  335. } else {
  336. write_count = MIN(g_fsdev_udc.in_ep[ep_idx].xfer_len, g_fsdev_udc.in_ep[ep_idx].ep_mps);
  337. fsdev_write_pma(USB, g_fsdev_udc.in_ep[ep_idx].xfer_buf, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)write_count);
  338. PCD_SET_EP_TX_CNT(USB, ep_idx, write_count);
  339. PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID);
  340. }
  341. }
  342. }
  343. }
  344. }
  345. if (wIstr & USB_ISTR_RESET) {
  346. memset(&g_fsdev_udc, 0, sizeof(struct fsdev_udc));
  347. g_fsdev_udc.pma_offset = USB_BTABLE_SIZE;
  348. usbd_event_reset_handler(0);
  349. /* start reading setup packet */
  350. PCD_SET_EP_RX_STATUS(USB, 0, USB_EP_RX_VALID);
  351. USB->ISTR &= (uint16_t)(~USB_ISTR_RESET);
  352. }
  353. if (wIstr & USB_ISTR_PMAOVR) {
  354. USB->ISTR &= (uint16_t)(~USB_ISTR_PMAOVR);
  355. }
  356. if (wIstr & USB_ISTR_ERR) {
  357. USB->ISTR &= (uint16_t)(~USB_ISTR_ERR);
  358. }
  359. if (wIstr & USB_ISTR_WKUP) {
  360. USB->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE);
  361. USB->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP);
  362. USB->ISTR &= (uint16_t)(~USB_ISTR_WKUP);
  363. }
  364. if (wIstr & USB_ISTR_SUSP) {
  365. /* WA: To Clear Wakeup flag if raised with suspend signal */
  366. /* Store Endpoint register */
  367. for (uint8_t i = 0U; i < 8U; i++) {
  368. store_ep[i] = PCD_GET_ENDPOINT(USB, i);
  369. }
  370. /* FORCE RESET */
  371. USB->CNTR |= (uint16_t)(USB_CNTR_FRES);
  372. /* CLEAR RESET */
  373. USB->CNTR &= (uint16_t)(~USB_CNTR_FRES);
  374. /* wait for reset flag in ISTR */
  375. while ((USB->ISTR & USB_ISTR_RESET) == 0U) {
  376. }
  377. /* Clear Reset Flag */
  378. USB->ISTR &= (uint16_t)(~USB_ISTR_RESET);
  379. /* Restore Registre */
  380. for (uint8_t i = 0U; i < 8U; i++) {
  381. PCD_SET_ENDPOINT(USB, i, store_ep[i]);
  382. }
  383. /* Force low-power mode in the macrocell */
  384. USB->CNTR |= (uint16_t)USB_CNTR_FSUSP;
  385. /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
  386. USB->ISTR &= (uint16_t)(~USB_ISTR_SUSP);
  387. USB->CNTR |= (uint16_t)USB_CNTR_LP_MODE;
  388. }
  389. #ifdef CONFIG_USBDEV_SOF_ENABLE
  390. if (wIstr & USB_ISTR_SOF) {
  391. USB->ISTR &= (uint16_t)(~USB_ISTR_SOF);
  392. usbd_event_sof_handler(0);
  393. }
  394. #endif
  395. if (wIstr & USB_ISTR_ESOF) {
  396. USB->ISTR &= (uint16_t)(~USB_ISTR_ESOF);
  397. }
  398. }
  399. static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
  400. {
  401. uint32_t n = ((uint32_t)wNBytes + 1U) >> 1;
  402. uint32_t BaseAddr = (uint32_t)USBx;
  403. uint32_t i, temp1, temp2;
  404. __IO uint16_t *pdwVal;
  405. uint8_t *pBuf = pbUsrBuf;
  406. pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
  407. for (i = n; i != 0U; i--) {
  408. temp1 = *pBuf;
  409. pBuf++;
  410. temp2 = temp1 | ((uint16_t)((uint16_t)*pBuf << 8));
  411. *pdwVal = (uint16_t)temp2;
  412. pdwVal++;
  413. #if PMA_ACCESS > 1U
  414. pdwVal++;
  415. #endif
  416. pBuf++;
  417. }
  418. }
  419. /**
  420. * @brief Copy data from packet memory area (PMA) to user memory buffer
  421. * @param USBx USB peripheral instance register address.
  422. * @param pbUsrBuf pointer to user memory area.
  423. * @param wPMABufAddr address into PMA.
  424. * @param wNBytes no. of bytes to be copied.
  425. * @retval None
  426. */
  427. static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
  428. {
  429. uint32_t n = (uint32_t)wNBytes >> 1;
  430. uint32_t BaseAddr = (uint32_t)USBx;
  431. uint32_t i, temp;
  432. __IO uint16_t *pdwVal;
  433. uint8_t *pBuf = pbUsrBuf;
  434. pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS));
  435. for (i = n; i != 0U; i--) {
  436. temp = *(__IO uint16_t *)pdwVal;
  437. pdwVal++;
  438. *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
  439. pBuf++;
  440. *pBuf = (uint8_t)((temp >> 8) & 0xFFU);
  441. pBuf++;
  442. #if PMA_ACCESS > 1U
  443. pdwVal++;
  444. #endif
  445. }
  446. if ((wNBytes % 2U) != 0U) {
  447. temp = *pdwVal;
  448. *pBuf = (uint8_t)((temp >> 0) & 0xFFU);
  449. }
  450. }